# SKX skx_uc_events.v0.50p.txt skx_uc_derived.v0.50p.txt 

# aliases
aliases = {
     "CHAFilter1": "C{i}_MSR_PMON_BOX_FILTER1",
     "M2MAddrMask0": "M2M{i}_PCI_PMON_ADDRMASK0",
     "M2MAddrMask1": "M2M{i}_PCI_PMON_ADDRMASK1",
     "M2MOpcMask": "M2M{i}_PCI_PMON_OPCMASK",
     "M2MAddrMatch0": "M2M{i}_PCI_PMON_ADDRMATCH1",
     "PCUFilter": "PCU_MSR_PMON_BOX_FILTER",
     "UBoxFilter": "U_MSR_PMON_BOX_FILTER",
     "CHAFilter0": "C{i}_MSR_PMON_BOX_FILTER0",
}

events = {
     
# M3UPI:
     "M3UPI.AG0_AD_CRD_ACQUIRED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
     },
     "M3UPI.AG0_AD_CRD_ACQUIRED.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.AG0_AD_CRD_ACQUIRED.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.AG0_AD_CRD_ACQUIRED.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.AG0_AD_CRD_ACQUIRED.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.AG0_AD_CRD_ACQUIRED.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.AG0_AD_CRD_ACQUIRED.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.AG0_AD_CRD_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
     },
     "M3UPI.AG0_AD_CRD_OCCUPANCY.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.AG0_AD_CRD_OCCUPANCY.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.AG0_AD_CRD_OCCUPANCY.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.AG0_AD_CRD_OCCUPANCY.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.AG0_AD_CRD_OCCUPANCY.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.AG0_AD_CRD_OCCUPANCY.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.AG0_BL_CRD_ACQUIRED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
     },
     "M3UPI.AG0_BL_CRD_ACQUIRED.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.AG0_BL_CRD_ACQUIRED.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.AG0_BL_CRD_ACQUIRED.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.AG0_BL_CRD_ACQUIRED.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.AG0_BL_CRD_ACQUIRED.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.AG0_BL_CRD_ACQUIRED.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.AG0_BL_CRD_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
     },
     "M3UPI.AG0_BL_CRD_OCCUPANCY.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.AG0_BL_CRD_OCCUPANCY.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.AG0_BL_CRD_OCCUPANCY.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.AG0_BL_CRD_OCCUPANCY.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.AG0_BL_CRD_OCCUPANCY.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.AG0_BL_CRD_OCCUPANCY.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.AG1_AD_CRD_ACQUIRED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
     },
     "M3UPI.AG1_AD_CRD_ACQUIRED.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.AG1_AD_CRD_ACQUIRED.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.AG1_AD_CRD_ACQUIRED.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.AG1_AD_CRD_ACQUIRED.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.AG1_AD_CRD_ACQUIRED.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.AG1_AD_CRD_ACQUIRED.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.AG1_AD_CRD_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
     },
     "M3UPI.AG1_AD_CRD_OCCUPANCY.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.AG1_AD_CRD_OCCUPANCY.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.AG1_AD_CRD_OCCUPANCY.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.AG1_AD_CRD_OCCUPANCY.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.AG1_AD_CRD_OCCUPANCY.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.AG1_AD_CRD_OCCUPANCY.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.AG1_BL_CRD_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
     },
     "M3UPI.AG1_BL_CRD_OCCUPANCY.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.AG1_BL_CRD_OCCUPANCY.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.AG1_BL_CRD_OCCUPANCY.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.AG1_BL_CRD_OCCUPANCY.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.AG1_BL_CRD_OCCUPANCY.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.AG1_BL_CRD_OCCUPANCY.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.AG1_BL_CREDITS_ACQUIRED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
     },
     "M3UPI.AG1_BL_CREDITS_ACQUIRED.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.AG1_BL_CREDITS_ACQUIRED.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.AG1_BL_CREDITS_ACQUIRED.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.AG1_BL_CREDITS_ACQUIRED.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.AG1_BL_CREDITS_ACQUIRED.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.AG1_BL_CREDITS_ACQUIRED.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.CHA_AD_CREDITS_EMPTY": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
          "Desc": "CBox AD Credits Empty",
          "EvSel": 34,
          "ExtSel": "",
     },
     "M3UPI.CHA_AD_CREDITS_EMPTY.VNA": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
          "Desc": "CBox AD Credits Empty",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.CHA_AD_CREDITS_EMPTY.WB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
          "Desc": "CBox AD Credits Empty",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.CHA_AD_CREDITS_EMPTY.REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
          "Desc": "CBox AD Credits Empty",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.CHA_AD_CREDITS_EMPTY.SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to Cbox on the AD Ring (covers higher CBoxes)",
          "Desc": "CBox AD Credits Empty",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.CLOCKTICKS": {
          "Box": "M3UPI",
          "Category": "M3UPI UCLK Events",
          "Counters": "0-3",
          "Defn": "Counts the number of uclks in the M3 uclk domain.  This could be slightly different than the count in the Ubox because of enable/freeze delays.  However, because the M3 is close to the Ubox, they generally should not diverge by more than a handful of cycles.",
          "Desc": "Number of uclks in domain",
          "EvSel": 1,
          "ExtSel": "",
     },
     "M3UPI.CMS_CLOCKTICKS": {
          "Box": "M3UPI",
          "Category": "M3UPI Misc Events",
          "Desc": "CMS Clockticks",
          "EvSel": 192,
          "ExtSel": "",
     },
     "M3UPI.D2C_SENT": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Count cases BL sends direct to core",
          "Desc": "D2C Sent",
          "EvSel": 43,
          "ExtSel": "",
     },
     "M3UPI.D2U_SENT": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Cases where SMI3 sends D2U command",
          "Desc": "D2U Sent",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "NOT required anymore",
     },
     "M3UPI.EGRESS_ORDERING": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
     },
     "M3UPI.EGRESS_ORDERING.IV_SNOOPGO_DN": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.EGRESS_ORDERING.IV_SNOOPGO_UP": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.FAST_ASSERTED": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
     },
     "M3UPI.FAST_ASSERTED.HORZ": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "M3UPI.FAST_ASSERTED.VERT": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "M3UPI.HORZ_RING_AD_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
     },
     "M3UPI.HORZ_RING_AD_IN_USE.LEFT_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.HORZ_RING_AD_IN_USE.RIGHT_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.HORZ_RING_AD_IN_USE.LEFT_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.HORZ_RING_AD_IN_USE.RIGHT_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.HORZ_RING_AK_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
     },
     "M3UPI.HORZ_RING_AK_IN_USE.RIGHT_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.HORZ_RING_AK_IN_USE.LEFT_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.HORZ_RING_AK_IN_USE.LEFT_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.HORZ_RING_AK_IN_USE.RIGHT_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.HORZ_RING_BL_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
     },
     "M3UPI.HORZ_RING_BL_IN_USE.LEFT_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.HORZ_RING_BL_IN_USE.RIGHT_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.HORZ_RING_BL_IN_USE.LEFT_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.HORZ_RING_BL_IN_USE.RIGHT_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.HORZ_RING_IV_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
     },
     "M3UPI.HORZ_RING_IV_IN_USE.RIGHT": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.HORZ_RING_IV_IN_USE.LEFT": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.M2_BL_CREDITS_EMPTY": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No vn0 and vna credits available to send to M2",
          "Desc": "M2 BL Credits Empty",
          "EvSel": 35,
          "ExtSel": "",
     },
     "M3UPI.M2_BL_CREDITS_EMPTY.NCS_SEL": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No vn0 and vna credits available to send to M2",
          "Desc": "M2 BL Credits Empty",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.M2_BL_CREDITS_EMPTY.IIO5_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No vn0 and vna credits available to send to M2",
          "Desc": "M2 BL Credits Empty",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.M2_BL_CREDITS_EMPTY.IIO2_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No vn0 and vna credits available to send to M2",
          "Desc": "M2 BL Credits Empty",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.M2_BL_CREDITS_EMPTY.IIO0_IIO1_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No vn0 and vna credits available to send to M2",
          "Desc": "M2 BL Credits Empty",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.M2_BL_CREDITS_EMPTY.NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No vn0 and vna credits available to send to M2",
          "Desc": "M2 BL Credits Empty",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.M2_BL_CREDITS_EMPTY.IIO3_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No vn0 and vna credits available to send to M2",
          "Desc": "M2 BL Credits Empty",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.M2_BL_CREDITS_EMPTY.IIO4_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No vn0 and vna credits available to send to M2",
          "Desc": "M2 BL Credits Empty",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.MULTI_SLOT_RCVD": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
          "Desc": "Multi Slot Flit Received",
          "EvSel": 62,
          "ExtSel": "",
     },
     "M3UPI.MULTI_SLOT_RCVD.AD_SLOT0": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
          "Desc": "Multi Slot Flit Received",
          "EvSel": 62,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.MULTI_SLOT_RCVD.AD_SLOT2": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
          "Desc": "Multi Slot Flit Received",
          "EvSel": 62,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.MULTI_SLOT_RCVD.AD_SLOT1": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
          "Desc": "Multi Slot Flit Received",
          "EvSel": 62,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.MULTI_SLOT_RCVD.BL_SLOT0": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
          "Desc": "Multi Slot Flit Received",
          "EvSel": 62,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.MULTI_SLOT_RCVD.AK_SLOT2": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
          "Desc": "Multi Slot Flit Received",
          "EvSel": 62,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.MULTI_SLOT_RCVD.AK_SLOT0": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Multi slot flit received - S0, S1 and/or S2 populated (can use AK S0/S1 masks for AK allocations)",
          "Desc": "Multi Slot Flit Received",
          "EvSel": 62,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RING_BOUNCES_HORZ": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
     },
     "M3UPI.RING_BOUNCES_HORZ.BL": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RING_BOUNCES_HORZ.AD": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RING_BOUNCES_HORZ.AK": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RING_BOUNCES_HORZ.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RING_BOUNCES_VERT": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
     },
     "M3UPI.RING_BOUNCES_VERT.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RING_BOUNCES_VERT.BL": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RING_BOUNCES_VERT.AD": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RING_BOUNCES_VERT.AK": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RING_SINK_STARVED_HORZ": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
     },
     "M3UPI.RING_SINK_STARVED_HORZ.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RING_SINK_STARVED_HORZ.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RING_SINK_STARVED_HORZ.BL": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RING_SINK_STARVED_HORZ.AD": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RING_SINK_STARVED_HORZ.AK": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RING_SINK_STARVED_VERT": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
     },
     "M3UPI.RING_SINK_STARVED_VERT.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RING_SINK_STARVED_VERT.AK": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RING_SINK_STARVED_VERT.BL": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RING_SINK_STARVED_VERT.AD": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RING_SRC_THRTL": {
          "Box": "M3UPI",
          "Category": "M3UPI Horizontal  RING Events",
          "Desc": "Source Throttle",
          "EvSel": 164,
          "ExtSel": "",
     },
     "M3UPI.RxC_ARB_LOST_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message requested but lost arbitration",
          "Desc": "Lost Arb for VN0",
          "EvSel": 75,
          "ExtSel": "",
     },
     "M3UPI.RxC_ARB_LOST_VN0.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message requested but lost arbitration",
          "Desc": "Lost Arb for VN0",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_ARB_LOST_VN0.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message requested but lost arbitration",
          "Desc": "Lost Arb for VN0",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_ARB_LOST_VN0.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message requested but lost arbitration",
          "Desc": "Lost Arb for VN0",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_ARB_LOST_VN0.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message requested but lost arbitration",
          "Desc": "Lost Arb for VN0",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_ARB_LOST_VN0.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message requested but lost arbitration",
          "Desc": "Lost Arb for VN0",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_ARB_LOST_VN0.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message requested but lost arbitration",
          "Desc": "Lost Arb for VN0",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_ARB_LOST_VN0.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message requested but lost arbitration",
          "Desc": "Lost Arb for VN0",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_ARB_LOST_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message requested but lost arbitration",
          "Desc": "Lost Arb for VN1",
          "EvSel": 76,
          "ExtSel": "",
     },
     "M3UPI.RxC_ARB_LOST_VN1.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message requested but lost arbitration",
          "Desc": "Lost Arb for VN1",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_ARB_LOST_VN1.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message requested but lost arbitration",
          "Desc": "Lost Arb for VN1",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_ARB_LOST_VN1.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message requested but lost arbitration",
          "Desc": "Lost Arb for VN1",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_ARB_LOST_VN1.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message requested but lost arbitration",
          "Desc": "Lost Arb for VN1",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_ARB_LOST_VN1.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message requested but lost arbitration",
          "Desc": "Lost Arb for VN1",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_ARB_LOST_VN1.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message requested but lost arbitration",
          "Desc": "Lost Arb for VN1",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_ARB_LOST_VN1.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message requested but lost arbitration",
          "Desc": "Lost Arb for VN1",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_ARB_MISC": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Desc": "Arb Miscellaneous",
          "EvSel": 77,
          "ExtSel": "",
     },
     "M3UPI.RxC_ARB_MISC.NO_PROG_AD_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Desc": "Arb Miscellaneous",
          "EvSel": 77,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_ARB_MISC.NO_PROG_AD_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Desc": "Arb Miscellaneous",
          "EvSel": 77,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_ARB_MISC.NO_PROG_BL_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Desc": "Arb Miscellaneous",
          "EvSel": 77,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_ARB_MISC.NO_PROG_BL_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Desc": "Arb Miscellaneous",
          "EvSel": 77,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_ARB_MISC.PAR_BIAS_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Desc": "Arb Miscellaneous",
          "EvSel": 77,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_ARB_MISC.PAR_BIAS_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Desc": "Arb Miscellaneous",
          "EvSel": 77,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_ARB_MISC.ADBL_PARALLEL_WIN": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Desc": "Arb Miscellaneous",
          "EvSel": 77,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN0",
          "EvSel": 73,
          "ExtSel": "",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN0.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN0",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN0.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN0",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN0.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN0",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN0.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN0",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN0.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN0",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN0.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN0",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN0.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN0",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN1",
          "EvSel": 74,
          "ExtSel": "",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN1.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN1",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN1.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN1",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN1.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN1",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN1.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN1",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN1.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN1",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN1.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN1",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_ARB_NOAD_REQ_VN1.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message was not able to request arbitration while some other message won arbitration",
          "Desc": "Can't Arb for VN1",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN0",
          "EvSel": 71,
          "ExtSel": "",
     },
     "M3UPI.RxC_ARB_NOCRED_VN0.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN0",
          "EvSel": 71,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN0.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN0",
          "EvSel": 71,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN0.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN0",
          "EvSel": 71,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN0.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN0",
          "EvSel": 71,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN0.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN0",
          "EvSel": 71,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_ARB_NOCRED_VN0.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN0",
          "EvSel": 71,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN0.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN0 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN0",
          "EvSel": 71,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_ARB_NOCRED_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN1",
          "EvSel": 72,
          "ExtSel": "",
     },
     "M3UPI.RxC_ARB_NOCRED_VN1.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN1",
          "EvSel": 72,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN1.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN1",
          "EvSel": 72,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN1.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN1",
          "EvSel": 72,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN1.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN1",
          "EvSel": 72,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_ARB_NOCRED_VN1.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN1",
          "EvSel": 72,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_ARB_NOCRED_VN1.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN1",
          "EvSel": 72,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_ARB_NOCRED_VN1.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Arbitration Events",
          "Defn": "VN1 message is blocked from requesting arbitration due to lack of remote UPI credits",
          "Desc": "No Credits to Arb for VN1",
          "EvSel": 72,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_BYPASSED": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Counters": "0-2",
          "Defn": "Number ot times message is bypassed around the Ingress Queue",
          "Desc": "Ingress Queue Bypasses",
          "EvSel": 64,
          "ExtSel": "",
     },
     "M3UPI.RxC_BYPASSED.AD_S1_BL_SLOT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Counters": "0-2",
          "Defn": "Number ot times message is bypassed around the Ingress Queue",
          "Desc": "Ingress Queue Bypasses",
          "EvSel": 64,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_BYPASSED.AD_S2_BL_SLOT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Counters": "0-2",
          "Defn": "Number ot times message is bypassed around the Ingress Queue",
          "Desc": "Ingress Queue Bypasses",
          "EvSel": 64,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_BYPASSED.AD_S0_BL_ARB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Counters": "0-2",
          "Defn": "Number ot times message is bypassed around the Ingress Queue",
          "Desc": "Ingress Queue Bypasses",
          "EvSel": 64,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_BYPASSED.AD_S0_IDLE": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Counters": "0-2",
          "Defn": "Number ot times message is bypassed around the Ingress Queue",
          "Desc": "Ingress Queue Bypasses",
          "EvSel": 64,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_COLLISION_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.",
          "Desc": "VN0 message lost contest for flit",
          "EvSel": 80,
          "ExtSel": "",
     },
     "M3UPI.RxC_COLLISION_VN0.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.",
          "Desc": "VN0 message lost contest for flit",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_COLLISION_VN0.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.",
          "Desc": "VN0 message lost contest for flit",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_COLLISION_VN0.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.",
          "Desc": "VN0 message lost contest for flit",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_COLLISION_VN0.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.",
          "Desc": "VN0 message lost contest for flit",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_COLLISION_VN0.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.",
          "Desc": "VN0 message lost contest for flit",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_COLLISION_VN0.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.",
          "Desc": "VN0 message lost contest for flit",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_COLLISION_VN0.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN0 packets lost the contest for Flit Slot 0.",
          "Desc": "VN0 message lost contest for flit",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_COLLISION_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.",
          "Desc": "VN1 message lost contest for flit",
          "EvSel": 81,
          "ExtSel": "",
     },
     "M3UPI.RxC_COLLISION_VN1.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.",
          "Desc": "VN1 message lost contest for flit",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_COLLISION_VN1.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.",
          "Desc": "VN1 message lost contest for flit",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_COLLISION_VN1.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.",
          "Desc": "VN1 message lost contest for flit",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_COLLISION_VN1.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.",
          "Desc": "VN1 message lost contest for flit",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_COLLISION_VN1.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.",
          "Desc": "VN1 message lost contest for flit",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_COLLISION_VN1.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.",
          "Desc": "VN1 message lost contest for flit",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_COLLISION_VN1.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress VN1 packets lost the contest for Flit Slot 0.",
          "Desc": "VN1 message lost contest for flit",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_CRD_MISC": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Miscellaneous Credit Events",
          "EvSel": 96,
          "ExtSel": "",
     },
     "M3UPI.RxC_CRD_MISC.ANY_BGF_FIFO": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Miscellaneous Credit Events",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_CRD_MISC.NO_D2K_FOR_ARB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Miscellaneous Credit Events",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_CRD_MISC.ANY_BGF_PATH": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Miscellaneous Credit Events",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_CRD_OCC": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Credit Occupancy",
          "EvSel": 97,
          "ExtSel": "",
     },
     "M3UPI.RxC_CRD_OCC.P1P_TOTAL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Credit Occupancy",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_CRD_OCC.TxQ_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Credit Occupancy",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_CRD_OCC.P1P_FIFO": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Credit Occupancy",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_CRD_OCC.VNA_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Credit Occupancy",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_CRD_OCC.D2K_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Credit Occupancy",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_CRD_OCC.FLITS_IN_FIFO": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Credit Occupancy",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_CRD_OCC.FLITS_IN_PATH": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Credit Occupancy",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_CYCLES_NE_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 67,
          "ExtSel": "",
     },
     "M3UPI.RxC_CYCLES_NE_VN0.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 67,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_CYCLES_NE_VN0.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 67,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_CYCLES_NE_VN0.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 67,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_CYCLES_NE_VN0.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 67,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_CYCLES_NE_VN0.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 67,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_CYCLES_NE_VN0.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 67,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_CYCLES_NE_VN0.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of cycles when the UPI Ingress is not empty.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue occupancy.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 67,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_CYCLES_NE_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 68,
          "ExtSel": "",
     },
     "M3UPI.RxC_CYCLES_NE_VN1.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 68,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_CYCLES_NE_VN1.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 68,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_CYCLES_NE_VN1.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 68,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_CYCLES_NE_VN1.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 68,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_CYCLES_NE_VN1.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 68,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_CYCLES_NE_VN1.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 68,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_CYCLES_NE_VN1.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Cycles Not Empty",
          "EvSel": 68,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_FLITS_DATA_NOT_SENT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Data flit is ready for transmission but could not be sent",
          "Desc": "Data Flit Not Sent",
          "EvSel": 87,
          "ExtSel": "",
     },
     "M3UPI.RxC_FLITS_DATA_NOT_SENT.NO_BGF": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Data flit is ready for transmission but could not be sent",
          "Desc": "Data Flit Not Sent",
          "EvSel": 87,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_FLITS_DATA_NOT_SENT.NO_TXQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Data flit is ready for transmission but could not be sent",
          "Desc": "Data Flit Not Sent",
          "EvSel": 87,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_FLITS_DATA_NOT_SENT.ALL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Data flit is ready for transmission but could not be sent",
          "Desc": "Data Flit Not Sent",
          "EvSel": 87,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_FLITS_GEN_BL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Generating BL Data Flit Sequence",
          "EvSel": 89,
          "ExtSel": "",
     },
     "M3UPI.RxC_FLITS_GEN_BL.P1P_BUSY": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Generating BL Data Flit Sequence",
          "EvSel": 89,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_FLITS_GEN_BL.P1_WAIT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Generating BL Data Flit Sequence",
          "EvSel": 89,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_FLITS_GEN_BL.P1P_HOLD_P0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Generating BL Data Flit Sequence",
          "EvSel": 89,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_FLITS_GEN_BL.P0_WAIT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Generating BL Data Flit Sequence",
          "EvSel": 89,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_FLITS_GEN_BL.P1P_AT_LIMIT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Generating BL Data Flit Sequence",
          "EvSel": 89,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_FLITS_GEN_BL.P1P_FIFO_FULL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Generating BL Data Flit Sequence",
          "EvSel": 89,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_FLITS_GEN_BL.P1P_TO_LIMBO": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Generating BL Data Flit Sequence",
          "EvSel": 89,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_FLITS_MISC": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "EvSel": 90,
          "ExtSel": "",
     },
     "M3UPI.RxC_FLITS_SENT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Sent Header Flit",
          "EvSel": 86,
          "ExtSel": "",
     },
     "M3UPI.RxC_FLITS_SENT.3_MSGS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Sent Header Flit",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_FLITS_SENT.2_MSGS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Sent Header Flit",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_FLITS_SENT.1_MSG": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Sent Header Flit",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_FLITS_SENT.SLOTS_2": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Sent Header Flit",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_FLITS_SENT.1_MSG_VNX": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Sent Header Flit",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_FLITS_SENT.SLOTS_1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Sent Header Flit",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_FLITS_SENT.SLOTS_3": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Sent Header Flit",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_FLITS_SLOT_BL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Slotting BL Message Into Header Flit",
          "EvSel": 88,
          "ExtSel": "",
     },
     "M3UPI.RxC_FLITS_SLOT_BL.P0_WAIT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Slotting BL Message Into Header Flit",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_FLITS_SLOT_BL.P1_NOT_REQ_NOT_AVAIL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Slotting BL Message Into Header Flit",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_FLITS_SLOT_BL.P1_NOT_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Slotting BL Message Into Header Flit",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_FLITS_SLOT_BL.P1_NOT_REQ_BUT_BUBBLE": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Slotting BL Message Into Header Flit",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_FLITS_SLOT_BL.P1_WAIT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Slotting BL Message Into Header Flit",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_FLITS_SLOT_BL.ALL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Slotting BL Message Into Header Flit",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_FLITS_SLOT_BL.NEED_DATA": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Desc": "Slotting BL Message Into Header Flit",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1.AHEAD_BLOCKED": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1.PAR_MSG": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1.PAR_FLIT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1.AHEAD_MSG": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1.PAR": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1.ACCUM_WASTED": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1.ACCUM_READ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_FLIT_GEN_HDR1.ACCUM": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 1",
          "Desc": "Flit Gen - Header 1",
          "EvSel": 83,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_FLIT_GEN_HDR2": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 2",
          "Desc": "Flit Gen - Header 2",
          "EvSel": 84,
          "ExtSel": "",
     },
     "M3UPI.RxC_FLIT_GEN_HDR2.RMSTALL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 2",
          "Desc": "Flit Gen - Header 2",
          "EvSel": 84,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_FLIT_GEN_HDR2.RMSTALL_NOMSG": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "Events related to Header Flit Generation - Set 2",
          "Desc": "Flit Gen - Header 2",
          "EvSel": 84,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_FLIT_NOT_SENT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
     },
     "M3UPI.RxC_FLIT_NOT_SENT.NO_TXQ_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_FLIT_NOT_SENT.THREE_TAKEN": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.RxC_FLIT_NOT_SENT.TWO_TAKEN": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_FLIT_NOT_SENT.ONE_TAKEN": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_FLIT_NOT_SENT.ALL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_FLIT_NOT_SENT.NO_TXQ_NO_MSG": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_FLIT_NOT_SENT.NO_BGF_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_FLIT_NOT_SENT.NO_BGF_NO_MSG": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Flit Events",
          "Defn": "header flit is ready for transmission but could not be sent",
          "Desc": "Header Not Sent",
          "EvSel": 85,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_HELD": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
     },
     "M3UPI.RxC_HELD.VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_HELD.CANT_SLOT_BL": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.RxC_HELD.PARALLEL_AD_LOST": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_HELD.PARALLEL_ATTEMPT": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_HELD.CANT_SLOT_AD": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_HELD.PARALLEL_SUCCESS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_HELD.PARALLEL_BL_LOST": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_HELD.VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Desc": "Message Held",
          "EvSel": 82,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_INSERTS_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Inserts",
          "EvSel": 65,
          "ExtSel": "",
     },
     "M3UPI.RxC_INSERTS_VN0.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Inserts",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_INSERTS_VN0.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Inserts",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_INSERTS_VN0.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Inserts",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_INSERTS_VN0.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Inserts",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_INSERTS_VN0.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Inserts",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_INSERTS_VN0.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Inserts",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_INSERTS_VN0.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN0 Ingress (from CMS) Queue - Inserts",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_INSERTS_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Inserts",
          "EvSel": 66,
          "ExtSel": "",
     },
     "M3UPI.RxC_INSERTS_VN1.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Inserts",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_INSERTS_VN1.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Inserts",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_INSERTS_VN1.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Inserts",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_INSERTS_VN1.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Inserts",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_INSERTS_VN1.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Inserts",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_INSERTS_VN1.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Inserts",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_INSERTS_VN1.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Counts the number of allocations into the UPI VN1  Ingress.  This tracks one of the three rings that are used by the UPI agent.  This can be used in conjunction with the UPI VN1  Ingress Occupancy Accumulator event in order to calculate average queue latency.  Multiple ingress buffers can be tracked at a given time using multiple counters.",
          "Desc": "VN1 Ingress (from CMS) Queue - Inserts",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_OCCUPANCY_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN0 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 69,
          "ExtSel": "",
     },
     "M3UPI.RxC_OCCUPANCY_VN0.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN0 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_OCCUPANCY_VN0.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN0 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_OCCUPANCY_VN0.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN0 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_OCCUPANCY_VN0.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN0 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_OCCUPANCY_VN0.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN0 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_OCCUPANCY_VN0.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN0 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_OCCUPANCY_VN0.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN0 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_OCCUPANCY_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN1 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 70,
          "ExtSel": "",
     },
     "M3UPI.RxC_OCCUPANCY_VN1.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN1 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_OCCUPANCY_VN1.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN1 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_OCCUPANCY_VN1.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN1 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_OCCUPANCY_VN1.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN1 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_OCCUPANCY_VN1.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN1 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_OCCUPANCY_VN1.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN1 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_OCCUPANCY_VN1.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Events",
          "Defn": "Accumulates the occupancy of a given UPI VN1  Ingress queue in each cycle.  This tracks one of the three ring Ingress buffers.  This can be used with the UPI VN1  Ingress Not Empty event to calculate average occupancy or the UPI VN1  Ingress Allocations event in order to calculate average queuing latency.",
          "Desc": "VN1 Ingress (from CMS) Queue - Occupancy",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_PACKING_MISS_VN0": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN0 message can't slot into flit",
          "EvSel": 78,
          "ExtSel": "",
     },
     "M3UPI.RxC_PACKING_MISS_VN0.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN0 message can't slot into flit",
          "EvSel": 78,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_PACKING_MISS_VN0.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN0 message can't slot into flit",
          "EvSel": 78,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_PACKING_MISS_VN0.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN0 message can't slot into flit",
          "EvSel": 78,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_PACKING_MISS_VN0.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN0 message can't slot into flit",
          "EvSel": 78,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_PACKING_MISS_VN0.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN0 message can't slot into flit",
          "EvSel": 78,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_PACKING_MISS_VN0.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN0 message can't slot into flit",
          "EvSel": 78,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_PACKING_MISS_VN0.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN0 message can't slot into flit",
          "EvSel": 78,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_PACKING_MISS_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN1 message can't slot into flit",
          "EvSel": 79,
          "ExtSel": "",
     },
     "M3UPI.RxC_PACKING_MISS_VN1.BL_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN1 message can't slot into flit",
          "EvSel": 79,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_PACKING_MISS_VN1.BL_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN1 message can't slot into flit",
          "EvSel": 79,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxC_PACKING_MISS_VN1.BL_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN1 message can't slot into flit",
          "EvSel": 79,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_PACKING_MISS_VN1.AD_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN1 message can't slot into flit",
          "EvSel": 79,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_PACKING_MISS_VN1.AD_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN1 message can't slot into flit",
          "EvSel": 79,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_PACKING_MISS_VN1.AD_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN1 message can't slot into flit",
          "EvSel": 79,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_PACKING_MISS_VN1.BL_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Sloting Events",
          "Counters": "0-2",
          "Defn": "Count cases where Ingress has packets to send but did not have time to pack into flit before sending to Agent so slot was left NULL which could have been used.",
          "Desc": "VN1 message can't slot into flit",
          "EvSel": 79,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_SMI3_PFTCH": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "SMI3 Prefetch Messages",
          "EvSel": 98,
          "ExtSel": "",
     },
     "M3UPI.RxC_SMI3_PFTCH.ARB_LOST": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "SMI3 Prefetch Messages",
          "EvSel": 98,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_SMI3_PFTCH.DROP_OLD": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "SMI3 Prefetch Messages",
          "EvSel": 98,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_SMI3_PFTCH.SLOTTED": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "SMI3 Prefetch Messages",
          "EvSel": 98,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxC_SMI3_PFTCH.DROP_WRAP": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "SMI3 Prefetch Messages",
          "EvSel": 98,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_SMI3_PFTCH.ARRIVED": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "SMI3 Prefetch Messages",
          "EvSel": 98,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_VNA_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Remote VNA Credits",
          "EvSel": 91,
          "ExtSel": "",
     },
     "M3UPI.RxC_VNA_CRD.LT4": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Remote VNA Credits",
          "EvSel": 91,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxC_VNA_CRD.USED": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Remote VNA Credits",
          "EvSel": 91,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxC_VNA_CRD.LT5": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Remote VNA Credits",
          "EvSel": 91,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxC_VNA_CRD.ANY_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Remote VNA Credits",
          "EvSel": 91,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.RxC_VNA_CRD.CORRECTED": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Remote VNA Credits",
          "EvSel": 91,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxC_VNA_CRD.LT1": {
          "Box": "M3UPI",
          "Category": "M3UPI INGRESS Credit Events",
          "Desc": "Remote VNA Credits",
          "EvSel": 91,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxR_BUSY_STARVED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
     },
     "M3UPI.RxR_BUSY_STARVED.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxR_BUSY_STARVED.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxR_BUSY_STARVED.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxR_BUSY_STARVED.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxR_BYPASS": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "M3UPI.RxR_BYPASS.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxR_BYPASS.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxR_BYPASS.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxR_BYPASS.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxR_BYPASS.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxR_BYPASS.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxR_CRD_STARVED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
     },
     "M3UPI.RxR_CRD_STARVED.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxR_CRD_STARVED.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxR_CRD_STARVED.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxR_CRD_STARVED.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxR_CRD_STARVED.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxR_CRD_STARVED.IFV": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.RxR_CRD_STARVED.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxR_INSERTS": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "M3UPI.RxR_INSERTS.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxR_INSERTS.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.RxR_INSERTS.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxR_INSERTS.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxR_INSERTS.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxR_INSERTS.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxR_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "M3UPI.RxR_OCCUPANCY.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.RxR_OCCUPANCY.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.RxR_OCCUPANCY.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.RxR_OCCUPANCY.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.RxR_OCCUPANCY.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.RxR_OCCUPANCY.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_ARB_FAIL": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_ARB_FAIL.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_AD_ARB_FAIL.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_AD_ARB_FAIL.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_ARB_FAIL.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_AD_ARB_FAIL.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_ARB_FAIL.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_ARB_FAIL.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_AD_ARB_FAIL.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for AD",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_AD_FLQ_BYPASS": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
          "Desc": "AD FlowQ Bypass",
          "EvSel": 44,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_FLQ_BYPASS.AD_SLOT2": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
          "Desc": "AD FlowQ Bypass",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_AD_FLQ_BYPASS.AD_SLOT1": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
          "Desc": "AD FlowQ Bypass",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_FLQ_BYPASS.AD_SLOT0": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
          "Desc": "AD FlowQ Bypass",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_FLQ_BYPASS.BL_EARLY_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Counts cases when the AD flowQ is bypassed (S0, S1 and S2 indicate which slot was bypassed with S0 having the highest priority and S2 the least)",
          "Desc": "AD FlowQ Bypass",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_AD_FLQ_CYCLES_NE.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the AD Egress queue is Not Empty",
          "Desc": "AD Flow Q Not Empty",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_AD_FLQ_INSERTS": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "AD Flow Q Inserts",
          "EvSel": 45,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_FLQ_INSERTS.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "AD Flow Q Inserts",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_AD_FLQ_INSERTS.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "AD Flow Q Inserts",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_AD_FLQ_INSERTS.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "AD Flow Q Inserts",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_AD_FLQ_INSERTS.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "AD Flow Q Inserts",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_FLQ_INSERTS.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "AD Flow Q Inserts",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_FLQ_INSERTS.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "AD Flow Q Inserts",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_AD_FLQ_INSERTS.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "AD Flow Q Inserts",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_FLQ_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AD Flow Q Occupancy",
          "EvSel": 28,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_FLQ_OCCUPANCY.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AD Flow Q Occupancy",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_AD_FLQ_OCCUPANCY.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AD Flow Q Occupancy",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_FLQ_OCCUPANCY.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AD Flow Q Occupancy",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_AD_FLQ_OCCUPANCY.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AD Flow Q Occupancy",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_AD_FLQ_OCCUPANCY.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AD Flow Q Occupancy",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_AD_FLQ_OCCUPANCY.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AD Flow Q Occupancy",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_FLQ_OCCUPANCY.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AD Flow Q Occupancy",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI0": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI0": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1.VN1_NON_IDLE": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1.VN0_CHA": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1.VN0_NON_IDLE": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1.VN0_PEER_UPI1": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1.VN1_PEER_UPI1": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_AD_SNPF_GRP1_VN1.VN1_CHA": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Counters": 0,
          "Defn": "Number of snpfanout targets and non-idle cycles can be used to calculate average snpfanout latency",
          "Desc": "Number of Snoop Targets",
          "EvSel": 60,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_AD_SNPF_GRP2_VN1": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "Outcome of SnpF pending arbitration",
          "Desc": "Snoop Arbitration",
          "EvSel": 61,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_VN0SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "Outcome of SnpF pending arbitration",
          "Desc": "Snoop Arbitration",
          "EvSel": 61,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_VN2SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "Outcome of SnpF pending arbitration",
          "Desc": "Snoop Arbitration",
          "EvSel": 61,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_AD_SNPF_GRP2_VN1.VN0_SNPFP_NONSNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "Outcome of SnpF pending arbitration",
          "Desc": "Snoop Arbitration",
          "EvSel": 61,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_SNPF_GRP2_VN1.VN1_SNPFP_NONSNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "Outcome of SnpF pending arbitration",
          "Desc": "Snoop Arbitration",
          "EvSel": 61,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_SPEC_ARB_CRD_AVAIL": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request with prior cycle credit check complete and credit avail",
          "Desc": "Speculative ARB for AD  -  Credit Available",
          "EvSel": 52,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request with prior cycle credit check complete and credit avail",
          "Desc": "Speculative ARB for AD  -  Credit Available",
          "EvSel": 52,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request with prior cycle credit check complete and credit avail",
          "Desc": "Speculative ARB for AD  -  Credit Available",
          "EvSel": 52,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request with prior cycle credit check complete and credit avail",
          "Desc": "Speculative ARB for AD  -  Credit Available",
          "EvSel": 52,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request with prior cycle credit check complete and credit avail",
          "Desc": "Speculative ARB for AD  -  Credit Available",
          "EvSel": 52,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_SPEC_ARB_CRD_AVAIL.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request with prior cycle credit check complete and credit avail",
          "Desc": "Speculative ARB for AD  -  Credit Available",
          "EvSel": 52,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_CRD_AVAIL.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request with prior cycle credit check complete and credit avail",
          "Desc": "Speculative ARB for AD  -  Credit Available",
          "EvSel": 52,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NEW_MSG": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for AD  - New Message",
          "EvSel": 51,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NEW_MSG.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for AD  - New Message",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NEW_MSG.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for AD  - New Message",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NEW_MSG.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for AD  - New Message",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NEW_MSG.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for AD  - New Message",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NEW_MSG.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for AD  - New Message",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NEW_MSG.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for AD  - New Message",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_AD_SPEC_ARB_NO_OTHER_PEND.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "AD speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD  - No Credit",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_AK_FLQ_INSERTS": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Desc": "AK Flow Q Inserts",
          "EvSel": 47,
          "ExtSel": "",
     },
     "M3UPI.TxC_AK_FLQ_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "AK Flow Q Occupancy",
          "EvSel": 30,
          "ExtSel": "",
     },
     "M3UPI.TxC_BL_ARB_FAIL": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
     },
     "M3UPI.TxC_BL_ARB_FAIL.VN0_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_BL_ARB_FAIL.VN0_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_BL_ARB_FAIL.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_BL_ARB_FAIL.VN1_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_BL_ARB_FAIL.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_BL_ARB_FAIL.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_BL_ARB_FAIL.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_BL_ARB_FAIL.VN1_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL arb but no win; arb request asserted but not won",
          "Desc": "Failed ARB for BL",
          "EvSel": 53,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_BL_FLQ_CYCLES_NE.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Number of cycles the BL Egress queue is Not Empty",
          "Desc": "BL Flow Q Not Empty",
          "EvSel": 40,
          "ExtSel": "",
          "Notes": "Counts the number of cycles when the QPI FlowQ is not empty.  This tracks one of the three rings that are used by the QPI agent.  This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue occupancy.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS.VN1_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS.VN1_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS.VN0_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_BL_FLQ_INSERTS.VN0_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the QPI FlowQ. This can be used in conjunction with the QPI FlowQ Occupancy Accumulator event in order to calculate average queue latency.  Only a single FlowQ queue can be tracked at any given time.  It is not possible to filter based on direction or polarity.",
          "Desc": "BL Flow Q Inserts",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY.VN1_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY.VN0_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY.VN0_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_BL_FLQ_OCCUPANCY.VN1_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI FlowQ Events",
          "Counters": 0,
          "Desc": "BL Flow Q Occupancy",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NEW_MSG": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for BL  - New Message",
          "EvSel": 56,
          "ExtSel": "",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for BL  - New Message",
          "EvSel": 56,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NEW_MSG.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for BL  - New Message",
          "EvSel": 56,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NEW_MSG.VN1_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for BL  - New Message",
          "EvSel": 56,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for BL  - New Message",
          "EvSel": 56,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NEW_MSG.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for BL  - New Message",
          "EvSel": 56,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NEW_MSG.VN0_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request due to new message arriving on a specific channel (MC/VN)",
          "Desc": "Speculative ARB for BL  - New Message",
          "EvSel": 56,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN1_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxC_BL_SPEC_ARB_NO_OTHER_PEND.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI ARB Events",
          "Defn": "BL speculative arb request asserted due to no other channel being active (have a valid entry but don't have credits to send)",
          "Desc": "Speculative ARB for AD Failed - No Credit",
          "EvSel": 55,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_ADS_USED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
     },
     "M3UPI.TxR_HORZ_ADS_USED.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_HORZ_ADS_USED.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_HORZ_ADS_USED.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_ADS_USED.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_HORZ_ADS_USED.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_HORZ_BYPASS": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
     },
     "M3UPI.TxR_HORZ_BYPASS.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_HORZ_BYPASS.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_HORZ_BYPASS.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_HORZ_BYPASS.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_HORZ_BYPASS.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_BYPASS.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_HORZ_CYCLES_FULL": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
     },
     "M3UPI.TxR_HORZ_CYCLES_FULL.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_HORZ_CYCLES_FULL.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_HORZ_CYCLES_FULL.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_HORZ_CYCLES_FULL.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_HORZ_CYCLES_FULL.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_CYCLES_FULL.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_HORZ_CYCLES_NE": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
     },
     "M3UPI.TxR_HORZ_CYCLES_NE.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_HORZ_CYCLES_NE.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_CYCLES_NE.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_HORZ_CYCLES_NE.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_HORZ_CYCLES_NE.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_HORZ_CYCLES_NE.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_HORZ_INSERTS": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
     },
     "M3UPI.TxR_HORZ_INSERTS.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_HORZ_INSERTS.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_INSERTS.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_HORZ_INSERTS.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_HORZ_INSERTS.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_HORZ_INSERTS.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_HORZ_NACK": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
     },
     "M3UPI.TxR_HORZ_NACK.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_HORZ_NACK.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_HORZ_NACK.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_NACK.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_HORZ_NACK.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_HORZ_NACK.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_HORZ_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
     },
     "M3UPI.TxR_HORZ_OCCUPANCY.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_HORZ_OCCUPANCY.AD_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_HORZ_OCCUPANCY.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_HORZ_OCCUPANCY.BL_CRD": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_HORZ_OCCUPANCY.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_OCCUPANCY.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_HORZ_STARVED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
     },
     "M3UPI.TxR_HORZ_STARVED.AD_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_HORZ_STARVED.AK_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_HORZ_STARVED.IV_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_HORZ_STARVED.BL_BNC": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_VERT_ADS_USED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
     },
     "M3UPI.TxR_VERT_ADS_USED.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_VERT_ADS_USED.AK_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_VERT_ADS_USED.AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_VERT_ADS_USED.BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_VERT_ADS_USED.AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_VERT_ADS_USED.BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_VERT_BYPASS": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
     },
     "M3UPI.TxR_VERT_BYPASS.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_VERT_BYPASS.AK_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_VERT_BYPASS.AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_VERT_BYPASS.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_VERT_BYPASS.BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_VERT_BYPASS.AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_VERT_BYPASS.BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_VERT_CYCLES_FULL": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
     },
     "M3UPI.TxR_VERT_CYCLES_FULL.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_VERT_CYCLES_FULL.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_VERT_CYCLES_FULL.AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_VERT_CYCLES_FULL.AK_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_VERT_CYCLES_FULL.AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_VERT_CYCLES_FULL.BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_VERT_CYCLES_FULL.BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_VERT_CYCLES_NE": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
     },
     "M3UPI.TxR_VERT_CYCLES_NE.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_VERT_CYCLES_NE.AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_VERT_CYCLES_NE.AK_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_VERT_CYCLES_NE.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_VERT_CYCLES_NE.BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_VERT_CYCLES_NE.AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_VERT_CYCLES_NE.BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_VERT_INSERTS": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
     },
     "M3UPI.TxR_VERT_INSERTS.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_VERT_INSERTS.AK_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_VERT_INSERTS.AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_VERT_INSERTS.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_VERT_INSERTS.AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_VERT_INSERTS.BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_VERT_INSERTS.BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_VERT_NACK": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
     },
     "M3UPI.TxR_VERT_NACK.AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_VERT_NACK.BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_VERT_NACK.BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_VERT_NACK.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_VERT_NACK.AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_VERT_NACK.AK_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_VERT_NACK.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_VERT_OCCUPANCY": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
     },
     "M3UPI.TxR_VERT_OCCUPANCY.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_VERT_OCCUPANCY.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_VERT_OCCUPANCY.AK_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_VERT_OCCUPANCY.AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_VERT_OCCUPANCY.BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_VERT_OCCUPANCY.AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_VERT_OCCUPANCY.BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.TxR_VERT_STARVED": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
     },
     "M3UPI.TxR_VERT_STARVED.IV": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.TxR_VERT_STARVED.AK_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.TxR_VERT_STARVED.AD_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.TxR_VERT_STARVED.AK_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.TxR_VERT_STARVED.BL_AG1": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.TxR_VERT_STARVED.AD_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.TxR_VERT_STARVED.BL_AG0": {
          "Box": "M3UPI",
          "Category": "M3UPI CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.UPI_PEER_AD_CREDITS_EMPTY": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPIs on the AD Ring",
          "Desc": "UPI0 AD Credits Empty",
          "EvSel": 32,
          "ExtSel": "",
          "Notes": "2 cases for non-smi3 mode and 3 cases for smi3 mode",
     },
     "M3UPI.UPI_PEER_AD_CREDITS_EMPTY.VN0_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPIs on the AD Ring",
          "Desc": "UPI0 AD Credits Empty",
          "EvSel": 32,
          "ExtSel": "",
          "Notes": "2 cases for non-smi3 mode and 3 cases for smi3 mode",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.UPI_PEER_AD_CREDITS_EMPTY.VN0_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPIs on the AD Ring",
          "Desc": "UPI0 AD Credits Empty",
          "EvSel": 32,
          "ExtSel": "",
          "Notes": "2 cases for non-smi3 mode and 3 cases for smi3 mode",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.UPI_PEER_AD_CREDITS_EMPTY.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPIs on the AD Ring",
          "Desc": "UPI0 AD Credits Empty",
          "EvSel": 32,
          "ExtSel": "",
          "Notes": "2 cases for non-smi3 mode and 3 cases for smi3 mode",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.UPI_PEER_AD_CREDITS_EMPTY.VN1_SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPIs on the AD Ring",
          "Desc": "UPI0 AD Credits Empty",
          "EvSel": 32,
          "ExtSel": "",
          "Notes": "2 cases for non-smi3 mode and 3 cases for smi3 mode",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.UPI_PEER_AD_CREDITS_EMPTY.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPIs on the AD Ring",
          "Desc": "UPI0 AD Credits Empty",
          "EvSel": 32,
          "ExtSel": "",
          "Notes": "2 cases for non-smi3 mode and 3 cases for smi3 mode",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.UPI_PEER_AD_CREDITS_EMPTY.VN1_REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPIs on the AD Ring",
          "Desc": "UPI0 AD Credits Empty",
          "EvSel": 32,
          "ExtSel": "",
          "Notes": "2 cases for non-smi3 mode and 3 cases for smi3 mode",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.UPI_PEER_AD_CREDITS_EMPTY.VNA": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPIs on the AD Ring",
          "Desc": "UPI0 AD Credits Empty",
          "EvSel": 32,
          "ExtSel": "",
          "Notes": "2 cases for non-smi3 mode and 3 cases for smi3 mode",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.UPI_PEER_BL_CREDITS_EMPTY": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
          "Desc": "UPI0 BL Credits Empty",
          "EvSel": 33,
          "ExtSel": "",
          "Notes": "smi and non-smi modes",
     },
     "M3UPI.UPI_PEER_BL_CREDITS_EMPTY.VN1_NCS_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
          "Desc": "UPI0 BL Credits Empty",
          "EvSel": 33,
          "ExtSel": "",
          "Notes": "smi and non-smi modes",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.UPI_PEER_BL_CREDITS_EMPTY.VN0_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
          "Desc": "UPI0 BL Credits Empty",
          "EvSel": 33,
          "ExtSel": "",
          "Notes": "smi and non-smi modes",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.UPI_PEER_BL_CREDITS_EMPTY.VN0_NCS_NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
          "Desc": "UPI0 BL Credits Empty",
          "EvSel": 33,
          "ExtSel": "",
          "Notes": "smi and non-smi modes",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.UPI_PEER_BL_CREDITS_EMPTY.VNA": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
          "Desc": "UPI0 BL Credits Empty",
          "EvSel": 33,
          "ExtSel": "",
          "Notes": "smi and non-smi modes",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.UPI_PEER_BL_CREDITS_EMPTY.VN1_WB": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
          "Desc": "UPI0 BL Credits Empty",
          "EvSel": 33,
          "ExtSel": "",
          "Notes": "smi and non-smi modes",
          "Umask": "bx1xxxxxx",
     },
     "M3UPI.UPI_PEER_BL_CREDITS_EMPTY.VN0_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
          "Desc": "UPI0 BL Credits Empty",
          "EvSel": 33,
          "ExtSel": "",
          "Notes": "smi and non-smi modes",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.UPI_PEER_BL_CREDITS_EMPTY.VN1_RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI EGRESS Credit Events",
          "Counters": "0-3",
          "Defn": "No credits available to send to UPI on the BL Ring (diff between non-SMI and SMI mode)",
          "Desc": "UPI0 BL Credits Empty",
          "EvSel": 33,
          "ExtSel": "",
          "Notes": "smi and non-smi modes",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.UPI_PREFETCH_SPAWN": {
          "Box": "M3UPI",
          "Category": "M3UPI Special Egress Events",
          "Counters": "0-3",
          "Defn": "Count cases where FlowQ causes spawn of Prefetch to iMC/SMI3 target",
          "Desc": "FlowQ Generated Prefetch",
          "EvSel": 41,
          "ExtSel": "",
     },
     "M3UPI.VERT_RING_AD_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
     },
     "M3UPI.VERT_RING_AD_IN_USE.DN_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.VERT_RING_AD_IN_USE.UP_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.VERT_RING_AD_IN_USE.UP_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.VERT_RING_AD_IN_USE.DN_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.VERT_RING_AK_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
     },
     "M3UPI.VERT_RING_AK_IN_USE.UP_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.VERT_RING_AK_IN_USE.DN_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.VERT_RING_AK_IN_USE.UP_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.VERT_RING_AK_IN_USE.DN_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.VERT_RING_BL_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
     },
     "M3UPI.VERT_RING_BL_IN_USE.DN_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.VERT_RING_BL_IN_USE.UP_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.VERT_RING_BL_IN_USE.UP_ODD": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.VERT_RING_BL_IN_USE.DN_EVEN": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.VERT_RING_IV_IN_USE": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
     },
     "M3UPI.VERT_RING_IV_IN_USE.DN": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.VERT_RING_IV_IN_USE.UP": {
          "Box": "M3UPI",
          "Category": "M3UPI Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.VN0_CREDITS_USED": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN0 Credit Used",
          "EvSel": 92,
          "ExtSel": "",
     },
     "M3UPI.VN0_CREDITS_USED.SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN0 Credit Used",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.VN0_CREDITS_USED.NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN0 Credit Used",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.VN0_CREDITS_USED.RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN0 Credit Used",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.VN0_CREDITS_USED.REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN0 Credit Used",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.VN0_CREDITS_USED.WB": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN0 Credit Used",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.VN0_CREDITS_USED.NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN0 credit was used on the DRS message channel.  In order for a request to be transferred across UPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN0.  VNA is a shared pool used to achieve high performance.  The VN0 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN0 if they fail.  This counts the number of times a VN0 credit was used.  Note that a single VN0 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN0 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN0 Credit Used",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.VN0_NO_CREDITS": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN0 Credits",
          "Desc": "VN0 No Credits",
          "EvSel": 94,
          "ExtSel": "",
     },
     "M3UPI.VN0_NO_CREDITS.NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN0 Credits",
          "Desc": "VN0 No Credits",
          "EvSel": 94,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.VN0_NO_CREDITS.WB": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN0 Credits",
          "Desc": "VN0 No Credits",
          "EvSel": 94,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.VN0_NO_CREDITS.REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN0 Credits",
          "Desc": "VN0 No Credits",
          "EvSel": 94,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.VN0_NO_CREDITS.RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN0 Credits",
          "Desc": "VN0 No Credits",
          "EvSel": 94,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.VN0_NO_CREDITS.NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN0 Credits",
          "Desc": "VN0 No Credits",
          "EvSel": 94,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.VN0_NO_CREDITS.SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN0 Credits",
          "Desc": "VN0 No Credits",
          "EvSel": 94,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.VN1_CREDITS_USED": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN1 Credit Used",
          "EvSel": 93,
          "ExtSel": "",
     },
     "M3UPI.VN1_CREDITS_USED.NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN1 Credit Used",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.VN1_CREDITS_USED.WB": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN1 Credit Used",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.VN1_CREDITS_USED.REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN1 Credit Used",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M3UPI.VN1_CREDITS_USED.RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN1 Credit Used",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.VN1_CREDITS_USED.NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN1 Credit Used",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.VN1_CREDITS_USED.SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of times a VN1 credit was used on the WB message channel.  In order for a request to be transferred across QPI, it must be guaranteed to have a flit buffer on the remote socket to sink into.  There are two credit pools, VNA and VN1.  VNA is a shared pool used to achieve high performance.  The VN1 pool has reserved entries for each message class and is used to prevent deadlock.  Requests first attempt to acquire a VNA credit, and then fall back to VN1 if they fail.  This counts the number of times a VN1 credit was used.  Note that a single VN1 credit holds access to potentially multiple flit buffers.  For example, a transfer that uses VNA could use 9 flit buffers and in that case uses 9 credits.  A transfer on VN1 will only count a single credit even though it may use multiple buffers.",
          "Desc": "VN1 Credit Used",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.VN1_NO_CREDITS": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN1 Credits",
          "Desc": "VN1 No Credits",
          "EvSel": 95,
          "ExtSel": "",
     },
     "M3UPI.VN1_NO_CREDITS.WB": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN1 Credits",
          "Desc": "VN1 No Credits",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M3UPI.VN1_NO_CREDITS.NCS": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN1 Credits",
          "Desc": "VN1 No Credits",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M3UPI.VN1_NO_CREDITS.NCB": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN1 Credits",
          "Desc": "VN1 No Credits",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M3UPI.VN1_NO_CREDITS.SNP": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN1 Credits",
          "Desc": "VN1 No Credits",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M3UPI.VN1_NO_CREDITS.RSP": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN1 Credits",
          "Desc": "VN1 No Credits",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M3UPI.VN1_NO_CREDITS.REQ": {
          "Box": "M3UPI",
          "Category": "M3UPI Link VN Credit Events",
          "Defn": "Number of Cycles there were no VN1 Credits",
          "Desc": "VN1 No Credits",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     
# M2M:
     "M2M.AG0_AD_CRD_ACQUIRED": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
     },
     "M2M.AG0_AD_CRD_ACQUIRED.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxx1xxxx",
     },
     "M2M.AG0_AD_CRD_ACQUIRED.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxx1xxx",
     },
     "M2M.AG0_AD_CRD_ACQUIRED.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxxx1",
     },
     "M2M.AG0_AD_CRD_ACQUIRED.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxx1xx",
     },
     "M2M.AG0_AD_CRD_ACQUIRED.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxx1xxxxx",
     },
     "M2M.AG0_AD_CRD_ACQUIRED.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxx1x",
     },
     "M2M.AG0_AD_CRD_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
     },
     "M2M.AG0_AD_CRD_OCCUPANCY.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxx1xxx",
     },
     "M2M.AG0_AD_CRD_OCCUPANCY.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxx1xxxx",
     },
     "M2M.AG0_AD_CRD_OCCUPANCY.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxxx1",
     },
     "M2M.AG0_AD_CRD_OCCUPANCY.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxx1xxxxx",
     },
     "M2M.AG0_AD_CRD_OCCUPANCY.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxx1xx",
     },
     "M2M.AG0_AD_CRD_OCCUPANCY.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxx1x",
     },
     "M2M.AG0_BL_CRD_ACQUIRED": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
     },
     "M2M.AG0_BL_CRD_ACQUIRED.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.AG0_BL_CRD_ACQUIRED.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.AG0_BL_CRD_ACQUIRED.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.AG0_BL_CRD_ACQUIRED.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.AG0_BL_CRD_ACQUIRED.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.AG0_BL_CRD_ACQUIRED.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.AG0_BL_CRD_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
     },
     "M2M.AG0_BL_CRD_OCCUPANCY.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.AG0_BL_CRD_OCCUPANCY.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.AG0_BL_CRD_OCCUPANCY.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.AG0_BL_CRD_OCCUPANCY.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.AG0_BL_CRD_OCCUPANCY.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.AG0_BL_CRD_OCCUPANCY.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.AG1_AD_CRD_ACQUIRED": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
     },
     "M2M.AG1_AD_CRD_ACQUIRED.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxx1x",
     },
     "M2M.AG1_AD_CRD_ACQUIRED.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxx1xx",
     },
     "M2M.AG1_AD_CRD_ACQUIRED.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxx1xxxxx",
     },
     "M2M.AG1_AD_CRD_ACQUIRED.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxxx1",
     },
     "M2M.AG1_AD_CRD_ACQUIRED.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxx1xxxx",
     },
     "M2M.AG1_AD_CRD_ACQUIRED.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxx1xxx",
     },
     "M2M.AG1_AD_CRD_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
     },
     "M2M.AG1_AD_CRD_OCCUPANCY.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxx1xx",
     },
     "M2M.AG1_AD_CRD_OCCUPANCY.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxx1xxxxx",
     },
     "M2M.AG1_AD_CRD_OCCUPANCY.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxx1x",
     },
     "M2M.AG1_AD_CRD_OCCUPANCY.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxx1xxx",
     },
     "M2M.AG1_AD_CRD_OCCUPANCY.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxx1xxxx",
     },
     "M2M.AG1_AD_CRD_OCCUPANCY.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxxx1",
     },
     "M2M.AG1_BL_CRD_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
     },
     "M2M.AG1_BL_CRD_OCCUPANCY.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.AG1_BL_CRD_OCCUPANCY.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.AG1_BL_CRD_OCCUPANCY.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.AG1_BL_CRD_OCCUPANCY.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.AG1_BL_CRD_OCCUPANCY.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.AG1_BL_CRD_OCCUPANCY.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.AG1_BL_CREDITS_ACQUIRED": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
     },
     "M2M.AG1_BL_CREDITS_ACQUIRED.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.AG1_BL_CREDITS_ACQUIRED.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.AG1_BL_CREDITS_ACQUIRED.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.AG1_BL_CREDITS_ACQUIRED.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.AG1_BL_CREDITS_ACQUIRED.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.AG1_BL_CREDITS_ACQUIRED.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.BYPASS_M2M_EGRESS": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "M2M to iMC Bypass",
          "EvSel": 34,
          "ExtSel": "",
     },
     "M2M.BYPASS_M2M_EGRESS.TAKEN": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "M2M to iMC Bypass",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.BYPASS_M2M_EGRESS.NOT_TAKEN": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "M2M to iMC Bypass",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.BYPASS_M2M_INGRESS": {
          "Box": "M2M",
          "Category": "M2M BL Ingress Events",
          "Desc": "M2M to iMC Bypass",
          "EvSel": 33,
          "ExtSel": "",
     },
     "M2M.BYPASS_M2M_INGRESS.NOT_TAKEN": {
          "Box": "M2M",
          "Category": "M2M BL Ingress Events",
          "Desc": "M2M to iMC Bypass",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.BYPASS_M2M_INGRESS.TAKEN": {
          "Box": "M2M",
          "Category": "M2M BL Ingress Events",
          "Desc": "M2M to iMC Bypass",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.CLOCKTICKS": {
          "Box": "M2M",
          "Category": "M2M UCLK Events",
          "Desc": "Cycles - at UCLK",
          "EvSel": 0,
          "ExtSel": "",
     },
     "M2M.CMS_CLOCKTICKS": {
          "Box": "M2M",
          "Category": "M2M Misc Events",
          "Desc": "CMS Clockticks",
          "EvSel": 192,
          "ExtSel": "",
     },
     "M2M.DIRECT2CORE_NOT_TAKEN_DIRSTATE": {
          "Box": "M2M",
          "Category": "M2M DIRECT2CORE Events",
          "Desc": "Cycles when Direct2Core was Disabled",
          "EvSel": 36,
          "ExtSel": "",
     },
     "M2M.DIRECT2CORE_TAKEN": {
          "Box": "M2M",
          "Category": "M2M DIRECT2CORE Events",
          "Desc": "Direct2Core Messages Sent",
          "EvSel": 35,
          "ExtSel": "",
     },
     "M2M.DIRECT2CORE_TXN_OVERRIDE": {
          "Box": "M2M",
          "Category": "M2M DIRECT2CORE Events",
          "Desc": "Number of Reads that had Direct2Core Overridden",
          "EvSel": 37,
          "ExtSel": "",
     },
     "M2M.DIRECT2UPI_NOT_TAKEN_CREDITS": {
          "Box": "M2M",
          "Category": "M2M DIRECT2UPI Events",
          "Desc": "Number of Reads that had Direct2UPI Overridden",
          "EvSel": 40,
          "ExtSel": "",
     },
     "M2M.DIRECT2UPI_NOT_TAKEN_DIRSTATE": {
          "Box": "M2M",
          "Category": "M2M DIRECT2UPI Events",
          "Desc": "Cycles when Direct2UPI was Disabled",
          "EvSel": 39,
          "ExtSel": "",
     },
     "M2M.DIRECT2UPI_TAKEN": {
          "Box": "M2M",
          "Category": "M2M DIRECT2UPI Events",
          "Desc": "Direct2UPI Messages Sent",
          "EvSel": 38,
          "ExtSel": "",
     },
     "M2M.DIRECT2UPI_TXN_OVERRIDE": {
          "Box": "M2M",
          "Category": "M2M DIRECT2UPI Events",
          "Desc": "Number of Reads that had Direct2UPI Overridden",
          "EvSel": 41,
          "ExtSel": "",
     },
     "M2M.DIRECTORY_HIT": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
     },
     "M2M.DIRECTORY_HIT.CLEAN_A": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "b1xxxxxxx",
     },
     "M2M.DIRECTORY_HIT.DIRTY_I": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxxxxxx1",
     },
     "M2M.DIRECTORY_HIT.DIRTY_S": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxxxxx1x",
     },
     "M2M.DIRECTORY_HIT.CLEAN_P": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bx1xxxxxx",
     },
     "M2M.DIRECTORY_HIT.CLEAN_S": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxx1xxxxx",
     },
     "M2M.DIRECTORY_HIT.DIRTY_P": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxxxx1xx",
     },
     "M2M.DIRECTORY_HIT.CLEAN_I": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxx1xxxx",
     },
     "M2M.DIRECTORY_HIT.DIRTY_A": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Hit",
          "EvSel": 42,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxxx1xxx",
     },
     "M2M.DIRECTORY_LOOKUP": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Lookups",
          "EvSel": 45,
          "ExtSel": "",
     },
     "M2M.DIRECTORY_LOOKUP.ANY": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Lookups",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.DIRECTORY_LOOKUP.STATE_A": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Lookups",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.DIRECTORY_LOOKUP.STATE_S": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Lookups",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.DIRECTORY_LOOKUP.STATE_I": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Lookups",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.DIRECTORY_MISS": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
     },
     "M2M.DIRECTORY_MISS.DIRTY_I": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxxxxxx1",
     },
     "M2M.DIRECTORY_MISS.CLEAN_A": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "b1xxxxxxx",
     },
     "M2M.DIRECTORY_MISS.DIRTY_P": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxxxx1xx",
     },
     "M2M.DIRECTORY_MISS.DIRTY_A": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxxx1xxx",
     },
     "M2M.DIRECTORY_MISS.CLEAN_S": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxx1xxxxx",
     },
     "M2M.DIRECTORY_MISS.CLEAN_I": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxx1xxxx",
     },
     "M2M.DIRECTORY_MISS.DIRTY_S": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bxxxxxx1x",
     },
     "M2M.DIRECTORY_MISS.CLEAN_P": {
          "Box": "M2M",
          "Category": "M2M Directory State Events",
          "Desc": "Directory Miss",
          "EvSel": 43,
          "ExtSel": "",
          "Notes": "Covers NearMem Reads (Demand and Underfill).",
          "Umask": "bx1xxxxxx",
     },
     "M2M.DIRECTORY_UPDATE": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Updates",
          "EvSel": 46,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
     },
     "M2M.DIRECTORY_UPDATE.A2S": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Updates",
          "EvSel": 46,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bx1xxxxxx",
     },
     "M2M.DIRECTORY_UPDATE.S2I": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Updates",
          "EvSel": 46,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxxxx1xxx",
     },
     "M2M.DIRECTORY_UPDATE.ANY": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Updates",
          "EvSel": 46,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxxxxxxx1",
     },
     "M2M.DIRECTORY_UPDATE.A2I": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Updates",
          "EvSel": 46,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxx1xxxxx",
     },
     "M2M.DIRECTORY_UPDATE.S2A": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Updates",
          "EvSel": 46,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxxx1xxxx",
     },
     "M2M.DIRECTORY_UPDATE.I2A": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Updates",
          "EvSel": 46,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxxxxx1xx",
     },
     "M2M.DIRECTORY_UPDATE.I2S": {
          "Box": "M2M",
          "Category": "M2M DIRECTORY Events",
          "Desc": "Directory Updates",
          "EvSel": 46,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxxxxxx1x",
     },
     "M2M.EGRESS_ORDERING": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
     },
     "M2M.EGRESS_ORDERING.IV_SNOOPGO_DN": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.EGRESS_ORDERING.IV_SNOOPGO_UP": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.FAST_ASSERTED": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
     },
     "M2M.FAST_ASSERTED.HORZ": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "M2M.FAST_ASSERTED.VERT": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "M2M.HORZ_RING_AD_IN_USE": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
     },
     "M2M.HORZ_RING_AD_IN_USE.RIGHT_EVEN": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.HORZ_RING_AD_IN_USE.LEFT_ODD": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.HORZ_RING_AD_IN_USE.RIGHT_ODD": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.HORZ_RING_AD_IN_USE.LEFT_EVEN": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.HORZ_RING_AK_IN_USE": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
     },
     "M2M.HORZ_RING_AK_IN_USE.LEFT_EVEN": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.HORZ_RING_AK_IN_USE.RIGHT_ODD": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.HORZ_RING_AK_IN_USE.LEFT_ODD": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.HORZ_RING_AK_IN_USE.RIGHT_EVEN": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.HORZ_RING_BL_IN_USE": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
     },
     "M2M.HORZ_RING_BL_IN_USE.RIGHT_ODD": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.HORZ_RING_BL_IN_USE.LEFT_EVEN": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.HORZ_RING_BL_IN_USE.RIGHT_EVEN": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.HORZ_RING_BL_IN_USE.LEFT_ODD": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.HORZ_RING_IV_IN_USE": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
     },
     "M2M.HORZ_RING_IV_IN_USE.RIGHT": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.HORZ_RING_IV_IN_USE.LEFT": {
          "Box": "M2M",
          "Category": "M2M Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.IMC_READS": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Reads Issued to iMC",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Scrub Reads due to ECC errors not currently included",
     },
     "M2M.IMC_READS.ISOCH": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Reads Issued to iMC",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Scrub Reads due to ECC errors not currently included",
          "Umask": "bxxxxxx1x",
     },
     "M2M.IMC_READS.NORMAL": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Reads Issued to iMC",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Scrub Reads due to ECC errors not currently included",
          "Umask": "bxxxxxxx1",
     },
     "M2M.IMC_READS.FROM_TRANSGRESS": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Reads Issued to iMC",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Scrub Reads due to ECC errors not currently included",
          "Umask": "bxxx1xxxx",
     },
     "M2M.IMC_READS.ALL": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Reads Issued to iMC",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Scrub Reads due to ECC errors not currently included",
          "Umask": "bxxxxx1xx",
     },
     "M2M.IMC_WRITES": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Writes Issued to iMC",
          "EvSel": 56,
          "ExtSel": "",
          "Notes": "Scrub Writes due to ECC errors not currently included",
     },
     "M2M.IMC_WRITES.FULL": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Writes Issued to iMC",
          "EvSel": 56,
          "ExtSel": "",
          "Notes": "Scrub Writes due to ECC errors not currently included",
          "Umask": "bxxxxxxx1",
     },
     "M2M.IMC_WRITES.FULL_ISOCH": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Writes Issued to iMC",
          "EvSel": 56,
          "ExtSel": "",
          "Notes": "Scrub Writes due to ECC errors not currently included",
          "Umask": "bxxxxx1xx",
     },
     "M2M.IMC_WRITES.PARTIAL": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Writes Issued to iMC",
          "EvSel": 56,
          "ExtSel": "",
          "Notes": "Scrub Writes due to ECC errors not currently included",
          "Umask": "bxxxxxx1x",
     },
     "M2M.IMC_WRITES.PARTIAL_ISOCH": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Writes Issued to iMC",
          "EvSel": 56,
          "ExtSel": "",
          "Notes": "Scrub Writes due to ECC errors not currently included",
          "Umask": "bxxxx1xxx",
     },
     "M2M.IMC_WRITES.ALL": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Writes Issued to iMC",
          "EvSel": 56,
          "ExtSel": "",
          "Notes": "Scrub Writes due to ECC errors not currently included",
          "Umask": "bxxx1xxxx",
     },
     "M2M.IMC_WRITES.NI": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Writes Issued to iMC",
          "EvSel": 56,
          "ExtSel": "",
          "Notes": "Scrub Writes due to ECC errors not currently included",
          "Umask": "b1xxxxxxx",
     },
     "M2M.IMC_WRITES.FROM_TRANSGRESS": {
          "Box": "M2M",
          "Category": "M2M IMC Events",
          "Desc": "M2M Writes Issued to iMC",
          "EvSel": 56,
          "ExtSel": "",
          "Notes": "Scrub Writes due to ECC errors not currently included",
          "Umask": "bx1xxxxxx",
     },
     "M2M.PKT_MATCH": {
          "Box": "M2M",
          "Category": "M2M PACKET MATCH Events",
          "Desc": "Number Packet Header Matches",
          "EvSel": 76,
          "ExtSel": "",
     },
     "M2M.PKT_MATCH.MC": {
          "Box": "M2M",
          "Category": "M2M PACKET MATCH Events",
          "Desc": "Number Packet Header Matches",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.PKT_MATCH.MESH": {
          "Box": "M2M",
          "Category": "M2M PACKET MATCH Events",
          "Desc": "Number Packet Header Matches",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.PREFCAM_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M CAM Prefetch Events",
          "Desc": "Prefetch CAM Cycles Full",
          "EvSel": 83,
          "ExtSel": "",
     },
     "M2M.PREFCAM_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M CAM Prefetch Events",
          "Desc": "Prefetch CAM Cycles Not Empty",
          "EvSel": 84,
          "ExtSel": "",
     },
     "M2M.PREFCAM_DEMAND_PROMOTIONS": {
          "Box": "M2M",
          "Category": "M2M CAM Prefetch Events",
          "Desc": "Prefetch CAM Demand Promotions",
          "EvSel": 86,
          "ExtSel": "",
     },
     "M2M.PREFCAM_INSERTS": {
          "Box": "M2M",
          "Category": "M2M CAM Prefetch Events",
          "Desc": "Prefetch CAM Inserts",
          "EvSel": 87,
          "ExtSel": "",
     },
     "M2M.PREFCAM_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M CAM Prefetch Events",
          "Desc": "Prefetch CAM Occupancy",
          "EvSel": 85,
          "ExtSel": "",
     },
     "M2M.RING_BOUNCES_HORZ": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
     },
     "M2M.RING_BOUNCES_HORZ.AK": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RING_BOUNCES_HORZ.BL": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RING_BOUNCES_HORZ.AD": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RING_BOUNCES_HORZ.IV": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.RING_BOUNCES_VERT": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
     },
     "M2M.RING_BOUNCES_VERT.BL": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RING_BOUNCES_VERT.AK": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RING_BOUNCES_VERT.AD": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RING_BOUNCES_VERT.IV": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.RING_SINK_STARVED_HORZ": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
     },
     "M2M.RING_SINK_STARVED_HORZ.IV": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.RING_SINK_STARVED_HORZ.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.RING_SINK_STARVED_HORZ.BL": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RING_SINK_STARVED_HORZ.AD": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RING_SINK_STARVED_HORZ.AK": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RING_SINK_STARVED_VERT": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
     },
     "M2M.RING_SINK_STARVED_VERT.IV": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.RING_SINK_STARVED_VERT.BL": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RING_SINK_STARVED_VERT.AD": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RING_SINK_STARVED_VERT.AK": {
          "Box": "M2M",
          "Category": "M2M Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RING_SRC_THRTL": {
          "Box": "M2M",
          "Category": "M2M Horizontal  RING Events",
          "Desc": "Source Throttle",
          "EvSel": 164,
          "ExtSel": "",
     },
     "M2M.RPQ_CYCLES_REG_CREDITS": {
          "Box": "M2M",
          "Category": "M2M RPQ CREDIT Events",
          "Desc": "M2M to iMC RPQ Cycles w/Credits - Regular",
          "EvSel": 67,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
     },
     "M2M.RPQ_CYCLES_REG_CREDITS.CHN1": {
          "Box": "M2M",
          "Category": "M2M RPQ CREDIT Events",
          "Desc": "M2M to iMC RPQ Cycles w/Credits - Regular",
          "EvSel": 67,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RPQ_CYCLES_REG_CREDITS.CHN2": {
          "Box": "M2M",
          "Category": "M2M RPQ CREDIT Events",
          "Desc": "M2M to iMC RPQ Cycles w/Credits - Regular",
          "EvSel": 67,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RPQ_CYCLES_REG_CREDITS.CHN0": {
          "Box": "M2M",
          "Category": "M2M RPQ CREDIT Events",
          "Desc": "M2M to iMC RPQ Cycles w/Credits - Regular",
          "EvSel": 67,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RPQ_CYCLES_SPEC_CREDITS": {
          "Box": "M2M",
          "Category": "M2M RPQ CREDIT Events",
          "Desc": "M2M to iMC RPQ Cycles w/Credits - Special",
          "EvSel": 68,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
     },
     "M2M.RPQ_CYCLES_SPEC_CREDITS.CHN2": {
          "Box": "M2M",
          "Category": "M2M RPQ CREDIT Events",
          "Desc": "M2M to iMC RPQ Cycles w/Credits - Special",
          "EvSel": 68,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RPQ_CYCLES_SPEC_CREDITS.CHN0": {
          "Box": "M2M",
          "Category": "M2M RPQ CREDIT Events",
          "Desc": "M2M to iMC RPQ Cycles w/Credits - Special",
          "EvSel": 68,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RPQ_CYCLES_SPEC_CREDITS.CHN1": {
          "Box": "M2M",
          "Category": "M2M RPQ CREDIT Events",
          "Desc": "M2M to iMC RPQ Cycles w/Credits - Special",
          "EvSel": 68,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RxC_AD_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M AD Ingress Events",
          "Desc": "AD Ingress (from CMS) Full",
          "EvSel": 4,
          "ExtSel": "",
     },
     "M2M.RxC_AD_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M AD Ingress Events",
          "Desc": "AD Ingress (from CMS) Not Empty",
          "EvSel": 3,
          "ExtSel": "",
     },
     "M2M.RxC_AD_INSERTS": {
          "Box": "M2M",
          "Category": "M2M AD Ingress Events",
          "Desc": "AD Ingress (from CMS) Allocations",
          "EvSel": 1,
          "ExtSel": "",
     },
     "M2M.RxC_AD_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M AD Ingress Events",
          "Desc": "AD Ingress (from CMS) Occupancy",
          "EvSel": 2,
          "ExtSel": "",
     },
     "M2M.RxC_BL_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M BL Ingress Events",
          "Desc": "BL Ingress (from CMS) Full",
          "EvSel": 8,
          "ExtSel": "",
     },
     "M2M.RxC_BL_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M BL Ingress Events",
          "Desc": "BL Ingress (from CMS) Not Empty",
          "EvSel": 7,
          "ExtSel": "",
     },
     "M2M.RxC_BL_INSERTS": {
          "Box": "M2M",
          "Category": "M2M BL Ingress Events",
          "Desc": "BL Ingress (from CMS) Allocations",
          "EvSel": 5,
          "ExtSel": "",
     },
     "M2M.RxC_BL_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M BL Ingress Events",
          "Desc": "BL Ingress (from CMS) Occupancy",
          "EvSel": 6,
          "ExtSel": "",
     },
     "M2M.RxR_BUSY_STARVED": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
     },
     "M2M.RxR_BUSY_STARVED.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RxR_BUSY_STARVED.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RxR_BUSY_STARVED.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M2M.RxR_BUSY_STARVED.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M2M.RxR_BYPASS": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "M2M.RxR_BYPASS.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RxR_BYPASS.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RxR_BYPASS.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RxR_BYPASS.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M2M.RxR_BYPASS.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "M2M.RxR_BYPASS.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M2M.RxR_CRD_STARVED": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
     },
     "M2M.RxR_CRD_STARVED.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RxR_CRD_STARVED.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RxR_CRD_STARVED.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M2M.RxR_CRD_STARVED.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "M2M.RxR_CRD_STARVED.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M2M.RxR_CRD_STARVED.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RxR_CRD_STARVED.IFV": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "b1xxxxxxx",
     },
     "M2M.RxR_INSERTS": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "M2M.RxR_INSERTS.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RxR_INSERTS.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "M2M.RxR_INSERTS.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M2M.RxR_INSERTS.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M2M.RxR_INSERTS.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "M2M.RxR_INSERTS.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RxR_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "M2M.RxR_OCCUPANCY.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "M2M.RxR_OCCUPANCY.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "M2M.RxR_OCCUPANCY.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "M2M.RxR_OCCUPANCY.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "M2M.RxR_OCCUPANCY.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "M2M.RxR_OCCUPANCY.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1": {
          "Box": "M2M",
          "Category": "M2M CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TGR_AD_CREDITS": {
          "Box": "M2M",
          "Category": "M2M Transgress/M2MIngress Credit Events",
          "Desc": "Number AD Ingress Credits",
          "EvSel": 65,
          "ExtSel": "",
     },
     "M2M.TGR_BL_CREDITS": {
          "Box": "M2M",
          "Category": "M2M Transgress/M2MIngress Credit Events",
          "Desc": "Number BL Ingress Credits",
          "EvSel": 66,
          "ExtSel": "",
     },
     "M2M.TRACKER_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Cycles Full",
          "EvSel": 69,
          "ExtSel": "",
     },
     "M2M.TRACKER_CYCLES_FULL.CH1": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Cycles Full",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TRACKER_CYCLES_FULL.CH2": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Cycles Full",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TRACKER_CYCLES_FULL.CH0": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Cycles Full",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TRACKER_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Cycles Not Empty",
          "EvSel": 70,
          "ExtSel": "",
     },
     "M2M.TRACKER_CYCLES_NE.CH1": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Cycles Not Empty",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TRACKER_CYCLES_NE.CH2": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Cycles Not Empty",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TRACKER_CYCLES_NE.CH0": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Cycles Not Empty",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TRACKER_INSERTS": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Inserts",
          "EvSel": 73,
          "ExtSel": "",
     },
     "M2M.TRACKER_INSERTS.CH1": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Inserts",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TRACKER_INSERTS.CH2": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Inserts",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TRACKER_INSERTS.CH0": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Inserts",
          "EvSel": 73,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TRACKER_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Occupancy",
          "EvSel": 71,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
     },
     "M2M.TRACKER_OCCUPANCY.CH0": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Occupancy",
          "EvSel": 71,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TRACKER_OCCUPANCY.CH1": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Occupancy",
          "EvSel": 71,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TRACKER_OCCUPANCY.CH2": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Tracker Occupancy",
          "EvSel": 71,
          "ExtSel": "",
          "Notes": "Tie to Packet Mask/Match?",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TRACKER_PENDING_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Data Pending Occupancy",
          "EvSel": 72,
          "ExtSel": "",
     },
     "M2M.TxC_AD_CREDITS_ACQUIRED": {
          "Box": "M2M",
          "Category": "M2M AD CMS/Mesh Egress Credit Events",
          "Desc": "AD Egress (to CMS) Credit Acquired",
          "EvSel": 13,
          "ExtSel": "",
     },
     "M2M.TxC_AD_CREDIT_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M AD CMS/Mesh Egress Credit Events",
          "Desc": "AD Egress (to CMS) Credits Occupancy",
          "EvSel": 14,
          "ExtSel": "",
     },
     "M2M.TxC_AD_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M AD Egress Events",
          "Desc": "AD Egress (to CMS) Full",
          "EvSel": 12,
          "ExtSel": "",
     },
     "M2M.TxC_AD_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M AD Egress Events",
          "Desc": "AD Egress (to CMS) Not Empty",
          "EvSel": 11,
          "ExtSel": "",
     },
     "M2M.TxC_AD_INSERTS": {
          "Box": "M2M",
          "Category": "M2M AD Egress Events",
          "Desc": "AD Egress (to CMS) Allocations",
          "EvSel": 9,
          "ExtSel": "",
     },
     "M2M.TxC_AD_NO_CREDIT_CYCLES": {
          "Box": "M2M",
          "Category": "M2M AD CMS/Mesh Egress Credit Events",
          "Desc": "Cycles with No AD Egress (to CMS) Credits",
          "EvSel": 15,
          "ExtSel": "",
     },
     "M2M.TxC_AD_NO_CREDIT_STALLED": {
          "Box": "M2M",
          "Category": "M2M AD CMS/Mesh Egress Credit Events",
          "Desc": "Cycles Stalled with No AD Egress (to CMS) Credits",
          "EvSel": 16,
          "ExtSel": "",
     },
     "M2M.TxC_AD_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M AD Egress Events",
          "Desc": "AD Egress (to CMS) Occupancy",
          "EvSel": 10,
          "ExtSel": "",
     },
     "M2M.TxC_AK": {
          "Box": "M2M",
          "Category": "M2M OUTBOUND_TX Events",
          "Desc": "Outbound Ring Transactions on AK",
          "EvSel": 57,
          "ExtSel": "",
     },
     "M2M.TxC_AK.NDR": {
          "Box": "M2M",
          "Category": "M2M OUTBOUND_TX Events",
          "Desc": "Outbound Ring Transactions on AK",
          "EvSel": 57,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK.CRD_CBO": {
          "Box": "M2M",
          "Category": "M2M OUTBOUND_TX Events",
          "Desc": "Outbound Ring Transactions on AK",
          "EvSel": 57,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_CREDITS_ACQUIRED": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "AK Egress (to CMS) Credit Acquired",
          "EvSel": 29,
          "ExtSel": "",
     },
     "M2M.TxC_AK_CREDITS_ACQUIRED.CMS1": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "AK Egress (to CMS) Credit Acquired",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_CREDITS_ACQUIRED.CMS0": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "AK Egress (to CMS) Credit Acquired",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK_CREDIT_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "AK Egress (to CMS) Credits Occupancy",
          "EvSel": 30,
          "ExtSel": "",
     },
     "M2M.TxC_AK_CREDIT_OCCUPANCY.CMS1": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "AK Egress (to CMS) Credits Occupancy",
          "EvSel": 30,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_CREDIT_OCCUPANCY.CMS0": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "AK Egress (to CMS) Credits Occupancy",
          "EvSel": 30,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
     },
     "M2M.TxC_AK_CYCLES_FULL.RDCRD0": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "b0xxx1xxx",
     },
     "M2M.TxC_AK_CYCLES_FULL.CMS1": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_CYCLES_FULL.WRCMP1": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "b1x1xxxxx",
     },
     "M2M.TxC_AK_CYCLES_FULL.CMS0": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK_CYCLES_FULL.WRCRD1": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "b1xx1xxxx",
     },
     "M2M.TxC_AK_CYCLES_FULL.ALL": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "bxxxxxx11",
     },
     "M2M.TxC_AK_CYCLES_FULL.RDCRD1": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "b1xxx1xxx",
     },
     "M2M.TxC_AK_CYCLES_FULL.WRCMP0": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "b0x1xxxxx",
     },
     "M2M.TxC_AK_CYCLES_FULL.WRCRD0": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Full",
          "EvSel": 20,
          "ExtSel": "",
          "Notes": "Some extra wild guesses as to what the subevents count - and why does it seem to track 0 credits for each CMS agent, but the other related events don't?",
          "Umask": "b0xx1xxxx",
     },
     "M2M.TxC_AK_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Not Empty",
          "EvSel": 19,
          "ExtSel": "",
     },
     "M2M.TxC_AK_CYCLES_NE.ALL": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Not Empty",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxxxxx11",
     },
     "M2M.TxC_AK_CYCLES_NE.WRCRD": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Not Empty",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxC_AK_CYCLES_NE.WRCMP": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Not Empty",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxC_AK_CYCLES_NE.CMS0": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Not Empty",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK_CYCLES_NE.RDCRD": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Not Empty",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxC_AK_CYCLES_NE.CMS1": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Not Empty",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_INSERTS": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Allocations",
          "EvSel": 17,
          "ExtSel": "",
     },
     "M2M.TxC_AK_INSERTS.CMS0": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Allocations",
          "EvSel": 17,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK_INSERTS.ALL": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Allocations",
          "EvSel": 17,
          "ExtSel": "",
          "Umask": "bxxxxxx11",
     },
     "M2M.TxC_AK_INSERTS.PREF_RD_CAM_HIT": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Allocations",
          "EvSel": 17,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxC_AK_INSERTS.WRCRD": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Allocations",
          "EvSel": 17,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxC_AK_INSERTS.WRCMP": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Allocations",
          "EvSel": 17,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxC_AK_INSERTS.CMS1": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Allocations",
          "EvSel": 17,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_INSERTS.RDCRD": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Allocations",
          "EvSel": 17,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxC_AK_NO_CREDIT_CYCLES": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "Cycles with No AK Egress (to CMS) Credits",
          "EvSel": 31,
          "ExtSel": "",
     },
     "M2M.TxC_AK_NO_CREDIT_CYCLES.CMS1": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "Cycles with No AK Egress (to CMS) Credits",
          "EvSel": 31,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_NO_CREDIT_CYCLES.CMS0": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "Cycles with No AK Egress (to CMS) Credits",
          "EvSel": 31,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK_NO_CREDIT_STALLED": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "Cycles Stalled with No AK Egress (to CMS) Credits",
          "EvSel": 32,
          "ExtSel": "",
     },
     "M2M.TxC_AK_NO_CREDIT_STALLED.CMS0": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "Cycles Stalled with No AK Egress (to CMS) Credits",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK_NO_CREDIT_STALLED.CMS1": {
          "Box": "M2M",
          "Category": "M2M AK CMS/Mesh Egress Credit Events",
          "Desc": "Cycles Stalled with No AK Egress (to CMS) Credits",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Occupancy",
          "EvSel": 18,
          "ExtSel": "",
     },
     "M2M.TxC_AK_OCCUPANCY.RDCRD": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Occupancy",
          "EvSel": 18,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxC_AK_OCCUPANCY.CMS1": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Occupancy",
          "EvSel": 18,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_OCCUPANCY.ALL": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Occupancy",
          "EvSel": 18,
          "ExtSel": "",
          "Umask": "bxxxxxx11",
     },
     "M2M.TxC_AK_OCCUPANCY.WRCRD": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Occupancy",
          "EvSel": 18,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxC_AK_OCCUPANCY.WRCMP": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Occupancy",
          "EvSel": 18,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxC_AK_OCCUPANCY.CMS0": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Occupancy",
          "EvSel": 18,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_AK_SIDEBAND": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Sideband",
          "EvSel": 107,
          "ExtSel": "",
     },
     "M2M.TxC_AK_SIDEBAND.WR": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Sideband",
          "EvSel": 107,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_AK_SIDEBAND.RD": {
          "Box": "M2M",
          "Category": "M2M AK Egress Events",
          "Desc": "AK Egress (to CMS) Sideband",
          "EvSel": 107,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL": {
          "Box": "M2M",
          "Category": "M2M OUTBOUND_TX Events",
          "Desc": "Outbound DRS Ring Transactions to Cache",
          "EvSel": 64,
          "ExtSel": "",
     },
     "M2M.TxC_BL.DRS_CORE": {
          "Box": "M2M",
          "Category": "M2M OUTBOUND_TX Events",
          "Desc": "Outbound DRS Ring Transactions to Cache",
          "EvSel": 64,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL.DRS_CACHE": {
          "Box": "M2M",
          "Category": "M2M OUTBOUND_TX Events",
          "Desc": "Outbound DRS Ring Transactions to Cache",
          "EvSel": 64,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL.DRS_UPI": {
          "Box": "M2M",
          "Category": "M2M OUTBOUND_TX Events",
          "Desc": "Outbound DRS Ring Transactions to Cache",
          "EvSel": 64,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxC_BL_CREDITS_ACQUIRED": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "BL Egress (to CMS) Credit Acquired",
          "EvSel": 25,
          "ExtSel": "",
     },
     "M2M.TxC_BL_CREDITS_ACQUIRED.CMS0": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "BL Egress (to CMS) Credit Acquired",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL_CREDITS_ACQUIRED.CMS1": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "BL Egress (to CMS) Credit Acquired",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL_CREDIT_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "BL Egress (to CMS) Credits Occupancy",
          "EvSel": 26,
          "ExtSel": "",
     },
     "M2M.TxC_BL_CREDIT_OCCUPANCY.CMS1": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "BL Egress (to CMS) Credits Occupancy",
          "EvSel": 26,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL_CREDIT_OCCUPANCY.CMS0": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "BL Egress (to CMS) Credits Occupancy",
          "EvSel": 26,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Full",
          "EvSel": 24,
          "ExtSel": "",
     },
     "M2M.TxC_BL_CYCLES_FULL.CMS1": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Full",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL_CYCLES_FULL.CMS0": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Full",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL_CYCLES_FULL.ALL": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Full",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxxx11",
     },
     "M2M.TxC_BL_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Not Empty",
          "EvSel": 23,
          "ExtSel": "",
     },
     "M2M.TxC_BL_CYCLES_NE.CMS1": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Not Empty",
          "EvSel": 23,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL_CYCLES_NE.ALL": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Not Empty",
          "EvSel": 23,
          "ExtSel": "",
          "Umask": "bxxxxxx11",
     },
     "M2M.TxC_BL_CYCLES_NE.CMS0": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Not Empty",
          "EvSel": 23,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL_INSERTS": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Allocations",
          "EvSel": 21,
          "ExtSel": "",
     },
     "M2M.TxC_BL_INSERTS.CMS1": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Allocations",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL_INSERTS.CMS0": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Allocations",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL_INSERTS.ALL": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Allocations",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxxxxxx11",
     },
     "M2M.TxC_BL_NO_CREDIT_CYCLES": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "Cycles with No BL Egress (to CMS) Credits",
          "EvSel": 27,
          "ExtSel": "",
     },
     "M2M.TxC_BL_NO_CREDIT_CYCLES.CMS0": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "Cycles with No BL Egress (to CMS) Credits",
          "EvSel": 27,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL_NO_CREDIT_CYCLES.CMS1": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "Cycles with No BL Egress (to CMS) Credits",
          "EvSel": 27,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL_NO_CREDIT_STALLED": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "Cycles Stalled with No BL Egress (to CMS) Credits",
          "EvSel": 28,
          "ExtSel": "",
     },
     "M2M.TxC_BL_NO_CREDIT_STALLED.CMS1": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "Cycles Stalled with No BL Egress (to CMS) Credits",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL_NO_CREDIT_STALLED.CMS0": {
          "Box": "M2M",
          "Category": "M2M BL CMS/Mesh Egress Credit Events",
          "Desc": "Cycles Stalled with No BL Egress (to CMS) Credits",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Occupancy",
          "EvSel": 22,
          "ExtSel": "",
     },
     "M2M.TxC_BL_OCCUPANCY.CMS1": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Occupancy",
          "EvSel": 22,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxC_BL_OCCUPANCY.CMS0": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Occupancy",
          "EvSel": 22,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxC_BL_OCCUPANCY.ALL": {
          "Box": "M2M",
          "Category": "M2M BL Egress Events",
          "Desc": "BL Egress (to CMS) Occupancy",
          "EvSel": 22,
          "ExtSel": "",
          "Umask": "bxxxxxx11",
     },
     "M2M.TxR_HORZ_ADS_USED": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
     },
     "M2M.TxR_HORZ_ADS_USED.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_HORZ_ADS_USED.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_HORZ_ADS_USED.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_HORZ_ADS_USED.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_HORZ_ADS_USED.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_HORZ_BYPASS": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
     },
     "M2M.TxR_HORZ_BYPASS.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_HORZ_BYPASS.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_HORZ_BYPASS.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_HORZ_BYPASS.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_HORZ_BYPASS.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_HORZ_BYPASS.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_HORZ_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
     },
     "M2M.TxR_HORZ_CYCLES_FULL.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_HORZ_CYCLES_FULL.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_HORZ_CYCLES_FULL.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_HORZ_CYCLES_FULL.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_HORZ_CYCLES_FULL.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_HORZ_CYCLES_FULL.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_HORZ_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
     },
     "M2M.TxR_HORZ_CYCLES_NE.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_HORZ_CYCLES_NE.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_HORZ_CYCLES_NE.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_HORZ_CYCLES_NE.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_HORZ_CYCLES_NE.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_HORZ_CYCLES_NE.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_HORZ_INSERTS": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
     },
     "M2M.TxR_HORZ_INSERTS.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_HORZ_INSERTS.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_HORZ_INSERTS.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_HORZ_INSERTS.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_HORZ_INSERTS.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_HORZ_INSERTS.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_HORZ_NACK": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
     },
     "M2M.TxR_HORZ_NACK.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_HORZ_NACK.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_HORZ_NACK.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_HORZ_NACK.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_HORZ_NACK.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_HORZ_NACK.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_HORZ_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
     },
     "M2M.TxR_HORZ_OCCUPANCY.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_HORZ_OCCUPANCY.BL_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_HORZ_OCCUPANCY.AD_CRD": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_HORZ_OCCUPANCY.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_HORZ_OCCUPANCY.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_HORZ_OCCUPANCY.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_HORZ_STARVED": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
     },
     "M2M.TxR_HORZ_STARVED.AK_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_HORZ_STARVED.AD_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_HORZ_STARVED.IV_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_HORZ_STARVED.BL_BNC": {
          "Box": "M2M",
          "Category": "M2M CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_ADS_USED": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
     },
     "M2M.TxR_VERT_ADS_USED.BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_ADS_USED.AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_VERT_ADS_USED.BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_VERT_ADS_USED.AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_VERT_ADS_USED.AK_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_VERT_ADS_USED.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_VERT_BYPASS": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
     },
     "M2M.TxR_VERT_BYPASS.IV": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_VERT_BYPASS.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_VERT_BYPASS.AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_VERT_BYPASS.AK_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_VERT_BYPASS.AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_VERT_BYPASS.BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_VERT_BYPASS.BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
     },
     "M2M.TxR_VERT_CYCLES_FULL.BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_CYCLES_FULL.AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_VERT_CYCLES_FULL.BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_VERT_CYCLES_FULL.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_VERT_CYCLES_FULL.AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_VERT_CYCLES_FULL.AK_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_VERT_CYCLES_FULL.IV": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_VERT_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
     },
     "M2M.TxR_VERT_CYCLES_NE.IV": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_VERT_CYCLES_NE.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_VERT_CYCLES_NE.AK_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_VERT_CYCLES_NE.AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_VERT_CYCLES_NE.AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_VERT_CYCLES_NE.BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_VERT_CYCLES_NE.BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_INSERTS": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
     },
     "M2M.TxR_VERT_INSERTS.BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_INSERTS.AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_VERT_INSERTS.BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_VERT_INSERTS.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_VERT_INSERTS.AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_VERT_INSERTS.AK_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_VERT_INSERTS.IV": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_VERT_NACK": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
     },
     "M2M.TxR_VERT_NACK.AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_VERT_NACK.BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_VERT_NACK.BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_NACK.IV": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_VERT_NACK.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_VERT_NACK.AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_VERT_NACK.AK_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_VERT_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
     },
     "M2M.TxR_VERT_OCCUPANCY.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_VERT_OCCUPANCY.AK_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_VERT_OCCUPANCY.AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_VERT_OCCUPANCY.IV": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.TxR_VERT_OCCUPANCY.BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_OCCUPANCY.AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_VERT_OCCUPANCY.BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_VERT_STARVED": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
     },
     "M2M.TxR_VERT_STARVED.BL_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.TxR_VERT_STARVED.AD_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.TxR_VERT_STARVED.BL_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "M2M.TxR_VERT_STARVED.AD_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "M2M.TxR_VERT_STARVED.AK_AG0": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.TxR_VERT_STARVED.AK_AG1": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "M2M.TxR_VERT_STARVED.IV": {
          "Box": "M2M",
          "Category": "M2M CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.VERT_RING_AD_IN_USE": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
     },
     "M2M.VERT_RING_AD_IN_USE.UP_EVEN": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.VERT_RING_AD_IN_USE.DN_ODD": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.VERT_RING_AD_IN_USE.UP_ODD": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.VERT_RING_AD_IN_USE.DN_EVEN": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.VERT_RING_AK_IN_USE": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
     },
     "M2M.VERT_RING_AK_IN_USE.UP_ODD": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.VERT_RING_AK_IN_USE.DN_EVEN": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.VERT_RING_AK_IN_USE.DN_ODD": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.VERT_RING_AK_IN_USE.UP_EVEN": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.VERT_RING_BL_IN_USE": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
     },
     "M2M.VERT_RING_BL_IN_USE.DN_ODD": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "M2M.VERT_RING_BL_IN_USE.UP_EVEN": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.VERT_RING_BL_IN_USE.DN_EVEN": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.VERT_RING_BL_IN_USE.UP_ODD": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.VERT_RING_IV_IN_USE": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
     },
     "M2M.VERT_RING_IV_IN_USE.DN": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.VERT_RING_IV_IN_USE.UP": {
          "Box": "M2M",
          "Category": "M2M Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.WPQ_CYCLES_REG_CREDITS": {
          "Box": "M2M",
          "Category": "M2M WPQ_CREDITS Events",
          "Desc": "M2M->iMC WPQ Cycles w/Credits - Regular",
          "EvSel": 77,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
     },
     "M2M.WPQ_CYCLES_REG_CREDITS.CHN0": {
          "Box": "M2M",
          "Category": "M2M WPQ_CREDITS Events",
          "Desc": "M2M->iMC WPQ Cycles w/Credits - Regular",
          "EvSel": 77,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxxxx1",
     },
     "M2M.WPQ_CYCLES_REG_CREDITS.CHN2": {
          "Box": "M2M",
          "Category": "M2M WPQ_CREDITS Events",
          "Desc": "M2M->iMC WPQ Cycles w/Credits - Regular",
          "EvSel": 77,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxx1xx",
     },
     "M2M.WPQ_CYCLES_REG_CREDITS.CHN1": {
          "Box": "M2M",
          "Category": "M2M WPQ_CREDITS Events",
          "Desc": "M2M->iMC WPQ Cycles w/Credits - Regular",
          "EvSel": 77,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxxx1x",
     },
     "M2M.WPQ_CYCLES_SPEC_CREDITS": {
          "Box": "M2M",
          "Category": "M2M WPQ_CREDITS Events",
          "Desc": "M2M->iMC WPQ Cycles w/Credits - Special",
          "EvSel": 78,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
     },
     "M2M.WPQ_CYCLES_SPEC_CREDITS.CHN0": {
          "Box": "M2M",
          "Category": "M2M WPQ_CREDITS Events",
          "Desc": "M2M->iMC WPQ Cycles w/Credits - Special",
          "EvSel": 78,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxxxx1",
     },
     "M2M.WPQ_CYCLES_SPEC_CREDITS.CHN2": {
          "Box": "M2M",
          "Category": "M2M WPQ_CREDITS Events",
          "Desc": "M2M->iMC WPQ Cycles w/Credits - Special",
          "EvSel": 78,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxx1xx",
     },
     "M2M.WPQ_CYCLES_SPEC_CREDITS.CHN1": {
          "Box": "M2M",
          "Category": "M2M WPQ_CREDITS Events",
          "Desc": "M2M->iMC WPQ Cycles w/Credits - Special",
          "EvSel": 78,
          "ExtSel": "",
          "Notes": "To Count # cycles w/o credits, either set .thresh to 1 and .invert to 1 OR subtract this from total cycles",
          "Umask": "bxxxxxx1x",
     },
     "M2M.WRITE_TRACKER_CYCLES_FULL": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Cycles Full",
          "EvSel": 74,
          "ExtSel": "",
     },
     "M2M.WRITE_TRACKER_CYCLES_FULL.CH1": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Cycles Full",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.WRITE_TRACKER_CYCLES_FULL.CH2": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Cycles Full",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.WRITE_TRACKER_CYCLES_FULL.CH0": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Cycles Full",
          "EvSel": 74,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.WRITE_TRACKER_CYCLES_NE": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Cycles Not Empty",
          "EvSel": 75,
          "ExtSel": "",
     },
     "M2M.WRITE_TRACKER_CYCLES_NE.CH2": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Cycles Not Empty",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.WRITE_TRACKER_CYCLES_NE.CH1": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Cycles Not Empty",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.WRITE_TRACKER_CYCLES_NE.CH0": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Cycles Not Empty",
          "EvSel": 75,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.WRITE_TRACKER_INSERTS": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Inserts",
          "EvSel": 97,
          "ExtSel": "",
     },
     "M2M.WRITE_TRACKER_INSERTS.CH1": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Inserts",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.WRITE_TRACKER_INSERTS.CH2": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Inserts",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "M2M.WRITE_TRACKER_INSERTS.CH0": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Inserts",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.WRITE_TRACKER_OCCUPANCY": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Occupancy",
          "EvSel": 96,
          "ExtSel": "",
     },
     "M2M.WRITE_TRACKER_OCCUPANCY.CH0": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Occupancy",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "M2M.WRITE_TRACKER_OCCUPANCY.CH1": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Occupancy",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "M2M.WRITE_TRACKER_OCCUPANCY.CH2": {
          "Box": "M2M",
          "Category": "M2M TRACKER Events",
          "Desc": "Write Tracker Occupancy",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     
# PCU:
     "PCU.CLOCKTICKS": {
          "Box": "PCU",
          "Category": "PCU MEMORY_PHASE_SHEDDING Events",
          "Counters": "0-3",
          "Defn": "The PCU runs off a fixed 1 GHz clock.  This event counts the number of pclk cycles measured while the counter was enabled.  The pclk, like the Memory Controller's dclk, counts at a constant rate making it a good measure of actual wall time.",
          "Desc": "pclk Cycles",
          "EvSel": 0,
          "ExtSel": "",
     },
     "PCU.CORE_TRANSITION_CYCLES": {
          "Box": "PCU",
          "Category": "PCU CORE_C_STATE_TRANSITION Events",
          "Counters": "0-3",
          "EvSel": 96,
          "ExtSel": "",
     },
     "PCU.CTS_EVENT0": {
          "Box": "PCU",
          "Category": "PCU Misc Events",
          "EvSel": 17,
          "ExtSel": "",
     },
     "PCU.CTS_EVENT1": {
          "Box": "PCU",
          "Category": "PCU Misc Events",
          "EvSel": 18,
          "ExtSel": "",
     },
     "PCU.DEMOTIONS": {
          "Box": "PCU",
          "Category": "PCU CORE_C_STATE_TRANSITION Events",
          "EvSel": 48,
          "ExtSel": "",
     },
     "PCU.FIVR_PS_PS0_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FIVR Events",
          "Counters": "0-3",
          "Defn": "Cycles spent in phase-shedding power state 0",
          "Desc": "Phase Shed 0 Cycles",
          "EvSel": 117,
          "ExtSel": "",
     },
     "PCU.FIVR_PS_PS1_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FIVR Events",
          "Counters": "0-3",
          "Defn": "Cycles spent in phase-shedding power state 1",
          "Desc": "Phase Shed 1 Cycles",
          "EvSel": 118,
          "ExtSel": "",
     },
     "PCU.FIVR_PS_PS2_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FIVR Events",
          "Counters": "0-3",
          "Defn": "Cycles spent in phase-shedding power state 2",
          "Desc": "Phase Shed 2 Cycles",
          "EvSel": 119,
          "ExtSel": "",
     },
     "PCU.FIVR_PS_PS3_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FIVR Events",
          "Counters": "0-3",
          "Defn": "Cycles spent in phase-shedding power state 3",
          "Desc": "Phase Shed 3 Cycles",
          "EvSel": 120,
          "ExtSel": "",
     },
     "PCU.FREQ_MAX_LIMIT_THERMAL_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FREQ_MAX_LIMIT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when thermal conditions are the upper limit on frequency.  This is related to the THERMAL_THROTTLE CYCLES_ABOVE_TEMP event, which always counts cycles when we are above the thermal temperature.  This event (STRONGEST_UPPER_LIMIT) is sampled at the output of the algorithm that determines the actual frequency, while THERMAL_THROTTLE looks at the input.",
          "Desc": "Thermal Strongest Upper Limit Cycles",
          "EvSel": 4,
          "ExtSel": "",
     },
     "PCU.FREQ_MAX_POWER_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FREQ_MAX_LIMIT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when power is the upper limit on frequency.",
          "Desc": "Power Strongest Upper Limit Cycles",
          "EvSel": 5,
          "ExtSel": "",
     },
     "PCU.FREQ_MIN_IO_P_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FREQ_MIN_LIMIT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when IO P Limit is preventing us from dropping the frequency lower.  This algorithm monitors the needs to the IO subsystem on both local and remote sockets and will maintain a frequency high enough to maintain good IO BW.  This is necessary for when all the IA cores on a socket are idle but a user still would like to maintain high IO Bandwidth.",
          "Desc": "IO P Limit Strongest Lower Limit Cycles",
          "EvSel": 115,
          "ExtSel": "",
     },
     "PCU.FREQ_TRANS_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FREQ_TRANS Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the system is changing frequency.  This can not be filtered by thread ID.  One can also use it with the occupancy counter that monitors number of threads in C0 to estimate the performance impact that frequency transitions had on the system.",
          "Desc": "Cycles spent changing Frequency",
          "EvSel": 116,
          "ExtSel": "",
     },
     "PCU.MCP_PROCHOT_CYCLES": {
          "Box": "PCU",
          "Category": "PCU PROCHOT Events",
          "EvSel": 6,
          "ExtSel": "",
     },
     "PCU.MEMORY_PHASE_SHEDDING_CYCLES": {
          "Box": "PCU",
          "Category": "PCU MEMORY_PHASE_SHEDDING Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles that the PCU has triggered memory phase shedding.  This is a mode that can be run in the iMC physicals that saves power at the expense of additional latency.",
          "Desc": "Memory Phase Shedding Cycles",
          "EvSel": 47,
          "ExtSel": "",
          "Notes": "Package C1",
     },
     "PCU.PKG_RESIDENCY_C0_CYCLES": {
          "Box": "PCU",
          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the package was in C0.  This event can be used in conjunction with edge detect to count C0 entrances (or exits using invert).  Residency events do not include transition times.",
          "Desc": "Package C State Residency - C0",
          "EvSel": 42,
          "ExtSel": "",
     },
     "PCU.PKG_RESIDENCY_C2E_CYCLES": {
          "Box": "PCU",
          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the package was in C2E.  This event can be used in conjunction with edge detect to count C2E entrances (or exits using invert).  Residency events do not include transition times.",
          "Desc": "Package C State Residency - C2E",
          "EvSel": 43,
          "ExtSel": "",
     },
     "PCU.PKG_RESIDENCY_C3_CYCLES": {
          "Box": "PCU",
          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the package was in C3.  This event can be used in conjunction with edge detect to count C3 entrances (or exits using invert).  Residency events do not include transition times.",
          "Desc": "Package C State Residency - C3",
          "EvSel": 44,
          "ExtSel": "",
     },
     "PCU.PKG_RESIDENCY_C6_CYCLES": {
          "Box": "PCU",
          "Category": "PCU PKG_C_STATE_RESIDENCY Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the package was in C6.  This event can be used in conjunction with edge detect to count C6 entrances (or exits using invert).  Residency events do not include transition times.",
          "Desc": "Package C State Residency - C6",
          "EvSel": 45,
          "ExtSel": "",
     },
     "PCU.PMAX_THROTTLED_CYCLES": {
          "Box": "PCU",
          "Category": "PCU FREQ_MAX_LIMIT Events",
          "EvSel": 7,
          "ExtSel": "",
     },
     "PCU.PROCHOT_EXTERNAL_CYCLES": {
          "Box": "PCU",
          "Category": "PCU PROCHOT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles that we are in external PROCHOT mode.  This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip.",
          "Desc": "External Prochot",
          "EvSel": 10,
          "ExtSel": "",
     },
     "PCU.PROCHOT_INTERNAL_CYCLES": {
          "Box": "PCU",
          "Category": "PCU PROCHOT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles that we are in Interal PROCHOT mode.  This mode is triggered when a sensor on the die determines that we are too hot and must throttle to avoid damaging the chip.",
          "Desc": "Internal Prochot",
          "EvSel": 9,
          "ExtSel": "",
     },
     "PCU.TOTAL_TRANSITION_CYCLES": {
          "Box": "PCU",
          "Category": "PCU CORE_C_STATE_TRANSITION Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent performing core C state transitions across all cores.",
          "Desc": "Total Core C State Transition Cycles",
          "EvSel": 114,
          "ExtSel": "",
     },
     "PCU.VR_HOT_CYCLES": {
          "Box": "PCU",
          "Category": "PCU VR_HOT Events",
          "Counters": "0-3",
          "Desc": "VR Hot",
          "EvSel": 66,
          "ExtSel": "",
     },
     
# IRP:
     "IRP.CACHE_TOTAL_OCCUPANCY": {
          "Box": "IRP",
          "Category": "IRP WRITE_CACHE Events",
          "Counters": "0-1",
          "Defn": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
          "Desc": "Total Write Cache Occupancy",
          "EvSel": 15,
          "ExtSel": "",
     },
     "IRP.CACHE_TOTAL_OCCUPANCY.ANY": {
          "Box": "IRP",
          "Category": "IRP WRITE_CACHE Events",
          "Counters": "0-1",
          "Defn": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
          "Desc": "Total Write Cache Occupancy",
          "EvSel": 15,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "IRP.CACHE_TOTAL_OCCUPANCY.IV_Q": {
          "Box": "IRP",
          "Category": "IRP WRITE_CACHE Events",
          "Counters": "0-1",
          "Defn": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
          "Desc": "Total Write Cache Occupancy",
          "EvSel": 15,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "IRP.CACHE_TOTAL_OCCUPANCY.MEM": {
          "Box": "IRP",
          "Category": "IRP WRITE_CACHE Events",
          "Counters": "0-1",
          "Defn": "Accumulates the number of reads and writes that are outstanding in the uncore in each cycle.  This is effectively the sum of the READ_OCCUPANCY and WRITE_OCCUPANCY events.",
          "Desc": "Total Write Cache Occupancy",
          "EvSel": 15,
          "ExtSel": "",
          "Umask": "b00000100",
     },
     "IRP.CLOCKTICKS": {
          "Box": "IRP",
          "Category": "IRP CLOCK Events",
          "Desc": "IRP Clocks",
          "EvSel": 1,
          "ExtSel": "",
     },
     "IRP.COHERENT_OPS": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
     },
     "IRP.COHERENT_OPS.PCIRDCUR": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "IRP.COHERENT_OPS.PCIDCAHINT": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "IRP.COHERENT_OPS.RFO": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "IRP.COHERENT_OPS.PCITOM": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "IRP.COHERENT_OPS.WBMTOI": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "IRP.COHERENT_OPS.DRD": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "IRP.COHERENT_OPS.CLFLUSH": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "IRP.COHERENT_OPS.CRD": {
          "Box": "IRP",
          "Category": "IRP Coherency Events",
          "Counters": "0-1",
          "Defn": "Counts the number of coherency related operations servied by the IRP",
          "Desc": "Coherent Ops",
          "EvSel": 16,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "IRP.FAF_FULL": {
          "Box": "IRP",
          "Category": "IRP FAF Events",
          "Desc": "FAF RF full",
          "EvSel": 23,
          "ExtSel": "",
     },
     "IRP.FAF_INSERTS": {
          "Box": "IRP",
          "Category": "IRP FAF Events",
          "Desc": "FAF - request insert from TC.",
          "EvSel": 24,
          "ExtSel": "",
     },
     "IRP.FAF_OCCUPANCY": {
          "Box": "IRP",
          "Category": "IRP FAF Events",
          "Desc": "FAF occupancy",
          "EvSel": 25,
          "ExtSel": "",
     },
     "IRP.FAF_TRANSACTIONS": {
          "Box": "IRP",
          "Category": "IRP FAF Events",
          "Desc": "FAF allocation -- sent to ADQ",
          "EvSel": 22,
          "ExtSel": "",
     },
     "IRP.IRP_ALL": {
          "Box": "IRP",
          "Category": "IRP IRP Buffer Events",
          "EvSel": 30,
          "ExtSel": "",
     },
     "IRP.IRP_ALL.OUTBOUND_INSERTS": {
          "Box": "IRP",
          "Category": "IRP IRP Buffer Events",
          "EvSel": 30,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "IRP.IRP_ALL.INBOUND_INSERTS": {
          "Box": "IRP",
          "Category": "IRP IRP Buffer Events",
          "EvSel": 30,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "IRP.MISC0": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
     },
     "IRP.MISC0.UNKNOWN": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "b1xx00000",
     },
     "IRP.MISC0.FAST_REQ": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "b000000x1",
     },
     "IRP.MISC0.2ND_RD_INSERT": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bx00xx100",
     },
     "IRP.MISC0.FAST_REJ": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "b0000001x",
     },
     "IRP.MISC0.2ND_WR_INSERT": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bx00x1x00",
     },
     "IRP.MISC0.FAST_XFER": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bxx100000",
     },
     "IRP.MISC0.2ND_ATOMIC_INSERT": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bx001xx00",
     },
     "IRP.MISC0.PF_ACK_HINT": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 0",
          "EvSel": 28,
          "ExtSel": "",
          "Umask": "bx1x00000",
     },
     "IRP.MISC1": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 1",
          "EvSel": 29,
          "ExtSel": "",
     },
     "IRP.MISC1.SEC_RCVD_VLD": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 1",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bx1xx0000",
     },
     "IRP.MISC1.SLOW_M": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 1",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "b000x1xxx",
     },
     "IRP.MISC1.LOST_FWD": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 1",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "b0001xxxx",
     },
     "IRP.MISC1.SEC_RCVD_INVLD": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 1",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "bxx1x0000",
     },
     "IRP.MISC1.SLOW_E": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 1",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "b000xx1xx",
     },
     "IRP.MISC1.SLOW_S": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 1",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "b000xxx1x",
     },
     "IRP.MISC1.SLOW_I": {
          "Box": "IRP",
          "Category": "IRP MISC Events",
          "Counters": "0-1",
          "Desc": "Misc Events - Set 1",
          "EvSel": 29,
          "ExtSel": "",
          "Umask": "b000xxxx1",
     },
     "IRP.P2P_INSERTS": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Defn": "P2P requests from the ITC",
          "Desc": "P2P Requests",
          "EvSel": 20,
          "ExtSel": "",
     },
     "IRP.P2P_OCCUPANCY": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Defn": "P2P B & S Queue Occupancy",
          "Desc": "P2P Occupancy",
          "EvSel": 21,
          "ExtSel": "",
     },
     "IRP.P2P_TRANSACTIONS": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
     },
     "IRP.P2P_TRANSACTIONS.RD": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "IRP.P2P_TRANSACTIONS.WR": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "IRP.P2P_TRANSACTIONS.REM": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "IRP.P2P_TRANSACTIONS.REM_AND_TGT_MATCH": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "IRP.P2P_TRANSACTIONS.LOC_AND_TGT_MATCH": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "IRP.P2P_TRANSACTIONS.LOC": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "IRP.P2P_TRANSACTIONS.CMPL": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "IRP.P2P_TRANSACTIONS.MSG": {
          "Box": "IRP",
          "Category": "IRP P2P Events",
          "Desc": "P2P Transactions",
          "EvSel": 19,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "IRP.SNOOP_RESP": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Desc": "Snoop Responses",
          "EvSel": 18,
          "ExtSel": "",
          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
     },
     "IRP.SNOOP_RESP.MISS": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Desc": "Snoop Responses",
          "EvSel": 18,
          "ExtSel": "",
          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
          "Umask": "bxxxxxxx1",
     },
     "IRP.SNOOP_RESP.SNPINV": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Desc": "Snoop Responses",
          "EvSel": 18,
          "ExtSel": "",
          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
          "Umask": "bx1xxxxxx",
     },
     "IRP.SNOOP_RESP.HIT_ES": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Desc": "Snoop Responses",
          "EvSel": 18,
          "ExtSel": "",
          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
          "Umask": "bxxxxx1xx",
     },
     "IRP.SNOOP_RESP.SNPCODE": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Desc": "Snoop Responses",
          "EvSel": 18,
          "ExtSel": "",
          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
          "Umask": "bxxx1xxxx",
     },
     "IRP.SNOOP_RESP.HIT_I": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Desc": "Snoop Responses",
          "EvSel": 18,
          "ExtSel": "",
          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
          "Umask": "bxxxxxx1x",
     },
     "IRP.SNOOP_RESP.SNPDATA": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Desc": "Snoop Responses",
          "EvSel": 18,
          "ExtSel": "",
          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
          "Umask": "bxx1xxxxx",
     },
     "IRP.SNOOP_RESP.HIT_M": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Desc": "Snoop Responses",
          "EvSel": 18,
          "ExtSel": "",
          "Notes": "The first 4 subevent bits are the Responses to the Code/Data/Invalid Snoops represented by the last 3 subevent bits.  At least 1 of the bottom 4 bits must be combined with 1 of the top 3 bits to obtain counts.  Unsure which combinations are possible.",
          "Umask": "bxxxx1xxx",
     },
     "IRP.TRANSACTIONS": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
          "Desc": "Inbound Transaction Count",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
     },
     "IRP.TRANSACTIONS.WR_PREF": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
          "Desc": "Inbound Transaction Count",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
          "Umask": "bxxxx1xxx",
     },
     "IRP.TRANSACTIONS.READS": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
          "Desc": "Inbound Transaction Count",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
          "Umask": "bxxxxxxx1",
     },
     "IRP.TRANSACTIONS.ATOMIC": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
          "Desc": "Inbound Transaction Count",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
          "Umask": "bxxx1xxxx",
     },
     "IRP.TRANSACTIONS.WRITES": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
          "Desc": "Inbound Transaction Count",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
          "Umask": "bxxxxxx1x",
     },
     "IRP.TRANSACTIONS.RD_PREF": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
          "Desc": "Inbound Transaction Count",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
          "Umask": "bxxxxx1xx",
     },
     "IRP.TRANSACTIONS.OTHER": {
          "Box": "IRP",
          "Category": "IRP TRANSACTIONS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of \"Inbound\" transactions from the IRP to the Uncore.  This can be filtered based on request type in addition to the source queue.  Note the special filtering equation.  We do OR-reduction on the request type.  If the SOURCE bit is set, then we also do AND qualification based on the source portID.",
          "Desc": "Inbound Transaction Count",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "Bit 7 is a filter that can be applied to the other subevents.  Meaningless by itself.",
          "Umask": "bxx1xxxxx",
     },
     "IRP.TxC_AK_INSERTS": {
          "Box": "IRP",
          "Category": "IRP AK Egress Events",
          "Counters": "0-1",
          "Desc": "AK Egress Allocations",
          "EvSel": 11,
          "ExtSel": "",
     },
     "IRP.TxC_BL_DRS_CYCLES_FULL": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL DRS Egress Cycles Full",
          "EvSel": 5,
          "ExtSel": "",
     },
     "IRP.TxC_BL_DRS_INSERTS": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL DRS Egress Inserts",
          "EvSel": 2,
          "ExtSel": "",
     },
     "IRP.TxC_BL_DRS_OCCUPANCY": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL DRS Egress Occupancy",
          "EvSel": 8,
          "ExtSel": "",
     },
     "IRP.TxC_BL_NCB_CYCLES_FULL": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL NCB Egress Cycles Full",
          "EvSel": 6,
          "ExtSel": "",
     },
     "IRP.TxC_BL_NCB_INSERTS": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL NCB Egress Inserts",
          "EvSel": 3,
          "ExtSel": "",
     },
     "IRP.TxC_BL_NCB_OCCUPANCY": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL NCB Egress Occupancy",
          "EvSel": 9,
          "ExtSel": "",
     },
     "IRP.TxC_BL_NCS_CYCLES_FULL": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL NCS Egress Cycles Full",
          "EvSel": 7,
          "ExtSel": "",
     },
     "IRP.TxC_BL_NCS_INSERTS": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL NCS Egress Inserts",
          "EvSel": 4,
          "ExtSel": "",
     },
     "IRP.TxC_BL_NCS_OCCUPANCY": {
          "Box": "IRP",
          "Category": "IRP BL Egress Events",
          "Counters": "0-1",
          "Desc": "BL NCS Egress Occupancy",
          "EvSel": 10,
          "ExtSel": "",
     },
     "IRP.TxR2_AD_STALL_CREDIT_CYCLES": {
          "Box": "IRP",
          "Category": "IRP STALL_CYCLES Events",
          "Counters": "0-1",
          "Defn": "Counts the number times when it is not possible to issue a request to the R2PCIe because there are no AD Egress Credits available.",
          "Desc": "No AD Egress Credit Stalls",
          "EvSel": 26,
          "ExtSel": "",
     },
     "IRP.TxR2_BL_STALL_CREDIT_CYCLES": {
          "Box": "IRP",
          "Category": "IRP STALL_CYCLES Events",
          "Counters": "0-1",
          "Defn": "Counts the number times when it is not possible to issue data to the R2PCIe because there are no BL Egress Credits available.",
          "Desc": "No BL Egress Credit Stalls",
          "EvSel": 27,
          "ExtSel": "",
     },
     "IRP.TxS_DATA_INSERTS_NCB": {
          "Box": "IRP",
          "Category": "IRP OUTBOUND_REQUESTS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of requests issued to the switch (towards the devices).",
          "Desc": "Outbound Read Requests",
          "EvSel": 13,
          "ExtSel": "",
     },
     "IRP.TxS_DATA_INSERTS_NCS": {
          "Box": "IRP",
          "Category": "IRP OUTBOUND_REQUESTS Events",
          "Counters": "0-1",
          "Defn": "Counts the number of requests issued to the switch (towards the devices).",
          "Desc": "Outbound Read Requests",
          "EvSel": 14,
          "ExtSel": "",
     },
     "IRP.TxS_REQUEST_OCCUPANCY": {
          "Box": "IRP",
          "Category": "IRP OUTBOUND_REQUESTS Events",
          "Counters": "0-1",
          "Defn": "Accumultes the number of outstanding outbound requests from the IRP to the switch (towards the devices).  This can be used in conjuection with the allocations event in order to calculate average latency of outbound requests.",
          "Desc": "Outbound Request Queue Occupancy",
          "EvSel": 12,
          "ExtSel": "",
     },
     
# IIO:
     "IIO.CLOCKTICKS": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Desc": "Traffic Controller Clocks",
          "EvSel": 1,
          "ExtSel": "",
     },
     "IIO.COMP_BUF_INSERTS": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Inserts",
          "EvSel": 194,
          "ExtSel": "",
     },
     "IIO.COMP_BUF_INSERTS.PORT3": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Inserts",
          "EvSel": 194,
          "FCMask": "b111",
          "ExtSel": "",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.COMP_BUF_INSERTS.PORT0": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Inserts",
          "EvSel": 194,
          "FCMask": "b111",
          "ExtSel": "",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxx1xx",
     },
     "IIO.COMP_BUF_INSERTS.PORT2": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Inserts",
          "EvSel": 194,
          "FCMask": "b111",
          "ExtSel": "",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.COMP_BUF_INSERTS.PORT1": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Inserts",
          "EvSel": 194,
          "FCMask": "b111",
          "ExtSel": "",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxx1xx",
     },
     "IIO.COMP_BUF_OCCUPANCY": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Occupancy",
          "EvSel": 213,
          "ExtSel": "",
     },
     "IIO.COMP_BUF_OCCUPANCY.PORT2": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Occupancy",
          "EvSel": 213,
          "ExtSel": "",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxxxx",
     },
     "IIO.COMP_BUF_OCCUPANCY.PORT1": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Occupancy",
          "EvSel": 213,
          "ExtSel": "",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxxxx",
     },
     "IIO.COMP_BUF_OCCUPANCY.PORT0": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Occupancy",
          "EvSel": 213,
          "ExtSel": "",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxxxx",
     },
     "IIO.COMP_BUF_OCCUPANCY.PORT3": {
          "Box": "IIO",
          "Category": "IIO PCIe Completion Buffer Events",
          "Desc": "PCIe Completion Buffer Occupancy",
          "EvSel": 213,
          "ExtSel": "",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
     },
     "IIO.DATA_REQ_BY_CPU.IO_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "b1xxxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "b1xxxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "b1xxxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.MEM_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_BY_CPU.IO_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "b1xxxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.CFG_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "b1xxxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.PEER_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_BY_CPU.IO_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "b1xxxxxxx",
     },
     "IIO.DATA_REQ_BY_CPU.IO_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "2-3",
          "Defn": "Number of double word (4 bytes) requests initiated by the main die to the attached device.",
          "Desc": "Data requested by the CPU",
          "EvSel": 192,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_OF_CPU": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_OF_CPU.MSG.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMICCMP.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMICCMP.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMIC.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMIC.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_OF_CPU.MSG.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMIC.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMIC.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_OF_CPU.MSG.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMICCMP.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.MSG.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_OF_CPU.MSG.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMIC.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMIC.PART1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxx1xxxx",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_OF_CPU.ATOMICCMP.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.DATA_REQ_OF_CPU.MSG.VTD0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.DATA_REQ_OF_CPU.MEM_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxxx1",
     },
     "IIO.DATA_REQ_OF_CPU.PEER_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Payload Events",
          "Counters": "0-1",
          "Defn": "Number of double word (4 bytes) requests the attached device made of the main die.",
          "Desc": "Data requested of the CPU",
          "EvSel": 131,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Multiply value by 4 to convert to number of Bytes.   Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.   Counts are incremented on the request path rather than the completion path.    Expect to change back on next prodcut.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.LINK_NUM_CORR_ERR": {
          "Box": "IIO",
          "Category": "IIO Link Events",
          "Desc": "Num Link  Correctable Errors",
          "EvSel": 15,
          "ExtSel": "",
     },
     "IIO.LINK_NUM_RETRIES": {
          "Box": "IIO",
          "Category": "IIO Link Events",
          "Desc": "Num Link Retries",
          "EvSel": 14,
          "ExtSel": "",
     },
     "IIO.MASK_MATCH": {
          "Box": "IIO",
          "Category": "IIO Miscellaneous Events",
          "Desc": "Number packets that passed the Mask/Match Filter",
          "EvSel": 33,
          "ExtSel": "",
     },
     "IIO.MASK_MATCH_AND": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if all bits specified by mask match",
          "Desc": "AND Mask/match for debug bus",
          "EvSel": 2,
          "ExtSel": "",
     },
     "IIO.MASK_MATCH_AND.BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if all bits specified by mask match",
          "Desc": "AND Mask/match for debug bus",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "IIO.MASK_MATCH_AND.NOT_BUS0_NOT_BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if all bits specified by mask match",
          "Desc": "AND Mask/match for debug bus",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "IIO.MASK_MATCH_AND.BUS0_NOT_BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if all bits specified by mask match",
          "Desc": "AND Mask/match for debug bus",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "IIO.MASK_MATCH_AND.NOT_BUS0_BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if all bits specified by mask match",
          "Desc": "AND Mask/match for debug bus",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "IIO.MASK_MATCH_AND.BUS0": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if all bits specified by mask match",
          "Desc": "AND Mask/match for debug bus",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "IIO.MASK_MATCH_AND.BUS0_BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if all bits specified by mask match",
          "Desc": "AND Mask/match for debug bus",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "IIO.MASK_MATCH_OR": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if any bits specified by mask match",
          "Desc": "OR Mask/match for debug bus",
          "EvSel": 3,
          "ExtSel": "",
     },
     "IIO.MASK_MATCH_OR.BUS0_BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if any bits specified by mask match",
          "Desc": "OR Mask/match for debug bus",
          "EvSel": 3,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "IIO.MASK_MATCH_OR.BUS0": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if any bits specified by mask match",
          "Desc": "OR Mask/match for debug bus",
          "EvSel": 3,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "IIO.MASK_MATCH_OR.NOT_BUS0_BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if any bits specified by mask match",
          "Desc": "OR Mask/match for debug bus",
          "EvSel": 3,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "IIO.MASK_MATCH_OR.NOT_BUS0_NOT_BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if any bits specified by mask match",
          "Desc": "OR Mask/match for debug bus",
          "EvSel": 3,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "IIO.MASK_MATCH_OR.BUS0_NOT_BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if any bits specified by mask match",
          "Desc": "OR Mask/match for debug bus",
          "EvSel": 3,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "IIO.MASK_MATCH_OR.BUS1": {
          "Box": "IIO",
          "Category": "IIO Debug Events",
          "Counters": "0-3",
          "Defn": "Asserted if any bits specified by mask match",
          "Desc": "OR Mask/match for debug bus",
          "EvSel": 3,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "IIO.NOTHING": {
          "Box": "IIO",
          "Category": "IIO CLOCK Events",
          "EvSel": 0,
          "ExtSel": "",
     },
     "IIO.SYMBOL_TIMES": {
          "Box": "IIO",
          "Category": "IIO Miscellaneous Events",
          "Defn": "Gen1 - increment once every 4nS, Gen2 - increment once every 2nS, Gen3 - increment once every 1nS",
          "Desc": "Symbol Times on Link",
          "EvSel": 130,
          "ExtSel": "",
     },
     "IIO.TXN_REQ_BY_CPU": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "b1xxxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_BY_CPU.IO_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "b1xxxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "b1xxxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.MEM_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "b1xxxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.CFG_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "b1xxxxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.PEER_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_BY_CPU.IO_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_BY_CPU.IO_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Outbound.  Number of requests, to the attached device, initiated by the main die.",
          "Desc": "Number Transactions requested by the CPU",
          "EvSel": 193,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "b1xxxxxxx",
     },
     "IIO.TXN_REQ_OF_CPU": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
     },
     "IIO.TXN_REQ_OF_CPU.MSG.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMIC.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMIC.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMICCMP.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MSG.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_WRITE.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_WRITE.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_WRITE.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMIC.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_OF_CPU.MSG.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMIC.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MSG.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMICCMP.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_READ.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMIC.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_WRITE.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMIC.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bx1xxxxxx",
          "Umask": "bxxx1xxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_READ.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_OF_CPU.MSG.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_READ.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxxxxx1xx",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_WRITE.PART1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxx1x",
          "Umask": "bxxxxxx1x",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_READ.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMICCMP.PART2": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxx1xx",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.MEM_WRITE.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxxxxx1",
     },
     "IIO.TXN_REQ_OF_CPU.MSG.VTD1": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxx1xxxxx",
          "Umask": "bx1xxxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.ATOMICCMP.PART0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxxxxx1",
          "Umask": "bxx1xxxxx",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_READ.PART3": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxxx1xxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.TXN_REQ_OF_CPU.PEER_READ.VTD0": {
          "Box": "IIO",
          "Category": "IIO Transaction Events",
          "Counters": "0-3",
          "Defn": "Also known as Inbound.  Number of 64 byte cache line requests initiated by the attached device.",
          "Desc": "Number Transactions requested of the CPU",
          "EvSel": 132,
          "FCMask": "b111",
          "ExtSel": "",
          "Notes": "Unlike free running counters, Mem Read and Peer read subevents count requests not completions.  Peer R/W subevents do not include confined P2P traffic.",
          "PortMask": "bxxx1xxxx",
          "Umask": "bxxxx1xxx",
     },
     "IIO.VTD_ACCESS": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
     },
     "IIO.VTD_ACCESS.L1_MISS": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
          "Umask": "bxxxxx1xx",
     },
     "IIO.VTD_ACCESS.TLB_FULL": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
          "Umask": "bx1xxxxxx",
     },
     "IIO.VTD_ACCESS.L2_MISS": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
          "Umask": "bxxxx1xxx",
     },
     "IIO.VTD_ACCESS.L4_PAGE_HIT": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
          "Umask": "bxxxxxxx1",
     },
     "IIO.VTD_ACCESS.L3_MISS": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
          "Umask": "bxxx1xxxx",
     },
     "IIO.VTD_ACCESS.TLB1_MISS": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
          "Umask": "b1xxxxxxx",
     },
     "IIO.VTD_ACCESS.TLB_MISS": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
          "Umask": "bxx1xxxxx",
     },
     "IIO.VTD_ACCESS.CTXT_MISS": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Access",
          "EvSel": 65,
          "ExtSel": "",
          "Notes": ".L4_PAGE_HIT + L4_MISS == # VT-D Lookups?   .CTXT_MISS + .L1_MISS + .L2_MISS + .L3_MISS + .L4_MISS == # Page Walker Reads Issued by VT-d?",
          "Umask": "bxxxxxx1x",
     },
     "IIO.VTD_OCCUPANCY": {
          "Box": "IIO",
          "Category": "IIO VTd Events",
          "Counters": "0-3",
          "Desc": "VTd Occupancy",
          "EvSel": 64,
          "ExtSel": "",
     },
     
# CHA:
     "CHA.AG0_AD_CRD_ACQUIRED": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
     },
     "CHA.AG0_AD_CRD_ACQUIRED.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxxx1",
     },
     "CHA.AG0_AD_CRD_ACQUIRED.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxx1xxxx",
     },
     "CHA.AG0_AD_CRD_ACQUIRED.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxx1xxx",
     },
     "CHA.AG0_AD_CRD_ACQUIRED.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxx1x",
     },
     "CHA.AG0_AD_CRD_ACQUIRED.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxx1xx",
     },
     "CHA.AG0_AD_CRD_ACQUIRED.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 AD Credits Acquired",
          "EvSel": 128,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxx1xxxxx",
     },
     "CHA.AG0_AD_CRD_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
     },
     "CHA.AG0_AD_CRD_OCCUPANCY.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxx1x",
     },
     "CHA.AG0_AD_CRD_OCCUPANCY.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxx1xxxxx",
     },
     "CHA.AG0_AD_CRD_OCCUPANCY.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxx1xx",
     },
     "CHA.AG0_AD_CRD_OCCUPANCY.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxxx1",
     },
     "CHA.AG0_AD_CRD_OCCUPANCY.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxx1xxx",
     },
     "CHA.AG0_AD_CRD_OCCUPANCY.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 AD Credits Occupancy",
          "EvSel": 130,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxx1xxxx",
     },
     "CHA.AG0_BL_CRD_ACQUIRED": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
     },
     "CHA.AG0_BL_CRD_ACQUIRED.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.AG0_BL_CRD_ACQUIRED.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.AG0_BL_CRD_ACQUIRED.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.AG0_BL_CRD_ACQUIRED.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.AG0_BL_CRD_ACQUIRED.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.AG0_BL_CRD_ACQUIRED.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent0 BL Credits Acquired",
          "EvSel": 136,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.AG0_BL_CRD_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
     },
     "CHA.AG0_BL_CRD_OCCUPANCY.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.AG0_BL_CRD_OCCUPANCY.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.AG0_BL_CRD_OCCUPANCY.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.AG0_BL_CRD_OCCUPANCY.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.AG0_BL_CRD_OCCUPANCY.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.AG0_BL_CRD_OCCUPANCY.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 0 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent0 BL Credits Occupancy",
          "EvSel": 138,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.AG1_AD_CRD_ACQUIRED": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
     },
     "CHA.AG1_AD_CRD_ACQUIRED.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxx1x",
     },
     "CHA.AG1_AD_CRD_ACQUIRED.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxx1xxxxx",
     },
     "CHA.AG1_AD_CRD_ACQUIRED.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxx1xx",
     },
     "CHA.AG1_AD_CRD_ACQUIRED.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxxxxx1",
     },
     "CHA.AG1_AD_CRD_ACQUIRED.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxx1xxxx",
     },
     "CHA.AG1_AD_CRD_ACQUIRED.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 AD Credits Acquired",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the OR of all selected",
          "Umask": "bxxxx1xxx",
     },
     "CHA.AG1_AD_CRD_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
     },
     "CHA.AG1_AD_CRD_OCCUPANCY.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxx1xxxxx",
     },
     "CHA.AG1_AD_CRD_OCCUPANCY.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxx1xx",
     },
     "CHA.AG1_AD_CRD_OCCUPANCY.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxx1x",
     },
     "CHA.AG1_AD_CRD_OCCUPANCY.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxx1xxxx",
     },
     "CHA.AG1_AD_CRD_OCCUPANCY.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxx1xxx",
     },
     "CHA.AG1_AD_CRD_OCCUPANCY.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 AD credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 AD Credits Occupancy",
          "EvSel": 134,
          "ExtSel": "",
          "Notes": "If multiple masks are selected, will count the SUM of all selected",
          "Umask": "bxxxxxxx1",
     },
     "CHA.AG1_BL_CRD_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
     },
     "CHA.AG1_BL_CRD_OCCUPANCY.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.AG1_BL_CRD_OCCUPANCY.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.AG1_BL_CRD_OCCUPANCY.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.AG1_BL_CRD_OCCUPANCY.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.AG1_BL_CRD_OCCUPANCY.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.AG1_BL_CRD_OCCUPANCY.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits in use in a given cycle, per transgress",
          "Desc": "CMS Agent1 BL Credits Occupancy",
          "EvSel": 142,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.AG1_BL_CREDITS_ACQUIRED": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
     },
     "CHA.AG1_BL_CREDITS_ACQUIRED.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.AG1_BL_CREDITS_ACQUIRED.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.AG1_BL_CREDITS_ACQUIRED.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.AG1_BL_CREDITS_ACQUIRED.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.AG1_BL_CREDITS_ACQUIRED.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.AG1_BL_CREDITS_ACQUIRED.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of CMS Agent 1 BL credits acquired in a given cycle, per transgress.",
          "Desc": "CMS Agent1 BL Credits Acquired",
          "EvSel": 140,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.BYPASS_CHA_IMC": {
          "Box": "CHA",
          "Category": "CHA HA BYPASS Events",
          "Defn": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.",
          "Desc": "CHA to iMC Bypass",
          "EvSel": 87,
          "ExtSel": "",
     },
     "CHA.BYPASS_CHA_IMC.NOT_TAKEN": {
          "Box": "CHA",
          "Category": "CHA HA BYPASS Events",
          "Defn": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.",
          "Desc": "CHA to iMC Bypass",
          "EvSel": 87,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.BYPASS_CHA_IMC.INTERMEDIATE": {
          "Box": "CHA",
          "Category": "CHA HA BYPASS Events",
          "Defn": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.",
          "Desc": "CHA to iMC Bypass",
          "EvSel": 87,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.BYPASS_CHA_IMC.TAKEN": {
          "Box": "CHA",
          "Category": "CHA HA BYPASS Events",
          "Defn": "Counts the number of times when the CHA was able to bypass HA pipe on the way to iMC.  This is a latency optimization for situations when there is light loadings on the memory subsystem.  This can be filtered by when the bypass was taken and when it was not.",
          "Desc": "CHA to iMC Bypass",
          "EvSel": 87,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.CLOCKTICKS": {
          "Box": "CHA",
          "Category": "CHA UCLK Events",
          "Counters": "0-3",
          "Desc": "Uncore Clocks",
          "EvSel": 0,
          "ExtSel": "",
     },
     "CHA.CMS_CLOCKTICKS": {
          "Box": "CHA",
          "Category": "CHA Misc Events",
          "Desc": "CMS Clockticks",
          "EvSel": 192,
          "ExtSel": "",
     },
     "CHA.CORE_PMA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Counters": "0-3",
          "Desc": "Core PMA Events",
          "EvSel": 23,
          "ExtSel": "",
     },
     "CHA.CORE_PMA.C1_STATE": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Counters": "0-3",
          "Desc": "Core PMA Events",
          "EvSel": 23,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.CORE_PMA.C6_TRANSITION": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Counters": "0-3",
          "Desc": "Core PMA Events",
          "EvSel": 23,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.CORE_PMA.GV": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Counters": "0-3",
          "Desc": "Core PMA Events",
          "EvSel": 23,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.CORE_PMA.C1_TRANSITION": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Counters": "0-3",
          "Desc": "Core PMA Events",
          "EvSel": 23,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.CORE_PMA.C6_STATE": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Counters": "0-3",
          "Desc": "Core PMA Events",
          "EvSel": 23,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.CORE_SNP": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
     },
     "CHA.CORE_SNP.CORE_GTONE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b01000010",
     },
     "CHA.CORE_SNP.EVICT_REMOTE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b10000100",
     },
     "CHA.CORE_SNP.CORE_REMOTE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b01000100",
     },
     "CHA.CORE_SNP.EXT_REMOTE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b00100100",
     },
     "CHA.CORE_SNP.EXT_GTONE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b00100010",
     },
     "CHA.CORE_SNP.ANY_REMOTE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b11100100",
     },
     "CHA.CORE_SNP.EXT_ONE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b00100001",
     },
     "CHA.CORE_SNP.CORE_ONE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b01000001",
     },
     "CHA.CORE_SNP.EVICT_GTONE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b10000010",
     },
     "CHA.CORE_SNP.ANY_ONE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b11100001",
     },
     "CHA.CORE_SNP.ANY_GTONE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b11100010",
     },
     "CHA.CORE_SNP.EVICT_ONE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Defn": "Counts the number of transactions that trigger a configurable number of cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type and what CoreValid bits are set.  For example, if 2 CV bits are set on a data read, the cores must have the data in S state so it is not necessary to snoop them.  However, if only 1 CV bit is set the core my have modified the data.  If the transaction was an RFO, it would need to invalidate the lines.  This event can be filtered based on who triggered the initial snoop(s).",
          "Desc": "Core Cross Snoops Issued",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "b10000001",
     },
     "CHA.COUNTER0_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA OCCUPANCY Events",
          "Counters": "0-3",
          "Defn": "Since occupancy counts can only be captured in the Cbo's 0 counter, this event allows a user to capture occupancy related information by filtering the Cb0 occupancy count captured in Counter 0.   The filtering available is found in the control register - threshold, invert and edge detect.   E.g. setting threshold to 1 can effectively monitor how many cycles the monitored queue has an entry.",
          "Desc": "Counter 0 Occupancy",
          "EvSel": 31,
          "ExtSel": "",
     },
     "CHA.DIR_LOOKUP": {
          "Box": "CHA",
          "Category": "CHA HA DIRECTORY Events",
          "Defn": "Counts the number of transactions that looked up the Home Agent directory.  Can be filtered by requests that had to snoop and those that did not have to.",
          "Desc": "Directory Lookups",
          "EvSel": 83,
          "ExtSel": "",
          "Notes": "Only valid for parts that implement the Directory",
     },
     "CHA.DIR_LOOKUP.NO_SNP": {
          "Box": "CHA",
          "Category": "CHA HA DIRECTORY Events",
          "Defn": "Counts the number of transactions that looked up the Home Agent directory.  Can be filtered by requests that had to snoop and those that did not have to.",
          "Desc": "Directory Lookups",
          "EvSel": 83,
          "ExtSel": "",
          "Notes": "Only valid for parts that implement the Directory",
          "Umask": "bxxxxxx1x",
     },
     "CHA.DIR_LOOKUP.SNP": {
          "Box": "CHA",
          "Category": "CHA HA DIRECTORY Events",
          "Defn": "Counts the number of transactions that looked up the Home Agent directory.  Can be filtered by requests that had to snoop and those that did not have to.",
          "Desc": "Directory Lookups",
          "EvSel": 83,
          "ExtSel": "",
          "Notes": "Only valid for parts that implement the Directory",
          "Umask": "bxxxxxxx1",
     },
     "CHA.DIR_UPDATE": {
          "Box": "CHA",
          "Category": "CHA HA DIRECTORY Events",
          "Defn": "Counts the number of directory updates that were required.  These result in writes to the memory controller.",
          "Desc": "Directory Updates",
          "EvSel": 84,
          "ExtSel": "",
          "Notes": "Only valid for parts that implement the Directory.  Note that any directory update that's a part of an explicit (eviction or core/IO) or an implicit (snoop response) writeback is not counted.",
     },
     "CHA.DIR_UPDATE.TOR": {
          "Box": "CHA",
          "Category": "CHA HA DIRECTORY Events",
          "Defn": "Counts the number of directory updates that were required.  These result in writes to the memory controller.",
          "Desc": "Directory Updates",
          "EvSel": 84,
          "ExtSel": "",
          "Notes": "Only valid for parts that implement the Directory.  Note that any directory update that's a part of an explicit (eviction or core/IO) or an implicit (snoop response) writeback is not counted.",
          "Umask": "bxxxxxx1x",
     },
     "CHA.DIR_UPDATE.HA": {
          "Box": "CHA",
          "Category": "CHA HA DIRECTORY Events",
          "Defn": "Counts the number of directory updates that were required.  These result in writes to the memory controller.",
          "Desc": "Directory Updates",
          "EvSel": 84,
          "ExtSel": "",
          "Notes": "Only valid for parts that implement the Directory.  Note that any directory update that's a part of an explicit (eviction or core/IO) or an implicit (snoop response) writeback is not counted.",
          "Umask": "bxxxxxxx1",
     },
     "CHA.EGRESS_ORDERING": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
     },
     "CHA.EGRESS_ORDERING.IV_SNOOPGO_DN": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.EGRESS_ORDERING.IV_SNOOPGO_UP": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts number of cycles IV was blocked in the TGR Egress due to SNP/GO Ordering requirements",
          "Desc": "Egress Blocking due to Ordering requirements",
          "EvSel": 174,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.FAST_ASSERTED": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
     },
     "CHA.FAST_ASSERTED.HORZ": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "CHA.FAST_ASSERTED.VERT": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Defn": "Counts the number of cycles either the local or incoming distress signals are asserted.  Incoming distress includes up, dn and across.",
          "Desc": "FaST wire asserted",
          "EvSel": 165,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "CHA.HITME_HIT": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Hits in HitMe Cache",
          "EvSel": 95,
          "ExtSel": "",
     },
     "CHA.HITME_HIT.EX_RDS": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Hits in HitMe Cache",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.HITME_HIT.WBMTOI_OR_S": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Hits in HitMe Cache",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.HITME_HIT.SHARED_OWNREQ": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Hits in HitMe Cache",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.HITME_HIT.WBMTOE": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Hits in HitMe Cache",
          "EvSel": 95,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.HITME_LOOKUP": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of times HitMe Cache is accessed",
          "EvSel": 94,
          "ExtSel": "",
     },
     "CHA.HITME_LOOKUP.READ": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of times HitMe Cache is accessed",
          "EvSel": 94,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.HITME_LOOKUP.WRITE": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of times HitMe Cache is accessed",
          "EvSel": 94,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.HITME_MISS": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Misses in HitMe Cache",
          "EvSel": 96,
          "ExtSel": "",
     },
     "CHA.HITME_MISS.READ_OR_INV": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Misses in HitMe Cache",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.HITME_MISS.SHARED_RDINVOWN": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Misses in HitMe Cache",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.HITME_MISS.NOTSHARED_RDINVOWN": {
          "Box": "CHA",
          "Category": "CHA HA HitME Events",
          "Desc": "Counts Number of Misses in HitMe Cache",
          "EvSel": 96,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.HITME_UPDATE": {
          "Box": "CHA",
          "Category": "CHA HA HitME Pipe Events",
          "Desc": "Counts the number of Allocate/Update to HitMe Cache",
          "EvSel": 97,
          "ExtSel": "",
     },
     "CHA.HITME_UPDATE.DEALLOCATE": {
          "Box": "CHA",
          "Category": "CHA HA HitME Pipe Events",
          "Desc": "Counts the number of Allocate/Update to HitMe Cache",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.HITME_UPDATE.SHARED": {
          "Box": "CHA",
          "Category": "CHA HA HitME Pipe Events",
          "Desc": "Counts the number of Allocate/Update to HitMe Cache",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.HITME_UPDATE.RSPFWDI_REM": {
          "Box": "CHA",
          "Category": "CHA HA HitME Pipe Events",
          "Desc": "Counts the number of Allocate/Update to HitMe Cache",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.HITME_UPDATE.DEALLOCATE_RSPFWDI_LOC": {
          "Box": "CHA",
          "Category": "CHA HA HitME Pipe Events",
          "Desc": "Counts the number of Allocate/Update to HitMe Cache",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.HITME_UPDATE.RDINVOWN": {
          "Box": "CHA",
          "Category": "CHA HA HitME Pipe Events",
          "Desc": "Counts the number of Allocate/Update to HitMe Cache",
          "EvSel": 97,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.HORZ_RING_AD_IN_USE": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
     },
     "CHA.HORZ_RING_AD_IN_USE.LEFT_EVEN": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.HORZ_RING_AD_IN_USE.RIGHT_ODD": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.HORZ_RING_AD_IN_USE.RIGHT_EVEN": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.HORZ_RING_AD_IN_USE.LEFT_ODD": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AD Ring In Use",
          "EvSel": 167,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.HORZ_RING_AK_IN_USE": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
     },
     "CHA.HORZ_RING_AK_IN_USE.RIGHT_EVEN": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.HORZ_RING_AK_IN_USE.LEFT_ODD": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.HORZ_RING_AK_IN_USE.LEFT_EVEN": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.HORZ_RING_AK_IN_USE.RIGHT_ODD": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal AK Ring In Use",
          "EvSel": 169,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.HORZ_RING_BL_IN_USE": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
     },
     "CHA.HORZ_RING_BL_IN_USE.LEFT_ODD": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.HORZ_RING_BL_IN_USE.RIGHT_EVEN": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.HORZ_RING_BL_IN_USE.RIGHT_ODD": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.HORZ_RING_BL_IN_USE.LEFT_EVEN": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Horizontal BL Ring in Use",
          "EvSel": 171,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.HORZ_RING_IV_IN_USE": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
     },
     "CHA.HORZ_RING_IV_IN_USE.RIGHT": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.HORZ_RING_IV_IN_USE.LEFT": {
          "Box": "CHA",
          "Category": "CHA Horizontal In Use RING Events",
          "Defn": "Counts the number of cycles that the Horizontal IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Horizontal IV Ring in Use",
          "EvSel": 173,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.IMC_READS_COUNT": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
          "Desc": "HA to iMC Reads Issued",
          "EvSel": 89,
          "ExtSel": "",
          "Notes": "To match the number of reads seen at the IMC, it's necessary to account for any bypasses.   IMC_READS_COUNT.* + BYPASS_CHA_IMC.TAKEN == CAS_COUNT.RD",
     },
     "CHA.IMC_READS_COUNT.PRIORITY": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
          "Desc": "HA to iMC Reads Issued",
          "EvSel": 89,
          "ExtSel": "",
          "Notes": "To match the number of reads seen at the IMC, it's necessary to account for any bypasses.   IMC_READS_COUNT.* + BYPASS_CHA_IMC.TAKEN == CAS_COUNT.RD",
          "Umask": "bxxxxxx1x",
     },
     "CHA.IMC_READS_COUNT.NORMAL": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Count of the number of reads issued to any of the memory controller channels.  This can be filtered by the priority of the reads.",
          "Desc": "HA to iMC Reads Issued",
          "EvSel": 89,
          "ExtSel": "",
          "Notes": "To match the number of reads seen at the IMC, it's necessary to account for any bypasses.   IMC_READS_COUNT.* + BYPASS_CHA_IMC.TAKEN == CAS_COUNT.RD",
          "Umask": "bxxxxxxx1",
     },
     "CHA.IMC_WRITES_COUNT": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
          "Desc": "Writes Issued to the iMC by the HA",
          "EvSel": 91,
          "ExtSel": "",
          "Notes": "Directory bits are stored in memory.   Remote socket RFOs will result in a directory update which, in turn, will cause a write command.",
     },
     "CHA.IMC_WRITES_COUNT.FULL_PRIORITY": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
          "Desc": "Writes Issued to the iMC by the HA",
          "EvSel": 91,
          "ExtSel": "",
          "Notes": "Directory bits are stored in memory.   Remote socket RFOs will result in a directory update which, in turn, will cause a write command.",
          "Umask": "bxxxxx1xx",
     },
     "CHA.IMC_WRITES_COUNT.PARTIAL_MIG": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
          "Desc": "Writes Issued to the iMC by the HA",
          "EvSel": 91,
          "ExtSel": "",
          "Notes": "Directory bits are stored in memory.   Remote socket RFOs will result in a directory update which, in turn, will cause a write command.",
          "Umask": "bxx1xxxxx",
     },
     "CHA.IMC_WRITES_COUNT.FULL_MIG": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
          "Desc": "Writes Issued to the iMC by the HA",
          "EvSel": 91,
          "ExtSel": "",
          "Notes": "Directory bits are stored in memory.   Remote socket RFOs will result in a directory update which, in turn, will cause a write command.",
          "Umask": "bxxx1xxxx",
     },
     "CHA.IMC_WRITES_COUNT.FULL": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
          "Desc": "Writes Issued to the iMC by the HA",
          "EvSel": 91,
          "ExtSel": "",
          "Notes": "Directory bits are stored in memory.   Remote socket RFOs will result in a directory update which, in turn, will cause a write command.",
          "Umask": "bxxxxxxx1",
     },
     "CHA.IMC_WRITES_COUNT.PARTIAL_PRIORITY": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
          "Desc": "Writes Issued to the iMC by the HA",
          "EvSel": 91,
          "ExtSel": "",
          "Notes": "Directory bits are stored in memory.   Remote socket RFOs will result in a directory update which, in turn, will cause a write command.",
          "Umask": "bxxxx1xxx",
     },
     "CHA.IMC_WRITES_COUNT.PARTIAL": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the total number of writes issued from the HA into the memory controller.  This counts for all four channels.  It can be filtered by full/partial and ISOCH/non-ISOCH.",
          "Desc": "Writes Issued to the iMC by the HA",
          "EvSel": 91,
          "ExtSel": "",
          "Notes": "Directory bits are stored in memory.   Remote socket RFOs will result in a directory update which, in turn, will cause a write command.",
          "Umask": "bxxxxxx1x",
     },
     "CHA.IODC_ALLOC": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts Number of times IODC entry allocation is attempted",
          "EvSel": 98,
          "ExtSel": "",
     },
     "CHA.IODC_ALLOC.IODCFULL": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts Number of times IODC entry allocation is attempted",
          "EvSel": 98,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.IODC_ALLOC.OSBGATED": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts Number of times IODC entry allocation is attempted",
          "EvSel": 98,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.IODC_ALLOC.INVITOM": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts Number of times IODC entry allocation is attempted",
          "EvSel": 98,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.IODC_DEALLOC": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts number of IODC deallocations",
          "EvSel": 99,
          "ExtSel": "",
     },
     "CHA.IODC_DEALLOC.WBMTOI": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts number of IODC deallocations",
          "EvSel": 99,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.IODC_DEALLOC.WBPUSHMTOI": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts number of IODC deallocations",
          "EvSel": 99,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.IODC_DEALLOC.SNPOUT": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts number of IODC deallocations",
          "EvSel": 99,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.IODC_DEALLOC.ALL": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts number of IODC deallocations",
          "EvSel": 99,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.IODC_DEALLOC.WBMTOE": {
          "Box": "CHA",
          "Category": "CHA HA IODC Events",
          "Desc": "Counts number of IODC deallocations",
          "EvSel": 99,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.LLC_LOOKUP": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
          "Desc": "Cache and Snoop Filter Lookups",
          "EvSel": 52,
          "ExtSel": "",
          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match against a given state (or states) as programmed in the Cn_MSR_PMON_BOX_FILTER0.state field bitmask.    0 = I (miss), 4 = S, 5 = E, 6 = M, 7 = F.  For example, if you wanted to monitor F and S hits, you could set 00001001b in the 8-bit state field.   To monitor any lookup, set the field to 0x1F.  Extra note - it may be a little confusing for customers of earlier products.  With the CBo and HA functionality combined, it's possible to also measure Snoop Filter lookups with bits 1-3 of the FILTER0.state field",
     },
     "CHA.LLC_LOOKUP.REMOTE_SNOOP": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
          "Desc": "Cache and Snoop Filter Lookups",
          "EvSel": 52,
          "ExtSel": "",
          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match against a given state (or states) as programmed in the Cn_MSR_PMON_BOX_FILTER0.state field bitmask.    0 = I (miss), 4 = S, 5 = E, 6 = M, 7 = F.  For example, if you wanted to monitor F and S hits, you could set 00001001b in the 8-bit state field.   To monitor any lookup, set the field to 0x1F.  Extra note - it may be a little confusing for customers of earlier products.  With the CBo and HA functionality combined, it's possible to also measure Snoop Filter lookups with bits 1-3 of the FILTER0.state field",
          "Umask": "b00001001",
     },
     "CHA.LLC_LOOKUP.LOCAL": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
          "Desc": "Cache and Snoop Filter Lookups",
          "EvSel": 52,
          "ExtSel": "",
          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match against a given state (or states) as programmed in the Cn_MSR_PMON_BOX_FILTER0.state field bitmask.    0 = I (miss), 4 = S, 5 = E, 6 = M, 7 = F.  For example, if you wanted to monitor F and S hits, you could set 00001001b in the 8-bit state field.   To monitor any lookup, set the field to 0x1F.  Extra note - it may be a little confusing for customers of earlier products.  With the CBo and HA functionality combined, it's possible to also measure Snoop Filter lookups with bits 1-3 of the FILTER0.state field",
          "Umask": "b00110001",
     },
     "CHA.LLC_LOOKUP.REMOTE": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
          "Desc": "Cache and Snoop Filter Lookups",
          "EvSel": 52,
          "ExtSel": "",
          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match against a given state (or states) as programmed in the Cn_MSR_PMON_BOX_FILTER0.state field bitmask.    0 = I (miss), 4 = S, 5 = E, 6 = M, 7 = F.  For example, if you wanted to monitor F and S hits, you could set 00001001b in the 8-bit state field.   To monitor any lookup, set the field to 0x1F.  Extra note - it may be a little confusing for customers of earlier products.  With the CBo and HA functionality combined, it's possible to also measure Snoop Filter lookups with bits 1-3 of the FILTER0.state field",
          "Umask": "b10010001",
     },
     "CHA.LLC_LOOKUP.DATA_READ": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
          "Desc": "Cache and Snoop Filter Lookups",
          "EvSel": 52,
          "ExtSel": "",
          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match against a given state (or states) as programmed in the Cn_MSR_PMON_BOX_FILTER0.state field bitmask.    0 = I (miss), 4 = S, 5 = E, 6 = M, 7 = F.  For example, if you wanted to monitor F and S hits, you could set 00001001b in the 8-bit state field.   To monitor any lookup, set the field to 0x1F.  Extra note - it may be a little confusing for customers of earlier products.  With the CBo and HA functionality combined, it's possible to also measure Snoop Filter lookups with bits 1-3 of the FILTER0.state field",
          "Umask": "b00000011",
     },
     "CHA.LLC_LOOKUP.ANY": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
          "Desc": "Cache and Snoop Filter Lookups",
          "EvSel": 52,
          "ExtSel": "",
          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match against a given state (or states) as programmed in the Cn_MSR_PMON_BOX_FILTER0.state field bitmask.    0 = I (miss), 4 = S, 5 = E, 6 = M, 7 = F.  For example, if you wanted to monitor F and S hits, you could set 00001001b in the 8-bit state field.   To monitor any lookup, set the field to 0x1F.  Extra note - it may be a little confusing for customers of earlier products.  With the CBo and HA functionality combined, it's possible to also measure Snoop Filter lookups with bits 1-3 of the FILTER0.state field",
          "Umask": "b00010001",
     },
     "CHA.LLC_LOOKUP.WRITE": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times the LLC was accessed - this includes code, data, prefetches and hints coming from L2.  This has numerous filters available.  Note the non-standard filtering equation.  This event will count requests that lookup the cache multiple times with multiple increments.  One must ALWAYS set umask bit 0 and select a state or states to match.  Otherwise, the event will count nothing.   CHAFilter0[24:21,17] bits correspond to [FMESI] state.",
          "Desc": "Cache and Snoop Filter Lookups",
          "EvSel": 52,
          "ExtSel": "",
          "Notes": "Bit 0 of the umask must always be set for this event.  This allows us to match against a given state (or states) as programmed in the Cn_MSR_PMON_BOX_FILTER0.state field bitmask.    0 = I (miss), 4 = S, 5 = E, 6 = M, 7 = F.  For example, if you wanted to monitor F and S hits, you could set 00001001b in the 8-bit state field.   To monitor any lookup, set the field to 0x1F.  Extra note - it may be a little confusing for customers of earlier products.  With the CBo and HA functionality combined, it's possible to also measure Snoop Filter lookups with bits 1-3 of the FILTER0.state field",
          "Umask": "b00000101",
     },
     "CHA.LLC_VICTIMS": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
     },
     "CHA.LLC_VICTIMS.LOCAL_F": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b00101000",
     },
     "CHA.LLC_VICTIMS.LOCAL_M": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b00100001",
     },
     "CHA.LLC_VICTIMS.REMOTE_S": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10000100",
     },
     "CHA.LLC_VICTIMS.LOCAL_E": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b00100010",
     },
     "CHA.LLC_VICTIMS.LOCAL_S": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b00100100",
     },
     "CHA.LLC_VICTIMS.REMOTE_M": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10000001",
     },
     "CHA.LLC_VICTIMS.TOTAL_E": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10100010",
     },
     "CHA.LLC_VICTIMS.REMOTE_ALL": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10001111",
     },
     "CHA.LLC_VICTIMS.TOTAL_M": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10100001",
     },
     "CHA.LLC_VICTIMS.TOTAL_S": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10100100",
     },
     "CHA.LLC_VICTIMS.REMOTE_E": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10000010",
     },
     "CHA.LLC_VICTIMS.LOCAL_ALL": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b00101111",
     },
     "CHA.LLC_VICTIMS.TOTAL_F": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10101000",
     },
     "CHA.LLC_VICTIMS.REMOTE_F": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of lines that were victimized on a fill.  This can be filtered by the state that the line was in.",
          "Desc": "Lines Victimized",
          "EvSel": 55,
          "ExtSel": "",
          "Notes": "Does not include evict cleans",
          "Umask": "b10001000",
     },
     "CHA.MISC": {
          "Box": "CHA",
          "Category": "CHA MISC Events",
          "Counters": "0-3",
          "Defn": "Miscellaneous events in the Cbo.",
          "Desc": "Cbo Misc",
          "EvSel": 57,
          "ExtSel": "",
     },
     "CHA.MISC.CV0_PREF_MISS": {
          "Box": "CHA",
          "Category": "CHA MISC Events",
          "Counters": "0-3",
          "Defn": "Miscellaneous events in the Cbo.",
          "Desc": "Cbo Misc",
          "EvSel": 57,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.MISC.WC_ALIASING": {
          "Box": "CHA",
          "Category": "CHA MISC Events",
          "Counters": "0-3",
          "Defn": "Miscellaneous events in the Cbo.",
          "Desc": "Cbo Misc",
          "EvSel": 57,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.MISC.RFO_HIT_S": {
          "Box": "CHA",
          "Category": "CHA MISC Events",
          "Counters": "0-3",
          "Defn": "Miscellaneous events in the Cbo.",
          "Desc": "Cbo Misc",
          "EvSel": 57,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.MISC.RSPI_WAS_FSE": {
          "Box": "CHA",
          "Category": "CHA MISC Events",
          "Counters": "0-3",
          "Defn": "Miscellaneous events in the Cbo.",
          "Desc": "Cbo Misc",
          "EvSel": 57,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.MISC.CV0_PREF_VIC": {
          "Box": "CHA",
          "Category": "CHA MISC Events",
          "Counters": "0-3",
          "Defn": "Miscellaneous events in the Cbo.",
          "Desc": "Cbo Misc",
          "EvSel": 57,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.OSB": {
          "Box": "CHA",
          "Category": "CHA HA OSB Events",
          "Defn": "Count of OSB snoop broadcasts. Counts by 1 per request causing OSB snoops to be broadcast. Does not count all the snoops generated by OSB.",
          "Desc": "OSB Snoop Broadcast",
          "EvSel": 85,
          "ExtSel": "",
     },
     "CHA.READ_NO_CREDITS": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.",
          "Desc": "CHA iMC CHNx READ Credits Empty",
          "EvSel": 88,
          "ExtSel": "",
     },
     "CHA.READ_NO_CREDITS.EDC1_SMI3": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.",
          "Desc": "CHA iMC CHNx READ Credits Empty",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.READ_NO_CREDITS.EDC3_SMI5": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.",
          "Desc": "CHA iMC CHNx READ Credits Empty",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.READ_NO_CREDITS.MC0_SMI0": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.",
          "Desc": "CHA iMC CHNx READ Credits Empty",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.READ_NO_CREDITS.EDC0_SMI2": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.",
          "Desc": "CHA iMC CHNx READ Credits Empty",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.READ_NO_CREDITS.EDC2_SMI4": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.",
          "Desc": "CHA iMC CHNx READ Credits Empty",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.READ_NO_CREDITS.MC1_SMI1": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending reads from the CHA into the iMC.  In order to send reads into the memory controller, the HA must first acquire a credit for the iMC's AD Ingress queue.",
          "Desc": "CHA iMC CHNx READ Credits Empty",
          "EvSel": 88,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.REQUESTS": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
     },
     "CHA.REQUESTS.INVITOE_LOCAL": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.REQUESTS.READS": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "b00000011",
     },
     "CHA.REQUESTS.READS_REMOTE": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.REQUESTS.WRITES_REMOTE": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.REQUESTS.READS_LOCAL": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.REQUESTS.WRITES": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "b00001100",
     },
     "CHA.REQUESTS.WRITES_LOCAL": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.REQUESTS.INVITOE_REMOTE": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of read requests made into the Home Agent. Reads include all read opcodes (including RFO).  Writes include all writes (streaming, evictions, HitM, etc).",
          "Desc": "Read and Write Requests",
          "EvSel": 80,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RING_BOUNCES_HORZ": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
     },
     "CHA.RING_BOUNCES_HORZ.AK": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RING_BOUNCES_HORZ.BL": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RING_BOUNCES_HORZ.AD": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RING_BOUNCES_HORZ.IV": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Defn": "Number of cycles incoming messages from the Horizontal ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Horizontal Ring.",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RING_BOUNCES_VERT": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
     },
     "CHA.RING_BOUNCES_VERT.IV": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RING_BOUNCES_VERT.BL": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RING_BOUNCES_VERT.AD": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RING_BOUNCES_VERT.AK": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Defn": "Number of cycles incoming messages from the Vertical ring that were bounced, by ring type.",
          "Desc": "Messages that bounced on the Vertical Ring.",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RING_SINK_STARVED_HORZ": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
     },
     "CHA.RING_SINK_STARVED_HORZ.AK": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RING_SINK_STARVED_HORZ.BL": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RING_SINK_STARVED_HORZ.AD": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RING_SINK_STARVED_HORZ.IV": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RING_SINK_STARVED_HORZ.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Desc": "Sink Starvation on Horizontal Ring",
          "EvSel": 163,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RING_SINK_STARVED_VERT": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
     },
     "CHA.RING_SINK_STARVED_VERT.IV": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RING_SINK_STARVED_VERT.AK": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RING_SINK_STARVED_VERT.BL": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RING_SINK_STARVED_VERT.AD": {
          "Box": "CHA",
          "Category": "CHA Vertical RING Events",
          "Desc": "Sink Starvation on Vertical Ring",
          "EvSel": 162,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RING_SRC_THRTL": {
          "Box": "CHA",
          "Category": "CHA Horizontal  RING Events",
          "Desc": "Source Throttle",
          "EvSel": 164,
          "ExtSel": "",
     },
     "CHA.RxC_INSERTS": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": "0-3",
          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
          "Desc": "Ingress (from CMS) Allocations",
          "EvSel": 19,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
     },
     "CHA.RxC_INSERTS.RRQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": "0-3",
          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
          "Desc": "Ingress (from CMS) Allocations",
          "EvSel": 19,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_INSERTS.IRQ_REJ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": "0-3",
          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
          "Desc": "Ingress (from CMS) Allocations",
          "EvSel": 19,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_INSERTS.IPQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": "0-3",
          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
          "Desc": "Ingress (from CMS) Allocations",
          "EvSel": 19,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_INSERTS.WBQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": "0-3",
          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
          "Desc": "Ingress (from CMS) Allocations",
          "EvSel": 19,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_INSERTS.IRQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": "0-3",
          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
          "Desc": "Ingress (from CMS) Allocations",
          "EvSel": 19,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_INSERTS.PRQ_REJ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": "0-3",
          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
          "Desc": "Ingress (from CMS) Allocations",
          "EvSel": 19,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_INSERTS.PRQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": "0-3",
          "Defn": "Counts number of allocations per cycle into the specified Ingress queue.",
          "Desc": "Ingress (from CMS) Allocations",
          "EvSel": 19,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_IPQ0_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
     },
     "CHA.RxC_IPQ0_REJECT.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_IPQ0_REJECT.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_IPQ0_REJECT.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_IPQ0_REJECT.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_IPQ0_REJECT.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_IPQ0_REJECT.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_IPQ0_REJECT.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_IPQ0_REJECT.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 34,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_IPQ1_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
     },
     "CHA.RxC_IPQ1_REJECT.LLC_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_IPQ1_REJECT.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_IPQ1_REJECT.PA_MATCH": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_IPQ1_REJECT.VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_IPQ1_REJECT.ALLOW_SNP": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_IPQ1_REJECT.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_IPQ1_REJECT.LLC_OR_SF_WAY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_IPQ1_REJECT.SF_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress Probe Queue Rejects",
          "EvSel": 35,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_IRQ0_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
     },
     "CHA.RxC_IRQ0_REJECT.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_IRQ0_REJECT.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_IRQ0_REJECT.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_IRQ0_REJECT.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_IRQ0_REJECT.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_IRQ0_REJECT.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_IRQ0_REJECT.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_IRQ0_REJECT.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_IRQ1_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
     },
     "CHA.RxC_IRQ1_REJECT.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_IRQ1_REJECT.VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_IRQ1_REJECT.ALLOW_SNP": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_IRQ1_REJECT.SF_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_IRQ1_REJECT.LLC_OR_SF_WAY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_IRQ1_REJECT.LLC_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_IRQ1_REJECT.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_IRQ1_REJECT.PA_MATCH": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 25,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_ISMQ0_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
     },
     "CHA.RxC_ISMQ0_REJECT.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_ISMQ0_REJECT.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_ISMQ0_REJECT.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_ISMQ0_REJECT.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_ISMQ0_REJECT.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_ISMQ0_REJECT.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_ISMQ0_REJECT.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_ISMQ0_REJECT.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 36,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_ISMQ0_RETRY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
     },
     "CHA.RxC_ISMQ0_RETRY.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_ISMQ0_RETRY.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_ISMQ0_RETRY.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_ISMQ0_RETRY.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_ISMQ0_RETRY.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_ISMQ0_RETRY.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_ISMQ0_RETRY.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_ISMQ0_RETRY.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 44,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_ISMQ1_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 37,
          "ExtSel": "",
     },
     "CHA.RxC_ISMQ1_REJECT.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 37,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_ISMQ1_REJECT.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Rejects",
          "EvSel": 37,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_ISMQ1_RETRY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 45,
          "ExtSel": "",
     },
     "CHA.RxC_ISMQ1_RETRY.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_ISMQ1_RETRY.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the ISMQ had to retry.  Transaction pass through the ISMQ as responses for requests that already exist in the Cbo.  Some examples include: when data is returned or when snoop responses come back from the cores.",
          "Desc": "ISMQ Retries",
          "EvSel": 45,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": 0,
          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
          "Desc": "Ingress (from CMS) Occupancy",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
     },
     "CHA.RxC_OCCUPANCY.WBQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": 0,
          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
          "Desc": "Ingress (from CMS) Occupancy",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "b10000000",
     },
     "CHA.RxC_OCCUPANCY.IRQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": 0,
          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
          "Desc": "Ingress (from CMS) Occupancy",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "b00000001",
     },
     "CHA.RxC_OCCUPANCY.IPQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": 0,
          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
          "Desc": "Ingress (from CMS) Occupancy",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "b00000100",
     },
     "CHA.RxC_OCCUPANCY.RRQ": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Counters": 0,
          "Defn": "Counts number of entries in the specified Ingress queue in each cycle.",
          "Desc": "Ingress (from CMS) Occupancy",
          "EvSel": 17,
          "ExtSel": "",
          "Notes": "IRQ_REJECTED should not be Ored with the other umasks.",
          "Umask": "b01000000",
     },
     "CHA.RxC_OTHER0_RETRY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
     },
     "CHA.RxC_OTHER0_RETRY.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_OTHER0_RETRY.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_OTHER0_RETRY.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_OTHER0_RETRY.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_OTHER0_RETRY.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_OTHER0_RETRY.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_OTHER0_RETRY.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_OTHER0_RETRY.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 46,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_OTHER1_RETRY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
     },
     "CHA.RxC_OTHER1_RETRY.LLC_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_OTHER1_RETRY.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_OTHER1_RETRY.PA_MATCH": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_OTHER1_RETRY.VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_OTHER1_RETRY.ALLOW_SNP": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_OTHER1_RETRY.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_OTHER1_RETRY.LLC_OR_SF_WAY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_OTHER1_RETRY.SF_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Retry Queue Inserts of Transactions that were already in another Retry Q (sub-events encode the reason for the next reject)",
          "Desc": "Other Retries",
          "EvSel": 47,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_PRQ0_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
     },
     "CHA.RxC_PRQ0_REJECT.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_PRQ0_REJECT.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_PRQ0_REJECT.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_PRQ0_REJECT.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_PRQ0_REJECT.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_PRQ0_REJECT.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_PRQ0_REJECT.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_PRQ0_REJECT.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 32,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_PRQ1_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
     },
     "CHA.RxC_PRQ1_REJECT.PA_MATCH": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_PRQ1_REJECT.LLC_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_PRQ1_REJECT.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_PRQ1_REJECT.LLC_OR_SF_WAY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_PRQ1_REJECT.SF_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_PRQ1_REJECT.ALLOW_SNP": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_PRQ1_REJECT.VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_PRQ1_REJECT.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Desc": "Ingress (from CMS) Request Queue Rejects",
          "EvSel": 33,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_REQ_Q0_RETRY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
     },
     "CHA.RxC_REQ_Q0_RETRY.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_REQ_Q0_RETRY.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_REQ_Q0_RETRY.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_REQ_Q0_RETRY.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_REQ_Q0_RETRY.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_REQ_Q0_RETRY.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_REQ_Q0_RETRY.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_REQ_Q0_RETRY.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_REQ_Q1_RETRY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
     },
     "CHA.RxC_REQ_Q1_RETRY.PA_MATCH": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_REQ_Q1_RETRY.LLC_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_REQ_Q1_RETRY.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_REQ_Q1_RETRY.SF_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_REQ_Q1_RETRY.LLC_OR_SF_WAY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_REQ_Q1_RETRY.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_REQ_Q1_RETRY.ALLOW_SNP": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_REQ_Q1_RETRY.VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "\"REQUESTQ\" includes:  IRQ, PRQ, IPQ, RRQ, WBQ (everything except for ISMQ)",
          "Desc": "Request Queue Retries",
          "EvSel": 43,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_RRQ0_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
     },
     "CHA.RxC_RRQ0_REJECT.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_RRQ0_REJECT.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_RRQ0_REJECT.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_RRQ0_REJECT.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_RRQ0_REJECT.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_RRQ0_REJECT.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_RRQ0_REJECT.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_RRQ0_REJECT.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 38,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_RRQ1_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
     },
     "CHA.RxC_RRQ1_REJECT.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_RRQ1_REJECT.LLC_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_RRQ1_REJECT.PA_MATCH": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_RRQ1_REJECT.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_RRQ1_REJECT.ALLOW_SNP": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_RRQ1_REJECT.VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_RRQ1_REJECT.SF_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_RRQ1_REJECT.LLC_OR_SF_WAY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the RRQ (Remote Response Queue) had to retry.",
          "Desc": "RRQ Rejects",
          "EvSel": 39,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_WBQ0_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
     },
     "CHA.RxC_WBQ0_REJECT.AK_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxC_WBQ0_REJECT.IV_NON_UPI": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_WBQ0_REJECT.BL_NCB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_WBQ0_REJECT.BL_NCS_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_WBQ0_REJECT.BL_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_WBQ0_REJECT.AD_RSP_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_WBQ0_REJECT.AD_REQ_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_WBQ0_REJECT.BL_WB_VN0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 40,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_WBQ1_REJECT": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
     },
     "CHA.RxC_WBQ1_REJECT.PA_MATCH": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxC_WBQ1_REJECT.LLC_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxC_WBQ1_REJECT.HA": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxC_WBQ1_REJECT.SF_VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxC_WBQ1_REJECT.LLC_OR_SF_WAY": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.RxC_WBQ1_REJECT.ANY0": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxC_WBQ1_REJECT.VICTIM": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxC_WBQ1_REJECT.ALLOW_SNP": {
          "Box": "CHA",
          "Category": "CHA INGRESS_RETRY Events",
          "Defn": "Number of times a transaction flowing through the WBQ (Writeback Queue) had to retry.",
          "Desc": "WBQ Rejects",
          "EvSel": 41,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxR_BUSY_STARVED": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
     },
     "CHA.RxR_BUSY_STARVED.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxR_BUSY_STARVED.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxR_BUSY_STARVED.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxR_BUSY_STARVED.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, because a message from the other queue has higher priority",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 180,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxR_BYPASS": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "CHA.RxR_BYPASS.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxR_BYPASS.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxR_BYPASS.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxR_BYPASS.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxR_BYPASS.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxR_BYPASS.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of packets bypassing the CMS Ingress",
          "Desc": "Transgress Ingress Bypass",
          "EvSel": 178,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxR_CRD_STARVED": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
     },
     "CHA.RxR_CRD_STARVED.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxR_CRD_STARVED.IFV": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "b1xxxxxxx",
     },
     "CHA.RxR_CRD_STARVED.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxR_CRD_STARVED.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxR_CRD_STARVED.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxR_CRD_STARVED.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxR_CRD_STARVED.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Counts cycles under injection starvation mode.  This starvation is triggered when the CMS Ingress cannot send a transaction onto the mesh for a long period of time.  In this case, the Ingress is unable to forward to the Egress due to a lack of credit.",
          "Desc": "Transgress Injection Starvation",
          "EvSel": 179,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the OR of the two. For this purpose IFV is considered an AK ring type. Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxR_INSERTS": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "CHA.RxR_INSERTS.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "CHA.RxR_INSERTS.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxR_INSERTS.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxR_INSERTS.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxR_INSERTS.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxR_INSERTS.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Number of allocations into the CMS Ingress  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Allocations",
          "EvSel": 177,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxR_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
     },
     "CHA.RxR_OCCUPANCY.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxx1xxxx",
     },
     "CHA.RxR_OCCUPANCY.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bx1xxxxxx",
     },
     "CHA.RxR_OCCUPANCY.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxx1xxx",
     },
     "CHA.RxR_OCCUPANCY.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxx1x",
     },
     "CHA.RxR_OCCUPANCY.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxxxx1",
     },
     "CHA.RxR_OCCUPANCY.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress INGRESS Events",
          "Defn": "Occupancy event for the Ingress buffers in the CMS  The Ingress is used to queue up requests received from the mesh",
          "Desc": "Transgress Ingress Occupancy",
          "EvSel": 176,
          "ExtSel": "",
          "Notes": "If both masks are selected for one ring type (ex: AD CRD + BNC), will count the SUM of the two.  Selecting multiple ring types NOT supported",
          "Umask": "bxxxxx1xx",
     },
     "CHA.SF_EVICTION": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Desc": "Snoop Filter Eviction",
          "EvSel": 61,
          "ExtSel": "",
     },
     "CHA.SF_EVICTION.S_STATE": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Desc": "Snoop Filter Eviction",
          "EvSel": 61,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.SF_EVICTION.M_STATE": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Desc": "Snoop Filter Eviction",
          "EvSel": 61,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.SF_EVICTION.E_STATE": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Desc": "Snoop Filter Eviction",
          "EvSel": 61,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.SNOOPS_SENT": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Counts the number of snoops issued by the HA.",
          "Desc": "Snoops Sent",
          "EvSel": 81,
          "ExtSel": "",
     },
     "CHA.SNOOPS_SENT.LOCAL": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Counts the number of snoops issued by the HA.",
          "Desc": "Snoops Sent",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.SNOOPS_SENT.BCST_REMOTE": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Counts the number of snoops issued by the HA.",
          "Desc": "Snoops Sent",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.SNOOPS_SENT.REMOTE": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Counts the number of snoops issued by the HA.",
          "Desc": "Snoops Sent",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.SNOOPS_SENT.ALL": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Counts the number of snoops issued by the HA.",
          "Desc": "Snoops Sent",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.SNOOPS_SENT.DIRECT_LOCAL": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Counts the number of snoops issued by the HA.",
          "Desc": "Snoops Sent",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.SNOOPS_SENT.DIRECT_REMOTE": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Counts the number of snoops issued by the HA.",
          "Desc": "Snoops Sent",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.SNOOPS_SENT.BCST_LOCAL": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Counts the number of snoops issued by the HA.",
          "Desc": "Snoops Sent",
          "EvSel": 81,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.SNOOP_RESP": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
     },
     "CHA.SNOOP_RESP.RSPI": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.SNOOP_RESP.RSP_WBWB": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.SNOOP_RESP.RSPIFWD": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.SNOOP_RESP.RSPFWD": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.SNOOP_RESP.RSP_FWD_WB": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.SNOOP_RESP.RSPS": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.SNOOP_RESP.RSPSFWD": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.SNOOP_RESP.RSPCNFLCTS": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Counts the total number of RspI snoop responses received.  Whenever a snoops are issued, one or more snoop responses will be returned depending on the topology of the system.   In systems larger than 2s, when multiple snoops are returned this will count all the snoops that are received.  For example, if 3 snoops were issued and returned RspI, RspS, and RspSFwd; then each of these sub-events would increment by 1.",
          "Desc": "Snoop Responses Received",
          "EvSel": 92,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.SNOOP_RESP_LOCAL": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Number of snoop responses received for a Local  request",
          "Desc": "Snoop Responses Received Local",
          "EvSel": 93,
          "ExtSel": "",
     },
     "CHA.SNOOP_RESP_LOCAL.RSPSFWD": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Number of snoop responses received for a Local  request",
          "Desc": "Snoop Responses Received Local",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.SNOOP_RESP_LOCAL.RSPIFWD": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Number of snoop responses received for a Local  request",
          "Desc": "Snoop Responses Received Local",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.SNOOP_RESP_LOCAL.RSPFWD": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Number of snoop responses received for a Local  request",
          "Desc": "Snoop Responses Received Local",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "CHA.SNOOP_RESP_LOCAL.RSP_WB": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Number of snoop responses received for a Local  request",
          "Desc": "Snoop Responses Received Local",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.SNOOP_RESP_LOCAL.RSP_FWD_WB": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Number of snoop responses received for a Local  request",
          "Desc": "Snoop Responses Received Local",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.SNOOP_RESP_LOCAL.RSPI": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Number of snoop responses received for a Local  request",
          "Desc": "Snoop Responses Received Local",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.SNOOP_RESP_LOCAL.RSPS": {
          "Box": "CHA",
          "Category": "CHA HA SNOOP RESPONSE Events",
          "Defn": "Number of snoop responses received for a Local  request",
          "Desc": "Snoop Responses Received Local",
          "EvSel": 93,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG0.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent0 Transgress Credits",
          "EvSel": 208,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_AD_AG1.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the AD Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No AD Agent1 Transgress Credits",
          "EvSel": 210,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG0.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 0 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent0 Transgress Credits",
          "EvSel": 212,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR3": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR4": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR0": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR2": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR5": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.STALL_NO_TxR_HORZ_CRD_BL_AG1.TGR1": {
          "Box": "CHA",
          "Category": "CHA CMS Transgress Credit Events",
          "Defn": "Number of cycles the BL Agent 1 Egress Buffer is stalled waiting for a TGR credit to become available, per transgress.",
          "Desc": "Stall on No BL Agent1 Transgress Credits",
          "EvSel": 214,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TOR_INSERTS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
     },
     "CHA.TOR_INSERTS.EVICT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TOR_INSERTS.IO_MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00100100",
     },
     "CHA.TOR_INSERTS.ALL_MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00100101",
     },
     "CHA.TOR_INSERTS.IA": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00110001",
     },
     "CHA.TOR_INSERTS.IPQ": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TOR_INSERTS.HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TOR_INSERTS.IA_HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00010001",
     },
     "CHA.TOR_INSERTS.IO": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00110100",
     },
     "CHA.TOR_INSERTS.IA_MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00100001",
     },
     "CHA.TOR_INSERTS.IO_HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00010100",
     },
     "CHA.TOR_INSERTS.MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TOR_INSERTS.ALL_HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00010101",
     },
     "CHA.TOR_INSERTS.IRQ": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TOR_INSERTS.ALL_IO_IA": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00110101",
     },
     "CHA.TOR_INSERTS.PRQ": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": "0-3",
          "Defn": "Counts the number of entries successfuly inserted into the TOR that match qualifications specified by the subevent.",
          "Desc": "TOR Inserts",
          "EvSel": 53,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TOR_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
     },
     "CHA.TOR_OCCUPANCY.IO_MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00100100",
     },
     "CHA.TOR_OCCUPANCY.EVICT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TOR_OCCUPANCY.ALL_MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00100111",
     },
     "CHA.TOR_OCCUPANCY.HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TOR_OCCUPANCY.IA_HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00010001",
     },
     "CHA.TOR_OCCUPANCY.IA": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00110001",
     },
     "CHA.TOR_OCCUPANCY.IPQ": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TOR_OCCUPANCY.IO_HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00010100",
     },
     "CHA.TOR_OCCUPANCY.MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TOR_OCCUPANCY.ALL_HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00010111",
     },
     "CHA.TOR_OCCUPANCY.IO": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00110100",
     },
     "CHA.TOR_OCCUPANCY.IA_MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00100001",
     },
     "CHA.TOR_OCCUPANCY.ALL": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "b00110111",
     },
     "CHA.TOR_OCCUPANCY.PRQ": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TOR_OCCUPANCY.IRQ": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Counters": 0,
          "Defn": "For each cycle, this event accumulates the number of valid entries in the TOR that match qualifications specified by the subevent.   T",
          "Desc": "TOR Occupancy",
          "EvSel": 54,
          "ExtSel": "",
          "Notes": "HW does not strictly OR each subevent.   The equation is roughly (IRQ|EVICT|PRQ|IPQ|RRQ|WBQ) & (HIT|MISS).  Meaing it is necessary to set one of the queue bits before one can measure .HIT or .MISS.   Also note this event is subect to CHA Filter1 which allows a user to opcode match against TOR entries, distinguish those requests satsified locally vs. those that came from a remote node, etc.",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_ADS_USED": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
     },
     "CHA.TxR_HORZ_ADS_USED.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_HORZ_ADS_USED.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_HORZ_ADS_USED.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_ADS_USED.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_HORZ_ADS_USED.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets using the Horizontal Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal ADS Used",
          "EvSel": 157,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_HORZ_BYPASS": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
     },
     "CHA.TxR_HORZ_BYPASS.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_HORZ_BYPASS.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_HORZ_BYPASS.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_HORZ_BYPASS.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_HORZ_BYPASS.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_BYPASS.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of packets bypassing the Horizontal Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Horizontal Bypass Used",
          "EvSel": 159,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_HORZ_CYCLES_FULL": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
     },
     "CHA.TxR_HORZ_CYCLES_FULL.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_HORZ_CYCLES_FULL.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_HORZ_CYCLES_FULL.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_HORZ_CYCLES_FULL.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_HORZ_CYCLES_FULL.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_CYCLES_FULL.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Full.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Full",
          "EvSel": 150,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_HORZ_CYCLES_NE": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
     },
     "CHA.TxR_HORZ_CYCLES_NE.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_HORZ_CYCLES_NE.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_HORZ_CYCLES_NE.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_HORZ_CYCLES_NE.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_CYCLES_NE.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_HORZ_CYCLES_NE.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Cycles the Transgress buffers in the Common Mesh Stop are Not-Empty.  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "Cycles CMS Horizontal Egress Queue is Not Empty",
          "EvSel": 151,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_HORZ_INSERTS": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
     },
     "CHA.TxR_HORZ_INSERTS.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_HORZ_INSERTS.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_INSERTS.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_HORZ_INSERTS.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_HORZ_INSERTS.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_HORZ_INSERTS.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Number of allocations into the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Inserts",
          "EvSel": 149,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_HORZ_NACK": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
     },
     "CHA.TxR_HORZ_NACK.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_HORZ_NACK.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_HORZ_NACK.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_NACK.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_HORZ_NACK.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_HORZ_NACK.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Horizontal Ring",
          "Desc": "CMS Horizontal Egress NACKs",
          "EvSel": 153,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_HORZ_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
     },
     "CHA.TxR_HORZ_OCCUPANCY.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_HORZ_OCCUPANCY.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_OCCUPANCY.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_HORZ_OCCUPANCY.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_HORZ_OCCUPANCY.BL_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_HORZ_OCCUPANCY.AD_CRD": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Occupancy event for the Transgress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Horizontal Ring on the Mesh.",
          "Desc": "CMS Horizontal Egress Occupancy",
          "EvSel": 148,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_HORZ_STARVED": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
     },
     "CHA.TxR_HORZ_STARVED.BL_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_HORZ_STARVED.AK_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_HORZ_STARVED.AD_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_HORZ_STARVED.IV_BNC": {
          "Box": "CHA",
          "Category": "CHA CMS Horizontal EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Transgress buffer cannot send a transaction onto the Horizontal ring for a long period of time.",
          "Desc": "CMS Horizontal Egress Injection Starvation",
          "EvSel": 155,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_VERT_ADS_USED": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
     },
     "CHA.TxR_VERT_ADS_USED.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_VERT_ADS_USED.AK_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_VERT_ADS_USED.AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_VERT_ADS_USED.BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_VERT_ADS_USED.BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_VERT_ADS_USED.AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets using the Vertical Anti-Deadlock Slot, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 156,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_VERT_BYPASS": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
     },
     "CHA.TxR_VERT_BYPASS.BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_VERT_BYPASS.BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_VERT_BYPASS.AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_VERT_BYPASS.AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_VERT_BYPASS.AK_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_VERT_BYPASS.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_VERT_BYPASS.IV": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of packets bypassing the Vertical Egress, broken down by ring type and CMS Agent.",
          "Desc": "CMS Vertical ADS Used",
          "EvSel": 158,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_VERT_CYCLES_FULL": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
     },
     "CHA.TxR_VERT_CYCLES_FULL.BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_VERT_CYCLES_FULL.BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_VERT_CYCLES_FULL.AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_VERT_CYCLES_FULL.AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_VERT_CYCLES_FULL.AK_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_VERT_CYCLES_FULL.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_VERT_CYCLES_FULL.IV": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Full.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Full",
          "EvSel": 146,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_VERT_CYCLES_NE": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
     },
     "CHA.TxR_VERT_CYCLES_NE.AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_VERT_CYCLES_NE.AK_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_VERT_CYCLES_NE.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_VERT_CYCLES_NE.IV": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_VERT_CYCLES_NE.BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_VERT_CYCLES_NE.BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_VERT_CYCLES_NE.AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of cycles the Common Mesh Stop Egress was Not Empty.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "Cycles CMS Vertical Egress Queue Is Not Empty",
          "EvSel": 147,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_VERT_INSERTS": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
     },
     "CHA.TxR_VERT_INSERTS.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_VERT_INSERTS.AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_VERT_INSERTS.AK_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_VERT_INSERTS.IV": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_VERT_INSERTS.BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_VERT_INSERTS.BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_VERT_INSERTS.AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Number of allocations into the Common Mesh Stop Egress.  The Egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Allocations",
          "EvSel": 145,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_VERT_NACK": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
     },
     "CHA.TxR_VERT_NACK.BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_VERT_NACK.AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_VERT_NACK.BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_VERT_NACK.IV": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_VERT_NACK.AK_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_VERT_NACK.AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_VERT_NACK.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts number of Egress packets NACK'ed on to the Vertical Ring",
          "Desc": "CMS Vertical Egress NACKs",
          "EvSel": 152,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_VERT_OCCUPANCY": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
     },
     "CHA.TxR_VERT_OCCUPANCY.AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_VERT_OCCUPANCY.AK_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_VERT_OCCUPANCY.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_VERT_OCCUPANCY.IV": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_VERT_OCCUPANCY.BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_VERT_OCCUPANCY.AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_VERT_OCCUPANCY.BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Occupancy event for the Egress buffers in the Common Mesh Stop  The egress is used to queue up requests destined for the Vertical Ring on the Mesh.",
          "Desc": "CMS Vert Egress Occupancy",
          "EvSel": 144,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.TxR_VERT_STARVED": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
     },
     "CHA.TxR_VERT_STARVED.AK_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.TxR_VERT_STARVED.AD_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.TxR_VERT_STARVED.AK_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.TxR_VERT_STARVED.IV": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.TxR_VERT_STARVED.BL_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.TxR_VERT_STARVED.AD_AG0": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.TxR_VERT_STARVED.BL_AG1": {
          "Box": "CHA",
          "Category": "CHA CMS Vertical EGRESS Events",
          "Defn": "Counts injection starvation.  This starvation is triggered when the CMS Egress cannot send a transaction onto the Vertical ring for a long period of time.",
          "Desc": "CMS Vertical Egress Injection Starvation",
          "EvSel": 154,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "CHA.VERT_RING_AD_IN_USE": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
     },
     "CHA.VERT_RING_AD_IN_USE.UP_EVEN": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.VERT_RING_AD_IN_USE.DN_ODD": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.VERT_RING_AD_IN_USE.UP_ODD": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.VERT_RING_AD_IN_USE.DN_EVEN": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AD ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  We really have two rings  -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AD Ring In Use",
          "EvSel": 166,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.VERT_RING_AK_IN_USE": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
     },
     "CHA.VERT_RING_AK_IN_USE.UP_EVEN": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.VERT_RING_AK_IN_USE.DN_ODD": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.VERT_RING_AK_IN_USE.UP_ODD": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.VERT_RING_AK_IN_USE.DN_EVEN": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical AK ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.We really have two rings in -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical AK Ring In Use",
          "EvSel": 168,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.VERT_RING_BL_IN_USE": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
     },
     "CHA.VERT_RING_BL_IN_USE.UP_EVEN": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.VERT_RING_BL_IN_USE.DN_ODD": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.VERT_RING_BL_IN_USE.UP_ODD": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.VERT_RING_BL_IN_USE.DN_EVEN": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical BL ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from  the ring stop.We really have two rings -- a clockwise ring and a counter-clockwise ring.  On the left side of the ring, the \"UP\" direction is on the clockwise ring and \"DN\" is on the counter-clockwise ring.  On the right side of the ring, this is reversed.  The first half of the CBos are on the left side of the ring, and the 2nd half are on the right side of the ring.  In other words (for example), in a 4c part, Cbo 0 UP AD is NOT the same ring as CBo 2 UP AD because they are on opposite sides of the ring.",
          "Desc": "Vertical BL Ring in Use",
          "EvSel": 170,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.VERT_RING_IV_IN_USE": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
     },
     "CHA.VERT_RING_IV_IN_USE.DN": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.VERT_RING_IV_IN_USE.UP": {
          "Box": "CHA",
          "Category": "CHA Vertical In Use RING Events",
          "Defn": "Counts the number of cycles that the Vertical IV ring is being used at this ring stop.  This includes when packets are passing by and when packets are being sunk, but does not include when packets are being sent from the ring stop.  There is only 1 IV ring.  Therefore, if one wants to monitor the \"Even\" ring, they should select both UP_EVEN and DN_EVEN.  To monitor the \"Odd\" ring, they should select both UP_ODD and DN_ODD.",
          "Desc": "Vertical IV Ring in Use",
          "EvSel": 172,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.WB_PUSH_MTOI": {
          "Box": "CHA",
          "Category": "CHA HA WBPUSHMTOI Events",
          "Defn": "Counts the number of times when the CHA was received WbPushMtoI",
          "Desc": "WbPushMtoI",
          "EvSel": 86,
          "ExtSel": "",
     },
     "CHA.WB_PUSH_MTOI.LLC": {
          "Box": "CHA",
          "Category": "CHA HA WBPUSHMTOI Events",
          "Defn": "Counts the number of times when the CHA was received WbPushMtoI",
          "Desc": "WbPushMtoI",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.WB_PUSH_MTOI.MEM": {
          "Box": "CHA",
          "Category": "CHA HA WBPUSHMTOI Events",
          "Defn": "Counts the number of times when the CHA was received WbPushMtoI",
          "Desc": "WbPushMtoI",
          "EvSel": 86,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.WRITE_NO_CREDITS": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.",
          "Desc": "CHA iMC CHNx WRITE Credits Empty",
          "EvSel": 90,
          "ExtSel": "",
     },
     "CHA.WRITE_NO_CREDITS.MC1_SMI1": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.",
          "Desc": "CHA iMC CHNx WRITE Credits Empty",
          "EvSel": 90,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "CHA.WRITE_NO_CREDITS.EDC2_SMI4": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.",
          "Desc": "CHA iMC CHNx WRITE Credits Empty",
          "EvSel": 90,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "CHA.WRITE_NO_CREDITS.EDC0_SMI2": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.",
          "Desc": "CHA iMC CHNx WRITE Credits Empty",
          "EvSel": 90,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "CHA.WRITE_NO_CREDITS.MC0_SMI0": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.",
          "Desc": "CHA iMC CHNx WRITE Credits Empty",
          "EvSel": 90,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "CHA.WRITE_NO_CREDITS.EDC1_SMI3": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.",
          "Desc": "CHA iMC CHNx WRITE Credits Empty",
          "EvSel": 90,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "CHA.WRITE_NO_CREDITS.EDC3_SMI5": {
          "Box": "CHA",
          "Category": "CHA HA READ WRITE Events",
          "Defn": "Counts the number of times when there are no credits available for sending WRITEs from the CHA into the iMC.  In order to send WRITEs into the memory controller, the HA must first acquire a credit for the iMC's BL Ingress queue.",
          "Desc": "CHA iMC CHNx WRITE Credits Empty",
          "EvSel": 90,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "CHA.XSNP_RESP": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
     },
     "CHA.XSNP_RESP.EXT_RSPI_FWDM": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b00110000",
     },
     "CHA.XSNP_RESP.ANY_RSP_HITFSE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b11100001",
     },
     "CHA.XSNP_RESP.CORE_RSPS_FWDFE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b01000010",
     },
     "CHA.XSNP_RESP.EVICT_RSPS_FWDFE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b10000010",
     },
     "CHA.XSNP_RESP.CORE_RSPI_FWDFE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b01000100",
     },
     "CHA.XSNP_RESP.EVICT_RSP_HITFSE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b10000001",
     },
     "CHA.XSNP_RESP.CORE_RSPI_FWDM": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b01010000",
     },
     "CHA.XSNP_RESP.EXT_RSPS_FWDFE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b00100010",
     },
     "CHA.XSNP_RESP.EXT_RSPS_FWDM": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b00101000",
     },
     "CHA.XSNP_RESP.EVICT_RSPI_FWDM": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b10010000",
     },
     "CHA.XSNP_RESP.CORE_RSP_HITFSE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b01000001",
     },
     "CHA.XSNP_RESP.EXT_RSP_HITFSE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b00100001",
     },
     "CHA.XSNP_RESP.ANY_RSPS_FWDFE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b11100010",
     },
     "CHA.XSNP_RESP.EVICT_RSPS_FWDM": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b10001000",
     },
     "CHA.XSNP_RESP.EXT_RSPI_FWDFE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b00100100",
     },
     "CHA.XSNP_RESP.ANY_RSPI_FWDFE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b11100100",
     },
     "CHA.XSNP_RESP.ANY_RSPS_FWDM": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b11101000",
     },
     "CHA.XSNP_RESP.EVICT_RSPI_FWDFE": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b10000100",
     },
     "CHA.XSNP_RESP.CORE_RSPS_FWDM": {
          "Box": "CHA",
          "Category": "CHA ISMQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of core cross snoops.  Cores are snooped if the transaction looks up the cache and determines that it is necessary based on the operation type. This event can be filtered based on who triggered the initial snoop(s):  from Evictions, Core  or External (i.e. from a remote node) Requests.  And the event can be filtered based on the responses:  RspX_Fwd/HitY where Y is the state prior to the snoop response and X is the state following.",
          "Desc": "Core Cross Snoop Responses",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "b01001000",
     },
     
# UBOX:
     "UBOX.EVENT_MSG": {
          "Box": "UBOX",
          "Category": "UBOX EVENT_MSG Events",
          "Counters": "0-1",
          "Defn": "Virtual Logical Wire (legacy) message were received from Uncore.",
          "Desc": "Message Received",
          "EvSel": 66,
          "ExtSel": "",
     },
     "UBOX.EVENT_MSG.VLW_RCVD": {
          "Box": "UBOX",
          "Category": "UBOX EVENT_MSG Events",
          "Counters": "0-1",
          "Defn": "Virtual Logical Wire (legacy) message were received from Uncore.",
          "Desc": "Message Received",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UBOX.EVENT_MSG.MSI_RCVD": {
          "Box": "UBOX",
          "Category": "UBOX EVENT_MSG Events",
          "Counters": "0-1",
          "Defn": "Virtual Logical Wire (legacy) message were received from Uncore.",
          "Desc": "Message Received",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UBOX.EVENT_MSG.DOORBELL_RCVD": {
          "Box": "UBOX",
          "Category": "UBOX EVENT_MSG Events",
          "Counters": "0-1",
          "Defn": "Virtual Logical Wire (legacy) message were received from Uncore.",
          "Desc": "Message Received",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "UBOX.EVENT_MSG.IPI_RCVD": {
          "Box": "UBOX",
          "Category": "UBOX EVENT_MSG Events",
          "Counters": "0-1",
          "Defn": "Virtual Logical Wire (legacy) message were received from Uncore.",
          "Desc": "Message Received",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UBOX.EVENT_MSG.INT_PRIO": {
          "Box": "UBOX",
          "Category": "UBOX EVENT_MSG Events",
          "Counters": "0-1",
          "Defn": "Virtual Logical Wire (legacy) message were received from Uncore.",
          "Desc": "Message Received",
          "EvSel": 66,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "UBOX.LOCK_CYCLES": {
          "Box": "UBOX",
          "Category": "UBOX LOCK Events",
          "Counters": "0-1",
          "Defn": "Number of times an IDI Lock/SplitLock sequence was started",
          "Desc": "IDI Lock/SplitLock Cycles",
          "EvSel": 68,
          "ExtSel": "",
     },
     "UBOX.PHOLD_CYCLES": {
          "Box": "UBOX",
          "Category": "UBOX PHOLD Events",
          "Counters": "0-1",
          "Defn": "PHOLD cycles.",
          "Desc": "Cycles PHOLD Assert to Ack",
          "EvSel": 69,
          "ExtSel": "",
     },
     "UBOX.PHOLD_CYCLES.ASSERT_TO_ACK": {
          "Box": "UBOX",
          "Category": "UBOX PHOLD Events",
          "Counters": "0-1",
          "Defn": "PHOLD cycles.",
          "Desc": "Cycles PHOLD Assert to Ack",
          "EvSel": 69,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UBOX.RACU_DRNG": {
          "Box": "UBOX",
          "Category": "UBOX RACU Events",
          "EvSel": 76,
          "ExtSel": "",
     },
     "UBOX.RACU_DRNG.RDSEED": {
          "Box": "UBOX",
          "Category": "UBOX RACU Events",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UBOX.RACU_DRNG.PFTCH_BUF_EMPTY": {
          "Box": "UBOX",
          "Category": "UBOX RACU Events",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UBOX.RACU_DRNG.RDRAND": {
          "Box": "UBOX",
          "Category": "UBOX RACU Events",
          "EvSel": 76,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UBOX.RACU_REQUESTS": {
          "Box": "UBOX",
          "Category": "UBOX RACU Events",
          "Counters": "0-1",
          "Defn": "Number outstanding register requests within message channel tracker",
          "Desc": "RACU Request",
          "EvSel": 70,
          "ExtSel": "",
     },
     
# UPI_LL:
     "UPI_LL.CLOCKTICKS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CFCLK Events",
          "Counters": "0-3",
          "Defn": "Counts the number of clocks in the UPI LL.  This clock runs at 1/8th the \"GT/s\" speed of the UPI link.  For example, a 8GT/s link will have qfclk or 1GHz.  Current products do not support dynamic link speeds, so this frequency is fixed.",
          "Desc": "Number of kfclks",
          "EvSel": 1,
          "ExtSel": "",
     },
     "UPI_LL.DIRECT_ATTEMPTS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL DIRECT2CORE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of Data Response(DRS) packets UPI attempted to send directly to the core or to a different UPI link.    Note:  This only counts attempts on valid candidates such as DRS packets destined for CHAs.",
          "Desc": "Direct packet attempts",
          "EvSel": 18,
          "ExtSel": "",
     },
     "UPI_LL.DIRECT_ATTEMPTS.D2U": {
          "Box": "UPI_LL",
          "Category": "UPI_LL DIRECT2CORE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of Data Response(DRS) packets UPI attempted to send directly to the core or to a different UPI link.    Note:  This only counts attempts on valid candidates such as DRS packets destined for CHAs.",
          "Desc": "Direct packet attempts",
          "EvSel": 18,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.DIRECT_ATTEMPTS.D2C": {
          "Box": "UPI_LL",
          "Category": "UPI_LL DIRECT2CORE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of Data Response(DRS) packets UPI attempted to send directly to the core or to a different UPI link.    Note:  This only counts attempts on valid candidates such as DRS packets destined for CHAs.",
          "Desc": "Direct packet attempts",
          "EvSel": 18,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD.AD_VNA_EQ2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD.AK_VNA_EQ3": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD.BL_VNA_EQ0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD.AK_VNA_EQ2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD.AD_VNA_EQ1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD.AK_VNA_EQ1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD.AK_VNA_EQ0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "UPI_LL.FLOWQ_NO_VNA_CRD.AD_VNA_EQ0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 24,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.L1_POWER_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER Events",
          "Counters": "0-3",
          "Defn": "Number of UPI qfclk cycles spent in L1 power mode.  L1 is a mode that totally shuts down a UPI link.  Use edge detect to count the number of instances when the UPI link entered L1.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another. Because L1 totally shuts down the link, it takes a good amount of time to exit this mode.",
          "Desc": "Cycles in L1",
          "EvSel": 33,
          "ExtSel": "",
     },
     "UPI_LL.M3_BYP_BLOCKED": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 20,
          "ExtSel": "",
     },
     "UPI_LL.M3_BYP_BLOCKED.BGF_CRD": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 20,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "UPI_LL.M3_BYP_BLOCKED.FLOWQ_AK_VNA_LE3": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 20,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.M3_BYP_BLOCKED.FLOWQ_AD_VNA_LE2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 20,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.M3_BYP_BLOCKED.GV_BLOCK": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 20,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "UPI_LL.M3_BYP_BLOCKED.FLOWQ_BL_VNA_EQ0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 20,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.M3_CRD_RETURN_BLOCKED": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 22,
          "ExtSel": "",
     },
     "UPI_LL.M3_RXQ_BLOCKED": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 21,
          "ExtSel": "",
     },
     "UPI_LL.M3_RXQ_BLOCKED.FLOWQ_AK_VNA_LE3": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "UPI_LL.M3_RXQ_BLOCKED.FLOWQ_AD_VNA_BTW_2_THRESH": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.M3_RXQ_BLOCKED.BGF_CRD": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "UPI_LL.M3_RXQ_BLOCKED.FLOWQ_BL_VNA_EQ0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.M3_RXQ_BLOCKED.FLOWQ_BL_VNA_BTW_0_THRESH": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "UPI_LL.M3_RXQ_BLOCKED.GV_BLOCK": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "UPI_LL.M3_RXQ_BLOCKED.FLOWQ_AD_VNA_LE2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL LL to M3 Events",
          "Counters": "0-3",
          "EvSel": 21,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.PHY_INIT_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER Events",
          "Counters": "0-3",
          "Desc": "Cycles where phy is not in L0, L0c, L0p, L1",
          "EvSel": 32,
          "ExtSel": "",
     },
     "UPI_LL.POWER_L1_NACK": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times a link sends/receives a LinkReqNAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqNAck refers to receiving an NAck (meaning this agent's Tx originally requested the power change).  A Tx LinkReqNAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
          "Desc": "L1 Req Nack",
          "EvSel": 35,
          "ExtSel": "",
          "Notes": "L1 only",
     },
     "UPI_LL.POWER_L1_REQ": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times a link sends/receives a LinkReqAck.  When the UPI links would like to change power state, the Tx side initiates a request to the Rx side requesting to change states.  This requests can either be accepted or denied.  If the Rx side replies with an Ack, the power mode will change.  If it replies with NAck, no change will take place.  This can be filtered based on Rx and Tx.  An Rx LinkReqAck refers to receiving an Ack (meaning this agent's Tx originally requested the power change).  A Tx LinkReqAck refers to sending this command (meaning the peer agent's Tx originally requested the power change and this agent accepted it).",
          "Desc": "L1 Req (same as L1 Ack).",
          "EvSel": 34,
          "ExtSel": "",
          "Notes": "L1 only",
     },
     "UPI_LL.REQ_SLOT2_FROM_M3": {
          "Box": "UPI_LL",
          "Category": "UPI_LL VNA_CREDIT_RETURN Events",
          "Counters": "0-3",
          "EvSel": 70,
          "ExtSel": "",
     },
     "UPI_LL.REQ_SLOT2_FROM_M3.VN0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL VNA_CREDIT_RETURN Events",
          "Counters": "0-3",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.REQ_SLOT2_FROM_M3.VNA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL VNA_CREDIT_RETURN Events",
          "Counters": "0-3",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.REQ_SLOT2_FROM_M3.ACK": {
          "Box": "UPI_LL",
          "Category": "UPI_LL VNA_CREDIT_RETURN Events",
          "Counters": "0-3",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "UPI_LL.REQ_SLOT2_FROM_M3.VN1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL VNA_CREDIT_RETURN Events",
          "Counters": "0-3",
          "EvSel": 70,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.RxL0P_POWER_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_RX Events",
          "Counters": "0-3",
          "Defn": "Number of UPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses.  Use edge detect to count the number of instances when the UPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
          "Desc": "Cycles link in L0p.  Receive side.",
          "EvSel": 37,
          "ExtSel": "",
          "Notes": "Using .edge_det to count transitions does not function if L1_POWER_CYCLES > 0.",
     },
     "UPI_LL.RxL0_POWER_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_RX Events",
          "Counters": "0-3",
          "Defn": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
          "Desc": "Cycles in L0. Receive side.",
          "EvSel": 36,
          "ExtSel": "",
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.RSP_NODATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1010",
          "UmaskExt": 0x0,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.NCS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1111",
          "UmaskExt": 0x0,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.RSP_DATA_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bXXXX1100",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.WB_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1101",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.REQ_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bXXXX1000",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.RSPCNFLT": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "b10101010",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.NCB_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1110",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.RSP_NODATA_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bXXXX1010",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.NCB": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1110",
          "UmaskExt": 0x0,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.SNP": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1001",
          "UmaskExt": 0x0,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.REQ": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1000",
          "UmaskExt": 0x0,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.NCS_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1111",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.SNP_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "b1001",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.RSPI": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "b00101010",
          "UmaskExt": 0x1,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.WB": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1101",
          "UmaskExt": 0x0,
     },
     "UPI_LL.RxL_BASIC_HDR_MATCH.RSP_DATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Receive path of a UPI Port",
          "EvSel": 5,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1100",
          "UmaskExt": 0x0,
     },
     "UPI_LL.RxL_BYPASSED": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
          "Desc": "RxQ Flit Buffer Bypassed",
          "EvSel": 49,
          "ExtSel": "",
     },
     "UPI_LL.RxL_BYPASSED.SLOT1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
          "Desc": "RxQ Flit Buffer Bypassed",
          "EvSel": 49,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.RxL_BYPASSED.SLOT0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
          "Desc": "RxQ Flit Buffer Bypassed",
          "EvSel": 49,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.RxL_BYPASSED.SLOT2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that an incoming flit was able to bypass the flit buffer and pass directly and into the Egress.  This is a latency optimization, and should generally be the common case.  If this value is less than the number of flits transfered, it implies that there was queueing getting onto the ring, and thus the transactions saw higher latency.",
          "Desc": "RxQ Flit Buffer Bypassed",
          "EvSel": 49,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.RxL_CREDITS_CONSUMED_VN0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RX_CREDITS_CONSUMED Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that an RxQ VN0 credit was consumed (i.e. message uses a VN0 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
          "Desc": "VN0 Credit Consumed",
          "EvSel": 57,
          "ExtSel": "",
     },
     "UPI_LL.RxL_CREDITS_CONSUMED_VN1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RX_CREDITS_CONSUMED Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that an RxQ VN1 credit was consumed (i.e. message uses a VN1 credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
          "Desc": "VN1 Credit Consumed",
          "EvSel": 58,
          "ExtSel": "",
     },
     "UPI_LL.RxL_CREDITS_CONSUMED_VNA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RX_CREDITS_CONSUMED Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that an RxQ VNA credit was consumed (i.e. message uses a VNA credit for the Rx Buffer).  This includes packets that went through the RxQ and those that were bypasssed.",
          "Desc": "VNA Credit Consumed",
          "EvSel": 56,
          "ExtSel": "",
     },
     "UPI_LL.RxL_FLITS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
     },
     "UPI_LL.RxL_FLITS.NULL": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "bxx1xxxxx",
     },
     "UPI_LL.RxL_FLITS.SLOT0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.RxL_FLITS.ALL_NULL": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "b00100111",
     },
     "UPI_LL.RxL_FLITS.NON_DATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "b10010111",
     },
     "UPI_LL.RxL_FLITS.IDLE": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "b01000111",
     },
     "UPI_LL.RxL_FLITS.LLCTRL": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "bx1xxxxxx",
     },
     "UPI_LL.RxL_FLITS.ALL_DATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "b00001111",
     },
     "UPI_LL.RxL_FLITS.SLOT1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.RxL_FLITS.PROTHDR": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "b1xxxxxxx",
     },
     "UPI_LL.RxL_FLITS.DATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "bxxxx1xxx",
     },
     "UPI_LL.RxL_FLITS.LLCRD": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "bxxx1xxxx",
     },
     "UPI_LL.RxL_FLITS.SLOT2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Received",
          "EvSel": 3,
          "ExtSel": "",
          "Notes": "When Umask is set to all 1's then  all Flits should be counted as 3 since a full flit is counted for each valid slot.  By counting all legal flit time we exclude  impact of L0p, L0c, and the 5/6 ratio in L0.   Slot 0 Dual is counted in slot 0 and slot 1 (as a protocol header)",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.RxL_INSERTS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
          "Desc": "RxQ Flit Buffer Allocations",
          "EvSel": 48,
          "ExtSel": "",
     },
     "UPI_LL.RxL_INSERTS.SLOT2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
          "Desc": "RxQ Flit Buffer Allocations",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.RxL_INSERTS.SLOT0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
          "Desc": "RxQ Flit Buffer Allocations",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.RxL_INSERTS.SLOT1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Number of allocations into the UPI Rx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
          "Desc": "RxQ Flit Buffer Allocations",
          "EvSel": 48,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.RxL_OCCUPANCY": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
          "Desc": "RxQ Occupancy - All Packets",
          "EvSel": 50,
          "ExtSel": "",
     },
     "UPI_LL.RxL_OCCUPANCY.SLOT1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
          "Desc": "RxQ Occupancy - All Packets",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.RxL_OCCUPANCY.SLOT0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
          "Desc": "RxQ Occupancy - All Packets",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.RxL_OCCUPANCY.SLOT2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "Defn": "Accumulates the number of elements in the UPI RxQ in each cycle.  Generally, when data is transmitted across UPI, it will bypass the RxQ and pass directly to the ring interface.  If things back up getting transmitted onto the ring, however, it may need to allocate into this buffer, thus increasing the latency.  This event can be used in conjunction with the Flit Buffer Not Empty event to calculate average occupancy, or with the Flit Buffer Allocations event to track average lifetime.",
          "Desc": "RxQ Occupancy - All Packets",
          "EvSel": 50,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.RxL_SLOT_BYPASS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "EvSel": 51,
          "ExtSel": "",
     },
     "UPI_LL.RxL_SLOT_BYPASS.S0_RXQ2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.RxL_SLOT_BYPASS.S0_RXQ1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.RxL_SLOT_BYPASS.S1_RXQ0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.RxL_SLOT_BYPASS.S2_RXQ1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "UPI_LL.RxL_SLOT_BYPASS.S1_RXQ2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "UPI_LL.RxL_SLOT_BYPASS.S2_RXQ0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL RXQ Events",
          "Counters": "0-3",
          "EvSel": 51,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE.RXQ_CRED": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE.RXQ": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE.RETRY": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE.RXQ_BYPASS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE.DFX": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE.CFG_CTL": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE.SPARE": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "UPI_LL.TxL0P_CLK_ACTIVE.TXQ": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 42,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "UPI_LL.TxL0P_POWER_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "Defn": "Number of UPI qfclk cycles spent in L0p power mode.  L0p is a mode where we disable 60% of the UPI lanes, decreasing our bandwidth in order to save power.  It increases snoop and data transfer latencies and decreases overall bandwidth.  This mode can be very useful in NUMA optimized workloads that largely only utilize UPI for snoops and their responses.  Use edge detect to count the number of instances when the UPI link entered L0p.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.",
          "Desc": "Cycles in L0p. Transmit side.",
          "EvSel": 39,
          "ExtSel": "",
          "Notes": "Using .edge_det to count transitions does not function if L1_POWER_CYCLES > 0.",
     },
     "UPI_LL.TxL0P_POWER_CYCLES_LL_ENTER": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 40,
          "ExtSel": "",
     },
     "UPI_LL.TxL0P_POWER_CYCLES_M3_EXIT": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "EvSel": 41,
          "ExtSel": "",
     },
     "UPI_LL.TxL0_POWER_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_TX Events",
          "Counters": "0-3",
          "Defn": "Number of UPI qfclk cycles spent in L0 power mode in the Link Layer.  L0 is the default mode which provides the highest performance with the most power.  Use edge detect to count the number of instances that the link entered L0.  Link power states are per link and per direction, so for example the Tx direction could be in one state while Rx was in another.  The phy layer  sometimes leaves L0 for training, which will not be captured by this event.",
          "Desc": "Cycles in L0. Transmit side.",
          "EvSel": 38,
          "ExtSel": "",
          "Notes": "Includes L0p cycles.  To get just L0, subtract TxL0P_POWER_CYCLES",
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.RSP_DATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1100",
          "UmaskExt": 0x0,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.WB": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1101",
          "UmaskExt": 0x0,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.RSPI": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "b00101010",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.SNP_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bXXXX1001",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.NCS_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1111",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.REQ": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1000",
          "UmaskExt": 0x0,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.NCB": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1110",
          "UmaskExt": 0x0,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.SNP": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1001",
          "UmaskExt": 0x0,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.RSP_NODATA_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bXXXX1010",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.NCB_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1110",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.RSPCNFLT": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "b10101010",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.WB_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1101",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.REQ_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bXXXX1000",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.RSP_DATA_OPC": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bXXXX1100",
          "UmaskExt": 0x1,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.NCS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1111",
          "UmaskExt": 0x0,
     },
     "UPI_LL.TxL_BASIC_HDR_MATCH.RSP_NODATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL FLIT match Events",
          "Counters": "0-3",
          "Desc": "Matches on Transmit path of a UPI Port",
          "EvSel": 4,
          "Filter": "CtrCtrl[55:32]",
          "ExtSel": "",
          "Notes": "This event is subject to finer grain filtering.   See doc for more information.  Filters available in the counter control's umask extention field b[55:32] - message class, opcode, local, remote, datahdr, ndatahdr, dual slot header, single slot header and pe) ANDed per Slot.   Then slots are ORed.",
          "Umask": "bxxxx1010",
          "UmaskExt": 0x0,
     },
     "UPI_LL.TxL_BYPASSED": {
          "Box": "UPI_LL",
          "Category": "UPI_LL TXQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that an incoming flit was able to bypass the Tx flit buffer and pass directly out the UPI Link. Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.",
          "Desc": "Tx Flit Buffer Bypassed",
          "EvSel": 65,
          "ExtSel": "",
     },
     "UPI_LL.TxL_FLITS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
     },
     "UPI_LL.TxL_FLITS.SLOT2": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "bxxxxx1xx",
     },
     "UPI_LL.TxL_FLITS.DATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "bxxxx1xxx",
     },
     "UPI_LL.TxL_FLITS.LLCRD": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "bxxx1xxxx",
     },
     "UPI_LL.TxL_FLITS.SLOT1": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "bxxxxxx1x",
     },
     "UPI_LL.TxL_FLITS.PROTHDR": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "b1xxxxxxx",
     },
     "UPI_LL.TxL_FLITS.IDLE": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "b01000111",
     },
     "UPI_LL.TxL_FLITS.ALL_DATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "b00001111",
     },
     "UPI_LL.TxL_FLITS.LLCTRL": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "bx1xxxxxx",
     },
     "UPI_LL.TxL_FLITS.SLOT0": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "bxxxxxxx1",
     },
     "UPI_LL.TxL_FLITS.ALL_NULL": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "b00100111",
     },
     "UPI_LL.TxL_FLITS.NON_DATA": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "b10010111",
     },
     "UPI_LL.TxL_FLITS.NULL": {
          "Box": "UPI_LL",
          "Category": "UPI_LL Flit Events",
          "Counters": "0-3",
          "Defn": "Shows legal flit time (hides impact of L0p and L0c).",
          "Desc": "Valid Flits Sent",
          "EvSel": 2,
          "ExtSel": "",
          "Notes": "You can OR any of 5 MSB together and apply against any combination of slots and they will be added together, but a slot MUST be selected.",
          "Umask": "bxx1xxxxx",
     },
     "UPI_LL.TxL_INSERTS": {
          "Box": "UPI_LL",
          "Category": "UPI_LL TXQ Events",
          "Counters": "0-3",
          "Defn": "Number of allocations into the UPI Tx Flit Buffer.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link.  This event can be used in conjunction with the Flit Buffer Occupancy event in order to calculate the average flit buffer lifetime.",
          "Desc": "Tx Flit Buffer Allocations",
          "EvSel": 64,
          "ExtSel": "",
     },
     "UPI_LL.TxL_OCCUPANCY": {
          "Box": "UPI_LL",
          "Category": "UPI_LL TXQ Events",
          "Counters": "0-3",
          "Defn": "Accumulates the number of flits in the TxQ.  Generally, when data is transmitted across UPI, it will bypass the TxQ and pass directly to the link.  However, the TxQ will be used with L0p and when LLR occurs, increasing latency to transfer out to the link. This can be used with the cycles not empty event to track average occupancy, or the allocations event to track average lifetime in the TxQ.",
          "Desc": "Tx Flit Buffer Occupancy",
          "EvSel": 66,
          "ExtSel": "",
     },
     "UPI_LL.VNA_CREDIT_RETURN_BLOCKED_VN01": {
          "Box": "UPI_LL",
          "Category": "UPI_LL VNA_CREDIT_RETURN Events",
          "Counters": "0-3",
          "EvSel": 69,
          "ExtSel": "",
     },
     "UPI_LL.VNA_CREDIT_RETURN_OCCUPANCY": {
          "Box": "UPI_LL",
          "Category": "UPI_LL VNA_CREDIT_RETURN Events",
          "Counters": "0-3",
          "Defn": "Number of VNA credits in the Rx side that are waitng to be returned back across the link.",
          "Desc": "VNA Credits Pending Return - Occupancy",
          "EvSel": 68,
          "ExtSel": "",
     },
     
# iMC:
     "iMC.ACT_COUNT": {
          "Box": "iMC",
          "Category": "iMC ACT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
          "Desc": "DRAM Activate Count",
          "EvSel": 1,
          "ExtSel": "",
     },
     "iMC.ACT_COUNT.BYP": {
          "Box": "iMC",
          "Category": "iMC ACT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
          "Desc": "DRAM Activate Count",
          "EvSel": 1,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "iMC.ACT_COUNT.RD": {
          "Box": "iMC",
          "Category": "iMC ACT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
          "Desc": "DRAM Activate Count",
          "EvSel": 1,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.ACT_COUNT.WR": {
          "Box": "iMC",
          "Category": "iMC ACT Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Activate commands sent on this channel.  Activate commands are issued to open up a page on the DRAM devices so that it can be read or written to with a CAS.  One can calculate the number of Page Misses by subtracting the number of Page Miss precharges from the number of Activates.",
          "Desc": "DRAM Activate Count",
          "EvSel": 1,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.BYP_CMDS": {
          "Box": "iMC",
          "Category": "iMC BYPASS Command Events",
          "Counters": "0-3",
          "EvSel": 161,
          "ExtSel": "",
     },
     "iMC.BYP_CMDS.PRE": {
          "Box": "iMC",
          "Category": "iMC BYPASS Command Events",
          "Counters": "0-3",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "iMC.BYP_CMDS.ACT": {
          "Box": "iMC",
          "Category": "iMC BYPASS Command Events",
          "Counters": "0-3",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.BYP_CMDS.CAS": {
          "Box": "iMC",
          "Category": "iMC BYPASS Command Events",
          "Counters": "0-3",
          "EvSel": 161,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.CAS_COUNT": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
     },
     "iMC.CAS_COUNT.WR_WMM": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "iMC.CAS_COUNT.RD_RMM": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "iMC.CAS_COUNT.ALL": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "b00001111",
     },
     "iMC.CAS_COUNT.RD_REG": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.CAS_COUNT.WR_RMM": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "iMC.CAS_COUNT.RD": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "b00000011",
     },
     "iMC.CAS_COUNT.WR_ISOCH": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "iMC.CAS_COUNT.WR": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "b00001100",
     },
     "iMC.CAS_COUNT.RD_ISOCH": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "iMC.CAS_COUNT.RD_WMM": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "iMC.CAS_COUNT.RD_UNDERFILL": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Desc": "DRAM CAS (Column Address Strobe) Commands.",
          "EvSel": 4,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.CLOCKTICKS": {
          "Box": "iMC",
          "Category": "iMC DCLK Events",
          "Counters": "0-3",
          "Desc": "DRAM Clockticks",
          "EvSel": 0,
          "ExtSel": "",
     },
     "iMC.DRAM_PRE_ALL": {
          "Box": "iMC",
          "Category": "iMC DRAM_PRE_ALL Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times that the precharge all command was sent.",
          "Desc": "DRAM Precharge All Commands",
          "EvSel": 6,
          "ExtSel": "",
     },
     "iMC.DRAM_REFRESH": {
          "Box": "iMC",
          "Category": "iMC DRAM_REFRESH Events",
          "Counters": "0-3",
          "Defn": "Counts the number of refreshes issued.",
          "Desc": "Number of DRAM Refreshes Issued",
          "EvSel": 5,
          "ExtSel": "",
     },
     "iMC.DRAM_REFRESH.HIGH": {
          "Box": "iMC",
          "Category": "iMC DRAM_REFRESH Events",
          "Counters": "0-3",
          "Defn": "Counts the number of refreshes issued.",
          "Desc": "Number of DRAM Refreshes Issued",
          "EvSel": 5,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "iMC.DRAM_REFRESH.PANIC": {
          "Box": "iMC",
          "Category": "iMC DRAM_REFRESH Events",
          "Counters": "0-3",
          "Defn": "Counts the number of refreshes issued.",
          "Desc": "Number of DRAM Refreshes Issued",
          "EvSel": 5,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.ECC_CORRECTABLE_ERRORS": {
          "Box": "iMC",
          "Category": "iMC ECC Events",
          "Counters": "0-3",
          "Defn": "Counts the number of ECC errors detected and corrected by the iMC on this channel.  This counter is only useful with ECC DRAM devices.  This count will increment one time for each correction regardless of the number of bits corrected.  The iMC can correct up to 4 bit errors in independent channel mode and 8 bit erros in lockstep mode.",
          "Desc": "ECC Correctable Errors",
          "EvSel": 9,
          "ExtSel": "",
     },
     "iMC.MAJOR_MODES": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
          "Desc": "Cycles in a Major Mode",
          "EvSel": 7,
          "ExtSel": "",
     },
     "iMC.MAJOR_MODES.WRITE": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
          "Desc": "Cycles in a Major Mode",
          "EvSel": 7,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.MAJOR_MODES.PARTIAL": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
          "Desc": "Cycles in a Major Mode",
          "EvSel": 7,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "iMC.MAJOR_MODES.READ": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
          "Desc": "Cycles in a Major Mode",
          "EvSel": 7,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.MAJOR_MODES.ISOCH": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Defn": "Counts the total number of cycles spent in a major mode (selected by a filter) on the given channel.   Major modea are channel-wide, and not a per-rank (or dimm or bank) mode.",
          "Desc": "Cycles in a Major Mode",
          "EvSel": 7,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "iMC.POWER_CHANNEL_DLLOFF": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles when all the ranks in the channel are in CKE Slow (DLLOFF) mode.",
          "Desc": "Channel DLLOFF Cycles",
          "EvSel": 132,
          "ExtSel": "",
          "Notes": "IBT = Input Buffer Termination = Off",
     },
     "iMC.POWER_CHANNEL_PPD": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles when all the ranks in the channel are in PPD mode.  If IBT=off is enabled, then this can be used to count those cycles.  If it is not enabled, then this can count the number of cycles when that could have been taken advantage of.",
          "Desc": "Channel PPD Cycles",
          "EvSel": 133,
          "ExtSel": "",
          "Notes": "IBT = Input Buffer Termination = On",
     },
     "iMC.POWER_CKE_CYCLES": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
     },
     "iMC.POWER_CKE_CYCLES.RANK3": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
          "Umask": "b00001000",
     },
     "iMC.POWER_CKE_CYCLES.RANK2": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
          "Umask": "b00000100",
     },
     "iMC.POWER_CKE_CYCLES.RANK5": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
          "Umask": "b00100000",
     },
     "iMC.POWER_CKE_CYCLES.RANK0": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "iMC.POWER_CKE_CYCLES.RANK1": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "iMC.POWER_CKE_CYCLES.RANK4": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
          "Umask": "b00010000",
     },
     "iMC.POWER_CKE_CYCLES.RANK7": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
          "Umask": "b10000000",
     },
     "iMC.POWER_CKE_CYCLES.RANK6": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Number of cycles spent in CKE ON mode.  The filter allows you to select a rank to monitor.  If multiple ranks are in CKE ON mode at one time, the counter will ONLY increment by one rather than doing accumulation.  Multiple counters will need to be used to track multiple ranks simultaneously.  There is no distinction between the different CKE modes (APD, PPDS, PPDF).  This can be determined based on the system programming.  These events should commonly be used with Invert to get the number of cycles in power saving mode.  Edge Detect is also useful here.  Make sure that you do NOT use Invert with Edge Detect (this just confuses the system and is not necessary).",
          "Desc": "CKE_ON_CYCLES by Rank",
          "EvSel": 131,
          "ExtSel": "",
          "Umask": "b01000000",
     },
     "iMC.POWER_CRITICAL_THROTTLE_CYCLES": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the iMC is in critical thermal throttling.  When this happens, all traffic is blocked.  This should be rare unless something bad is going on in the platform.  There is no filtering by rank for this event.",
          "Desc": "Critical Throttle Cycles",
          "EvSel": 134,
          "ExtSel": "",
     },
     "iMC.POWER_PCU_THROTTLING": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "EvSel": 66,
          "ExtSel": "",
     },
     "iMC.POWER_SELF_REFRESH": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the iMC is in self-refresh and the iMC still has a clock.  This happens in some package C-states.  For example, the PCU may ask the iMC to enter self-refresh even though some of the cores are still processing.  One use of this is for Monroe technology.  Self-refresh is required during package C3 and C6, but there is no clock in the iMC at this time, so it is not possible to count these cases.",
          "Desc": "Clock-Enabled Self-Refresh",
          "EvSel": 67,
          "ExtSel": "",
     },
     "iMC.POWER_THROTTLE_CYCLES": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
     },
     "iMC.POWER_THROTTLE_CYCLES.RANK6": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bx1xxxxxx",
     },
     "iMC.POWER_THROTTLE_CYCLES.RANK7": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "b1xxxxxxx",
     },
     "iMC.POWER_THROTTLE_CYCLES.RANK4": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "iMC.POWER_THROTTLE_CYCLES.RANK1": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.POWER_THROTTLE_CYCLES.RANK0": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.POWER_THROTTLE_CYCLES.RANK5": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxx1xxxxx",
     },
     "iMC.POWER_THROTTLE_CYCLES.RANK2": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "iMC.POWER_THROTTLE_CYCLES.RANK3": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles while the iMC is being throttled by either thermal constraints or by the PCU throttling.  It is not possible to distinguish between the two.  This can be filtered by rank.  If multiple ranks are selected and are being throttled at the same time, the counter will only increment by 1.",
          "Desc": "Throttle Cycles for Rank 0",
          "EvSel": 65,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "iMC.PREEMPTION": {
          "Box": "iMC",
          "Category": "iMC PREEMPTION Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
          "Desc": "Read Preemption Count",
          "EvSel": 8,
          "ExtSel": "",
     },
     "iMC.PREEMPTION.RD_PREEMPT_RD": {
          "Box": "iMC",
          "Category": "iMC PREEMPTION Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
          "Desc": "Read Preemption Count",
          "EvSel": 8,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.PREEMPTION.RD_PREEMPT_WR": {
          "Box": "iMC",
          "Category": "iMC PREEMPTION Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times a read in the iMC preempts another read or write.  Generally reads to an open page are issued ahead of requests to closed pages.  This improves the page hit rate of the system.  However, high priority requests can cause pages of active requests to be closed in order to get them out.  This will reduce the latency of the high-priority request at the expense of lower bandwidth and increased overall average latency.",
          "Desc": "Read Preemption Count",
          "EvSel": 8,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.PRE_COUNT": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
          "Desc": "DRAM Precharge commands.",
          "EvSel": 2,
          "ExtSel": "",
     },
     "iMC.PRE_COUNT.BYP": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
          "Desc": "DRAM Precharge commands.",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxx1xxxx",
     },
     "iMC.PRE_COUNT.RD": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
          "Desc": "DRAM Precharge commands.",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "iMC.PRE_COUNT.WR": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
          "Desc": "DRAM Precharge commands.",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "iMC.PRE_COUNT.PAGE_CLOSE": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
          "Desc": "DRAM Precharge commands.",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.PRE_COUNT.PAGE_MISS": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Counters": "0-3",
          "Defn": "Counts the number of DRAM Precharge commands sent on this channel.",
          "Desc": "DRAM Precharge commands.",
          "EvSel": 2,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.RD_CAS_PRIO": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "EvSel": 160,
          "ExtSel": "",
     },
     "iMC.RD_CAS_PRIO.HIGH": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "iMC.RD_CAS_PRIO.LOW": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.RD_CAS_PRIO.MED": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.RD_CAS_PRIO.PANIC": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "EvSel": 160,
          "ExtSel": "",
          "Umask": "bxxxx1xxx",
     },
     "iMC.RD_CAS_RANK0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
     },
     "iMC.RD_CAS_RANK0.BANK5": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00000101",
     },
     "iMC.RD_CAS_RANK0.BANK12": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00001100",
     },
     "iMC.RD_CAS_RANK0.BANK2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "iMC.RD_CAS_RANK0.BANK9": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00001001",
     },
     "iMC.RD_CAS_RANK0.BANK7": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00000111",
     },
     "iMC.RD_CAS_RANK0.BANKG0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00010001",
     },
     "iMC.RD_CAS_RANK0.BANKG3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00010100",
     },
     "iMC.RD_CAS_RANK0.ALLBANKS": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00010000",
     },
     "iMC.RD_CAS_RANK0.BANK3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00000011",
     },
     "iMC.RD_CAS_RANK0.BANK15": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00001111",
     },
     "iMC.RD_CAS_RANK0.BANKG1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00010010",
     },
     "iMC.RD_CAS_RANK0.BANKG2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00010011",
     },
     "iMC.RD_CAS_RANK0.BANK1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "iMC.RD_CAS_RANK0.BANK10": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00001010",
     },
     "iMC.RD_CAS_RANK0.BANK8": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00001000",
     },
     "iMC.RD_CAS_RANK0.BANK14": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00001110",
     },
     "iMC.RD_CAS_RANK0.BANK4": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00000100",
     },
     "iMC.RD_CAS_RANK0.BANK13": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00001101",
     },
     "iMC.RD_CAS_RANK0.BANK11": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00001011",
     },
     "iMC.RD_CAS_RANK0.BANK0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00000000",
     },
     "iMC.RD_CAS_RANK0.BANK6": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 0",
          "EvSel": 176,
          "ExtSel": "",
          "Umask": "b00000110",
     },
     "iMC.RD_CAS_RANK1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
     },
     "iMC.RD_CAS_RANK1.BANK13": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00001101",
     },
     "iMC.RD_CAS_RANK1.BANK4": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00000100",
     },
     "iMC.RD_CAS_RANK1.BANK0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00000000",
     },
     "iMC.RD_CAS_RANK1.BANK6": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00000110",
     },
     "iMC.RD_CAS_RANK1.BANK11": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00001011",
     },
     "iMC.RD_CAS_RANK1.BANK1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "iMC.RD_CAS_RANK1.BANK8": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00001000",
     },
     "iMC.RD_CAS_RANK1.BANK14": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00001110",
     },
     "iMC.RD_CAS_RANK1.BANK10": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00001010",
     },
     "iMC.RD_CAS_RANK1.BANK3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00000011",
     },
     "iMC.RD_CAS_RANK1.ALLBANKS": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00010000",
     },
     "iMC.RD_CAS_RANK1.BANKG1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00010010",
     },
     "iMC.RD_CAS_RANK1.BANKG2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00010011",
     },
     "iMC.RD_CAS_RANK1.BANK15": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00001111",
     },
     "iMC.RD_CAS_RANK1.BANK2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "iMC.RD_CAS_RANK1.BANK12": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00001100",
     },
     "iMC.RD_CAS_RANK1.BANK5": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00000101",
     },
     "iMC.RD_CAS_RANK1.BANK9": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00001001",
     },
     "iMC.RD_CAS_RANK1.BANK7": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00000111",
     },
     "iMC.RD_CAS_RANK1.BANKG3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00010100",
     },
     "iMC.RD_CAS_RANK1.BANKG0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 1",
          "EvSel": 177,
          "ExtSel": "",
          "Umask": "b00010001",
     },
     "iMC.RD_CAS_RANK2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 2",
          "EvSel": 178,
          "ExtSel": "",
     },
     "iMC.RD_CAS_RANK2.BANK13": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 2",
          "EvSel": 178,
          "ExtSel": "",
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          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 5",
          "EvSel": 181,
          "ExtSel": "",
          "Umask": "b00001100",
     },
     "iMC.RD_CAS_RANK5.BANK5": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 5",
          "EvSel": 181,
          "ExtSel": "",
          "Umask": "b00000101",
     },
     "iMC.RD_CAS_RANK5.BANKG0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 5",
          "EvSel": 181,
          "ExtSel": "",
          "Umask": "b00010001",
     },
     "iMC.RD_CAS_RANK5.BANKG3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 5",
          "EvSel": 181,
          "ExtSel": "",
          "Umask": "b00010100",
     },
     "iMC.RD_CAS_RANK5.BANK9": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 5",
          "EvSel": 181,
          "ExtSel": "",
          "Umask": "b00001001",
     },
     "iMC.RD_CAS_RANK5.BANK7": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 5",
          "EvSel": 181,
          "ExtSel": "",
          "Umask": "b00000111",
     },
     "iMC.RD_CAS_RANK6": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
     },
     "iMC.RD_CAS_RANK6.BANKG0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00010001",
     },
     "iMC.RD_CAS_RANK6.BANKG3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00010100",
     },
     "iMC.RD_CAS_RANK6.BANK9": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00001001",
     },
     "iMC.RD_CAS_RANK6.BANK7": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00000111",
     },
     "iMC.RD_CAS_RANK6.BANK5": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00000101",
     },
     "iMC.RD_CAS_RANK6.BANK12": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00001100",
     },
     "iMC.RD_CAS_RANK6.BANK2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "iMC.RD_CAS_RANK6.BANK15": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00001111",
     },
     "iMC.RD_CAS_RANK6.BANKG2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00010011",
     },
     "iMC.RD_CAS_RANK6.BANKG1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00010010",
     },
     "iMC.RD_CAS_RANK6.BANK3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00000011",
     },
     "iMC.RD_CAS_RANK6.ALLBANKS": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00010000",
     },
     "iMC.RD_CAS_RANK6.BANK10": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00001010",
     },
     "iMC.RD_CAS_RANK6.BANK14": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00001110",
     },
     "iMC.RD_CAS_RANK6.BANK8": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00001000",
     },
     "iMC.RD_CAS_RANK6.BANK1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "iMC.RD_CAS_RANK6.BANK11": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00001011",
     },
     "iMC.RD_CAS_RANK6.BANK6": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00000110",
     },
     "iMC.RD_CAS_RANK6.BANK0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00000000",
     },
     "iMC.RD_CAS_RANK6.BANK4": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00000100",
     },
     "iMC.RD_CAS_RANK6.BANK13": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 6",
          "EvSel": 182,
          "ExtSel": "",
          "Umask": "b00001101",
     },
     "iMC.RD_CAS_RANK7": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
     },
     "iMC.RD_CAS_RANK7.BANK11": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00001011",
     },
     "iMC.RD_CAS_RANK7.BANK6": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00000110",
     },
     "iMC.RD_CAS_RANK7.BANK0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00000000",
     },
     "iMC.RD_CAS_RANK7.BANK4": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00000100",
     },
     "iMC.RD_CAS_RANK7.BANK13": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00001101",
     },
     "iMC.RD_CAS_RANK7.BANK10": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00001010",
     },
     "iMC.RD_CAS_RANK7.BANK8": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00001000",
     },
     "iMC.RD_CAS_RANK7.BANK14": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00001110",
     },
     "iMC.RD_CAS_RANK7.BANK1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "iMC.RD_CAS_RANK7.BANK15": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00001111",
     },
     "iMC.RD_CAS_RANK7.BANKG2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00010011",
     },
     "iMC.RD_CAS_RANK7.BANKG1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00010010",
     },
     "iMC.RD_CAS_RANK7.BANK3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00000011",
     },
     "iMC.RD_CAS_RANK7.ALLBANKS": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00010000",
     },
     "iMC.RD_CAS_RANK7.BANKG0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00010001",
     },
     "iMC.RD_CAS_RANK7.BANKG3": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00010100",
     },
     "iMC.RD_CAS_RANK7.BANK9": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00001001",
     },
     "iMC.RD_CAS_RANK7.BANK7": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00000111",
     },
     "iMC.RD_CAS_RANK7.BANK5": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00000101",
     },
     "iMC.RD_CAS_RANK7.BANK12": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00001100",
     },
     "iMC.RD_CAS_RANK7.BANK2": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "RD_CAS Access to Rank 7",
          "EvSel": 183,
          "ExtSel": "",
          "Umask": "b00000010",
     },
     "iMC.RPQ_CYCLES_FULL": {
          "Box": "iMC",
          "Category": "iMC RPQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the Read Pending Queue is full.  When the RPQ is full, the HA will not be able to issue any additional read requests into the iMC.  This count should be similar count in the HA which tracks the number of cycles that the HA has no RPQ credits, just somewhat smaller to account for the credit return overhead.  We generally do not expect to see RPQ become full except for potentially during Write Major Mode or while running with slow DRAM.  This event only tracks non-ISOC queue entries.",
          "Desc": "Read Pending Queue Full Cycles",
          "EvSel": 18,
          "ExtSel": "",
     },
     "iMC.RPQ_CYCLES_NE": {
          "Box": "iMC",
          "Category": "iMC RPQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles that the Read Pending Queue is not empty.  This can then be used to calculate the average occupancy (in conjunction with the Read Pending Queue Occupancy count).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This filter is to be used in conjunction with the occupancy filter so that one can correctly track the average occupancies for schedulable entries and scheduled requests.",
          "Desc": "Read Pending Queue Not Empty",
          "EvSel": 17,
          "ExtSel": "",
     },
     "iMC.RPQ_INSERTS": {
          "Box": "iMC",
          "Category": "iMC RPQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the Read Pending Queue.  This queue is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC.  They deallocate after the CAS command has been issued to memory.  This includes both ISOCH and non-ISOCH requests.",
          "Desc": "Read Pending Queue Allocations",
          "EvSel": 16,
          "ExtSel": "",
     },
     "iMC.RPQ_OCCUPANCY": {
          "Box": "iMC",
          "Category": "iMC RPQ Events",
          "Counters": "0-3",
          "Defn": "Accumulates the occupancies of the Read Pending Queue each cycle.  This can then be used to calculate both the average occupancy (in conjunction with the number of cycles not empty) and the average latency (in conjunction with the number of allocations).  The RPQ is used to schedule reads out to the memory controller and to track the requests.  Requests allocate into the RPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the HA to the iMC. They deallocate after the CAS command has been issued to memory.",
          "Desc": "Read Pending Queue Occupancy",
          "EvSel": 128,
          "ExtSel": "",
     },
     "iMC.WMM_TO_RMM": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Desc": "Transition from WMM to RMM because of low threshold",
          "EvSel": 192,
          "ExtSel": "",
     },
     "iMC.WMM_TO_RMM.STARVE": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Desc": "Transition from WMM to RMM because of low threshold",
          "EvSel": 192,
          "ExtSel": "",
          "Umask": "bxxxxxx1x",
     },
     "iMC.WMM_TO_RMM.VMSE_RETRY": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Desc": "Transition from WMM to RMM because of low threshold",
          "EvSel": 192,
          "ExtSel": "",
          "Umask": "bxxxxx1xx",
     },
     "iMC.WMM_TO_RMM.LOW_THRESH": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Desc": "Transition from WMM to RMM because of low threshold",
          "EvSel": 192,
          "ExtSel": "",
          "Umask": "bxxxxxxx1",
     },
     "iMC.WPQ_CYCLES_FULL": {
          "Box": "iMC",
          "Category": "iMC WPQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles when the Write Pending Queue is full.  When the WPQ is full, the HA will not be able to issue any additional write requests into the iMC.  This count should be similar count in the CHA which tracks the number of cycles that the CHA has no WPQ credits, just somewhat smaller to account for the credit return overhead.",
          "Desc": "Write Pending Queue Full Cycles",
          "EvSel": 34,
          "ExtSel": "",
     },
     "iMC.WPQ_CYCLES_NE": {
          "Box": "iMC",
          "Category": "iMC WPQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of cycles that the Write Pending Queue is not empty.  This can then be used to calculate the average queue occupancy (in conjunction with the WPQ Occupancy Accumulation count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have \"posted\" to the iMC.  This is not to be confused with actually performing the write to DRAM.  Therefore, the average latency for this queue is actually not useful for deconstruction intermediate write latencies.",
          "Desc": "Write Pending Queue Not Empty",
          "EvSel": 33,
          "ExtSel": "",
     },
     "iMC.WPQ_INSERTS": {
          "Box": "iMC",
          "Category": "iMC WPQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of allocations into the Write Pending Queue.  This can then be used to calculate the average queuing latency (in conjunction with the WPQ occupancy count).  The WPQ is used to schedule write out to the memory controller and to track the writes.  Requests allocate into the WPQ soon after they enter the memory controller, and need credits for an entry in this buffer before being sent from the CHA to the iMC.  They deallocate after being issued to DRAM.  Write requests themselves are able to complete (from the perspective of the rest of the system) as soon they have \"posted\" to the iMC.",
          "Desc": "Write Pending Queue Allocations",
          "EvSel": 32,
          "ExtSel": "",
     },
     "iMC.WPQ_READ_HIT": {
          "Box": "iMC",
          "Category": "iMC WPQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
          "Desc": "Write Pending Queue CAM Match",
          "EvSel": 35,
          "ExtSel": "",
     },
     "iMC.WPQ_WRITE_HIT": {
          "Box": "iMC",
          "Category": "iMC WPQ Events",
          "Counters": "0-3",
          "Defn": "Counts the number of times a request hits in the WPQ (write-pending queue).  The iMC allows writes and reads to pass up other writes to different addresses.  Before a read or a write is issued, it will first CAM the WPQ to see if there is a write pending to that address.  When reads hit, they are able to directly pull their data from the WPQ instead of going to memory.  Writes that hit will overwrite the existing data.  Partial writes that hit will not need to do underfill reads and will simply update their relevant sections.",
          "Desc": "Write Pending Queue CAM Match",
          "EvSel": 36,
          "ExtSel": "",
     },
     "iMC.WRONG_MM": {
          "Box": "iMC",
          "Category": "iMC MAJOR_MODES Events",
          "Counters": "0-3",
          "Desc": "Not getting the requested Major Mode",
          "EvSel": 193,
          "ExtSel": "",
     },
     "iMC.WR_CAS_RANK0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 0",
          "EvSel": 184,
          "ExtSel": "",
     },
     "iMC.WR_CAS_RANK0.BANK1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 0",
          "EvSel": 184,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "iMC.WR_CAS_RANK0.BANK14": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 0",
          "EvSel": 184,
          "ExtSel": "",
          "Umask": "b00001110",
     },
     "iMC.WR_CAS_RANK0.BANK8": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 0",
          "EvSel": 184,
          "ExtSel": "",
          "Umask": "b00001000",
     },
     "iMC.WR_CAS_RANK0.BANK10": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 0",
          "EvSel": 184,
          "ExtSel": "",
          "Umask": "b00001010",
     },
     "iMC.WR_CAS_RANK0.BANK13": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 0",
          "EvSel": 184,
          "ExtSel": "",
          "Umask": "b00001101",
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          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00001111",
     },
     "iMC.WR_CAS_RANK7.BANK1": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00000001",
     },
     "iMC.WR_CAS_RANK7.BANK8": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00001000",
     },
     "iMC.WR_CAS_RANK7.BANK14": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00001110",
     },
     "iMC.WR_CAS_RANK7.BANK10": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00001010",
     },
     "iMC.WR_CAS_RANK7.BANK13": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00001101",
     },
     "iMC.WR_CAS_RANK7.BANK4": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00000100",
     },
     "iMC.WR_CAS_RANK7.BANK0": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00000000",
     },
     "iMC.WR_CAS_RANK7.BANK6": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00000110",
     },
     "iMC.WR_CAS_RANK7.BANK11": {
          "Box": "iMC",
          "Category": "iMC CAS Events",
          "Counters": "0-3",
          "Desc": "WR_CAS Access to Rank 7",
          "EvSel": 191,
          "ExtSel": "",
          "Umask": "b00001011",
     },
}
derived = {
     
# iMC:
     "iMC.MEM_BW_READS": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Defn": "Memory bandwidth consumed by reads.  Expressed in bytes.",
          "Desc": "Read Memory Bandwidth",
          "Equation": "(CAS_COUNT.RD * 64)",
     },
     "iMC.MEM_BW_TOTAL": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Defn": "Total memory bandwidth.  Expressed in bytes.",
          "Desc": "Total Memory Bandwidth",
          "Equation": "MEM_BW_READS + MEM_BW_WRITES",
     },
     "iMC.MEM_BW_WRITES": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Defn": "Memory bandwidth consumed by writes  Expressed in bytes.",
          "Desc": "Write Memory Bandwidth",
          "Equation": "(CAS_COUNT.WR * 64)",
     },
     "iMC.PCT_CYCLES_CRITICAL_THROTTLE": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Defn": "The percentage of cycles all DRAM ranks in critical thermal throttling",
          "Desc": "Percent Cycles Critical Throttle",
          "Equation": "POWER_CRITICAL_THROTTLE_CYCLES / MC_Chy_PCI_PMON_CTR_FIXED",
     },
     "iMC.PCT_CYCLES_DLLOFF": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Defn": "The percentage of cycles all DRAM ranks in CKE slow (DLOFF) mode",
          "Desc": "Percent Cycles DLOFF",
          "Equation": "POWER_CHANNEL_DLLOFF / MC_Chy_PCI_PMON_CTR_FIXED",
     },
     "iMC.PCT_CYCLES_DRAM_RANKx_IN_CKE": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Defn": "The percentage of cycles DRAM rank (x) spent in CKE ON mode.",
          "Desc": "Percent Cycles DRAM Rank x in CKE",
          "Equation": "POWER_CKE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED",
     },
     "iMC.PCT_CYCLES_DRAM_RANKx_IN_THR": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Defn": "The percentage of cycles DRAM rank (x) spent in thermal throttling.",
          "Desc": "Percent Cycles DRAM Rank x in CKE",
          "Equation": "POWER_THROTTLE_CYCLES.RANKx / MC_Chy_PCI_PMON_CTR_FIXED",
     },
     "iMC.PCT_CYCLES_PPD": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Defn": "The percentage of cycles all DRAM ranks in PPD mode",
          "Desc": "Percent Cycles PPD",
          "Equation": "POWER_CHANNEL_PPD / MC_Chy_PCI_PMON_CTR_FIXED",
     },
     "iMC.PCT_CYCLES_SELF_REFRESH": {
          "Box": "iMC",
          "Category": "iMC POWER Events",
          "Defn": "The percentage of cycles Memory is in self refresh power mode",
          "Desc": "Percent Cycles Self Refresh",
          "Equation": "POWER_SELF_REFRESH / MC_Chy_PCI_PMON_CTR_FIXED",
     },
     "iMC.PCT_RD_REQUESTS": {
          "Box": "iMC",
          "Category": "iMC RPQ Events",
          "Defn": "Percentage of read requests from total requests.",
          "Desc": "Percent Read Requests",
          "Equation": "RPQ_INSERTS / (RPQ_INSERTS + WPQ_INSERTS)",
     },
     "iMC.PCT_REQUESTS_PAGE_EMPTY": {
          "Box": "iMC",
          "Category": "iMC ACT Events",
          "Defn": "Percentage of memory requests that resulted in Page Empty",
          "Desc": "Percent Requests Page Empty",
          "Equation": "(ACT_COUNT - PRE_COUNT.PAGE_MISS)/ (CAS_COUNT.RD + CAS_COUNT.WR)",
     },
     "iMC.PCT_REQUESTS_PAGE_HIT": {
          "Box": "iMC",
          "Category": "iMC ACT Events",
          "Defn": "Percentage of memory requests that resulted in Page Hits",
          "Desc": "Percent Requests Page Hit",
          "Equation": "1 - (PCT_REQUESTS_PAGE_EMPTY + PCT_REQUESTS_PAGE_MISS)",
     },
     "iMC.PCT_REQUESTS_PAGE_MISS": {
          "Box": "iMC",
          "Category": "iMC PRE Events",
          "Defn": "Percentage of memory requests that resulted in Page Misses",
          "Desc": "Percent Requests Page Miss",
          "Equation": "PRE_COUNT.PAGE_MISS / (CAS_COUNT.RD + CAS_COUNT.WR)",
     },
     "iMC.PCT_WR_REQUESTS": {
          "Box": "iMC",
          "Category": "iMC WPQ Events",
          "Defn": "Percentage of write requests from total requests.",
          "Desc": "Percent Write Requests",
          "Equation": "WPQ_INSERTS / (RPQ_INSERTS + WPQ_INSERTS)",
     },
     
# rxl_hdr:
     "rxl_hdr.AVG_DEMAND_RD_MISS_REMOTE_LATENCY": {
          "Box": "rxl_hdr",
          "Category": "rxl_hdr TOR Events",
          "Defn": "Average Latency of Data Reads from an iA Core that miss the LLC and were satsified by a Remote cache or Remote Memory",
          "Desc": "Average Data Read Remote Miss Latency",
          "Equation": "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,0,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     
# UPI_LL:
    "DRS_E_FROM_UPI": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CTO Events",
          "Defn": "DRS response in F or E states received from UPI in bytes.  To calculate the total data response for each cache line state, it's necessary to add the contribution from three flavors {DataC, DataC_FrcAckCnflt, DataC_Cmp} of data response packets for each cache line state.",
          "Desc": "DRS Data in F or E From UPI",
          "Equation": "RxL_BASIC_HDR_MATCH with:{umask=0x1c,opc=1}  * 64",
     },
     "UPI_LL.DRS_M_FROM_UPI": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CTO Events",
          "Defn": "Data Response DataM packets received from UPI.  Expressed in bytes",
          "Desc": "DRS Data_Ms From UPI",
          "Equation": "RxL_BASIC_HDR_MATCH with:{umask=0x0C,opc=1}  * 64",
     },
     "UPI_LL.DRS_WB_FROM_UPI": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CTO Events",
          "Defn": "DRS writeback packets received from UPI in bytes.  This is the sum of Wb{I,S,E} DRS packets",
          "Desc": "DRS Writeback From UPI",
          "Equation": "DRS_WbI_FROM_UPI + DRS_WbS_FROM_UPI + DRS_WbE_FROM_UPI",
     },
     "UPI_LL.DRS_WbE_FROM_UPI": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CTO Events",
          "Defn": "DRS writeback 'change M to E state' packets received from UPI in bytes",
          "Desc": "DRS WbE From UPI",
          "Equation": "RxL_BASIC_HDR_MATCH with:{umask=0x2d,opc=1}  *64",
     },
     "UPI_LL.DRS_WbI_FROM_UPI": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CTO Events",
          "Defn": "DRS writeback 'change M to I state' packets received from UPI in bytes",
          "Desc": "DRS WbI From UPI",
          "Equation": "RxL_BASIC_HDR_MATCH with:{umask=0x0D,opc=1} *64",
     },
     "UPI_LL.DRS_WbS_FROM_UPI": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CTO Events",
          "Defn": "DRS writeback 'change M to S state' packets received from UPI in bytes",
          "Desc": "DRS WbSFrom UPI",
          "Equation": "RxL_BASIC_HDR_MATCH with:{umask=0x1D,opc=1}  *64",
     },
     "UPI_LL.NCB_DATA_FROM_UPI_TO_NODEx": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CTO Events",
          "Defn": "NCB Data packets (Any - Interrupts) received from UPI sent to Node ID 'x'.  Expressed in bytes",
          "Desc": "NCB Data From UPI To Node x",
          "Equation": "RxL_BASIC_HDR_MATCH with:{umask=0xE,endnid=1,dnid=x} * 64",
     },
     "UPI_LL.PCT_LINK_CRC_RETRY_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL CRC_ERRORS_RX Events",
          "Defn": "Percent of Cycles the UPI link layer is in retry mode due to CRC errors",
          "Desc": "Percent Link CRC Retry Cycles",
          "Equation": "RxL_CRC_CYCLES_IN_LLR / CLOCKTICKS",
     },
     "UPI_LL.PCT_LINK_FULL_POWER_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_RX Events",
          "Defn": "Percent of Cycles the UPI link is at Full Power",
          "Desc": "Percent Link Full Power Cycles",
          "Equation": "RxL0_POWER_CYCLES / CLOCKTICKS",
     },
     "UPI_LL.PCT_LINK_HALF_DISABLED_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER_RX Events",
          "Defn": "Percent of Cycles the UPI link in power mode where 60% of the lanes are disabled.",
          "Desc": "Percent Link Half Disabled Cycles",
          "Equation": "RxL0P_POWER_CYCLES / CLOCKTICKS",
     },
     "UPI_LL.PCT_LINK_SHUTDOWN_CYCLES": {
          "Box": "UPI_LL",
          "Category": "UPI_LL POWER Events",
          "Defn": "Percent of Cycles the UPI link is Shutdown",
          "Desc": "Percent Link Shutdown Cycles",
          "Equation": "L1_POWER_CYCLES / CLOCKTICKS",
     },
     
# CHA:
     "CHA.AVG_CRD_MISS_LATENCY": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Average Latency of Code Reads from an iA Core that miss the LLC",
          "Desc": "Average Code Read Latency",
          "Equation": "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x259,0x201,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.AVG_DEMAND_RD_HIT_LATENCY": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Average Latency of Data Reads that hit the LLC",
          "Desc": "Average Data Read Hit Latency",
          "Equation": "TOR_OCCUPANCY.ALL_HIT / (TOR_INSERTS.ALL_HIT with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,1,1})",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.AVG_DEMAND_RD_MISS_LOCAL_LATENCY": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Average Latency of Data Reads from an IA Core that miss the LLC and were satsified by Local Memory",
          "Desc": "Average Data Read Local Miss Latency",
          "Equation": "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,1,0}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.AVG_DRD_MISS_LATENCY": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Average Latency of Data Reads or Data Read Prefetches from an IA Core that miss the LLC",
          "Desc": "Average Data Read Miss Latency",
          "Equation": "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc1, opc0,not_nm,nm,all_opc,loc,rem}={0x25A,0x202,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.AVG_IA_CRD_LLC_HIT_LATENCY": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Average Latency of Code Reads from an iA Core that miss the LLC",
          "Desc": "Average Code Read Latency",
          "Equation": "(TOR_OCCUPANCY.IA_HIT / TOR_INSERTS.IA_HIT) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x201,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.AVG_INGRESS_DEPTH": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Defn": "Average Depth of the Ingress Queue through the sample interval",
          "Desc": "Average Ingress (from CMS) Depth",
          "Equation": "RxC_OCCUPANCY.IRQ  / SAMPLE_INTERVAL",
     },
     "CHA.AVG_INGRESS_LATENCY": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Defn": "Average Latency of Requests through the Ingress Queue in Uncore Clocks",
          "Desc": "Average Ingress (from CMS) Latency",
          "Equation": "RxC_OCCUPANCY.IRQ / RxC_INSERTS.IRQ",
     },
     "CHA.AVG_INGRESS_LATENCY_WHEN_NE": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Defn": "Average Latency of Requests through the Ingress Queue in Uncore Clocks when Ingress Queue has at least one entry",
          "Desc": "Average Latency in Non-Empty Ingress (from CMS)",
          "Equation": "RxC_OCCUPANCY.IRQ / COUNTER0_OCCUPANCY{edge_det,thresh=0x1}",
     },
     "CHA.AVG_RFO_MISS_LATENCY": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Average Latency of RFOs from an iA Core that miss the LLC",
          "Desc": "Average RFO Latency",
          "Equation": "(TOR_OCCUPANCY.IA_MISS / TOR_INSERTS.IA_MISS) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x200,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.AVG_TOR_DRDS_MISS_WHEN_NE": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Average Number of Data Read Entries that Miss the LLC when the TOR is not empty.",
          "Desc": "Average Data Read Misses in Non-Empty TOR",
          "Equation": "(TOR_OCCUPANCY.ALL_MISS / COUNTER0_OCCUPANCY{edge_det,thresh=0x1}) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.AVG_TOR_DRDS_WHEN_NE": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Average Number of Data Read Entries when the TOR is not empty.",
          "Desc": "Average Data Reads in Non-Empty TOR",
          "Equation": "(TOR_OCCUPANCY.ALL / COUNTER0_OCCUPANCY{edge_det,thresh=0x1}) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x202,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.CYC_INGRESS_BLOCKED": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Defn": "Cycles the Ingress Request Queue arbiter was Blocked",
          "Desc": "Cycles Ingress (from CMS) Blocked",
          "Equation": "RxC_EXT_STARVED.IRQ  / SAMPLE_INTERVAL",
     },
     "CHA.FAST_STR_LLC_HIT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Number of ItoM (fast string) operations that reference the LLC",
          "Desc": "Fast String operations",
          "Equation": "TOR_INSERTS.IA_HIT with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x248,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.FAST_STR_LLC_MISS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Number of ItoM (fast string) operations that miss the LLC",
          "Desc": "Fast String misses",
          "Equation": "TOR_INSERTS.IA_MISS with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x248,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.INGRESS_REJ_V_INS": {
          "Box": "CHA",
          "Category": "CHA INGRESS Events",
          "Defn": "Ratio of Ingress Request Entries that were rejected vs. inserted",
          "Desc": "Ingress (from CMS) Rejects vs. Inserts",
          "Equation": "RxC_INSERTS.IRQ_REJECTED  / RxC_INSERTS.IRQ",
     },
     "CHA.LLC_CRD_MISS_TO_LOC_MEM": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC Code Read and Code Prefetch misses satisfied by local memory.",
          "Desc": "LLC Code Read Misses to Local Memory",
          "Equation": "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x259,0x201,1,1,0,1,0}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_CRD_MISS_TO_REM_MEM": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC Code Read and Code Read Prefetch misses satisfied by a remote cache or remote memory.",
          "Desc": "LLC Code Read Misses to Remote Memory",
          "Equation": "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x259,0x201,1,1,0,0,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_DRD_MISS_PCT": {
          "Box": "CHA",
          "Category": "CHA CACHE Events",
          "Desc": "LLC DRd Miss Percentage",
          "Equation": "LLC_LOOKUP.DATA_READ with:Cn_MSR_PMON_BOX_FILTER0.state=0x1 / LLC_LOOKUP.DATA_READ with:Cn_MSR_PMON_BOX_FILTER0.state=0xF1",
          "Filter": "CHAFilter0[26:17]",
     },
     "CHA.LLC_DRD_MISS_TO_LOC_MEM": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC Data Read and Data Prefetch misses satisfied by local memory.",
          "Desc": "LLC Data Read Misses to Local Memory",
          "Equation": "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x25A,0x202,1,1,0,1,0}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_DRD_MISS_TO_REM_MEM": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC Data Read and Data Prefetch misses satisfied by a remote cache or remote memory.",
          "Desc": "LLC Data Read Misses to Remote Memory",
          "Equation": "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x25A,0x202,1,1,0,0,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_DRD_PREFETCH_HITS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Desc": "DRd Prefetches that Hit the LLC",
          "Equation": "TOR_INSERTS.IA_HIT  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x25A,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_DRD_PREFETCH_MISSES": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Desc": "DRd Prefetches that Missed the LLC",
          "Equation": "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x25A,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_IA_CRD_HITS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC Code Read and Code Prefetch misses satisfied by local memory.",
          "Desc": "LLC Code Read Misses to Local Memory",
          "Equation": "TOR_INSERTS.IA_HIT  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x201,1,1,0,1,0}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_PCIE_DATA_BYTES": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC write miss (disk/network reads) bandwidth in MB",
          "Desc": "LLC Miss Data from PCIe",
          "Equation": "TOR_INSERTS.IO with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x248,1,1,0,1,1} * 64",
          "Filter": "CHAFilter0[8:0], (CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.LLC_RFO_MISS_PCT": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC RFO Miss Ratio",
          "Desc": "LLC RFO Miss Ratio",
          "Equation": "(TOR_INSERTS.ALL_MISS / TOR_INSERTS.ALL) with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x200,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.LLC_RFO_MISS_TO_LOC_MEM": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC  RFO and RFO Prefetch misses satisfied by local memory.",
          "Desc": "LLC RFO Misses to Local Memory",
          "Equation": "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x258,0x200,1,1,0,1,0}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_RFO_MISS_TO_REM_MEM": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "LLC RFO and RFO Prefetch misses satisfied by a remote cache or remote memory.",
          "Desc": "LLC RFO Misses to Remote Memory",
          "Equation": "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc1,opc0,not_nm,nm,all_opc,loc,rem}={0x258,0x200,1,1,0,0,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_RFO_PREFETCH_HITS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Desc": "RFO Prefetches that Hit the LLC",
          "Equation": "TOR_INSERTS.IA_HIT  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x258,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.LLC_RFO_PREFETCH_MISSES": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Desc": "RFO Prefetches that Missed the LLC",
          "Equation": "TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x258,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9]), CHAFilter1[1:0]",
     },
     "CHA.MMIO_READ_BW": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "IO Read Bandwidth in MB - Disk or Network Reads",
          "Desc": "IO Read Bandwidth",
          "Equation": "(TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{nc,opc0,not_nm,nm,all_opc,loc,rem}={1,0x20E,1,1,0,1,1}) * 64 / 1000000",
          "Filter": "CHAFilter0[8:0], (CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.MMIO_WRITE_BW": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "IO Write Bandwidth in MB - Disk or Network Writes",
          "Desc": "IO Write Bandwidth",
          "Equation": "(TOR_INSERTS.IA_MISS  with:Cn_MSR_PMON_BOX_FILTER1.{nc,opc0,not_nm,nm,all_opc,loc,rem}={1,0x20F,1,1,0,1,1}) * 64 / 1000000",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.PCIE_FULL_WRITES": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Number of full PCI writes",
          "Desc": "PCIe Data Traffic",
          "Equation": "TOR_INSERTS.IO with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x248,1,1,0,1,1}",
          "Filter": "CHAFilter0[8:0], (CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.PCI_PARTIAL_WRITES": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Number of partial PCI writes",
          "Desc": "Partial PCI Writes",
          "Equation": "TOR_INSERTS.IO with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x200,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.PCI_READS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Number of  PCI reads",
          "Desc": "Partial PCI Reads",
          "Equation": "TOR_INSERTS.IO with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x21E,1,1,0,1,1}",
          "Filter": "CHAFilter0[8:0], (CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.PCT_RD_REQUESTS": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Percentage of HA traffic that is from Read Requests",
          "Desc": "Percent Read Requests",
          "Equation": "REQUESTS.READS / (REQUESTS.READS + REQUESTS.WRITES)",
     },
     "CHA.PCT_WR_REQUESTS": {
          "Box": "CHA",
          "Category": "CHA HA REQUEST Events",
          "Defn": "Percentage of HA traffic that is from Write Requests",
          "Desc": "Percent Write Requests",
          "Equation": "REQUESTS.WRITES / (REQUESTS.READS + REQUESTS.WRITES)",
     },
     "CHA.STREAMED_FULL_STORES": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Number of Streamed Store (of Full Cache Line) Transactions",
          "Desc": "Streaming Stores (Full Line)",
          "Equation": "TOR_INSERTS.IA with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x20C,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.STREAMED_PART_STORES": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Number of Streamed Store (of Partial Cache Line) Transactions",
          "Desc": "Streaming Stores (Partial Line)",
          "Equation": "TOR_INSERTS.IA with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x20D,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     "CHA.UC_READS": {
          "Box": "CHA",
          "Category": "CHA TOR Events",
          "Defn": "Uncachable Read Transactions",
          "Desc": "Uncacheable Reads",
          "Equation": "TOR_INSERTS.IA_MISS with:Cn_MSR_PMON_BOX_FILTER1.{opc0,not_nm,nm,all_opc,loc,rem}={0x207,1,1,0,1,1}",
          "Filter": "(CHAFilter1[28:19] | CHAFilter1[18:9])",
     },
     
# PCU:
     "PCU.PCT_CYC_FREQ_CURRENT_LTD": {
          "Box": "PCU",
          "Category": "PCU FREQ_MAX_LIMIT Events",
          "Defn": "Percentage of Cycles the Max Frequency is limited by current",
          "Desc": "Percent Frequency Current Limited",
          "Equation": "FREQ_MAX_CURRENT_CYCLES / CLOCKTICKS",
     },
     "PCU.PCT_CYC_FREQ_POWER_LTD": {
          "Box": "PCU",
          "Category": "PCU FREQ_MAX_LIMIT Events",
          "Defn": "Percentage of Cycles the Max Frequency is limited by power",
          "Desc": "Percent Frequency Power Limited",
          "Equation": "FREQ_MAX_POWER_CYCLES / CLOCKTICKS",
     },
     "PCU.PCT_CYC_FREQ_THERMAL_LTD": {
          "Box": "PCU",
          "Category": "PCU FREQ_MAX_LIMIT Events",
          "Defn": "Percentage of Cycles the Max Frequency is limited by thermal issues",
          "Desc": "Percent Frequency Thermal Limited",
          "Equation": "FREQ_MAX_CURRENT_CYCLES / CLOCKTICKS",
     },
     "PCU.s": {
          "Box": "PCU",
          "Category": "PCU FREQ_MAX_LIMIT Events",
          "Defn": "Percentage of Cycles the Max Frequency is limited by the OS",
          "Desc": "Percent Frequency OS Limited",
          "Equation": "FREQ_MAX_OS_CYCLES / CLOCKTICKS",
     },
}
categories = (
     "CHA CACHE Events",
     "CHA CMS Horizontal EGRESS Events",
     "CHA CMS Transgress Credit Events",
     "CHA CMS Transgress INGRESS Events",
     "CHA CMS Vertical EGRESS Events",
     "CHA HA BYPASS Events",
     "CHA HA DIRECTORY Events",
     "CHA HA HitME Events",
     "CHA HA HitME Pipe Events",
     "CHA HA IODC Events",
     "CHA HA OSB Events",
     "CHA HA READ WRITE Events",
     "CHA HA REQUEST Events",
     "CHA HA SNOOP RESPONSE Events",
     "CHA HA WBPUSHMTOI Events",
     "CHA Horizontal  RING Events",
     "CHA Horizontal In Use RING Events",
     "CHA INGRESS Events",
     "CHA INGRESS_RETRY Events",
     "CHA ISMQ Events",
     "CHA MISC Events",
     "CHA Misc Events",
     "CHA OCCUPANCY Events",
     "CHA TOR Events",
     "CHA UCLK Events",
     "CHA Vertical In Use RING Events",
     "CHA Vertical RING Events",
     "IIO CLOCK Events",
     "IIO Debug Events",
     "IIO Link Events",
     "IIO Miscellaneous Events",
     "IIO PCIe Completion Buffer Events",
     "IIO Payload Events",
     "IIO Transaction Events",
     "IIO VTd Events",
     "IRP AK Egress Events",
     "IRP BL Egress Events",
     "IRP CLOCK Events",
     "IRP Coherency Events",
     "IRP FAF Events",
     "IRP IRP Buffer Events",
     "IRP MISC Events",
     "IRP OUTBOUND_REQUESTS Events",
     "IRP P2P Events",
     "IRP STALL_CYCLES Events",
     "IRP TRANSACTIONS Events",
     "IRP WRITE_CACHE Events",
     "M2M AD CMS/Mesh Egress Credit Events",
     "M2M AD Egress Events",
     "M2M AD Ingress Events",
     "M2M AK CMS/Mesh Egress Credit Events",
     "M2M AK Egress Events",
     "M2M BL CMS/Mesh Egress Credit Events",
     "M2M BL Egress Events",
     "M2M BL Ingress Events",
     "M2M CAM Prefetch Events",
     "M2M CMS Horizontal EGRESS Events",
     "M2M CMS Transgress Credit Events",
     "M2M CMS Transgress INGRESS Events",
     "M2M CMS Vertical EGRESS Events",
     "M2M DIRECT2CORE Events",
     "M2M DIRECT2UPI Events",
     "M2M DIRECTORY Events",
     "M2M Directory State Events",
     "M2M Horizontal  RING Events",
     "M2M Horizontal In Use RING Events",
     "M2M IMC Events",
     "M2M Misc Events",
     "M2M OUTBOUND_TX Events",
     "M2M PACKET MATCH Events",
     "M2M RPQ CREDIT Events",
     "M2M TRACKER Events",
     "M2M Transgress/M2MIngress Credit Events",
     "M2M UCLK Events",
     "M2M Vertical In Use RING Events",
     "M2M Vertical RING Events",
     "M2M WPQ_CREDITS Events",
     "M2PCIe CMS Horizontal EGRESS Events",
     "M2PCIe CMS Transgress Credit Events",
     "M2PCIe CMS Transgress INGRESS Events",
     "M2PCIe CMS Vertical EGRESS Events",
     "M2PCIe EGRESS Events",
     "M2PCIe Horizontal  RING Events",
     "M2PCIe Horizontal In Use RING Events",
     "M2PCIe IIO_CREDITS Events",
     "M2PCIe INGRESS Events",
     "M2PCIe Misc Events",
     "M2PCIe UCLK Events",
     "M2PCIe Vertical In Use RING Events",
     "M2PCIe Vertical RING Events",
     "M3UPI ARB Events",
     "M3UPI CMS Horizontal EGRESS Events",
     "M3UPI CMS Transgress Credit Events",
     "M3UPI CMS Transgress INGRESS Events",
     "M3UPI CMS Vertical EGRESS Events",
     "M3UPI EGRESS Credit Events",
     "M3UPI FlowQ Events",
     "M3UPI Horizontal  RING Events",
     "M3UPI Horizontal In Use RING Events",
     "M3UPI INGRESS Arbitration Events",
     "M3UPI INGRESS Credit Events",
     "M3UPI INGRESS Events",
     "M3UPI INGRESS Flit Events",
     "M3UPI INGRESS Sloting Events",
     "M3UPI Link VN Credit Events",
     "M3UPI Misc Events",
     "M3UPI Special Egress Events",
     "M3UPI UCLK Events",
     "M3UPI Vertical In Use RING Events",
     "M3UPI Vertical RING Events",
     "PCU CORE_C_STATE_TRANSITION Events",
     "PCU FIVR Events",
     "PCU FREQ_MAX_LIMIT Events",
     "PCU FREQ_MIN_LIMIT Events",
     "PCU FREQ_TRANS Events",
     "PCU MEMORY_PHASE_SHEDDING Events",
     "PCU Misc Events",
     "PCU PKG_C_STATE_RESIDENCY Events",
     "PCU PROCHOT Events",
     "PCU VR_HOT Events",
     "UBOX EVENT_MSG Events",
     "UBOX LOCK Events",
     "UBOX PHOLD Events",
     "UBOX RACU Events",
     "UPI_LL CFCLK Events",
     "UPI_LL CRC_ERRORS_RX Events",
     "UPI_LL CTO Events",
     "UPI_LL DIRECT2CORE Events",
     "UPI_LL FLIT match Events",
     "UPI_LL Flit Events",
     "UPI_LL LL to M3 Events",
     "UPI_LL POWER Events",
     "UPI_LL POWER_RX Events",
     "UPI_LL POWER_TX Events",
     "UPI_LL RXQ Events",
     "UPI_LL RX_CREDITS_CONSUMED Events",
     "UPI_LL TXQ Events",
     "UPI_LL VNA_CREDIT_RETURN Events",
     "iMC ACT Events",
     "iMC BYPASS Command Events",
     "iMC CAS Events",
     "iMC DCLK Events",
     "iMC DRAM_PRE_ALL Events",
     "iMC DRAM_REFRESH Events",
     "iMC ECC Events",
     "iMC MAJOR_MODES Events",
     "iMC POWER Events",
     "iMC PRE Events",
     "iMC PREEMPTION Events",
     "iMC RPQ Events",
     "iMC WPQ Events",
     "rxl_hdr TOR Events",
);
