test_spm_open_lane_configuration = {
    "PDK": "sky130A",
    "DESIGN_NAME": "spm",
    "VERILOG_FILES": ["./src/spm.v"],
    "CLOCK_PORT": "clk",
    "CLOCK_PERIOD": 10,
}

example_open_lane_configuration = {
    "CLOCK_PERIOD": 100,
    "CLOCK_NET": "clk_o",
    "CLOCK_PORT": None,
    "CLOCK_TREE_SYNTH": True,
    "DIE_AREA": "0 0 100.0 100.00",
    "DESIGN_NAME": None,
    "FP_CORE_UTIL": 40,
    "FP_PDN_AUTO_ADJUST": 0,
    "FP_PDN_VPITCH": 25,
    "FP_PDN_HPITCH": 25,
    "FP_PDN_VOFFSET": 5,
    "FP_PDN_HOFFSET": 5,
    "FP_PIN_ORDER_CFG": "dir::pin_order.cfg",
    "FP_SIZING": "absolute",
    "PL_TARGET_DENSITY": 0.75,
    "PL_RANDOM_GLB_PLACEMENT": True,
    "SYNTH_NO_FLAT": 1,
    "SYNTH_CAP_LOAD": 100,
    "SYNTH_FLAT_TOP": True,
    "SYNTH_MAX_FANOUT": 10,
    "SYNTH_PARAMETERS": "",
    "VERILOG_FILES": None,
    "VERILOG_INCLUDE_DIRS": "dir::src/",
    "pdk::sky130*": {
        "FP_CORE_UTIL": 45,
        "scl::sky130_fd_sc_hd": {"CLOCK_PERIOD": 10},
        "scl::sky130_fd_sc_hdll": {"CLOCK_PERIOD": 10},
        "scl::sky130_fd_sc_hs": {"CLOCK_PERIOD": 8},
        "scl::sky130_fd_sc_ls": {"CLOCK_PERIOD": 10, "SYNTH_MAX_FANOUT": 5},
        "scl::sky130_fd_sc_ms": {"CLOCK_PERIOD": 10},
    },
    "pdk::gf180mcu*": {
        "CLOCK_PERIOD": 24.0,
        "FP_CORE_UTIL": 40,
        "SYNTH_MAX_FANOUT": 4,
        "PL_TARGET_DENSITY": 0.5,
    },
}
