Makefile;
SIM ?= icarus;
TOPLEVEL_LANG ?= verilog;
VERILOG_SOURCES += C:\Users\dario\Documents\phd\piel\docs\examples\simple_design\src\adder.sv;
VERILOG_SOURCES += C:\Users\dario\Documents\phd\piel\docs\examples\simple_design\src\adder.vhdl;
TOPLEVEL = adder;
MODULE = test_adder;
include $(shell cocotb-config --makefiles)/Makefile.sim
