// Generated by PeakRDL-regblock - A free and open-source SystemVerilog generator
//  https://github.com/SystemRDL/PeakRDL-regblock

package I3CCSR_pkg;

    localparam I3CCSR_DATA_WIDTH = 32;
    localparam I3CCSR_MIN_ADDR_WIDTH = 10;

    typedef struct {
        logic [15:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__REC_PROT_VERSION__in_t;

    typedef struct {
        logic [15:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__AGENT_CAPS__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__REC_PROT_VERSION__in_t REC_PROT_VERSION;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__AGENT_CAPS__in_t AGENT_CAPS;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__NUM_OF_CMS_REGIONS__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__MAX_RESP_TIME__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__HEARTBEAT_PERIOD__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__NUM_OF_CMS_REGIONS__in_t NUM_OF_CMS_REGIONS;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__MAX_RESP_TIME__in_t MAX_RESP_TIME;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__HEARTBEAT_PERIOD__in_t HEARTBEAT_PERIOD;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__DESC_TYPE__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__VENDOR_SPECIFIC_STR_LENGTH__in_t;

    typedef struct {
        logic [15:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__DATA__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__DESC_TYPE__in_t DESC_TYPE;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__VENDOR_SPECIFIC_STR_LENGTH__in_t VENDOR_SPECIFIC_STR_LENGTH;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__DATA__in_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_1__DATA__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_1__DATA__in_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_1__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_2__DATA__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_2__DATA__in_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_2__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_3__DATA__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_3__DATA__in_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_3__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_4__DATA__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_4__DATA__in_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_4__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_5__DATA__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_5__DATA__in_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_5__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__DEV_STATUS__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__PROT_ERROR__in_t;

    typedef struct {
        logic [15:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__REC_REASON_CODE__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__DEV_STATUS__in_t DEV_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__PROT_ERROR__in_t PROT_ERROR;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__REC_REASON_CODE__in_t REC_REASON_CODE;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__in_t;

    typedef struct {
        logic [15:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__HEARTBEAT__in_t;

    typedef struct {
        logic [8:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__VENDOR_STATUS_LENGTH__in_t;

    typedef struct {
        logic [6:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__VENDOR_STATUS__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__HEARTBEAT__in_t HEARTBEAT;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__VENDOR_STATUS_LENGTH__in_t VENDOR_STATUS_LENGTH;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__VENDOR_STATUS__in_t VENDOR_STATUS;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__RESET_CTRL__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__FORCED_RECOVERY__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__IF_CTRL__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__RESET_CTRL__in_t RESET_CTRL;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__FORCED_RECOVERY__in_t FORCED_RECOVERY;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__IF_CTRL__in_t IF_CTRL;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__CMS__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__REC_IMG_SEL__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__ACTIVATE_REC_IMG__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__CMS__in_t CMS;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__REC_IMG_SEL__in_t REC_IMG_SEL;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__ACTIVATE_REC_IMG__in_t ACTIVATE_REC_IMG;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__in_t;

    typedef struct {
        logic [3:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__DEV_REC_STATUS__in_t;

    typedef struct {
        logic [3:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__REC_IMG_INDEX__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__VENDOR_SPECIFIC_STATUS__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__DEV_REC_STATUS__in_t DEV_REC_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__REC_IMG_INDEX__in_t REC_IMG_INDEX;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__VENDOR_SPECIFIC_STATUS__in_t VENDOR_SPECIFIC_STATUS;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__in_t;

    typedef struct {
        logic next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__TEMP_CRITICAL__in_t;

    typedef struct {
        logic next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__SOFT_ERR__in_t;

    typedef struct {
        logic next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__FATAL_ERR__in_t;

    typedef struct {
        logic [4:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__RESERVED_7_3__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__VENDOR_HW_STATUS__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__CTEMP__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__VENDOR_HW_STATUS_LEN__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__TEMP_CRITICAL__in_t TEMP_CRITICAL;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__SOFT_ERR__in_t SOFT_ERR;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__FATAL_ERR__in_t FATAL_ERR;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__RESERVED_7_3__in_t RESERVED_7_3;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__VENDOR_HW_STATUS__in_t VENDOR_HW_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__CTEMP__in_t CTEMP;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__VENDOR_HW_STATUS_LEN__in_t VENDOR_HW_STATUS_LEN;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__CMS__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
        logic hwclr;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__RESET__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__CMS__in_t CMS;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__RESET__in_t RESET;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_1__IMAGE_SIZE__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_1__IMAGE_SIZE__in_t IMAGE_SIZE;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_1__in_t;

    typedef struct {
        logic next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__EMPTY__in_t;

    typedef struct {
        logic next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__FULL__in_t;

    typedef struct {
        logic [2:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__REGION_TYPE__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__EMPTY__in_t EMPTY;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__FULL__in_t FULL;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__REGION_TYPE__in_t REGION_TYPE;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_1__WRITE_INDEX__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_1__WRITE_INDEX__in_t WRITE_INDEX;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_1__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_2__READ_INDEX__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_2__READ_INDEX__in_t READ_INDEX;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_2__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_3__FIFO_SIZE__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_3__FIFO_SIZE__in_t FIFO_SIZE;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_3__in_t;

    typedef struct {
        logic [31:0] next;
        logic we;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_RESERVED__DATA__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_RESERVED__DATA__in_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_RESERVED__in_t;

    typedef struct packed {
        logic [31:0] DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_DATA__external__fields__in_t;

    typedef struct {
        logic rd_ack;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_DATA__external__fields__in_t rd_data;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_DATA__external__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__in_t PROT_CAP_2;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__in_t PROT_CAP_3;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__in_t DEVICE_ID_0;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_1__in_t DEVICE_ID_1;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_2__in_t DEVICE_ID_2;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_3__in_t DEVICE_ID_3;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_4__in_t DEVICE_ID_4;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_5__in_t DEVICE_ID_5;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__in_t DEVICE_STATUS_0;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__in_t DEVICE_STATUS_1;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__in_t DEVICE_RESET;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__in_t RECOVERY_CTRL;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__in_t RECOVERY_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__in_t HW_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__in_t INDIRECT_FIFO_CTRL_0;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_1__in_t INDIRECT_FIFO_CTRL_1;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__in_t INDIRECT_FIFO_STATUS_0;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_1__in_t INDIRECT_FIFO_STATUS_1;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_2__in_t INDIRECT_FIFO_STATUS_2;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_3__in_t INDIRECT_FIFO_STATUS_3;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_RESERVED__in_t INDIRECT_FIFO_RESERVED;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_DATA__external__in_t INDIRECT_FIFO_DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__PENDING_RX_NACK__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__HANDOFF_DELAY_NACK__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__ACR_FSM_OP_SELECT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__PRIME_ACCEPT_GETACCCR__in_t;

    typedef struct {
        logic next;
        logic we;
        logic hwclr;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__HANDOFF_DEEP_SLEEP__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__TARGET_XACT_ENABLE__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_SETAASA_ENABLE__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_SETDASA_ENABLE__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_ENTDAA_ENABLE__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__PENDING_RX_NACK__in_t PENDING_RX_NACK;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__HANDOFF_DELAY_NACK__in_t HANDOFF_DELAY_NACK;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__ACR_FSM_OP_SELECT__in_t ACR_FSM_OP_SELECT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__PRIME_ACCEPT_GETACCCR__in_t PRIME_ACCEPT_GETACCCR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__HANDOFF_DEEP_SLEEP__in_t HANDOFF_DEEP_SLEEP;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__TARGET_XACT_ENABLE__in_t TARGET_XACT_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_SETAASA_ENABLE__in_t DAA_SETAASA_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_SETDASA_ENABLE__in_t DAA_SETDASA_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_ENTDAA_ENABLE__in_t DAA_ENTDAA_ENABLE;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__in_t;

    typedef struct {
        logic [6:0] next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__STATIC_ADDR__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__STATIC_ADDR_VALID__in_t;

    typedef struct {
        logic [6:0] next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__DYNAMIC_ADDR__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__DYNAMIC_ADDR_VALID__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__STATIC_ADDR__in_t STATIC_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__STATIC_ADDR_VALID__in_t STATIC_ADDR_VALID;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__DYNAMIC_ADDR__in_t DYNAMIC_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__DYNAMIC_ADDR_VALID__in_t DYNAMIC_ADDR_VALID;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__AC_CURRENT_OWN__in_t;

    typedef struct {
        logic [2:0] next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__SIMPLE_CRR_STATUS__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__HJ_REQ_STATUS__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__AC_CURRENT_OWN__in_t AC_CURRENT_OWN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__SIMPLE_CRR_STATUS__in_t SIMPLE_CRR_STATUS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__HJ_REQ_STATUS__in_t HJ_REQ_STATUS;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_OK_REMAIN_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_OK_PRIMED_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_ERR_FAIL_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_ERR_M3_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CRR_RESPONSE_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_DYN_ADDR_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_NACKED_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_OK_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_ERR_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_OP_RSTACT_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_PARAM_MODIFIED_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_UNHANDLED_NACK_STAT__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_FATAL_RSTDAA_ERR_STAT__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_OK_REMAIN_STAT__in_t ACR_HANDOFF_OK_REMAIN_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_OK_PRIMED_STAT__in_t ACR_HANDOFF_OK_PRIMED_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_ERR_FAIL_STAT__in_t ACR_HANDOFF_ERR_FAIL_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_ERR_M3_STAT__in_t ACR_HANDOFF_ERR_M3_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CRR_RESPONSE_STAT__in_t CRR_RESPONSE_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_DYN_ADDR_STAT__in_t STBY_CR_DYN_ADDR_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_NACKED_STAT__in_t STBY_CR_ACCEPT_NACKED_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_OK_STAT__in_t STBY_CR_ACCEPT_OK_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_ERR_STAT__in_t STBY_CR_ACCEPT_ERR_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_OP_RSTACT_STAT__in_t STBY_CR_OP_RSTACT_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_PARAM_MODIFIED_STAT__in_t CCC_PARAM_MODIFIED_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_UNHANDLED_NACK_STAT__in_t CCC_UNHANDLED_NACK_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_FATAL_RSTDAA_ERR_STAT__in_t CCC_FATAL_RSTDAA_ERR_STAT;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_OK_REMAIN_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_OK_PRIMED_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_ERR_FAIL_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_ERR_M3_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CRR_RESPONSE_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_DYN_ADDR_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_NACKED_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_OK_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_ERR_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_OP_RSTACT_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_PARAM_MODIFIED_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_UNHANDLED_NACK_SIGNAL_EN__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_FATAL_RSTDAA_ERR_SIGNAL_EN__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_OK_REMAIN_SIGNAL_EN__in_t ACR_HANDOFF_OK_REMAIN_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_OK_PRIMED_SIGNAL_EN__in_t ACR_HANDOFF_OK_PRIMED_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_ERR_FAIL_SIGNAL_EN__in_t ACR_HANDOFF_ERR_FAIL_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_ERR_M3_SIGNAL_EN__in_t ACR_HANDOFF_ERR_M3_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CRR_RESPONSE_SIGNAL_EN__in_t CRR_RESPONSE_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_DYN_ADDR_SIGNAL_EN__in_t STBY_CR_DYN_ADDR_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_NACKED_SIGNAL_EN__in_t STBY_CR_ACCEPT_NACKED_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_OK_SIGNAL_EN__in_t STBY_CR_ACCEPT_OK_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_ERR_SIGNAL_EN__in_t STBY_CR_ACCEPT_ERR_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_OP_RSTACT_SIGNAL_EN__in_t STBY_CR_OP_RSTACT_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_PARAM_MODIFIED_SIGNAL_EN__in_t CCC_PARAM_MODIFIED_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_UNHANDLED_NACK_SIGNAL_EN__in_t CCC_UNHANDLED_NACK_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_FATAL_RSTDAA_ERR_SIGNAL_EN__in_t CCC_FATAL_RSTDAA_ERR_SIGNAL_EN;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CRR_RESPONSE_FORCE__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_DYN_ADDR_FORCE__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_NACKED_FORCE__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_OK_FORCE__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_ERR_FORCE__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_OP_RSTACT_FORCE__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_PARAM_MODIFIED_FORCE__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_UNHANDLED_NACK_FORCE__in_t;

    typedef struct {
        logic next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_FATAL_RSTDAA_ERR_FORCE__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CRR_RESPONSE_FORCE__in_t CRR_RESPONSE_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_DYN_ADDR_FORCE__in_t STBY_CR_DYN_ADDR_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_NACKED_FORCE__in_t STBY_CR_ACCEPT_NACKED_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_OK_FORCE__in_t STBY_CR_ACCEPT_OK_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_ERR_FORCE__in_t STBY_CR_ACCEPT_ERR_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_OP_RSTACT_FORCE__in_t STBY_CR_OP_RSTACT_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_PARAM_MODIFIED_FORCE__in_t CCC_PARAM_MODIFIED_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_UNHANDLED_NACK_FORCE__in_t CCC_UNHANDLED_NACK_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_FATAL_RSTDAA_ERR_FORCE__in_t CCC_FATAL_RSTDAA_ERR_FORCE;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__in_t;

    typedef struct {
        logic [2:0] next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__F2_CRCAP1_BUS_CONFIG__in_t;

    typedef struct {
        logic [3:0] next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__F2_CRCAP2_DEV_INTERACT__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__F2_CRCAP1_BUS_CONFIG__in_t F2_CRCAP1_BUS_CONFIG;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__F2_CRCAP2_DEV_INTERACT__in_t F2_CRCAP2_DEV_INTERACT;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RST_ACTION__in_t;

    typedef struct {
        logic [7:0] next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_TIME_PERIPHERAL__in_t;

    typedef struct {
        logic [7:0] next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_TIME_TARGET__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_DYNAMIC_ADDR__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RST_ACTION__in_t RST_ACTION;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_TIME_PERIPHERAL__in_t RESET_TIME_PERIPHERAL;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_TIME_TARGET__in_t RESET_TIME_TARGET;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_DYNAMIC_ADDR__in_t RESET_DYNAMIC_ADDR;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__in_t;

    typedef struct {
        logic [6:0] next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_STATIC_ADDR__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_STATIC_ADDR_VALID__in_t;

    typedef struct {
        logic [6:0] next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_DYNAMIC_ADDR__in_t;

    typedef struct {
        logic next;
        logic we;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_DYNAMIC_ADDR_VALID__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_STATIC_ADDR__in_t VIRT_STATIC_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_STATIC_ADDR_VALID__in_t VIRT_STATIC_ADDR_VALID;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_DYNAMIC_ADDR__in_t VIRT_DYNAMIC_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_DYNAMIC_ADDR_VALID__in_t VIRT_DYNAMIC_ADDR_VALID;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__in_t;

    typedef struct {
        logic [31:0] next;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5____rsvd_3____rsvd__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5____rsvd_3____rsvd__in_t __rsvd;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5____rsvd_3__in_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__in_t STBY_CR_CONTROL;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__in_t STBY_CR_DEVICE_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__in_t STBY_CR_STATUS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__in_t STBY_CR_INTR_STATUS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__in_t STBY_CR_INTR_SIGNAL_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__in_t STBY_CR_INTR_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__in_t STBY_CR_CCC_CONFIG_GETCAPS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__in_t STBY_CR_CCC_CONFIG_RSTACT_PARAMS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__in_t STBY_CR_VIRT_DEVICE_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5____rsvd_3__in_t __rsvd_3;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__HJ_EN__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__CRR_EN__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__IBI_EN__in_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__HJ_EN__in_t HJ_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__CRR_EN__in_t CRR_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__IBI_EN__in_t IBI_EN;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__in_t;

    typedef struct {
        logic next;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__PROTOCOL_ERROR__in_t;

    typedef struct {
        logic [1:0] next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__LAST_IBI_STATUS__in_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__PROTOCOL_ERROR__in_t PROTOCOL_ERROR;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__LAST_IBI_STATUS__in_t LAST_IBI_STATUS;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__in_t;

    typedef struct {
        logic hwclr;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__SOFT_RST__in_t;

    typedef struct {
        logic hwclr;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__TX_DESC_RST__in_t;

    typedef struct {
        logic hwclr;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__RX_DESC_RST__in_t;

    typedef struct {
        logic hwclr;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__TX_DATA_RST__in_t;

    typedef struct {
        logic hwclr;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__RX_DATA_RST__in_t;

    typedef struct {
        logic hwclr;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__IBI_QUEUE_RST__in_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__SOFT_RST__in_t SOFT_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__TX_DESC_RST__in_t TX_DESC_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__RX_DESC_RST__in_t RX_DESC_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__TX_DATA_RST__in_t TX_DATA_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__RX_DATA_RST__in_t RX_DATA_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__IBI_QUEUE_RST__in_t IBI_QUEUE_RST;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_TIMEOUT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_TIMEOUT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DATA_THLD_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DATA_THLD_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_THLD_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_THLD_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__IBI_THLD_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__IBI_DONE__in_t;

    typedef struct {
        logic [3:0] next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__PENDING_INTERRUPT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TRANSFER_ABORT_STAT__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_COMPLETE__in_t;

    typedef struct {
        logic next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TRANSFER_ERR_STAT__in_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_STAT__in_t RX_DESC_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_STAT__in_t TX_DESC_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_TIMEOUT__in_t RX_DESC_TIMEOUT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_TIMEOUT__in_t TX_DESC_TIMEOUT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DATA_THLD_STAT__in_t TX_DATA_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DATA_THLD_STAT__in_t RX_DATA_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_THLD_STAT__in_t TX_DESC_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_THLD_STAT__in_t RX_DESC_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__IBI_THLD_STAT__in_t IBI_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__IBI_DONE__in_t IBI_DONE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__PENDING_INTERRUPT__in_t PENDING_INTERRUPT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TRANSFER_ABORT_STAT__in_t TRANSFER_ABORT_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_COMPLETE__in_t TX_DESC_COMPLETE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TRANSFER_ERR_STAT__in_t TRANSFER_ERR_STAT;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__in_t;

    typedef struct packed {
        logic [31:0] RX_DESC;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DESC_QUEUE_PORT__external__fields__in_t;

    typedef struct {
        logic rd_ack;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DESC_QUEUE_PORT__external__fields__in_t rd_data;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DESC_QUEUE_PORT__external__in_t;

    typedef struct packed {
        logic [31:0] RX_DATA;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DATA_PORT__external__fields__in_t;

    typedef struct {
        logic rd_ack;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DATA_PORT__external__fields__in_t rd_data;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DATA_PORT__external__in_t;

    typedef struct {
        logic wr_ack;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DESC_QUEUE_PORT__external__in_t;

    typedef struct {
        logic wr_ack;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DATA_PORT__external__in_t;

    typedef struct {
        logic wr_ack;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_PORT__external__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__TX_DESC_THLD__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__RX_DESC_THLD__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__IBI_THLD__in_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__TX_DESC_THLD__in_t TX_DESC_THLD;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__RX_DESC_THLD__in_t RX_DESC_THLD;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__IBI_THLD__in_t IBI_THLD;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__in_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__in_t CONTROL;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__in_t STATUS;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__in_t RESET_CONTROL;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__in_t INTERRUPT_STATUS;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DESC_QUEUE_PORT__external__in_t RX_DESC_QUEUE_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DATA_PORT__external__in_t RX_DATA_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DESC_QUEUE_PORT__external__in_t TX_DESC_QUEUE_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DATA_PORT__external__in_t TX_DATA_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_PORT__external__in_t IBI_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__in_t QUEUE_THLD_CTRL;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__in_t;

    typedef struct {
        logic next;
        logic we;
    } SoCManagementInterfaceRegisters__REC_INTF_CFG__REC_PAYLOAD_DONE__in_t;

    typedef struct {
        SoCManagementInterfaceRegisters__REC_INTF_CFG__REC_PAYLOAD_DONE__in_t REC_PAYLOAD_DONE;
    } SoCManagementInterfaceRegisters__REC_INTF_CFG__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__DEVICE_RESET_CTRL__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__RECOVERY_CTRL_ACTIVATE_REC_IMG__in_t;

    typedef struct {
        logic [7:0] next;
        logic we;
    } SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__INDIRECT_FIFO_CTRL_RESET__in_t;

    typedef struct {
        SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__DEVICE_RESET_CTRL__in_t DEVICE_RESET_CTRL;
        SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__RECOVERY_CTRL_ACTIVATE_REC_IMG__in_t RECOVERY_CTRL_ACTIVATE_REC_IMG;
        SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__INDIRECT_FIFO_CTRL_RESET__in_t INDIRECT_FIFO_CTRL_RESET;
    } SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__in_t;

    typedef struct {
        SoCManagementInterfaceRegisters__REC_INTF_CFG__in_t REC_INTF_CFG;
        SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__in_t REC_INTF_REG_W1C_ACCESS;
    } SoCManagementInterfaceRegisters__in_t;

    typedef struct {
        logic [1:0] next;
        logic we;
    } ControllerConfigRegisters__CONTROLLER_CONFIG__OPERATION_MODE__in_t;

    typedef struct {
        ControllerConfigRegisters__CONTROLLER_CONFIG__OPERATION_MODE__in_t OPERATION_MODE;
    } ControllerConfigRegisters__CONTROLLER_CONFIG__in_t;

    typedef struct {
        ControllerConfigRegisters__CONTROLLER_CONFIG__in_t CONTROLLER_CONFIG;
    } ControllerConfigRegisters__in_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__in_t SecFwRecoveryIf;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__in_t StdbyCtrlMode;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__in_t TTI;
        SoCManagementInterfaceRegisters__in_t SoCMgmtIf;
        ControllerConfigRegisters__in_t CtrlCfg;
    } ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__in_t;

    typedef struct {
        logic rst_ni;
        ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__in_t I3C_EC;
    } I3CCSR__in_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__EXTCAP_HEADER__CAP_ID__out_t;

    typedef struct {
        logic [15:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__EXTCAP_HEADER__CAP_LENGTH__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__EXTCAP_HEADER__CAP_ID__out_t CAP_ID;
        SecureFirmwareRecoveryInterfaceRegisters__EXTCAP_HEADER__CAP_LENGTH__out_t CAP_LENGTH;
    } SecureFirmwareRecoveryInterfaceRegisters__EXTCAP_HEADER__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_0__REC_MAGIC_STRING_0__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_0__REC_MAGIC_STRING_0__out_t REC_MAGIC_STRING_0;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_0__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_1__REC_MAGIC_STRING_1__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_1__REC_MAGIC_STRING_1__out_t REC_MAGIC_STRING_1;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_1__out_t;

    typedef struct {
        logic [15:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__REC_PROT_VERSION__out_t;

    typedef struct {
        logic [15:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__AGENT_CAPS__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__REC_PROT_VERSION__out_t REC_PROT_VERSION;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__AGENT_CAPS__out_t AGENT_CAPS;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__NUM_OF_CMS_REGIONS__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__MAX_RESP_TIME__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__HEARTBEAT_PERIOD__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__NUM_OF_CMS_REGIONS__out_t NUM_OF_CMS_REGIONS;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__MAX_RESP_TIME__out_t MAX_RESP_TIME;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__HEARTBEAT_PERIOD__out_t HEARTBEAT_PERIOD;
    } SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__DESC_TYPE__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__VENDOR_SPECIFIC_STR_LENGTH__out_t;

    typedef struct {
        logic [15:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__DATA__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__DESC_TYPE__out_t DESC_TYPE;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__VENDOR_SPECIFIC_STR_LENGTH__out_t VENDOR_SPECIFIC_STR_LENGTH;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__DATA__out_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_1__DATA__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_1__DATA__out_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_1__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_2__DATA__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_2__DATA__out_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_2__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_3__DATA__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_3__DATA__out_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_3__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_4__DATA__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_4__DATA__out_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_4__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_5__DATA__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_5__DATA__out_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_5__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_RESERVED__DATA__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_RESERVED__DATA__out_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_RESERVED__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__DEV_STATUS__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__PROT_ERROR__out_t;

    typedef struct {
        logic [15:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__REC_REASON_CODE__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__DEV_STATUS__out_t DEV_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__PROT_ERROR__out_t PROT_ERROR;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__REC_REASON_CODE__out_t REC_REASON_CODE;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__out_t;

    typedef struct {
        logic [15:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__HEARTBEAT__out_t;

    typedef struct {
        logic [8:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__VENDOR_STATUS_LENGTH__out_t;

    typedef struct {
        logic [6:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__VENDOR_STATUS__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__HEARTBEAT__out_t HEARTBEAT;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__VENDOR_STATUS_LENGTH__out_t VENDOR_STATUS_LENGTH;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__VENDOR_STATUS__out_t VENDOR_STATUS;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__RESET_CTRL__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__FORCED_RECOVERY__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__IF_CTRL__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__RESET_CTRL__out_t RESET_CTRL;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__FORCED_RECOVERY__out_t FORCED_RECOVERY;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__IF_CTRL__out_t IF_CTRL;
    } SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__CMS__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__REC_IMG_SEL__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__ACTIVATE_REC_IMG__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__CMS__out_t CMS;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__REC_IMG_SEL__out_t REC_IMG_SEL;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__ACTIVATE_REC_IMG__out_t ACTIVATE_REC_IMG;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__out_t;

    typedef struct {
        logic [3:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__DEV_REC_STATUS__out_t;

    typedef struct {
        logic [3:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__REC_IMG_INDEX__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__VENDOR_SPECIFIC_STATUS__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__DEV_REC_STATUS__out_t DEV_REC_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__REC_IMG_INDEX__out_t REC_IMG_INDEX;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__VENDOR_SPECIFIC_STATUS__out_t VENDOR_SPECIFIC_STATUS;
    } SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__out_t;

    typedef struct {
        logic value;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__TEMP_CRITICAL__out_t;

    typedef struct {
        logic value;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__SOFT_ERR__out_t;

    typedef struct {
        logic value;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__FATAL_ERR__out_t;

    typedef struct {
        logic [4:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__RESERVED_7_3__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__VENDOR_HW_STATUS__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__CTEMP__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__VENDOR_HW_STATUS_LEN__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__TEMP_CRITICAL__out_t TEMP_CRITICAL;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__SOFT_ERR__out_t SOFT_ERR;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__FATAL_ERR__out_t FATAL_ERR;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__RESERVED_7_3__out_t RESERVED_7_3;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__VENDOR_HW_STATUS__out_t VENDOR_HW_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__CTEMP__out_t CTEMP;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__VENDOR_HW_STATUS_LEN__out_t VENDOR_HW_STATUS_LEN;
    } SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__CMS__out_t;

    typedef struct {
        logic [7:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__RESET__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__CMS__out_t CMS;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__RESET__out_t RESET;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_1__IMAGE_SIZE__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_1__IMAGE_SIZE__out_t IMAGE_SIZE;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_1__out_t;

    typedef struct {
        logic value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__EMPTY__out_t;

    typedef struct {
        logic value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__FULL__out_t;

    typedef struct {
        logic [2:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__REGION_TYPE__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__EMPTY__out_t EMPTY;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__FULL__out_t FULL;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__REGION_TYPE__out_t REGION_TYPE;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_1__WRITE_INDEX__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_1__WRITE_INDEX__out_t WRITE_INDEX;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_1__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_2__READ_INDEX__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_2__READ_INDEX__out_t READ_INDEX;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_2__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_3__FIFO_SIZE__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_3__FIFO_SIZE__out_t FIFO_SIZE;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_3__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_4__MAX_TRANSFER_SIZE__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_4__MAX_TRANSFER_SIZE__out_t MAX_TRANSFER_SIZE;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_4__out_t;

    typedef struct {
        logic [31:0] value;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_RESERVED__DATA__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_RESERVED__DATA__out_t DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_RESERVED__out_t;

    typedef struct {
        logic req;
        logic req_is_wr;
    } SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_DATA__external__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__EXTCAP_HEADER__out_t EXTCAP_HEADER;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_0__out_t PROT_CAP_0;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_1__out_t PROT_CAP_1;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_2__out_t PROT_CAP_2;
        SecureFirmwareRecoveryInterfaceRegisters__PROT_CAP_3__out_t PROT_CAP_3;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_0__out_t DEVICE_ID_0;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_1__out_t DEVICE_ID_1;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_2__out_t DEVICE_ID_2;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_3__out_t DEVICE_ID_3;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_4__out_t DEVICE_ID_4;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_5__out_t DEVICE_ID_5;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_ID_RESERVED__out_t DEVICE_ID_RESERVED;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_0__out_t DEVICE_STATUS_0;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_STATUS_1__out_t DEVICE_STATUS_1;
        SecureFirmwareRecoveryInterfaceRegisters__DEVICE_RESET__out_t DEVICE_RESET;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_CTRL__out_t RECOVERY_CTRL;
        SecureFirmwareRecoveryInterfaceRegisters__RECOVERY_STATUS__out_t RECOVERY_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__HW_STATUS__out_t HW_STATUS;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_0__out_t INDIRECT_FIFO_CTRL_0;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_CTRL_1__out_t INDIRECT_FIFO_CTRL_1;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_0__out_t INDIRECT_FIFO_STATUS_0;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_1__out_t INDIRECT_FIFO_STATUS_1;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_2__out_t INDIRECT_FIFO_STATUS_2;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_3__out_t INDIRECT_FIFO_STATUS_3;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_STATUS_4__out_t INDIRECT_FIFO_STATUS_4;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_RESERVED__out_t INDIRECT_FIFO_RESERVED;
        SecureFirmwareRecoveryInterfaceRegisters__INDIRECT_FIFO_DATA__external__out_t INDIRECT_FIFO_DATA;
    } SecureFirmwareRecoveryInterfaceRegisters__out_t;

    typedef struct {
        logic [7:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__EXTCAP_HEADER__CAP_ID__out_t;

    typedef struct {
        logic [15:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__EXTCAP_HEADER__CAP_LENGTH__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__EXTCAP_HEADER__CAP_ID__out_t CAP_ID;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__EXTCAP_HEADER__CAP_LENGTH__out_t CAP_LENGTH;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__EXTCAP_HEADER__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__PENDING_RX_NACK__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__HANDOFF_DELAY_NACK__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__ACR_FSM_OP_SELECT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__PRIME_ACCEPT_GETACCCR__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__HANDOFF_DEEP_SLEEP__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__CR_REQUEST_SEND__out_t;

    typedef struct {
        logic [2:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__BAST_CCC_IBI_RING__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__TARGET_XACT_ENABLE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_SETAASA_ENABLE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_SETDASA_ENABLE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_ENTDAA_ENABLE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__RSTACT_DEFBYTE_02__out_t;

    typedef struct {
        logic [1:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__STBY_CR_ENABLE_INIT__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__PENDING_RX_NACK__out_t PENDING_RX_NACK;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__HANDOFF_DELAY_NACK__out_t HANDOFF_DELAY_NACK;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__ACR_FSM_OP_SELECT__out_t ACR_FSM_OP_SELECT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__PRIME_ACCEPT_GETACCCR__out_t PRIME_ACCEPT_GETACCCR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__HANDOFF_DEEP_SLEEP__out_t HANDOFF_DEEP_SLEEP;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__CR_REQUEST_SEND__out_t CR_REQUEST_SEND;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__BAST_CCC_IBI_RING__out_t BAST_CCC_IBI_RING;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__TARGET_XACT_ENABLE__out_t TARGET_XACT_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_SETAASA_ENABLE__out_t DAA_SETAASA_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_SETDASA_ENABLE__out_t DAA_SETDASA_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__DAA_ENTDAA_ENABLE__out_t DAA_ENTDAA_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__RSTACT_DEFBYTE_02__out_t RSTACT_DEFBYTE_02;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__STBY_CR_ENABLE_INIT__out_t STBY_CR_ENABLE_INIT;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__out_t;

    typedef struct {
        logic [6:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__STATIC_ADDR__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__STATIC_ADDR_VALID__out_t;

    typedef struct {
        logic [6:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__DYNAMIC_ADDR__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__DYNAMIC_ADDR_VALID__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__STATIC_ADDR__out_t STATIC_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__STATIC_ADDR_VALID__out_t STATIC_ADDR_VALID;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__DYNAMIC_ADDR__out_t DYNAMIC_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__DYNAMIC_ADDR_VALID__out_t DYNAMIC_ADDR_VALID;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__SIMPLE_CRR_SUPPORT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__TARGET_XACT_SUPPORT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__DAA_SETAASA_SUPPORT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__DAA_SETDASA_SUPPORT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__DAA_ENTDAA_SUPPORT__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__SIMPLE_CRR_SUPPORT__out_t SIMPLE_CRR_SUPPORT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__TARGET_XACT_SUPPORT__out_t TARGET_XACT_SUPPORT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__DAA_SETAASA_SUPPORT__out_t DAA_SETAASA_SUPPORT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__DAA_SETDASA_SUPPORT__out_t DAA_SETDASA_SUPPORT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__DAA_ENTDAA_SUPPORT__out_t DAA_ENTDAA_SUPPORT;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__out_t;

    typedef struct {
        logic [14:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__PID_HI__out_t;

    typedef struct {
        logic [7:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__DCR__out_t;

    typedef struct {
        logic [4:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__BCR_VAR__out_t;

    typedef struct {
        logic [2:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__BCR_FIXED__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__PID_HI__out_t PID_HI;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__DCR__out_t DCR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__BCR_VAR__out_t BCR_VAR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__BCR_FIXED__out_t BCR_FIXED;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__AC_CURRENT_OWN__out_t;

    typedef struct {
        logic [2:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__SIMPLE_CRR_STATUS__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__HJ_REQ_STATUS__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__AC_CURRENT_OWN__out_t AC_CURRENT_OWN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__SIMPLE_CRR_STATUS__out_t SIMPLE_CRR_STATUS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__HJ_REQ_STATUS__out_t HJ_REQ_STATUS;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__out_t;

    typedef struct {
        logic [14:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__PID_HI__out_t;

    typedef struct {
        logic [7:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__DCR__out_t;

    typedef struct {
        logic [4:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__BCR_VAR__out_t;

    typedef struct {
        logic [2:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__BCR_FIXED__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__PID_HI__out_t PID_HI;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__DCR__out_t DCR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__BCR_VAR__out_t BCR_VAR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__BCR_FIXED__out_t BCR_FIXED;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__out_t;

    typedef struct {
        logic [31:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_PID_LO__PID_LO__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_PID_LO__PID_LO__out_t PID_LO;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_PID_LO__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_OK_REMAIN_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_OK_PRIMED_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_ERR_FAIL_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_ERR_M3_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CRR_RESPONSE_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_DYN_ADDR_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_NACKED_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_OK_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_ERR_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_OP_RSTACT_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_PARAM_MODIFIED_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_UNHANDLED_NACK_STAT__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_FATAL_RSTDAA_ERR_STAT__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_OK_REMAIN_STAT__out_t ACR_HANDOFF_OK_REMAIN_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_OK_PRIMED_STAT__out_t ACR_HANDOFF_OK_PRIMED_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_ERR_FAIL_STAT__out_t ACR_HANDOFF_ERR_FAIL_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__ACR_HANDOFF_ERR_M3_STAT__out_t ACR_HANDOFF_ERR_M3_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CRR_RESPONSE_STAT__out_t CRR_RESPONSE_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_DYN_ADDR_STAT__out_t STBY_CR_DYN_ADDR_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_NACKED_STAT__out_t STBY_CR_ACCEPT_NACKED_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_OK_STAT__out_t STBY_CR_ACCEPT_OK_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_ACCEPT_ERR_STAT__out_t STBY_CR_ACCEPT_ERR_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__STBY_CR_OP_RSTACT_STAT__out_t STBY_CR_OP_RSTACT_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_PARAM_MODIFIED_STAT__out_t CCC_PARAM_MODIFIED_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_UNHANDLED_NACK_STAT__out_t CCC_UNHANDLED_NACK_STAT;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__CCC_FATAL_RSTDAA_ERR_STAT__out_t CCC_FATAL_RSTDAA_ERR_STAT;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__out_t;

    typedef struct {
        logic [31:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_PID_LO__PID_LO__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_PID_LO__PID_LO__out_t PID_LO;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_PID_LO__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_OK_REMAIN_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_OK_PRIMED_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_ERR_FAIL_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_ERR_M3_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CRR_RESPONSE_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_DYN_ADDR_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_NACKED_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_OK_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_ERR_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_OP_RSTACT_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_PARAM_MODIFIED_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_UNHANDLED_NACK_SIGNAL_EN__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_FATAL_RSTDAA_ERR_SIGNAL_EN__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_OK_REMAIN_SIGNAL_EN__out_t ACR_HANDOFF_OK_REMAIN_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_OK_PRIMED_SIGNAL_EN__out_t ACR_HANDOFF_OK_PRIMED_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_ERR_FAIL_SIGNAL_EN__out_t ACR_HANDOFF_ERR_FAIL_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__ACR_HANDOFF_ERR_M3_SIGNAL_EN__out_t ACR_HANDOFF_ERR_M3_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CRR_RESPONSE_SIGNAL_EN__out_t CRR_RESPONSE_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_DYN_ADDR_SIGNAL_EN__out_t STBY_CR_DYN_ADDR_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_NACKED_SIGNAL_EN__out_t STBY_CR_ACCEPT_NACKED_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_OK_SIGNAL_EN__out_t STBY_CR_ACCEPT_OK_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_ACCEPT_ERR_SIGNAL_EN__out_t STBY_CR_ACCEPT_ERR_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__STBY_CR_OP_RSTACT_SIGNAL_EN__out_t STBY_CR_OP_RSTACT_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_PARAM_MODIFIED_SIGNAL_EN__out_t CCC_PARAM_MODIFIED_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_UNHANDLED_NACK_SIGNAL_EN__out_t CCC_UNHANDLED_NACK_SIGNAL_EN;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__CCC_FATAL_RSTDAA_ERR_SIGNAL_EN__out_t CCC_FATAL_RSTDAA_ERR_SIGNAL_EN;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CRR_RESPONSE_FORCE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_DYN_ADDR_FORCE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_NACKED_FORCE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_OK_FORCE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_ERR_FORCE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_OP_RSTACT_FORCE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_PARAM_MODIFIED_FORCE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_UNHANDLED_NACK_FORCE__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_FATAL_RSTDAA_ERR_FORCE__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CRR_RESPONSE_FORCE__out_t CRR_RESPONSE_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_DYN_ADDR_FORCE__out_t STBY_CR_DYN_ADDR_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_NACKED_FORCE__out_t STBY_CR_ACCEPT_NACKED_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_OK_FORCE__out_t STBY_CR_ACCEPT_OK_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_ACCEPT_ERR_FORCE__out_t STBY_CR_ACCEPT_ERR_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__STBY_CR_OP_RSTACT_FORCE__out_t STBY_CR_OP_RSTACT_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_PARAM_MODIFIED_FORCE__out_t CCC_PARAM_MODIFIED_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_UNHANDLED_NACK_FORCE__out_t CCC_UNHANDLED_NACK_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__CCC_FATAL_RSTDAA_ERR_FORCE__out_t CCC_FATAL_RSTDAA_ERR_FORCE;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__out_t;

    typedef struct {
        logic [2:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__F2_CRCAP1_BUS_CONFIG__out_t;

    typedef struct {
        logic [3:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__F2_CRCAP2_DEV_INTERACT__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__F2_CRCAP1_BUS_CONFIG__out_t F2_CRCAP1_BUS_CONFIG;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__F2_CRCAP2_DEV_INTERACT__out_t F2_CRCAP2_DEV_INTERACT;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__out_t;

    typedef struct {
        logic [7:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RST_ACTION__out_t;

    typedef struct {
        logic [7:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_TIME_PERIPHERAL__out_t;

    typedef struct {
        logic [7:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_TIME_TARGET__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_DYNAMIC_ADDR__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RST_ACTION__out_t RST_ACTION;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_TIME_PERIPHERAL__out_t RESET_TIME_PERIPHERAL;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_TIME_TARGET__out_t RESET_TIME_TARGET;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__RESET_DYNAMIC_ADDR__out_t RESET_DYNAMIC_ADDR;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__out_t;

    typedef struct {
        logic [6:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_STATIC_ADDR__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_STATIC_ADDR_VALID__out_t;

    typedef struct {
        logic [6:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_DYNAMIC_ADDR__out_t;

    typedef struct {
        logic value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_DYNAMIC_ADDR_VALID__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_STATIC_ADDR__out_t VIRT_STATIC_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_STATIC_ADDR_VALID__out_t VIRT_STATIC_ADDR_VALID;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_DYNAMIC_ADDR__out_t VIRT_DYNAMIC_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__VIRT_DYNAMIC_ADDR_VALID__out_t VIRT_DYNAMIC_ADDR_VALID;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__out_t;

    typedef struct {
        logic [31:0] value;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5____rsvd_3____rsvd__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5____rsvd_3____rsvd__out_t __rsvd;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5____rsvd_3__out_t;

    typedef struct {
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__EXTCAP_HEADER__out_t EXTCAP_HEADER;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CONTROL__out_t STBY_CR_CONTROL;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_ADDR__out_t STBY_CR_DEVICE_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CAPABILITIES__out_t STBY_CR_CAPABILITIES;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_CHAR__out_t STBY_CR_VIRTUAL_DEVICE_CHAR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_STATUS__out_t STBY_CR_STATUS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_CHAR__out_t STBY_CR_DEVICE_CHAR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_DEVICE_PID_LO__out_t STBY_CR_DEVICE_PID_LO;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_STATUS__out_t STBY_CR_INTR_STATUS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRTUAL_DEVICE_PID_LO__out_t STBY_CR_VIRTUAL_DEVICE_PID_LO;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_SIGNAL_ENABLE__out_t STBY_CR_INTR_SIGNAL_ENABLE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_INTR_FORCE__out_t STBY_CR_INTR_FORCE;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_GETCAPS__out_t STBY_CR_CCC_CONFIG_GETCAPS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_CCC_CONFIG_RSTACT_PARAMS__out_t STBY_CR_CCC_CONFIG_RSTACT_PARAMS;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__STBY_CR_VIRT_DEVICE_ADDR__out_t STBY_CR_VIRT_DEVICE_ADDR;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5____rsvd_3__out_t __rsvd_3;
    } StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__out_t;

    typedef struct {
        logic [7:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__EXTCAP_HEADER__CAP_ID__out_t;

    typedef struct {
        logic [15:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__EXTCAP_HEADER__CAP_LENGTH__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__EXTCAP_HEADER__CAP_ID__out_t CAP_ID;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__EXTCAP_HEADER__CAP_LENGTH__out_t CAP_LENGTH;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__EXTCAP_HEADER__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__HJ_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__CRR_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__IBI_EN__out_t;

    typedef struct {
        logic [2:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__IBI_RETRY_NUM__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__HJ_EN__out_t HJ_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__CRR_EN__out_t CRR_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__IBI_EN__out_t IBI_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__IBI_RETRY_NUM__out_t IBI_RETRY_NUM;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__PROTOCOL_ERROR__out_t;

    typedef struct {
        logic [1:0] value;
        logic swacc;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__LAST_IBI_STATUS__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__PROTOCOL_ERROR__out_t PROTOCOL_ERROR;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__LAST_IBI_STATUS__out_t LAST_IBI_STATUS;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__SOFT_RST__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__TX_DESC_RST__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__RX_DESC_RST__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__TX_DATA_RST__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__RX_DATA_RST__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__IBI_QUEUE_RST__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__SOFT_RST__out_t SOFT_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__TX_DESC_RST__out_t TX_DESC_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__RX_DESC_RST__out_t RX_DESC_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__TX_DATA_RST__out_t TX_DATA_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__RX_DATA_RST__out_t RX_DATA_RST;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__IBI_QUEUE_RST__out_t IBI_QUEUE_RST;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_STAT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_STAT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_TIMEOUT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_TIMEOUT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DATA_THLD_STAT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DATA_THLD_STAT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_THLD_STAT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_THLD_STAT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__IBI_THLD_STAT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__IBI_DONE__out_t;

    typedef struct {
        logic [3:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__PENDING_INTERRUPT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TRANSFER_ABORT_STAT__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_COMPLETE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TRANSFER_ERR_STAT__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_STAT__out_t RX_DESC_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_STAT__out_t TX_DESC_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_TIMEOUT__out_t RX_DESC_TIMEOUT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_TIMEOUT__out_t TX_DESC_TIMEOUT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DATA_THLD_STAT__out_t TX_DATA_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DATA_THLD_STAT__out_t RX_DATA_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_THLD_STAT__out_t TX_DESC_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__RX_DESC_THLD_STAT__out_t RX_DESC_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__IBI_THLD_STAT__out_t IBI_THLD_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__IBI_DONE__out_t IBI_DONE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__PENDING_INTERRUPT__out_t PENDING_INTERRUPT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TRANSFER_ABORT_STAT__out_t TRANSFER_ABORT_STAT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TX_DESC_COMPLETE__out_t TX_DESC_COMPLETE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__TRANSFER_ERR_STAT__out_t TRANSFER_ERR_STAT;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__RX_DESC_STAT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DESC_STAT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__RX_DESC_TIMEOUT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DESC_TIMEOUT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DATA_THLD_STAT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__RX_DATA_THLD_STAT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DESC_THLD_STAT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__RX_DESC_THLD_STAT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__IBI_THLD_STAT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__IBI_DONE_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TRANSFER_ABORT_STAT_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DESC_COMPLETE_EN__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TRANSFER_ERR_STAT_EN__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__RX_DESC_STAT_EN__out_t RX_DESC_STAT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DESC_STAT_EN__out_t TX_DESC_STAT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__RX_DESC_TIMEOUT_EN__out_t RX_DESC_TIMEOUT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DESC_TIMEOUT_EN__out_t TX_DESC_TIMEOUT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DATA_THLD_STAT_EN__out_t TX_DATA_THLD_STAT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__RX_DATA_THLD_STAT_EN__out_t RX_DATA_THLD_STAT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DESC_THLD_STAT_EN__out_t TX_DESC_THLD_STAT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__RX_DESC_THLD_STAT_EN__out_t RX_DESC_THLD_STAT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__IBI_THLD_STAT_EN__out_t IBI_THLD_STAT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__IBI_DONE_EN__out_t IBI_DONE_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TRANSFER_ABORT_STAT_EN__out_t TRANSFER_ABORT_STAT_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TX_DESC_COMPLETE_EN__out_t TX_DESC_COMPLETE_EN;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__TRANSFER_ERR_STAT_EN__out_t TRANSFER_ERR_STAT_EN;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__RX_DESC_STAT_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DESC_STAT_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__RX_DESC_TIMEOUT_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DESC_TIMEOUT_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DATA_THLD_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__RX_DATA_THLD_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DESC_THLD_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__RX_DESC_THLD_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__IBI_THLD_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__IBI_DONE_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TRANSFER_ABORT_STAT_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DESC_COMPLETE_FORCE__out_t;

    typedef struct {
        logic value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TRANSFER_ERR_STAT_FORCE__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__RX_DESC_STAT_FORCE__out_t RX_DESC_STAT_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DESC_STAT_FORCE__out_t TX_DESC_STAT_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__RX_DESC_TIMEOUT_FORCE__out_t RX_DESC_TIMEOUT_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DESC_TIMEOUT_FORCE__out_t TX_DESC_TIMEOUT_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DATA_THLD_FORCE__out_t TX_DATA_THLD_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__RX_DATA_THLD_FORCE__out_t RX_DATA_THLD_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DESC_THLD_FORCE__out_t TX_DESC_THLD_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__RX_DESC_THLD_FORCE__out_t RX_DESC_THLD_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__IBI_THLD_FORCE__out_t IBI_THLD_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__IBI_DONE_FORCE__out_t IBI_DONE_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TRANSFER_ABORT_STAT_FORCE__out_t TRANSFER_ABORT_STAT_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TX_DESC_COMPLETE_FORCE__out_t TX_DESC_COMPLETE_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__TRANSFER_ERR_STAT_FORCE__out_t TRANSFER_ERR_STAT_FORCE;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__out_t;

    typedef struct {
        logic req;
        logic req_is_wr;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DESC_QUEUE_PORT__external__out_t;

    typedef struct {
        logic req;
        logic req_is_wr;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DATA_PORT__external__out_t;

    typedef struct packed {
        logic [31:0] TX_DESC;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DESC_QUEUE_PORT__external__fields__out_t;

    typedef struct {
        logic req;
        logic req_is_wr;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DESC_QUEUE_PORT__external__fields__out_t wr_data;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DESC_QUEUE_PORT__external__fields__out_t wr_biten;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DESC_QUEUE_PORT__external__out_t;

    typedef struct packed {
        logic [31:0] TX_DATA;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DATA_PORT__external__fields__out_t;

    typedef struct {
        logic req;
        logic req_is_wr;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DATA_PORT__external__fields__out_t wr_data;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DATA_PORT__external__fields__out_t wr_biten;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DATA_PORT__external__out_t;

    typedef struct packed {
        logic [31:0] IBI_DATA;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_PORT__external__fields__out_t;

    typedef struct {
        logic req;
        logic req_is_wr;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_PORT__external__fields__out_t wr_data;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_PORT__external__fields__out_t wr_biten;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_PORT__external__out_t;

    typedef struct {
        logic [7:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__RX_DESC_BUFFER_SIZE__out_t;

    typedef struct {
        logic [7:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__TX_DESC_BUFFER_SIZE__out_t;

    typedef struct {
        logic [7:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__RX_DATA_BUFFER_SIZE__out_t;

    typedef struct {
        logic [7:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__TX_DATA_BUFFER_SIZE__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__RX_DESC_BUFFER_SIZE__out_t RX_DESC_BUFFER_SIZE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__TX_DESC_BUFFER_SIZE__out_t TX_DESC_BUFFER_SIZE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__RX_DATA_BUFFER_SIZE__out_t RX_DATA_BUFFER_SIZE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__TX_DATA_BUFFER_SIZE__out_t TX_DATA_BUFFER_SIZE;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__out_t;

    typedef struct {
        logic [7:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_QUEUE_SIZE__IBI_QUEUE_SIZE__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_QUEUE_SIZE__IBI_QUEUE_SIZE__out_t IBI_QUEUE_SIZE;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_QUEUE_SIZE__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__TX_DESC_THLD__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__RX_DESC_THLD__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__IBI_THLD__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__TX_DESC_THLD__out_t TX_DESC_THLD;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__RX_DESC_THLD__out_t RX_DESC_THLD;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__IBI_THLD__out_t IBI_THLD;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__out_t;

    typedef struct {
        logic [2:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__TX_DATA_THLD__out_t;

    typedef struct {
        logic [2:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__RX_DATA_THLD__out_t;

    typedef struct {
        logic [2:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__TX_START_THLD__out_t;

    typedef struct {
        logic [2:0] value;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__RX_START_THLD__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__TX_DATA_THLD__out_t TX_DATA_THLD;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__RX_DATA_THLD__out_t RX_DATA_THLD;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__TX_START_THLD__out_t TX_START_THLD;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__RX_START_THLD__out_t RX_START_THLD;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__out_t;

    typedef struct {
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__EXTCAP_HEADER__out_t EXTCAP_HEADER;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__CONTROL__out_t CONTROL;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__STATUS__out_t STATUS;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RESET_CONTROL__out_t RESET_CONTROL;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_STATUS__out_t INTERRUPT_STATUS;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_ENABLE__out_t INTERRUPT_ENABLE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__INTERRUPT_FORCE__out_t INTERRUPT_FORCE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DESC_QUEUE_PORT__external__out_t RX_DESC_QUEUE_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__RX_DATA_PORT__external__out_t RX_DATA_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DESC_QUEUE_PORT__external__out_t TX_DESC_QUEUE_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__TX_DATA_PORT__external__out_t TX_DATA_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_PORT__external__out_t IBI_PORT;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_SIZE__out_t QUEUE_SIZE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__IBI_QUEUE_SIZE__out_t IBI_QUEUE_SIZE;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__QUEUE_THLD_CTRL__out_t QUEUE_THLD_CTRL;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__DATA_BUFFER_THLD_CTRL__out_t DATA_BUFFER_THLD_CTRL;
    } TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__out_t;

    typedef struct {
        logic [7:0] value;
    } SoCManagementInterfaceRegisters__EXTCAP_HEADER__CAP_ID__out_t;

    typedef struct {
        logic [15:0] value;
    } SoCManagementInterfaceRegisters__EXTCAP_HEADER__CAP_LENGTH__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__EXTCAP_HEADER__CAP_ID__out_t CAP_ID;
        SoCManagementInterfaceRegisters__EXTCAP_HEADER__CAP_LENGTH__out_t CAP_LENGTH;
    } SoCManagementInterfaceRegisters__EXTCAP_HEADER__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__SOC_MGMT_CONTROL__PLACEHOLDER__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__SOC_MGMT_CONTROL__PLACEHOLDER__out_t PLACEHOLDER;
    } SoCManagementInterfaceRegisters__SOC_MGMT_CONTROL__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__SOC_MGMT_STATUS__PLACEHOLDER__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__SOC_MGMT_STATUS__PLACEHOLDER__out_t PLACEHOLDER;
    } SoCManagementInterfaceRegisters__SOC_MGMT_STATUS__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__REC_INTF_CFG__REC_INTF_BYPASS__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__REC_INTF_CFG__REC_PAYLOAD_DONE__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__REC_INTF_CFG__REC_INTF_BYPASS__out_t REC_INTF_BYPASS;
        SoCManagementInterfaceRegisters__REC_INTF_CFG__REC_PAYLOAD_DONE__out_t REC_PAYLOAD_DONE;
    } SoCManagementInterfaceRegisters__REC_INTF_CFG__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__DEVICE_RESET_CTRL__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__RECOVERY_CTRL_ACTIVATE_REC_IMG__out_t;

    typedef struct {
        logic [7:0] value;
        logic swmod;
    } SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__INDIRECT_FIFO_CTRL_RESET__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__DEVICE_RESET_CTRL__out_t DEVICE_RESET_CTRL;
        SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__RECOVERY_CTRL_ACTIVATE_REC_IMG__out_t RECOVERY_CTRL_ACTIVATE_REC_IMG;
        SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__INDIRECT_FIFO_CTRL_RESET__out_t INDIRECT_FIFO_CTRL_RESET;
    } SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__SOC_MGMT_RSVD_2__PLACEHOLDER__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__SOC_MGMT_RSVD_2__PLACEHOLDER__out_t PLACEHOLDER;
    } SoCManagementInterfaceRegisters__SOC_MGMT_RSVD_2__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__SOC_MGMT_RSVD_3__PLACEHOLDER__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__SOC_MGMT_RSVD_3__PLACEHOLDER__out_t PLACEHOLDER;
    } SoCManagementInterfaceRegisters__SOC_MGMT_RSVD_3__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__INPUT_ENABLE__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__SCHMITT_EN__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__KEEPER_EN__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__PULL_DIR__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__PULL_EN__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__IO_INVERSION__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__OD_EN__out_t;

    typedef struct {
        logic value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__VIRTUAL_OD_EN__out_t;

    typedef struct {
        logic [7:0] value;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__PAD_TYPE__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__INPUT_ENABLE__out_t INPUT_ENABLE;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__SCHMITT_EN__out_t SCHMITT_EN;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__KEEPER_EN__out_t KEEPER_EN;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__PULL_DIR__out_t PULL_DIR;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__PULL_EN__out_t PULL_EN;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__IO_INVERSION__out_t IO_INVERSION;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__OD_EN__out_t OD_EN;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__VIRTUAL_OD_EN__out_t VIRTUAL_OD_EN;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__PAD_TYPE__out_t PAD_TYPE;
    } SoCManagementInterfaceRegisters__SOC_PAD_CONF__out_t;

    typedef struct {
        logic [7:0] value;
    } SoCManagementInterfaceRegisters__SOC_PAD_ATTR__DRIVE_SLEW_RATE__out_t;

    typedef struct {
        logic [7:0] value;
    } SoCManagementInterfaceRegisters__SOC_PAD_ATTR__DRIVE_STRENGTH__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__SOC_PAD_ATTR__DRIVE_SLEW_RATE__out_t DRIVE_SLEW_RATE;
        SoCManagementInterfaceRegisters__SOC_PAD_ATTR__DRIVE_STRENGTH__out_t DRIVE_STRENGTH;
    } SoCManagementInterfaceRegisters__SOC_PAD_ATTR__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__SOC_MGMT_FEATURE_2__PLACEHOLDER__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__SOC_MGMT_FEATURE_2__PLACEHOLDER__out_t PLACEHOLDER;
    } SoCManagementInterfaceRegisters__SOC_MGMT_FEATURE_2__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__SOC_MGMT_FEATURE_3__PLACEHOLDER__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__SOC_MGMT_FEATURE_3__PLACEHOLDER__out_t PLACEHOLDER;
    } SoCManagementInterfaceRegisters__SOC_MGMT_FEATURE_3__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_R_REG__T_R__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_R_REG__T_R__out_t T_R;
    } SoCManagementInterfaceRegisters__T_R_REG__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_F_REG__T_F__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_F_REG__T_F__out_t T_F;
    } SoCManagementInterfaceRegisters__T_F_REG__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_SU_DAT_REG__T_SU_DAT__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_SU_DAT_REG__T_SU_DAT__out_t T_SU_DAT;
    } SoCManagementInterfaceRegisters__T_SU_DAT_REG__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_HD_DAT_REG__T_HD_DAT__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_HD_DAT_REG__T_HD_DAT__out_t T_HD_DAT;
    } SoCManagementInterfaceRegisters__T_HD_DAT_REG__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_HIGH_REG__T_HIGH__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_HIGH_REG__T_HIGH__out_t T_HIGH;
    } SoCManagementInterfaceRegisters__T_HIGH_REG__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_LOW_REG__T_LOW__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_LOW_REG__T_LOW__out_t T_LOW;
    } SoCManagementInterfaceRegisters__T_LOW_REG__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_HD_STA_REG__T_HD_STA__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_HD_STA_REG__T_HD_STA__out_t T_HD_STA;
    } SoCManagementInterfaceRegisters__T_HD_STA_REG__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_SU_STA_REG__T_SU_STA__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_SU_STA_REG__T_SU_STA__out_t T_SU_STA;
    } SoCManagementInterfaceRegisters__T_SU_STA_REG__out_t;

    typedef struct {
        logic [19:0] value;
    } SoCManagementInterfaceRegisters__T_SU_STO_REG__T_SU_STO__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_SU_STO_REG__T_SU_STO__out_t T_SU_STO;
    } SoCManagementInterfaceRegisters__T_SU_STO_REG__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__T_FREE_REG__T_FREE__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_FREE_REG__T_FREE__out_t T_FREE;
    } SoCManagementInterfaceRegisters__T_FREE_REG__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__T_AVAL_REG__T_AVAL__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_AVAL_REG__T_AVAL__out_t T_AVAL;
    } SoCManagementInterfaceRegisters__T_AVAL_REG__out_t;

    typedef struct {
        logic [31:0] value;
    } SoCManagementInterfaceRegisters__T_IDLE_REG__T_IDLE__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__T_IDLE_REG__T_IDLE__out_t T_IDLE;
    } SoCManagementInterfaceRegisters__T_IDLE_REG__out_t;

    typedef struct {
        SoCManagementInterfaceRegisters__EXTCAP_HEADER__out_t EXTCAP_HEADER;
        SoCManagementInterfaceRegisters__SOC_MGMT_CONTROL__out_t SOC_MGMT_CONTROL;
        SoCManagementInterfaceRegisters__SOC_MGMT_STATUS__out_t SOC_MGMT_STATUS;
        SoCManagementInterfaceRegisters__REC_INTF_CFG__out_t REC_INTF_CFG;
        SoCManagementInterfaceRegisters__REC_INTF_REG_W1C_ACCESS__out_t REC_INTF_REG_W1C_ACCESS;
        SoCManagementInterfaceRegisters__SOC_MGMT_RSVD_2__out_t SOC_MGMT_RSVD_2;
        SoCManagementInterfaceRegisters__SOC_MGMT_RSVD_3__out_t SOC_MGMT_RSVD_3;
        SoCManagementInterfaceRegisters__SOC_PAD_CONF__out_t SOC_PAD_CONF;
        SoCManagementInterfaceRegisters__SOC_PAD_ATTR__out_t SOC_PAD_ATTR;
        SoCManagementInterfaceRegisters__SOC_MGMT_FEATURE_2__out_t SOC_MGMT_FEATURE_2;
        SoCManagementInterfaceRegisters__SOC_MGMT_FEATURE_3__out_t SOC_MGMT_FEATURE_3;
        SoCManagementInterfaceRegisters__T_R_REG__out_t T_R_REG;
        SoCManagementInterfaceRegisters__T_F_REG__out_t T_F_REG;
        SoCManagementInterfaceRegisters__T_SU_DAT_REG__out_t T_SU_DAT_REG;
        SoCManagementInterfaceRegisters__T_HD_DAT_REG__out_t T_HD_DAT_REG;
        SoCManagementInterfaceRegisters__T_HIGH_REG__out_t T_HIGH_REG;
        SoCManagementInterfaceRegisters__T_LOW_REG__out_t T_LOW_REG;
        SoCManagementInterfaceRegisters__T_HD_STA_REG__out_t T_HD_STA_REG;
        SoCManagementInterfaceRegisters__T_SU_STA_REG__out_t T_SU_STA_REG;
        SoCManagementInterfaceRegisters__T_SU_STO_REG__out_t T_SU_STO_REG;
        SoCManagementInterfaceRegisters__T_FREE_REG__out_t T_FREE_REG;
        SoCManagementInterfaceRegisters__T_AVAL_REG__out_t T_AVAL_REG;
        SoCManagementInterfaceRegisters__T_IDLE_REG__out_t T_IDLE_REG;
    } SoCManagementInterfaceRegisters__out_t;

    typedef struct {
        logic [7:0] value;
    } ControllerConfigRegisters__EXTCAP_HEADER__CAP_ID__out_t;

    typedef struct {
        logic [15:0] value;
    } ControllerConfigRegisters__EXTCAP_HEADER__CAP_LENGTH__out_t;

    typedef struct {
        ControllerConfigRegisters__EXTCAP_HEADER__CAP_ID__out_t CAP_ID;
        ControllerConfigRegisters__EXTCAP_HEADER__CAP_LENGTH__out_t CAP_LENGTH;
    } ControllerConfigRegisters__EXTCAP_HEADER__out_t;

    typedef struct {
        logic [1:0] value;
    } ControllerConfigRegisters__CONTROLLER_CONFIG__OPERATION_MODE__out_t;

    typedef struct {
        ControllerConfigRegisters__CONTROLLER_CONFIG__OPERATION_MODE__out_t OPERATION_MODE;
    } ControllerConfigRegisters__CONTROLLER_CONFIG__out_t;

    typedef struct {
        ControllerConfigRegisters__EXTCAP_HEADER__out_t EXTCAP_HEADER;
        ControllerConfigRegisters__CONTROLLER_CONFIG__out_t CONTROLLER_CONFIG;
    } ControllerConfigRegisters__out_t;

    typedef struct {
        logic [7:0] value;
    } ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__TERMINATION_EXTCAP_HEADER__CAP_ID__out_t;

    typedef struct {
        logic [15:0] value;
    } ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__TERMINATION_EXTCAP_HEADER__CAP_LENGTH__out_t;

    typedef struct {
        ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__TERMINATION_EXTCAP_HEADER__CAP_ID__out_t CAP_ID;
        ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__TERMINATION_EXTCAP_HEADER__CAP_LENGTH__out_t CAP_LENGTH;
    } ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__TERMINATION_EXTCAP_HEADER__out_t;

    typedef struct {
        SecureFirmwareRecoveryInterfaceRegisters__out_t SecFwRecoveryIf;
        StandbyControllerModeRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__out_t StdbyCtrlMode;
        TargetTransactionInterfaceRegisters_rx_desc_fifo_size_5_tx_desc_fifo_size_5_rx_fifo_size_5_tx_fifo_size_5_ibi_fifo_size_5__out_t TTI;
        SoCManagementInterfaceRegisters__out_t SoCMgmtIf;
        ControllerConfigRegisters__out_t CtrlCfg;
        ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__TERMINATION_EXTCAP_HEADER__out_t TERMINATION_EXTCAP_HEADER;
    } ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__out_t;

    typedef struct {
        ECRegisters_pid_hi_7fff_pid_lo_5a00a5_virtual_pid_hi_7fff_virtual_pid_lo_5a10a5__out_t I3C_EC;
    } I3CCSR__out_t;
endpackage
