{#- PCILeech Sources Template -#}
{#- This template generates the source file inclusion script for PCILeech builds -#}
{{ header_comment if header_comment else "# PCILeech Sources Script" }}
#
# PCILeech FPGA Firmware Source Files
# Generated for: {{ device.vendor_id if device.vendor_id else "Unknown" }}:{{ device.device_id if device.device_id else "Unknown" }}
# Board: {{ board.name if board.name else "Unknown" }}
#

# Source directories
set src_dir "{{ pcileech.src_dir if pcileech.src_dir else 'src' }}"
set ip_dir "{{ pcileech.ip_dir if pcileech.ip_dir else 'ip' }}"

puts "Adding PCILeech source files..."

# Add PCILeech SystemVerilog source files
{% if pcileech.source_files %}
{% for source_file in pcileech.source_files %}
if {[file exists "$src_dir/{{ source_file }}"]} {
    add_files -norecurse "$src_dir/{{ source_file }}"
    puts "Added source file: {{ source_file }}"
} else {
    puts "WARNING: Source file not found: $src_dir/{{ source_file }}"
}
{% endfor %}
{% else %}
# Default PCILeech source files
set pcileech_sources [list \
    "pcileech_tlps128_bar_controller.sv" \
    "pcileech_fifo.sv" \
    "bar_controller.sv" \
    "cfg_shadow.sv" \
    "device_config.sv" \
    "msix_capability_registers.sv" \
    "msix_implementation.sv" \
    "msix_table.sv" \
    "option_rom_bar_window.sv" \
    "option_rom_spi_flash.sv" \
    "top_level_wrapper.sv" \
]

foreach source_file $pcileech_sources {
    if {[file exists "$src_dir/$source_file"]} {
        add_files -norecurse "$src_dir/$source_file"
        puts "Added source file: $source_file"
    } else {
        puts "WARNING: Source file not found: $src_dir/$source_file"
    }
}
{% endif %}

# Add PCILeech IP core files
{% if pcileech.ip_files %}
{% for ip_file in pcileech.ip_files %}
if {[file exists "$ip_dir/{{ ip_file }}"]} {
    add_files -norecurse "$ip_dir/{{ ip_file }}"
    puts "Added IP file: {{ ip_file }}"
} else {
    puts "WARNING: IP file not found: $ip_dir/{{ ip_file }}"
}
{% endfor %}
{% else %}
# Default PCILeech IP files
set pcileech_ip_files [list \
    "pcie_7x_0.xci" \
    "fifo_generator_0.xci" \
    "clk_wiz_0.xci" \
]

foreach ip_file $pcileech_ip_files {
    if {[file exists "$ip_dir/$ip_file"]} {
        add_files -norecurse "$ip_dir/$ip_file"
        puts "Added IP file: $ip_file"
    } else {
        puts "INFO: Optional IP file not found: $ip_dir/$ip_file"
    }
}
{% endif %}

# Add PCILeech coefficient files
{% if pcileech.coefficient_files %}
{% for coeff_file in pcileech.coefficient_files %}
if {[file exists "$src_dir/{{ coeff_file }}"]} {
    add_files -norecurse "$src_dir/{{ coeff_file }}"
    set_property file_type "Coefficient Files" [get_files "$src_dir/{{ coeff_file }}"]
    puts "Added coefficient file: {{ coeff_file }}"
} else {
    puts "WARNING: Coefficient file not found: $src_dir/{{ coeff_file }}"
}
{% endfor %}
{% else %}
# Default PCILeech coefficient files
set pcileech_coeff_files [list \
    "pcileech_cfgspace.coe" \
]

foreach coeff_file $pcileech_coeff_files {
    if {[file exists "$src_dir/$coeff_file"]} {
        add_files -norecurse "$src_dir/$coeff_file"
        set_property file_type "Coefficient Files" [get_files "$src_dir/$coeff_file"]
        puts "Added coefficient file: $coeff_file"
    } else {
        puts "INFO: Optional coefficient file not found: $src_dir/$coeff_file"
    }
}
{% endif %}

# Set top-level module
{% if top_module %}
set_property top {{ top_module }} [current_fileset]
{% else %}
set_property top pcileech_top [current_fileset]
{% endif %}

# Update compile order
update_compile_order -fileset sources_1

puts "PCILeech source files added successfully"