{#- PCILeech Header File Template -#}
{#- SystemVerilog Header File for PCILeech FPGA projects -#}
//
// PCILeech FPGA.
//
// SystemVerilog Header File for PCILeech FPGA projects.
//
// Generated by PCILeech Firmware Generator
//

`ifndef _pcileech_header_svh_
`define _pcileech_header_svh_

`define _bs16(v)   {{v}[7:0], {v}[15:8]}
`define _bs32(v)   {{v}[7:0], {v}[15:8], {v}[23:16], {v}[31:24]}

// ------------------------------------------------------------------------
// PCIe Configuration Parameters
// ------------------------------------------------------------------------
{%- if pcileech_config and pcileech_config.cfg_force_mps is defined %}
`define CFG_FORCE_MPS {{ pcileech_config.cfg_force_mps }}  // Force Maximum Payload Size encoding (0-5)
{%- else %}
`define CFG_FORCE_MPS 1  // Default: 256 bytes (encoding 1)
{%- endif %}

// ------------------------------------------------------------------------
// Interface connecting COM to FIFO module.
// ------------------------------------------------------------------------
interface IfComToFifo;
    wire [63:0]     com_dout;
    wire            com_dout_valid;
    wire [255:0]    com_din;
    wire            com_din_wr_en;
    wire            com_din_ready;

    modport mp_com (
        output com_dout, com_dout_valid, com_din_ready,
        input com_din, com_din_wr_en
    );

    modport mp_fifo (
        input com_dout, com_dout_valid, com_din_ready,
        output com_din, com_din_wr_en
    );
endinterface

// ------------------------------------------------------------------------
// Interface connecting PCIe to PCIe CFG module.
// ------------------------------------------------------------------------
interface IfPCIeSignals;
    // ------------------------------------------------------------------------
    // VALUES FROM PCIe TO module.
    // ------------------------------------------------------------------------
    wire    [7:0]       cfg_bus_number;
    wire    [4:0]       cfg_device_number;
    wire    [2:0]       cfg_function_number;
    
    wire    [15:0]      cfg_command;
    wire    [31:0]      cfg_mgmt_do;
    wire                cfg_mgmt_rd_wr_done;
    
    wire    [2:0]       pl_initial_link_width;
    wire                pl_phy_lnk_up;
    wire    [1:0]       pl_lane_reversal_mode;
    wire                pl_link_gen2_cap;
    wire                pl_link_partner_gen2_supported;
    wire                pl_link_upcfg_cap;
    wire                pl_sel_lnk_rate;
    wire    [1:0]       pl_sel_lnk_width;
    wire    [5:0]       pl_ltssm_state;
    wire    [1:0]       pl_rx_pm_state;
    wire    [2:0]       pl_tx_pm_state;
    wire                pl_directed_change_done;
    wire                pl_received_hot_rst;
    
    wire                cfg_aer_rooterr_corr_err_received;
    wire                cfg_aer_rooterr_corr_err_reporting_en;
    wire                cfg_aer_rooterr_fatal_err_received;
    wire                cfg_aer_rooterr_fatal_err_reporting_en;
    wire                cfg_aer_rooterr_non_fatal_err_received;
    wire                cfg_aer_rooterr_non_fatal_err_reporting_en;
    wire                cfg_bridge_serr_en;
    wire    [15:0]      cfg_dcommand;
    wire    [15:0]      cfg_dcommand2;
    wire    [15:0]      cfg_dstatus;
    wire    [15:0]      cfg_lcommand;
    wire    [15:0]      cfg_lstatus;
    wire    [2:0]       cfg_pcie_link_state;
    wire                cfg_pmcsr_pme_en;
    wire                cfg_pmcsr_pme_status;
    wire    [1:0]       cfg_pmcsr_powerstate;
    wire                cfg_received_func_lvl_rst;
    wire                cfg_root_control_pme_int_en;
    wire                cfg_root_control_syserr_corr_err_en;
    wire                cfg_root_control_syserr_fatal_err_en;
    wire                cfg_root_control_syserr_non_fatal_err_en;
    wire                cfg_slot_control_electromech_il_ctl_pulse;
    wire    [15:0]      cfg_status;
    wire                cfg_to_turnoff;
    wire    [5:0]       tx_buf_av;
    wire                tx_cfg_req;
    wire                tx_err_drop;
    wire    [6:0]       cfg_vc_tcvc_map;
    
    wire    [2:0]       cfg_interrupt_mmenable;
    wire                cfg_interrupt_msienable;
    wire                cfg_interrupt_msixenable;
    wire                cfg_interrupt_msixfm;
    wire                cfg_interrupt_rdy;
    wire    [7:0]       cfg_interrupt_do;
    
    // ------------------------------------------------------------------------
    // VALUES TO PCIe FROM module.
    // ------------------------------------------------------------------------
    wire    [31:0]      cfg_mgmt_di;
    wire    [3:0]       cfg_mgmt_byte_en;
    wire    [9:0]       cfg_mgmt_dwaddr;
    wire                cfg_mgmt_wr_en;
    wire                cfg_mgmt_rd_en;
    wire                cfg_mgmt_wr_readonly;
    
    wire                cfg_trn_pending;
    wire                cfg_pm_halt_aspm_l0s;
    wire                cfg_pm_halt_aspm_l1;
    wire                cfg_pm_force_state_en;
    wire    [1:0]       cfg_pm_force_state;
    wire                cfg_pm_wake;
    wire    [63:0]      cfg_dsn;
    wire                cfg_turnoff_ok;
    wire                cfg_pm_send_pme_to;
    wire    [7:0]       cfg_ds_bus_number;
    wire    [4:0]       cfg_ds_device_number;
    wire    [2:0]       cfg_ds_function_number;
    
    wire                cfg_interrupt;
    wire                cfg_interrupt_assert;
    wire    [7:0]       cfg_interrupt_di;
    wire                cfg_interrupt_stat;
    wire    [4:0]       cfg_pciecap_interrupt_msgnum;
    
    wire                pl_directed_link_auton;
    wire    [1:0]       pl_directed_link_change;
    wire                pl_directed_link_speed;
    wire    [1:0]       pl_directed_link_width;
    wire                pl_upstream_prefer_deemph;
    wire                pl_downstream_deemph_source;
    wire                pl_transmit_hot_rst;
    
    wire    [127:0]     cfg_err_aer_headerlog;
    wire    [4:0]       cfg_aer_interrupt_msgnum;
    wire                cfg_err_aer_headerlog_set;
    wire                cfg_aer_ecrc_check_en;
    wire                cfg_aer_ecrc_gen_en;
    
    wire                cfg_err_atomic_egress_blocked;
    wire                cfg_err_cor;
    wire                cfg_err_cpl_abort;
    wire                cfg_err_cpl_rdy;
    wire                cfg_err_cpl_timeout;
    wire                cfg_err_cpl_unexpect;
    wire                cfg_err_ecrc;
    wire                cfg_err_internal_cor;
    wire                cfg_err_internal_uncor;
    wire                cfg_err_locked;
    wire                cfg_err_malformed;
    wire                cfg_err_mc_blocked;
    wire                cfg_err_norecovery;
    wire                cfg_err_poisoned;
    wire                cfg_err_posted;
    wire    [47:0]      cfg_err_tlp_cpl_header;
    wire                cfg_err_ur;
    
    modport mp_pcie (
        output cfg_bus_number, cfg_device_number, cfg_function_number, cfg_command, cfg_mgmt_do, cfg_mgmt_rd_wr_done,
        output pl_initial_link_width, pl_phy_lnk_up, pl_lane_reversal_mode, pl_link_gen2_cap, pl_link_partner_gen2_supported, pl_link_upcfg_cap, pl_sel_lnk_rate, pl_sel_lnk_width, pl_ltssm_state, pl_rx_pm_state, pl_tx_pm_state, pl_directed_change_done, pl_received_hot_rst,
        output cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_fatal_err_received, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_bridge_serr_en, cfg_dcommand, cfg_dcommand2, cfg_dstatus, cfg_lcommand, cfg_lstatus, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_pme_status, cfg_pmcsr_powerstate, cfg_received_func_lvl_rst, cfg_root_control_pme_int_en, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_status, cfg_to_turnoff, tx_buf_av, tx_cfg_req, tx_err_drop, cfg_vc_tcvc_map,
        output cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_rdy, cfg_interrupt_do,
        input cfg_mgmt_di, cfg_mgmt_byte_en, cfg_mgmt_dwaddr, cfg_mgmt_wr_en, cfg_mgmt_rd_en, cfg_mgmt_wr_readonly,
        input cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_pm_wake, cfg_dsn, cfg_turnoff_ok, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number,
        input cfg_interrupt, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum,
        input pl_directed_link_auton, pl_directed_link_change, pl_directed_link_speed, pl_directed_link_width, pl_upstream_prefer_deemph, pl_downstream_deemph_source, pl_transmit_hot_rst,
        input cfg_err_aer_headerlog, cfg_aer_interrupt_msgnum, cfg_err_aer_headerlog_set, cfg_aer_ecrc_check_en, cfg_aer_ecrc_gen_en,
        input cfg_err_atomic_egress_blocked, cfg_err_cor, cfg_err_cpl_abort, cfg_err_cpl_rdy, cfg_err_cpl_timeout, cfg_err_cpl_unexpect, cfg_err_ecrc, cfg_err_internal_cor, cfg_err_internal_uncor, cfg_err_locked, cfg_err_malformed, cfg_err_mc_blocked, cfg_err_norecovery, cfg_err_poisoned, cfg_err_posted, cfg_err_tlp_cpl_header, cfg_err_ur
    );
    
    modport mp_module (
        input cfg_bus_number, cfg_device_number, cfg_function_number, cfg_command, cfg_mgmt_do, cfg_mgmt_rd_wr_done,
        input pl_initial_link_width, pl_phy_lnk_up, pl_lane_reversal_mode, pl_link_gen2_cap, pl_link_partner_gen2_supported, pl_link_upcfg_cap, pl_sel_lnk_rate, pl_sel_lnk_width, pl_ltssm_state, pl_rx_pm_state, pl_tx_pm_state, pl_directed_change_done, pl_received_hot_rst,
        input cfg_aer_rooterr_corr_err_received, cfg_aer_rooterr_corr_err_reporting_en, cfg_aer_rooterr_fatal_err_received, cfg_aer_rooterr_fatal_err_reporting_en, cfg_aer_rooterr_non_fatal_err_received, cfg_aer_rooterr_non_fatal_err_reporting_en, cfg_bridge_serr_en, cfg_dcommand, cfg_dcommand2, cfg_dstatus, cfg_lcommand, cfg_lstatus, cfg_pcie_link_state, cfg_pmcsr_pme_en, cfg_pmcsr_pme_status, cfg_pmcsr_powerstate, cfg_received_func_lvl_rst, cfg_root_control_pme_int_en, cfg_root_control_syserr_corr_err_en, cfg_root_control_syserr_fatal_err_en, cfg_root_control_syserr_non_fatal_err_en, cfg_slot_control_electromech_il_ctl_pulse, cfg_status, cfg_to_turnoff, tx_buf_av, tx_cfg_req, tx_err_drop, cfg_vc_tcvc_map,
        input cfg_interrupt_mmenable, cfg_interrupt_msienable, cfg_interrupt_msixenable, cfg_interrupt_msixfm, cfg_interrupt_rdy, cfg_interrupt_do,
        output cfg_mgmt_di, cfg_mgmt_byte_en, cfg_mgmt_dwaddr, cfg_mgmt_wr_en, cfg_mgmt_rd_en, cfg_mgmt_wr_readonly,
        output cfg_trn_pending, cfg_pm_halt_aspm_l0s, cfg_pm_halt_aspm_l1, cfg_pm_force_state_en, cfg_pm_force_state, cfg_pm_wake, cfg_dsn, cfg_turnoff_ok, cfg_pm_send_pme_to, cfg_ds_bus_number, cfg_ds_device_number, cfg_ds_function_number,
        output cfg_interrupt, cfg_interrupt_assert, cfg_interrupt_di, cfg_interrupt_stat, cfg_pciecap_interrupt_msgnum,
        output pl_directed_link_auton, pl_directed_link_change, pl_directed_link_speed, pl_directed_link_width, pl_upstream_prefer_deemph, pl_downstream_deemph_source, pl_transmit_hot_rst,
        output cfg_err_aer_headerlog, cfg_aer_interrupt_msgnum, cfg_err_aer_headerlog_set, cfg_aer_ecrc_check_en, cfg_aer_ecrc_gen_en,
        output cfg_err_atomic_egress_blocked, cfg_err_cor, cfg_err_cpl_abort, cfg_err_cpl_rdy, cfg_err_cpl_timeout, cfg_err_cpl_unexpect, cfg_err_ecrc, cfg_err_internal_cor, cfg_err_internal_uncor, cfg_err_locked, cfg_err_malformed, cfg_err_mc_blocked, cfg_err_norecovery, cfg_err_poisoned, cfg_err_posted, cfg_err_tlp_cpl_header, cfg_err_ur
    );
endinterface

// ------------------------------------------------------------------------
// Interface connecting PCIe CFG to FIFO
// ------------------------------------------------------------------------
interface IfPCIeFifoCfg;
    wire    [63:0]      tx_data;
    wire                tx_valid;
    wire    [31:0]      rx_data;
    wire                rx_valid;
    wire                rx_rd_en;

    modport mp_fifo (
        output tx_data, tx_valid, rx_rd_en,
        input rx_data, rx_valid
    );

    modport mp_pcie (
        input tx_data, tx_valid, rx_rd_en,
        output rx_data, rx_valid
    );
endinterface

// ------------------------------------------------------------------------
// Interface connecting PCIe TLP to FIFO
// ------------------------------------------------------------------------
interface IfPCIeFifoTlp;
    wire    [31:0]      tx_data;
    wire                tx_last;
    wire                tx_valid;   
    wire    [31:0]      rx_data[4];
    wire                rx_first[4];
    wire                rx_last[4];
    wire                rx_valid[4];
    wire                rx_rd_en;

    modport mp_fifo (
        output tx_data, tx_last, tx_valid, rx_rd_en,
        input rx_data, rx_first, rx_last, rx_valid
    );

    modport mp_pcie (
        input tx_data, tx_last, tx_valid, rx_rd_en,
        output rx_data, rx_first, rx_last, rx_valid
    );
endinterface

// ------------------------------------------------------------------------
// Interface connecting PCIe CORE config to FIFO
// ------------------------------------------------------------------------
interface IfPCIeFifoCore;
    // PCIe optional config
    wire                pcie_rst_core;
    wire                pcie_rst_subsys;
    // DRP config
    wire                drp_rdy;
    wire    [15:0]      drp_do;
    wire                drp_en;
    wire                drp_we;
    wire    [8:0]       drp_addr;
    wire    [15:0]      drp_di;
    
    modport mp_fifo (
        input drp_rdy, drp_do,
        output pcie_rst_core, pcie_rst_subsys, drp_en, drp_we, drp_addr, drp_di
    );

    modport mp_pcie (
        input pcie_rst_core, pcie_rst_subsys, drp_en, drp_we, drp_addr, drp_di,
        output drp_rdy, drp_do
    );
endinterface

interface IfShadow2Fifo;
    // SHADOW CONFIGURATION SPACE TO FIFO
    wire                rx_rden;
    wire                rx_wren;
    wire    [3:0]       rx_be;
    wire    [31:0]      rx_data;
    wire    [9:0]       rx_addr;
    wire                rx_addr_lo;
    wire                tx_valid;
    wire    [31:0]      tx_data;
    wire    [9:0]       tx_addr;
    wire                tx_addr_lo;
    wire                cfgtlp_wren;
    wire                cfgtlp_zero;
    wire                cfgtlp_en;
    wire                cfgtlp_filter;
    wire                alltlp_filter;
    wire                bar_en;
    wire                cfgtlp_pcie_write_en;  // CFGTLP PCIE WRITE ENABLE
    wire    [1:0]       cfg_a7;                // Configuration address bit 7
    
    modport fifo (
        output cfgtlp_wren, cfgtlp_zero, rx_rden, rx_wren, rx_be, rx_addr, rx_addr_lo, rx_data, cfgtlp_en, cfgtlp_filter, alltlp_filter, bar_en, cfgtlp_pcie_write_en, cfg_a7,
        input tx_valid, tx_addr, tx_addr_lo, tx_data
    );

    modport shadow (
        input cfgtlp_wren, cfgtlp_zero, rx_rden, rx_wren, rx_be, rx_addr, rx_addr_lo, rx_data, cfgtlp_en, cfgtlp_filter, alltlp_filter, bar_en, cfgtlp_pcie_write_en, cfg_a7,
        output tx_valid, tx_addr, tx_addr_lo, tx_data
    );
endinterface

`endif // _pcileech_header_svh_