# PCILeech Firmware Build Script
# Generated by PCILeech Firmware Generator
# Build System Version: {{ build_system_version }}
# Integration Type: {{ integration_type }}
# Device: {{ build_params.device_bdf }} (VID:{{ build_params.vendor_id }}, DID:{{ build_params.device_id }})

# Set project variables
set project_name "pcileech_firmware"
set project_dir "./pcileech_build"
set device_part "{{ build_params.device_part | default('xc7a35tcpg236-1') }}"

# Create project
create_project $project_name $project_dir -part $device_part -force

# Set project properties
set_property target_language Verilog [current_project]
set_property simulator_language Mixed [current_project]

# Add SystemVerilog source files
{% for sv_file in systemverilog_files %}
add_files -norecurse "{{ sv_file }}"
{% endfor %}

# Add constraint files
{% for constraint_file in constraint_files %}
add_files -fileset constrs_1 -norecurse "{{ constraint_file }}"
{% endfor %}

# Create and configure IP cores
{% for ip_core in ip_cores %}
# Create {{ ip_core.name }} IP
create_ip -name {{ ip_core.type }} -vendor xilinx.com -library ip -version {{ ip_core.version }} -module_name {{ ip_core.name }}
{% for param, value in ip_core.config.items() %}
set_property -dict [list CONFIG.{{ param }} "{{ value }}"] [get_ips {{ ip_core.name }}]
{% endfor %}

{% endfor %}

# Set build parameters based on device characteristics
set_param general.maxThreads {{ build_params.max_threads | default(8) }}
set_param synth.elaboration.rodinMoreOptions "rt::set_parameter var_size_limit 4194304"

# Configure synthesis settings
set_property strategy "Vivado Synthesis Defaults" [get_runs synth_1]

{% if build_params.enable_burst_optimization %}
# Enable burst optimization for high-frequency devices
set_property STEPS.SYNTH_DESIGN.ARGS.RETIMING true [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.PIPELINE_REGISTER true [get_runs synth_1]
{% endif %}

{% if build_params.enable_adaptive_timing %}
# Enable adaptive timing for complex timing patterns
set_property strategy "Performance_ExplorePostRoutePhysOpt" [get_runs impl_1]
{% endif %}

# Configure implementation settings
set_property strategy "Vivado Implementation Defaults" [get_runs impl_1]
set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]

# Set timing constraints based on device characteristics
{% set clock_period = (1000.0 / build_params.clock_frequency_mhz) | round(3) %}
{% set input_delay = (build_params.read_latency_cycles * clock_period) | round(3) %}
{% set output_delay = (build_params.write_latency_cycles * clock_period) | round(3) %}
create_clock -period {{ clock_period }} [get_ports clk]
set_input_delay -clock clk {{ input_delay }} [get_ports "*_data_in"]
set_output_delay -clock clk {{ output_delay }} [get_ports "*_data_out"]

# Run synthesis and implementation
launch_runs synth_1 -jobs {{ build_params.max_threads | default(8) }}
wait_on_run synth_1

launch_runs impl_1 -jobs {{ build_params.max_threads | default(8) }}
wait_on_run impl_1

# Generate bitstream
launch_runs impl_1 -to_step write_bitstream -jobs {{ build_params.max_threads | default(8) }}
wait_on_run impl_1

# Report timing and utilization
open_run impl_1
report_timing_summary -file timing_summary.rpt
report_utilization -file utilization.rpt
report_power -file power.rpt

puts "PCILeech firmware build completed successfully"
puts "Device: {{ build_params.device_bdf }}"
puts "Clock Frequency: {{ build_params.clock_frequency_mhz }} MHz"
puts "Advanced Features: {{ build_params.enable_advanced_features }}"
puts "DMA Operations: {{ build_params.enable_dma_operations }}"