{#- PCILeech Project Setup Template -#}
{#- This template generates the main project setup script for PCILeech builds -#}
{{ header_comment if header_comment else "# PCILeech Project Setup Script" }}
#
# PCILeech FPGA Firmware Project Setup
# Generated for: {{ device.vendor_id if device.vendor_id else "Unknown" }}:{{ device.device_id if device.device_id else "Unknown" }}
# Board: {{ board.name if board.name else "Unknown" }}
# FPGA Part: {{ board.fpga_part if board.fpga_part else "Unknown" }}
#

# Set project variables
set project_name "{{ project.name if project.name else 'pcileech_firmware' }}"
set project_dir "{{ project.dir if project.dir else './vivado_project' }}"
set output_dir "{{ project.output_dir if project.output_dir else '.' }}"

# PCILeech-specific directories
set pcileech_src_dir "{{ pcileech.src_dir if pcileech.src_dir else 'src' }}"
set pcileech_ip_dir "{{ pcileech.ip_dir if pcileech.ip_dir else 'ip' }}"

# Device configuration
set fpga_part "{{ board.fpga_part if board.fpga_part else 'xc7a35tcsg324-2' }}"
set fpga_family "{{ board.fpga_family if board.fpga_family else 'Artix-7' }}"

# PCIe configuration
set pcie_ip_type "{{ board.pcie_ip_type if board.pcie_ip_type else 'pcie7x' }}"
set max_lanes {{ max_lanes if max_lanes else 4 }}

# Device identification
{% if device.vendor_id %}
set vendor_id {{ device.vendor_id }}
{% endif %}
{% if device.device_id %}
set device_id {{ device.device_id }}
{% endif %}
{% if device.class_code %}
set class_code {{ device.class_code }}
{% endif %}
{% if device.revision_id %}
set revision_id {{ device.revision_id }}
{% endif %}

# Create project
puts "Creating PCILeech project: $project_name"
create_project $project_name $project_dir -part $fpga_part -force

# Set project properties
set_property target_language Verilog [current_project]
set_property simulator_language Mixed [current_project]
set_property default_lib xil_defaultlib [current_project]

# Enable PCILeech-specific project settings
set_property strategy {{ synthesis_strategy if synthesis_strategy else 'Vivado Synthesis Defaults' }} [get_runs synth_1]
set_property strategy {{ implementation_strategy if implementation_strategy else 'Performance_Explore' }} [get_runs impl_1]

# Configure build settings for PCILeech
{% if build.batch_mode %}
set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION off [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.BUFG 12 [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.FANOUT_LIMIT 400 [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION one_hot [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.RESOURCE_SHARING off [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.NO_LC true [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.SHREG_MIN_SIZE 5 [get_runs synth_1]
{% endif %}

puts "PCILeech project setup completed successfully"