{#- PCILeech Implementation Template -#}
{#- This template generates PCILeech-specific implementation settings for Vivado -#}
{{ header_comment if header_comment else "# PCILeech Implementation Script" }}
#
# PCILeech FPGA Firmware Implementation Settings
# Generated for: {{ device.vendor_id if device.vendor_id else "Unknown" }}:{{ device.device_id if device.device_id else "Unknown" }}
# Board: {{ board.name if board.name else "Unknown" }}
# FPGA Part: {{ board.fpga_part if board.fpga_part else "Unknown" }}
#

puts "Configuring PCILeech implementation settings..."

# Implementation strategy
set impl_strategy "{{ implementation_strategy if implementation_strategy else 'Performance_Explore' }}"
set_property strategy $impl_strategy [get_runs impl_1]

# PCILeech-specific implementation settings
set_property STEPS.OPT_DESIGN.ARGS.DIRECTIVE {{ opt_directive if opt_directive else 'Explore' }} [get_runs impl_1]
set_property STEPS.PLACE_DESIGN.ARGS.DIRECTIVE {{ place_directive if place_directive else 'Explore' }} [get_runs impl_1]
set_property STEPS.PHYS_OPT_DESIGN.ARGS.DIRECTIVE {{ phys_opt_directive if phys_opt_directive else 'Explore' }} [get_runs impl_1]
set_property STEPS.ROUTE_DESIGN.ARGS.DIRECTIVE {{ route_directive if route_directive else 'Explore' }} [get_runs impl_1]

# Enable physical optimization
set_property STEPS.PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]

# PCILeech timing optimization
set_property STEPS.OPT_DESIGN.ARGS.VERBOSE true [get_runs impl_1]
set_property STEPS.PLACE_DESIGN.ARGS.VERBOSE true [get_runs impl_1]
set_property STEPS.ROUTE_DESIGN.ARGS.VERBOSE true [get_runs impl_1]

# PCIe-specific implementation settings
{% if board.pcie_ip_type == "pcie7x" %}
# PCIe 7-series optimizations
set_property STEPS.PLACE_DESIGN.ARGS.MORE_OPTIONS {-fanout_opt} [get_runs impl_1]
set_property STEPS.ROUTE_DESIGN.ARGS.MORE_OPTIONS {-tns_cleanup} [get_runs impl_1]
{% elif board.pcie_ip_type == "ultrascale" %}
# UltraScale+ optimizations
set_property STEPS.PLACE_DESIGN.ARGS.MORE_OPTIONS {-ultrathreads} [get_runs impl_1]
set_property STEPS.ROUTE_DESIGN.ARGS.MORE_OPTIONS {-ultrathreads} [get_runs impl_1]
{% endif %}

# PCILeech BAR controller optimization
set_property STEPS.PHYS_OPT_DESIGN.ARGS.MORE_OPTIONS {-critical_cell_opt -critical_pin_opt -rewire} [get_runs impl_1]

# MSI-X optimization
{% if supports_msix %}
set_property STEPS.POST_ROUTE_PHYS_OPT_DESIGN.ARGS.MORE_OPTIONS {-critical_cell_opt -hold_fix -rewire} [get_runs impl_1]
{% endif %}

# Device-specific optimizations
{% if device.class_code == "0x020000" %}
# Network controller optimizations
set_property STEPS.ROUTE_DESIGN.ARGS.MORE_OPTIONS {-preserve_loops} [get_runs impl_1]
{% elif device.class_code == "0x040300" %}
# Audio controller optimizations
set_property STEPS.PLACE_DESIGN.ARGS.MORE_OPTIONS {-timing_summary} [get_runs impl_1]
{% endif %}

# Power optimization for PCILeech
{% if enable_power_opt %}
set_property STEPS.POWER_OPT_DESIGN.IS_ENABLED true [get_runs impl_1]
set_property STEPS.POWER_OPT_DESIGN.ARGS.MORE_OPTIONS {-verbose} [get_runs impl_1]
{% endif %}

# Incremental implementation for faster builds
{% if enable_incremental %}
set_property AUTO_INCREMENTAL_CHECKPOINT true [get_runs impl_1]
{% endif %}

# Parallel implementation jobs
{% if build.jobs %}
set_property STEPS.PLACE_DESIGN.ARGS.JOBS {{ build.jobs }} [get_runs impl_1]
set_property STEPS.ROUTE_DESIGN.ARGS.JOBS {{ build.jobs }} [get_runs impl_1]
{% endif %}

# Report generation
set_property STEPS.WRITE_BITSTREAM.ARGS.BIN_FILE true [get_runs impl_1]
set_property STEPS.ROUTE_DESIGN.ARGS.REPORT_ALL true [get_runs impl_1]

# PCILeech-specific reports
set_property STEPS.ROUTE_DESIGN.TCL.POST {
    report_timing_summary -delay_type min_max -report_unconstrained -check_timing_verbose -max_paths 10 -input_pins -routable_nets -file timing_summary.rpt
    report_power -file power_report.rpt
    report_drc -file drc_report.rpt
    report_utilization -file utilization_report.rpt
    report_clock_utilization -file clock_utilization_report.rpt
} [get_runs impl_1]

# Bitstream generation settings
set_property STEPS.WRITE_BITSTREAM.ARGS.VERBOSE true [get_runs impl_1]

# PCILeech bitstream configuration
set_property BITSTREAM.GENERAL.COMPRESS true [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]

# Device identification in bitstream
{% if device.vendor_id and device.device_id %}
set_property BITSTREAM.CONFIG.USR_ACCESS "0x{{ device.vendor_id }}{{ device.device_id }}" [current_design]
{% endif %}

puts "PCILeech implementation settings configured successfully"