; PCILeech Configuration Space COE File
; Generated by PCILeech Firmware Generator
;
; This file contains the configuration space data for PCILeech firmware
; based on the analyzed device configuration and behavior profile.
;
; Device Information:
; - Vendor ID: {{ config_space.vendor_id | default("8086") }}
; - Device ID: {{ config_space.device_id | default("15B8") }}
; - Class Code: {{ config_space.class_code | default("020000") }}
; - Revision ID: {{ config_space.revision_id | default("01") }}
;
; Generation Metadata:
; - Generated: {{ generation_metadata.generated_at | default("Unknown") }}
; - Device BDF: {{ device_config.device_bdf | default("Unknown") }}
; - Has Behavior Profile: {{ device_config.behavior_profile is defined }}
; - MSI-X Vectors: {{ msix_config.num_vectors | default(0) }}

memory_initialization_radix=16;
memory_initialization_vector=

; Standard PCI Configuration Header (0x00-0x3F)
; Vendor ID (0x00-0x01) and Device ID (0x02-0x03)
{{ config_space.device_id | default("15B8") | string }}{{ config_space.vendor_id | default("8086") | string }},

; Command Register (0x04-0x05) and Status Register (0x06-0x07)
; Command: Memory Space Enable + Bus Master Enable
; Status: Capabilities List + Fast Back-to-Back + 66MHz Capable
{% if device_config.enable_dma_operations %}
0210{% else %}0200{% endif %}0006,

; Revision ID (0x08), Programming Interface (0x09), Sub Class (0x0A), Base Class (0x0B)
{{ config_space.class_code | default("020000") | string }}{{ config_space.revision_id | default("01") | string }},

; Cache Line Size (0x0C), Latency Timer (0x0D), Header Type (0x0E), BIST (0x0F)
00001010,

; Base Address Register 0 (0x10-0x13) - Memory BAR
{% if bar_config.bars and bar_config.bars|length > 0 %}
{% set bar = bar_config.bars[0] %}
{% if bar.size > 0 and hasattr(bar, 'get_size_encoding') %}
; BAR0: {{ bar.bar_type }} BAR, Size: {{ "0x%X" | format(bar.size) }} bytes
{{ "%08X" | format(bar.get_size_encoding()) }},
{% else %}
; BAR0: Using base address (no size encoding available)
{{ "%08X" | format(bar.base_address | default(0xF0000000)) }},
{% endif %}
{% else %}
; BAR0: Default memory BAR (64KB)
FFFF0004,
{% endif %}

; Base Address Register 1 (0x14-0x17) - Upper 32 bits for 64-bit BAR or second BAR
{% if bar_config.bars and bar_config.bars|length > 0 and bar_config.bars[0].is_64bit %}
; BAR1: Upper 32 bits of 64-bit BAR0
FFFFFFFF,
{% elif bar_config.bars and bar_config.bars|length > 1 %}
{% set bar = bar_config.bars[1] %}
{% if bar.size > 0 and hasattr(bar, 'get_size_encoding') %}
; BAR1: {{ bar.bar_type }} BAR, Size: {{ "0x%X" | format(bar.size) }} bytes
{{ "%08X" | format(bar.get_size_encoding()) }},
{% else %}
; BAR1: Using base address (no size encoding available)
{{ "%08X" | format(bar.base_address | default(0x00000000)) }},
{% endif %}
{% else %}
; BAR1: Disabled
00000000,
{% endif %}

; Base Address Register 2 (0x18-0x1B) - I/O BAR or third memory BAR
{% if bar_config.bars and bar_config.bars|length > 2 %}
{% set bar = bar_config.bars[2] %}
{% if bar.size > 0 and hasattr(bar, 'get_size_encoding') %}
; BAR2: {{ bar.bar_type }} BAR, Size: {{ "0x%X" | format(bar.size) }} bytes
{{ "%08X" | format(bar.get_size_encoding()) }},
{% else %}
; BAR2: Using base address (no size encoding available)
{{ "%08X" | format(bar.base_address | default(0x0000E001)) }},
{% endif %}
{% else %}
; BAR2: Default I/O BAR (256 bytes)
FFFFFF01,
{% endif %}

; Base Address Register 3 (0x1C-0x1F) - Fourth BAR
{% if bar_config.bars and bar_config.bars|length > 3 %}
{% set bar = bar_config.bars[3] %}
{% if bar.size > 0 and hasattr(bar, 'get_size_encoding') %}
; BAR3: {{ bar.bar_type }} BAR, Size: {{ "0x%X" | format(bar.size) }} bytes
{{ "%08X" | format(bar.get_size_encoding()) }},
{% else %}
; BAR3: Using base address (no size encoding available)
{{ "%08X" | format(bar.base_address | default(0x00000000)) }},
{% endif %}
{% else %}
; BAR3: Disabled
00000000,
{% endif %}

; Base Address Register 4 (0x20-0x23) - Fifth BAR
{% if bar_config.bars and bar_config.bars|length > 4 %}
{% set bar = bar_config.bars[4] %}
{% if bar.size > 0 and hasattr(bar, 'get_size_encoding') %}
; BAR4: {{ bar.bar_type }} BAR, Size: {{ "0x%X" | format(bar.size) }} bytes
{{ "%08X" | format(bar.get_size_encoding()) }},
{% else %}
; BAR4: Using base address (no size encoding available)
{{ "%08X" | format(bar.base_address | default(0x00000000)) }},
{% endif %}
{% else %}
; BAR4: Disabled
00000000,
{% endif %}

; Base Address Register 5 (0x24-0x27) - Sixth BAR
{% if bar_config.bars and bar_config.bars|length > 5 %}
{% set bar = bar_config.bars[5] %}
{% if bar.size > 0 and hasattr(bar, 'get_size_encoding') %}
; BAR5: {{ bar.bar_type }} BAR, Size: {{ "0x%X" | format(bar.size) }} bytes
{{ "%08X" | format(bar.get_size_encoding()) }},
{% else %}
; BAR5: Using base address (no size encoding available)
{{ "%08X" | format(bar.base_address | default(0x00000000)) }},
{% endif %}
{% else %}
; BAR5: Disabled
00000000,
{% endif %}

; Cardbus CIS Pointer (0x28-0x2B) - Unused
00000000,

; Subsystem Vendor ID (0x2C-0x2D) and Subsystem ID (0x2E-0x2F)
{{ config_space.device_id | default("0000") | string }}{{ config_space.vendor_id | default("8086") | string }},

; Expansion ROM Base Address (0x30-0x33) - Disabled
00000000,

; Capabilities Pointer (0x34), Reserved (0x35-0x3B)
00000040,

; Interrupt Line (0x3C), Interrupt Pin (0x3D), Min_Gnt (0x3E), Max_Lat (0x3F)
{% if msix_config.is_supported %}
0000010B,
{% else %}
0000010B,
{% endif %}

; Capabilities List starts at 0x40
; Power Management Capability (0x40-0x47)
; Cap ID=0x01, Next=0x50, PMC=0x0003, PMCSR=0x0000
00030150,
00000000,

; MSI Capability (0x48-0x4F) - if not using MSI-X
{% if not msix_config.is_supported %}
; Cap ID=0x05, Next=0x60, Message Control=0x0080 (64-bit capable)
00800560,
; Message Address Lower 32 bits
00000000,
{% else %}
; Reserved space when MSI-X is used
00000000,
00000000,
{% endif %}

; MSI-X Capability (0x50-0x5B) - if supported
{% if msix_config.is_supported %}
; Cap ID=0x11, Next=0x70, Message Control={{ "%04X" | format((msix_config.num_vectors - 1) | default(0) | int) }}
{{ "%04X" | format((msix_config.num_vectors - 1) | default(0) | int) }}7011,
; Table Offset/BIR: Offset={{ "%08X" | format(msix_config.table_offset | default(0x1000) | int) }}, BIR={{ msix_config.table_bir | default(0) }}
{% set table_offset_bir = (msix_config.table_offset | default(0x1000) | int) + (msix_config.table_bir | default(0)) %}{{ "%08X" | format(table_offset_bir) }},
; PBA Offset/BIR: Offset={{ "%08X" | format(msix_config.pba_offset | default(0x2000) | int) }}, BIR={{ msix_config.pba_bir | default(0) }}
{% set pba_offset_bir = (msix_config.pba_offset | default(0x2000) | int) + (msix_config.pba_bir | default(0)) %}{{ "%08X" | format(pba_offset_bir) }},
{% else %}
; No MSI-X capability
00000000,
00000000,
00000000,
{% endif %}

; PCIe Capability (0x60-0x9F) - Modern devices
; Cap ID=0x10, Next=0x00 (end of chain), PCIe Capabilities=0x0002
00020010,
; Device Capabilities
00000000,
; Device Control and Status
00000000,
; Link Capabilities
00000000,
; Link Control and Status
00000000,
; Slot Capabilities (if applicable)
00000000,
; Slot Control and Status
00000000,
; Root Capabilities
00000000,
; Root Control and Status
00000000,
; Device Capabilities 2
00000000,
; Device Control 2 and Status 2
00000000,
; Link Capabilities 2
00000000,
; Link Control 2 and Status 2
00000000,
; Slot Capabilities 2
00000000,
; Slot Control 2 and Status 2
00000000,

{% if device_config.enable_advanced_features %}
; Advanced Error Reporting Capability (0xA0-0xDF) - if enabled
; Cap ID=0x01, Next=0x00, AER Capabilities=0x0000
00000001,
; Uncorrectable Error Status
00000000,
; Uncorrectable Error Mask
00000000,
; Uncorrectable Error Severity
00000000,
; Correctable Error Status
00000000,
; Correctable Error Mask
00000000,
; Advanced Error Capabilities and Control
00000000,
; Header Log (4 DWORDs)
00000000,
00000000,
00000000,
00000000,
; Root Error Command
00000000,
; Root Error Status
00000000,
; Error Source Identification
00000000,
; Reserved
00000000,
00000000,
00000000,
{% endif %}

{% if device_config.has_manufacturing_variance %}
; Device-Specific Configuration based on Manufacturing Variance
; Timing adjustments based on behavior profile
{% if timing_config.timing_regularity > 0.8 %}
; High regularity device - optimized timing
{% elif timing_config.timing_regularity < 0.3 %}
; Low regularity device - conservative timing
{% endif %}
{% endif %}

; Extended Configuration Space (0x100-0xFFF) - mostly zeros for basic implementation
{% for i in range(0x100, 0x1000, 4) %}
{% if loop.index % 16 == 1 %}
; Offset {{ "%03X" | format(i) }}
{% endif %}
00000000{% if not loop.last %},{% endif %}
{% endfor %};

; PCILeech-Specific Configuration Data
; This section contains device-specific configuration derived from behavior analysis
;
{% if device_config.behavior_profile %}
; Behavior Profile Summary:
; - Total Register Accesses: {{ device_config.total_register_accesses | default(0) }}
; - Capture Duration: {{ device_config.capture_duration | default(0) }}s
; - Timing Patterns: {{ device_config.timing_patterns_count | default(0) }}
; - State Transitions: {{ device_config.state_transitions_count | default(0) }}
{% endif %}
;
; PCILeech Configuration:
; - Command Timeout: {{ pcileech_config.command_timeout | default(1000) }} cycles
; - Buffer Size: {{ pcileech_config.buffer_size | default(4096) }} bytes
; - DMA Operations: {{ pcileech_config.enable_dma | default(false) }}
; - Scatter-Gather: {{ pcileech_config.enable_scatter_gather | default(true) }}
;
; Timing Configuration:
; - Read Latency: {{ timing_config.read_latency | default(4) }} cycles
; - Write Latency: {{ timing_config.write_latency | default(2) }} cycles
; - Burst Length: {{ timing_config.burst_length | default(16) }}
; - Clock Frequency: {{ timing_config.clock_frequency_mhz | default(100.0) }} MHz
;
; BAR Configuration:
; - Primary BAR Index: {{ bar_config.bar_index | default(0) }}
; - Aperture Size: {{ bar_config.aperture_size | default(65536) }} bytes
; - BAR Type: {{ bar_config.bar_type | default(0) }} (0=32-bit, 1=64-bit)
; - Prefetchable: {{ bar_config.prefetchable | default(0) }}
