{#
PCIe UltraScale IP Configuration Template

This template generates PCIe UltraScale IP core configuration for
UltraScale and UltraScale+ parts.

Context variables expected:
- device: Device information (vendor_id, device_id, revision_id)
- board: Board information (name, fpga_part)
#}
{{ header }}

puts "Creating PCIe UltraScale IP core for device {{ device.vendor_id }}:{{ device.device_id }}..."
puts "FPGA Part: {{ board.fpga_part }}"
puts "Board: {{ board.name }}"

# Create PCIe UltraScale IP core with specific version for reproducible builds
create_ip -name pcie4_uscale_plus -vendor xilinx.com -library ip -version 1.3 -module_name pcie4_uscale_plus_0

# Get IP instance for cleaner code
set ip [get_ips pcie4_uscale_plus_0]

# Configure PCIe UltraScale IP core with device-specific settings
set_property -dict [list \
    CONFIG.PL_LINK_CAP_MAX_LINK_SPEED {2.5_GT/s} \
    CONFIG.PL_LINK_CAP_MAX_LINK_WIDTH {X1} \
    CONFIG.AXISTEN_IF_EXT_512_RQ_STRADDLE {false} \
    CONFIG.PF0_DEVICE_ID {0x{{ device.device_id }}} \
    CONFIG.PF0_VENDOR_ID {0x{{ device.vendor_id }}} \
    CONFIG.PF0_SUBSYSTEM_VENDOR_ID {0x{{ device.vendor_id }}} \
    CONFIG.PF0_SUBSYSTEM_ID {0x0000} \
    CONFIG.PF0_REVISION_ID {0x{{ device.revision_id }}} \
    CONFIG.PF0_CLASS_CODE {0x040300} \
    CONFIG.PF0_BAR0_SCALE {Kilobytes} \
    CONFIG.PF0_BAR0_SIZE {128} \
    CONFIG.PF0_MSI_ENABLED {false} \
    CONFIG.PF0_MSIX_ENABLED {true} \
] $ip

# Generate IP targets for complete synthesis flow
generate_target {instantiation_template synthesis implementation} $ip

# Export IP user files for out-of-context runs
export_ip_user_files -of_objects $ip -force

puts "PCIe UltraScale IP core configuration completed"