{{ header_comment }}
puts "setting project up..."

{%- from "_helpers.j2" import safe_name, safe_attr, board_name, board_fpga_part, safe_board_name, safe_board_fpga_part %}
{%- from "_helpers.j2" import safe_name, safe_attr %}
# Set project variables
set project_name "{{ safe_name(project) }}"
set project_dir "{{ safe_attr(project, 'dir', project_dir|default('./vivado_project')) }}"
set output_dir "{{ safe_attr(project, 'output_dir', '.') }}"

# PCILeech-specific directories
set pcileech_src_dir "{{ safe_attr(pcileech, 'src_dir', 'src') }}"
set pcileech_ip_dir "{{ safe_attr(pcileech, 'ip_dir', 'ip') }}"

# Device configuration
set fpga_part "{{ safe_attr(board, 'fpga_part', 'xc7a35tcsg324-2') }}"
set fpga_family "{{ safe_attr(board, 'fpga_family', 'Artix-7') }}"

# PCIe configuration
set pcie_ip_type "{{ safe_attr(board, 'pcie_ip_type', 'pcie7x') }}"
set max_lanes {{ max_lanes if max_lanes else 4 }}

# Device identification
{% if device.vendor_id %}
set vendor_id {{ device.vendor_id }}
{% endif %}
{% if device.device_id %}
set device_id {{ device.device_id }}
{% endif %}
{% if device.class_code %}
set class_code {{ device.class_code }}
{% endif %}
{% if device.revision_id %}
set revision_id {{ device.revision_id }}
{% endif %}

# Create project
puts "Creating PCILeech project: $project_name"
create_project $project_name $project_dir -part $fpga_part -force

# Set project properties
set_property target_language Verilog [current_project]
set_property simulator_language Mixed [current_project]
set_property default_lib xil_defaultlib [current_project]

# Enable PCILeech-specific project settings
set_property strategy {{ synthesis_strategy if synthesis_strategy else 'Vivado Synthesis Defaults' }} [get_runs synth_1]
set_property strategy {{ implementation_strategy if implementation_strategy else 'Performance_Explore' }} [get_runs impl_1]

# Configure build settings for PCILeech
{% if build.batch_mode %}
set_property STEPS.SYNTH_DESIGN.ARGS.FLATTEN_HIERARCHY rebuilt [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.GATED_CLOCK_CONVERSION off [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.BUFG 12 [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.FANOUT_LIMIT 400 [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.FSM_EXTRACTION one_hot [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.KEEP_EQUIVALENT_REGISTERS true [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.RESOURCE_SHARING off [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.NO_LC true [get_runs synth_1]
set_property STEPS.SYNTH_DESIGN.ARGS.SHREG_MIN_SIZE 5 [get_runs synth_1]
{% endif %}

puts "PCILeech project setup completed successfully"