# Generated from VerilogParser.g4 by ANTLR 4.7.2
# encoding: utf-8
from antlr4 import *
from io import StringIO
from typing.io import TextIO
import sys

def serializedATN():
    with StringIO() as buf:
        buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\u00f7")
        buf.write("\u11c2\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7")
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        buf.write("\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23\t\23")
        buf.write("\4\24\t\24\4\25\t\25\4\26\t\26\4\27\t\27\4\30\t\30\4\31")
        buf.write("\t\31\4\32\t\32\4\33\t\33\4\34\t\34\4\35\t\35\4\36\t\36")
        buf.write("\4\37\t\37\4 \t \4!\t!\4\"\t\"\4#\t#\4$\t$\4%\t%\4&\t")
        buf.write("&\4\'\t\'\4(\t(\4)\t)\4*\t*\4+\t+\4,\t,\4-\t-\4.\t.\4")
        buf.write("/\t/\4\60\t\60\4\61\t\61\4\62\t\62\4\63\t\63\4\64\t\64")
        buf.write("\4\65\t\65\4\66\t\66\4\67\t\67\48\t8\49\t9\4:\t:\4;\t")
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        buf.write("V\4W\tW\4X\tX\4Y\tY\4Z\tZ\4[\t[\4\\\t\\\4]\t]\4^\t^\4")
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        buf.write("z\tz\4{\t{\4|\t|\4}\t}\4~\t~\4\177\t\177\4\u0080\t\u0080")
        buf.write("\4\u0081\t\u0081\4\u0082\t\u0082\4\u0083\t\u0083\4\u0084")
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        buf.write("\u1133\u1136\u113c\u1142\u1168\u1171\u118a\u1191\u1197")
        return buf.getvalue()


class VerilogParser ( Parser ):

    grammarFileName = "VerilogParser.g4"

    atn = ATNDeserializer().deserialize(serializedATN())

    decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ]

    sharedContextCache = PredictionContextCache()

    literalNames = [ "<INVALID>", "'always'", "'and'", "'assign'", "'automatic'", 
                     "'begin'", "'buf'", "'bufif1'", "'bufif0'", "'case'", 
                     "'casex'", "'casez'", "'cell'", "'cmos'", "'config'", 
                     "'deassign'", "'default'", "'defparam'", "'design'", 
                     "'disable'", "'$fullskew'", "'$hold'", "'$nochange'", 
                     "'$period'", "'$recovery'", "'$recrem'", "'$removal'", 
                     "'$setup'", "'$setuphold'", "'$skew'", "'$timeskew'", 
                     "'$width'", "'edge'", "'else'", "'end'", "'endcase'", 
                     "'endconfig'", "'endfunction'", "'endgenerate'", "'endmodule'", 
                     "'endprimitive'", "'endspecify'", "'endtable'", "'endtask'", 
                     "'event'", "'for'", "'force'", "'forever'", "'fork'", 
                     "'function'", "'generate'", "'genvar'", "'highz1'", 
                     "'highz0'", "'if'", "'ifnone'", "'include'", "'initial'", 
                     "'inout'", "'input'", "'instance'", "'integer'", "'join'", 
                     "'large'", "'liblist'", "'library'", "'localparam'", 
                     "'macromodule'", "'medium'", "'-incdir'", "'module'", 
                     "'nand'", "'negedge'", "'nmos'", "'nor'", "'noshowcancelled'", 
                     "'not'", "'notif1'", "'notif0'", "'or'", "'output'", 
                     "'parameter'", "'PATHPULSE$'", "'pmos'", "'posedge'", 
                     "'primitive'", "'pulldown'", "'pull1'", "'pullup'", 
                     "'pull0'", "'pulsestyle_ondetect'", "'pulsestyle_onevent'", 
                     "'rcmos'", "'real'", "'realtime'", "'reg'", "'release'", 
                     "'repeat'", "'rnmos'", "'rpmos'", "'rtran'", "'rtranif1'", 
                     "'rtranif0'", "'scalared'", "'showcancelled'", "'signed'", 
                     "'small'", "'specify'", "'specparam'", "'strong1'", 
                     "'strong0'", "'supply1'", "'supply0'", "'table'", "'task'", 
                     "'time'", "'tran'", "'tranif1'", "'tranif0'", "'tri'", 
                     "'triand'", "'tri1'", "'trior'", "'trireg'", "'tri0'", 
                     "'use'", "'uwire'", "'vectored'", "'wait'", "'wand'", 
                     "'weak1'", "'weak0'", "'while'", "'wire'", "'wor'", 
                     "'xnor'", "'xor'", "'&'", "'&&'", "'&&&'", "'*'", "'**'", 
                     "'*>'", "'@'", "'^'", "'^~'", "':'", "','", "'$'", 
                     "'\"'", "'.'", "'!'", "'!='", "'!=='", "'='", "'=='", 
                     "'==='", "'=>'", "<INVALID>", "'>'", "'>='", "'>>'", 
                     "'>>>'", "'#'", "'['", "'{'", "'('", "'<'", "'<='", 
                     "'<<'", "'<<<'", "'-'", "'-:'", "'->'", "'%'", "'+'", 
                     "'+:'", "'?'", "']'", "'}'", "')'", "';'", "'/'", "'~'", 
                     "'~&'", "'~^'", "'~|'", "'|'", "'||'", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "'celldefine'", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "'end_keywords'", "'endcelldefine'", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "'nounconnected_drive'", 
                     "<INVALID>", "'resetall'", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "'``'", "<INVALID>", "'`\\`\"'", 
                     "'`\"'" ]

    symbolicNames = [ "<INVALID>", "ALWAYS", "AND", "ASSIGN", "AUTOMATIC", 
                      "BEGIN", "BUF", "BUFIFONE", "BUFIFZERO", "CASE", "CASEX", 
                      "CASEZ", "CELL", "CMOS", "CONFIG", "DEASSIGN", "DEFAULT", 
                      "DEFPARAM", "DESIGN", "DISABLE", "DLFULLSKEW", "DLHOLD", 
                      "DLNOCHANGE", "DLPERIOD", "DLRECOVERY", "DLRECREM", 
                      "DLREMOVAL", "DLSETUP", "DLSETUPHOLD", "DLSKEW", "DLTIMESKEW", 
                      "DLWIDTH", "EDGE", "ELSE", "END", "ENDCASE", "ENDCONFIG", 
                      "ENDFUNCTION", "ENDGENERATE", "ENDMODULE", "ENDPRIMITIVE", 
                      "ENDSPECIFY", "ENDTABLE", "ENDTASK", "EVENT", "FOR", 
                      "FORCE", "FOREVER", "FORK", "FUNCTION", "GENERATE", 
                      "GENVAR", "HIGHZONE", "HIGHZZERO", "IF", "IFNONE", 
                      "INCLUDE", "INITIAL", "INOUT", "INPUT", "INSTANCE", 
                      "INTEGER", "JOIN", "LARGE", "LIBLIST", "LIBRARY", 
                      "LOCALPARAM", "MACROMODULE", "MEDIUM", "MIINCDIR", 
                      "MODULE", "NAND", "NEGEDGE", "NMOS", "NOR", "NOSHOWCANCELLED", 
                      "NOT", "NOTIFONE", "NOTIFZERO", "OR", "OUTPUT", "PARAMETER", 
                      "PATHPULSEDL", "PMOS", "POSEDGE", "PRIMITIVE", "PULLDOWN", 
                      "PULLONE", "PULLUP", "PULLZERO", "PULSESTYLE_ONDETECT", 
                      "PULSESTYLE_ONEVENT", "RCMOS", "REAL", "REALTIME", 
                      "REG", "RELEASE", "REPEAT", "RNMOS", "RPMOS", "RTRAN", 
                      "RTRANIFONE", "RTRANIFZERO", "SCALARED", "SHOWCANCELLED", 
                      "SIGNED", "SMALL", "SPECIFY", "SPECPARAM", "STRONGONE", 
                      "STRONGZERO", "SUPPLYONE", "SUPPLYZERO", "TABLE", 
                      "TASK", "TIME", "TRAN", "TRANIFONE", "TRANIFZERO", 
                      "TRI", "TRIAND", "TRIONE", "TRIOR", "TRIREG", "TRIZERO", 
                      "USE", "UWIRE", "VECTORED", "WAIT", "WAND", "WEAKONE", 
                      "WEAKZERO", "WHILE", "WIRE", "WOR", "XNOR", "XOR", 
                      "AM", "AMAM", "AMAMAM", "AS", "ASAS", "ASGT", "AT", 
                      "CA", "CATI", "CL", "CO", "DL", "DQ", "DT", "EM", 
                      "EMEQ", "EMEQEQ", "EQ", "EQEQ", "EQEQEQ", "EQGT", 
                      "GA", "GT", "GTEQ", "GTGT", "GTGTGT", "HA", "LB", 
                      "LC", "LP", "LT", "LTEQ", "LTLT", "LTLTLT", "MI", 
                      "MICL", "MIGT", "MO", "PL", "PLCL", "QM", "RB", "RC", 
                      "RP", "SC", "SL", "TI", "TIAM", "TICA", "TIVL", "VL", 
                      "VLVL", "BINARY_BASE", "BLOCK_COMMENT", "DECIMAL_BASE", 
                      "ESCAPED_IDENTIFIER", "EXPONENTIAL_NUMBER", "FIXED_POINT_NUMBER", 
                      "HEX_BASE", "LINE_COMMENT", "OCTAL_BASE", "SIMPLE_IDENTIFIER", 
                      "STRING", "SYSTEM_TF_IDENTIFIER", "UNSIGNED_NUMBER", 
                      "WHITE_SPACE", "BINARY_VALUE", "X_OR_Z_UNDERSCORE", 
                      "EDGE_DESCRIPTOR", "HEX_VALUE", "FILE_PATH_SPEC", 
                      "OCTAL_VALUE", "EDGE_SYMBOL", "LEVEL_ONLY_SYMBOL", 
                      "OUTPUT_OR_LEVEL_SYMBOL", "BEGIN_KEYWORDS_DIRECTIVE", 
                      "CELLDEFINE_DIRECTIVE", "DEFAULT_NETTYPE_DIRECTIVE", 
                      "DEFINE_DIRECTIVE", "ELSE_DIRECTIVE", "ELSIF_DIRECTIVE", 
                      "END_KEYWORDS_DIRECTIVE", "ENDCELLDEFINE_DIRECTIVE", 
                      "ENDIF_DIRECTIVE", "IFDEF_DIRECTIVE", "IFNDEF_DIRECTIVE", 
                      "INCLUDE_DIRECTIVE", "LINE_DIRECTIVE", "NOUNCONNECTED_DRIVE_DIRECTIVE", 
                      "PRAGMA_DIRECTIVE", "RESETALL_DIRECTIVE", "TIMESCALE_DIRECTIVE", 
                      "UNCONNECTED_DRIVE_DIRECTIVE", "UNDEF_DIRECTIVE", 
                      "MACRO_USAGE", "VERSION_SPECIFIER", "DEFAULT_NETTYPE_VALUE", 
                      "MACRO_NAME", "FILENAME", "MACRO_DELIMITER", "MACRO_ESC_NEWLINE", 
                      "MACRO_ESC_QUOTE", "MACRO_QUOTE", "MACRO_TEXT", "SOURCE_TEXT", 
                      "TIME_UNIT", "TIME_VALUE", "UNCONNECTED_DRIVE_VALUE", 
                      "MACRO_IDENTIFIER" ]

    RULE_library_text = 0
    RULE_library_description = 1
    RULE_library_declaration = 2
    RULE_library_incdir = 3
    RULE_include_statement = 4
    RULE_file_path_spec = 5
    RULE_source_text = 6
    RULE_description = 7
    RULE_module_declaration = 8
    RULE_module_keyword = 9
    RULE_module_parameter_port_list = 10
    RULE_list_of_port_declarations = 11
    RULE_port = 12
    RULE_port_implicit = 13
    RULE_port_explicit = 14
    RULE_port_expression = 15
    RULE_port_reference = 16
    RULE_port_declaration = 17
    RULE_module_item = 18
    RULE_module_or_generate_item = 19
    RULE_module_or_generate_item_declaration = 20
    RULE_parameter_override = 21
    RULE_config_declaration = 22
    RULE_design_statement = 23
    RULE_design_statement_item = 24
    RULE_config_rule_statement = 25
    RULE_default_clause = 26
    RULE_inst_clause = 27
    RULE_inst_name = 28
    RULE_cell_clause = 29
    RULE_liblist_clause = 30
    RULE_use_clause = 31
    RULE_local_parameter_declaration = 32
    RULE_parameter_declaration = 33
    RULE_specparam_declaration = 34
    RULE_parameter_type = 35
    RULE_inout_declaration = 36
    RULE_input_declaration = 37
    RULE_output_declaration = 38
    RULE_event_declaration = 39
    RULE_integer_declaration = 40
    RULE_net_declaration = 41
    RULE_real_declaration = 42
    RULE_realtime_declaration = 43
    RULE_reg_declaration = 44
    RULE_time_declaration = 45
    RULE_net_type = 46
    RULE_output_variable_type = 47
    RULE_real_type = 48
    RULE_variable_type = 49
    RULE_drive_strength = 50
    RULE_strength0 = 51
    RULE_strength1 = 52
    RULE_charge_strength = 53
    RULE_delay3 = 54
    RULE_delay2 = 55
    RULE_delay_value = 56
    RULE_list_of_defparam_assignments = 57
    RULE_list_of_event_identifiers = 58
    RULE_event_id = 59
    RULE_list_of_net_decl_assignments = 60
    RULE_list_of_net_identifiers = 61
    RULE_net_id = 62
    RULE_list_of_param_assignments = 63
    RULE_list_of_port_identifiers = 64
    RULE_list_of_real_identifiers = 65
    RULE_list_of_specparam_assignments = 66
    RULE_list_of_variable_identifiers = 67
    RULE_list_of_variable_port_identifiers = 68
    RULE_var_port_id = 69
    RULE_defparam_assignment = 70
    RULE_net_decl_assignment = 71
    RULE_param_assignment = 72
    RULE_specparam_assignment = 73
    RULE_pulse_control_specparam = 74
    RULE_error_limit_value = 75
    RULE_reject_limit_value = 76
    RULE_limit_value = 77
    RULE_dimension = 78
    RULE_range_ = 79
    RULE_function_declaration = 80
    RULE_function_item_declaration = 81
    RULE_function_port_list = 82
    RULE_func_port_item = 83
    RULE_function_range_or_type = 84
    RULE_task_declaration = 85
    RULE_task_item_declaration = 86
    RULE_task_port_list = 87
    RULE_task_port_item = 88
    RULE_tf_input_declaration = 89
    RULE_tf_output_declaration = 90
    RULE_tf_inout_declaration = 91
    RULE_task_port_type = 92
    RULE_block_item_declaration = 93
    RULE_list_of_block_variable_identifiers = 94
    RULE_list_of_block_real_identifiers = 95
    RULE_block_variable_type = 96
    RULE_block_real_type = 97
    RULE_gate_instantiation = 98
    RULE_cmos_switch_instance = 99
    RULE_enable_gate_instance = 100
    RULE_mos_switch_instance = 101
    RULE_n_input_gate_instance = 102
    RULE_n_output_gate_instance = 103
    RULE_pass_switch_instance = 104
    RULE_pass_enable_switch_instance = 105
    RULE_pull_gate_instance = 106
    RULE_name_of_gate_instance = 107
    RULE_pulldown_strength = 108
    RULE_pullup_strength = 109
    RULE_enable_terminal = 110
    RULE_inout_terminal = 111
    RULE_input_terminal = 112
    RULE_ncontrol_terminal = 113
    RULE_output_terminal = 114
    RULE_pcontrol_terminal = 115
    RULE_cmos_switchtype = 116
    RULE_enable_gatetype = 117
    RULE_mos_switchtype = 118
    RULE_n_input_gatetype = 119
    RULE_n_output_gatetype = 120
    RULE_pass_en_switchtype = 121
    RULE_pass_switchtype = 122
    RULE_module_instantiation = 123
    RULE_parameter_value_assignment = 124
    RULE_list_of_parameter_assignments = 125
    RULE_ordered_parameter_assignment = 126
    RULE_named_parameter_assignment = 127
    RULE_module_instance = 128
    RULE_name_of_module_instance = 129
    RULE_list_of_port_connections = 130
    RULE_ordered_port_connection = 131
    RULE_named_port_connection = 132
    RULE_generate_region = 133
    RULE_genvar_declaration = 134
    RULE_list_of_genvar_identifiers = 135
    RULE_loop_generate_construct = 136
    RULE_genvar_initialization = 137
    RULE_genvar_expression = 138
    RULE_genvar_iteration = 139
    RULE_conditional_generate_construct = 140
    RULE_if_generate_construct = 141
    RULE_case_generate_construct = 142
    RULE_case_generate_item = 143
    RULE_generate_block = 144
    RULE_generate_block_name = 145
    RULE_generate_block_or_null = 146
    RULE_udp_declaration = 147
    RULE_udp_port_list = 148
    RULE_udp_declaration_port_list = 149
    RULE_udp_port_declaration = 150
    RULE_udp_output_declaration = 151
    RULE_udp_input_declaration = 152
    RULE_udp_reg_declaration = 153
    RULE_udp_body = 154
    RULE_combinational_body = 155
    RULE_combinational_entry = 156
    RULE_sequential_body = 157
    RULE_udp_initial_statement = 158
    RULE_init_val = 159
    RULE_sequential_entry = 160
    RULE_seq_input_list = 161
    RULE_level_input_list = 162
    RULE_edge_input_list = 163
    RULE_edge_indicator = 164
    RULE_current_state = 165
    RULE_next_state = 166
    RULE_output_symbol = 167
    RULE_level_symbol = 168
    RULE_edge_symbol = 169
    RULE_udp_instantiation = 170
    RULE_udp_instance = 171
    RULE_name_of_udp_instance = 172
    RULE_continuous_assign = 173
    RULE_list_of_net_assignments = 174
    RULE_net_assignment = 175
    RULE_initial_construct = 176
    RULE_always_construct = 177
    RULE_blocking_assignment = 178
    RULE_nonblocking_assignment = 179
    RULE_procedural_continuous_assignments = 180
    RULE_variable_assignment = 181
    RULE_par_block = 182
    RULE_block_name = 183
    RULE_seq_block = 184
    RULE_statement = 185
    RULE_statement_or_null = 186
    RULE_function_statement = 187
    RULE_delay_control = 188
    RULE_delay_or_event_control = 189
    RULE_disable_statement = 190
    RULE_event_control = 191
    RULE_event_trigger = 192
    RULE_event_expression = 193
    RULE_procedural_timing_control = 194
    RULE_procedural_timing_control_statement = 195
    RULE_wait_statement = 196
    RULE_conditional_statement = 197
    RULE_case_statement = 198
    RULE_case_item = 199
    RULE_loop_statement = 200
    RULE_system_task_enable = 201
    RULE_sys_task_en_port_list = 202
    RULE_sys_task_en_port_item = 203
    RULE_task_enable = 204
    RULE_task_en_port_list = 205
    RULE_specify_block = 206
    RULE_specify_item = 207
    RULE_pulsestyle_declaration = 208
    RULE_showcancelled_declaration = 209
    RULE_path_declaration = 210
    RULE_simple_path_declaration = 211
    RULE_parallel_path_description = 212
    RULE_full_path_description = 213
    RULE_list_of_path_inputs = 214
    RULE_list_of_path_outputs = 215
    RULE_specify_input_terminal_descriptor = 216
    RULE_specify_output_terminal_descriptor = 217
    RULE_input_identifier = 218
    RULE_output_identifier = 219
    RULE_path_delay_value = 220
    RULE_list_of_path_delay_expressions = 221
    RULE_t_path_delay_expression = 222
    RULE_trise_path_delay_expression = 223
    RULE_tfall_path_delay_expression = 224
    RULE_tz_path_delay_expression = 225
    RULE_t01_path_delay_expression = 226
    RULE_t10_path_delay_expression = 227
    RULE_t0z_path_delay_expression = 228
    RULE_tz1_path_delay_expression = 229
    RULE_t1z_path_delay_expression = 230
    RULE_tz0_path_delay_expression = 231
    RULE_t0x_path_delay_expression = 232
    RULE_tx1_path_delay_expression = 233
    RULE_t1x_path_delay_expression = 234
    RULE_tx0_path_delay_expression = 235
    RULE_txz_path_delay_expression = 236
    RULE_tzx_path_delay_expression = 237
    RULE_path_delay_expression = 238
    RULE_edge_sensitive_path_declaration = 239
    RULE_parallel_edge_sensitive_path_description = 240
    RULE_full_edge_sensitive_path_description = 241
    RULE_data_source_expression = 242
    RULE_edge_identifier = 243
    RULE_state_dependent_path_declaration = 244
    RULE_polarity_operator = 245
    RULE_system_timing_check = 246
    RULE_setup_timing_check = 247
    RULE_notifier_opt = 248
    RULE_hold_timing_check = 249
    RULE_setuphold_timing_check = 250
    RULE_timing_check_opt = 251
    RULE_stamptime_cond_opt = 252
    RULE_checktime_cond_opt = 253
    RULE_delayed_ref_opt = 254
    RULE_delayed_data_opt = 255
    RULE_recovery_timing_check = 256
    RULE_removal_timing_check = 257
    RULE_recrem_timing_check = 258
    RULE_skew_timing_check = 259
    RULE_timeskew_timing_check = 260
    RULE_skew_timing_check_opt = 261
    RULE_event_based_flag_opt = 262
    RULE_remain_active_flag_opt = 263
    RULE_fullskew_timing_check = 264
    RULE_period_timing_check = 265
    RULE_width_timing_check = 266
    RULE_threshold_opt = 267
    RULE_nochange_timing_check = 268
    RULE_checktime_condition = 269
    RULE_controlled_reference_event = 270
    RULE_data_event = 271
    RULE_delayed_data = 272
    RULE_delayed_reference = 273
    RULE_end_edge_offset = 274
    RULE_event_based_flag = 275
    RULE_notifier = 276
    RULE_reference_event = 277
    RULE_remain_active_flag = 278
    RULE_stamptime_condition = 279
    RULE_start_edge_offset = 280
    RULE_threshold = 281
    RULE_timing_check_limit = 282
    RULE_timing_check_event = 283
    RULE_controlled_timing_check_event = 284
    RULE_timing_check_event_control = 285
    RULE_specify_terminal_descriptor = 286
    RULE_edge_control_specifier = 287
    RULE_edge_descriptor = 288
    RULE_timing_check_condition = 289
    RULE_scalar_timing_check_condition = 290
    RULE_scalar_constant = 291
    RULE_concatenation = 292
    RULE_constant_concatenation = 293
    RULE_constant_multiple_concatenation = 294
    RULE_module_path_concatenation = 295
    RULE_module_path_multiple_concatenation = 296
    RULE_multiple_concatenation = 297
    RULE_constant_function_call = 298
    RULE_constant_system_function_call = 299
    RULE_function_call = 300
    RULE_system_function_call = 301
    RULE_sys_func_call_port_list = 302
    RULE_base_expression = 303
    RULE_constant_base_expression = 304
    RULE_constant_expression = 305
    RULE_constant_mintypmax_expression = 306
    RULE_constant_range_expression = 307
    RULE_dimension_constant_expression = 308
    RULE_expression = 309
    RULE_lsb_constant_expression = 310
    RULE_mintypmax_expression = 311
    RULE_module_path_expression = 312
    RULE_module_path_mintypmax_expression = 313
    RULE_msb_constant_expression = 314
    RULE_range_expression = 315
    RULE_width_constant_expression = 316
    RULE_constant_primary = 317
    RULE_module_path_primary = 318
    RULE_primary = 319
    RULE_select_ = 320
    RULE_bit_select = 321
    RULE_net_lvalue = 322
    RULE_const_select = 323
    RULE_const_bit_select = 324
    RULE_variable_lvalue = 325
    RULE_unary_operator = 326
    RULE_unary_module_path_operator = 327
    RULE_number = 328
    RULE_real_number = 329
    RULE_decimal_number = 330
    RULE_binary_number = 331
    RULE_octal_number = 332
    RULE_hex_number = 333
    RULE_size = 334
    RULE_fixed_point_number = 335
    RULE_exponential_number = 336
    RULE_unsigned_number = 337
    RULE_decimal_value = 338
    RULE_binary_value = 339
    RULE_octal_value = 340
    RULE_hex_value = 341
    RULE_decimal_base = 342
    RULE_binary_base = 343
    RULE_octal_base = 344
    RULE_hex_base = 345
    RULE_string_ = 346
    RULE_attribute_instance = 347
    RULE_attr_spec = 348
    RULE_attr_name = 349
    RULE_block_identifier = 350
    RULE_cell_identifier = 351
    RULE_config_identifier = 352
    RULE_escaped_identifier = 353
    RULE_event_identifier = 354
    RULE_function_identifier = 355
    RULE_gate_instance_identifier = 356
    RULE_generate_block_identifier = 357
    RULE_genvar_identifier = 358
    RULE_hierarchical_identifier = 359
    RULE_hier_ref = 360
    RULE_identifier = 361
    RULE_input_port_identifier = 362
    RULE_instance_identifier = 363
    RULE_library_identifier = 364
    RULE_module_identifier = 365
    RULE_module_instance_identifier = 366
    RULE_net_identifier = 367
    RULE_output_port_identifier = 368
    RULE_parameter_identifier = 369
    RULE_port_identifier = 370
    RULE_real_identifier = 371
    RULE_simple_identifier = 372
    RULE_specparam_identifier = 373
    RULE_system_function_identifier = 374
    RULE_system_task_identifier = 375
    RULE_task_identifier = 376
    RULE_terminal_identifier = 377
    RULE_topmodule_identifier = 378
    RULE_udp_identifier = 379
    RULE_udp_instance_identifier = 380
    RULE_variable_identifier = 381

    ruleNames =  [ "library_text", "library_description", "library_declaration", 
                   "library_incdir", "include_statement", "file_path_spec", 
                   "source_text", "description", "module_declaration", "module_keyword", 
                   "module_parameter_port_list", "list_of_port_declarations", 
                   "port", "port_implicit", "port_explicit", "port_expression", 
                   "port_reference", "port_declaration", "module_item", 
                   "module_or_generate_item", "module_or_generate_item_declaration", 
                   "parameter_override", "config_declaration", "design_statement", 
                   "design_statement_item", "config_rule_statement", "default_clause", 
                   "inst_clause", "inst_name", "cell_clause", "liblist_clause", 
                   "use_clause", "local_parameter_declaration", "parameter_declaration", 
                   "specparam_declaration", "parameter_type", "inout_declaration", 
                   "input_declaration", "output_declaration", "event_declaration", 
                   "integer_declaration", "net_declaration", "real_declaration", 
                   "realtime_declaration", "reg_declaration", "time_declaration", 
                   "net_type", "output_variable_type", "real_type", "variable_type", 
                   "drive_strength", "strength0", "strength1", "charge_strength", 
                   "delay3", "delay2", "delay_value", "list_of_defparam_assignments", 
                   "list_of_event_identifiers", "event_id", "list_of_net_decl_assignments", 
                   "list_of_net_identifiers", "net_id", "list_of_param_assignments", 
                   "list_of_port_identifiers", "list_of_real_identifiers", 
                   "list_of_specparam_assignments", "list_of_variable_identifiers", 
                   "list_of_variable_port_identifiers", "var_port_id", "defparam_assignment", 
                   "net_decl_assignment", "param_assignment", "specparam_assignment", 
                   "pulse_control_specparam", "error_limit_value", "reject_limit_value", 
                   "limit_value", "dimension", "range_", "function_declaration", 
                   "function_item_declaration", "function_port_list", "func_port_item", 
                   "function_range_or_type", "task_declaration", "task_item_declaration", 
                   "task_port_list", "task_port_item", "tf_input_declaration", 
                   "tf_output_declaration", "tf_inout_declaration", "task_port_type", 
                   "block_item_declaration", "list_of_block_variable_identifiers", 
                   "list_of_block_real_identifiers", "block_variable_type", 
                   "block_real_type", "gate_instantiation", "cmos_switch_instance", 
                   "enable_gate_instance", "mos_switch_instance", "n_input_gate_instance", 
                   "n_output_gate_instance", "pass_switch_instance", "pass_enable_switch_instance", 
                   "pull_gate_instance", "name_of_gate_instance", "pulldown_strength", 
                   "pullup_strength", "enable_terminal", "inout_terminal", 
                   "input_terminal", "ncontrol_terminal", "output_terminal", 
                   "pcontrol_terminal", "cmos_switchtype", "enable_gatetype", 
                   "mos_switchtype", "n_input_gatetype", "n_output_gatetype", 
                   "pass_en_switchtype", "pass_switchtype", "module_instantiation", 
                   "parameter_value_assignment", "list_of_parameter_assignments", 
                   "ordered_parameter_assignment", "named_parameter_assignment", 
                   "module_instance", "name_of_module_instance", "list_of_port_connections", 
                   "ordered_port_connection", "named_port_connection", "generate_region", 
                   "genvar_declaration", "list_of_genvar_identifiers", "loop_generate_construct", 
                   "genvar_initialization", "genvar_expression", "genvar_iteration", 
                   "conditional_generate_construct", "if_generate_construct", 
                   "case_generate_construct", "case_generate_item", "generate_block", 
                   "generate_block_name", "generate_block_or_null", "udp_declaration", 
                   "udp_port_list", "udp_declaration_port_list", "udp_port_declaration", 
                   "udp_output_declaration", "udp_input_declaration", "udp_reg_declaration", 
                   "udp_body", "combinational_body", "combinational_entry", 
                   "sequential_body", "udp_initial_statement", "init_val", 
                   "sequential_entry", "seq_input_list", "level_input_list", 
                   "edge_input_list", "edge_indicator", "current_state", 
                   "next_state", "output_symbol", "level_symbol", "edge_symbol", 
                   "udp_instantiation", "udp_instance", "name_of_udp_instance", 
                   "continuous_assign", "list_of_net_assignments", "net_assignment", 
                   "initial_construct", "always_construct", "blocking_assignment", 
                   "nonblocking_assignment", "procedural_continuous_assignments", 
                   "variable_assignment", "par_block", "block_name", "seq_block", 
                   "statement", "statement_or_null", "function_statement", 
                   "delay_control", "delay_or_event_control", "disable_statement", 
                   "event_control", "event_trigger", "event_expression", 
                   "procedural_timing_control", "procedural_timing_control_statement", 
                   "wait_statement", "conditional_statement", "case_statement", 
                   "case_item", "loop_statement", "system_task_enable", 
                   "sys_task_en_port_list", "sys_task_en_port_item", "task_enable", 
                   "task_en_port_list", "specify_block", "specify_item", 
                   "pulsestyle_declaration", "showcancelled_declaration", 
                   "path_declaration", "simple_path_declaration", "parallel_path_description", 
                   "full_path_description", "list_of_path_inputs", "list_of_path_outputs", 
                   "specify_input_terminal_descriptor", "specify_output_terminal_descriptor", 
                   "input_identifier", "output_identifier", "path_delay_value", 
                   "list_of_path_delay_expressions", "t_path_delay_expression", 
                   "trise_path_delay_expression", "tfall_path_delay_expression", 
                   "tz_path_delay_expression", "t01_path_delay_expression", 
                   "t10_path_delay_expression", "t0z_path_delay_expression", 
                   "tz1_path_delay_expression", "t1z_path_delay_expression", 
                   "tz0_path_delay_expression", "t0x_path_delay_expression", 
                   "tx1_path_delay_expression", "t1x_path_delay_expression", 
                   "tx0_path_delay_expression", "txz_path_delay_expression", 
                   "tzx_path_delay_expression", "path_delay_expression", 
                   "edge_sensitive_path_declaration", "parallel_edge_sensitive_path_description", 
                   "full_edge_sensitive_path_description", "data_source_expression", 
                   "edge_identifier", "state_dependent_path_declaration", 
                   "polarity_operator", "system_timing_check", "setup_timing_check", 
                   "notifier_opt", "hold_timing_check", "setuphold_timing_check", 
                   "timing_check_opt", "stamptime_cond_opt", "checktime_cond_opt", 
                   "delayed_ref_opt", "delayed_data_opt", "recovery_timing_check", 
                   "removal_timing_check", "recrem_timing_check", "skew_timing_check", 
                   "timeskew_timing_check", "skew_timing_check_opt", "event_based_flag_opt", 
                   "remain_active_flag_opt", "fullskew_timing_check", "period_timing_check", 
                   "width_timing_check", "threshold_opt", "nochange_timing_check", 
                   "checktime_condition", "controlled_reference_event", 
                   "data_event", "delayed_data", "delayed_reference", "end_edge_offset", 
                   "event_based_flag", "notifier", "reference_event", "remain_active_flag", 
                   "stamptime_condition", "start_edge_offset", "threshold", 
                   "timing_check_limit", "timing_check_event", "controlled_timing_check_event", 
                   "timing_check_event_control", "specify_terminal_descriptor", 
                   "edge_control_specifier", "edge_descriptor", "timing_check_condition", 
                   "scalar_timing_check_condition", "scalar_constant", "concatenation", 
                   "constant_concatenation", "constant_multiple_concatenation", 
                   "module_path_concatenation", "module_path_multiple_concatenation", 
                   "multiple_concatenation", "constant_function_call", "constant_system_function_call", 
                   "function_call", "system_function_call", "sys_func_call_port_list", 
                   "base_expression", "constant_base_expression", "constant_expression", 
                   "constant_mintypmax_expression", "constant_range_expression", 
                   "dimension_constant_expression", "expression", "lsb_constant_expression", 
                   "mintypmax_expression", "module_path_expression", "module_path_mintypmax_expression", 
                   "msb_constant_expression", "range_expression", "width_constant_expression", 
                   "constant_primary", "module_path_primary", "primary", 
                   "select_", "bit_select", "net_lvalue", "const_select", 
                   "const_bit_select", "variable_lvalue", "unary_operator", 
                   "unary_module_path_operator", "number", "real_number", 
                   "decimal_number", "binary_number", "octal_number", "hex_number", 
                   "size", "fixed_point_number", "exponential_number", "unsigned_number", 
                   "decimal_value", "binary_value", "octal_value", "hex_value", 
                   "decimal_base", "binary_base", "octal_base", "hex_base", 
                   "string_", "attribute_instance", "attr_spec", "attr_name", 
                   "block_identifier", "cell_identifier", "config_identifier", 
                   "escaped_identifier", "event_identifier", "function_identifier", 
                   "gate_instance_identifier", "generate_block_identifier", 
                   "genvar_identifier", "hierarchical_identifier", "hier_ref", 
                   "identifier", "input_port_identifier", "instance_identifier", 
                   "library_identifier", "module_identifier", "module_instance_identifier", 
                   "net_identifier", "output_port_identifier", "parameter_identifier", 
                   "port_identifier", "real_identifier", "simple_identifier", 
                   "specparam_identifier", "system_function_identifier", 
                   "system_task_identifier", "task_identifier", "terminal_identifier", 
                   "topmodule_identifier", "udp_identifier", "udp_instance_identifier", 
                   "variable_identifier" ]

    EOF = Token.EOF
    ALWAYS=1
    AND=2
    ASSIGN=3
    AUTOMATIC=4
    BEGIN=5
    BUF=6
    BUFIFONE=7
    BUFIFZERO=8
    CASE=9
    CASEX=10
    CASEZ=11
    CELL=12
    CMOS=13
    CONFIG=14
    DEASSIGN=15
    DEFAULT=16
    DEFPARAM=17
    DESIGN=18
    DISABLE=19
    DLFULLSKEW=20
    DLHOLD=21
    DLNOCHANGE=22
    DLPERIOD=23
    DLRECOVERY=24
    DLRECREM=25
    DLREMOVAL=26
    DLSETUP=27
    DLSETUPHOLD=28
    DLSKEW=29
    DLTIMESKEW=30
    DLWIDTH=31
    EDGE=32
    ELSE=33
    END=34
    ENDCASE=35
    ENDCONFIG=36
    ENDFUNCTION=37
    ENDGENERATE=38
    ENDMODULE=39
    ENDPRIMITIVE=40
    ENDSPECIFY=41
    ENDTABLE=42
    ENDTASK=43
    EVENT=44
    FOR=45
    FORCE=46
    FOREVER=47
    FORK=48
    FUNCTION=49
    GENERATE=50
    GENVAR=51
    HIGHZONE=52
    HIGHZZERO=53
    IF=54
    IFNONE=55
    INCLUDE=56
    INITIAL=57
    INOUT=58
    INPUT=59
    INSTANCE=60
    INTEGER=61
    JOIN=62
    LARGE=63
    LIBLIST=64
    LIBRARY=65
    LOCALPARAM=66
    MACROMODULE=67
    MEDIUM=68
    MIINCDIR=69
    MODULE=70
    NAND=71
    NEGEDGE=72
    NMOS=73
    NOR=74
    NOSHOWCANCELLED=75
    NOT=76
    NOTIFONE=77
    NOTIFZERO=78
    OR=79
    OUTPUT=80
    PARAMETER=81
    PATHPULSEDL=82
    PMOS=83
    POSEDGE=84
    PRIMITIVE=85
    PULLDOWN=86
    PULLONE=87
    PULLUP=88
    PULLZERO=89
    PULSESTYLE_ONDETECT=90
    PULSESTYLE_ONEVENT=91
    RCMOS=92
    REAL=93
    REALTIME=94
    REG=95
    RELEASE=96
    REPEAT=97
    RNMOS=98
    RPMOS=99
    RTRAN=100
    RTRANIFONE=101
    RTRANIFZERO=102
    SCALARED=103
    SHOWCANCELLED=104
    SIGNED=105
    SMALL=106
    SPECIFY=107
    SPECPARAM=108
    STRONGONE=109
    STRONGZERO=110
    SUPPLYONE=111
    SUPPLYZERO=112
    TABLE=113
    TASK=114
    TIME=115
    TRAN=116
    TRANIFONE=117
    TRANIFZERO=118
    TRI=119
    TRIAND=120
    TRIONE=121
    TRIOR=122
    TRIREG=123
    TRIZERO=124
    USE=125
    UWIRE=126
    VECTORED=127
    WAIT=128
    WAND=129
    WEAKONE=130
    WEAKZERO=131
    WHILE=132
    WIRE=133
    WOR=134
    XNOR=135
    XOR=136
    AM=137
    AMAM=138
    AMAMAM=139
    AS=140
    ASAS=141
    ASGT=142
    AT=143
    CA=144
    CATI=145
    CL=146
    CO=147
    DL=148
    DQ=149
    DT=150
    EM=151
    EMEQ=152
    EMEQEQ=153
    EQ=154
    EQEQ=155
    EQEQEQ=156
    EQGT=157
    GA=158
    GT=159
    GTEQ=160
    GTGT=161
    GTGTGT=162
    HA=163
    LB=164
    LC=165
    LP=166
    LT=167
    LTEQ=168
    LTLT=169
    LTLTLT=170
    MI=171
    MICL=172
    MIGT=173
    MO=174
    PL=175
    PLCL=176
    QM=177
    RB=178
    RC=179
    RP=180
    SC=181
    SL=182
    TI=183
    TIAM=184
    TICA=185
    TIVL=186
    VL=187
    VLVL=188
    BINARY_BASE=189
    BLOCK_COMMENT=190
    DECIMAL_BASE=191
    ESCAPED_IDENTIFIER=192
    EXPONENTIAL_NUMBER=193
    FIXED_POINT_NUMBER=194
    HEX_BASE=195
    LINE_COMMENT=196
    OCTAL_BASE=197
    SIMPLE_IDENTIFIER=198
    STRING=199
    SYSTEM_TF_IDENTIFIER=200
    UNSIGNED_NUMBER=201
    WHITE_SPACE=202
    BINARY_VALUE=203
    X_OR_Z_UNDERSCORE=204
    EDGE_DESCRIPTOR=205
    HEX_VALUE=206
    FILE_PATH_SPEC=207
    OCTAL_VALUE=208
    EDGE_SYMBOL=209
    LEVEL_ONLY_SYMBOL=210
    OUTPUT_OR_LEVEL_SYMBOL=211
    BEGIN_KEYWORDS_DIRECTIVE=212
    CELLDEFINE_DIRECTIVE=213
    DEFAULT_NETTYPE_DIRECTIVE=214
    DEFINE_DIRECTIVE=215
    ELSE_DIRECTIVE=216
    ELSIF_DIRECTIVE=217
    END_KEYWORDS_DIRECTIVE=218
    ENDCELLDEFINE_DIRECTIVE=219
    ENDIF_DIRECTIVE=220
    IFDEF_DIRECTIVE=221
    IFNDEF_DIRECTIVE=222
    INCLUDE_DIRECTIVE=223
    LINE_DIRECTIVE=224
    NOUNCONNECTED_DRIVE_DIRECTIVE=225
    PRAGMA_DIRECTIVE=226
    RESETALL_DIRECTIVE=227
    TIMESCALE_DIRECTIVE=228
    UNCONNECTED_DRIVE_DIRECTIVE=229
    UNDEF_DIRECTIVE=230
    MACRO_USAGE=231
    VERSION_SPECIFIER=232
    DEFAULT_NETTYPE_VALUE=233
    MACRO_NAME=234
    FILENAME=235
    MACRO_DELIMITER=236
    MACRO_ESC_NEWLINE=237
    MACRO_ESC_QUOTE=238
    MACRO_QUOTE=239
    MACRO_TEXT=240
    SOURCE_TEXT=241
    TIME_UNIT=242
    TIME_VALUE=243
    UNCONNECTED_DRIVE_VALUE=244
    MACRO_IDENTIFIER=245

    def __init__(self, input:TokenStream, output:TextIO = sys.stdout):
        super().__init__(input, output)
        self.checkVersion("4.7.2")
        self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache)
        self._predicates = None



    class Library_textContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EOF(self):
            return self.getToken(VerilogParser.EOF, 0)

        def library_description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Library_descriptionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Library_descriptionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_library_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_text" ):
                listener.enterLibrary_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_text" ):
                listener.exitLibrary_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_text" ):
                return visitor.visitLibrary_text(self)
            else:
                return visitor.visitChildren(self)




    def library_text(self):

        localctx = VerilogParser.Library_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 0, self.RULE_library_text)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 767
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 14)) & ~0x3f) == 0 and ((1 << (_la - 14)) & ((1 << (VerilogParser.CONFIG - 14)) | (1 << (VerilogParser.INCLUDE - 14)) | (1 << (VerilogParser.LIBRARY - 14)))) != 0):
                self.state = 764
                self.library_description()
                self.state = 769
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 770
            self.match(VerilogParser.EOF)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Library_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def library_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Library_declarationContext,0)


        def include_statement(self):
            return self.getTypedRuleContext(VerilogParser.Include_statementContext,0)


        def config_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Config_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_library_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_description" ):
                listener.enterLibrary_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_description" ):
                listener.exitLibrary_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_description" ):
                return visitor.visitLibrary_description(self)
            else:
                return visitor.visitChildren(self)




    def library_description(self):

        localctx = VerilogParser.Library_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 2, self.RULE_library_description)
        try:
            self.state = 775
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.LIBRARY]:
                self.enterOuterAlt(localctx, 1)
                self.state = 772
                self.library_declaration()
                pass
            elif token in [VerilogParser.INCLUDE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 773
                self.include_statement()
                pass
            elif token in [VerilogParser.CONFIG]:
                self.enterOuterAlt(localctx, 3)
                self.state = 774
                self.config_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Library_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LIBRARY(self):
            return self.getToken(VerilogParser.LIBRARY, 0)

        def library_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Library_identifierContext,0)


        def file_path_spec(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.File_path_specContext)
            else:
                return self.getTypedRuleContext(VerilogParser.File_path_specContext,i)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def library_incdir(self):
            return self.getTypedRuleContext(VerilogParser.Library_incdirContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_library_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_declaration" ):
                listener.enterLibrary_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_declaration" ):
                listener.exitLibrary_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_declaration" ):
                return visitor.visitLibrary_declaration(self)
            else:
                return visitor.visitChildren(self)




    def library_declaration(self):

        localctx = VerilogParser.Library_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 4, self.RULE_library_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 777
            self.match(VerilogParser.LIBRARY)
            self.state = 778
            self.library_identifier()
            self.state = 779
            self.file_path_spec()
            self.state = 784
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 780
                self.match(VerilogParser.CO)
                self.state = 781
                self.file_path_spec()
                self.state = 786
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 788
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.MIINCDIR:
                self.state = 787
                self.library_incdir()


            self.state = 790
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Library_incdirContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MIINCDIR(self):
            return self.getToken(VerilogParser.MIINCDIR, 0)

        def file_path_spec(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.File_path_specContext)
            else:
                return self.getTypedRuleContext(VerilogParser.File_path_specContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_library_incdir

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_incdir" ):
                listener.enterLibrary_incdir(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_incdir" ):
                listener.exitLibrary_incdir(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_incdir" ):
                return visitor.visitLibrary_incdir(self)
            else:
                return visitor.visitChildren(self)




    def library_incdir(self):

        localctx = VerilogParser.Library_incdirContext(self, self._ctx, self.state)
        self.enterRule(localctx, 6, self.RULE_library_incdir)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 792
            self.match(VerilogParser.MIINCDIR)
            self.state = 793
            self.file_path_spec()
            self.state = 798
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 794
                self.match(VerilogParser.CO)
                self.state = 795
                self.file_path_spec()
                self.state = 800
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Include_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INCLUDE(self):
            return self.getToken(VerilogParser.INCLUDE, 0)

        def file_path_spec(self):
            return self.getTypedRuleContext(VerilogParser.File_path_specContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_include_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInclude_statement" ):
                listener.enterInclude_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInclude_statement" ):
                listener.exitInclude_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInclude_statement" ):
                return visitor.visitInclude_statement(self)
            else:
                return visitor.visitChildren(self)




    def include_statement(self):

        localctx = VerilogParser.Include_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 8, self.RULE_include_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 801
            self.match(VerilogParser.INCLUDE)
            self.state = 802
            self.file_path_spec()
            self.state = 803
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class File_path_specContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FILE_PATH_SPEC(self):
            return self.getToken(VerilogParser.FILE_PATH_SPEC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_file_path_spec

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_path_spec" ):
                listener.enterFile_path_spec(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_path_spec" ):
                listener.exitFile_path_spec(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_path_spec" ):
                return visitor.visitFile_path_spec(self)
            else:
                return visitor.visitChildren(self)




    def file_path_spec(self):

        localctx = VerilogParser.File_path_specContext(self, self._ctx, self.state)
        self.enterRule(localctx, 10, self.RULE_file_path_spec)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 805
            self.match(VerilogParser.FILE_PATH_SPEC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Source_textContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EOF(self):
            return self.getToken(VerilogParser.EOF, 0)

        def description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DescriptionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DescriptionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_source_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSource_text" ):
                listener.enterSource_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSource_text" ):
                listener.exitSource_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSource_text" ):
                return visitor.visitSource_text(self)
            else:
                return visitor.visitChildren(self)




    def source_text(self):

        localctx = VerilogParser.Source_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 12, self.RULE_source_text)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 810
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CONFIG or ((((_la - 67)) & ~0x3f) == 0 and ((1 << (_la - 67)) & ((1 << (VerilogParser.MACROMODULE - 67)) | (1 << (VerilogParser.MODULE - 67)) | (1 << (VerilogParser.PRIMITIVE - 67)))) != 0) or _la==VerilogParser.LP:
                self.state = 807
                self.description()
                self.state = 812
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 813
            self.match(VerilogParser.EOF)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class DescriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Module_declarationContext,0)


        def udp_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Udp_declarationContext,0)


        def config_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Config_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDescription" ):
                listener.enterDescription(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDescription" ):
                listener.exitDescription(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDescription" ):
                return visitor.visitDescription(self)
            else:
                return visitor.visitChildren(self)




    def description(self):

        localctx = VerilogParser.DescriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 14, self.RULE_description)
        try:
            self.state = 818
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,6,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 815
                self.module_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 816
                self.udp_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 817
                self.config_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_keyword(self):
            return self.getTypedRuleContext(VerilogParser.Module_keywordContext,0)


        def module_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Module_identifierContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def ENDMODULE(self):
            return self.getToken(VerilogParser.ENDMODULE, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def module_parameter_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Module_parameter_port_listContext,0)


        def list_of_port_declarations(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_declarationsContext,0)


        def module_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_itemContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_declaration" ):
                listener.enterModule_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_declaration" ):
                listener.exitModule_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_declaration" ):
                return visitor.visitModule_declaration(self)
            else:
                return visitor.visitChildren(self)




    def module_declaration(self):

        localctx = VerilogParser.Module_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 16, self.RULE_module_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 823
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LP:
                self.state = 820
                self.attribute_instance()
                self.state = 825
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 826
            self.module_keyword()
            self.state = 827
            self.module_identifier()
            self.state = 829
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.HA:
                self.state = 828
                self.module_parameter_port_list()


            self.state = 832
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LP:
                self.state = 831
                self.list_of_port_declarations()


            self.state = 834
            self.match(VerilogParser.SC)
            self.state = 838
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ALWAYS) | (1 << VerilogParser.AND) | (1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BUF) | (1 << VerilogParser.BUFIFONE) | (1 << VerilogParser.BUFIFZERO) | (1 << VerilogParser.CASE) | (1 << VerilogParser.CMOS) | (1 << VerilogParser.DEFPARAM) | (1 << VerilogParser.EVENT) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FUNCTION) | (1 << VerilogParser.GENERATE) | (1 << VerilogParser.GENVAR) | (1 << VerilogParser.IF) | (1 << VerilogParser.INITIAL) | (1 << VerilogParser.INOUT) | (1 << VerilogParser.INPUT) | (1 << VerilogParser.INTEGER))) != 0) or ((((_la - 66)) & ~0x3f) == 0 and ((1 << (_la - 66)) & ((1 << (VerilogParser.LOCALPARAM - 66)) | (1 << (VerilogParser.NAND - 66)) | (1 << (VerilogParser.NMOS - 66)) | (1 << (VerilogParser.NOR - 66)) | (1 << (VerilogParser.NOT - 66)) | (1 << (VerilogParser.NOTIFONE - 66)) | (1 << (VerilogParser.NOTIFZERO - 66)) | (1 << (VerilogParser.OR - 66)) | (1 << (VerilogParser.OUTPUT - 66)) | (1 << (VerilogParser.PARAMETER - 66)) | (1 << (VerilogParser.PMOS - 66)) | (1 << (VerilogParser.PULLDOWN - 66)) | (1 << (VerilogParser.PULLUP - 66)) | (1 << (VerilogParser.RCMOS - 66)) | (1 << (VerilogParser.REAL - 66)) | (1 << (VerilogParser.REALTIME - 66)) | (1 << (VerilogParser.REG - 66)) | (1 << (VerilogParser.RNMOS - 66)) | (1 << (VerilogParser.RPMOS - 66)) | (1 << (VerilogParser.RTRAN - 66)) | (1 << (VerilogParser.RTRANIFONE - 66)) | (1 << (VerilogParser.RTRANIFZERO - 66)) | (1 << (VerilogParser.SPECIFY - 66)) | (1 << (VerilogParser.SPECPARAM - 66)) | (1 << (VerilogParser.SUPPLYONE - 66)) | (1 << (VerilogParser.SUPPLYZERO - 66)) | (1 << (VerilogParser.TASK - 66)) | (1 << (VerilogParser.TIME - 66)) | (1 << (VerilogParser.TRAN - 66)) | (1 << (VerilogParser.TRANIFONE - 66)) | (1 << (VerilogParser.TRANIFZERO - 66)) | (1 << (VerilogParser.TRI - 66)) | (1 << (VerilogParser.TRIAND - 66)) | (1 << (VerilogParser.TRIONE - 66)) | (1 << (VerilogParser.TRIOR - 66)) | (1 << (VerilogParser.TRIREG - 66)) | (1 << (VerilogParser.TRIZERO - 66)) | (1 << (VerilogParser.UWIRE - 66)) | (1 << (VerilogParser.WAND - 66)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (VerilogParser.WIRE - 133)) | (1 << (VerilogParser.WOR - 133)) | (1 << (VerilogParser.XNOR - 133)) | (1 << (VerilogParser.XOR - 133)) | (1 << (VerilogParser.LP - 133)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 133)))) != 0) or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 835
                self.module_item()
                self.state = 840
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 841
            self.match(VerilogParser.ENDMODULE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_keywordContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MODULE(self):
            return self.getToken(VerilogParser.MODULE, 0)

        def MACROMODULE(self):
            return self.getToken(VerilogParser.MACROMODULE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_keyword" ):
                listener.enterModule_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_keyword" ):
                listener.exitModule_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_keyword" ):
                return visitor.visitModule_keyword(self)
            else:
                return visitor.visitChildren(self)




    def module_keyword(self):

        localctx = VerilogParser.Module_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 18, self.RULE_module_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 843
            _la = self._input.LA(1)
            if not(_la==VerilogParser.MACROMODULE or _la==VerilogParser.MODULE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_parameter_port_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HA(self):
            return self.getToken(VerilogParser.HA, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def parameter_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Parameter_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Parameter_declarationContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_parameter_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_parameter_port_list" ):
                listener.enterModule_parameter_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_parameter_port_list" ):
                listener.exitModule_parameter_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_parameter_port_list" ):
                return visitor.visitModule_parameter_port_list(self)
            else:
                return visitor.visitChildren(self)




    def module_parameter_port_list(self):

        localctx = VerilogParser.Module_parameter_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 20, self.RULE_module_parameter_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 845
            self.match(VerilogParser.HA)
            self.state = 846
            self.match(VerilogParser.LP)
            self.state = 847
            self.parameter_declaration()
            self.state = 852
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 848
                self.match(VerilogParser.CO)
                self.state = 849
                self.parameter_declaration()
                self.state = 854
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 855
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_port_declarationsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def port_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Port_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Port_declarationContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def port(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.PortContext)
            else:
                return self.getTypedRuleContext(VerilogParser.PortContext,i)


        def port_implicit(self):
            return self.getTypedRuleContext(VerilogParser.Port_implicitContext,0)


        def port_explicit(self):
            return self.getTypedRuleContext(VerilogParser.Port_explicitContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_port_declarations

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_declarations" ):
                listener.enterList_of_port_declarations(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_declarations" ):
                listener.exitList_of_port_declarations(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_declarations" ):
                return visitor.visitList_of_port_declarations(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_declarations(self):

        localctx = VerilogParser.List_of_port_declarationsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 22, self.RULE_list_of_port_declarations)
        self._la = 0 # Token type
        try:
            self.state = 888
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,14,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 857
                self.match(VerilogParser.LP)
                self.state = 858
                self.port_declaration()
                self.state = 863
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 859
                    self.match(VerilogParser.CO)
                    self.state = 860
                    self.port_declaration()
                    self.state = 865
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 866
                self.match(VerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 868
                self.match(VerilogParser.LP)
                self.state = 869
                self.port()
                self.state = 872 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while True:
                    self.state = 870
                    self.match(VerilogParser.CO)
                    self.state = 871
                    self.port()
                    self.state = 874 
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if not (_la==VerilogParser.CO):
                        break

                self.state = 876
                self.match(VerilogParser.RP)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 878
                self.match(VerilogParser.LP)
                self.state = 879
                self.port_implicit()
                self.state = 880
                self.match(VerilogParser.RP)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 882
                self.match(VerilogParser.LP)
                self.state = 883
                self.port_explicit()
                self.state = 884
                self.match(VerilogParser.RP)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 886
                self.match(VerilogParser.LP)
                self.state = 887
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class PortContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_implicit(self):
            return self.getTypedRuleContext(VerilogParser.Port_implicitContext,0)


        def port_explicit(self):
            return self.getTypedRuleContext(VerilogParser.Port_explicitContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_port

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort" ):
                listener.enterPort(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort" ):
                listener.exitPort(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort" ):
                return visitor.visitPort(self)
            else:
                return visitor.visitChildren(self)




    def port(self):

        localctx = VerilogParser.PortContext(self, self._ctx, self.state)
        self.enterRule(localctx, 24, self.RULE_port)
        self._la = 0 # Token type
        try:
            self.state = 894
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.CO, VerilogParser.LC, VerilogParser.RP, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 891
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 165)) & ~0x3f) == 0 and ((1 << (_la - 165)) & ((1 << (VerilogParser.LC - 165)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 165)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 165)))) != 0):
                    self.state = 890
                    self.port_implicit()


                pass
            elif token in [VerilogParser.DT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 893
                self.port_explicit()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Port_implicitContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_expression(self):
            return self.getTypedRuleContext(VerilogParser.Port_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_port_implicit

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_implicit" ):
                listener.enterPort_implicit(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_implicit" ):
                listener.exitPort_implicit(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_implicit" ):
                return visitor.visitPort_implicit(self)
            else:
                return visitor.visitChildren(self)




    def port_implicit(self):

        localctx = VerilogParser.Port_implicitContext(self, self._ctx, self.state)
        self.enterRule(localctx, 26, self.RULE_port_implicit)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 896
            self.port_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Port_explicitContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DT(self):
            return self.getToken(VerilogParser.DT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def port_expression(self):
            return self.getTypedRuleContext(VerilogParser.Port_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_port_explicit

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_explicit" ):
                listener.enterPort_explicit(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_explicit" ):
                listener.exitPort_explicit(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_explicit" ):
                return visitor.visitPort_explicit(self)
            else:
                return visitor.visitChildren(self)




    def port_explicit(self):

        localctx = VerilogParser.Port_explicitContext(self, self._ctx, self.state)
        self.enterRule(localctx, 28, self.RULE_port_explicit)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 898
            self.match(VerilogParser.DT)
            self.state = 899
            self.port_identifier()
            self.state = 900
            self.match(VerilogParser.LP)
            self.state = 902
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 165)) & ~0x3f) == 0 and ((1 << (_la - 165)) & ((1 << (VerilogParser.LC - 165)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 165)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 165)))) != 0):
                self.state = 901
                self.port_expression()


            self.state = 904
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Port_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_reference(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Port_referenceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Port_referenceContext,i)


        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_port_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_expression" ):
                listener.enterPort_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_expression" ):
                listener.exitPort_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_expression" ):
                return visitor.visitPort_expression(self)
            else:
                return visitor.visitChildren(self)




    def port_expression(self):

        localctx = VerilogParser.Port_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 30, self.RULE_port_expression)
        self._la = 0 # Token type
        try:
            self.state = 918
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 906
                self.port_reference()
                pass
            elif token in [VerilogParser.LC]:
                self.enterOuterAlt(localctx, 2)
                self.state = 907
                self.match(VerilogParser.LC)
                self.state = 908
                self.port_reference()
                self.state = 913
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 909
                    self.match(VerilogParser.CO)
                    self.state = 910
                    self.port_reference()
                    self.state = 915
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 916
                self.match(VerilogParser.RC)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Port_referenceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_port_reference

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_reference" ):
                listener.enterPort_reference(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_reference" ):
                listener.exitPort_reference(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_reference" ):
                return visitor.visitPort_reference(self)
            else:
                return visitor.visitChildren(self)




    def port_reference(self):

        localctx = VerilogParser.Port_referenceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 32, self.RULE_port_reference)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 920
            self.port_identifier()
            self.state = 925
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 921
                self.match(VerilogParser.LB)
                self.state = 922
                self.constant_range_expression()
                self.state = 923
                self.match(VerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Port_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def inout_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Inout_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Input_declarationContext,0)


        def output_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Output_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_declaration" ):
                listener.enterPort_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_declaration" ):
                listener.exitPort_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_declaration" ):
                return visitor.visitPort_declaration(self)
            else:
                return visitor.visitChildren(self)




    def port_declaration(self):

        localctx = VerilogParser.Port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 34, self.RULE_port_declaration)
        self._la = 0 # Token type
        try:
            self.state = 948
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,24,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 930
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 927
                    self.attribute_instance()
                    self.state = 932
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 933
                self.inout_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 937
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 934
                    self.attribute_instance()
                    self.state = 939
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 940
                self.input_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 944
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 941
                    self.attribute_instance()
                    self.state = 946
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 947
                self.output_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Port_declarationContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def module_or_generate_item(self):
            return self.getTypedRuleContext(VerilogParser.Module_or_generate_itemContext,0)


        def generate_region(self):
            return self.getTypedRuleContext(VerilogParser.Generate_regionContext,0)


        def specify_block(self):
            return self.getTypedRuleContext(VerilogParser.Specify_blockContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def specparam_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Specparam_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_item" ):
                listener.enterModule_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_item" ):
                listener.exitModule_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_item" ):
                return visitor.visitModule_item(self)
            else:
                return visitor.visitChildren(self)




    def module_item(self):

        localctx = VerilogParser.Module_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 36, self.RULE_module_item)
        self._la = 0 # Token type
        try:
            self.state = 972
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,27,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 950
                self.port_declaration()
                self.state = 951
                self.match(VerilogParser.SC)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 953
                self.module_or_generate_item()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 954
                self.generate_region()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 955
                self.specify_block()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 959
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 956
                    self.attribute_instance()
                    self.state = 961
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 962
                self.parameter_declaration()
                self.state = 963
                self.match(VerilogParser.SC)
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 968
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 965
                    self.attribute_instance()
                    self.state = 970
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 971
                self.specparam_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_or_generate_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_or_generate_item_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Module_or_generate_item_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def local_parameter_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Local_parameter_declarationContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def parameter_override(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_overrideContext,0)


        def continuous_assign(self):
            return self.getTypedRuleContext(VerilogParser.Continuous_assignContext,0)


        def gate_instantiation(self):
            return self.getTypedRuleContext(VerilogParser.Gate_instantiationContext,0)


        def module_instantiation(self):
            return self.getTypedRuleContext(VerilogParser.Module_instantiationContext,0)


        def udp_instantiation(self):
            return self.getTypedRuleContext(VerilogParser.Udp_instantiationContext,0)


        def initial_construct(self):
            return self.getTypedRuleContext(VerilogParser.Initial_constructContext,0)


        def always_construct(self):
            return self.getTypedRuleContext(VerilogParser.Always_constructContext,0)


        def loop_generate_construct(self):
            return self.getTypedRuleContext(VerilogParser.Loop_generate_constructContext,0)


        def conditional_generate_construct(self):
            return self.getTypedRuleContext(VerilogParser.Conditional_generate_constructContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_or_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_or_generate_item" ):
                listener.enterModule_or_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_or_generate_item" ):
                listener.exitModule_or_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_or_generate_item" ):
                return visitor.visitModule_or_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def module_or_generate_item(self):

        localctx = VerilogParser.Module_or_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 38, self.RULE_module_or_generate_item)
        self._la = 0 # Token type
        try:
            self.state = 1053
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,39,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 977
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 974
                    self.attribute_instance()
                    self.state = 979
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 980
                self.module_or_generate_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 984
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 981
                    self.attribute_instance()
                    self.state = 986
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 987
                self.local_parameter_declaration()
                self.state = 988
                self.match(VerilogParser.SC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 993
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 990
                    self.attribute_instance()
                    self.state = 995
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 996
                self.parameter_override()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1000
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 997
                    self.attribute_instance()
                    self.state = 1002
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1003
                self.continuous_assign()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1007
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1004
                    self.attribute_instance()
                    self.state = 1009
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1010
                self.gate_instantiation()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1014
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1011
                    self.attribute_instance()
                    self.state = 1016
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1017
                self.module_instantiation()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1021
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1018
                    self.attribute_instance()
                    self.state = 1023
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1024
                self.udp_instantiation()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1028
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1025
                    self.attribute_instance()
                    self.state = 1030
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1031
                self.initial_construct()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 1035
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1032
                    self.attribute_instance()
                    self.state = 1037
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1038
                self.always_construct()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 1042
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1039
                    self.attribute_instance()
                    self.state = 1044
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1045
                self.loop_generate_construct()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 1049
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1046
                    self.attribute_instance()
                    self.state = 1051
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1052
                self.conditional_generate_construct()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_or_generate_item_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Net_declarationContext,0)


        def reg_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Reg_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Integer_declarationContext,0)


        def real_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Real_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Time_declarationContext,0)


        def realtime_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Realtime_declarationContext,0)


        def event_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Event_declarationContext,0)


        def genvar_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_declarationContext,0)


        def task_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Task_declarationContext,0)


        def function_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Function_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_or_generate_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_or_generate_item_declaration" ):
                listener.enterModule_or_generate_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_or_generate_item_declaration" ):
                listener.exitModule_or_generate_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_or_generate_item_declaration" ):
                return visitor.visitModule_or_generate_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def module_or_generate_item_declaration(self):

        localctx = VerilogParser.Module_or_generate_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 40, self.RULE_module_or_generate_item_declaration)
        try:
            self.state = 1065
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.SUPPLYONE, VerilogParser.SUPPLYZERO, VerilogParser.TRI, VerilogParser.TRIAND, VerilogParser.TRIONE, VerilogParser.TRIOR, VerilogParser.TRIREG, VerilogParser.TRIZERO, VerilogParser.UWIRE, VerilogParser.WAND, VerilogParser.WIRE, VerilogParser.WOR]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1055
                self.net_declaration()
                pass
            elif token in [VerilogParser.REG]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1056
                self.reg_declaration()
                pass
            elif token in [VerilogParser.INTEGER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1057
                self.integer_declaration()
                pass
            elif token in [VerilogParser.REAL]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1058
                self.real_declaration()
                pass
            elif token in [VerilogParser.TIME]:
                self.enterOuterAlt(localctx, 5)
                self.state = 1059
                self.time_declaration()
                pass
            elif token in [VerilogParser.REALTIME]:
                self.enterOuterAlt(localctx, 6)
                self.state = 1060
                self.realtime_declaration()
                pass
            elif token in [VerilogParser.EVENT]:
                self.enterOuterAlt(localctx, 7)
                self.state = 1061
                self.event_declaration()
                pass
            elif token in [VerilogParser.GENVAR]:
                self.enterOuterAlt(localctx, 8)
                self.state = 1062
                self.genvar_declaration()
                pass
            elif token in [VerilogParser.TASK]:
                self.enterOuterAlt(localctx, 9)
                self.state = 1063
                self.task_declaration()
                pass
            elif token in [VerilogParser.FUNCTION]:
                self.enterOuterAlt(localctx, 10)
                self.state = 1064
                self.function_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Parameter_overrideContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DEFPARAM(self):
            return self.getToken(VerilogParser.DEFPARAM, 0)

        def list_of_defparam_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_defparam_assignmentsContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_override

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_override" ):
                listener.enterParameter_override(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_override" ):
                listener.exitParameter_override(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_override" ):
                return visitor.visitParameter_override(self)
            else:
                return visitor.visitChildren(self)




    def parameter_override(self):

        localctx = VerilogParser.Parameter_overrideContext(self, self._ctx, self.state)
        self.enterRule(localctx, 42, self.RULE_parameter_override)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1067
            self.match(VerilogParser.DEFPARAM)
            self.state = 1068
            self.list_of_defparam_assignments()
            self.state = 1069
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Config_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CONFIG(self):
            return self.getToken(VerilogParser.CONFIG, 0)

        def config_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Config_identifierContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def design_statement(self):
            return self.getTypedRuleContext(VerilogParser.Design_statementContext,0)


        def ENDCONFIG(self):
            return self.getToken(VerilogParser.ENDCONFIG, 0)

        def config_rule_statement(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Config_rule_statementContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Config_rule_statementContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_config_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_declaration" ):
                listener.enterConfig_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_declaration" ):
                listener.exitConfig_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_declaration" ):
                return visitor.visitConfig_declaration(self)
            else:
                return visitor.visitChildren(self)




    def config_declaration(self):

        localctx = VerilogParser.Config_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 44, self.RULE_config_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1071
            self.match(VerilogParser.CONFIG)
            self.state = 1072
            self.config_identifier()
            self.state = 1073
            self.match(VerilogParser.SC)
            self.state = 1074
            self.design_statement()
            self.state = 1078
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.CELL) | (1 << VerilogParser.DEFAULT) | (1 << VerilogParser.INSTANCE))) != 0):
                self.state = 1075
                self.config_rule_statement()
                self.state = 1080
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1081
            self.match(VerilogParser.ENDCONFIG)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Design_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DESIGN(self):
            return self.getToken(VerilogParser.DESIGN, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def design_statement_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Design_statement_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Design_statement_itemContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_design_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDesign_statement" ):
                listener.enterDesign_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDesign_statement" ):
                listener.exitDesign_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDesign_statement" ):
                return visitor.visitDesign_statement(self)
            else:
                return visitor.visitChildren(self)




    def design_statement(self):

        localctx = VerilogParser.Design_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 46, self.RULE_design_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1083
            self.match(VerilogParser.DESIGN)
            self.state = 1087
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 1084
                self.design_statement_item()
                self.state = 1089
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1090
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Design_statement_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cell_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Cell_identifierContext,0)


        def library_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Library_identifierContext,0)


        def DT(self):
            return self.getToken(VerilogParser.DT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_design_statement_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDesign_statement_item" ):
                listener.enterDesign_statement_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDesign_statement_item" ):
                listener.exitDesign_statement_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDesign_statement_item" ):
                return visitor.visitDesign_statement_item(self)
            else:
                return visitor.visitChildren(self)




    def design_statement_item(self):

        localctx = VerilogParser.Design_statement_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 48, self.RULE_design_statement_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1095
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,43,self._ctx)
            if la_ == 1:
                self.state = 1092
                self.library_identifier()
                self.state = 1093
                self.match(VerilogParser.DT)


            self.state = 1097
            self.cell_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Config_rule_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def default_clause(self):
            return self.getTypedRuleContext(VerilogParser.Default_clauseContext,0)


        def liblist_clause(self):
            return self.getTypedRuleContext(VerilogParser.Liblist_clauseContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def inst_clause(self):
            return self.getTypedRuleContext(VerilogParser.Inst_clauseContext,0)


        def use_clause(self):
            return self.getTypedRuleContext(VerilogParser.Use_clauseContext,0)


        def cell_clause(self):
            return self.getTypedRuleContext(VerilogParser.Cell_clauseContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_config_rule_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_rule_statement" ):
                listener.enterConfig_rule_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_rule_statement" ):
                listener.exitConfig_rule_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_rule_statement" ):
                return visitor.visitConfig_rule_statement(self)
            else:
                return visitor.visitChildren(self)




    def config_rule_statement(self):

        localctx = VerilogParser.Config_rule_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 50, self.RULE_config_rule_statement)
        try:
            self.state = 1119
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,44,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1099
                self.default_clause()
                self.state = 1100
                self.liblist_clause()
                self.state = 1101
                self.match(VerilogParser.SC)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1103
                self.inst_clause()
                self.state = 1104
                self.liblist_clause()
                self.state = 1105
                self.match(VerilogParser.SC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1107
                self.inst_clause()
                self.state = 1108
                self.use_clause()
                self.state = 1109
                self.match(VerilogParser.SC)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1111
                self.cell_clause()
                self.state = 1112
                self.liblist_clause()
                self.state = 1113
                self.match(VerilogParser.SC)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1115
                self.cell_clause()
                self.state = 1116
                self.use_clause()
                self.state = 1117
                self.match(VerilogParser.SC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Default_clauseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DEFAULT(self):
            return self.getToken(VerilogParser.DEFAULT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_default_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefault_clause" ):
                listener.enterDefault_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefault_clause" ):
                listener.exitDefault_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefault_clause" ):
                return visitor.visitDefault_clause(self)
            else:
                return visitor.visitChildren(self)




    def default_clause(self):

        localctx = VerilogParser.Default_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 52, self.RULE_default_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1121
            self.match(VerilogParser.DEFAULT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Inst_clauseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INSTANCE(self):
            return self.getToken(VerilogParser.INSTANCE, 0)

        def inst_name(self):
            return self.getTypedRuleContext(VerilogParser.Inst_nameContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_inst_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInst_clause" ):
                listener.enterInst_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInst_clause" ):
                listener.exitInst_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInst_clause" ):
                return visitor.visitInst_clause(self)
            else:
                return visitor.visitChildren(self)




    def inst_clause(self):

        localctx = VerilogParser.Inst_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 54, self.RULE_inst_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1123
            self.match(VerilogParser.INSTANCE)
            self.state = 1124
            self.inst_name()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Inst_nameContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def topmodule_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Topmodule_identifierContext,0)


        def DT(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.DT)
            else:
                return self.getToken(VerilogParser.DT, i)

        def instance_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Instance_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Instance_identifierContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_inst_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInst_name" ):
                listener.enterInst_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInst_name" ):
                listener.exitInst_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInst_name" ):
                return visitor.visitInst_name(self)
            else:
                return visitor.visitChildren(self)




    def inst_name(self):

        localctx = VerilogParser.Inst_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 56, self.RULE_inst_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1126
            self.topmodule_identifier()
            self.state = 1131
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.DT:
                self.state = 1127
                self.match(VerilogParser.DT)
                self.state = 1128
                self.instance_identifier()
                self.state = 1133
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Cell_clauseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CELL(self):
            return self.getToken(VerilogParser.CELL, 0)

        def cell_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Cell_identifierContext,0)


        def library_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Library_identifierContext,0)


        def DT(self):
            return self.getToken(VerilogParser.DT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_cell_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCell_clause" ):
                listener.enterCell_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCell_clause" ):
                listener.exitCell_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCell_clause" ):
                return visitor.visitCell_clause(self)
            else:
                return visitor.visitChildren(self)




    def cell_clause(self):

        localctx = VerilogParser.Cell_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 58, self.RULE_cell_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1134
            self.match(VerilogParser.CELL)
            self.state = 1138
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,46,self._ctx)
            if la_ == 1:
                self.state = 1135
                self.library_identifier()
                self.state = 1136
                self.match(VerilogParser.DT)


            self.state = 1140
            self.cell_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Liblist_clauseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LIBLIST(self):
            return self.getToken(VerilogParser.LIBLIST, 0)

        def library_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Library_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Library_identifierContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_liblist_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLiblist_clause" ):
                listener.enterLiblist_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLiblist_clause" ):
                listener.exitLiblist_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLiblist_clause" ):
                return visitor.visitLiblist_clause(self)
            else:
                return visitor.visitChildren(self)




    def liblist_clause(self):

        localctx = VerilogParser.Liblist_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 60, self.RULE_liblist_clause)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1142
            self.match(VerilogParser.LIBLIST)
            self.state = 1146
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 1143
                self.library_identifier()
                self.state = 1148
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Use_clauseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def USE(self):
            return self.getToken(VerilogParser.USE, 0)

        def cell_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Cell_identifierContext,0)


        def library_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Library_identifierContext,0)


        def DT(self):
            return self.getToken(VerilogParser.DT, 0)

        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def CONFIG(self):
            return self.getToken(VerilogParser.CONFIG, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_use_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUse_clause" ):
                listener.enterUse_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUse_clause" ):
                listener.exitUse_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUse_clause" ):
                return visitor.visitUse_clause(self)
            else:
                return visitor.visitChildren(self)




    def use_clause(self):

        localctx = VerilogParser.Use_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 62, self.RULE_use_clause)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1149
            self.match(VerilogParser.USE)
            self.state = 1153
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,48,self._ctx)
            if la_ == 1:
                self.state = 1150
                self.library_identifier()
                self.state = 1151
                self.match(VerilogParser.DT)


            self.state = 1155
            self.cell_identifier()
            self.state = 1158
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CL:
                self.state = 1156
                self.match(VerilogParser.CL)
                self.state = 1157
                self.match(VerilogParser.CONFIG)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Local_parameter_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LOCALPARAM(self):
            return self.getToken(VerilogParser.LOCALPARAM, 0)

        def list_of_param_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_param_assignmentsContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def parameter_type(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_local_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLocal_parameter_declaration" ):
                listener.enterLocal_parameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLocal_parameter_declaration" ):
                listener.exitLocal_parameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLocal_parameter_declaration" ):
                return visitor.visitLocal_parameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def local_parameter_declaration(self):

        localctx = VerilogParser.Local_parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 64, self.RULE_local_parameter_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1172
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,52,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1160
                self.match(VerilogParser.LOCALPARAM)
                self.state = 1162
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1161
                    self.match(VerilogParser.SIGNED)


                self.state = 1165
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1164
                    self.range_()


                self.state = 1167
                self.list_of_param_assignments()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1168
                self.match(VerilogParser.LOCALPARAM)
                self.state = 1169
                self.parameter_type()
                self.state = 1170
                self.list_of_param_assignments()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Parameter_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PARAMETER(self):
            return self.getToken(VerilogParser.PARAMETER, 0)

        def list_of_param_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_param_assignmentsContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def parameter_type(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_declaration" ):
                listener.enterParameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_declaration" ):
                listener.exitParameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_declaration" ):
                return visitor.visitParameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def parameter_declaration(self):

        localctx = VerilogParser.Parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 66, self.RULE_parameter_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1186
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,55,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1174
                self.match(VerilogParser.PARAMETER)
                self.state = 1176
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1175
                    self.match(VerilogParser.SIGNED)


                self.state = 1179
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1178
                    self.range_()


                self.state = 1181
                self.list_of_param_assignments()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1182
                self.match(VerilogParser.PARAMETER)
                self.state = 1183
                self.parameter_type()
                self.state = 1184
                self.list_of_param_assignments()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Specparam_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SPECPARAM(self):
            return self.getToken(VerilogParser.SPECPARAM, 0)

        def list_of_specparam_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_specparam_assignmentsContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specparam_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_declaration" ):
                listener.enterSpecparam_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_declaration" ):
                listener.exitSpecparam_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_declaration" ):
                return visitor.visitSpecparam_declaration(self)
            else:
                return visitor.visitChildren(self)




    def specparam_declaration(self):

        localctx = VerilogParser.Specparam_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 68, self.RULE_specparam_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1188
            self.match(VerilogParser.SPECPARAM)
            self.state = 1190
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 1189
                self.range_()


            self.state = 1192
            self.list_of_specparam_assignments()
            self.state = 1193
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Parameter_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_type" ):
                listener.enterParameter_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_type" ):
                listener.exitParameter_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_type" ):
                return visitor.visitParameter_type(self)
            else:
                return visitor.visitChildren(self)




    def parameter_type(self):

        localctx = VerilogParser.Parameter_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 70, self.RULE_parameter_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1195
            _la = self._input.LA(1)
            if not(((((_la - 61)) & ~0x3f) == 0 and ((1 << (_la - 61)) & ((1 << (VerilogParser.INTEGER - 61)) | (1 << (VerilogParser.REAL - 61)) | (1 << (VerilogParser.REALTIME - 61)) | (1 << (VerilogParser.TIME - 61)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Inout_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INOUT(self):
            return self.getToken(VerilogParser.INOUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def net_type(self):
            return self.getTypedRuleContext(VerilogParser.Net_typeContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_inout_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_declaration" ):
                listener.enterInout_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_declaration" ):
                listener.exitInout_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_declaration" ):
                return visitor.visitInout_declaration(self)
            else:
                return visitor.visitChildren(self)




    def inout_declaration(self):

        localctx = VerilogParser.Inout_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 72, self.RULE_inout_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1197
            self.match(VerilogParser.INOUT)
            self.state = 1199
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 111)) & ~0x3f) == 0 and ((1 << (_la - 111)) & ((1 << (VerilogParser.SUPPLYONE - 111)) | (1 << (VerilogParser.SUPPLYZERO - 111)) | (1 << (VerilogParser.TRI - 111)) | (1 << (VerilogParser.TRIAND - 111)) | (1 << (VerilogParser.TRIONE - 111)) | (1 << (VerilogParser.TRIOR - 111)) | (1 << (VerilogParser.TRIZERO - 111)) | (1 << (VerilogParser.UWIRE - 111)) | (1 << (VerilogParser.WAND - 111)) | (1 << (VerilogParser.WIRE - 111)) | (1 << (VerilogParser.WOR - 111)))) != 0):
                self.state = 1198
                self.net_type()


            self.state = 1202
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.SIGNED:
                self.state = 1201
                self.match(VerilogParser.SIGNED)


            self.state = 1205
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 1204
                self.range_()


            self.state = 1207
            self.list_of_port_identifiers()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Input_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INPUT(self):
            return self.getToken(VerilogParser.INPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def net_type(self):
            return self.getTypedRuleContext(VerilogParser.Net_typeContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_input_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_declaration" ):
                listener.enterInput_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_declaration" ):
                listener.exitInput_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_declaration" ):
                return visitor.visitInput_declaration(self)
            else:
                return visitor.visitChildren(self)




    def input_declaration(self):

        localctx = VerilogParser.Input_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 74, self.RULE_input_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1209
            self.match(VerilogParser.INPUT)
            self.state = 1211
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 111)) & ~0x3f) == 0 and ((1 << (_la - 111)) & ((1 << (VerilogParser.SUPPLYONE - 111)) | (1 << (VerilogParser.SUPPLYZERO - 111)) | (1 << (VerilogParser.TRI - 111)) | (1 << (VerilogParser.TRIAND - 111)) | (1 << (VerilogParser.TRIONE - 111)) | (1 << (VerilogParser.TRIOR - 111)) | (1 << (VerilogParser.TRIZERO - 111)) | (1 << (VerilogParser.UWIRE - 111)) | (1 << (VerilogParser.WAND - 111)) | (1 << (VerilogParser.WIRE - 111)) | (1 << (VerilogParser.WOR - 111)))) != 0):
                self.state = 1210
                self.net_type()


            self.state = 1214
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.SIGNED:
                self.state = 1213
                self.match(VerilogParser.SIGNED)


            self.state = 1217
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 1216
                self.range_()


            self.state = 1219
            self.list_of_port_identifiers()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Output_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def OUTPUT(self):
            return self.getToken(VerilogParser.OUTPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def net_type(self):
            return self.getTypedRuleContext(VerilogParser.Net_typeContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def list_of_variable_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_variable_port_identifiersContext,0)


        def output_variable_type(self):
            return self.getTypedRuleContext(VerilogParser.Output_variable_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_output_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_declaration" ):
                listener.enterOutput_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_declaration" ):
                listener.exitOutput_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_declaration" ):
                return visitor.visitOutput_declaration(self)
            else:
                return visitor.visitChildren(self)




    def output_declaration(self):

        localctx = VerilogParser.Output_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 76, self.RULE_output_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1245
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,68,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1221
                self.match(VerilogParser.OUTPUT)
                self.state = 1223
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 111)) & ~0x3f) == 0 and ((1 << (_la - 111)) & ((1 << (VerilogParser.SUPPLYONE - 111)) | (1 << (VerilogParser.SUPPLYZERO - 111)) | (1 << (VerilogParser.TRI - 111)) | (1 << (VerilogParser.TRIAND - 111)) | (1 << (VerilogParser.TRIONE - 111)) | (1 << (VerilogParser.TRIOR - 111)) | (1 << (VerilogParser.TRIZERO - 111)) | (1 << (VerilogParser.UWIRE - 111)) | (1 << (VerilogParser.WAND - 111)) | (1 << (VerilogParser.WIRE - 111)) | (1 << (VerilogParser.WOR - 111)))) != 0):
                    self.state = 1222
                    self.net_type()


                self.state = 1226
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1225
                    self.match(VerilogParser.SIGNED)


                self.state = 1229
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1228
                    self.range_()


                self.state = 1231
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1232
                self.match(VerilogParser.OUTPUT)
                self.state = 1233
                self.match(VerilogParser.REG)
                self.state = 1235
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1234
                    self.match(VerilogParser.SIGNED)


                self.state = 1238
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1237
                    self.range_()


                self.state = 1240
                self.list_of_variable_port_identifiers()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1241
                self.match(VerilogParser.OUTPUT)
                self.state = 1242
                self.output_variable_type()
                self.state = 1243
                self.list_of_variable_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Event_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EVENT(self):
            return self.getToken(VerilogParser.EVENT, 0)

        def list_of_event_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_event_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_event_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_declaration" ):
                listener.enterEvent_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_declaration" ):
                listener.exitEvent_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_declaration" ):
                return visitor.visitEvent_declaration(self)
            else:
                return visitor.visitChildren(self)




    def event_declaration(self):

        localctx = VerilogParser.Event_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 78, self.RULE_event_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1247
            self.match(VerilogParser.EVENT)
            self.state = 1248
            self.list_of_event_identifiers()
            self.state = 1249
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Integer_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def list_of_variable_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_variable_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_integer_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInteger_declaration" ):
                listener.enterInteger_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInteger_declaration" ):
                listener.exitInteger_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInteger_declaration" ):
                return visitor.visitInteger_declaration(self)
            else:
                return visitor.visitChildren(self)




    def integer_declaration(self):

        localctx = VerilogParser.Integer_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 80, self.RULE_integer_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1251
            self.match(VerilogParser.INTEGER)
            self.state = 1252
            self.list_of_variable_identifiers()
            self.state = 1253
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Net_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_type(self):
            return self.getTypedRuleContext(VerilogParser.Net_typeContext,0)


        def list_of_net_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_net_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def delay3(self):
            return self.getTypedRuleContext(VerilogParser.Delay3Context,0)


        def list_of_net_decl_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_net_decl_assignmentsContext,0)


        def drive_strength(self):
            return self.getTypedRuleContext(VerilogParser.Drive_strengthContext,0)


        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def VECTORED(self):
            return self.getToken(VerilogParser.VECTORED, 0)

        def SCALARED(self):
            return self.getToken(VerilogParser.SCALARED, 0)

        def TRIREG(self):
            return self.getToken(VerilogParser.TRIREG, 0)

        def charge_strength(self):
            return self.getTypedRuleContext(VerilogParser.Charge_strengthContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_declaration" ):
                listener.enterNet_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_declaration" ):
                listener.exitNet_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_declaration" ):
                return visitor.visitNet_declaration(self)
            else:
                return visitor.visitChildren(self)




    def net_declaration(self):

        localctx = VerilogParser.Net_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 82, self.RULE_net_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1369
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,95,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1255
                self.net_type()
                self.state = 1257
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1256
                    self.match(VerilogParser.SIGNED)


                self.state = 1260
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 1259
                    self.delay3()


                self.state = 1262
                self.list_of_net_identifiers()
                self.state = 1263
                self.match(VerilogParser.SC)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1265
                self.net_type()
                self.state = 1267
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LP:
                    self.state = 1266
                    self.drive_strength()


                self.state = 1270
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1269
                    self.match(VerilogParser.SIGNED)


                self.state = 1273
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 1272
                    self.delay3()


                self.state = 1275
                self.list_of_net_decl_assignments()
                self.state = 1276
                self.match(VerilogParser.SC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1278
                self.net_type()
                self.state = 1280
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED:
                    self.state = 1279
                    _la = self._input.LA(1)
                    if not(_la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 1283
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1282
                    self.match(VerilogParser.SIGNED)


                self.state = 1285
                self.range_()
                self.state = 1287
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 1286
                    self.delay3()


                self.state = 1289
                self.list_of_net_identifiers()
                self.state = 1290
                self.match(VerilogParser.SC)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1292
                self.net_type()
                self.state = 1294
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LP:
                    self.state = 1293
                    self.drive_strength()


                self.state = 1297
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED:
                    self.state = 1296
                    _la = self._input.LA(1)
                    if not(_la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 1300
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1299
                    self.match(VerilogParser.SIGNED)


                self.state = 1302
                self.range_()
                self.state = 1304
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 1303
                    self.delay3()


                self.state = 1306
                self.list_of_net_decl_assignments()
                self.state = 1307
                self.match(VerilogParser.SC)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1309
                self.match(VerilogParser.TRIREG)
                self.state = 1311
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LP:
                    self.state = 1310
                    self.charge_strength()


                self.state = 1314
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1313
                    self.match(VerilogParser.SIGNED)


                self.state = 1317
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 1316
                    self.delay3()


                self.state = 1319
                self.list_of_net_identifiers()
                self.state = 1320
                self.match(VerilogParser.SC)
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1322
                self.match(VerilogParser.TRIREG)
                self.state = 1324
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LP:
                    self.state = 1323
                    self.drive_strength()


                self.state = 1327
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1326
                    self.match(VerilogParser.SIGNED)


                self.state = 1330
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 1329
                    self.delay3()


                self.state = 1332
                self.list_of_net_decl_assignments()
                self.state = 1333
                self.match(VerilogParser.SC)
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1335
                self.match(VerilogParser.TRIREG)
                self.state = 1337
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LP:
                    self.state = 1336
                    self.charge_strength()


                self.state = 1340
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED:
                    self.state = 1339
                    _la = self._input.LA(1)
                    if not(_la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 1343
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1342
                    self.match(VerilogParser.SIGNED)


                self.state = 1345
                self.range_()
                self.state = 1347
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 1346
                    self.delay3()


                self.state = 1349
                self.list_of_net_identifiers()
                self.state = 1350
                self.match(VerilogParser.SC)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1352
                self.match(VerilogParser.TRIREG)
                self.state = 1354
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LP:
                    self.state = 1353
                    self.drive_strength()


                self.state = 1357
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED:
                    self.state = 1356
                    _la = self._input.LA(1)
                    if not(_la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 1360
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1359
                    self.match(VerilogParser.SIGNED)


                self.state = 1362
                self.range_()
                self.state = 1364
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 1363
                    self.delay3()


                self.state = 1366
                self.list_of_net_decl_assignments()
                self.state = 1367
                self.match(VerilogParser.SC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Real_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def list_of_real_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_real_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_real_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_declaration" ):
                listener.enterReal_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_declaration" ):
                listener.exitReal_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_declaration" ):
                return visitor.visitReal_declaration(self)
            else:
                return visitor.visitChildren(self)




    def real_declaration(self):

        localctx = VerilogParser.Real_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 84, self.RULE_real_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1371
            self.match(VerilogParser.REAL)
            self.state = 1372
            self.list_of_real_identifiers()
            self.state = 1373
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Realtime_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def list_of_real_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_real_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_realtime_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRealtime_declaration" ):
                listener.enterRealtime_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRealtime_declaration" ):
                listener.exitRealtime_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRealtime_declaration" ):
                return visitor.visitRealtime_declaration(self)
            else:
                return visitor.visitChildren(self)




    def realtime_declaration(self):

        localctx = VerilogParser.Realtime_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 86, self.RULE_realtime_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1375
            self.match(VerilogParser.REALTIME)
            self.state = 1376
            self.list_of_real_identifiers()
            self.state = 1377
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Reg_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def list_of_variable_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_variable_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_reg_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReg_declaration" ):
                listener.enterReg_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReg_declaration" ):
                listener.exitReg_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReg_declaration" ):
                return visitor.visitReg_declaration(self)
            else:
                return visitor.visitChildren(self)




    def reg_declaration(self):

        localctx = VerilogParser.Reg_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 88, self.RULE_reg_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1379
            self.match(VerilogParser.REG)
            self.state = 1381
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.SIGNED:
                self.state = 1380
                self.match(VerilogParser.SIGNED)


            self.state = 1384
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 1383
                self.range_()


            self.state = 1386
            self.list_of_variable_identifiers()
            self.state = 1387
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Time_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def list_of_variable_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_variable_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_time_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTime_declaration" ):
                listener.enterTime_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTime_declaration" ):
                listener.exitTime_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTime_declaration" ):
                return visitor.visitTime_declaration(self)
            else:
                return visitor.visitChildren(self)




    def time_declaration(self):

        localctx = VerilogParser.Time_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 90, self.RULE_time_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1389
            self.match(VerilogParser.TIME)
            self.state = 1390
            self.list_of_variable_identifiers()
            self.state = 1391
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Net_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SUPPLYZERO(self):
            return self.getToken(VerilogParser.SUPPLYZERO, 0)

        def SUPPLYONE(self):
            return self.getToken(VerilogParser.SUPPLYONE, 0)

        def TRI(self):
            return self.getToken(VerilogParser.TRI, 0)

        def TRIAND(self):
            return self.getToken(VerilogParser.TRIAND, 0)

        def TRIOR(self):
            return self.getToken(VerilogParser.TRIOR, 0)

        def TRIZERO(self):
            return self.getToken(VerilogParser.TRIZERO, 0)

        def TRIONE(self):
            return self.getToken(VerilogParser.TRIONE, 0)

        def UWIRE(self):
            return self.getToken(VerilogParser.UWIRE, 0)

        def WIRE(self):
            return self.getToken(VerilogParser.WIRE, 0)

        def WAND(self):
            return self.getToken(VerilogParser.WAND, 0)

        def WOR(self):
            return self.getToken(VerilogParser.WOR, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_net_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_type" ):
                listener.enterNet_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_type" ):
                listener.exitNet_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_type" ):
                return visitor.visitNet_type(self)
            else:
                return visitor.visitChildren(self)




    def net_type(self):

        localctx = VerilogParser.Net_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 92, self.RULE_net_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1393
            _la = self._input.LA(1)
            if not(((((_la - 111)) & ~0x3f) == 0 and ((1 << (_la - 111)) & ((1 << (VerilogParser.SUPPLYONE - 111)) | (1 << (VerilogParser.SUPPLYZERO - 111)) | (1 << (VerilogParser.TRI - 111)) | (1 << (VerilogParser.TRIAND - 111)) | (1 << (VerilogParser.TRIONE - 111)) | (1 << (VerilogParser.TRIOR - 111)) | (1 << (VerilogParser.TRIZERO - 111)) | (1 << (VerilogParser.UWIRE - 111)) | (1 << (VerilogParser.WAND - 111)) | (1 << (VerilogParser.WIRE - 111)) | (1 << (VerilogParser.WOR - 111)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Output_variable_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_output_variable_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_variable_type" ):
                listener.enterOutput_variable_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_variable_type" ):
                listener.exitOutput_variable_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_variable_type" ):
                return visitor.visitOutput_variable_type(self)
            else:
                return visitor.visitChildren(self)




    def output_variable_type(self):

        localctx = VerilogParser.Output_variable_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 94, self.RULE_output_variable_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1395
            _la = self._input.LA(1)
            if not(_la==VerilogParser.INTEGER or _la==VerilogParser.TIME):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Real_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def real_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Real_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_real_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_type" ):
                listener.enterReal_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_type" ):
                listener.exitReal_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_type" ):
                return visitor.visitReal_type(self)
            else:
                return visitor.visitChildren(self)




    def real_type(self):

        localctx = VerilogParser.Real_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 96, self.RULE_real_type)
        self._la = 0 # Token type
        try:
            self.state = 1408
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,99,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1397
                self.real_identifier()
                self.state = 1401
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LB:
                    self.state = 1398
                    self.dimension()
                    self.state = 1403
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1404
                self.real_identifier()
                self.state = 1405
                self.match(VerilogParser.EQ)
                self.state = 1406
                self.constant_expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Variable_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_variable_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_type" ):
                listener.enterVariable_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_type" ):
                listener.exitVariable_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_type" ):
                return visitor.visitVariable_type(self)
            else:
                return visitor.visitChildren(self)




    def variable_type(self):

        localctx = VerilogParser.Variable_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 98, self.RULE_variable_type)
        self._la = 0 # Token type
        try:
            self.state = 1421
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,101,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1410
                self.variable_identifier()
                self.state = 1414
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LB:
                    self.state = 1411
                    self.dimension()
                    self.state = 1416
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1417
                self.variable_identifier()
                self.state = 1418
                self.match(VerilogParser.EQ)
                self.state = 1419
                self.constant_expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Drive_strengthContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def strength0(self):
            return self.getTypedRuleContext(VerilogParser.Strength0Context,0)


        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def strength1(self):
            return self.getTypedRuleContext(VerilogParser.Strength1Context,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def HIGHZONE(self):
            return self.getToken(VerilogParser.HIGHZONE, 0)

        def HIGHZZERO(self):
            return self.getToken(VerilogParser.HIGHZZERO, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_drive_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDrive_strength" ):
                listener.enterDrive_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDrive_strength" ):
                listener.exitDrive_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDrive_strength" ):
                return visitor.visitDrive_strength(self)
            else:
                return visitor.visitChildren(self)




    def drive_strength(self):

        localctx = VerilogParser.Drive_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 100, self.RULE_drive_strength)
        try:
            self.state = 1459
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,102,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1423
                self.match(VerilogParser.LP)
                self.state = 1424
                self.strength0()
                self.state = 1425
                self.match(VerilogParser.CO)
                self.state = 1426
                self.strength1()
                self.state = 1427
                self.match(VerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1429
                self.match(VerilogParser.LP)
                self.state = 1430
                self.strength1()
                self.state = 1431
                self.match(VerilogParser.CO)
                self.state = 1432
                self.strength0()
                self.state = 1433
                self.match(VerilogParser.RP)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1435
                self.match(VerilogParser.LP)
                self.state = 1436
                self.strength0()
                self.state = 1437
                self.match(VerilogParser.CO)
                self.state = 1438
                self.match(VerilogParser.HIGHZONE)
                self.state = 1439
                self.match(VerilogParser.RP)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1441
                self.match(VerilogParser.LP)
                self.state = 1442
                self.strength1()
                self.state = 1443
                self.match(VerilogParser.CO)
                self.state = 1444
                self.match(VerilogParser.HIGHZZERO)
                self.state = 1445
                self.match(VerilogParser.RP)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1447
                self.match(VerilogParser.LP)
                self.state = 1448
                self.match(VerilogParser.HIGHZZERO)
                self.state = 1449
                self.match(VerilogParser.CO)
                self.state = 1450
                self.strength1()
                self.state = 1451
                self.match(VerilogParser.RP)
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1453
                self.match(VerilogParser.LP)
                self.state = 1454
                self.match(VerilogParser.HIGHZONE)
                self.state = 1455
                self.match(VerilogParser.CO)
                self.state = 1456
                self.strength0()
                self.state = 1457
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Strength0Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SUPPLYZERO(self):
            return self.getToken(VerilogParser.SUPPLYZERO, 0)

        def STRONGZERO(self):
            return self.getToken(VerilogParser.STRONGZERO, 0)

        def PULLZERO(self):
            return self.getToken(VerilogParser.PULLZERO, 0)

        def WEAKZERO(self):
            return self.getToken(VerilogParser.WEAKZERO, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_strength0

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrength0" ):
                listener.enterStrength0(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrength0" ):
                listener.exitStrength0(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrength0" ):
                return visitor.visitStrength0(self)
            else:
                return visitor.visitChildren(self)




    def strength0(self):

        localctx = VerilogParser.Strength0Context(self, self._ctx, self.state)
        self.enterRule(localctx, 102, self.RULE_strength0)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1461
            _la = self._input.LA(1)
            if not(((((_la - 89)) & ~0x3f) == 0 and ((1 << (_la - 89)) & ((1 << (VerilogParser.PULLZERO - 89)) | (1 << (VerilogParser.STRONGZERO - 89)) | (1 << (VerilogParser.SUPPLYZERO - 89)) | (1 << (VerilogParser.WEAKZERO - 89)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Strength1Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SUPPLYONE(self):
            return self.getToken(VerilogParser.SUPPLYONE, 0)

        def STRONGONE(self):
            return self.getToken(VerilogParser.STRONGONE, 0)

        def PULLONE(self):
            return self.getToken(VerilogParser.PULLONE, 0)

        def WEAKONE(self):
            return self.getToken(VerilogParser.WEAKONE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_strength1

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrength1" ):
                listener.enterStrength1(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrength1" ):
                listener.exitStrength1(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrength1" ):
                return visitor.visitStrength1(self)
            else:
                return visitor.visitChildren(self)




    def strength1(self):

        localctx = VerilogParser.Strength1Context(self, self._ctx, self.state)
        self.enterRule(localctx, 104, self.RULE_strength1)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1463
            _la = self._input.LA(1)
            if not(((((_la - 87)) & ~0x3f) == 0 and ((1 << (_la - 87)) & ((1 << (VerilogParser.PULLONE - 87)) | (1 << (VerilogParser.STRONGONE - 87)) | (1 << (VerilogParser.SUPPLYONE - 87)) | (1 << (VerilogParser.WEAKONE - 87)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Charge_strengthContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def SMALL(self):
            return self.getToken(VerilogParser.SMALL, 0)

        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def MEDIUM(self):
            return self.getToken(VerilogParser.MEDIUM, 0)

        def LARGE(self):
            return self.getToken(VerilogParser.LARGE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_charge_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCharge_strength" ):
                listener.enterCharge_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCharge_strength" ):
                listener.exitCharge_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCharge_strength" ):
                return visitor.visitCharge_strength(self)
            else:
                return visitor.visitChildren(self)




    def charge_strength(self):

        localctx = VerilogParser.Charge_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 106, self.RULE_charge_strength)
        try:
            self.state = 1474
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,103,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1465
                self.match(VerilogParser.LP)
                self.state = 1466
                self.match(VerilogParser.SMALL)
                self.state = 1467
                self.match(VerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1468
                self.match(VerilogParser.LP)
                self.state = 1469
                self.match(VerilogParser.MEDIUM)
                self.state = 1470
                self.match(VerilogParser.RP)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1471
                self.match(VerilogParser.LP)
                self.state = 1472
                self.match(VerilogParser.LARGE)
                self.state = 1473
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delay3Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HA(self):
            return self.getToken(VerilogParser.HA, 0)

        def delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Delay_valueContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def mintypmax_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Mintypmax_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_delay3

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay3" ):
                listener.enterDelay3(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay3" ):
                listener.exitDelay3(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay3" ):
                return visitor.visitDelay3(self)
            else:
                return visitor.visitChildren(self)




    def delay3(self):

        localctx = VerilogParser.Delay3Context(self, self._ctx, self.state)
        self.enterRule(localctx, 108, self.RULE_delay3)
        self._la = 0 # Token type
        try:
            self.state = 1491
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,106,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1476
                self.match(VerilogParser.HA)
                self.state = 1477
                self.delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1478
                self.match(VerilogParser.HA)
                self.state = 1479
                self.match(VerilogParser.LP)
                self.state = 1480
                self.mintypmax_expression()
                self.state = 1487
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CO:
                    self.state = 1481
                    self.match(VerilogParser.CO)
                    self.state = 1482
                    self.mintypmax_expression()
                    self.state = 1485
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==VerilogParser.CO:
                        self.state = 1483
                        self.match(VerilogParser.CO)
                        self.state = 1484
                        self.mintypmax_expression()




                self.state = 1489
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delay2Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HA(self):
            return self.getToken(VerilogParser.HA, 0)

        def delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Delay_valueContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def mintypmax_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Mintypmax_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_delay2

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay2" ):
                listener.enterDelay2(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay2" ):
                listener.exitDelay2(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay2" ):
                return visitor.visitDelay2(self)
            else:
                return visitor.visitChildren(self)




    def delay2(self):

        localctx = VerilogParser.Delay2Context(self, self._ctx, self.state)
        self.enterRule(localctx, 110, self.RULE_delay2)
        self._la = 0 # Token type
        try:
            self.state = 1504
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,108,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1493
                self.match(VerilogParser.HA)
                self.state = 1494
                self.delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1495
                self.match(VerilogParser.HA)
                self.state = 1496
                self.match(VerilogParser.LP)
                self.state = 1497
                self.mintypmax_expression()
                self.state = 1500
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CO:
                    self.state = 1498
                    self.match(VerilogParser.CO)
                    self.state = 1499
                    self.mintypmax_expression()


                self.state = 1502
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delay_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def unsigned_number(self):
            return self.getTypedRuleContext(VerilogParser.Unsigned_numberContext,0)


        def real_number(self):
            return self.getTypedRuleContext(VerilogParser.Real_numberContext,0)


        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_delay_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_value" ):
                listener.enterDelay_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_value" ):
                listener.exitDelay_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_value" ):
                return visitor.visitDelay_value(self)
            else:
                return visitor.visitChildren(self)




    def delay_value(self):

        localctx = VerilogParser.Delay_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 112, self.RULE_delay_value)
        try:
            self.state = 1509
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.UNSIGNED_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1506
                self.unsigned_number()
                pass
            elif token in [VerilogParser.EXPONENTIAL_NUMBER, VerilogParser.FIXED_POINT_NUMBER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1507
                self.real_number()
                pass
            elif token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1508
                self.identifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_defparam_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def defparam_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Defparam_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Defparam_assignmentContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_defparam_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_defparam_assignments" ):
                listener.enterList_of_defparam_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_defparam_assignments" ):
                listener.exitList_of_defparam_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_defparam_assignments" ):
                return visitor.visitList_of_defparam_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_defparam_assignments(self):

        localctx = VerilogParser.List_of_defparam_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 114, self.RULE_list_of_defparam_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1511
            self.defparam_assignment()
            self.state = 1516
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1512
                self.match(VerilogParser.CO)
                self.state = 1513
                self.defparam_assignment()
                self.state = 1518
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_event_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def event_id(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Event_idContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Event_idContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_event_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_event_identifiers" ):
                listener.enterList_of_event_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_event_identifiers" ):
                listener.exitList_of_event_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_event_identifiers" ):
                return visitor.visitList_of_event_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_event_identifiers(self):

        localctx = VerilogParser.List_of_event_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 116, self.RULE_list_of_event_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1519
            self.event_id()
            self.state = 1524
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1520
                self.match(VerilogParser.CO)
                self.state = 1521
                self.event_id()
                self.state = 1526
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Event_idContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def event_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Event_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_event_id

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_id" ):
                listener.enterEvent_id(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_id" ):
                listener.exitEvent_id(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_id" ):
                return visitor.visitEvent_id(self)
            else:
                return visitor.visitChildren(self)




    def event_id(self):

        localctx = VerilogParser.Event_idContext(self, self._ctx, self.state)
        self.enterRule(localctx, 118, self.RULE_event_id)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1527
            self.event_identifier()
            self.state = 1531
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LB:
                self.state = 1528
                self.dimension()
                self.state = 1533
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_net_decl_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_decl_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Net_decl_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Net_decl_assignmentContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_net_decl_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_net_decl_assignments" ):
                listener.enterList_of_net_decl_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_net_decl_assignments" ):
                listener.exitList_of_net_decl_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_net_decl_assignments" ):
                return visitor.visitList_of_net_decl_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_net_decl_assignments(self):

        localctx = VerilogParser.List_of_net_decl_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 120, self.RULE_list_of_net_decl_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1534
            self.net_decl_assignment()
            self.state = 1539
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1535
                self.match(VerilogParser.CO)
                self.state = 1536
                self.net_decl_assignment()
                self.state = 1541
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_net_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_id(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Net_idContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Net_idContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_net_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_net_identifiers" ):
                listener.enterList_of_net_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_net_identifiers" ):
                listener.exitList_of_net_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_net_identifiers" ):
                return visitor.visitList_of_net_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_net_identifiers(self):

        localctx = VerilogParser.List_of_net_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 122, self.RULE_list_of_net_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1542
            self.net_id()
            self.state = 1547
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1543
                self.match(VerilogParser.CO)
                self.state = 1544
                self.net_id()
                self.state = 1549
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Net_idContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Net_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_id

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_id" ):
                listener.enterNet_id(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_id" ):
                listener.exitNet_id(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_id" ):
                return visitor.visitNet_id(self)
            else:
                return visitor.visitChildren(self)




    def net_id(self):

        localctx = VerilogParser.Net_idContext(self, self._ctx, self.state)
        self.enterRule(localctx, 124, self.RULE_net_id)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1550
            self.net_identifier()
            self.state = 1554
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LB:
                self.state = 1551
                self.dimension()
                self.state = 1556
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_param_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def param_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Param_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Param_assignmentContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_param_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_param_assignments" ):
                listener.enterList_of_param_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_param_assignments" ):
                listener.exitList_of_param_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_param_assignments" ):
                return visitor.visitList_of_param_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_param_assignments(self):

        localctx = VerilogParser.List_of_param_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 126, self.RULE_list_of_param_assignments)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1557
            self.param_assignment()
            self.state = 1562
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,116,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1558
                    self.match(VerilogParser.CO)
                    self.state = 1559
                    self.param_assignment() 
                self.state = 1564
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,116,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_port_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Port_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Port_identifierContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_port_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_identifiers" ):
                listener.enterList_of_port_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_identifiers" ):
                listener.exitList_of_port_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_identifiers" ):
                return visitor.visitList_of_port_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_identifiers(self):

        localctx = VerilogParser.List_of_port_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 128, self.RULE_list_of_port_identifiers)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1565
            self.port_identifier()
            self.state = 1570
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,117,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1566
                    self.match(VerilogParser.CO)
                    self.state = 1567
                    self.port_identifier() 
                self.state = 1572
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,117,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_real_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def real_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Real_typeContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Real_typeContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_real_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_real_identifiers" ):
                listener.enterList_of_real_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_real_identifiers" ):
                listener.exitList_of_real_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_real_identifiers" ):
                return visitor.visitList_of_real_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_real_identifiers(self):

        localctx = VerilogParser.List_of_real_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 130, self.RULE_list_of_real_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1573
            self.real_type()
            self.state = 1578
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1574
                self.match(VerilogParser.CO)
                self.state = 1575
                self.real_type()
                self.state = 1580
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_specparam_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Specparam_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Specparam_assignmentContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_specparam_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_specparam_assignments" ):
                listener.enterList_of_specparam_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_specparam_assignments" ):
                listener.exitList_of_specparam_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_specparam_assignments" ):
                return visitor.visitList_of_specparam_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_specparam_assignments(self):

        localctx = VerilogParser.List_of_specparam_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 132, self.RULE_list_of_specparam_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1581
            self.specparam_assignment()
            self.state = 1586
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1582
                self.match(VerilogParser.CO)
                self.state = 1583
                self.specparam_assignment()
                self.state = 1588
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_variable_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Variable_typeContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Variable_typeContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_variable_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_identifiers" ):
                listener.enterList_of_variable_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_identifiers" ):
                listener.exitList_of_variable_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_identifiers" ):
                return visitor.visitList_of_variable_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_identifiers(self):

        localctx = VerilogParser.List_of_variable_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 134, self.RULE_list_of_variable_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1589
            self.variable_type()
            self.state = 1594
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1590
                self.match(VerilogParser.CO)
                self.state = 1591
                self.variable_type()
                self.state = 1596
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_variable_port_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def var_port_id(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Var_port_idContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Var_port_idContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_variable_port_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_port_identifiers" ):
                listener.enterList_of_variable_port_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_port_identifiers" ):
                listener.exitList_of_variable_port_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_port_identifiers" ):
                return visitor.visitList_of_variable_port_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_port_identifiers(self):

        localctx = VerilogParser.List_of_variable_port_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 136, self.RULE_list_of_variable_port_identifiers)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1597
            self.var_port_id()
            self.state = 1602
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,121,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1598
                    self.match(VerilogParser.CO)
                    self.state = 1599
                    self.var_port_id() 
                self.state = 1604
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,121,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Var_port_idContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_var_port_id

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVar_port_id" ):
                listener.enterVar_port_id(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVar_port_id" ):
                listener.exitVar_port_id(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVar_port_id" ):
                return visitor.visitVar_port_id(self)
            else:
                return visitor.visitChildren(self)




    def var_port_id(self):

        localctx = VerilogParser.Var_port_idContext(self, self._ctx, self.state)
        self.enterRule(localctx, 138, self.RULE_var_port_id)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1605
            self.port_identifier()
            self.state = 1608
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.EQ:
                self.state = 1606
                self.match(VerilogParser.EQ)
                self.state = 1607
                self.constant_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Defparam_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_defparam_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefparam_assignment" ):
                listener.enterDefparam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefparam_assignment" ):
                listener.exitDefparam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefparam_assignment" ):
                return visitor.visitDefparam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def defparam_assignment(self):

        localctx = VerilogParser.Defparam_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 140, self.RULE_defparam_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1610
            self.hierarchical_identifier()
            self.state = 1611
            self.match(VerilogParser.EQ)
            self.state = 1612
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Net_decl_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Net_identifierContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_decl_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_decl_assignment" ):
                listener.enterNet_decl_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_decl_assignment" ):
                listener.exitNet_decl_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_decl_assignment" ):
                return visitor.visitNet_decl_assignment(self)
            else:
                return visitor.visitChildren(self)




    def net_decl_assignment(self):

        localctx = VerilogParser.Net_decl_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 142, self.RULE_net_decl_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1614
            self.net_identifier()
            self.state = 1615
            self.match(VerilogParser.EQ)
            self.state = 1616
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Param_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_identifierContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_param_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParam_assignment" ):
                listener.enterParam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParam_assignment" ):
                listener.exitParam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParam_assignment" ):
                return visitor.visitParam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def param_assignment(self):

        localctx = VerilogParser.Param_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 144, self.RULE_param_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1618
            self.parameter_identifier()
            self.state = 1619
            self.match(VerilogParser.EQ)
            self.state = 1620
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Specparam_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Specparam_identifierContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def pulse_control_specparam(self):
            return self.getTypedRuleContext(VerilogParser.Pulse_control_specparamContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specparam_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_assignment" ):
                listener.enterSpecparam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_assignment" ):
                listener.exitSpecparam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_assignment" ):
                return visitor.visitSpecparam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def specparam_assignment(self):

        localctx = VerilogParser.Specparam_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 146, self.RULE_specparam_assignment)
        try:
            self.state = 1627
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1622
                self.specparam_identifier()
                self.state = 1623
                self.match(VerilogParser.EQ)
                self.state = 1624
                self.constant_mintypmax_expression()
                pass
            elif token in [VerilogParser.PATHPULSEDL]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1626
                self.pulse_control_specparam()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pulse_control_specparamContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PATHPULSEDL(self):
            return self.getToken(VerilogParser.PATHPULSEDL, 0)

        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reject_limit_value(self):
            return self.getTypedRuleContext(VerilogParser.Reject_limit_valueContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def error_limit_value(self):
            return self.getTypedRuleContext(VerilogParser.Error_limit_valueContext,0)


        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,0)


        def DL(self):
            return self.getToken(VerilogParser.DL, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pulse_control_specparam

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulse_control_specparam" ):
                listener.enterPulse_control_specparam(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulse_control_specparam" ):
                listener.exitPulse_control_specparam(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulse_control_specparam" ):
                return visitor.visitPulse_control_specparam(self)
            else:
                return visitor.visitChildren(self)




    def pulse_control_specparam(self):

        localctx = VerilogParser.Pulse_control_specparamContext(self, self._ctx, self.state)
        self.enterRule(localctx, 148, self.RULE_pulse_control_specparam)
        self._la = 0 # Token type
        try:
            self.state = 1652
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,126,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1629
                self.match(VerilogParser.PATHPULSEDL)
                self.state = 1630
                self.match(VerilogParser.EQ)
                self.state = 1631
                self.match(VerilogParser.LP)
                self.state = 1632
                self.reject_limit_value()
                self.state = 1635
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CO:
                    self.state = 1633
                    self.match(VerilogParser.CO)
                    self.state = 1634
                    self.error_limit_value()


                self.state = 1637
                self.match(VerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1639
                self.match(VerilogParser.PATHPULSEDL)
                self.state = 1640
                self.specify_input_terminal_descriptor()
                self.state = 1641
                self.match(VerilogParser.DL)
                self.state = 1642
                self.specify_output_terminal_descriptor()
                self.state = 1643
                self.match(VerilogParser.EQ)
                self.state = 1644
                self.match(VerilogParser.LP)
                self.state = 1645
                self.reject_limit_value()
                self.state = 1648
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CO:
                    self.state = 1646
                    self.match(VerilogParser.CO)
                    self.state = 1647
                    self.error_limit_value()


                self.state = 1650
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Error_limit_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def limit_value(self):
            return self.getTypedRuleContext(VerilogParser.Limit_valueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_error_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterError_limit_value" ):
                listener.enterError_limit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitError_limit_value" ):
                listener.exitError_limit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitError_limit_value" ):
                return visitor.visitError_limit_value(self)
            else:
                return visitor.visitChildren(self)




    def error_limit_value(self):

        localctx = VerilogParser.Error_limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 150, self.RULE_error_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1654
            self.limit_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Reject_limit_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def limit_value(self):
            return self.getTypedRuleContext(VerilogParser.Limit_valueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_reject_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReject_limit_value" ):
                listener.enterReject_limit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReject_limit_value" ):
                listener.exitReject_limit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReject_limit_value" ):
                return visitor.visitReject_limit_value(self)
            else:
                return visitor.visitChildren(self)




    def reject_limit_value(self):

        localctx = VerilogParser.Reject_limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 152, self.RULE_reject_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1656
            self.limit_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Limit_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLimit_value" ):
                listener.enterLimit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLimit_value" ):
                listener.exitLimit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLimit_value" ):
                return visitor.visitLimit_value(self)
            else:
                return visitor.visitChildren(self)




    def limit_value(self):

        localctx = VerilogParser.Limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 154, self.RULE_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1658
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class DimensionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def dimension_constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Dimension_constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Dimension_constant_expressionContext,i)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDimension" ):
                listener.enterDimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDimension" ):
                listener.exitDimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDimension" ):
                return visitor.visitDimension(self)
            else:
                return visitor.visitChildren(self)




    def dimension(self):

        localctx = VerilogParser.DimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 156, self.RULE_dimension)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1660
            self.match(VerilogParser.LB)
            self.state = 1661
            self.dimension_constant_expression()
            self.state = 1662
            self.match(VerilogParser.CL)
            self.state = 1663
            self.dimension_constant_expression()
            self.state = 1664
            self.match(VerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Range_Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def msb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Msb_constant_expressionContext,0)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def lsb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Lsb_constant_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_range_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRange_" ):
                listener.enterRange_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRange_" ):
                listener.exitRange_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRange_" ):
                return visitor.visitRange_(self)
            else:
                return visitor.visitChildren(self)




    def range_(self):

        localctx = VerilogParser.Range_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 158, self.RULE_range_)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1666
            self.match(VerilogParser.LB)
            self.state = 1667
            self.msb_constant_expression()
            self.state = 1668
            self.match(VerilogParser.CL)
            self.state = 1669
            self.lsb_constant_expression()
            self.state = 1670
            self.match(VerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Function_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FUNCTION(self):
            return self.getToken(VerilogParser.FUNCTION, 0)

        def function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Function_identifierContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def function_statement(self):
            return self.getTypedRuleContext(VerilogParser.Function_statementContext,0)


        def ENDFUNCTION(self):
            return self.getToken(VerilogParser.ENDFUNCTION, 0)

        def AUTOMATIC(self):
            return self.getToken(VerilogParser.AUTOMATIC, 0)

        def function_range_or_type(self):
            return self.getTypedRuleContext(VerilogParser.Function_range_or_typeContext,0)


        def function_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Function_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Function_item_declarationContext,i)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def function_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Function_port_listContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_function_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_declaration" ):
                listener.enterFunction_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_declaration" ):
                listener.exitFunction_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_declaration" ):
                return visitor.visitFunction_declaration(self)
            else:
                return visitor.visitChildren(self)




    def function_declaration(self):

        localctx = VerilogParser.Function_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 160, self.RULE_function_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1710
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,133,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1672
                self.match(VerilogParser.FUNCTION)
                self.state = 1674
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.AUTOMATIC:
                    self.state = 1673
                    self.match(VerilogParser.AUTOMATIC)


                self.state = 1677
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 61)) & ~0x3f) == 0 and ((1 << (_la - 61)) & ((1 << (VerilogParser.INTEGER - 61)) | (1 << (VerilogParser.REAL - 61)) | (1 << (VerilogParser.REALTIME - 61)) | (1 << (VerilogParser.SIGNED - 61)) | (1 << (VerilogParser.TIME - 61)))) != 0) or _la==VerilogParser.LB:
                    self.state = 1676
                    self.function_range_or_type()


                self.state = 1679
                self.function_identifier()
                self.state = 1680
                self.match(VerilogParser.SC)
                self.state = 1682 
                self._errHandler.sync(self)
                _alt = 1
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt == 1:
                        self.state = 1681
                        self.function_item_declaration()

                    else:
                        raise NoViableAltException(self)
                    self.state = 1684 
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,129,self._ctx)

                self.state = 1686
                self.function_statement()
                self.state = 1687
                self.match(VerilogParser.ENDFUNCTION)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1689
                self.match(VerilogParser.FUNCTION)
                self.state = 1691
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.AUTOMATIC:
                    self.state = 1690
                    self.match(VerilogParser.AUTOMATIC)


                self.state = 1694
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 61)) & ~0x3f) == 0 and ((1 << (_la - 61)) & ((1 << (VerilogParser.INTEGER - 61)) | (1 << (VerilogParser.REAL - 61)) | (1 << (VerilogParser.REALTIME - 61)) | (1 << (VerilogParser.SIGNED - 61)) | (1 << (VerilogParser.TIME - 61)))) != 0) or _la==VerilogParser.LB:
                    self.state = 1693
                    self.function_range_or_type()


                self.state = 1696
                self.function_identifier()
                self.state = 1697
                self.match(VerilogParser.LP)
                self.state = 1698
                self.function_port_list()
                self.state = 1699
                self.match(VerilogParser.RP)
                self.state = 1700
                self.match(VerilogParser.SC)
                self.state = 1704
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,132,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 1701
                        self.block_item_declaration() 
                    self.state = 1706
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,132,self._ctx)

                self.state = 1707
                self.function_statement()
                self.state = 1708
                self.match(VerilogParser.ENDFUNCTION)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Function_item_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,0)


        def tf_input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_input_declarationContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_function_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_item_declaration" ):
                listener.enterFunction_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_item_declaration" ):
                listener.exitFunction_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_item_declaration" ):
                return visitor.visitFunction_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def function_item_declaration(self):

        localctx = VerilogParser.Function_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 162, self.RULE_function_item_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1722
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,135,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1712
                self.block_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1716
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1713
                    self.attribute_instance()
                    self.state = 1718
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1719
                self.tf_input_declaration()
                self.state = 1720
                self.match(VerilogParser.SC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Function_port_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def func_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Func_port_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Func_port_itemContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_function_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_port_list" ):
                listener.enterFunction_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_port_list" ):
                listener.exitFunction_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_port_list" ):
                return visitor.visitFunction_port_list(self)
            else:
                return visitor.visitChildren(self)




    def function_port_list(self):

        localctx = VerilogParser.Function_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 164, self.RULE_function_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1724
            self.func_port_item()
            self.state = 1729
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1725
                self.match(VerilogParser.CO)
                self.state = 1726
                self.func_port_item()
                self.state = 1731
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Func_port_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def tf_input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_input_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_func_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunc_port_item" ):
                listener.enterFunc_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunc_port_item" ):
                listener.exitFunc_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunc_port_item" ):
                return visitor.visitFunc_port_item(self)
            else:
                return visitor.visitChildren(self)




    def func_port_item(self):

        localctx = VerilogParser.Func_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 166, self.RULE_func_port_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1735
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LP:
                self.state = 1732
                self.attribute_instance()
                self.state = 1737
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1738
            self.tf_input_declaration()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Function_range_or_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_function_range_or_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_range_or_type" ):
                listener.enterFunction_range_or_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_range_or_type" ):
                listener.exitFunction_range_or_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_range_or_type" ):
                return visitor.visitFunction_range_or_type(self)
            else:
                return visitor.visitChildren(self)




    def function_range_or_type(self):

        localctx = VerilogParser.Function_range_or_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 168, self.RULE_function_range_or_type)
        self._la = 0 # Token type
        try:
            self.state = 1749
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.LB]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1740
                self.range_()
                pass
            elif token in [VerilogParser.SIGNED]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1741
                self.match(VerilogParser.SIGNED)
                self.state = 1743
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1742
                    self.range_()


                pass
            elif token in [VerilogParser.INTEGER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1745
                self.match(VerilogParser.INTEGER)
                pass
            elif token in [VerilogParser.REAL]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1746
                self.match(VerilogParser.REAL)
                pass
            elif token in [VerilogParser.REALTIME]:
                self.enterOuterAlt(localctx, 5)
                self.state = 1747
                self.match(VerilogParser.REALTIME)
                pass
            elif token in [VerilogParser.TIME]:
                self.enterOuterAlt(localctx, 6)
                self.state = 1748
                self.match(VerilogParser.TIME)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Task_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TASK(self):
            return self.getToken(VerilogParser.TASK, 0)

        def task_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Task_identifierContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,0)


        def ENDTASK(self):
            return self.getToken(VerilogParser.ENDTASK, 0)

        def AUTOMATIC(self):
            return self.getToken(VerilogParser.AUTOMATIC, 0)

        def task_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Task_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Task_item_declarationContext,i)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def task_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Task_port_listContext,0)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_declaration" ):
                listener.enterTask_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_declaration" ):
                listener.exitTask_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_declaration" ):
                return visitor.visitTask_declaration(self)
            else:
                return visitor.visitChildren(self)




    def task_declaration(self):

        localctx = VerilogParser.Task_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 170, self.RULE_task_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1786
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,145,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1751
                self.match(VerilogParser.TASK)
                self.state = 1753
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.AUTOMATIC:
                    self.state = 1752
                    self.match(VerilogParser.AUTOMATIC)


                self.state = 1755
                self.task_identifier()
                self.state = 1756
                self.match(VerilogParser.SC)
                self.state = 1760
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,141,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 1757
                        self.task_item_declaration() 
                    self.state = 1762
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,141,self._ctx)

                self.state = 1763
                self.statement_or_null()
                self.state = 1764
                self.match(VerilogParser.ENDTASK)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1766
                self.match(VerilogParser.TASK)
                self.state = 1768
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.AUTOMATIC:
                    self.state = 1767
                    self.match(VerilogParser.AUTOMATIC)


                self.state = 1770
                self.task_identifier()
                self.state = 1771
                self.match(VerilogParser.LP)
                self.state = 1773
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 58)) & ~0x3f) == 0 and ((1 << (_la - 58)) & ((1 << (VerilogParser.INOUT - 58)) | (1 << (VerilogParser.INPUT - 58)) | (1 << (VerilogParser.OUTPUT - 58)))) != 0) or _la==VerilogParser.LP:
                    self.state = 1772
                    self.task_port_list()


                self.state = 1775
                self.match(VerilogParser.RP)
                self.state = 1776
                self.match(VerilogParser.SC)
                self.state = 1780
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,144,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 1777
                        self.block_item_declaration() 
                    self.state = 1782
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,144,self._ctx)

                self.state = 1783
                self.statement_or_null()
                self.state = 1784
                self.match(VerilogParser.ENDTASK)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Task_item_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,0)


        def tf_input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_input_declarationContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def tf_output_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_output_declarationContext,0)


        def tf_inout_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_inout_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_item_declaration" ):
                listener.enterTask_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_item_declaration" ):
                listener.exitTask_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_item_declaration" ):
                return visitor.visitTask_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def task_item_declaration(self):

        localctx = VerilogParser.Task_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 172, self.RULE_task_item_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1816
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,149,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1788
                self.block_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1792
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1789
                    self.attribute_instance()
                    self.state = 1794
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1795
                self.tf_input_declaration()
                self.state = 1796
                self.match(VerilogParser.SC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1801
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1798
                    self.attribute_instance()
                    self.state = 1803
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1804
                self.tf_output_declaration()
                self.state = 1805
                self.match(VerilogParser.SC)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1810
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1807
                    self.attribute_instance()
                    self.state = 1812
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1813
                self.tf_inout_declaration()
                self.state = 1814
                self.match(VerilogParser.SC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Task_port_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Task_port_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Task_port_itemContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_task_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_port_list" ):
                listener.enterTask_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_port_list" ):
                listener.exitTask_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_port_list" ):
                return visitor.visitTask_port_list(self)
            else:
                return visitor.visitChildren(self)




    def task_port_list(self):

        localctx = VerilogParser.Task_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 174, self.RULE_task_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1818
            self.task_port_item()
            self.state = 1823
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1819
                self.match(VerilogParser.CO)
                self.state = 1820
                self.task_port_item()
                self.state = 1825
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Task_port_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def tf_input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_input_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def tf_output_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_output_declarationContext,0)


        def tf_inout_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_inout_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_port_item" ):
                listener.enterTask_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_port_item" ):
                listener.exitTask_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_port_item" ):
                return visitor.visitTask_port_item(self)
            else:
                return visitor.visitChildren(self)




    def task_port_item(self):

        localctx = VerilogParser.Task_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 176, self.RULE_task_port_item)
        self._la = 0 # Token type
        try:
            self.state = 1847
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,154,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1829
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1826
                    self.attribute_instance()
                    self.state = 1831
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1832
                self.tf_input_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1836
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1833
                    self.attribute_instance()
                    self.state = 1838
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1839
                self.tf_output_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1843
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1840
                    self.attribute_instance()
                    self.state = 1845
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1846
                self.tf_inout_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tf_input_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INPUT(self):
            return self.getToken(VerilogParser.INPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def task_port_type(self):
            return self.getTypedRuleContext(VerilogParser.Task_port_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tf_input_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_input_declaration" ):
                listener.enterTf_input_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_input_declaration" ):
                listener.exitTf_input_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_input_declaration" ):
                return visitor.visitTf_input_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_input_declaration(self):

        localctx = VerilogParser.Tf_input_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 178, self.RULE_tf_input_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1864
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,158,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1849
                self.match(VerilogParser.INPUT)
                self.state = 1851
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.REG:
                    self.state = 1850
                    self.match(VerilogParser.REG)


                self.state = 1854
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1853
                    self.match(VerilogParser.SIGNED)


                self.state = 1857
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1856
                    self.range_()


                self.state = 1859
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1860
                self.match(VerilogParser.INPUT)
                self.state = 1861
                self.task_port_type()
                self.state = 1862
                self.list_of_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tf_output_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def OUTPUT(self):
            return self.getToken(VerilogParser.OUTPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def task_port_type(self):
            return self.getTypedRuleContext(VerilogParser.Task_port_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tf_output_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_output_declaration" ):
                listener.enterTf_output_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_output_declaration" ):
                listener.exitTf_output_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_output_declaration" ):
                return visitor.visitTf_output_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_output_declaration(self):

        localctx = VerilogParser.Tf_output_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 180, self.RULE_tf_output_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1881
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,162,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1866
                self.match(VerilogParser.OUTPUT)
                self.state = 1868
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.REG:
                    self.state = 1867
                    self.match(VerilogParser.REG)


                self.state = 1871
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1870
                    self.match(VerilogParser.SIGNED)


                self.state = 1874
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1873
                    self.range_()


                self.state = 1876
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1877
                self.match(VerilogParser.OUTPUT)
                self.state = 1878
                self.task_port_type()
                self.state = 1879
                self.list_of_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tf_inout_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INOUT(self):
            return self.getToken(VerilogParser.INOUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def task_port_type(self):
            return self.getTypedRuleContext(VerilogParser.Task_port_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tf_inout_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_inout_declaration" ):
                listener.enterTf_inout_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_inout_declaration" ):
                listener.exitTf_inout_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_inout_declaration" ):
                return visitor.visitTf_inout_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_inout_declaration(self):

        localctx = VerilogParser.Tf_inout_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 182, self.RULE_tf_inout_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1898
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,166,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1883
                self.match(VerilogParser.INOUT)
                self.state = 1885
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.REG:
                    self.state = 1884
                    self.match(VerilogParser.REG)


                self.state = 1888
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1887
                    self.match(VerilogParser.SIGNED)


                self.state = 1891
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1890
                    self.range_()


                self.state = 1893
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1894
                self.match(VerilogParser.INOUT)
                self.state = 1895
                self.task_port_type()
                self.state = 1896
                self.list_of_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Task_port_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_task_port_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_port_type" ):
                listener.enterTask_port_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_port_type" ):
                listener.exitTask_port_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_port_type" ):
                return visitor.visitTask_port_type(self)
            else:
                return visitor.visitChildren(self)




    def task_port_type(self):

        localctx = VerilogParser.Task_port_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 184, self.RULE_task_port_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1900
            _la = self._input.LA(1)
            if not(((((_la - 61)) & ~0x3f) == 0 and ((1 << (_la - 61)) & ((1 << (VerilogParser.INTEGER - 61)) | (1 << (VerilogParser.REAL - 61)) | (1 << (VerilogParser.REALTIME - 61)) | (1 << (VerilogParser.TIME - 61)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Block_item_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def list_of_block_variable_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_block_variable_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def list_of_block_real_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_block_real_identifiersContext,0)


        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def event_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Event_declarationContext,0)


        def local_parameter_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Local_parameter_declarationContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_item_declaration" ):
                listener.enterBlock_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_item_declaration" ):
                listener.exitBlock_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_item_declaration" ):
                return visitor.visitBlock_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def block_item_declaration(self):

        localctx = VerilogParser.Block_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 186, self.RULE_block_item_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1983
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,177,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1905
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1902
                    self.attribute_instance()
                    self.state = 1907
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1908
                self.match(VerilogParser.REG)
                self.state = 1910
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1909
                    self.match(VerilogParser.SIGNED)


                self.state = 1913
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 1912
                    self.range_()


                self.state = 1915
                self.list_of_block_variable_identifiers()
                self.state = 1916
                self.match(VerilogParser.SC)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1921
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1918
                    self.attribute_instance()
                    self.state = 1923
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1924
                self.match(VerilogParser.INTEGER)
                self.state = 1925
                self.list_of_block_variable_identifiers()
                self.state = 1926
                self.match(VerilogParser.SC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1931
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1928
                    self.attribute_instance()
                    self.state = 1933
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1934
                self.match(VerilogParser.TIME)
                self.state = 1935
                self.list_of_block_variable_identifiers()
                self.state = 1936
                self.match(VerilogParser.SC)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1941
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1938
                    self.attribute_instance()
                    self.state = 1943
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1944
                self.match(VerilogParser.REAL)
                self.state = 1945
                self.list_of_block_real_identifiers()
                self.state = 1946
                self.match(VerilogParser.SC)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1951
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1948
                    self.attribute_instance()
                    self.state = 1953
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1954
                self.match(VerilogParser.REALTIME)
                self.state = 1955
                self.list_of_block_real_identifiers()
                self.state = 1956
                self.match(VerilogParser.SC)
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1961
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1958
                    self.attribute_instance()
                    self.state = 1963
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1964
                self.event_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1968
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1965
                    self.attribute_instance()
                    self.state = 1970
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1971
                self.local_parameter_declaration()
                self.state = 1972
                self.match(VerilogParser.SC)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1977
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 1974
                    self.attribute_instance()
                    self.state = 1979
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1980
                self.parameter_declaration()
                self.state = 1981
                self.match(VerilogParser.SC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_block_variable_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_variable_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_variable_typeContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_variable_typeContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_block_variable_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_block_variable_identifiers" ):
                listener.enterList_of_block_variable_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_block_variable_identifiers" ):
                listener.exitList_of_block_variable_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_block_variable_identifiers" ):
                return visitor.visitList_of_block_variable_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_block_variable_identifiers(self):

        localctx = VerilogParser.List_of_block_variable_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 188, self.RULE_list_of_block_variable_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1985
            self.block_variable_type()
            self.state = 1990
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1986
                self.match(VerilogParser.CO)
                self.state = 1987
                self.block_variable_type()
                self.state = 1992
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_block_real_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_real_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_real_typeContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_real_typeContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_block_real_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_block_real_identifiers" ):
                listener.enterList_of_block_real_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_block_real_identifiers" ):
                listener.exitList_of_block_real_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_block_real_identifiers" ):
                return visitor.visitList_of_block_real_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_block_real_identifiers(self):

        localctx = VerilogParser.List_of_block_real_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 190, self.RULE_list_of_block_real_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1993
            self.block_real_type()
            self.state = 1998
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 1994
                self.match(VerilogParser.CO)
                self.state = 1995
                self.block_real_type()
                self.state = 2000
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Block_variable_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_variable_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_variable_type" ):
                listener.enterBlock_variable_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_variable_type" ):
                listener.exitBlock_variable_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_variable_type" ):
                return visitor.visitBlock_variable_type(self)
            else:
                return visitor.visitChildren(self)




    def block_variable_type(self):

        localctx = VerilogParser.Block_variable_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 192, self.RULE_block_variable_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2001
            self.variable_identifier()
            self.state = 2005
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LB:
                self.state = 2002
                self.dimension()
                self.state = 2007
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Block_real_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def real_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Real_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_real_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_real_type" ):
                listener.enterBlock_real_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_real_type" ):
                listener.exitBlock_real_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_real_type" ):
                return visitor.visitBlock_real_type(self)
            else:
                return visitor.visitChildren(self)




    def block_real_type(self):

        localctx = VerilogParser.Block_real_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 194, self.RULE_block_real_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2008
            self.real_identifier()
            self.state = 2012
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LB:
                self.state = 2009
                self.dimension()
                self.state = 2014
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Gate_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cmos_switchtype(self):
            return self.getTypedRuleContext(VerilogParser.Cmos_switchtypeContext,0)


        def cmos_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Cmos_switch_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Cmos_switch_instanceContext,i)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def delay3(self):
            return self.getTypedRuleContext(VerilogParser.Delay3Context,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def enable_gatetype(self):
            return self.getTypedRuleContext(VerilogParser.Enable_gatetypeContext,0)


        def enable_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Enable_gate_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Enable_gate_instanceContext,i)


        def drive_strength(self):
            return self.getTypedRuleContext(VerilogParser.Drive_strengthContext,0)


        def mos_switchtype(self):
            return self.getTypedRuleContext(VerilogParser.Mos_switchtypeContext,0)


        def mos_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Mos_switch_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Mos_switch_instanceContext,i)


        def n_input_gatetype(self):
            return self.getTypedRuleContext(VerilogParser.N_input_gatetypeContext,0)


        def n_input_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.N_input_gate_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.N_input_gate_instanceContext,i)


        def delay2(self):
            return self.getTypedRuleContext(VerilogParser.Delay2Context,0)


        def n_output_gatetype(self):
            return self.getTypedRuleContext(VerilogParser.N_output_gatetypeContext,0)


        def n_output_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.N_output_gate_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.N_output_gate_instanceContext,i)


        def pass_en_switchtype(self):
            return self.getTypedRuleContext(VerilogParser.Pass_en_switchtypeContext,0)


        def pass_enable_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Pass_enable_switch_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Pass_enable_switch_instanceContext,i)


        def pass_switchtype(self):
            return self.getTypedRuleContext(VerilogParser.Pass_switchtypeContext,0)


        def pass_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Pass_switch_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Pass_switch_instanceContext,i)


        def PULLDOWN(self):
            return self.getToken(VerilogParser.PULLDOWN, 0)

        def pull_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Pull_gate_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Pull_gate_instanceContext,i)


        def pulldown_strength(self):
            return self.getTypedRuleContext(VerilogParser.Pulldown_strengthContext,0)


        def PULLUP(self):
            return self.getToken(VerilogParser.PULLUP, 0)

        def pullup_strength(self):
            return self.getTypedRuleContext(VerilogParser.Pullup_strengthContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_gate_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGate_instantiation" ):
                listener.enterGate_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGate_instantiation" ):
                listener.exitGate_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGate_instantiation" ):
                return visitor.visitGate_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def gate_instantiation(self):

        localctx = VerilogParser.Gate_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 196, self.RULE_gate_instantiation)
        self._la = 0 # Token type
        try:
            self.state = 2147
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.CMOS, VerilogParser.RCMOS]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2015
                self.cmos_switchtype()
                self.state = 2017
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 2016
                    self.delay3()


                self.state = 2019
                self.cmos_switch_instance()
                self.state = 2024
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2020
                    self.match(VerilogParser.CO)
                    self.state = 2021
                    self.cmos_switch_instance()
                    self.state = 2026
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2027
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.BUFIFONE, VerilogParser.BUFIFZERO, VerilogParser.NOTIFONE, VerilogParser.NOTIFZERO]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2029
                self.enable_gatetype()
                self.state = 2031
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,184,self._ctx)
                if la_ == 1:
                    self.state = 2030
                    self.drive_strength()


                self.state = 2034
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 2033
                    self.delay3()


                self.state = 2036
                self.enable_gate_instance()
                self.state = 2041
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2037
                    self.match(VerilogParser.CO)
                    self.state = 2038
                    self.enable_gate_instance()
                    self.state = 2043
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2044
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.NMOS, VerilogParser.PMOS, VerilogParser.RNMOS, VerilogParser.RPMOS]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2046
                self.mos_switchtype()
                self.state = 2048
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 2047
                    self.delay3()


                self.state = 2050
                self.mos_switch_instance()
                self.state = 2055
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2051
                    self.match(VerilogParser.CO)
                    self.state = 2052
                    self.mos_switch_instance()
                    self.state = 2057
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2058
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.AND, VerilogParser.NAND, VerilogParser.NOR, VerilogParser.OR, VerilogParser.XNOR, VerilogParser.XOR]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2060
                self.n_input_gatetype()
                self.state = 2062
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,189,self._ctx)
                if la_ == 1:
                    self.state = 2061
                    self.drive_strength()


                self.state = 2065
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 2064
                    self.delay2()


                self.state = 2067
                self.n_input_gate_instance()
                self.state = 2072
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2068
                    self.match(VerilogParser.CO)
                    self.state = 2069
                    self.n_input_gate_instance()
                    self.state = 2074
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2075
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.BUF, VerilogParser.NOT]:
                self.enterOuterAlt(localctx, 5)
                self.state = 2077
                self.n_output_gatetype()
                self.state = 2079
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,192,self._ctx)
                if la_ == 1:
                    self.state = 2078
                    self.drive_strength()


                self.state = 2082
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 2081
                    self.delay2()


                self.state = 2084
                self.n_output_gate_instance()
                self.state = 2089
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2085
                    self.match(VerilogParser.CO)
                    self.state = 2086
                    self.n_output_gate_instance()
                    self.state = 2091
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2092
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.RTRANIFONE, VerilogParser.RTRANIFZERO, VerilogParser.TRANIFONE, VerilogParser.TRANIFZERO]:
                self.enterOuterAlt(localctx, 6)
                self.state = 2094
                self.pass_en_switchtype()
                self.state = 2096
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HA:
                    self.state = 2095
                    self.delay2()


                self.state = 2098
                self.pass_enable_switch_instance()
                self.state = 2103
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2099
                    self.match(VerilogParser.CO)
                    self.state = 2100
                    self.pass_enable_switch_instance()
                    self.state = 2105
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2106
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.RTRAN, VerilogParser.TRAN]:
                self.enterOuterAlt(localctx, 7)
                self.state = 2108
                self.pass_switchtype()
                self.state = 2109
                self.pass_switch_instance()
                self.state = 2114
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2110
                    self.match(VerilogParser.CO)
                    self.state = 2111
                    self.pass_switch_instance()
                    self.state = 2116
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2117
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.PULLDOWN]:
                self.enterOuterAlt(localctx, 8)
                self.state = 2119
                self.match(VerilogParser.PULLDOWN)
                self.state = 2121
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,198,self._ctx)
                if la_ == 1:
                    self.state = 2120
                    self.pulldown_strength()


                self.state = 2123
                self.pull_gate_instance()
                self.state = 2128
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2124
                    self.match(VerilogParser.CO)
                    self.state = 2125
                    self.pull_gate_instance()
                    self.state = 2130
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2131
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.PULLUP]:
                self.enterOuterAlt(localctx, 9)
                self.state = 2133
                self.match(VerilogParser.PULLUP)
                self.state = 2135
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,200,self._ctx)
                if la_ == 1:
                    self.state = 2134
                    self.pullup_strength()


                self.state = 2137
                self.pull_gate_instance()
                self.state = 2142
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2138
                    self.match(VerilogParser.CO)
                    self.state = 2139
                    self.pull_gate_instance()
                    self.state = 2144
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2145
                self.match(VerilogParser.SC)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Cmos_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def input_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Input_terminalContext,0)


        def ncontrol_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Ncontrol_terminalContext,0)


        def pcontrol_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Pcontrol_terminalContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_cmos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switch_instance" ):
                listener.enterCmos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switch_instance" ):
                listener.exitCmos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switch_instance" ):
                return visitor.visitCmos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switch_instance(self):

        localctx = VerilogParser.Cmos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 198, self.RULE_cmos_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2150
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2149
                self.name_of_gate_instance()


            self.state = 2152
            self.match(VerilogParser.LP)
            self.state = 2153
            self.output_terminal()
            self.state = 2154
            self.match(VerilogParser.CO)
            self.state = 2155
            self.input_terminal()
            self.state = 2156
            self.match(VerilogParser.CO)
            self.state = 2157
            self.ncontrol_terminal()
            self.state = 2158
            self.match(VerilogParser.CO)
            self.state = 2159
            self.pcontrol_terminal()
            self.state = 2160
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Enable_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def input_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Input_terminalContext,0)


        def enable_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Enable_terminalContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_enable_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gate_instance" ):
                listener.enterEnable_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gate_instance" ):
                listener.exitEnable_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gate_instance" ):
                return visitor.visitEnable_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def enable_gate_instance(self):

        localctx = VerilogParser.Enable_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 200, self.RULE_enable_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2163
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2162
                self.name_of_gate_instance()


            self.state = 2165
            self.match(VerilogParser.LP)
            self.state = 2166
            self.output_terminal()
            self.state = 2167
            self.match(VerilogParser.CO)
            self.state = 2168
            self.input_terminal()
            self.state = 2169
            self.match(VerilogParser.CO)
            self.state = 2170
            self.enable_terminal()
            self.state = 2171
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Mos_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def input_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Input_terminalContext,0)


        def enable_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Enable_terminalContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_mos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switch_instance" ):
                listener.enterMos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switch_instance" ):
                listener.exitMos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switch_instance" ):
                return visitor.visitMos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def mos_switch_instance(self):

        localctx = VerilogParser.Mos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 202, self.RULE_mos_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2174
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2173
                self.name_of_gate_instance()


            self.state = 2176
            self.match(VerilogParser.LP)
            self.state = 2177
            self.output_terminal()
            self.state = 2178
            self.match(VerilogParser.CO)
            self.state = 2179
            self.input_terminal()
            self.state = 2180
            self.match(VerilogParser.CO)
            self.state = 2181
            self.enable_terminal()
            self.state = 2182
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class N_input_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def input_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Input_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Input_terminalContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_n_input_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gate_instance" ):
                listener.enterN_input_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gate_instance" ):
                listener.exitN_input_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gate_instance" ):
                return visitor.visitN_input_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gate_instance(self):

        localctx = VerilogParser.N_input_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 204, self.RULE_n_input_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2185
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2184
                self.name_of_gate_instance()


            self.state = 2187
            self.match(VerilogParser.LP)
            self.state = 2188
            self.output_terminal()
            self.state = 2189
            self.match(VerilogParser.CO)
            self.state = 2190
            self.input_terminal()
            self.state = 2195
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 2191
                self.match(VerilogParser.CO)
                self.state = 2192
                self.input_terminal()
                self.state = 2197
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2198
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class N_output_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def output_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Output_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Output_terminalContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def input_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Input_terminalContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_n_output_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gate_instance" ):
                listener.enterN_output_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gate_instance" ):
                listener.exitN_output_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gate_instance" ):
                return visitor.visitN_output_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gate_instance(self):

        localctx = VerilogParser.N_output_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 206, self.RULE_n_output_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2201
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2200
                self.name_of_gate_instance()


            self.state = 2203
            self.match(VerilogParser.LP)
            self.state = 2204
            self.output_terminal()
            self.state = 2209
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,209,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 2205
                    self.match(VerilogParser.CO)
                    self.state = 2206
                    self.output_terminal() 
                self.state = 2211
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,209,self._ctx)

            self.state = 2212
            self.match(VerilogParser.CO)
            self.state = 2213
            self.input_terminal()
            self.state = 2214
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pass_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def inout_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Inout_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Inout_terminalContext,i)


        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pass_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switch_instance" ):
                listener.enterPass_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switch_instance" ):
                listener.exitPass_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switch_instance" ):
                return visitor.visitPass_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def pass_switch_instance(self):

        localctx = VerilogParser.Pass_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 208, self.RULE_pass_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2217
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2216
                self.name_of_gate_instance()


            self.state = 2219
            self.match(VerilogParser.LP)
            self.state = 2220
            self.inout_terminal()
            self.state = 2221
            self.match(VerilogParser.CO)
            self.state = 2222
            self.inout_terminal()
            self.state = 2223
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pass_enable_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def inout_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Inout_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Inout_terminalContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def enable_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Enable_terminalContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pass_enable_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_enable_switch_instance" ):
                listener.enterPass_enable_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_enable_switch_instance" ):
                listener.exitPass_enable_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_enable_switch_instance" ):
                return visitor.visitPass_enable_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def pass_enable_switch_instance(self):

        localctx = VerilogParser.Pass_enable_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 210, self.RULE_pass_enable_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2226
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2225
                self.name_of_gate_instance()


            self.state = 2228
            self.match(VerilogParser.LP)
            self.state = 2229
            self.inout_terminal()
            self.state = 2230
            self.match(VerilogParser.CO)
            self.state = 2231
            self.inout_terminal()
            self.state = 2232
            self.match(VerilogParser.CO)
            self.state = 2233
            self.enable_terminal()
            self.state = 2234
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pull_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pull_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPull_gate_instance" ):
                listener.enterPull_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPull_gate_instance" ):
                listener.exitPull_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPull_gate_instance" ):
                return visitor.visitPull_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def pull_gate_instance(self):

        localctx = VerilogParser.Pull_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 212, self.RULE_pull_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2237
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2236
                self.name_of_gate_instance()


            self.state = 2239
            self.match(VerilogParser.LP)
            self.state = 2240
            self.output_terminal()
            self.state = 2241
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Name_of_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def gate_instance_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Gate_instance_identifierContext,0)


        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_name_of_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterName_of_gate_instance" ):
                listener.enterName_of_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitName_of_gate_instance" ):
                listener.exitName_of_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitName_of_gate_instance" ):
                return visitor.visitName_of_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def name_of_gate_instance(self):

        localctx = VerilogParser.Name_of_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 214, self.RULE_name_of_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2243
            self.gate_instance_identifier()
            self.state = 2245
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 2244
                self.range_()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pulldown_strengthContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def strength0(self):
            return self.getTypedRuleContext(VerilogParser.Strength0Context,0)


        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def strength1(self):
            return self.getTypedRuleContext(VerilogParser.Strength1Context,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pulldown_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulldown_strength" ):
                listener.enterPulldown_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulldown_strength" ):
                listener.exitPulldown_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulldown_strength" ):
                return visitor.visitPulldown_strength(self)
            else:
                return visitor.visitChildren(self)




    def pulldown_strength(self):

        localctx = VerilogParser.Pulldown_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 216, self.RULE_pulldown_strength)
        try:
            self.state = 2263
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,214,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2247
                self.match(VerilogParser.LP)
                self.state = 2248
                self.strength0()
                self.state = 2249
                self.match(VerilogParser.CO)
                self.state = 2250
                self.strength1()
                self.state = 2251
                self.match(VerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2253
                self.match(VerilogParser.LP)
                self.state = 2254
                self.strength1()
                self.state = 2255
                self.match(VerilogParser.CO)
                self.state = 2256
                self.strength0()
                self.state = 2257
                self.match(VerilogParser.RP)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2259
                self.match(VerilogParser.LP)
                self.state = 2260
                self.strength0()
                self.state = 2261
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pullup_strengthContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def strength0(self):
            return self.getTypedRuleContext(VerilogParser.Strength0Context,0)


        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def strength1(self):
            return self.getTypedRuleContext(VerilogParser.Strength1Context,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pullup_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPullup_strength" ):
                listener.enterPullup_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPullup_strength" ):
                listener.exitPullup_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPullup_strength" ):
                return visitor.visitPullup_strength(self)
            else:
                return visitor.visitChildren(self)




    def pullup_strength(self):

        localctx = VerilogParser.Pullup_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 218, self.RULE_pullup_strength)
        try:
            self.state = 2281
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,215,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2265
                self.match(VerilogParser.LP)
                self.state = 2266
                self.strength0()
                self.state = 2267
                self.match(VerilogParser.CO)
                self.state = 2268
                self.strength1()
                self.state = 2269
                self.match(VerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2271
                self.match(VerilogParser.LP)
                self.state = 2272
                self.strength1()
                self.state = 2273
                self.match(VerilogParser.CO)
                self.state = 2274
                self.strength0()
                self.state = 2275
                self.match(VerilogParser.RP)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2277
                self.match(VerilogParser.LP)
                self.state = 2278
                self.strength1()
                self.state = 2279
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Enable_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_enable_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_terminal" ):
                listener.enterEnable_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_terminal" ):
                listener.exitEnable_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_terminal" ):
                return visitor.visitEnable_terminal(self)
            else:
                return visitor.visitChildren(self)




    def enable_terminal(self):

        localctx = VerilogParser.Enable_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 220, self.RULE_enable_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2283
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Inout_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_inout_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_terminal" ):
                listener.enterInout_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_terminal" ):
                listener.exitInout_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_terminal" ):
                return visitor.visitInout_terminal(self)
            else:
                return visitor.visitChildren(self)




    def inout_terminal(self):

        localctx = VerilogParser.Inout_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 222, self.RULE_inout_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2285
            self.net_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Input_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_input_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_terminal" ):
                listener.enterInput_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_terminal" ):
                listener.exitInput_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_terminal" ):
                return visitor.visitInput_terminal(self)
            else:
                return visitor.visitChildren(self)




    def input_terminal(self):

        localctx = VerilogParser.Input_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 224, self.RULE_input_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2287
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Ncontrol_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_ncontrol_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNcontrol_terminal" ):
                listener.enterNcontrol_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNcontrol_terminal" ):
                listener.exitNcontrol_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNcontrol_terminal" ):
                return visitor.visitNcontrol_terminal(self)
            else:
                return visitor.visitChildren(self)




    def ncontrol_terminal(self):

        localctx = VerilogParser.Ncontrol_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 226, self.RULE_ncontrol_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2289
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Output_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_output_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_terminal" ):
                listener.enterOutput_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_terminal" ):
                listener.exitOutput_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_terminal" ):
                return visitor.visitOutput_terminal(self)
            else:
                return visitor.visitChildren(self)




    def output_terminal(self):

        localctx = VerilogParser.Output_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 228, self.RULE_output_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2291
            self.net_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pcontrol_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pcontrol_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPcontrol_terminal" ):
                listener.enterPcontrol_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPcontrol_terminal" ):
                listener.exitPcontrol_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPcontrol_terminal" ):
                return visitor.visitPcontrol_terminal(self)
            else:
                return visitor.visitChildren(self)




    def pcontrol_terminal(self):

        localctx = VerilogParser.Pcontrol_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 230, self.RULE_pcontrol_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2293
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Cmos_switchtypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CMOS(self):
            return self.getToken(VerilogParser.CMOS, 0)

        def RCMOS(self):
            return self.getToken(VerilogParser.RCMOS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_cmos_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switchtype" ):
                listener.enterCmos_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switchtype" ):
                listener.exitCmos_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switchtype" ):
                return visitor.visitCmos_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switchtype(self):

        localctx = VerilogParser.Cmos_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 232, self.RULE_cmos_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2295
            _la = self._input.LA(1)
            if not(_la==VerilogParser.CMOS or _la==VerilogParser.RCMOS):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Enable_gatetypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def BUFIFZERO(self):
            return self.getToken(VerilogParser.BUFIFZERO, 0)

        def BUFIFONE(self):
            return self.getToken(VerilogParser.BUFIFONE, 0)

        def NOTIFZERO(self):
            return self.getToken(VerilogParser.NOTIFZERO, 0)

        def NOTIFONE(self):
            return self.getToken(VerilogParser.NOTIFONE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_enable_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gatetype" ):
                listener.enterEnable_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gatetype" ):
                listener.exitEnable_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gatetype" ):
                return visitor.visitEnable_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def enable_gatetype(self):

        localctx = VerilogParser.Enable_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 234, self.RULE_enable_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2297
            _la = self._input.LA(1)
            if not(_la==VerilogParser.BUFIFONE or _la==VerilogParser.BUFIFZERO or _la==VerilogParser.NOTIFONE or _la==VerilogParser.NOTIFZERO):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Mos_switchtypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def NMOS(self):
            return self.getToken(VerilogParser.NMOS, 0)

        def PMOS(self):
            return self.getToken(VerilogParser.PMOS, 0)

        def RNMOS(self):
            return self.getToken(VerilogParser.RNMOS, 0)

        def RPMOS(self):
            return self.getToken(VerilogParser.RPMOS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_mos_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switchtype" ):
                listener.enterMos_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switchtype" ):
                listener.exitMos_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switchtype" ):
                return visitor.visitMos_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def mos_switchtype(self):

        localctx = VerilogParser.Mos_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 236, self.RULE_mos_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2299
            _la = self._input.LA(1)
            if not(((((_la - 73)) & ~0x3f) == 0 and ((1 << (_la - 73)) & ((1 << (VerilogParser.NMOS - 73)) | (1 << (VerilogParser.PMOS - 73)) | (1 << (VerilogParser.RNMOS - 73)) | (1 << (VerilogParser.RPMOS - 73)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class N_input_gatetypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def AND(self):
            return self.getToken(VerilogParser.AND, 0)

        def NAND(self):
            return self.getToken(VerilogParser.NAND, 0)

        def OR(self):
            return self.getToken(VerilogParser.OR, 0)

        def NOR(self):
            return self.getToken(VerilogParser.NOR, 0)

        def XOR(self):
            return self.getToken(VerilogParser.XOR, 0)

        def XNOR(self):
            return self.getToken(VerilogParser.XNOR, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_n_input_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gatetype" ):
                listener.enterN_input_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gatetype" ):
                listener.exitN_input_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gatetype" ):
                return visitor.visitN_input_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gatetype(self):

        localctx = VerilogParser.N_input_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 238, self.RULE_n_input_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2301
            _la = self._input.LA(1)
            if not(_la==VerilogParser.AND or ((((_la - 71)) & ~0x3f) == 0 and ((1 << (_la - 71)) & ((1 << (VerilogParser.NAND - 71)) | (1 << (VerilogParser.NOR - 71)) | (1 << (VerilogParser.OR - 71)))) != 0) or _la==VerilogParser.XNOR or _la==VerilogParser.XOR):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class N_output_gatetypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def BUF(self):
            return self.getToken(VerilogParser.BUF, 0)

        def NOT(self):
            return self.getToken(VerilogParser.NOT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_n_output_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gatetype" ):
                listener.enterN_output_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gatetype" ):
                listener.exitN_output_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gatetype" ):
                return visitor.visitN_output_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gatetype(self):

        localctx = VerilogParser.N_output_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 240, self.RULE_n_output_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2303
            _la = self._input.LA(1)
            if not(_la==VerilogParser.BUF or _la==VerilogParser.NOT):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pass_en_switchtypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TRANIFZERO(self):
            return self.getToken(VerilogParser.TRANIFZERO, 0)

        def TRANIFONE(self):
            return self.getToken(VerilogParser.TRANIFONE, 0)

        def RTRANIFONE(self):
            return self.getToken(VerilogParser.RTRANIFONE, 0)

        def RTRANIFZERO(self):
            return self.getToken(VerilogParser.RTRANIFZERO, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pass_en_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_en_switchtype" ):
                listener.enterPass_en_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_en_switchtype" ):
                listener.exitPass_en_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_en_switchtype" ):
                return visitor.visitPass_en_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def pass_en_switchtype(self):

        localctx = VerilogParser.Pass_en_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 242, self.RULE_pass_en_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2305
            _la = self._input.LA(1)
            if not(((((_la - 101)) & ~0x3f) == 0 and ((1 << (_la - 101)) & ((1 << (VerilogParser.RTRANIFONE - 101)) | (1 << (VerilogParser.RTRANIFZERO - 101)) | (1 << (VerilogParser.TRANIFONE - 101)) | (1 << (VerilogParser.TRANIFZERO - 101)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pass_switchtypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TRAN(self):
            return self.getToken(VerilogParser.TRAN, 0)

        def RTRAN(self):
            return self.getToken(VerilogParser.RTRAN, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pass_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switchtype" ):
                listener.enterPass_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switchtype" ):
                listener.exitPass_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switchtype" ):
                return visitor.visitPass_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def pass_switchtype(self):

        localctx = VerilogParser.Pass_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 244, self.RULE_pass_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2307
            _la = self._input.LA(1)
            if not(_la==VerilogParser.RTRAN or _la==VerilogParser.TRAN):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Module_identifierContext,0)


        def module_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_instanceContext,i)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def parameter_value_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_value_assignmentContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instantiation" ):
                listener.enterModule_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instantiation" ):
                listener.exitModule_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instantiation" ):
                return visitor.visitModule_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def module_instantiation(self):

        localctx = VerilogParser.Module_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 246, self.RULE_module_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2309
            self.module_identifier()
            self.state = 2311
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.HA:
                self.state = 2310
                self.parameter_value_assignment()


            self.state = 2313
            self.module_instance()
            self.state = 2318
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 2314
                self.match(VerilogParser.CO)
                self.state = 2315
                self.module_instance()
                self.state = 2320
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2321
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Parameter_value_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HA(self):
            return self.getToken(VerilogParser.HA, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def list_of_parameter_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_parameter_assignmentsContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_value_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_value_assignment" ):
                listener.enterParameter_value_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_value_assignment" ):
                listener.exitParameter_value_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_value_assignment" ):
                return visitor.visitParameter_value_assignment(self)
            else:
                return visitor.visitChildren(self)




    def parameter_value_assignment(self):

        localctx = VerilogParser.Parameter_value_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 248, self.RULE_parameter_value_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2323
            self.match(VerilogParser.HA)
            self.state = 2324
            self.match(VerilogParser.LP)
            self.state = 2325
            self.list_of_parameter_assignments()
            self.state = 2326
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_parameter_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ordered_parameter_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Ordered_parameter_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Ordered_parameter_assignmentContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def named_parameter_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Named_parameter_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Named_parameter_assignmentContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_parameter_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_parameter_assignments" ):
                listener.enterList_of_parameter_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_parameter_assignments" ):
                listener.exitList_of_parameter_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_parameter_assignments" ):
                return visitor.visitList_of_parameter_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_parameter_assignments(self):

        localctx = VerilogParser.List_of_parameter_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 250, self.RULE_list_of_parameter_assignments)
        self._la = 0 # Token type
        try:
            self.state = 2344
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.AM, VerilogParser.CA, VerilogParser.CATI, VerilogParser.EM, VerilogParser.LC, VerilogParser.LP, VerilogParser.MI, VerilogParser.PL, VerilogParser.TI, VerilogParser.TIAM, VerilogParser.TICA, VerilogParser.TIVL, VerilogParser.VL, VerilogParser.BINARY_BASE, VerilogParser.DECIMAL_BASE, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.EXPONENTIAL_NUMBER, VerilogParser.FIXED_POINT_NUMBER, VerilogParser.HEX_BASE, VerilogParser.OCTAL_BASE, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.STRING, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.UNSIGNED_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2328
                self.ordered_parameter_assignment()
                self.state = 2333
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2329
                    self.match(VerilogParser.CO)
                    self.state = 2330
                    self.ordered_parameter_assignment()
                    self.state = 2335
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            elif token in [VerilogParser.DT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2336
                self.named_parameter_assignment()
                self.state = 2341
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2337
                    self.match(VerilogParser.CO)
                    self.state = 2338
                    self.named_parameter_assignment()
                    self.state = 2343
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Ordered_parameter_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_ordered_parameter_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOrdered_parameter_assignment" ):
                listener.enterOrdered_parameter_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOrdered_parameter_assignment" ):
                listener.exitOrdered_parameter_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOrdered_parameter_assignment" ):
                return visitor.visitOrdered_parameter_assignment(self)
            else:
                return visitor.visitChildren(self)




    def ordered_parameter_assignment(self):

        localctx = VerilogParser.Ordered_parameter_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 252, self.RULE_ordered_parameter_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2346
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Named_parameter_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DT(self):
            return self.getToken(VerilogParser.DT, 0)

        def parameter_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_identifierContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_named_parameter_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNamed_parameter_assignment" ):
                listener.enterNamed_parameter_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNamed_parameter_assignment" ):
                listener.exitNamed_parameter_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNamed_parameter_assignment" ):
                return visitor.visitNamed_parameter_assignment(self)
            else:
                return visitor.visitChildren(self)




    def named_parameter_assignment(self):

        localctx = VerilogParser.Named_parameter_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 254, self.RULE_named_parameter_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2348
            self.match(VerilogParser.DT)
            self.state = 2349
            self.parameter_identifier()
            self.state = 2350
            self.match(VerilogParser.LP)
            self.state = 2352
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 2351
                self.mintypmax_expression()


            self.state = 2354
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def name_of_module_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_module_instanceContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def list_of_port_connections(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_connectionsContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instance" ):
                listener.enterModule_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instance" ):
                listener.exitModule_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instance" ):
                return visitor.visitModule_instance(self)
            else:
                return visitor.visitChildren(self)




    def module_instance(self):

        localctx = VerilogParser.Module_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 256, self.RULE_module_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2356
            self.name_of_module_instance()
            self.state = 2357
            self.match(VerilogParser.LP)
            self.state = 2358
            self.list_of_port_connections()
            self.state = 2359
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Name_of_module_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_instance_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Module_instance_identifierContext,0)


        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_name_of_module_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterName_of_module_instance" ):
                listener.enterName_of_module_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitName_of_module_instance" ):
                listener.exitName_of_module_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitName_of_module_instance" ):
                return visitor.visitName_of_module_instance(self)
            else:
                return visitor.visitChildren(self)




    def name_of_module_instance(self):

        localctx = VerilogParser.Name_of_module_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 258, self.RULE_name_of_module_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2361
            self.module_instance_identifier()
            self.state = 2363
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 2362
                self.range_()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_port_connectionsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ordered_port_connection(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Ordered_port_connectionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Ordered_port_connectionContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def named_port_connection(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Named_port_connectionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Named_port_connectionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_port_connections

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_connections" ):
                listener.enterList_of_port_connections(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_connections" ):
                listener.exitList_of_port_connections(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_connections" ):
                return visitor.visitList_of_port_connections(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_connections(self):

        localctx = VerilogParser.List_of_port_connectionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 260, self.RULE_list_of_port_connections)
        self._la = 0 # Token type
        try:
            self.state = 2381
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,225,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2365
                self.ordered_port_connection()
                self.state = 2370
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2366
                    self.match(VerilogParser.CO)
                    self.state = 2367
                    self.ordered_port_connection()
                    self.state = 2372
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2373
                self.named_port_connection()
                self.state = 2378
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2374
                    self.match(VerilogParser.CO)
                    self.state = 2375
                    self.named_port_connection()
                    self.state = 2380
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Ordered_port_connectionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_ordered_port_connection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOrdered_port_connection" ):
                listener.enterOrdered_port_connection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOrdered_port_connection" ):
                listener.exitOrdered_port_connection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOrdered_port_connection" ):
                return visitor.visitOrdered_port_connection(self)
            else:
                return visitor.visitChildren(self)




    def ordered_port_connection(self):

        localctx = VerilogParser.Ordered_port_connectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 262, self.RULE_ordered_port_connection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2386
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,226,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 2383
                    self.attribute_instance() 
                self.state = 2388
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,226,self._ctx)

            self.state = 2390
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 2389
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Named_port_connectionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DT(self):
            return self.getToken(VerilogParser.DT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_named_port_connection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNamed_port_connection" ):
                listener.enterNamed_port_connection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNamed_port_connection" ):
                listener.exitNamed_port_connection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNamed_port_connection" ):
                return visitor.visitNamed_port_connection(self)
            else:
                return visitor.visitChildren(self)




    def named_port_connection(self):

        localctx = VerilogParser.Named_port_connectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 264, self.RULE_named_port_connection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2395
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LP:
                self.state = 2392
                self.attribute_instance()
                self.state = 2397
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2398
            self.match(VerilogParser.DT)
            self.state = 2399
            self.port_identifier()
            self.state = 2400
            self.match(VerilogParser.LP)
            self.state = 2402
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 2401
                self.expression(0)


            self.state = 2404
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Generate_regionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GENERATE(self):
            return self.getToken(VerilogParser.GENERATE, 0)

        def ENDGENERATE(self):
            return self.getToken(VerilogParser.ENDGENERATE, 0)

        def module_or_generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_or_generate_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_or_generate_itemContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_generate_region

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_region" ):
                listener.enterGenerate_region(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_region" ):
                listener.exitGenerate_region(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_region" ):
                return visitor.visitGenerate_region(self)
            else:
                return visitor.visitChildren(self)




    def generate_region(self):

        localctx = VerilogParser.Generate_regionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 266, self.RULE_generate_region)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2406
            self.match(VerilogParser.GENERATE)
            self.state = 2410
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ALWAYS) | (1 << VerilogParser.AND) | (1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BUF) | (1 << VerilogParser.BUFIFONE) | (1 << VerilogParser.BUFIFZERO) | (1 << VerilogParser.CASE) | (1 << VerilogParser.CMOS) | (1 << VerilogParser.DEFPARAM) | (1 << VerilogParser.EVENT) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FUNCTION) | (1 << VerilogParser.GENVAR) | (1 << VerilogParser.IF) | (1 << VerilogParser.INITIAL) | (1 << VerilogParser.INTEGER))) != 0) or ((((_la - 66)) & ~0x3f) == 0 and ((1 << (_la - 66)) & ((1 << (VerilogParser.LOCALPARAM - 66)) | (1 << (VerilogParser.NAND - 66)) | (1 << (VerilogParser.NMOS - 66)) | (1 << (VerilogParser.NOR - 66)) | (1 << (VerilogParser.NOT - 66)) | (1 << (VerilogParser.NOTIFONE - 66)) | (1 << (VerilogParser.NOTIFZERO - 66)) | (1 << (VerilogParser.OR - 66)) | (1 << (VerilogParser.PMOS - 66)) | (1 << (VerilogParser.PULLDOWN - 66)) | (1 << (VerilogParser.PULLUP - 66)) | (1 << (VerilogParser.RCMOS - 66)) | (1 << (VerilogParser.REAL - 66)) | (1 << (VerilogParser.REALTIME - 66)) | (1 << (VerilogParser.REG - 66)) | (1 << (VerilogParser.RNMOS - 66)) | (1 << (VerilogParser.RPMOS - 66)) | (1 << (VerilogParser.RTRAN - 66)) | (1 << (VerilogParser.RTRANIFONE - 66)) | (1 << (VerilogParser.RTRANIFZERO - 66)) | (1 << (VerilogParser.SUPPLYONE - 66)) | (1 << (VerilogParser.SUPPLYZERO - 66)) | (1 << (VerilogParser.TASK - 66)) | (1 << (VerilogParser.TIME - 66)) | (1 << (VerilogParser.TRAN - 66)) | (1 << (VerilogParser.TRANIFONE - 66)) | (1 << (VerilogParser.TRANIFZERO - 66)) | (1 << (VerilogParser.TRI - 66)) | (1 << (VerilogParser.TRIAND - 66)) | (1 << (VerilogParser.TRIONE - 66)) | (1 << (VerilogParser.TRIOR - 66)) | (1 << (VerilogParser.TRIREG - 66)) | (1 << (VerilogParser.TRIZERO - 66)) | (1 << (VerilogParser.UWIRE - 66)) | (1 << (VerilogParser.WAND - 66)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (VerilogParser.WIRE - 133)) | (1 << (VerilogParser.WOR - 133)) | (1 << (VerilogParser.XNOR - 133)) | (1 << (VerilogParser.XOR - 133)) | (1 << (VerilogParser.LP - 133)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 133)))) != 0) or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2407
                self.module_or_generate_item()
                self.state = 2412
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2413
            self.match(VerilogParser.ENDGENERATE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Genvar_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GENVAR(self):
            return self.getToken(VerilogParser.GENVAR, 0)

        def list_of_genvar_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_genvar_identifiersContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_declaration" ):
                listener.enterGenvar_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_declaration" ):
                listener.exitGenvar_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_declaration" ):
                return visitor.visitGenvar_declaration(self)
            else:
                return visitor.visitChildren(self)




    def genvar_declaration(self):

        localctx = VerilogParser.Genvar_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 268, self.RULE_genvar_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2415
            self.match(VerilogParser.GENVAR)
            self.state = 2416
            self.list_of_genvar_identifiers()
            self.state = 2417
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_genvar_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Genvar_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Genvar_identifierContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_genvar_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_genvar_identifiers" ):
                listener.enterList_of_genvar_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_genvar_identifiers" ):
                listener.exitList_of_genvar_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_genvar_identifiers" ):
                return visitor.visitList_of_genvar_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_genvar_identifiers(self):

        localctx = VerilogParser.List_of_genvar_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 270, self.RULE_list_of_genvar_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2419
            self.genvar_identifier()
            self.state = 2424
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 2420
                self.match(VerilogParser.CO)
                self.state = 2421
                self.genvar_identifier()
                self.state = 2426
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Loop_generate_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FOR(self):
            return self.getToken(VerilogParser.FOR, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def genvar_initialization(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_initializationContext,0)


        def SC(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.SC)
            else:
                return self.getToken(VerilogParser.SC, i)

        def genvar_expression(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_expressionContext,0)


        def genvar_iteration(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_iterationContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def generate_block(self):
            return self.getTypedRuleContext(VerilogParser.Generate_blockContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_loop_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_generate_construct" ):
                listener.enterLoop_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_generate_construct" ):
                listener.exitLoop_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_generate_construct" ):
                return visitor.visitLoop_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def loop_generate_construct(self):

        localctx = VerilogParser.Loop_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 272, self.RULE_loop_generate_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2427
            self.match(VerilogParser.FOR)
            self.state = 2428
            self.match(VerilogParser.LP)
            self.state = 2429
            self.genvar_initialization()
            self.state = 2430
            self.match(VerilogParser.SC)
            self.state = 2431
            self.genvar_expression()
            self.state = 2432
            self.match(VerilogParser.SC)
            self.state = 2433
            self.genvar_iteration()
            self.state = 2434
            self.match(VerilogParser.RP)
            self.state = 2435
            self.generate_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Genvar_initializationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_identifierContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_initialization

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_initialization" ):
                listener.enterGenvar_initialization(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_initialization" ):
                listener.exitGenvar_initialization(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_initialization" ):
                return visitor.visitGenvar_initialization(self)
            else:
                return visitor.visitChildren(self)




    def genvar_initialization(self):

        localctx = VerilogParser.Genvar_initializationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 274, self.RULE_genvar_initialization)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2437
            self.genvar_identifier()
            self.state = 2438
            self.match(VerilogParser.EQ)
            self.state = 2439
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Genvar_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_expression" ):
                listener.enterGenvar_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_expression" ):
                listener.exitGenvar_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_expression" ):
                return visitor.visitGenvar_expression(self)
            else:
                return visitor.visitChildren(self)




    def genvar_expression(self):

        localctx = VerilogParser.Genvar_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 276, self.RULE_genvar_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2441
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Genvar_iterationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_identifierContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def genvar_expression(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_iteration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_iteration" ):
                listener.enterGenvar_iteration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_iteration" ):
                listener.exitGenvar_iteration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_iteration" ):
                return visitor.visitGenvar_iteration(self)
            else:
                return visitor.visitChildren(self)




    def genvar_iteration(self):

        localctx = VerilogParser.Genvar_iterationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 278, self.RULE_genvar_iteration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2443
            self.genvar_identifier()
            self.state = 2444
            self.match(VerilogParser.EQ)
            self.state = 2445
            self.genvar_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Conditional_generate_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def if_generate_construct(self):
            return self.getTypedRuleContext(VerilogParser.If_generate_constructContext,0)


        def case_generate_construct(self):
            return self.getTypedRuleContext(VerilogParser.Case_generate_constructContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_conditional_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConditional_generate_construct" ):
                listener.enterConditional_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConditional_generate_construct" ):
                listener.exitConditional_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConditional_generate_construct" ):
                return visitor.visitConditional_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def conditional_generate_construct(self):

        localctx = VerilogParser.Conditional_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 280, self.RULE_conditional_generate_construct)
        try:
            self.state = 2449
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.IF]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2447
                self.if_generate_construct()
                pass
            elif token in [VerilogParser.CASE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2448
                self.case_generate_construct()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class If_generate_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def IF(self):
            return self.getToken(VerilogParser.IF, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def generate_block_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Generate_block_or_nullContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Generate_block_or_nullContext,i)


        def ELSE(self):
            return self.getToken(VerilogParser.ELSE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_if_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIf_generate_construct" ):
                listener.enterIf_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIf_generate_construct" ):
                listener.exitIf_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIf_generate_construct" ):
                return visitor.visitIf_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def if_generate_construct(self):

        localctx = VerilogParser.If_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 282, self.RULE_if_generate_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2451
            self.match(VerilogParser.IF)
            self.state = 2452
            self.match(VerilogParser.LP)
            self.state = 2453
            self.constant_expression(0)
            self.state = 2454
            self.match(VerilogParser.RP)
            self.state = 2455
            self.generate_block_or_null()
            self.state = 2458
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,233,self._ctx)
            if la_ == 1:
                self.state = 2456
                self.match(VerilogParser.ELSE)
                self.state = 2457
                self.generate_block_or_null()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Case_generate_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CASE(self):
            return self.getToken(VerilogParser.CASE, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def ENDCASE(self):
            return self.getToken(VerilogParser.ENDCASE, 0)

        def case_generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Case_generate_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Case_generate_itemContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_case_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_generate_construct" ):
                listener.enterCase_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_generate_construct" ):
                listener.exitCase_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_generate_construct" ):
                return visitor.visitCase_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def case_generate_construct(self):

        localctx = VerilogParser.Case_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 284, self.RULE_case_generate_construct)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2460
            self.match(VerilogParser.CASE)
            self.state = 2461
            self.match(VerilogParser.LP)
            self.state = 2462
            self.constant_expression(0)
            self.state = 2463
            self.match(VerilogParser.RP)
            self.state = 2465 
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while True:
                self.state = 2464
                self.case_generate_item()
                self.state = 2467 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if not (_la==VerilogParser.DEFAULT or ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER):
                    break

            self.state = 2469
            self.match(VerilogParser.ENDCASE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Case_generate_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def generate_block_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Generate_block_or_nullContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def DEFAULT(self):
            return self.getToken(VerilogParser.DEFAULT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_case_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_generate_item" ):
                listener.enterCase_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_generate_item" ):
                listener.exitCase_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_generate_item" ):
                return visitor.visitCase_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def case_generate_item(self):

        localctx = VerilogParser.Case_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 286, self.RULE_case_generate_item)
        self._la = 0 # Token type
        try:
            self.state = 2487
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.AM, VerilogParser.CA, VerilogParser.CATI, VerilogParser.EM, VerilogParser.LC, VerilogParser.LP, VerilogParser.MI, VerilogParser.PL, VerilogParser.TI, VerilogParser.TIAM, VerilogParser.TICA, VerilogParser.TIVL, VerilogParser.VL, VerilogParser.BINARY_BASE, VerilogParser.DECIMAL_BASE, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.EXPONENTIAL_NUMBER, VerilogParser.FIXED_POINT_NUMBER, VerilogParser.HEX_BASE, VerilogParser.OCTAL_BASE, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.STRING, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.UNSIGNED_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2471
                self.constant_expression(0)
                self.state = 2476
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 2472
                    self.match(VerilogParser.CO)
                    self.state = 2473
                    self.constant_expression(0)
                    self.state = 2478
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2479
                self.match(VerilogParser.CL)
                self.state = 2480
                self.generate_block_or_null()
                pass
            elif token in [VerilogParser.DEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2482
                self.match(VerilogParser.DEFAULT)
                self.state = 2484
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CL:
                    self.state = 2483
                    self.match(VerilogParser.CL)


                self.state = 2486
                self.generate_block_or_null()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Generate_blockContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_or_generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_or_generate_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_or_generate_itemContext,i)


        def BEGIN(self):
            return self.getToken(VerilogParser.BEGIN, 0)

        def END(self):
            return self.getToken(VerilogParser.END, 0)

        def generate_block_name(self):
            return self.getTypedRuleContext(VerilogParser.Generate_block_nameContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_generate_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block" ):
                listener.enterGenerate_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block" ):
                listener.exitGenerate_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block" ):
                return visitor.visitGenerate_block(self)
            else:
                return visitor.visitChildren(self)




    def generate_block(self):

        localctx = VerilogParser.Generate_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 288, self.RULE_generate_block)
        self._la = 0 # Token type
        try:
            self.state = 2501
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ALWAYS, VerilogParser.AND, VerilogParser.ASSIGN, VerilogParser.BUF, VerilogParser.BUFIFONE, VerilogParser.BUFIFZERO, VerilogParser.CASE, VerilogParser.CMOS, VerilogParser.DEFPARAM, VerilogParser.EVENT, VerilogParser.FOR, VerilogParser.FUNCTION, VerilogParser.GENVAR, VerilogParser.IF, VerilogParser.INITIAL, VerilogParser.INTEGER, VerilogParser.LOCALPARAM, VerilogParser.NAND, VerilogParser.NMOS, VerilogParser.NOR, VerilogParser.NOT, VerilogParser.NOTIFONE, VerilogParser.NOTIFZERO, VerilogParser.OR, VerilogParser.PMOS, VerilogParser.PULLDOWN, VerilogParser.PULLUP, VerilogParser.RCMOS, VerilogParser.REAL, VerilogParser.REALTIME, VerilogParser.REG, VerilogParser.RNMOS, VerilogParser.RPMOS, VerilogParser.RTRAN, VerilogParser.RTRANIFONE, VerilogParser.RTRANIFZERO, VerilogParser.SUPPLYONE, VerilogParser.SUPPLYZERO, VerilogParser.TASK, VerilogParser.TIME, VerilogParser.TRAN, VerilogParser.TRANIFONE, VerilogParser.TRANIFZERO, VerilogParser.TRI, VerilogParser.TRIAND, VerilogParser.TRIONE, VerilogParser.TRIOR, VerilogParser.TRIREG, VerilogParser.TRIZERO, VerilogParser.UWIRE, VerilogParser.WAND, VerilogParser.WIRE, VerilogParser.WOR, VerilogParser.XNOR, VerilogParser.XOR, VerilogParser.LP, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2489
                self.module_or_generate_item()
                pass
            elif token in [VerilogParser.BEGIN]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2490
                self.match(VerilogParser.BEGIN)
                self.state = 2492
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CL:
                    self.state = 2491
                    self.generate_block_name()


                self.state = 2497
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ALWAYS) | (1 << VerilogParser.AND) | (1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BUF) | (1 << VerilogParser.BUFIFONE) | (1 << VerilogParser.BUFIFZERO) | (1 << VerilogParser.CASE) | (1 << VerilogParser.CMOS) | (1 << VerilogParser.DEFPARAM) | (1 << VerilogParser.EVENT) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FUNCTION) | (1 << VerilogParser.GENVAR) | (1 << VerilogParser.IF) | (1 << VerilogParser.INITIAL) | (1 << VerilogParser.INTEGER))) != 0) or ((((_la - 66)) & ~0x3f) == 0 and ((1 << (_la - 66)) & ((1 << (VerilogParser.LOCALPARAM - 66)) | (1 << (VerilogParser.NAND - 66)) | (1 << (VerilogParser.NMOS - 66)) | (1 << (VerilogParser.NOR - 66)) | (1 << (VerilogParser.NOT - 66)) | (1 << (VerilogParser.NOTIFONE - 66)) | (1 << (VerilogParser.NOTIFZERO - 66)) | (1 << (VerilogParser.OR - 66)) | (1 << (VerilogParser.PMOS - 66)) | (1 << (VerilogParser.PULLDOWN - 66)) | (1 << (VerilogParser.PULLUP - 66)) | (1 << (VerilogParser.RCMOS - 66)) | (1 << (VerilogParser.REAL - 66)) | (1 << (VerilogParser.REALTIME - 66)) | (1 << (VerilogParser.REG - 66)) | (1 << (VerilogParser.RNMOS - 66)) | (1 << (VerilogParser.RPMOS - 66)) | (1 << (VerilogParser.RTRAN - 66)) | (1 << (VerilogParser.RTRANIFONE - 66)) | (1 << (VerilogParser.RTRANIFZERO - 66)) | (1 << (VerilogParser.SUPPLYONE - 66)) | (1 << (VerilogParser.SUPPLYZERO - 66)) | (1 << (VerilogParser.TASK - 66)) | (1 << (VerilogParser.TIME - 66)) | (1 << (VerilogParser.TRAN - 66)) | (1 << (VerilogParser.TRANIFONE - 66)) | (1 << (VerilogParser.TRANIFZERO - 66)) | (1 << (VerilogParser.TRI - 66)) | (1 << (VerilogParser.TRIAND - 66)) | (1 << (VerilogParser.TRIONE - 66)) | (1 << (VerilogParser.TRIOR - 66)) | (1 << (VerilogParser.TRIREG - 66)) | (1 << (VerilogParser.TRIZERO - 66)) | (1 << (VerilogParser.UWIRE - 66)) | (1 << (VerilogParser.WAND - 66)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (VerilogParser.WIRE - 133)) | (1 << (VerilogParser.WOR - 133)) | (1 << (VerilogParser.XNOR - 133)) | (1 << (VerilogParser.XOR - 133)) | (1 << (VerilogParser.LP - 133)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 133)))) != 0) or _la==VerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 2494
                    self.module_or_generate_item()
                    self.state = 2499
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2500
                self.match(VerilogParser.END)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Generate_block_nameContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def generate_block_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Generate_block_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_generate_block_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block_name" ):
                listener.enterGenerate_block_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block_name" ):
                listener.exitGenerate_block_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block_name" ):
                return visitor.visitGenerate_block_name(self)
            else:
                return visitor.visitChildren(self)




    def generate_block_name(self):

        localctx = VerilogParser.Generate_block_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 290, self.RULE_generate_block_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2503
            self.match(VerilogParser.CL)
            self.state = 2504
            self.generate_block_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Generate_block_or_nullContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_block(self):
            return self.getTypedRuleContext(VerilogParser.Generate_blockContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_generate_block_or_null

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block_or_null" ):
                listener.enterGenerate_block_or_null(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block_or_null" ):
                listener.exitGenerate_block_or_null(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block_or_null" ):
                return visitor.visitGenerate_block_or_null(self)
            else:
                return visitor.visitChildren(self)




    def generate_block_or_null(self):

        localctx = VerilogParser.Generate_block_or_nullContext(self, self._ctx, self.state)
        self.enterRule(localctx, 292, self.RULE_generate_block_or_null)
        try:
            self.state = 2508
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ALWAYS, VerilogParser.AND, VerilogParser.ASSIGN, VerilogParser.BEGIN, VerilogParser.BUF, VerilogParser.BUFIFONE, VerilogParser.BUFIFZERO, VerilogParser.CASE, VerilogParser.CMOS, VerilogParser.DEFPARAM, VerilogParser.EVENT, VerilogParser.FOR, VerilogParser.FUNCTION, VerilogParser.GENVAR, VerilogParser.IF, VerilogParser.INITIAL, VerilogParser.INTEGER, VerilogParser.LOCALPARAM, VerilogParser.NAND, VerilogParser.NMOS, VerilogParser.NOR, VerilogParser.NOT, VerilogParser.NOTIFONE, VerilogParser.NOTIFZERO, VerilogParser.OR, VerilogParser.PMOS, VerilogParser.PULLDOWN, VerilogParser.PULLUP, VerilogParser.RCMOS, VerilogParser.REAL, VerilogParser.REALTIME, VerilogParser.REG, VerilogParser.RNMOS, VerilogParser.RPMOS, VerilogParser.RTRAN, VerilogParser.RTRANIFONE, VerilogParser.RTRANIFZERO, VerilogParser.SUPPLYONE, VerilogParser.SUPPLYZERO, VerilogParser.TASK, VerilogParser.TIME, VerilogParser.TRAN, VerilogParser.TRANIFONE, VerilogParser.TRANIFZERO, VerilogParser.TRI, VerilogParser.TRIAND, VerilogParser.TRIONE, VerilogParser.TRIOR, VerilogParser.TRIREG, VerilogParser.TRIZERO, VerilogParser.UWIRE, VerilogParser.WAND, VerilogParser.WIRE, VerilogParser.WOR, VerilogParser.XNOR, VerilogParser.XOR, VerilogParser.LP, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2506
                self.generate_block()
                pass
            elif token in [VerilogParser.SC]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2507
                self.match(VerilogParser.SC)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PRIMITIVE(self):
            return self.getToken(VerilogParser.PRIMITIVE, 0)

        def udp_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Udp_identifierContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def udp_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Udp_port_listContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def udp_body(self):
            return self.getTypedRuleContext(VerilogParser.Udp_bodyContext,0)


        def ENDPRIMITIVE(self):
            return self.getToken(VerilogParser.ENDPRIMITIVE, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def udp_port_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Udp_port_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Udp_port_declarationContext,i)


        def udp_declaration_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Udp_declaration_port_listContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_declaration" ):
                listener.enterUdp_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_declaration" ):
                listener.exitUdp_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_declaration" ):
                return visitor.visitUdp_declaration(self)
            else:
                return visitor.visitChildren(self)




    def udp_declaration(self):

        localctx = VerilogParser.Udp_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 294, self.RULE_udp_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2545
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,245,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2513
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2510
                    self.attribute_instance()
                    self.state = 2515
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2516
                self.match(VerilogParser.PRIMITIVE)
                self.state = 2517
                self.udp_identifier()
                self.state = 2518
                self.match(VerilogParser.LP)
                self.state = 2519
                self.udp_port_list()
                self.state = 2520
                self.match(VerilogParser.RP)
                self.state = 2521
                self.match(VerilogParser.SC)
                self.state = 2523 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while True:
                    self.state = 2522
                    self.udp_port_declaration()
                    self.state = 2525 
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if not (((((_la - 59)) & ~0x3f) == 0 and ((1 << (_la - 59)) & ((1 << (VerilogParser.INPUT - 59)) | (1 << (VerilogParser.OUTPUT - 59)) | (1 << (VerilogParser.REG - 59)))) != 0) or _la==VerilogParser.LP):
                        break

                self.state = 2527
                self.udp_body()
                self.state = 2528
                self.match(VerilogParser.ENDPRIMITIVE)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2533
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2530
                    self.attribute_instance()
                    self.state = 2535
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2536
                self.match(VerilogParser.PRIMITIVE)
                self.state = 2537
                self.udp_identifier()
                self.state = 2538
                self.match(VerilogParser.LP)
                self.state = 2539
                self.udp_declaration_port_list()
                self.state = 2540
                self.match(VerilogParser.RP)
                self.state = 2541
                self.match(VerilogParser.SC)
                self.state = 2542
                self.udp_body()
                self.state = 2543
                self.match(VerilogParser.ENDPRIMITIVE)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_port_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def output_port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Output_port_identifierContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def input_port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Input_port_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Input_port_identifierContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_port_list" ):
                listener.enterUdp_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_port_list" ):
                listener.exitUdp_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_port_list" ):
                return visitor.visitUdp_port_list(self)
            else:
                return visitor.visitChildren(self)




    def udp_port_list(self):

        localctx = VerilogParser.Udp_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 296, self.RULE_udp_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2547
            self.output_port_identifier()
            self.state = 2548
            self.match(VerilogParser.CO)
            self.state = 2549
            self.input_port_identifier()
            self.state = 2554
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 2550
                self.match(VerilogParser.CO)
                self.state = 2551
                self.input_port_identifier()
                self.state = 2556
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_declaration_port_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def udp_output_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Udp_output_declarationContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def udp_input_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Udp_input_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Udp_input_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_declaration_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_declaration_port_list" ):
                listener.enterUdp_declaration_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_declaration_port_list" ):
                listener.exitUdp_declaration_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_declaration_port_list" ):
                return visitor.visitUdp_declaration_port_list(self)
            else:
                return visitor.visitChildren(self)




    def udp_declaration_port_list(self):

        localctx = VerilogParser.Udp_declaration_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 298, self.RULE_udp_declaration_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2557
            self.udp_output_declaration()
            self.state = 2558
            self.match(VerilogParser.CO)
            self.state = 2559
            self.udp_input_declaration()
            self.state = 2564
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 2560
                self.match(VerilogParser.CO)
                self.state = 2561
                self.udp_input_declaration()
                self.state = 2566
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_port_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def udp_output_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Udp_output_declarationContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def udp_input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Udp_input_declarationContext,0)


        def udp_reg_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Udp_reg_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_port_declaration" ):
                listener.enterUdp_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_port_declaration" ):
                listener.exitUdp_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_port_declaration" ):
                return visitor.visitUdp_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def udp_port_declaration(self):

        localctx = VerilogParser.Udp_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 300, self.RULE_udp_port_declaration)
        try:
            self.state = 2576
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,248,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2567
                self.udp_output_declaration()
                self.state = 2568
                self.match(VerilogParser.SC)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2570
                self.udp_input_declaration()
                self.state = 2571
                self.match(VerilogParser.SC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2573
                self.udp_reg_declaration()
                self.state = 2574
                self.match(VerilogParser.SC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_output_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def OUTPUT(self):
            return self.getToken(VerilogParser.OUTPUT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_output_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_output_declaration" ):
                listener.enterUdp_output_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_output_declaration" ):
                listener.exitUdp_output_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_output_declaration" ):
                return visitor.visitUdp_output_declaration(self)
            else:
                return visitor.visitChildren(self)




    def udp_output_declaration(self):

        localctx = VerilogParser.Udp_output_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 302, self.RULE_udp_output_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2599
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,252,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2581
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2578
                    self.attribute_instance()
                    self.state = 2583
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2584
                self.match(VerilogParser.OUTPUT)
                self.state = 2585
                self.port_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2589
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2586
                    self.attribute_instance()
                    self.state = 2591
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2592
                self.match(VerilogParser.OUTPUT)
                self.state = 2593
                self.match(VerilogParser.REG)
                self.state = 2594
                self.port_identifier()
                self.state = 2597
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.EQ:
                    self.state = 2595
                    self.match(VerilogParser.EQ)
                    self.state = 2596
                    self.constant_expression(0)


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_input_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INPUT(self):
            return self.getToken(VerilogParser.INPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_input_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_input_declaration" ):
                listener.enterUdp_input_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_input_declaration" ):
                listener.exitUdp_input_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_input_declaration" ):
                return visitor.visitUdp_input_declaration(self)
            else:
                return visitor.visitChildren(self)




    def udp_input_declaration(self):

        localctx = VerilogParser.Udp_input_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 304, self.RULE_udp_input_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2604
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LP:
                self.state = 2601
                self.attribute_instance()
                self.state = 2606
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2607
            self.match(VerilogParser.INPUT)
            self.state = 2608
            self.list_of_port_identifiers()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_reg_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_reg_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_reg_declaration" ):
                listener.enterUdp_reg_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_reg_declaration" ):
                listener.exitUdp_reg_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_reg_declaration" ):
                return visitor.visitUdp_reg_declaration(self)
            else:
                return visitor.visitChildren(self)




    def udp_reg_declaration(self):

        localctx = VerilogParser.Udp_reg_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 306, self.RULE_udp_reg_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2613
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LP:
                self.state = 2610
                self.attribute_instance()
                self.state = 2615
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2616
            self.match(VerilogParser.REG)
            self.state = 2617
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_bodyContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def combinational_body(self):
            return self.getTypedRuleContext(VerilogParser.Combinational_bodyContext,0)


        def sequential_body(self):
            return self.getTypedRuleContext(VerilogParser.Sequential_bodyContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_body

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_body" ):
                listener.enterUdp_body(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_body" ):
                listener.exitUdp_body(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_body" ):
                return visitor.visitUdp_body(self)
            else:
                return visitor.visitChildren(self)




    def udp_body(self):

        localctx = VerilogParser.Udp_bodyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 308, self.RULE_udp_body)
        try:
            self.state = 2621
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,255,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2619
                self.combinational_body()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2620
                self.sequential_body()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Combinational_bodyContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TABLE(self):
            return self.getToken(VerilogParser.TABLE, 0)

        def ENDTABLE(self):
            return self.getToken(VerilogParser.ENDTABLE, 0)

        def combinational_entry(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Combinational_entryContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Combinational_entryContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_combinational_body

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCombinational_body" ):
                listener.enterCombinational_body(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCombinational_body" ):
                listener.exitCombinational_body(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCombinational_body" ):
                return visitor.visitCombinational_body(self)
            else:
                return visitor.visitChildren(self)




    def combinational_body(self):

        localctx = VerilogParser.Combinational_bodyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 310, self.RULE_combinational_body)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2623
            self.match(VerilogParser.TABLE)
            self.state = 2625 
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while True:
                self.state = 2624
                self.combinational_entry()
                self.state = 2627 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if not (_la==VerilogParser.LEVEL_ONLY_SYMBOL or _la==VerilogParser.OUTPUT_OR_LEVEL_SYMBOL):
                    break

            self.state = 2629
            self.match(VerilogParser.ENDTABLE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Combinational_entryContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def level_input_list(self):
            return self.getTypedRuleContext(VerilogParser.Level_input_listContext,0)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def output_symbol(self):
            return self.getTypedRuleContext(VerilogParser.Output_symbolContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_combinational_entry

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCombinational_entry" ):
                listener.enterCombinational_entry(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCombinational_entry" ):
                listener.exitCombinational_entry(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCombinational_entry" ):
                return visitor.visitCombinational_entry(self)
            else:
                return visitor.visitChildren(self)




    def combinational_entry(self):

        localctx = VerilogParser.Combinational_entryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 312, self.RULE_combinational_entry)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2631
            self.level_input_list()
            self.state = 2632
            self.match(VerilogParser.CL)
            self.state = 2633
            self.output_symbol()
            self.state = 2634
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Sequential_bodyContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TABLE(self):
            return self.getToken(VerilogParser.TABLE, 0)

        def ENDTABLE(self):
            return self.getToken(VerilogParser.ENDTABLE, 0)

        def udp_initial_statement(self):
            return self.getTypedRuleContext(VerilogParser.Udp_initial_statementContext,0)


        def sequential_entry(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Sequential_entryContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Sequential_entryContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_sequential_body

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequential_body" ):
                listener.enterSequential_body(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequential_body" ):
                listener.exitSequential_body(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequential_body" ):
                return visitor.visitSequential_body(self)
            else:
                return visitor.visitChildren(self)




    def sequential_body(self):

        localctx = VerilogParser.Sequential_bodyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 314, self.RULE_sequential_body)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2637
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.INITIAL:
                self.state = 2636
                self.udp_initial_statement()


            self.state = 2639
            self.match(VerilogParser.TABLE)
            self.state = 2641 
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while True:
                self.state = 2640
                self.sequential_entry()
                self.state = 2643 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if not (((((_la - 166)) & ~0x3f) == 0 and ((1 << (_la - 166)) & ((1 << (VerilogParser.LP - 166)) | (1 << (VerilogParser.EDGE_SYMBOL - 166)) | (1 << (VerilogParser.LEVEL_ONLY_SYMBOL - 166)) | (1 << (VerilogParser.OUTPUT_OR_LEVEL_SYMBOL - 166)))) != 0)):
                    break

            self.state = 2645
            self.match(VerilogParser.ENDTABLE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_initial_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INITIAL(self):
            return self.getToken(VerilogParser.INITIAL, 0)

        def output_port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Output_port_identifierContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def init_val(self):
            return self.getTypedRuleContext(VerilogParser.Init_valContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_udp_initial_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_initial_statement" ):
                listener.enterUdp_initial_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_initial_statement" ):
                listener.exitUdp_initial_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_initial_statement" ):
                return visitor.visitUdp_initial_statement(self)
            else:
                return visitor.visitChildren(self)




    def udp_initial_statement(self):

        localctx = VerilogParser.Udp_initial_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 316, self.RULE_udp_initial_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2647
            self.match(VerilogParser.INITIAL)
            self.state = 2648
            self.output_port_identifier()
            self.state = 2649
            self.match(VerilogParser.EQ)
            self.state = 2650
            self.init_val()
            self.state = 2651
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Init_valContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def binary_number(self):
            return self.getTypedRuleContext(VerilogParser.Binary_numberContext,0)


        def unsigned_number(self):
            return self.getTypedRuleContext(VerilogParser.Unsigned_numberContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_init_val

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInit_val" ):
                listener.enterInit_val(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInit_val" ):
                listener.exitInit_val(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInit_val" ):
                return visitor.visitInit_val(self)
            else:
                return visitor.visitChildren(self)




    def init_val(self):

        localctx = VerilogParser.Init_valContext(self, self._ctx, self.state)
        self.enterRule(localctx, 318, self.RULE_init_val)
        try:
            self.state = 2655
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,259,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2653
                self.binary_number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2654
                self.unsigned_number()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Sequential_entryContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def seq_input_list(self):
            return self.getTypedRuleContext(VerilogParser.Seq_input_listContext,0)


        def CL(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CL)
            else:
                return self.getToken(VerilogParser.CL, i)

        def current_state(self):
            return self.getTypedRuleContext(VerilogParser.Current_stateContext,0)


        def next_state(self):
            return self.getTypedRuleContext(VerilogParser.Next_stateContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_sequential_entry

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequential_entry" ):
                listener.enterSequential_entry(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequential_entry" ):
                listener.exitSequential_entry(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequential_entry" ):
                return visitor.visitSequential_entry(self)
            else:
                return visitor.visitChildren(self)




    def sequential_entry(self):

        localctx = VerilogParser.Sequential_entryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 320, self.RULE_sequential_entry)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2657
            self.seq_input_list()
            self.state = 2658
            self.match(VerilogParser.CL)
            self.state = 2659
            self.current_state()
            self.state = 2660
            self.match(VerilogParser.CL)
            self.state = 2661
            self.next_state()
            self.state = 2662
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Seq_input_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def level_input_list(self):
            return self.getTypedRuleContext(VerilogParser.Level_input_listContext,0)


        def edge_input_list(self):
            return self.getTypedRuleContext(VerilogParser.Edge_input_listContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_seq_input_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSeq_input_list" ):
                listener.enterSeq_input_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSeq_input_list" ):
                listener.exitSeq_input_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSeq_input_list" ):
                return visitor.visitSeq_input_list(self)
            else:
                return visitor.visitChildren(self)




    def seq_input_list(self):

        localctx = VerilogParser.Seq_input_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 322, self.RULE_seq_input_list)
        try:
            self.state = 2666
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,260,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2664
                self.level_input_list()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2665
                self.edge_input_list()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Level_input_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def level_symbol(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Level_symbolContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Level_symbolContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_level_input_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLevel_input_list" ):
                listener.enterLevel_input_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLevel_input_list" ):
                listener.exitLevel_input_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLevel_input_list" ):
                return visitor.visitLevel_input_list(self)
            else:
                return visitor.visitChildren(self)




    def level_input_list(self):

        localctx = VerilogParser.Level_input_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 324, self.RULE_level_input_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2669 
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while True:
                self.state = 2668
                self.level_symbol()
                self.state = 2671 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if not (_la==VerilogParser.LEVEL_ONLY_SYMBOL or _la==VerilogParser.OUTPUT_OR_LEVEL_SYMBOL):
                    break

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Edge_input_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def edge_indicator(self):
            return self.getTypedRuleContext(VerilogParser.Edge_indicatorContext,0)


        def level_symbol(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Level_symbolContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Level_symbolContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_edge_input_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_input_list" ):
                listener.enterEdge_input_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_input_list" ):
                listener.exitEdge_input_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_input_list" ):
                return visitor.visitEdge_input_list(self)
            else:
                return visitor.visitChildren(self)




    def edge_input_list(self):

        localctx = VerilogParser.Edge_input_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 326, self.RULE_edge_input_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2676
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LEVEL_ONLY_SYMBOL or _la==VerilogParser.OUTPUT_OR_LEVEL_SYMBOL:
                self.state = 2673
                self.level_symbol()
                self.state = 2678
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2679
            self.edge_indicator()
            self.state = 2683
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LEVEL_ONLY_SYMBOL or _la==VerilogParser.OUTPUT_OR_LEVEL_SYMBOL:
                self.state = 2680
                self.level_symbol()
                self.state = 2685
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Edge_indicatorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def level_symbol(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Level_symbolContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Level_symbolContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def edge_symbol(self):
            return self.getTypedRuleContext(VerilogParser.Edge_symbolContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_edge_indicator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_indicator" ):
                listener.enterEdge_indicator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_indicator" ):
                listener.exitEdge_indicator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_indicator" ):
                return visitor.visitEdge_indicator(self)
            else:
                return visitor.visitChildren(self)




    def edge_indicator(self):

        localctx = VerilogParser.Edge_indicatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 328, self.RULE_edge_indicator)
        try:
            self.state = 2692
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.LP]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2686
                self.match(VerilogParser.LP)
                self.state = 2687
                self.level_symbol()
                self.state = 2688
                self.level_symbol()
                self.state = 2689
                self.match(VerilogParser.RP)
                pass
            elif token in [VerilogParser.EDGE_SYMBOL]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2691
                self.edge_symbol()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Current_stateContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def level_symbol(self):
            return self.getTypedRuleContext(VerilogParser.Level_symbolContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_current_state

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCurrent_state" ):
                listener.enterCurrent_state(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCurrent_state" ):
                listener.exitCurrent_state(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCurrent_state" ):
                return visitor.visitCurrent_state(self)
            else:
                return visitor.visitChildren(self)




    def current_state(self):

        localctx = VerilogParser.Current_stateContext(self, self._ctx, self.state)
        self.enterRule(localctx, 330, self.RULE_current_state)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2694
            self.level_symbol()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Next_stateContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def output_symbol(self):
            return self.getTypedRuleContext(VerilogParser.Output_symbolContext,0)


        def MI(self):
            return self.getToken(VerilogParser.MI, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_next_state

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNext_state" ):
                listener.enterNext_state(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNext_state" ):
                listener.exitNext_state(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNext_state" ):
                return visitor.visitNext_state(self)
            else:
                return visitor.visitChildren(self)




    def next_state(self):

        localctx = VerilogParser.Next_stateContext(self, self._ctx, self.state)
        self.enterRule(localctx, 332, self.RULE_next_state)
        try:
            self.state = 2698
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.OUTPUT_OR_LEVEL_SYMBOL]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2696
                self.output_symbol()
                pass
            elif token in [VerilogParser.MI]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2697
                self.match(VerilogParser.MI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Output_symbolContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def OUTPUT_OR_LEVEL_SYMBOL(self):
            return self.getToken(VerilogParser.OUTPUT_OR_LEVEL_SYMBOL, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_output_symbol

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_symbol" ):
                listener.enterOutput_symbol(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_symbol" ):
                listener.exitOutput_symbol(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_symbol" ):
                return visitor.visitOutput_symbol(self)
            else:
                return visitor.visitChildren(self)




    def output_symbol(self):

        localctx = VerilogParser.Output_symbolContext(self, self._ctx, self.state)
        self.enterRule(localctx, 334, self.RULE_output_symbol)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2700
            self.match(VerilogParser.OUTPUT_OR_LEVEL_SYMBOL)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Level_symbolContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEVEL_ONLY_SYMBOL(self):
            return self.getToken(VerilogParser.LEVEL_ONLY_SYMBOL, 0)

        def OUTPUT_OR_LEVEL_SYMBOL(self):
            return self.getToken(VerilogParser.OUTPUT_OR_LEVEL_SYMBOL, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_level_symbol

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLevel_symbol" ):
                listener.enterLevel_symbol(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLevel_symbol" ):
                listener.exitLevel_symbol(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLevel_symbol" ):
                return visitor.visitLevel_symbol(self)
            else:
                return visitor.visitChildren(self)




    def level_symbol(self):

        localctx = VerilogParser.Level_symbolContext(self, self._ctx, self.state)
        self.enterRule(localctx, 336, self.RULE_level_symbol)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2702
            _la = self._input.LA(1)
            if not(_la==VerilogParser.LEVEL_ONLY_SYMBOL or _la==VerilogParser.OUTPUT_OR_LEVEL_SYMBOL):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Edge_symbolContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EDGE_SYMBOL(self):
            return self.getToken(VerilogParser.EDGE_SYMBOL, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_edge_symbol

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_symbol" ):
                listener.enterEdge_symbol(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_symbol" ):
                listener.exitEdge_symbol(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_symbol" ):
                return visitor.visitEdge_symbol(self)
            else:
                return visitor.visitChildren(self)




    def edge_symbol(self):

        localctx = VerilogParser.Edge_symbolContext(self, self._ctx, self.state)
        self.enterRule(localctx, 338, self.RULE_edge_symbol)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2704
            self.match(VerilogParser.EDGE_SYMBOL)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def udp_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Udp_identifierContext,0)


        def udp_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Udp_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Udp_instanceContext,i)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def drive_strength(self):
            return self.getTypedRuleContext(VerilogParser.Drive_strengthContext,0)


        def delay2(self):
            return self.getTypedRuleContext(VerilogParser.Delay2Context,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_udp_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_instantiation" ):
                listener.enterUdp_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_instantiation" ):
                listener.exitUdp_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_instantiation" ):
                return visitor.visitUdp_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def udp_instantiation(self):

        localctx = VerilogParser.Udp_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 340, self.RULE_udp_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2706
            self.udp_identifier()
            self.state = 2708
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,266,self._ctx)
            if la_ == 1:
                self.state = 2707
                self.drive_strength()


            self.state = 2711
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.HA:
                self.state = 2710
                self.delay2()


            self.state = 2713
            self.udp_instance()
            self.state = 2718
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 2714
                self.match(VerilogParser.CO)
                self.state = 2715
                self.udp_instance()
                self.state = 2720
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2721
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def input_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Input_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Input_terminalContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def name_of_udp_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_udp_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_instance" ):
                listener.enterUdp_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_instance" ):
                listener.exitUdp_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_instance" ):
                return visitor.visitUdp_instance(self)
            else:
                return visitor.visitChildren(self)




    def udp_instance(self):

        localctx = VerilogParser.Udp_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 342, self.RULE_udp_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2724
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2723
                self.name_of_udp_instance()


            self.state = 2726
            self.match(VerilogParser.LP)
            self.state = 2727
            self.output_terminal()
            self.state = 2728
            self.match(VerilogParser.CO)
            self.state = 2729
            self.input_terminal()
            self.state = 2734
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 2730
                self.match(VerilogParser.CO)
                self.state = 2731
                self.input_terminal()
                self.state = 2736
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2737
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Name_of_udp_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def udp_instance_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Udp_instance_identifierContext,0)


        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_name_of_udp_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterName_of_udp_instance" ):
                listener.enterName_of_udp_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitName_of_udp_instance" ):
                listener.exitName_of_udp_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitName_of_udp_instance" ):
                return visitor.visitName_of_udp_instance(self)
            else:
                return visitor.visitChildren(self)




    def name_of_udp_instance(self):

        localctx = VerilogParser.Name_of_udp_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 344, self.RULE_name_of_udp_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2739
            self.udp_instance_identifier()
            self.state = 2741
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 2740
                self.range_()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Continuous_assignContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ASSIGN(self):
            return self.getToken(VerilogParser.ASSIGN, 0)

        def list_of_net_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_net_assignmentsContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def drive_strength(self):
            return self.getTypedRuleContext(VerilogParser.Drive_strengthContext,0)


        def delay3(self):
            return self.getTypedRuleContext(VerilogParser.Delay3Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_continuous_assign

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterContinuous_assign" ):
                listener.enterContinuous_assign(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitContinuous_assign" ):
                listener.exitContinuous_assign(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitContinuous_assign" ):
                return visitor.visitContinuous_assign(self)
            else:
                return visitor.visitChildren(self)




    def continuous_assign(self):

        localctx = VerilogParser.Continuous_assignContext(self, self._ctx, self.state)
        self.enterRule(localctx, 346, self.RULE_continuous_assign)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2743
            self.match(VerilogParser.ASSIGN)
            self.state = 2745
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LP:
                self.state = 2744
                self.drive_strength()


            self.state = 2748
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.HA:
                self.state = 2747
                self.delay3()


            self.state = 2750
            self.list_of_net_assignments()
            self.state = 2751
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_net_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Net_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Net_assignmentContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_net_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_net_assignments" ):
                listener.enterList_of_net_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_net_assignments" ):
                listener.exitList_of_net_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_net_assignments" ):
                return visitor.visitList_of_net_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_net_assignments(self):

        localctx = VerilogParser.List_of_net_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 348, self.RULE_list_of_net_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2753
            self.net_assignment()
            self.state = 2758
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 2754
                self.match(VerilogParser.CO)
                self.state = 2755
                self.net_assignment()
                self.state = 2760
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Net_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_assignment" ):
                listener.enterNet_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_assignment" ):
                listener.exitNet_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_assignment" ):
                return visitor.visitNet_assignment(self)
            else:
                return visitor.visitChildren(self)




    def net_assignment(self):

        localctx = VerilogParser.Net_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 350, self.RULE_net_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2761
            self.net_lvalue()
            self.state = 2762
            self.match(VerilogParser.EQ)
            self.state = 2763
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Initial_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INITIAL(self):
            return self.getToken(VerilogParser.INITIAL, 0)

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_initial_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInitial_construct" ):
                listener.enterInitial_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInitial_construct" ):
                listener.exitInitial_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInitial_construct" ):
                return visitor.visitInitial_construct(self)
            else:
                return visitor.visitChildren(self)




    def initial_construct(self):

        localctx = VerilogParser.Initial_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 352, self.RULE_initial_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2765
            self.match(VerilogParser.INITIAL)
            self.state = 2766
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Always_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ALWAYS(self):
            return self.getToken(VerilogParser.ALWAYS, 0)

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_always_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAlways_construct" ):
                listener.enterAlways_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAlways_construct" ):
                listener.exitAlways_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAlways_construct" ):
                return visitor.visitAlways_construct(self)
            else:
                return visitor.visitChildren(self)




    def always_construct(self):

        localctx = VerilogParser.Always_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 354, self.RULE_always_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2768
            self.match(VerilogParser.ALWAYS)
            self.state = 2769
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Blocking_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def delay_or_event_control(self):
            return self.getTypedRuleContext(VerilogParser.Delay_or_event_controlContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_blocking_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlocking_assignment" ):
                listener.enterBlocking_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlocking_assignment" ):
                listener.exitBlocking_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlocking_assignment" ):
                return visitor.visitBlocking_assignment(self)
            else:
                return visitor.visitChildren(self)




    def blocking_assignment(self):

        localctx = VerilogParser.Blocking_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 356, self.RULE_blocking_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2771
            self.variable_lvalue()
            self.state = 2772
            self.match(VerilogParser.EQ)
            self.state = 2774
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.REPEAT or _la==VerilogParser.AT or _la==VerilogParser.HA:
                self.state = 2773
                self.delay_or_event_control()


            self.state = 2776
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Nonblocking_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,0)


        def LTEQ(self):
            return self.getToken(VerilogParser.LTEQ, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def delay_or_event_control(self):
            return self.getTypedRuleContext(VerilogParser.Delay_or_event_controlContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_nonblocking_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNonblocking_assignment" ):
                listener.enterNonblocking_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNonblocking_assignment" ):
                listener.exitNonblocking_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNonblocking_assignment" ):
                return visitor.visitNonblocking_assignment(self)
            else:
                return visitor.visitChildren(self)




    def nonblocking_assignment(self):

        localctx = VerilogParser.Nonblocking_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 358, self.RULE_nonblocking_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2778
            self.variable_lvalue()
            self.state = 2779
            self.match(VerilogParser.LTEQ)
            self.state = 2781
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.REPEAT or _la==VerilogParser.AT or _la==VerilogParser.HA:
                self.state = 2780
                self.delay_or_event_control()


            self.state = 2783
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Procedural_continuous_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ASSIGN(self):
            return self.getToken(VerilogParser.ASSIGN, 0)

        def variable_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Variable_assignmentContext,0)


        def DEASSIGN(self):
            return self.getToken(VerilogParser.DEASSIGN, 0)

        def variable_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,0)


        def FORCE(self):
            return self.getToken(VerilogParser.FORCE, 0)

        def RELEASE(self):
            return self.getToken(VerilogParser.RELEASE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_procedural_continuous_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_continuous_assignments" ):
                listener.enterProcedural_continuous_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_continuous_assignments" ):
                listener.exitProcedural_continuous_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_continuous_assignments" ):
                return visitor.visitProcedural_continuous_assignments(self)
            else:
                return visitor.visitChildren(self)




    def procedural_continuous_assignments(self):

        localctx = VerilogParser.Procedural_continuous_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 360, self.RULE_procedural_continuous_assignments)
        try:
            self.state = 2793
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ASSIGN]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2785
                self.match(VerilogParser.ASSIGN)
                self.state = 2786
                self.variable_assignment()
                pass
            elif token in [VerilogParser.DEASSIGN]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2787
                self.match(VerilogParser.DEASSIGN)
                self.state = 2788
                self.variable_lvalue()
                pass
            elif token in [VerilogParser.FORCE]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2789
                self.match(VerilogParser.FORCE)
                self.state = 2790
                self.variable_assignment()
                pass
            elif token in [VerilogParser.RELEASE]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2791
                self.match(VerilogParser.RELEASE)
                self.state = 2792
                self.variable_lvalue()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Variable_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_variable_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_assignment" ):
                listener.enterVariable_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_assignment" ):
                listener.exitVariable_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_assignment" ):
                return visitor.visitVariable_assignment(self)
            else:
                return visitor.visitChildren(self)




    def variable_assignment(self):

        localctx = VerilogParser.Variable_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 362, self.RULE_variable_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2795
            self.variable_lvalue()
            self.state = 2796
            self.match(VerilogParser.EQ)
            self.state = 2797
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Par_blockContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FORK(self):
            return self.getToken(VerilogParser.FORK, 0)

        def JOIN(self):
            return self.getToken(VerilogParser.JOIN, 0)

        def block_name(self):
            return self.getTypedRuleContext(VerilogParser.Block_nameContext,0)


        def statement(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.StatementContext)
            else:
                return self.getTypedRuleContext(VerilogParser.StatementContext,i)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_par_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPar_block" ):
                listener.enterPar_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPar_block" ):
                listener.exitPar_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPar_block" ):
                return visitor.visitPar_block(self)
            else:
                return visitor.visitChildren(self)




    def par_block(self):

        localctx = VerilogParser.Par_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 364, self.RULE_par_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2799
            self.match(VerilogParser.FORK)
            self.state = 2807
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CL:
                self.state = 2800
                self.block_name()
                self.state = 2804
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,278,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2801
                        self.block_item_declaration() 
                    self.state = 2806
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,278,self._ctx)



            self.state = 2812
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BEGIN) | (1 << VerilogParser.CASE) | (1 << VerilogParser.CASEX) | (1 << VerilogParser.CASEZ) | (1 << VerilogParser.DEASSIGN) | (1 << VerilogParser.DISABLE) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FORCE) | (1 << VerilogParser.FOREVER) | (1 << VerilogParser.FORK) | (1 << VerilogParser.IF))) != 0) or ((((_la - 96)) & ~0x3f) == 0 and ((1 << (_la - 96)) & ((1 << (VerilogParser.RELEASE - 96)) | (1 << (VerilogParser.REPEAT - 96)) | (1 << (VerilogParser.WAIT - 96)) | (1 << (VerilogParser.WHILE - 96)) | (1 << (VerilogParser.AT - 96)))) != 0) or ((((_la - 163)) & ~0x3f) == 0 and ((1 << (_la - 163)) & ((1 << (VerilogParser.HA - 163)) | (1 << (VerilogParser.LC - 163)) | (1 << (VerilogParser.LP - 163)) | (1 << (VerilogParser.MIGT - 163)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 163)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 163)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 163)))) != 0):
                self.state = 2809
                self.statement()
                self.state = 2814
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2815
            self.match(VerilogParser.JOIN)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Block_nameContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def block_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Block_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_name" ):
                listener.enterBlock_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_name" ):
                listener.exitBlock_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_name" ):
                return visitor.visitBlock_name(self)
            else:
                return visitor.visitChildren(self)




    def block_name(self):

        localctx = VerilogParser.Block_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 366, self.RULE_block_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2817
            self.match(VerilogParser.CL)
            self.state = 2818
            self.block_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Seq_blockContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def BEGIN(self):
            return self.getToken(VerilogParser.BEGIN, 0)

        def END(self):
            return self.getToken(VerilogParser.END, 0)

        def block_name(self):
            return self.getTypedRuleContext(VerilogParser.Block_nameContext,0)


        def statement(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.StatementContext)
            else:
                return self.getTypedRuleContext(VerilogParser.StatementContext,i)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_seq_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSeq_block" ):
                listener.enterSeq_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSeq_block" ):
                listener.exitSeq_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSeq_block" ):
                return visitor.visitSeq_block(self)
            else:
                return visitor.visitChildren(self)




    def seq_block(self):

        localctx = VerilogParser.Seq_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 368, self.RULE_seq_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2820
            self.match(VerilogParser.BEGIN)
            self.state = 2828
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CL:
                self.state = 2821
                self.block_name()
                self.state = 2825
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,281,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2822
                        self.block_item_declaration() 
                    self.state = 2827
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,281,self._ctx)



            self.state = 2833
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BEGIN) | (1 << VerilogParser.CASE) | (1 << VerilogParser.CASEX) | (1 << VerilogParser.CASEZ) | (1 << VerilogParser.DEASSIGN) | (1 << VerilogParser.DISABLE) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FORCE) | (1 << VerilogParser.FOREVER) | (1 << VerilogParser.FORK) | (1 << VerilogParser.IF))) != 0) or ((((_la - 96)) & ~0x3f) == 0 and ((1 << (_la - 96)) & ((1 << (VerilogParser.RELEASE - 96)) | (1 << (VerilogParser.REPEAT - 96)) | (1 << (VerilogParser.WAIT - 96)) | (1 << (VerilogParser.WHILE - 96)) | (1 << (VerilogParser.AT - 96)))) != 0) or ((((_la - 163)) & ~0x3f) == 0 and ((1 << (_la - 163)) & ((1 << (VerilogParser.HA - 163)) | (1 << (VerilogParser.LC - 163)) | (1 << (VerilogParser.LP - 163)) | (1 << (VerilogParser.MIGT - 163)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 163)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 163)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 163)))) != 0):
                self.state = 2830
                self.statement()
                self.state = 2835
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2836
            self.match(VerilogParser.END)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class StatementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def blocking_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Blocking_assignmentContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def case_statement(self):
            return self.getTypedRuleContext(VerilogParser.Case_statementContext,0)


        def conditional_statement(self):
            return self.getTypedRuleContext(VerilogParser.Conditional_statementContext,0)


        def disable_statement(self):
            return self.getTypedRuleContext(VerilogParser.Disable_statementContext,0)


        def event_trigger(self):
            return self.getTypedRuleContext(VerilogParser.Event_triggerContext,0)


        def loop_statement(self):
            return self.getTypedRuleContext(VerilogParser.Loop_statementContext,0)


        def nonblocking_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Nonblocking_assignmentContext,0)


        def par_block(self):
            return self.getTypedRuleContext(VerilogParser.Par_blockContext,0)


        def procedural_continuous_assignments(self):
            return self.getTypedRuleContext(VerilogParser.Procedural_continuous_assignmentsContext,0)


        def procedural_timing_control_statement(self):
            return self.getTypedRuleContext(VerilogParser.Procedural_timing_control_statementContext,0)


        def seq_block(self):
            return self.getTypedRuleContext(VerilogParser.Seq_blockContext,0)


        def system_task_enable(self):
            return self.getTypedRuleContext(VerilogParser.System_task_enableContext,0)


        def task_enable(self):
            return self.getTypedRuleContext(VerilogParser.Task_enableContext,0)


        def wait_statement(self):
            return self.getTypedRuleContext(VerilogParser.Wait_statementContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement" ):
                listener.enterStatement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement" ):
                listener.exitStatement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement" ):
                return visitor.visitStatement(self)
            else:
                return visitor.visitChildren(self)




    def statement(self):

        localctx = VerilogParser.StatementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 370, self.RULE_statement)
        self._la = 0 # Token type
        try:
            self.state = 2942
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,298,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2841
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2838
                    self.attribute_instance()
                    self.state = 2843
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2844
                self.blocking_assignment()
                self.state = 2845
                self.match(VerilogParser.SC)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2850
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2847
                    self.attribute_instance()
                    self.state = 2852
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2853
                self.case_statement()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2857
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2854
                    self.attribute_instance()
                    self.state = 2859
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2860
                self.conditional_statement()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2864
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2861
                    self.attribute_instance()
                    self.state = 2866
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2867
                self.disable_statement()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2871
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2868
                    self.attribute_instance()
                    self.state = 2873
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2874
                self.event_trigger()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2878
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2875
                    self.attribute_instance()
                    self.state = 2880
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2881
                self.loop_statement()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2885
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2882
                    self.attribute_instance()
                    self.state = 2887
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2888
                self.nonblocking_assignment()
                self.state = 2889
                self.match(VerilogParser.SC)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2894
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2891
                    self.attribute_instance()
                    self.state = 2896
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2897
                self.par_block()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 2901
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2898
                    self.attribute_instance()
                    self.state = 2903
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2904
                self.procedural_continuous_assignments()
                self.state = 2905
                self.match(VerilogParser.SC)
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 2910
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2907
                    self.attribute_instance()
                    self.state = 2912
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2913
                self.procedural_timing_control_statement()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 2917
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2914
                    self.attribute_instance()
                    self.state = 2919
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2920
                self.seq_block()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 2924
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2921
                    self.attribute_instance()
                    self.state = 2926
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2927
                self.system_task_enable()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 2931
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2928
                    self.attribute_instance()
                    self.state = 2933
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2934
                self.task_enable()
                pass

            elif la_ == 14:
                self.enterOuterAlt(localctx, 14)
                self.state = 2938
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2935
                    self.attribute_instance()
                    self.state = 2940
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2941
                self.wait_statement()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Statement_or_nullContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_statement_or_null

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement_or_null" ):
                listener.enterStatement_or_null(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement_or_null" ):
                listener.exitStatement_or_null(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement_or_null" ):
                return visitor.visitStatement_or_null(self)
            else:
                return visitor.visitChildren(self)




    def statement_or_null(self):

        localctx = VerilogParser.Statement_or_nullContext(self, self._ctx, self.state)
        self.enterRule(localctx, 372, self.RULE_statement_or_null)
        self._la = 0 # Token type
        try:
            self.state = 2952
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,300,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2944
                self.statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2948
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LP:
                    self.state = 2945
                    self.attribute_instance()
                    self.state = 2950
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2951
                self.match(VerilogParser.SC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Function_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_function_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_statement" ):
                listener.enterFunction_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_statement" ):
                listener.exitFunction_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_statement" ):
                return visitor.visitFunction_statement(self)
            else:
                return visitor.visitChildren(self)




    def function_statement(self):

        localctx = VerilogParser.Function_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 374, self.RULE_function_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2954
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delay_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HA(self):
            return self.getToken(VerilogParser.HA, 0)

        def delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Delay_valueContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_delay_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_control" ):
                listener.enterDelay_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_control" ):
                listener.exitDelay_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_control" ):
                return visitor.visitDelay_control(self)
            else:
                return visitor.visitChildren(self)




    def delay_control(self):

        localctx = VerilogParser.Delay_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 376, self.RULE_delay_control)
        try:
            self.state = 2963
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,301,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2956
                self.match(VerilogParser.HA)
                self.state = 2957
                self.delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2958
                self.match(VerilogParser.HA)
                self.state = 2959
                self.match(VerilogParser.LP)
                self.state = 2960
                self.mintypmax_expression()
                self.state = 2961
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delay_or_event_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_control(self):
            return self.getTypedRuleContext(VerilogParser.Delay_controlContext,0)


        def event_control(self):
            return self.getTypedRuleContext(VerilogParser.Event_controlContext,0)


        def REPEAT(self):
            return self.getToken(VerilogParser.REPEAT, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_delay_or_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_or_event_control" ):
                listener.enterDelay_or_event_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_or_event_control" ):
                listener.exitDelay_or_event_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_or_event_control" ):
                return visitor.visitDelay_or_event_control(self)
            else:
                return visitor.visitChildren(self)




    def delay_or_event_control(self):

        localctx = VerilogParser.Delay_or_event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 378, self.RULE_delay_or_event_control)
        try:
            self.state = 2973
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.HA]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2965
                self.delay_control()
                pass
            elif token in [VerilogParser.AT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2966
                self.event_control()
                pass
            elif token in [VerilogParser.REPEAT]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2967
                self.match(VerilogParser.REPEAT)
                self.state = 2968
                self.match(VerilogParser.LP)
                self.state = 2969
                self.expression(0)
                self.state = 2970
                self.match(VerilogParser.RP)
                self.state = 2971
                self.event_control()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Disable_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DISABLE(self):
            return self.getToken(VerilogParser.DISABLE, 0)

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_disable_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDisable_statement" ):
                listener.enterDisable_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDisable_statement" ):
                listener.exitDisable_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDisable_statement" ):
                return visitor.visitDisable_statement(self)
            else:
                return visitor.visitChildren(self)




    def disable_statement(self):

        localctx = VerilogParser.Disable_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 380, self.RULE_disable_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2975
            self.match(VerilogParser.DISABLE)
            self.state = 2976
            self.hierarchical_identifier()
            self.state = 2977
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Event_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def AT(self):
            return self.getToken(VerilogParser.AT, 0)

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def event_expression(self):
            return self.getTypedRuleContext(VerilogParser.Event_expressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def AS(self):
            return self.getToken(VerilogParser.AS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_control" ):
                listener.enterEvent_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_control" ):
                listener.exitEvent_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_control" ):
                return visitor.visitEvent_control(self)
            else:
                return visitor.visitChildren(self)




    def event_control(self):

        localctx = VerilogParser.Event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 382, self.RULE_event_control)
        try:
            self.state = 2992
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,303,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2979
                self.match(VerilogParser.AT)
                self.state = 2980
                self.hierarchical_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2981
                self.match(VerilogParser.AT)
                self.state = 2982
                self.match(VerilogParser.LP)
                self.state = 2983
                self.event_expression(0)
                self.state = 2984
                self.match(VerilogParser.RP)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2986
                self.match(VerilogParser.AT)
                self.state = 2987
                self.match(VerilogParser.AS)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2988
                self.match(VerilogParser.AT)
                self.state = 2989
                self.match(VerilogParser.LP)
                self.state = 2990
                self.match(VerilogParser.AS)
                self.state = 2991
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Event_triggerContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MIGT(self):
            return self.getToken(VerilogParser.MIGT, 0)

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def bit_select(self):
            return self.getTypedRuleContext(VerilogParser.Bit_selectContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_event_trigger

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_trigger" ):
                listener.enterEvent_trigger(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_trigger" ):
                listener.exitEvent_trigger(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_trigger" ):
                return visitor.visitEvent_trigger(self)
            else:
                return visitor.visitChildren(self)




    def event_trigger(self):

        localctx = VerilogParser.Event_triggerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 384, self.RULE_event_trigger)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2994
            self.match(VerilogParser.MIGT)
            self.state = 2995
            self.hierarchical_identifier()
            self.state = 2997
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 2996
                self.bit_select()


            self.state = 2999
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Event_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def POSEDGE(self):
            return self.getToken(VerilogParser.POSEDGE, 0)

        def NEGEDGE(self):
            return self.getToken(VerilogParser.NEGEDGE, 0)

        def event_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Event_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Event_expressionContext,i)


        def OR(self):
            return self.getToken(VerilogParser.OR, 0)

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_event_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_expression" ):
                listener.enterEvent_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_expression" ):
                listener.exitEvent_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_expression" ):
                return visitor.visitEvent_expression(self)
            else:
                return visitor.visitChildren(self)



    def event_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.Event_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 386
        self.enterRecursionRule(localctx, 386, self.RULE_event_expression, _p)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3007
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.AM, VerilogParser.CA, VerilogParser.CATI, VerilogParser.EM, VerilogParser.LC, VerilogParser.LP, VerilogParser.MI, VerilogParser.PL, VerilogParser.TI, VerilogParser.TIAM, VerilogParser.TICA, VerilogParser.TIVL, VerilogParser.VL, VerilogParser.BINARY_BASE, VerilogParser.DECIMAL_BASE, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.EXPONENTIAL_NUMBER, VerilogParser.FIXED_POINT_NUMBER, VerilogParser.HEX_BASE, VerilogParser.OCTAL_BASE, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.STRING, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.UNSIGNED_NUMBER]:
                self.state = 3002
                self.expression(0)
                pass
            elif token in [VerilogParser.POSEDGE]:
                self.state = 3003
                self.match(VerilogParser.POSEDGE)
                self.state = 3004
                self.expression(0)
                pass
            elif token in [VerilogParser.NEGEDGE]:
                self.state = 3005
                self.match(VerilogParser.NEGEDGE)
                self.state = 3006
                self.expression(0)
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 3017
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,307,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 3015
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,306,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.Event_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_event_expression)
                        self.state = 3009
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 3010
                        self.match(VerilogParser.OR)
                        self.state = 3011
                        self.event_expression(3)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.Event_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_event_expression)
                        self.state = 3012
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 3013
                        self.match(VerilogParser.CO)
                        self.state = 3014
                        self.event_expression(2)
                        pass

             
                self.state = 3019
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,307,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx

    class Procedural_timing_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_control(self):
            return self.getTypedRuleContext(VerilogParser.Delay_controlContext,0)


        def event_control(self):
            return self.getTypedRuleContext(VerilogParser.Event_controlContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_procedural_timing_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_timing_control" ):
                listener.enterProcedural_timing_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_timing_control" ):
                listener.exitProcedural_timing_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_timing_control" ):
                return visitor.visitProcedural_timing_control(self)
            else:
                return visitor.visitChildren(self)




    def procedural_timing_control(self):

        localctx = VerilogParser.Procedural_timing_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 388, self.RULE_procedural_timing_control)
        try:
            self.state = 3022
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.HA]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3020
                self.delay_control()
                pass
            elif token in [VerilogParser.AT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3021
                self.event_control()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Procedural_timing_control_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def procedural_timing_control(self):
            return self.getTypedRuleContext(VerilogParser.Procedural_timing_controlContext,0)


        def statement_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_procedural_timing_control_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_timing_control_statement" ):
                listener.enterProcedural_timing_control_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_timing_control_statement" ):
                listener.exitProcedural_timing_control_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_timing_control_statement" ):
                return visitor.visitProcedural_timing_control_statement(self)
            else:
                return visitor.visitChildren(self)




    def procedural_timing_control_statement(self):

        localctx = VerilogParser.Procedural_timing_control_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 390, self.RULE_procedural_timing_control_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3024
            self.procedural_timing_control()
            self.state = 3025
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Wait_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def WAIT(self):
            return self.getToken(VerilogParser.WAIT, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_wait_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWait_statement" ):
                listener.enterWait_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWait_statement" ):
                listener.exitWait_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWait_statement" ):
                return visitor.visitWait_statement(self)
            else:
                return visitor.visitChildren(self)




    def wait_statement(self):

        localctx = VerilogParser.Wait_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 392, self.RULE_wait_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3027
            self.match(VerilogParser.WAIT)
            self.state = 3028
            self.match(VerilogParser.LP)
            self.state = 3029
            self.expression(0)
            self.state = 3030
            self.match(VerilogParser.RP)
            self.state = 3031
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Conditional_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def IF(self):
            return self.getToken(VerilogParser.IF, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Statement_or_nullContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,i)


        def ELSE(self):
            return self.getToken(VerilogParser.ELSE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_conditional_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConditional_statement" ):
                listener.enterConditional_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConditional_statement" ):
                listener.exitConditional_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConditional_statement" ):
                return visitor.visitConditional_statement(self)
            else:
                return visitor.visitChildren(self)




    def conditional_statement(self):

        localctx = VerilogParser.Conditional_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 394, self.RULE_conditional_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3033
            self.match(VerilogParser.IF)
            self.state = 3034
            self.match(VerilogParser.LP)
            self.state = 3035
            self.expression(0)
            self.state = 3036
            self.match(VerilogParser.RP)
            self.state = 3037
            self.statement_or_null()
            self.state = 3040
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,309,self._ctx)
            if la_ == 1:
                self.state = 3038
                self.match(VerilogParser.ELSE)
                self.state = 3039
                self.statement_or_null()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Case_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CASE(self):
            return self.getToken(VerilogParser.CASE, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def ENDCASE(self):
            return self.getToken(VerilogParser.ENDCASE, 0)

        def case_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Case_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Case_itemContext,i)


        def CASEZ(self):
            return self.getToken(VerilogParser.CASEZ, 0)

        def CASEX(self):
            return self.getToken(VerilogParser.CASEX, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_case_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_statement" ):
                listener.enterCase_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_statement" ):
                listener.exitCase_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_statement" ):
                return visitor.visitCase_statement(self)
            else:
                return visitor.visitChildren(self)




    def case_statement(self):

        localctx = VerilogParser.Case_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 396, self.RULE_case_statement)
        self._la = 0 # Token type
        try:
            self.state = 3075
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.CASE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3042
                self.match(VerilogParser.CASE)
                self.state = 3043
                self.match(VerilogParser.LP)
                self.state = 3044
                self.expression(0)
                self.state = 3045
                self.match(VerilogParser.RP)
                self.state = 3047 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while True:
                    self.state = 3046
                    self.case_item()
                    self.state = 3049 
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if not (_la==VerilogParser.DEFAULT or ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER):
                        break

                self.state = 3051
                self.match(VerilogParser.ENDCASE)
                pass
            elif token in [VerilogParser.CASEZ]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3053
                self.match(VerilogParser.CASEZ)
                self.state = 3054
                self.match(VerilogParser.LP)
                self.state = 3055
                self.expression(0)
                self.state = 3056
                self.match(VerilogParser.RP)
                self.state = 3058 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while True:
                    self.state = 3057
                    self.case_item()
                    self.state = 3060 
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if not (_la==VerilogParser.DEFAULT or ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER):
                        break

                self.state = 3062
                self.match(VerilogParser.ENDCASE)
                pass
            elif token in [VerilogParser.CASEX]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3064
                self.match(VerilogParser.CASEX)
                self.state = 3065
                self.match(VerilogParser.LP)
                self.state = 3066
                self.expression(0)
                self.state = 3067
                self.match(VerilogParser.RP)
                self.state = 3069 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while True:
                    self.state = 3068
                    self.case_item()
                    self.state = 3071 
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if not (_la==VerilogParser.DEFAULT or ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER):
                        break

                self.state = 3073
                self.match(VerilogParser.ENDCASE)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Case_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def DEFAULT(self):
            return self.getToken(VerilogParser.DEFAULT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_case_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_item" ):
                listener.enterCase_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_item" ):
                listener.exitCase_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_item" ):
                return visitor.visitCase_item(self)
            else:
                return visitor.visitChildren(self)




    def case_item(self):

        localctx = VerilogParser.Case_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 398, self.RULE_case_item)
        self._la = 0 # Token type
        try:
            self.state = 3093
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.AM, VerilogParser.CA, VerilogParser.CATI, VerilogParser.EM, VerilogParser.LC, VerilogParser.LP, VerilogParser.MI, VerilogParser.PL, VerilogParser.TI, VerilogParser.TIAM, VerilogParser.TICA, VerilogParser.TIVL, VerilogParser.VL, VerilogParser.BINARY_BASE, VerilogParser.DECIMAL_BASE, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.EXPONENTIAL_NUMBER, VerilogParser.FIXED_POINT_NUMBER, VerilogParser.HEX_BASE, VerilogParser.OCTAL_BASE, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.STRING, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.UNSIGNED_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3077
                self.expression(0)
                self.state = 3082
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 3078
                    self.match(VerilogParser.CO)
                    self.state = 3079
                    self.expression(0)
                    self.state = 3084
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3085
                self.match(VerilogParser.CL)
                self.state = 3086
                self.statement_or_null()
                pass
            elif token in [VerilogParser.DEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3088
                self.match(VerilogParser.DEFAULT)
                self.state = 3090
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CL:
                    self.state = 3089
                    self.match(VerilogParser.CL)


                self.state = 3092
                self.statement_or_null()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FOREVER(self):
            return self.getToken(VerilogParser.FOREVER, 0)

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def REPEAT(self):
            return self.getToken(VerilogParser.REPEAT, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def WHILE(self):
            return self.getToken(VerilogParser.WHILE, 0)

        def FOR(self):
            return self.getToken(VerilogParser.FOR, 0)

        def variable_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Variable_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Variable_assignmentContext,i)


        def SC(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.SC)
            else:
                return self.getToken(VerilogParser.SC, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_statement" ):
                listener.enterLoop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_statement" ):
                listener.exitLoop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_statement" ):
                return visitor.visitLoop_statement(self)
            else:
                return visitor.visitChildren(self)




    def loop_statement(self):

        localctx = VerilogParser.Loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 400, self.RULE_loop_statement)
        try:
            self.state = 3119
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.FOREVER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3095
                self.match(VerilogParser.FOREVER)
                self.state = 3096
                self.statement()
                pass
            elif token in [VerilogParser.REPEAT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3097
                self.match(VerilogParser.REPEAT)
                self.state = 3098
                self.match(VerilogParser.LP)
                self.state = 3099
                self.expression(0)
                self.state = 3100
                self.match(VerilogParser.RP)
                self.state = 3101
                self.statement()
                pass
            elif token in [VerilogParser.WHILE]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3103
                self.match(VerilogParser.WHILE)
                self.state = 3104
                self.match(VerilogParser.LP)
                self.state = 3105
                self.expression(0)
                self.state = 3106
                self.match(VerilogParser.RP)
                self.state = 3107
                self.statement()
                pass
            elif token in [VerilogParser.FOR]:
                self.enterOuterAlt(localctx, 4)
                self.state = 3109
                self.match(VerilogParser.FOR)
                self.state = 3110
                self.match(VerilogParser.LP)
                self.state = 3111
                self.variable_assignment()
                self.state = 3112
                self.match(VerilogParser.SC)
                self.state = 3113
                self.expression(0)
                self.state = 3114
                self.match(VerilogParser.SC)
                self.state = 3115
                self.variable_assignment()
                self.state = 3116
                self.match(VerilogParser.RP)
                self.state = 3117
                self.statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class System_task_enableContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def system_task_identifier(self):
            return self.getTypedRuleContext(VerilogParser.System_task_identifierContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def sys_task_en_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Sys_task_en_port_listContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_system_task_enable

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_task_enable" ):
                listener.enterSystem_task_enable(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_task_enable" ):
                listener.exitSystem_task_enable(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_task_enable" ):
                return visitor.visitSystem_task_enable(self)
            else:
                return visitor.visitChildren(self)




    def system_task_enable(self):

        localctx = VerilogParser.System_task_enableContext(self, self._ctx, self.state)
        self.enterRule(localctx, 402, self.RULE_system_task_enable)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3121
            self.system_task_identifier()
            self.state = 3123
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LP:
                self.state = 3122
                self.sys_task_en_port_list()


            self.state = 3125
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Sys_task_en_port_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def sys_task_en_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Sys_task_en_port_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Sys_task_en_port_itemContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_sys_task_en_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSys_task_en_port_list" ):
                listener.enterSys_task_en_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSys_task_en_port_list" ):
                listener.exitSys_task_en_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSys_task_en_port_list" ):
                return visitor.visitSys_task_en_port_list(self)
            else:
                return visitor.visitChildren(self)




    def sys_task_en_port_list(self):

        localctx = VerilogParser.Sys_task_en_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 404, self.RULE_sys_task_en_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3127
            self.match(VerilogParser.LP)
            self.state = 3128
            self.sys_task_en_port_item()
            self.state = 3133
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3129
                self.match(VerilogParser.CO)
                self.state = 3130
                self.sys_task_en_port_item()
                self.state = 3135
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3136
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Sys_task_en_port_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_sys_task_en_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSys_task_en_port_item" ):
                listener.enterSys_task_en_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSys_task_en_port_item" ):
                listener.exitSys_task_en_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSys_task_en_port_item" ):
                return visitor.visitSys_task_en_port_item(self)
            else:
                return visitor.visitChildren(self)




    def sys_task_en_port_item(self):

        localctx = VerilogParser.Sys_task_en_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 406, self.RULE_sys_task_en_port_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3139
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 3138
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Task_enableContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def task_en_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Task_en_port_listContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_enable

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_enable" ):
                listener.enterTask_enable(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_enable" ):
                listener.exitTask_enable(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_enable" ):
                return visitor.visitTask_enable(self)
            else:
                return visitor.visitChildren(self)




    def task_enable(self):

        localctx = VerilogParser.Task_enableContext(self, self._ctx, self.state)
        self.enterRule(localctx, 408, self.RULE_task_enable)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3141
            self.hierarchical_identifier()
            self.state = 3143
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LP:
                self.state = 3142
                self.task_en_port_list()


            self.state = 3145
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Task_en_port_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_task_en_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_en_port_list" ):
                listener.enterTask_en_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_en_port_list" ):
                listener.exitTask_en_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_en_port_list" ):
                return visitor.visitTask_en_port_list(self)
            else:
                return visitor.visitChildren(self)




    def task_en_port_list(self):

        localctx = VerilogParser.Task_en_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 410, self.RULE_task_en_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3147
            self.match(VerilogParser.LP)
            self.state = 3148
            self.expression(0)
            self.state = 3153
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3149
                self.match(VerilogParser.CO)
                self.state = 3150
                self.expression(0)
                self.state = 3155
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3156
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Specify_blockContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SPECIFY(self):
            return self.getToken(VerilogParser.SPECIFY, 0)

        def ENDSPECIFY(self):
            return self.getToken(VerilogParser.ENDSPECIFY, 0)

        def specify_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Specify_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Specify_itemContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_specify_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_block" ):
                listener.enterSpecify_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_block" ):
                listener.exitSpecify_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_block" ):
                return visitor.visitSpecify_block(self)
            else:
                return visitor.visitChildren(self)




    def specify_block(self):

        localctx = VerilogParser.Specify_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 412, self.RULE_specify_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3158
            self.match(VerilogParser.SPECIFY)
            self.state = 3162
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.DLFULLSKEW) | (1 << VerilogParser.DLHOLD) | (1 << VerilogParser.DLNOCHANGE) | (1 << VerilogParser.DLPERIOD) | (1 << VerilogParser.DLRECOVERY) | (1 << VerilogParser.DLRECREM) | (1 << VerilogParser.DLREMOVAL) | (1 << VerilogParser.DLSETUP) | (1 << VerilogParser.DLSETUPHOLD) | (1 << VerilogParser.DLSKEW) | (1 << VerilogParser.DLTIMESKEW) | (1 << VerilogParser.DLWIDTH) | (1 << VerilogParser.IF) | (1 << VerilogParser.IFNONE))) != 0) or ((((_la - 75)) & ~0x3f) == 0 and ((1 << (_la - 75)) & ((1 << (VerilogParser.NOSHOWCANCELLED - 75)) | (1 << (VerilogParser.PULSESTYLE_ONDETECT - 75)) | (1 << (VerilogParser.PULSESTYLE_ONEVENT - 75)) | (1 << (VerilogParser.SHOWCANCELLED - 75)) | (1 << (VerilogParser.SPECPARAM - 75)))) != 0) or _la==VerilogParser.LP:
                self.state = 3159
                self.specify_item()
                self.state = 3164
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3165
            self.match(VerilogParser.ENDSPECIFY)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Specify_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Specparam_declarationContext,0)


        def pulsestyle_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Pulsestyle_declarationContext,0)


        def showcancelled_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Showcancelled_declarationContext,0)


        def path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Path_declarationContext,0)


        def system_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.System_timing_checkContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specify_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_item" ):
                listener.enterSpecify_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_item" ):
                listener.exitSpecify_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_item" ):
                return visitor.visitSpecify_item(self)
            else:
                return visitor.visitChildren(self)




    def specify_item(self):

        localctx = VerilogParser.Specify_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 414, self.RULE_specify_item)
        try:
            self.state = 3172
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.SPECPARAM]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3167
                self.specparam_declaration()
                pass
            elif token in [VerilogParser.PULSESTYLE_ONDETECT, VerilogParser.PULSESTYLE_ONEVENT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3168
                self.pulsestyle_declaration()
                pass
            elif token in [VerilogParser.NOSHOWCANCELLED, VerilogParser.SHOWCANCELLED]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3169
                self.showcancelled_declaration()
                pass
            elif token in [VerilogParser.IF, VerilogParser.IFNONE, VerilogParser.LP]:
                self.enterOuterAlt(localctx, 4)
                self.state = 3170
                self.path_declaration()
                pass
            elif token in [VerilogParser.DLFULLSKEW, VerilogParser.DLHOLD, VerilogParser.DLNOCHANGE, VerilogParser.DLPERIOD, VerilogParser.DLRECOVERY, VerilogParser.DLRECREM, VerilogParser.DLREMOVAL, VerilogParser.DLSETUP, VerilogParser.DLSETUPHOLD, VerilogParser.DLSKEW, VerilogParser.DLTIMESKEW, VerilogParser.DLWIDTH]:
                self.enterOuterAlt(localctx, 5)
                self.state = 3171
                self.system_timing_check()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Pulsestyle_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PULSESTYLE_ONEVENT(self):
            return self.getToken(VerilogParser.PULSESTYLE_ONEVENT, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_outputsContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def PULSESTYLE_ONDETECT(self):
            return self.getToken(VerilogParser.PULSESTYLE_ONDETECT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pulsestyle_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulsestyle_declaration" ):
                listener.enterPulsestyle_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulsestyle_declaration" ):
                listener.exitPulsestyle_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulsestyle_declaration" ):
                return visitor.visitPulsestyle_declaration(self)
            else:
                return visitor.visitChildren(self)




    def pulsestyle_declaration(self):

        localctx = VerilogParser.Pulsestyle_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 416, self.RULE_pulsestyle_declaration)
        try:
            self.state = 3182
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.PULSESTYLE_ONEVENT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3174
                self.match(VerilogParser.PULSESTYLE_ONEVENT)
                self.state = 3175
                self.list_of_path_outputs()
                self.state = 3176
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.PULSESTYLE_ONDETECT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3178
                self.match(VerilogParser.PULSESTYLE_ONDETECT)
                self.state = 3179
                self.list_of_path_outputs()
                self.state = 3180
                self.match(VerilogParser.SC)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Showcancelled_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SHOWCANCELLED(self):
            return self.getToken(VerilogParser.SHOWCANCELLED, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_outputsContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def NOSHOWCANCELLED(self):
            return self.getToken(VerilogParser.NOSHOWCANCELLED, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_showcancelled_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterShowcancelled_declaration" ):
                listener.enterShowcancelled_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitShowcancelled_declaration" ):
                listener.exitShowcancelled_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitShowcancelled_declaration" ):
                return visitor.visitShowcancelled_declaration(self)
            else:
                return visitor.visitChildren(self)




    def showcancelled_declaration(self):

        localctx = VerilogParser.Showcancelled_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 418, self.RULE_showcancelled_declaration)
        try:
            self.state = 3192
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.SHOWCANCELLED]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3184
                self.match(VerilogParser.SHOWCANCELLED)
                self.state = 3185
                self.list_of_path_outputs()
                self.state = 3186
                self.match(VerilogParser.SC)
                pass
            elif token in [VerilogParser.NOSHOWCANCELLED]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3188
                self.match(VerilogParser.NOSHOWCANCELLED)
                self.state = 3189
                self.list_of_path_outputs()
                self.state = 3190
                self.match(VerilogParser.SC)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Path_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def simple_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Simple_path_declarationContext,0)


        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def edge_sensitive_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Edge_sensitive_path_declarationContext,0)


        def state_dependent_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.State_dependent_path_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_declaration" ):
                listener.enterPath_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_declaration" ):
                listener.exitPath_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_declaration" ):
                return visitor.visitPath_declaration(self)
            else:
                return visitor.visitChildren(self)




    def path_declaration(self):

        localctx = VerilogParser.Path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 420, self.RULE_path_declaration)
        try:
            self.state = 3203
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,327,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3194
                self.simple_path_declaration()
                self.state = 3195
                self.match(VerilogParser.SC)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3197
                self.edge_sensitive_path_declaration()
                self.state = 3198
                self.match(VerilogParser.SC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3200
                self.state_dependent_path_declaration()
                self.state = 3201
                self.match(VerilogParser.SC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Simple_path_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parallel_path_description(self):
            return self.getTypedRuleContext(VerilogParser.Parallel_path_descriptionContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def path_delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_valueContext,0)


        def full_path_description(self):
            return self.getTypedRuleContext(VerilogParser.Full_path_descriptionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_simple_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_path_declaration" ):
                listener.enterSimple_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_path_declaration" ):
                listener.exitSimple_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_path_declaration" ):
                return visitor.visitSimple_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def simple_path_declaration(self):

        localctx = VerilogParser.Simple_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 422, self.RULE_simple_path_declaration)
        try:
            self.state = 3213
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,328,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3205
                self.parallel_path_description()
                self.state = 3206
                self.match(VerilogParser.EQ)
                self.state = 3207
                self.path_delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3209
                self.full_path_description()
                self.state = 3210
                self.match(VerilogParser.EQ)
                self.state = 3211
                self.path_delay_value()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Parallel_path_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,0)


        def EQGT(self):
            return self.getToken(VerilogParser.EQGT, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def polarity_operator(self):
            return self.getTypedRuleContext(VerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_parallel_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParallel_path_description" ):
                listener.enterParallel_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParallel_path_description" ):
                listener.exitParallel_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParallel_path_description" ):
                return visitor.visitParallel_path_description(self)
            else:
                return visitor.visitChildren(self)




    def parallel_path_description(self):

        localctx = VerilogParser.Parallel_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 424, self.RULE_parallel_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3215
            self.match(VerilogParser.LP)
            self.state = 3216
            self.specify_input_terminal_descriptor()
            self.state = 3218
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.MI or _la==VerilogParser.PL:
                self.state = 3217
                self.polarity_operator()


            self.state = 3220
            self.match(VerilogParser.EQGT)
            self.state = 3221
            self.specify_output_terminal_descriptor()
            self.state = 3222
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Full_path_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def list_of_path_inputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_inputsContext,0)


        def ASGT(self):
            return self.getToken(VerilogParser.ASGT, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_outputsContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def polarity_operator(self):
            return self.getTypedRuleContext(VerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_full_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFull_path_description" ):
                listener.enterFull_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFull_path_description" ):
                listener.exitFull_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFull_path_description" ):
                return visitor.visitFull_path_description(self)
            else:
                return visitor.visitChildren(self)




    def full_path_description(self):

        localctx = VerilogParser.Full_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 426, self.RULE_full_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3224
            self.match(VerilogParser.LP)
            self.state = 3225
            self.list_of_path_inputs()
            self.state = 3227
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.MI or _la==VerilogParser.PL:
                self.state = 3226
                self.polarity_operator()


            self.state = 3229
            self.match(VerilogParser.ASGT)
            self.state = 3230
            self.list_of_path_outputs()
            self.state = 3231
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_path_inputsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specify_input_terminal_descriptor(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Specify_input_terminal_descriptorContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_path_inputs

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_inputs" ):
                listener.enterList_of_path_inputs(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_inputs" ):
                listener.exitList_of_path_inputs(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_inputs" ):
                return visitor.visitList_of_path_inputs(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_inputs(self):

        localctx = VerilogParser.List_of_path_inputsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 428, self.RULE_list_of_path_inputs)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3233
            self.specify_input_terminal_descriptor()
            self.state = 3238
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3234
                self.match(VerilogParser.CO)
                self.state = 3235
                self.specify_input_terminal_descriptor()
                self.state = 3240
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_path_outputsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specify_output_terminal_descriptor(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Specify_output_terminal_descriptorContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_path_outputs

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_outputs" ):
                listener.enterList_of_path_outputs(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_outputs" ):
                listener.exitList_of_path_outputs(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_outputs" ):
                return visitor.visitList_of_path_outputs(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_outputs(self):

        localctx = VerilogParser.List_of_path_outputsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 430, self.RULE_list_of_path_outputs)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3241
            self.specify_output_terminal_descriptor()
            self.state = 3246
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3242
                self.match(VerilogParser.CO)
                self.state = 3243
                self.specify_output_terminal_descriptor()
                self.state = 3248
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Specify_input_terminal_descriptorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def input_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Input_identifierContext,0)


        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_specify_input_terminal_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_input_terminal_descriptor" ):
                listener.enterSpecify_input_terminal_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_input_terminal_descriptor" ):
                listener.exitSpecify_input_terminal_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_input_terminal_descriptor" ):
                return visitor.visitSpecify_input_terminal_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def specify_input_terminal_descriptor(self):

        localctx = VerilogParser.Specify_input_terminal_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 432, self.RULE_specify_input_terminal_descriptor)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3249
            self.input_identifier()
            self.state = 3254
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 3250
                self.match(VerilogParser.LB)
                self.state = 3251
                self.constant_range_expression()
                self.state = 3252
                self.match(VerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Specify_output_terminal_descriptorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def output_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Output_identifierContext,0)


        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_specify_output_terminal_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_output_terminal_descriptor" ):
                listener.enterSpecify_output_terminal_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_output_terminal_descriptor" ):
                listener.exitSpecify_output_terminal_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_output_terminal_descriptor" ):
                return visitor.visitSpecify_output_terminal_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def specify_output_terminal_descriptor(self):

        localctx = VerilogParser.Specify_output_terminal_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 434, self.RULE_specify_output_terminal_descriptor)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3256
            self.output_identifier()
            self.state = 3261
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 3257
                self.match(VerilogParser.LB)
                self.state = 3258
                self.constant_range_expression()
                self.state = 3259
                self.match(VerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Input_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_input_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_identifier" ):
                listener.enterInput_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_identifier" ):
                listener.exitInput_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_identifier" ):
                return visitor.visitInput_identifier(self)
            else:
                return visitor.visitChildren(self)




    def input_identifier(self):

        localctx = VerilogParser.Input_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 436, self.RULE_input_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3263
            self.port_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Output_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_output_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_identifier" ):
                listener.enterOutput_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_identifier" ):
                listener.exitOutput_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_identifier" ):
                return visitor.visitOutput_identifier(self)
            else:
                return visitor.visitChildren(self)




    def output_identifier(self):

        localctx = VerilogParser.Output_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 438, self.RULE_output_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3265
            self.port_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Path_delay_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_path_delay_expressions(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_delay_expressionsContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_path_delay_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_delay_value" ):
                listener.enterPath_delay_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_delay_value" ):
                listener.exitPath_delay_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_delay_value" ):
                return visitor.visitPath_delay_value(self)
            else:
                return visitor.visitChildren(self)




    def path_delay_value(self):

        localctx = VerilogParser.Path_delay_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 440, self.RULE_path_delay_value)
        try:
            self.state = 3272
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,335,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3267
                self.list_of_path_delay_expressions()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3268
                self.match(VerilogParser.LP)
                self.state = 3269
                self.list_of_path_delay_expressions()
                self.state = 3270
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class List_of_path_delay_expressionsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def t_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T_path_delay_expressionContext,0)


        def trise_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Trise_path_delay_expressionContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def tfall_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tfall_path_delay_expressionContext,0)


        def tz_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tz_path_delay_expressionContext,0)


        def t01_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T01_path_delay_expressionContext,0)


        def t10_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T10_path_delay_expressionContext,0)


        def t0z_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T0z_path_delay_expressionContext,0)


        def tz1_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tz1_path_delay_expressionContext,0)


        def t1z_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T1z_path_delay_expressionContext,0)


        def tz0_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tz0_path_delay_expressionContext,0)


        def t0x_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T0x_path_delay_expressionContext,0)


        def tx1_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tx1_path_delay_expressionContext,0)


        def t1x_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T1x_path_delay_expressionContext,0)


        def tx0_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tx0_path_delay_expressionContext,0)


        def txz_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Txz_path_delay_expressionContext,0)


        def tzx_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tzx_path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_path_delay_expressions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_delay_expressions" ):
                listener.enterList_of_path_delay_expressions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_delay_expressions" ):
                listener.exitList_of_path_delay_expressions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_delay_expressions" ):
                return visitor.visitList_of_path_delay_expressions(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_delay_expressions(self):

        localctx = VerilogParser.List_of_path_delay_expressionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 442, self.RULE_list_of_path_delay_expressions)
        self._la = 0 # Token type
        try:
            self.state = 3308
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,338,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3274
                self.t_path_delay_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3275
                self.trise_path_delay_expression()
                self.state = 3276
                self.match(VerilogParser.CO)
                self.state = 3277
                self.tfall_path_delay_expression()
                self.state = 3280
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CO:
                    self.state = 3278
                    self.match(VerilogParser.CO)
                    self.state = 3279
                    self.tz_path_delay_expression()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3282
                self.t01_path_delay_expression()
                self.state = 3283
                self.match(VerilogParser.CO)
                self.state = 3284
                self.t10_path_delay_expression()
                self.state = 3285
                self.match(VerilogParser.CO)
                self.state = 3286
                self.t0z_path_delay_expression()
                self.state = 3287
                self.match(VerilogParser.CO)
                self.state = 3288
                self.tz1_path_delay_expression()
                self.state = 3289
                self.match(VerilogParser.CO)
                self.state = 3290
                self.t1z_path_delay_expression()
                self.state = 3291
                self.match(VerilogParser.CO)
                self.state = 3292
                self.tz0_path_delay_expression()
                self.state = 3306
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.CO:
                    self.state = 3293
                    self.match(VerilogParser.CO)
                    self.state = 3294
                    self.t0x_path_delay_expression()
                    self.state = 3295
                    self.match(VerilogParser.CO)
                    self.state = 3296
                    self.tx1_path_delay_expression()
                    self.state = 3297
                    self.match(VerilogParser.CO)
                    self.state = 3298
                    self.t1x_path_delay_expression()
                    self.state = 3299
                    self.match(VerilogParser.CO)
                    self.state = 3300
                    self.tx0_path_delay_expression()
                    self.state = 3301
                    self.match(VerilogParser.CO)
                    self.state = 3302
                    self.txz_path_delay_expression()
                    self.state = 3303
                    self.match(VerilogParser.CO)
                    self.state = 3304
                    self.tzx_path_delay_expression()


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class T_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT_path_delay_expression" ):
                listener.enterT_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT_path_delay_expression" ):
                listener.exitT_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT_path_delay_expression" ):
                return visitor.visitT_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t_path_delay_expression(self):

        localctx = VerilogParser.T_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 444, self.RULE_t_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3310
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Trise_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_trise_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTrise_path_delay_expression" ):
                listener.enterTrise_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTrise_path_delay_expression" ):
                listener.exitTrise_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTrise_path_delay_expression" ):
                return visitor.visitTrise_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def trise_path_delay_expression(self):

        localctx = VerilogParser.Trise_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 446, self.RULE_trise_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3312
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tfall_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tfall_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTfall_path_delay_expression" ):
                listener.enterTfall_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTfall_path_delay_expression" ):
                listener.exitTfall_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTfall_path_delay_expression" ):
                return visitor.visitTfall_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tfall_path_delay_expression(self):

        localctx = VerilogParser.Tfall_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 448, self.RULE_tfall_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3314
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tz_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tz_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz_path_delay_expression" ):
                listener.enterTz_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz_path_delay_expression" ):
                listener.exitTz_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz_path_delay_expression" ):
                return visitor.visitTz_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz_path_delay_expression(self):

        localctx = VerilogParser.Tz_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 450, self.RULE_tz_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3316
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class T01_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t01_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT01_path_delay_expression" ):
                listener.enterT01_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT01_path_delay_expression" ):
                listener.exitT01_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT01_path_delay_expression" ):
                return visitor.visitT01_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t01_path_delay_expression(self):

        localctx = VerilogParser.T01_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 452, self.RULE_t01_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3318
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class T10_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t10_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT10_path_delay_expression" ):
                listener.enterT10_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT10_path_delay_expression" ):
                listener.exitT10_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT10_path_delay_expression" ):
                return visitor.visitT10_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t10_path_delay_expression(self):

        localctx = VerilogParser.T10_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 454, self.RULE_t10_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3320
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class T0z_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t0z_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT0z_path_delay_expression" ):
                listener.enterT0z_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT0z_path_delay_expression" ):
                listener.exitT0z_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT0z_path_delay_expression" ):
                return visitor.visitT0z_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t0z_path_delay_expression(self):

        localctx = VerilogParser.T0z_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 456, self.RULE_t0z_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3322
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tz1_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tz1_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz1_path_delay_expression" ):
                listener.enterTz1_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz1_path_delay_expression" ):
                listener.exitTz1_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz1_path_delay_expression" ):
                return visitor.visitTz1_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz1_path_delay_expression(self):

        localctx = VerilogParser.Tz1_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 458, self.RULE_tz1_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3324
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class T1z_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t1z_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT1z_path_delay_expression" ):
                listener.enterT1z_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT1z_path_delay_expression" ):
                listener.exitT1z_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT1z_path_delay_expression" ):
                return visitor.visitT1z_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t1z_path_delay_expression(self):

        localctx = VerilogParser.T1z_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 460, self.RULE_t1z_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3326
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tz0_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tz0_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz0_path_delay_expression" ):
                listener.enterTz0_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz0_path_delay_expression" ):
                listener.exitTz0_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz0_path_delay_expression" ):
                return visitor.visitTz0_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz0_path_delay_expression(self):

        localctx = VerilogParser.Tz0_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 462, self.RULE_tz0_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3328
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class T0x_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t0x_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT0x_path_delay_expression" ):
                listener.enterT0x_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT0x_path_delay_expression" ):
                listener.exitT0x_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT0x_path_delay_expression" ):
                return visitor.visitT0x_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t0x_path_delay_expression(self):

        localctx = VerilogParser.T0x_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 464, self.RULE_t0x_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3330
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tx1_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tx1_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTx1_path_delay_expression" ):
                listener.enterTx1_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTx1_path_delay_expression" ):
                listener.exitTx1_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTx1_path_delay_expression" ):
                return visitor.visitTx1_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tx1_path_delay_expression(self):

        localctx = VerilogParser.Tx1_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 466, self.RULE_tx1_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3332
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class T1x_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t1x_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT1x_path_delay_expression" ):
                listener.enterT1x_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT1x_path_delay_expression" ):
                listener.exitT1x_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT1x_path_delay_expression" ):
                return visitor.visitT1x_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t1x_path_delay_expression(self):

        localctx = VerilogParser.T1x_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 468, self.RULE_t1x_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3334
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tx0_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tx0_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTx0_path_delay_expression" ):
                listener.enterTx0_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTx0_path_delay_expression" ):
                listener.exitTx0_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTx0_path_delay_expression" ):
                return visitor.visitTx0_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tx0_path_delay_expression(self):

        localctx = VerilogParser.Tx0_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 470, self.RULE_tx0_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3336
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Txz_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_txz_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTxz_path_delay_expression" ):
                listener.enterTxz_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTxz_path_delay_expression" ):
                listener.exitTxz_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTxz_path_delay_expression" ):
                return visitor.visitTxz_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def txz_path_delay_expression(self):

        localctx = VerilogParser.Txz_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 472, self.RULE_txz_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3338
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Tzx_path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tzx_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTzx_path_delay_expression" ):
                listener.enterTzx_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTzx_path_delay_expression" ):
                listener.exitTzx_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTzx_path_delay_expression" ):
                return visitor.visitTzx_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tzx_path_delay_expression(self):

        localctx = VerilogParser.Tzx_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 474, self.RULE_tzx_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3340
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Path_delay_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_delay_expression" ):
                listener.enterPath_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_delay_expression" ):
                listener.exitPath_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_delay_expression" ):
                return visitor.visitPath_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def path_delay_expression(self):

        localctx = VerilogParser.Path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 476, self.RULE_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3342
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Edge_sensitive_path_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parallel_edge_sensitive_path_description(self):
            return self.getTypedRuleContext(VerilogParser.Parallel_edge_sensitive_path_descriptionContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def path_delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_valueContext,0)


        def full_edge_sensitive_path_description(self):
            return self.getTypedRuleContext(VerilogParser.Full_edge_sensitive_path_descriptionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_edge_sensitive_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_sensitive_path_declaration" ):
                listener.enterEdge_sensitive_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_sensitive_path_declaration" ):
                listener.exitEdge_sensitive_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_sensitive_path_declaration" ):
                return visitor.visitEdge_sensitive_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def edge_sensitive_path_declaration(self):

        localctx = VerilogParser.Edge_sensitive_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 478, self.RULE_edge_sensitive_path_declaration)
        try:
            self.state = 3352
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,339,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3344
                self.parallel_edge_sensitive_path_description()
                self.state = 3345
                self.match(VerilogParser.EQ)
                self.state = 3346
                self.path_delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3348
                self.full_edge_sensitive_path_description()
                self.state = 3349
                self.match(VerilogParser.EQ)
                self.state = 3350
                self.path_delay_value()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Parallel_edge_sensitive_path_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LP)
            else:
                return self.getToken(VerilogParser.LP, i)

        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,0)


        def EQGT(self):
            return self.getToken(VerilogParser.EQGT, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,0)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def data_source_expression(self):
            return self.getTypedRuleContext(VerilogParser.Data_source_expressionContext,0)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RP)
            else:
                return self.getToken(VerilogParser.RP, i)

        def edge_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Edge_identifierContext,0)


        def polarity_operator(self):
            return self.getTypedRuleContext(VerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_parallel_edge_sensitive_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParallel_edge_sensitive_path_description" ):
                listener.enterParallel_edge_sensitive_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParallel_edge_sensitive_path_description" ):
                listener.exitParallel_edge_sensitive_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParallel_edge_sensitive_path_description" ):
                return visitor.visitParallel_edge_sensitive_path_description(self)
            else:
                return visitor.visitChildren(self)




    def parallel_edge_sensitive_path_description(self):

        localctx = VerilogParser.Parallel_edge_sensitive_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 480, self.RULE_parallel_edge_sensitive_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3354
            self.match(VerilogParser.LP)
            self.state = 3356
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.NEGEDGE or _la==VerilogParser.POSEDGE:
                self.state = 3355
                self.edge_identifier()


            self.state = 3358
            self.specify_input_terminal_descriptor()
            self.state = 3359
            self.match(VerilogParser.EQGT)
            self.state = 3360
            self.match(VerilogParser.LP)
            self.state = 3361
            self.specify_output_terminal_descriptor()
            self.state = 3363
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.MI or _la==VerilogParser.PL:
                self.state = 3362
                self.polarity_operator()


            self.state = 3365
            self.match(VerilogParser.CL)
            self.state = 3366
            self.data_source_expression()
            self.state = 3367
            self.match(VerilogParser.RP)
            self.state = 3368
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Full_edge_sensitive_path_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LP)
            else:
                return self.getToken(VerilogParser.LP, i)

        def list_of_path_inputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_inputsContext,0)


        def ASGT(self):
            return self.getToken(VerilogParser.ASGT, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_outputsContext,0)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def data_source_expression(self):
            return self.getTypedRuleContext(VerilogParser.Data_source_expressionContext,0)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RP)
            else:
                return self.getToken(VerilogParser.RP, i)

        def edge_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Edge_identifierContext,0)


        def polarity_operator(self):
            return self.getTypedRuleContext(VerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_full_edge_sensitive_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFull_edge_sensitive_path_description" ):
                listener.enterFull_edge_sensitive_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFull_edge_sensitive_path_description" ):
                listener.exitFull_edge_sensitive_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFull_edge_sensitive_path_description" ):
                return visitor.visitFull_edge_sensitive_path_description(self)
            else:
                return visitor.visitChildren(self)




    def full_edge_sensitive_path_description(self):

        localctx = VerilogParser.Full_edge_sensitive_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 482, self.RULE_full_edge_sensitive_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3370
            self.match(VerilogParser.LP)
            self.state = 3372
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.NEGEDGE or _la==VerilogParser.POSEDGE:
                self.state = 3371
                self.edge_identifier()


            self.state = 3374
            self.list_of_path_inputs()
            self.state = 3375
            self.match(VerilogParser.ASGT)
            self.state = 3376
            self.match(VerilogParser.LP)
            self.state = 3377
            self.list_of_path_outputs()
            self.state = 3379
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.MI or _la==VerilogParser.PL:
                self.state = 3378
                self.polarity_operator()


            self.state = 3381
            self.match(VerilogParser.CL)
            self.state = 3382
            self.data_source_expression()
            self.state = 3383
            self.match(VerilogParser.RP)
            self.state = 3384
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Data_source_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_data_source_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterData_source_expression" ):
                listener.enterData_source_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitData_source_expression" ):
                listener.exitData_source_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitData_source_expression" ):
                return visitor.visitData_source_expression(self)
            else:
                return visitor.visitChildren(self)




    def data_source_expression(self):

        localctx = VerilogParser.Data_source_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 484, self.RULE_data_source_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3386
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Edge_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def POSEDGE(self):
            return self.getToken(VerilogParser.POSEDGE, 0)

        def NEGEDGE(self):
            return self.getToken(VerilogParser.NEGEDGE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_edge_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_identifier" ):
                listener.enterEdge_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_identifier" ):
                listener.exitEdge_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_identifier" ):
                return visitor.visitEdge_identifier(self)
            else:
                return visitor.visitChildren(self)




    def edge_identifier(self):

        localctx = VerilogParser.Edge_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 486, self.RULE_edge_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3388
            _la = self._input.LA(1)
            if not(_la==VerilogParser.NEGEDGE or _la==VerilogParser.POSEDGE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class State_dependent_path_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def IF(self):
            return self.getToken(VerilogParser.IF, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def module_path_expression(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_expressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def simple_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Simple_path_declarationContext,0)


        def edge_sensitive_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Edge_sensitive_path_declarationContext,0)


        def IFNONE(self):
            return self.getToken(VerilogParser.IFNONE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_state_dependent_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterState_dependent_path_declaration" ):
                listener.enterState_dependent_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitState_dependent_path_declaration" ):
                listener.exitState_dependent_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitState_dependent_path_declaration" ):
                return visitor.visitState_dependent_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def state_dependent_path_declaration(self):

        localctx = VerilogParser.State_dependent_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 488, self.RULE_state_dependent_path_declaration)
        try:
            self.state = 3404
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,344,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3390
                self.match(VerilogParser.IF)
                self.state = 3391
                self.match(VerilogParser.LP)
                self.state = 3392
                self.module_path_expression(0)
                self.state = 3393
                self.match(VerilogParser.RP)
                self.state = 3394
                self.simple_path_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3396
                self.match(VerilogParser.IF)
                self.state = 3397
                self.match(VerilogParser.LP)
                self.state = 3398
                self.module_path_expression(0)
                self.state = 3399
                self.match(VerilogParser.RP)
                self.state = 3400
                self.edge_sensitive_path_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3402
                self.match(VerilogParser.IFNONE)
                self.state = 3403
                self.simple_path_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Polarity_operatorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PL(self):
            return self.getToken(VerilogParser.PL, 0)

        def MI(self):
            return self.getToken(VerilogParser.MI, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_polarity_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPolarity_operator" ):
                listener.enterPolarity_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPolarity_operator" ):
                listener.exitPolarity_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPolarity_operator" ):
                return visitor.visitPolarity_operator(self)
            else:
                return visitor.visitChildren(self)




    def polarity_operator(self):

        localctx = VerilogParser.Polarity_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 490, self.RULE_polarity_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3406
            _la = self._input.LA(1)
            if not(_la==VerilogParser.MI or _la==VerilogParser.PL):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class System_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def setup_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Setup_timing_checkContext,0)


        def hold_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Hold_timing_checkContext,0)


        def setuphold_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Setuphold_timing_checkContext,0)


        def recovery_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Recovery_timing_checkContext,0)


        def removal_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Removal_timing_checkContext,0)


        def recrem_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Recrem_timing_checkContext,0)


        def skew_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Skew_timing_checkContext,0)


        def timeskew_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Timeskew_timing_checkContext,0)


        def fullskew_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Fullskew_timing_checkContext,0)


        def period_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Period_timing_checkContext,0)


        def width_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Width_timing_checkContext,0)


        def nochange_timing_check(self):
            return self.getTypedRuleContext(VerilogParser.Nochange_timing_checkContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_system_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_timing_check" ):
                listener.enterSystem_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_timing_check" ):
                listener.exitSystem_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_timing_check" ):
                return visitor.visitSystem_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def system_timing_check(self):

        localctx = VerilogParser.System_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 492, self.RULE_system_timing_check)
        try:
            self.state = 3420
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DLSETUP]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3408
                self.setup_timing_check()
                pass
            elif token in [VerilogParser.DLHOLD]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3409
                self.hold_timing_check()
                pass
            elif token in [VerilogParser.DLSETUPHOLD]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3410
                self.setuphold_timing_check()
                pass
            elif token in [VerilogParser.DLRECOVERY]:
                self.enterOuterAlt(localctx, 4)
                self.state = 3411
                self.recovery_timing_check()
                pass
            elif token in [VerilogParser.DLREMOVAL]:
                self.enterOuterAlt(localctx, 5)
                self.state = 3412
                self.removal_timing_check()
                pass
            elif token in [VerilogParser.DLRECREM]:
                self.enterOuterAlt(localctx, 6)
                self.state = 3413
                self.recrem_timing_check()
                pass
            elif token in [VerilogParser.DLSKEW]:
                self.enterOuterAlt(localctx, 7)
                self.state = 3414
                self.skew_timing_check()
                pass
            elif token in [VerilogParser.DLTIMESKEW]:
                self.enterOuterAlt(localctx, 8)
                self.state = 3415
                self.timeskew_timing_check()
                pass
            elif token in [VerilogParser.DLFULLSKEW]:
                self.enterOuterAlt(localctx, 9)
                self.state = 3416
                self.fullskew_timing_check()
                pass
            elif token in [VerilogParser.DLPERIOD]:
                self.enterOuterAlt(localctx, 10)
                self.state = 3417
                self.period_timing_check()
                pass
            elif token in [VerilogParser.DLWIDTH]:
                self.enterOuterAlt(localctx, 11)
                self.state = 3418
                self.width_timing_check()
                pass
            elif token in [VerilogParser.DLNOCHANGE]:
                self.enterOuterAlt(localctx, 12)
                self.state = 3419
                self.nochange_timing_check()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Setup_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLSETUP(self):
            return self.getToken(VerilogParser.DLSETUP, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def timing_check_limit(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def notifier_opt(self):
            return self.getTypedRuleContext(VerilogParser.Notifier_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_setup_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSetup_timing_check" ):
                listener.enterSetup_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSetup_timing_check" ):
                listener.exitSetup_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSetup_timing_check" ):
                return visitor.visitSetup_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def setup_timing_check(self):

        localctx = VerilogParser.Setup_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 494, self.RULE_setup_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3422
            self.match(VerilogParser.DLSETUP)
            self.state = 3423
            self.match(VerilogParser.LP)
            self.state = 3424
            self.data_event()
            self.state = 3425
            self.match(VerilogParser.CO)
            self.state = 3426
            self.reference_event()
            self.state = 3427
            self.match(VerilogParser.CO)
            self.state = 3428
            self.timing_check_limit()
            self.state = 3430
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3429
                self.notifier_opt()


            self.state = 3432
            self.match(VerilogParser.RP)
            self.state = 3433
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Notifier_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def notifier(self):
            return self.getTypedRuleContext(VerilogParser.NotifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_notifier_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNotifier_opt" ):
                listener.enterNotifier_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNotifier_opt" ):
                listener.exitNotifier_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNotifier_opt" ):
                return visitor.visitNotifier_opt(self)
            else:
                return visitor.visitChildren(self)




    def notifier_opt(self):

        localctx = VerilogParser.Notifier_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 496, self.RULE_notifier_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3435
            self.match(VerilogParser.CO)
            self.state = 3437
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 3436
                self.notifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Hold_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLHOLD(self):
            return self.getToken(VerilogParser.DLHOLD, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def timing_check_limit(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def notifier_opt(self):
            return self.getTypedRuleContext(VerilogParser.Notifier_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hold_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHold_timing_check" ):
                listener.enterHold_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHold_timing_check" ):
                listener.exitHold_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHold_timing_check" ):
                return visitor.visitHold_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def hold_timing_check(self):

        localctx = VerilogParser.Hold_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 498, self.RULE_hold_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3439
            self.match(VerilogParser.DLHOLD)
            self.state = 3440
            self.match(VerilogParser.LP)
            self.state = 3441
            self.reference_event()
            self.state = 3442
            self.match(VerilogParser.CO)
            self.state = 3443
            self.data_event()
            self.state = 3444
            self.match(VerilogParser.CO)
            self.state = 3445
            self.timing_check_limit()
            self.state = 3447
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3446
                self.notifier_opt()


            self.state = 3449
            self.match(VerilogParser.RP)
            self.state = 3450
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Setuphold_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLSETUPHOLD(self):
            return self.getToken(VerilogParser.DLSETUPHOLD, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def timing_check_limit(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Timing_check_limitContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def timing_check_opt(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_setuphold_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSetuphold_timing_check" ):
                listener.enterSetuphold_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSetuphold_timing_check" ):
                listener.exitSetuphold_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSetuphold_timing_check" ):
                return visitor.visitSetuphold_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def setuphold_timing_check(self):

        localctx = VerilogParser.Setuphold_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 500, self.RULE_setuphold_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3452
            self.match(VerilogParser.DLSETUPHOLD)
            self.state = 3453
            self.match(VerilogParser.LP)
            self.state = 3454
            self.reference_event()
            self.state = 3455
            self.match(VerilogParser.CO)
            self.state = 3456
            self.data_event()
            self.state = 3457
            self.match(VerilogParser.CO)
            self.state = 3458
            self.timing_check_limit()
            self.state = 3459
            self.match(VerilogParser.CO)
            self.state = 3460
            self.timing_check_limit()
            self.state = 3462
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3461
                self.timing_check_opt()


            self.state = 3464
            self.match(VerilogParser.RP)
            self.state = 3465
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Timing_check_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def notifier(self):
            return self.getTypedRuleContext(VerilogParser.NotifierContext,0)


        def stamptime_cond_opt(self):
            return self.getTypedRuleContext(VerilogParser.Stamptime_cond_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_timing_check_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTiming_check_opt" ):
                listener.enterTiming_check_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTiming_check_opt" ):
                listener.exitTiming_check_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTiming_check_opt" ):
                return visitor.visitTiming_check_opt(self)
            else:
                return visitor.visitChildren(self)




    def timing_check_opt(self):

        localctx = VerilogParser.Timing_check_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 502, self.RULE_timing_check_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3467
            self.match(VerilogParser.CO)
            self.state = 3469
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 3468
                self.notifier()


            self.state = 3472
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3471
                self.stamptime_cond_opt()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Stamptime_cond_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def stamptime_condition(self):
            return self.getTypedRuleContext(VerilogParser.Stamptime_conditionContext,0)


        def checktime_cond_opt(self):
            return self.getTypedRuleContext(VerilogParser.Checktime_cond_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_stamptime_cond_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStamptime_cond_opt" ):
                listener.enterStamptime_cond_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStamptime_cond_opt" ):
                listener.exitStamptime_cond_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStamptime_cond_opt" ):
                return visitor.visitStamptime_cond_opt(self)
            else:
                return visitor.visitChildren(self)




    def stamptime_cond_opt(self):

        localctx = VerilogParser.Stamptime_cond_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 504, self.RULE_stamptime_cond_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3474
            self.match(VerilogParser.CO)
            self.state = 3476
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 3475
                self.stamptime_condition()


            self.state = 3479
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3478
                self.checktime_cond_opt()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Checktime_cond_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def checktime_condition(self):
            return self.getTypedRuleContext(VerilogParser.Checktime_conditionContext,0)


        def delayed_ref_opt(self):
            return self.getTypedRuleContext(VerilogParser.Delayed_ref_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_checktime_cond_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecktime_cond_opt" ):
                listener.enterChecktime_cond_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecktime_cond_opt" ):
                listener.exitChecktime_cond_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecktime_cond_opt" ):
                return visitor.visitChecktime_cond_opt(self)
            else:
                return visitor.visitChildren(self)




    def checktime_cond_opt(self):

        localctx = VerilogParser.Checktime_cond_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 506, self.RULE_checktime_cond_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3481
            self.match(VerilogParser.CO)
            self.state = 3483
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 3482
                self.checktime_condition()


            self.state = 3486
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3485
                self.delayed_ref_opt()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delayed_ref_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def delayed_reference(self):
            return self.getTypedRuleContext(VerilogParser.Delayed_referenceContext,0)


        def delayed_data_opt(self):
            return self.getTypedRuleContext(VerilogParser.Delayed_data_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_delayed_ref_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelayed_ref_opt" ):
                listener.enterDelayed_ref_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelayed_ref_opt" ):
                listener.exitDelayed_ref_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelayed_ref_opt" ):
                return visitor.visitDelayed_ref_opt(self)
            else:
                return visitor.visitChildren(self)




    def delayed_ref_opt(self):

        localctx = VerilogParser.Delayed_ref_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 508, self.RULE_delayed_ref_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3488
            self.match(VerilogParser.CO)
            self.state = 3490
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 3489
                self.delayed_reference()


            self.state = 3493
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3492
                self.delayed_data_opt()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delayed_data_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def delayed_data(self):
            return self.getTypedRuleContext(VerilogParser.Delayed_dataContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_delayed_data_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelayed_data_opt" ):
                listener.enterDelayed_data_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelayed_data_opt" ):
                listener.exitDelayed_data_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelayed_data_opt" ):
                return visitor.visitDelayed_data_opt(self)
            else:
                return visitor.visitChildren(self)




    def delayed_data_opt(self):

        localctx = VerilogParser.Delayed_data_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 510, self.RULE_delayed_data_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3495
            self.match(VerilogParser.CO)
            self.state = 3497
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 3496
                self.delayed_data()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Recovery_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLRECOVERY(self):
            return self.getToken(VerilogParser.DLRECOVERY, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def timing_check_limit(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def notifier_opt(self):
            return self.getTypedRuleContext(VerilogParser.Notifier_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_recovery_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRecovery_timing_check" ):
                listener.enterRecovery_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRecovery_timing_check" ):
                listener.exitRecovery_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRecovery_timing_check" ):
                return visitor.visitRecovery_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def recovery_timing_check(self):

        localctx = VerilogParser.Recovery_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 512, self.RULE_recovery_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3499
            self.match(VerilogParser.DLRECOVERY)
            self.state = 3500
            self.match(VerilogParser.LP)
            self.state = 3501
            self.reference_event()
            self.state = 3502
            self.match(VerilogParser.CO)
            self.state = 3503
            self.data_event()
            self.state = 3504
            self.match(VerilogParser.CO)
            self.state = 3505
            self.timing_check_limit()
            self.state = 3507
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3506
                self.notifier_opt()


            self.state = 3509
            self.match(VerilogParser.RP)
            self.state = 3510
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Removal_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLREMOVAL(self):
            return self.getToken(VerilogParser.DLREMOVAL, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def timing_check_limit(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def notifier_opt(self):
            return self.getTypedRuleContext(VerilogParser.Notifier_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_removal_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRemoval_timing_check" ):
                listener.enterRemoval_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRemoval_timing_check" ):
                listener.exitRemoval_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRemoval_timing_check" ):
                return visitor.visitRemoval_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def removal_timing_check(self):

        localctx = VerilogParser.Removal_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 514, self.RULE_removal_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3512
            self.match(VerilogParser.DLREMOVAL)
            self.state = 3513
            self.match(VerilogParser.LP)
            self.state = 3514
            self.reference_event()
            self.state = 3515
            self.match(VerilogParser.CO)
            self.state = 3516
            self.data_event()
            self.state = 3517
            self.match(VerilogParser.CO)
            self.state = 3518
            self.timing_check_limit()
            self.state = 3520
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3519
                self.notifier_opt()


            self.state = 3522
            self.match(VerilogParser.RP)
            self.state = 3523
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Recrem_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLRECREM(self):
            return self.getToken(VerilogParser.DLRECREM, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def timing_check_limit(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Timing_check_limitContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def timing_check_opt(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_recrem_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRecrem_timing_check" ):
                listener.enterRecrem_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRecrem_timing_check" ):
                listener.exitRecrem_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRecrem_timing_check" ):
                return visitor.visitRecrem_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def recrem_timing_check(self):

        localctx = VerilogParser.Recrem_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 516, self.RULE_recrem_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3525
            self.match(VerilogParser.DLRECREM)
            self.state = 3526
            self.match(VerilogParser.LP)
            self.state = 3527
            self.reference_event()
            self.state = 3528
            self.match(VerilogParser.CO)
            self.state = 3529
            self.data_event()
            self.state = 3530
            self.match(VerilogParser.CO)
            self.state = 3531
            self.timing_check_limit()
            self.state = 3532
            self.match(VerilogParser.CO)
            self.state = 3533
            self.timing_check_limit()
            self.state = 3535
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3534
                self.timing_check_opt()


            self.state = 3537
            self.match(VerilogParser.RP)
            self.state = 3538
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Skew_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLSKEW(self):
            return self.getToken(VerilogParser.DLSKEW, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def timing_check_limit(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def notifier_opt(self):
            return self.getTypedRuleContext(VerilogParser.Notifier_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_skew_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSkew_timing_check" ):
                listener.enterSkew_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSkew_timing_check" ):
                listener.exitSkew_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSkew_timing_check" ):
                return visitor.visitSkew_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def skew_timing_check(self):

        localctx = VerilogParser.Skew_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 518, self.RULE_skew_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3540
            self.match(VerilogParser.DLSKEW)
            self.state = 3541
            self.match(VerilogParser.LP)
            self.state = 3542
            self.reference_event()
            self.state = 3543
            self.match(VerilogParser.CO)
            self.state = 3544
            self.data_event()
            self.state = 3545
            self.match(VerilogParser.CO)
            self.state = 3546
            self.timing_check_limit()
            self.state = 3548
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3547
                self.notifier_opt()


            self.state = 3550
            self.match(VerilogParser.RP)
            self.state = 3551
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Timeskew_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLTIMESKEW(self):
            return self.getToken(VerilogParser.DLTIMESKEW, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def timing_check_limit(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def skew_timing_check_opt(self):
            return self.getTypedRuleContext(VerilogParser.Skew_timing_check_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_timeskew_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTimeskew_timing_check" ):
                listener.enterTimeskew_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTimeskew_timing_check" ):
                listener.exitTimeskew_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTimeskew_timing_check" ):
                return visitor.visitTimeskew_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def timeskew_timing_check(self):

        localctx = VerilogParser.Timeskew_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 520, self.RULE_timeskew_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3553
            self.match(VerilogParser.DLTIMESKEW)
            self.state = 3554
            self.match(VerilogParser.LP)
            self.state = 3555
            self.reference_event()
            self.state = 3556
            self.match(VerilogParser.CO)
            self.state = 3557
            self.data_event()
            self.state = 3558
            self.match(VerilogParser.CO)
            self.state = 3559
            self.timing_check_limit()
            self.state = 3561
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3560
                self.skew_timing_check_opt()


            self.state = 3563
            self.match(VerilogParser.RP)
            self.state = 3564
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Skew_timing_check_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def notifier(self):
            return self.getTypedRuleContext(VerilogParser.NotifierContext,0)


        def event_based_flag_opt(self):
            return self.getTypedRuleContext(VerilogParser.Event_based_flag_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_skew_timing_check_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSkew_timing_check_opt" ):
                listener.enterSkew_timing_check_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSkew_timing_check_opt" ):
                listener.exitSkew_timing_check_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSkew_timing_check_opt" ):
                return visitor.visitSkew_timing_check_opt(self)
            else:
                return visitor.visitChildren(self)




    def skew_timing_check_opt(self):

        localctx = VerilogParser.Skew_timing_check_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 522, self.RULE_skew_timing_check_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3566
            self.match(VerilogParser.CO)
            self.state = 3568
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 3567
                self.notifier()


            self.state = 3571
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3570
                self.event_based_flag_opt()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Event_based_flag_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def event_based_flag(self):
            return self.getTypedRuleContext(VerilogParser.Event_based_flagContext,0)


        def remain_active_flag_opt(self):
            return self.getTypedRuleContext(VerilogParser.Remain_active_flag_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_event_based_flag_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_based_flag_opt" ):
                listener.enterEvent_based_flag_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_based_flag_opt" ):
                listener.exitEvent_based_flag_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_based_flag_opt" ):
                return visitor.visitEvent_based_flag_opt(self)
            else:
                return visitor.visitChildren(self)




    def event_based_flag_opt(self):

        localctx = VerilogParser.Event_based_flag_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 524, self.RULE_event_based_flag_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3573
            self.match(VerilogParser.CO)
            self.state = 3575
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 3574
                self.event_based_flag()


            self.state = 3578
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3577
                self.remain_active_flag_opt()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Remain_active_flag_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def remain_active_flag(self):
            return self.getTypedRuleContext(VerilogParser.Remain_active_flagContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_remain_active_flag_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRemain_active_flag_opt" ):
                listener.enterRemain_active_flag_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRemain_active_flag_opt" ):
                listener.exitRemain_active_flag_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRemain_active_flag_opt" ):
                return visitor.visitRemain_active_flag_opt(self)
            else:
                return visitor.visitChildren(self)




    def remain_active_flag_opt(self):

        localctx = VerilogParser.Remain_active_flag_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 526, self.RULE_remain_active_flag_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3580
            self.match(VerilogParser.CO)
            self.state = 3582
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.LC - 137)) | (1 << (VerilogParser.LP - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)) | (1 << (VerilogParser.BINARY_BASE - 137)) | (1 << (VerilogParser.DECIMAL_BASE - 137)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 137)) | (1 << (VerilogParser.EXPONENTIAL_NUMBER - 137)) | (1 << (VerilogParser.FIXED_POINT_NUMBER - 137)) | (1 << (VerilogParser.HEX_BASE - 137)) | (1 << (VerilogParser.OCTAL_BASE - 137)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 137)) | (1 << (VerilogParser.STRING - 137)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 137)))) != 0) or _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 3581
                self.remain_active_flag()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Fullskew_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLFULLSKEW(self):
            return self.getToken(VerilogParser.DLFULLSKEW, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def timing_check_limit(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Timing_check_limitContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def skew_timing_check_opt(self):
            return self.getTypedRuleContext(VerilogParser.Skew_timing_check_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_fullskew_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFullskew_timing_check" ):
                listener.enterFullskew_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFullskew_timing_check" ):
                listener.exitFullskew_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFullskew_timing_check" ):
                return visitor.visitFullskew_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def fullskew_timing_check(self):

        localctx = VerilogParser.Fullskew_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 528, self.RULE_fullskew_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3584
            self.match(VerilogParser.DLFULLSKEW)
            self.state = 3585
            self.match(VerilogParser.LP)
            self.state = 3586
            self.reference_event()
            self.state = 3587
            self.match(VerilogParser.CO)
            self.state = 3588
            self.data_event()
            self.state = 3589
            self.match(VerilogParser.CO)
            self.state = 3590
            self.timing_check_limit()
            self.state = 3591
            self.match(VerilogParser.CO)
            self.state = 3592
            self.timing_check_limit()
            self.state = 3594
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3593
                self.skew_timing_check_opt()


            self.state = 3596
            self.match(VerilogParser.RP)
            self.state = 3597
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Period_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLPERIOD(self):
            return self.getToken(VerilogParser.DLPERIOD, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def controlled_reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Controlled_reference_eventContext,0)


        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def timing_check_limit(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def notifier_opt(self):
            return self.getTypedRuleContext(VerilogParser.Notifier_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_period_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPeriod_timing_check" ):
                listener.enterPeriod_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPeriod_timing_check" ):
                listener.exitPeriod_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPeriod_timing_check" ):
                return visitor.visitPeriod_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def period_timing_check(self):

        localctx = VerilogParser.Period_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 530, self.RULE_period_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3599
            self.match(VerilogParser.DLPERIOD)
            self.state = 3600
            self.match(VerilogParser.LP)
            self.state = 3601
            self.controlled_reference_event()
            self.state = 3602
            self.match(VerilogParser.CO)
            self.state = 3603
            self.timing_check_limit()
            self.state = 3605
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3604
                self.notifier_opt()


            self.state = 3607
            self.match(VerilogParser.RP)
            self.state = 3608
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Width_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLWIDTH(self):
            return self.getToken(VerilogParser.DLWIDTH, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def controlled_reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Controlled_reference_eventContext,0)


        def CO(self):
            return self.getToken(VerilogParser.CO, 0)

        def timing_check_limit(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_limitContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def threshold_opt(self):
            return self.getTypedRuleContext(VerilogParser.Threshold_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_width_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWidth_timing_check" ):
                listener.enterWidth_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWidth_timing_check" ):
                listener.exitWidth_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWidth_timing_check" ):
                return visitor.visitWidth_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def width_timing_check(self):

        localctx = VerilogParser.Width_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 532, self.RULE_width_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3610
            self.match(VerilogParser.DLWIDTH)
            self.state = 3611
            self.match(VerilogParser.LP)
            self.state = 3612
            self.controlled_reference_event()
            self.state = 3613
            self.match(VerilogParser.CO)
            self.state = 3614
            self.timing_check_limit()
            self.state = 3616
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3615
                self.threshold_opt()


            self.state = 3618
            self.match(VerilogParser.RP)
            self.state = 3619
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Threshold_optContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def threshold(self):
            return self.getTypedRuleContext(VerilogParser.ThresholdContext,0)


        def notifier(self):
            return self.getTypedRuleContext(VerilogParser.NotifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_threshold_opt

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterThreshold_opt" ):
                listener.enterThreshold_opt(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitThreshold_opt" ):
                listener.exitThreshold_opt(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitThreshold_opt" ):
                return visitor.visitThreshold_opt(self)
            else:
                return visitor.visitChildren(self)




    def threshold_opt(self):

        localctx = VerilogParser.Threshold_optContext(self, self._ctx, self.state)
        self.enterRule(localctx, 534, self.RULE_threshold_opt)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3621
            self.match(VerilogParser.CO)
            self.state = 3622
            self.threshold()
            self.state = 3625
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3623
                self.match(VerilogParser.CO)
                self.state = 3624
                self.notifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Nochange_timing_checkContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DLNOCHANGE(self):
            return self.getToken(VerilogParser.DLNOCHANGE, 0)

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def reference_event(self):
            return self.getTypedRuleContext(VerilogParser.Reference_eventContext,0)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def data_event(self):
            return self.getTypedRuleContext(VerilogParser.Data_eventContext,0)


        def start_edge_offset(self):
            return self.getTypedRuleContext(VerilogParser.Start_edge_offsetContext,0)


        def end_edge_offset(self):
            return self.getTypedRuleContext(VerilogParser.End_edge_offsetContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def SC(self):
            return self.getToken(VerilogParser.SC, 0)

        def notifier_opt(self):
            return self.getTypedRuleContext(VerilogParser.Notifier_optContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_nochange_timing_check

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNochange_timing_check" ):
                listener.enterNochange_timing_check(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNochange_timing_check" ):
                listener.exitNochange_timing_check(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNochange_timing_check" ):
                return visitor.visitNochange_timing_check(self)
            else:
                return visitor.visitChildren(self)




    def nochange_timing_check(self):

        localctx = VerilogParser.Nochange_timing_checkContext(self, self._ctx, self.state)
        self.enterRule(localctx, 536, self.RULE_nochange_timing_check)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3627
            self.match(VerilogParser.DLNOCHANGE)
            self.state = 3628
            self.match(VerilogParser.LP)
            self.state = 3629
            self.reference_event()
            self.state = 3630
            self.match(VerilogParser.CO)
            self.state = 3631
            self.data_event()
            self.state = 3632
            self.match(VerilogParser.CO)
            self.state = 3633
            self.start_edge_offset()
            self.state = 3634
            self.match(VerilogParser.CO)
            self.state = 3635
            self.end_edge_offset()
            self.state = 3637
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CO:
                self.state = 3636
                self.notifier_opt()


            self.state = 3639
            self.match(VerilogParser.RP)
            self.state = 3640
            self.match(VerilogParser.SC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Checktime_conditionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_checktime_condition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecktime_condition" ):
                listener.enterChecktime_condition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecktime_condition" ):
                listener.exitChecktime_condition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecktime_condition" ):
                return visitor.visitChecktime_condition(self)
            else:
                return visitor.visitChildren(self)




    def checktime_condition(self):

        localctx = VerilogParser.Checktime_conditionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 538, self.RULE_checktime_condition)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3642
            self.mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Controlled_reference_eventContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def controlled_timing_check_event(self):
            return self.getTypedRuleContext(VerilogParser.Controlled_timing_check_eventContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_controlled_reference_event

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterControlled_reference_event" ):
                listener.enterControlled_reference_event(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitControlled_reference_event" ):
                listener.exitControlled_reference_event(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitControlled_reference_event" ):
                return visitor.visitControlled_reference_event(self)
            else:
                return visitor.visitChildren(self)




    def controlled_reference_event(self):

        localctx = VerilogParser.Controlled_reference_eventContext(self, self._ctx, self.state)
        self.enterRule(localctx, 540, self.RULE_controlled_reference_event)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3644
            self.controlled_timing_check_event()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Data_eventContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def timing_check_event(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_eventContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_data_event

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterData_event" ):
                listener.enterData_event(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitData_event" ):
                listener.exitData_event(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitData_event" ):
                return visitor.visitData_event(self)
            else:
                return visitor.visitChildren(self)




    def data_event(self):

        localctx = VerilogParser.Data_eventContext(self, self._ctx, self.state)
        self.enterRule(localctx, 542, self.RULE_data_event)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3646
            self.timing_check_event()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delayed_dataContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def terminal_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Terminal_identifierContext,0)


        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_delayed_data

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelayed_data" ):
                listener.enterDelayed_data(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelayed_data" ):
                listener.exitDelayed_data(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelayed_data" ):
                return visitor.visitDelayed_data(self)
            else:
                return visitor.visitChildren(self)




    def delayed_data(self):

        localctx = VerilogParser.Delayed_dataContext(self, self._ctx, self.state)
        self.enterRule(localctx, 544, self.RULE_delayed_data)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3648
            self.terminal_identifier()
            self.state = 3653
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 3649
                self.match(VerilogParser.LB)
                self.state = 3650
                self.constant_mintypmax_expression()
                self.state = 3651
                self.match(VerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Delayed_referenceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def terminal_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Terminal_identifierContext,0)


        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_delayed_reference

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelayed_reference" ):
                listener.enterDelayed_reference(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelayed_reference" ):
                listener.exitDelayed_reference(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelayed_reference" ):
                return visitor.visitDelayed_reference(self)
            else:
                return visitor.visitChildren(self)




    def delayed_reference(self):

        localctx = VerilogParser.Delayed_referenceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 546, self.RULE_delayed_reference)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3655
            self.terminal_identifier()
            self.state = 3660
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 3656
                self.match(VerilogParser.LB)
                self.state = 3657
                self.constant_mintypmax_expression()
                self.state = 3658
                self.match(VerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class End_edge_offsetContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_end_edge_offset

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnd_edge_offset" ):
                listener.enterEnd_edge_offset(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnd_edge_offset" ):
                listener.exitEnd_edge_offset(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnd_edge_offset" ):
                return visitor.visitEnd_edge_offset(self)
            else:
                return visitor.visitChildren(self)




    def end_edge_offset(self):

        localctx = VerilogParser.End_edge_offsetContext(self, self._ctx, self.state)
        self.enterRule(localctx, 548, self.RULE_end_edge_offset)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3662
            self.mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Event_based_flagContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_event_based_flag

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_based_flag" ):
                listener.enterEvent_based_flag(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_based_flag" ):
                listener.exitEvent_based_flag(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_based_flag" ):
                return visitor.visitEvent_based_flag(self)
            else:
                return visitor.visitChildren(self)




    def event_based_flag(self):

        localctx = VerilogParser.Event_based_flagContext(self, self._ctx, self.state)
        self.enterRule(localctx, 550, self.RULE_event_based_flag)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3664
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class NotifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_notifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNotifier" ):
                listener.enterNotifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNotifier" ):
                listener.exitNotifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNotifier" ):
                return visitor.visitNotifier(self)
            else:
                return visitor.visitChildren(self)




    def notifier(self):

        localctx = VerilogParser.NotifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 552, self.RULE_notifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3666
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Reference_eventContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def timing_check_event(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_eventContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_reference_event

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReference_event" ):
                listener.enterReference_event(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReference_event" ):
                listener.exitReference_event(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReference_event" ):
                return visitor.visitReference_event(self)
            else:
                return visitor.visitChildren(self)




    def reference_event(self):

        localctx = VerilogParser.Reference_eventContext(self, self._ctx, self.state)
        self.enterRule(localctx, 554, self.RULE_reference_event)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3668
            self.timing_check_event()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Remain_active_flagContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_remain_active_flag

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRemain_active_flag" ):
                listener.enterRemain_active_flag(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRemain_active_flag" ):
                listener.exitRemain_active_flag(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRemain_active_flag" ):
                return visitor.visitRemain_active_flag(self)
            else:
                return visitor.visitChildren(self)




    def remain_active_flag(self):

        localctx = VerilogParser.Remain_active_flagContext(self, self._ctx, self.state)
        self.enterRule(localctx, 556, self.RULE_remain_active_flag)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3670
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Stamptime_conditionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_stamptime_condition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStamptime_condition" ):
                listener.enterStamptime_condition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStamptime_condition" ):
                listener.exitStamptime_condition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStamptime_condition" ):
                return visitor.visitStamptime_condition(self)
            else:
                return visitor.visitChildren(self)




    def stamptime_condition(self):

        localctx = VerilogParser.Stamptime_conditionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 558, self.RULE_stamptime_condition)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3672
            self.mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Start_edge_offsetContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_start_edge_offset

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStart_edge_offset" ):
                listener.enterStart_edge_offset(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStart_edge_offset" ):
                listener.exitStart_edge_offset(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStart_edge_offset" ):
                return visitor.visitStart_edge_offset(self)
            else:
                return visitor.visitChildren(self)




    def start_edge_offset(self):

        localctx = VerilogParser.Start_edge_offsetContext(self, self._ctx, self.state)
        self.enterRule(localctx, 560, self.RULE_start_edge_offset)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3674
            self.mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class ThresholdContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_threshold

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterThreshold" ):
                listener.enterThreshold(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitThreshold" ):
                listener.exitThreshold(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitThreshold" ):
                return visitor.visitThreshold(self)
            else:
                return visitor.visitChildren(self)




    def threshold(self):

        localctx = VerilogParser.ThresholdContext(self, self._ctx, self.state)
        self.enterRule(localctx, 562, self.RULE_threshold)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3676
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Timing_check_limitContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_timing_check_limit

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTiming_check_limit" ):
                listener.enterTiming_check_limit(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTiming_check_limit" ):
                listener.exitTiming_check_limit(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTiming_check_limit" ):
                return visitor.visitTiming_check_limit(self)
            else:
                return visitor.visitChildren(self)




    def timing_check_limit(self):

        localctx = VerilogParser.Timing_check_limitContext(self, self._ctx, self.state)
        self.enterRule(localctx, 564, self.RULE_timing_check_limit)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3678
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Timing_check_eventContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specify_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_terminal_descriptorContext,0)


        def timing_check_event_control(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_event_controlContext,0)


        def AMAMAM(self):
            return self.getToken(VerilogParser.AMAMAM, 0)

        def timing_check_condition(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_conditionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_timing_check_event

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTiming_check_event" ):
                listener.enterTiming_check_event(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTiming_check_event" ):
                listener.exitTiming_check_event(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTiming_check_event" ):
                return visitor.visitTiming_check_event(self)
            else:
                return visitor.visitChildren(self)




    def timing_check_event(self):

        localctx = VerilogParser.Timing_check_eventContext(self, self._ctx, self.state)
        self.enterRule(localctx, 566, self.RULE_timing_check_event)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3681
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 32)) & ~0x3f) == 0 and ((1 << (_la - 32)) & ((1 << (VerilogParser.EDGE - 32)) | (1 << (VerilogParser.NEGEDGE - 32)) | (1 << (VerilogParser.POSEDGE - 32)))) != 0):
                self.state = 3680
                self.timing_check_event_control()


            self.state = 3683
            self.specify_terminal_descriptor()
            self.state = 3686
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.AMAMAM:
                self.state = 3684
                self.match(VerilogParser.AMAMAM)
                self.state = 3685
                self.timing_check_condition()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Controlled_timing_check_eventContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def timing_check_event_control(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_event_controlContext,0)


        def specify_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_terminal_descriptorContext,0)


        def AMAMAM(self):
            return self.getToken(VerilogParser.AMAMAM, 0)

        def timing_check_condition(self):
            return self.getTypedRuleContext(VerilogParser.Timing_check_conditionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_controlled_timing_check_event

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterControlled_timing_check_event" ):
                listener.enterControlled_timing_check_event(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitControlled_timing_check_event" ):
                listener.exitControlled_timing_check_event(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitControlled_timing_check_event" ):
                return visitor.visitControlled_timing_check_event(self)
            else:
                return visitor.visitChildren(self)




    def controlled_timing_check_event(self):

        localctx = VerilogParser.Controlled_timing_check_eventContext(self, self._ctx, self.state)
        self.enterRule(localctx, 568, self.RULE_controlled_timing_check_event)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3688
            self.timing_check_event_control()
            self.state = 3689
            self.specify_terminal_descriptor()
            self.state = 3692
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.AMAMAM:
                self.state = 3690
                self.match(VerilogParser.AMAMAM)
                self.state = 3691
                self.timing_check_condition()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Timing_check_event_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def POSEDGE(self):
            return self.getToken(VerilogParser.POSEDGE, 0)

        def NEGEDGE(self):
            return self.getToken(VerilogParser.NEGEDGE, 0)

        def edge_control_specifier(self):
            return self.getTypedRuleContext(VerilogParser.Edge_control_specifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_timing_check_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTiming_check_event_control" ):
                listener.enterTiming_check_event_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTiming_check_event_control" ):
                listener.exitTiming_check_event_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTiming_check_event_control" ):
                return visitor.visitTiming_check_event_control(self)
            else:
                return visitor.visitChildren(self)




    def timing_check_event_control(self):

        localctx = VerilogParser.Timing_check_event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 570, self.RULE_timing_check_event_control)
        try:
            self.state = 3697
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.POSEDGE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3694
                self.match(VerilogParser.POSEDGE)
                pass
            elif token in [VerilogParser.NEGEDGE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3695
                self.match(VerilogParser.NEGEDGE)
                pass
            elif token in [VerilogParser.EDGE]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3696
                self.edge_control_specifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Specify_terminal_descriptorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,0)


        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specify_terminal_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_terminal_descriptor" ):
                listener.enterSpecify_terminal_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_terminal_descriptor" ):
                listener.exitSpecify_terminal_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_terminal_descriptor" ):
                return visitor.visitSpecify_terminal_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def specify_terminal_descriptor(self):

        localctx = VerilogParser.Specify_terminal_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 572, self.RULE_specify_terminal_descriptor)
        try:
            self.state = 3701
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,380,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3699
                self.specify_input_terminal_descriptor()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3700
                self.specify_output_terminal_descriptor()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Edge_control_specifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EDGE(self):
            return self.getToken(VerilogParser.EDGE, 0)

        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def edge_descriptor(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Edge_descriptorContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Edge_descriptorContext,i)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_edge_control_specifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_control_specifier" ):
                listener.enterEdge_control_specifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_control_specifier" ):
                listener.exitEdge_control_specifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_control_specifier" ):
                return visitor.visitEdge_control_specifier(self)
            else:
                return visitor.visitChildren(self)




    def edge_control_specifier(self):

        localctx = VerilogParser.Edge_control_specifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 574, self.RULE_edge_control_specifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3703
            self.match(VerilogParser.EDGE)
            self.state = 3704
            self.match(VerilogParser.LB)
            self.state = 3705
            self.edge_descriptor()
            self.state = 3710
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3706
                self.match(VerilogParser.CO)
                self.state = 3707
                self.edge_descriptor()
                self.state = 3712
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3713
            self.match(VerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Edge_descriptorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EDGE_DESCRIPTOR(self):
            return self.getToken(VerilogParser.EDGE_DESCRIPTOR, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_edge_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_descriptor" ):
                listener.enterEdge_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_descriptor" ):
                listener.exitEdge_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_descriptor" ):
                return visitor.visitEdge_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def edge_descriptor(self):

        localctx = VerilogParser.Edge_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 576, self.RULE_edge_descriptor)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3715
            self.match(VerilogParser.EDGE_DESCRIPTOR)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Timing_check_conditionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def scalar_timing_check_condition(self):
            return self.getTypedRuleContext(VerilogParser.Scalar_timing_check_conditionContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_timing_check_condition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTiming_check_condition" ):
                listener.enterTiming_check_condition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTiming_check_condition" ):
                listener.exitTiming_check_condition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTiming_check_condition" ):
                return visitor.visitTiming_check_condition(self)
            else:
                return visitor.visitChildren(self)




    def timing_check_condition(self):

        localctx = VerilogParser.Timing_check_conditionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 578, self.RULE_timing_check_condition)
        try:
            self.state = 3722
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,382,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3717
                self.scalar_timing_check_condition()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3718
                self.match(VerilogParser.LP)
                self.state = 3719
                self.scalar_timing_check_condition()
                self.state = 3720
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Scalar_timing_check_conditionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def TI(self):
            return self.getToken(VerilogParser.TI, 0)

        def EQEQ(self):
            return self.getToken(VerilogParser.EQEQ, 0)

        def scalar_constant(self):
            return self.getTypedRuleContext(VerilogParser.Scalar_constantContext,0)


        def EQEQEQ(self):
            return self.getToken(VerilogParser.EQEQEQ, 0)

        def EMEQ(self):
            return self.getToken(VerilogParser.EMEQ, 0)

        def EMEQEQ(self):
            return self.getToken(VerilogParser.EMEQEQ, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_scalar_timing_check_condition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterScalar_timing_check_condition" ):
                listener.enterScalar_timing_check_condition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitScalar_timing_check_condition" ):
                listener.exitScalar_timing_check_condition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitScalar_timing_check_condition" ):
                return visitor.visitScalar_timing_check_condition(self)
            else:
                return visitor.visitChildren(self)




    def scalar_timing_check_condition(self):

        localctx = VerilogParser.Scalar_timing_check_conditionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 580, self.RULE_scalar_timing_check_condition)
        try:
            self.state = 3743
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,383,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3724
                self.expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3725
                self.match(VerilogParser.TI)
                self.state = 3726
                self.expression(0)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3727
                self.expression(0)
                self.state = 3728
                self.match(VerilogParser.EQEQ)
                self.state = 3729
                self.scalar_constant()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3731
                self.expression(0)
                self.state = 3732
                self.match(VerilogParser.EQEQEQ)
                self.state = 3733
                self.scalar_constant()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 3735
                self.expression(0)
                self.state = 3736
                self.match(VerilogParser.EMEQ)
                self.state = 3737
                self.scalar_constant()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 3739
                self.expression(0)
                self.state = 3740
                self.match(VerilogParser.EMEQEQ)
                self.state = 3741
                self.scalar_constant()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Scalar_constantContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def binary_number(self):
            return self.getTypedRuleContext(VerilogParser.Binary_numberContext,0)


        def unsigned_number(self):
            return self.getTypedRuleContext(VerilogParser.Unsigned_numberContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_scalar_constant

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterScalar_constant" ):
                listener.enterScalar_constant(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitScalar_constant" ):
                listener.exitScalar_constant(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitScalar_constant" ):
                return visitor.visitScalar_constant(self)
            else:
                return visitor.visitChildren(self)




    def scalar_constant(self):

        localctx = VerilogParser.Scalar_constantContext(self, self._ctx, self.state)
        self.enterRule(localctx, 582, self.RULE_scalar_constant)
        try:
            self.state = 3747
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,384,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3745
                self.binary_number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3746
                self.unsigned_number()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class ConcatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConcatenation" ):
                listener.enterConcatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConcatenation" ):
                listener.exitConcatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConcatenation" ):
                return visitor.visitConcatenation(self)
            else:
                return visitor.visitChildren(self)




    def concatenation(self):

        localctx = VerilogParser.ConcatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 584, self.RULE_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3749
            self.match(VerilogParser.LC)
            self.state = 3750
            self.expression(0)
            self.state = 3755
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3751
                self.match(VerilogParser.CO)
                self.state = 3752
                self.expression(0)
                self.state = 3757
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3758
            self.match(VerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Constant_concatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_concatenation" ):
                listener.enterConstant_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_concatenation" ):
                listener.exitConstant_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_concatenation" ):
                return visitor.visitConstant_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def constant_concatenation(self):

        localctx = VerilogParser.Constant_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 586, self.RULE_constant_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3760
            self.match(VerilogParser.LC)
            self.state = 3761
            self.constant_expression(0)
            self.state = 3766
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3762
                self.match(VerilogParser.CO)
                self.state = 3763
                self.constant_expression(0)
                self.state = 3768
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3769
            self.match(VerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Constant_multiple_concatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def constant_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Constant_concatenationContext,0)


        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_multiple_concatenation" ):
                listener.enterConstant_multiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_multiple_concatenation" ):
                listener.exitConstant_multiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_multiple_concatenation" ):
                return visitor.visitConstant_multiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def constant_multiple_concatenation(self):

        localctx = VerilogParser.Constant_multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 588, self.RULE_constant_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3771
            self.match(VerilogParser.LC)
            self.state = 3772
            self.constant_expression(0)
            self.state = 3773
            self.constant_concatenation()
            self.state = 3774
            self.match(VerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_path_concatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_path_expressionContext,i)


        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_concatenation" ):
                listener.enterModule_path_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_concatenation" ):
                listener.exitModule_path_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_concatenation" ):
                return visitor.visitModule_path_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def module_path_concatenation(self):

        localctx = VerilogParser.Module_path_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 590, self.RULE_module_path_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3776
            self.match(VerilogParser.LC)
            self.state = 3777
            self.module_path_expression(0)
            self.state = 3782
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3778
                self.match(VerilogParser.CO)
                self.state = 3779
                self.module_path_expression(0)
                self.state = 3784
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3785
            self.match(VerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_path_multiple_concatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def module_path_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_concatenationContext,0)


        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_multiple_concatenation" ):
                listener.enterModule_path_multiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_multiple_concatenation" ):
                listener.exitModule_path_multiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_multiple_concatenation" ):
                return visitor.visitModule_path_multiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def module_path_multiple_concatenation(self):

        localctx = VerilogParser.Module_path_multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 592, self.RULE_module_path_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3787
            self.match(VerilogParser.LC)
            self.state = 3788
            self.constant_expression(0)
            self.state = 3789
            self.module_path_concatenation()
            self.state = 3790
            self.match(VerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Multiple_concatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def concatenation(self):
            return self.getTypedRuleContext(VerilogParser.ConcatenationContext,0)


        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMultiple_concatenation" ):
                listener.enterMultiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMultiple_concatenation" ):
                listener.exitMultiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMultiple_concatenation" ):
                return visitor.visitMultiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def multiple_concatenation(self):

        localctx = VerilogParser.Multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 594, self.RULE_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3792
            self.match(VerilogParser.LC)
            self.state = 3793
            self.constant_expression(0)
            self.state = 3794
            self.concatenation()
            self.state = 3795
            self.match(VerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Constant_function_callContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Function_identifierContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_function_call" ):
                listener.enterConstant_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_function_call" ):
                listener.exitConstant_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_function_call" ):
                return visitor.visitConstant_function_call(self)
            else:
                return visitor.visitChildren(self)




    def constant_function_call(self):

        localctx = VerilogParser.Constant_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 596, self.RULE_constant_function_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3797
            self.function_identifier()
            self.state = 3801
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,388,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3798
                    self.attribute_instance() 
                self.state = 3803
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,388,self._ctx)

            self.state = 3804
            self.match(VerilogParser.LP)
            self.state = 3805
            self.constant_expression(0)
            self.state = 3810
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3806
                self.match(VerilogParser.CO)
                self.state = 3807
                self.constant_expression(0)
                self.state = 3812
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3813
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Constant_system_function_callContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def system_function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.System_function_identifierContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_system_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_system_function_call" ):
                listener.enterConstant_system_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_system_function_call" ):
                listener.exitConstant_system_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_system_function_call" ):
                return visitor.visitConstant_system_function_call(self)
            else:
                return visitor.visitChildren(self)




    def constant_system_function_call(self):

        localctx = VerilogParser.Constant_system_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 598, self.RULE_constant_system_function_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3815
            self.system_function_identifier()
            self.state = 3816
            self.match(VerilogParser.LP)
            self.state = 3817
            self.constant_expression(0)
            self.state = 3822
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3818
                self.match(VerilogParser.CO)
                self.state = 3819
                self.constant_expression(0)
                self.state = 3824
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3825
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Function_callContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_call" ):
                listener.enterFunction_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_call" ):
                listener.exitFunction_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_call" ):
                return visitor.visitFunction_call(self)
            else:
                return visitor.visitChildren(self)




    def function_call(self):

        localctx = VerilogParser.Function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 600, self.RULE_function_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3827
            self.hierarchical_identifier()
            self.state = 3831
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,391,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3828
                    self.attribute_instance() 
                self.state = 3833
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,391,self._ctx)

            self.state = 3834
            self.match(VerilogParser.LP)
            self.state = 3835
            self.expression(0)
            self.state = 3840
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3836
                self.match(VerilogParser.CO)
                self.state = 3837
                self.expression(0)
                self.state = 3842
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3843
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class System_function_callContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def system_function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.System_function_identifierContext,0)


        def sys_func_call_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Sys_func_call_port_listContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_system_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_function_call" ):
                listener.enterSystem_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_function_call" ):
                listener.exitSystem_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_function_call" ):
                return visitor.visitSystem_function_call(self)
            else:
                return visitor.visitChildren(self)




    def system_function_call(self):

        localctx = VerilogParser.System_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 602, self.RULE_system_function_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3845
            self.system_function_identifier()
            self.state = 3847
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,393,self._ctx)
            if la_ == 1:
                self.state = 3846
                self.sys_func_call_port_list()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Sys_func_call_port_listContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_sys_func_call_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSys_func_call_port_list" ):
                listener.enterSys_func_call_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSys_func_call_port_list" ):
                listener.exitSys_func_call_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSys_func_call_port_list" ):
                return visitor.visitSys_func_call_port_list(self)
            else:
                return visitor.visitChildren(self)




    def sys_func_call_port_list(self):

        localctx = VerilogParser.Sys_func_call_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 604, self.RULE_sys_func_call_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3849
            self.match(VerilogParser.LP)
            self.state = 3850
            self.expression(0)
            self.state = 3855
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 3851
                self.match(VerilogParser.CO)
                self.state = 3852
                self.expression(0)
                self.state = 3857
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3858
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Base_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_base_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBase_expression" ):
                listener.enterBase_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBase_expression" ):
                listener.exitBase_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBase_expression" ):
                return visitor.visitBase_expression(self)
            else:
                return visitor.visitChildren(self)




    def base_expression(self):

        localctx = VerilogParser.Base_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 606, self.RULE_base_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3860
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Constant_base_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_constant_base_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_base_expression" ):
                listener.enterConstant_base_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_base_expression" ):
                listener.exitConstant_base_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_base_expression" ):
                return visitor.visitConstant_base_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_base_expression(self):

        localctx = VerilogParser.Constant_base_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 608, self.RULE_constant_base_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3862
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Constant_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_primary(self):
            return self.getTypedRuleContext(VerilogParser.Constant_primaryContext,0)


        def unary_operator(self):
            return self.getTypedRuleContext(VerilogParser.Unary_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def ASAS(self):
            return self.getToken(VerilogParser.ASAS, 0)

        def AS(self):
            return self.getToken(VerilogParser.AS, 0)

        def SL(self):
            return self.getToken(VerilogParser.SL, 0)

        def MO(self):
            return self.getToken(VerilogParser.MO, 0)

        def PL(self):
            return self.getToken(VerilogParser.PL, 0)

        def MI(self):
            return self.getToken(VerilogParser.MI, 0)

        def GTGT(self):
            return self.getToken(VerilogParser.GTGT, 0)

        def LTLT(self):
            return self.getToken(VerilogParser.LTLT, 0)

        def GTGTGT(self):
            return self.getToken(VerilogParser.GTGTGT, 0)

        def LTLTLT(self):
            return self.getToken(VerilogParser.LTLTLT, 0)

        def LT(self):
            return self.getToken(VerilogParser.LT, 0)

        def LTEQ(self):
            return self.getToken(VerilogParser.LTEQ, 0)

        def GT(self):
            return self.getToken(VerilogParser.GT, 0)

        def GTEQ(self):
            return self.getToken(VerilogParser.GTEQ, 0)

        def EQEQ(self):
            return self.getToken(VerilogParser.EQEQ, 0)

        def EMEQ(self):
            return self.getToken(VerilogParser.EMEQ, 0)

        def EQEQEQ(self):
            return self.getToken(VerilogParser.EQEQEQ, 0)

        def EMEQEQ(self):
            return self.getToken(VerilogParser.EMEQEQ, 0)

        def AM(self):
            return self.getToken(VerilogParser.AM, 0)

        def CA(self):
            return self.getToken(VerilogParser.CA, 0)

        def CATI(self):
            return self.getToken(VerilogParser.CATI, 0)

        def TICA(self):
            return self.getToken(VerilogParser.TICA, 0)

        def VL(self):
            return self.getToken(VerilogParser.VL, 0)

        def AMAM(self):
            return self.getToken(VerilogParser.AMAM, 0)

        def VLVL(self):
            return self.getToken(VerilogParser.VLVL, 0)

        def QM(self):
            return self.getToken(VerilogParser.QM, 0)

        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_expression" ):
                listener.enterConstant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_expression" ):
                listener.exitConstant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_expression" ):
                return visitor.visitConstant_expression(self)
            else:
                return visitor.visitChildren(self)



    def constant_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.Constant_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 610
        self.enterRecursionRule(localctx, 610, self.RULE_constant_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3875
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.LC, VerilogParser.LP, VerilogParser.BINARY_BASE, VerilogParser.DECIMAL_BASE, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.EXPONENTIAL_NUMBER, VerilogParser.FIXED_POINT_NUMBER, VerilogParser.HEX_BASE, VerilogParser.OCTAL_BASE, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.STRING, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.UNSIGNED_NUMBER]:
                self.state = 3865
                self.constant_primary()
                pass
            elif token in [VerilogParser.AM, VerilogParser.CA, VerilogParser.CATI, VerilogParser.EM, VerilogParser.MI, VerilogParser.PL, VerilogParser.TI, VerilogParser.TIAM, VerilogParser.TICA, VerilogParser.TIVL, VerilogParser.VL]:
                self.state = 3866
                self.unary_operator()
                self.state = 3870
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,395,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3867
                        self.attribute_instance() 
                    self.state = 3872
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,395,self._ctx)

                self.state = 3873
                self.constant_primary()
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 3990
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,410,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 3988
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,409,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3877
                        if not self.precpred(self._ctx, 12):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 12)")
                        self.state = 3878
                        self.match(VerilogParser.ASAS)
                        self.state = 3882
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,397,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3879
                                self.attribute_instance() 
                            self.state = 3884
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,397,self._ctx)

                        self.state = 3885
                        self.constant_expression(13)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3886
                        if not self.precpred(self._ctx, 11):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 11)")
                        self.state = 3887
                        _la = self._input.LA(1)
                        if not(((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (VerilogParser.AS - 140)) | (1 << (VerilogParser.MO - 140)) | (1 << (VerilogParser.SL - 140)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 3891
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,398,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3888
                                self.attribute_instance() 
                            self.state = 3893
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,398,self._ctx)

                        self.state = 3894
                        self.constant_expression(12)
                        pass

                    elif la_ == 3:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3895
                        if not self.precpred(self._ctx, 10):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 10)")
                        self.state = 3896
                        _la = self._input.LA(1)
                        if not(_la==VerilogParser.MI or _la==VerilogParser.PL):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 3900
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,399,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3897
                                self.attribute_instance() 
                            self.state = 3902
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,399,self._ctx)

                        self.state = 3903
                        self.constant_expression(11)
                        pass

                    elif la_ == 4:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3904
                        if not self.precpred(self._ctx, 9):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 9)")
                        self.state = 3905
                        _la = self._input.LA(1)
                        if not(((((_la - 161)) & ~0x3f) == 0 and ((1 << (_la - 161)) & ((1 << (VerilogParser.GTGT - 161)) | (1 << (VerilogParser.GTGTGT - 161)) | (1 << (VerilogParser.LTLT - 161)) | (1 << (VerilogParser.LTLTLT - 161)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 3909
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,400,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3906
                                self.attribute_instance() 
                            self.state = 3911
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,400,self._ctx)

                        self.state = 3912
                        self.constant_expression(10)
                        pass

                    elif la_ == 5:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3913
                        if not self.precpred(self._ctx, 8):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 8)")
                        self.state = 3914
                        _la = self._input.LA(1)
                        if not(((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (VerilogParser.GT - 159)) | (1 << (VerilogParser.GTEQ - 159)) | (1 << (VerilogParser.LT - 159)) | (1 << (VerilogParser.LTEQ - 159)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 3918
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,401,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3915
                                self.attribute_instance() 
                            self.state = 3920
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,401,self._ctx)

                        self.state = 3921
                        self.constant_expression(9)
                        pass

                    elif la_ == 6:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3922
                        if not self.precpred(self._ctx, 7):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 7)")
                        self.state = 3923
                        _la = self._input.LA(1)
                        if not(((((_la - 152)) & ~0x3f) == 0 and ((1 << (_la - 152)) & ((1 << (VerilogParser.EMEQ - 152)) | (1 << (VerilogParser.EMEQEQ - 152)) | (1 << (VerilogParser.EQEQ - 152)) | (1 << (VerilogParser.EQEQEQ - 152)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 3927
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,402,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3924
                                self.attribute_instance() 
                            self.state = 3929
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,402,self._ctx)

                        self.state = 3930
                        self.constant_expression(8)
                        pass

                    elif la_ == 7:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3931
                        if not self.precpred(self._ctx, 6):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 6)")
                        self.state = 3932
                        self.match(VerilogParser.AM)
                        self.state = 3936
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,403,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3933
                                self.attribute_instance() 
                            self.state = 3938
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,403,self._ctx)

                        self.state = 3939
                        self.constant_expression(7)
                        pass

                    elif la_ == 8:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3940
                        if not self.precpred(self._ctx, 5):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 5)")
                        self.state = 3941
                        _la = self._input.LA(1)
                        if not(((((_la - 144)) & ~0x3f) == 0 and ((1 << (_la - 144)) & ((1 << (VerilogParser.CA - 144)) | (1 << (VerilogParser.CATI - 144)) | (1 << (VerilogParser.TICA - 144)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 3945
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,404,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3942
                                self.attribute_instance() 
                            self.state = 3947
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,404,self._ctx)

                        self.state = 3948
                        self.constant_expression(6)
                        pass

                    elif la_ == 9:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3949
                        if not self.precpred(self._ctx, 4):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 4)")
                        self.state = 3950
                        self.match(VerilogParser.VL)
                        self.state = 3954
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,405,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3951
                                self.attribute_instance() 
                            self.state = 3956
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,405,self._ctx)

                        self.state = 3957
                        self.constant_expression(5)
                        pass

                    elif la_ == 10:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3958
                        if not self.precpred(self._ctx, 3):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 3)")
                        self.state = 3959
                        self.match(VerilogParser.AMAM)
                        self.state = 3963
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,406,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3960
                                self.attribute_instance() 
                            self.state = 3965
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,406,self._ctx)

                        self.state = 3966
                        self.constant_expression(4)
                        pass

                    elif la_ == 11:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3967
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 3968
                        self.match(VerilogParser.VLVL)
                        self.state = 3972
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,407,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3969
                                self.attribute_instance() 
                            self.state = 3974
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,407,self._ctx)

                        self.state = 3975
                        self.constant_expression(3)
                        pass

                    elif la_ == 12:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3976
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 3977
                        self.match(VerilogParser.QM)
                        self.state = 3981
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,408,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3978
                                self.attribute_instance() 
                            self.state = 3983
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,408,self._ctx)

                        self.state = 3984
                        self.constant_expression(0)
                        self.state = 3985
                        self.match(VerilogParser.CL)
                        self.state = 3986
                        self.constant_expression(1)
                        pass

             
                self.state = 3992
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,410,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx

    class Constant_mintypmax_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def CL(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CL)
            else:
                return self.getToken(VerilogParser.CL, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_mintypmax_expression" ):
                listener.enterConstant_mintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_mintypmax_expression" ):
                listener.exitConstant_mintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_mintypmax_expression" ):
                return visitor.visitConstant_mintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_mintypmax_expression(self):

        localctx = VerilogParser.Constant_mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 612, self.RULE_constant_mintypmax_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3993
            self.constant_expression(0)
            self.state = 3999
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CL:
                self.state = 3994
                self.match(VerilogParser.CL)
                self.state = 3995
                self.constant_expression(0)
                self.state = 3996
                self.match(VerilogParser.CL)
                self.state = 3997
                self.constant_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Constant_range_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def msb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Msb_constant_expressionContext,0)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def lsb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Lsb_constant_expressionContext,0)


        def constant_base_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_base_expressionContext,0)


        def PLCL(self):
            return self.getToken(VerilogParser.PLCL, 0)

        def width_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Width_constant_expressionContext,0)


        def MICL(self):
            return self.getToken(VerilogParser.MICL, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_range_expression" ):
                listener.enterConstant_range_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_range_expression" ):
                listener.exitConstant_range_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_range_expression" ):
                return visitor.visitConstant_range_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_range_expression(self):

        localctx = VerilogParser.Constant_range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 614, self.RULE_constant_range_expression)
        try:
            self.state = 4014
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,412,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4001
                self.constant_expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4002
                self.msb_constant_expression()
                self.state = 4003
                self.match(VerilogParser.CL)
                self.state = 4004
                self.lsb_constant_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4006
                self.constant_base_expression()
                self.state = 4007
                self.match(VerilogParser.PLCL)
                self.state = 4008
                self.width_constant_expression()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 4010
                self.constant_base_expression()
                self.state = 4011
                self.match(VerilogParser.MICL)
                self.state = 4012
                self.width_constant_expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Dimension_constant_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_dimension_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDimension_constant_expression" ):
                listener.enterDimension_constant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDimension_constant_expression" ):
                listener.exitDimension_constant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDimension_constant_expression" ):
                return visitor.visitDimension_constant_expression(self)
            else:
                return visitor.visitChildren(self)




    def dimension_constant_expression(self):

        localctx = VerilogParser.Dimension_constant_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 616, self.RULE_dimension_constant_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4016
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class ExpressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def primary(self):
            return self.getTypedRuleContext(VerilogParser.PrimaryContext,0)


        def unary_operator(self):
            return self.getTypedRuleContext(VerilogParser.Unary_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def ASAS(self):
            return self.getToken(VerilogParser.ASAS, 0)

        def AS(self):
            return self.getToken(VerilogParser.AS, 0)

        def SL(self):
            return self.getToken(VerilogParser.SL, 0)

        def MO(self):
            return self.getToken(VerilogParser.MO, 0)

        def PL(self):
            return self.getToken(VerilogParser.PL, 0)

        def MI(self):
            return self.getToken(VerilogParser.MI, 0)

        def GTGT(self):
            return self.getToken(VerilogParser.GTGT, 0)

        def LTLT(self):
            return self.getToken(VerilogParser.LTLT, 0)

        def GTGTGT(self):
            return self.getToken(VerilogParser.GTGTGT, 0)

        def LTLTLT(self):
            return self.getToken(VerilogParser.LTLTLT, 0)

        def LT(self):
            return self.getToken(VerilogParser.LT, 0)

        def LTEQ(self):
            return self.getToken(VerilogParser.LTEQ, 0)

        def GT(self):
            return self.getToken(VerilogParser.GT, 0)

        def GTEQ(self):
            return self.getToken(VerilogParser.GTEQ, 0)

        def EQEQ(self):
            return self.getToken(VerilogParser.EQEQ, 0)

        def EMEQ(self):
            return self.getToken(VerilogParser.EMEQ, 0)

        def EQEQEQ(self):
            return self.getToken(VerilogParser.EQEQEQ, 0)

        def EMEQEQ(self):
            return self.getToken(VerilogParser.EMEQEQ, 0)

        def AM(self):
            return self.getToken(VerilogParser.AM, 0)

        def CA(self):
            return self.getToken(VerilogParser.CA, 0)

        def CATI(self):
            return self.getToken(VerilogParser.CATI, 0)

        def TICA(self):
            return self.getToken(VerilogParser.TICA, 0)

        def VL(self):
            return self.getToken(VerilogParser.VL, 0)

        def AMAM(self):
            return self.getToken(VerilogParser.AMAM, 0)

        def VLVL(self):
            return self.getToken(VerilogParser.VLVL, 0)

        def QM(self):
            return self.getToken(VerilogParser.QM, 0)

        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExpression" ):
                listener.enterExpression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExpression" ):
                listener.exitExpression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExpression" ):
                return visitor.visitExpression(self)
            else:
                return visitor.visitChildren(self)



    def expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.ExpressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 618
        self.enterRecursionRule(localctx, 618, self.RULE_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4029
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.LC, VerilogParser.LP, VerilogParser.BINARY_BASE, VerilogParser.DECIMAL_BASE, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.EXPONENTIAL_NUMBER, VerilogParser.FIXED_POINT_NUMBER, VerilogParser.HEX_BASE, VerilogParser.OCTAL_BASE, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.STRING, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.UNSIGNED_NUMBER]:
                self.state = 4019
                self.primary()
                pass
            elif token in [VerilogParser.AM, VerilogParser.CA, VerilogParser.CATI, VerilogParser.EM, VerilogParser.MI, VerilogParser.PL, VerilogParser.TI, VerilogParser.TIAM, VerilogParser.TICA, VerilogParser.TIVL, VerilogParser.VL]:
                self.state = 4020
                self.unary_operator()
                self.state = 4024
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,413,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 4021
                        self.attribute_instance() 
                    self.state = 4026
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,413,self._ctx)

                self.state = 4027
                self.primary()
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 4144
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,428,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 4142
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,427,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4031
                        if not self.precpred(self._ctx, 12):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 12)")
                        self.state = 4032
                        self.match(VerilogParser.ASAS)
                        self.state = 4036
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,415,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4033
                                self.attribute_instance() 
                            self.state = 4038
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,415,self._ctx)

                        self.state = 4039
                        self.expression(13)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4040
                        if not self.precpred(self._ctx, 11):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 11)")
                        self.state = 4041
                        _la = self._input.LA(1)
                        if not(((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (VerilogParser.AS - 140)) | (1 << (VerilogParser.MO - 140)) | (1 << (VerilogParser.SL - 140)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4045
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,416,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4042
                                self.attribute_instance() 
                            self.state = 4047
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,416,self._ctx)

                        self.state = 4048
                        self.expression(12)
                        pass

                    elif la_ == 3:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4049
                        if not self.precpred(self._ctx, 10):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 10)")
                        self.state = 4050
                        _la = self._input.LA(1)
                        if not(_la==VerilogParser.MI or _la==VerilogParser.PL):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4054
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,417,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4051
                                self.attribute_instance() 
                            self.state = 4056
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,417,self._ctx)

                        self.state = 4057
                        self.expression(11)
                        pass

                    elif la_ == 4:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4058
                        if not self.precpred(self._ctx, 9):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 9)")
                        self.state = 4059
                        _la = self._input.LA(1)
                        if not(((((_la - 161)) & ~0x3f) == 0 and ((1 << (_la - 161)) & ((1 << (VerilogParser.GTGT - 161)) | (1 << (VerilogParser.GTGTGT - 161)) | (1 << (VerilogParser.LTLT - 161)) | (1 << (VerilogParser.LTLTLT - 161)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4063
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,418,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4060
                                self.attribute_instance() 
                            self.state = 4065
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,418,self._ctx)

                        self.state = 4066
                        self.expression(10)
                        pass

                    elif la_ == 5:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4067
                        if not self.precpred(self._ctx, 8):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 8)")
                        self.state = 4068
                        _la = self._input.LA(1)
                        if not(((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (VerilogParser.GT - 159)) | (1 << (VerilogParser.GTEQ - 159)) | (1 << (VerilogParser.LT - 159)) | (1 << (VerilogParser.LTEQ - 159)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4072
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,419,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4069
                                self.attribute_instance() 
                            self.state = 4074
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,419,self._ctx)

                        self.state = 4075
                        self.expression(9)
                        pass

                    elif la_ == 6:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4076
                        if not self.precpred(self._ctx, 7):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 7)")
                        self.state = 4077
                        _la = self._input.LA(1)
                        if not(((((_la - 152)) & ~0x3f) == 0 and ((1 << (_la - 152)) & ((1 << (VerilogParser.EMEQ - 152)) | (1 << (VerilogParser.EMEQEQ - 152)) | (1 << (VerilogParser.EQEQ - 152)) | (1 << (VerilogParser.EQEQEQ - 152)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4081
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,420,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4078
                                self.attribute_instance() 
                            self.state = 4083
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,420,self._ctx)

                        self.state = 4084
                        self.expression(8)
                        pass

                    elif la_ == 7:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4085
                        if not self.precpred(self._ctx, 6):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 6)")
                        self.state = 4086
                        self.match(VerilogParser.AM)
                        self.state = 4090
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,421,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4087
                                self.attribute_instance() 
                            self.state = 4092
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,421,self._ctx)

                        self.state = 4093
                        self.expression(7)
                        pass

                    elif la_ == 8:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4094
                        if not self.precpred(self._ctx, 5):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 5)")
                        self.state = 4095
                        _la = self._input.LA(1)
                        if not(((((_la - 144)) & ~0x3f) == 0 and ((1 << (_la - 144)) & ((1 << (VerilogParser.CA - 144)) | (1 << (VerilogParser.CATI - 144)) | (1 << (VerilogParser.TICA - 144)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4099
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,422,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4096
                                self.attribute_instance() 
                            self.state = 4101
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,422,self._ctx)

                        self.state = 4102
                        self.expression(6)
                        pass

                    elif la_ == 9:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4103
                        if not self.precpred(self._ctx, 4):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 4)")
                        self.state = 4104
                        self.match(VerilogParser.VL)
                        self.state = 4108
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,423,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4105
                                self.attribute_instance() 
                            self.state = 4110
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,423,self._ctx)

                        self.state = 4111
                        self.expression(5)
                        pass

                    elif la_ == 10:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4112
                        if not self.precpred(self._ctx, 3):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 3)")
                        self.state = 4113
                        self.match(VerilogParser.AMAM)
                        self.state = 4117
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,424,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4114
                                self.attribute_instance() 
                            self.state = 4119
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,424,self._ctx)

                        self.state = 4120
                        self.expression(4)
                        pass

                    elif la_ == 11:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4121
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 4122
                        self.match(VerilogParser.VLVL)
                        self.state = 4126
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,425,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4123
                                self.attribute_instance() 
                            self.state = 4128
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,425,self._ctx)

                        self.state = 4129
                        self.expression(3)
                        pass

                    elif la_ == 12:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 4130
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 4131
                        self.match(VerilogParser.QM)
                        self.state = 4135
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,426,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4132
                                self.attribute_instance() 
                            self.state = 4137
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,426,self._ctx)

                        self.state = 4138
                        self.expression(0)
                        self.state = 4139
                        self.match(VerilogParser.CL)
                        self.state = 4140
                        self.expression(1)
                        pass

             
                self.state = 4146
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,428,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx

    class Lsb_constant_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_lsb_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLsb_constant_expression" ):
                listener.enterLsb_constant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLsb_constant_expression" ):
                listener.exitLsb_constant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLsb_constant_expression" ):
                return visitor.visitLsb_constant_expression(self)
            else:
                return visitor.visitChildren(self)




    def lsb_constant_expression(self):

        localctx = VerilogParser.Lsb_constant_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 620, self.RULE_lsb_constant_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4147
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Mintypmax_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def CL(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CL)
            else:
                return self.getToken(VerilogParser.CL, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMintypmax_expression" ):
                listener.enterMintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMintypmax_expression" ):
                listener.exitMintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMintypmax_expression" ):
                return visitor.visitMintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def mintypmax_expression(self):

        localctx = VerilogParser.Mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 622, self.RULE_mintypmax_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4149
            self.expression(0)
            self.state = 4155
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CL:
                self.state = 4150
                self.match(VerilogParser.CL)
                self.state = 4151
                self.expression(0)
                self.state = 4152
                self.match(VerilogParser.CL)
                self.state = 4153
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_path_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_path_primary(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_primaryContext,0)


        def unary_module_path_operator(self):
            return self.getTypedRuleContext(VerilogParser.Unary_module_path_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_path_expressionContext,i)


        def EQEQ(self):
            return self.getToken(VerilogParser.EQEQ, 0)

        def EMEQ(self):
            return self.getToken(VerilogParser.EMEQ, 0)

        def AM(self):
            return self.getToken(VerilogParser.AM, 0)

        def CA(self):
            return self.getToken(VerilogParser.CA, 0)

        def CATI(self):
            return self.getToken(VerilogParser.CATI, 0)

        def TICA(self):
            return self.getToken(VerilogParser.TICA, 0)

        def VL(self):
            return self.getToken(VerilogParser.VL, 0)

        def AMAM(self):
            return self.getToken(VerilogParser.AMAM, 0)

        def VLVL(self):
            return self.getToken(VerilogParser.VLVL, 0)

        def QM(self):
            return self.getToken(VerilogParser.QM, 0)

        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_expression" ):
                listener.enterModule_path_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_expression" ):
                listener.exitModule_path_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_expression" ):
                return visitor.visitModule_path_expression(self)
            else:
                return visitor.visitChildren(self)



    def module_path_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.Module_path_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 624
        self.enterRecursionRule(localctx, 624, self.RULE_module_path_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4168
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.LC, VerilogParser.LP, VerilogParser.BINARY_BASE, VerilogParser.DECIMAL_BASE, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.EXPONENTIAL_NUMBER, VerilogParser.FIXED_POINT_NUMBER, VerilogParser.HEX_BASE, VerilogParser.OCTAL_BASE, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.UNSIGNED_NUMBER]:
                self.state = 4158
                self.module_path_primary()
                pass
            elif token in [VerilogParser.AM, VerilogParser.CA, VerilogParser.CATI, VerilogParser.EM, VerilogParser.TI, VerilogParser.TIAM, VerilogParser.TICA, VerilogParser.TIVL, VerilogParser.VL]:
                self.state = 4159
                self.unary_module_path_operator()
                self.state = 4163
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,430,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 4160
                        self.attribute_instance() 
                    self.state = 4165
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,430,self._ctx)

                self.state = 4166
                self.module_path_primary()
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 4238
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,440,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 4236
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,439,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 4170
                        if not self.precpred(self._ctx, 7):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 7)")
                        self.state = 4171
                        _la = self._input.LA(1)
                        if not(_la==VerilogParser.EMEQ or _la==VerilogParser.EQEQ):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4175
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,432,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4172
                                self.attribute_instance() 
                            self.state = 4177
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,432,self._ctx)

                        self.state = 4178
                        self.module_path_expression(8)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 4179
                        if not self.precpred(self._ctx, 6):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 6)")
                        self.state = 4180
                        self.match(VerilogParser.AM)
                        self.state = 4184
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,433,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4181
                                self.attribute_instance() 
                            self.state = 4186
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,433,self._ctx)

                        self.state = 4187
                        self.module_path_expression(7)
                        pass

                    elif la_ == 3:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 4188
                        if not self.precpred(self._ctx, 5):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 5)")
                        self.state = 4189
                        _la = self._input.LA(1)
                        if not(((((_la - 144)) & ~0x3f) == 0 and ((1 << (_la - 144)) & ((1 << (VerilogParser.CA - 144)) | (1 << (VerilogParser.CATI - 144)) | (1 << (VerilogParser.TICA - 144)))) != 0)):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4193
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,434,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4190
                                self.attribute_instance() 
                            self.state = 4195
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,434,self._ctx)

                        self.state = 4196
                        self.module_path_expression(6)
                        pass

                    elif la_ == 4:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 4197
                        if not self.precpred(self._ctx, 4):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 4)")
                        self.state = 4198
                        self.match(VerilogParser.VL)
                        self.state = 4202
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,435,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4199
                                self.attribute_instance() 
                            self.state = 4204
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,435,self._ctx)

                        self.state = 4205
                        self.module_path_expression(5)
                        pass

                    elif la_ == 5:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 4206
                        if not self.precpred(self._ctx, 3):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 3)")
                        self.state = 4207
                        self.match(VerilogParser.AMAM)
                        self.state = 4211
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,436,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4208
                                self.attribute_instance() 
                            self.state = 4213
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,436,self._ctx)

                        self.state = 4214
                        self.module_path_expression(4)
                        pass

                    elif la_ == 6:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 4215
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 4216
                        self.match(VerilogParser.VLVL)
                        self.state = 4220
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,437,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4217
                                self.attribute_instance() 
                            self.state = 4222
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,437,self._ctx)

                        self.state = 4223
                        self.module_path_expression(3)
                        pass

                    elif la_ == 7:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 4224
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 4225
                        self.match(VerilogParser.QM)
                        self.state = 4229
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,438,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4226
                                self.attribute_instance() 
                            self.state = 4231
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,438,self._ctx)

                        self.state = 4232
                        self.module_path_expression(0)
                        self.state = 4233
                        self.match(VerilogParser.CL)
                        self.state = 4234
                        self.module_path_expression(1)
                        pass

             
                self.state = 4240
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,440,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx

    class Module_path_mintypmax_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_path_expressionContext,i)


        def CL(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CL)
            else:
                return self.getToken(VerilogParser.CL, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_mintypmax_expression" ):
                listener.enterModule_path_mintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_mintypmax_expression" ):
                listener.exitModule_path_mintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_mintypmax_expression" ):
                return visitor.visitModule_path_mintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def module_path_mintypmax_expression(self):

        localctx = VerilogParser.Module_path_mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 626, self.RULE_module_path_mintypmax_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4241
            self.module_path_expression(0)
            self.state = 4247
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.CL:
                self.state = 4242
                self.match(VerilogParser.CL)
                self.state = 4243
                self.module_path_expression(0)
                self.state = 4244
                self.match(VerilogParser.CL)
                self.state = 4245
                self.module_path_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Msb_constant_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_msb_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMsb_constant_expression" ):
                listener.enterMsb_constant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMsb_constant_expression" ):
                listener.exitMsb_constant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMsb_constant_expression" ):
                return visitor.visitMsb_constant_expression(self)
            else:
                return visitor.visitChildren(self)




    def msb_constant_expression(self):

        localctx = VerilogParser.Msb_constant_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 628, self.RULE_msb_constant_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4249
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Range_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def msb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Msb_constant_expressionContext,0)


        def CL(self):
            return self.getToken(VerilogParser.CL, 0)

        def lsb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Lsb_constant_expressionContext,0)


        def base_expression(self):
            return self.getTypedRuleContext(VerilogParser.Base_expressionContext,0)


        def PLCL(self):
            return self.getToken(VerilogParser.PLCL, 0)

        def width_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Width_constant_expressionContext,0)


        def MICL(self):
            return self.getToken(VerilogParser.MICL, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRange_expression" ):
                listener.enterRange_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRange_expression" ):
                listener.exitRange_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRange_expression" ):
                return visitor.visitRange_expression(self)
            else:
                return visitor.visitChildren(self)




    def range_expression(self):

        localctx = VerilogParser.Range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 630, self.RULE_range_expression)
        try:
            self.state = 4264
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,442,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4251
                self.expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4252
                self.msb_constant_expression()
                self.state = 4253
                self.match(VerilogParser.CL)
                self.state = 4254
                self.lsb_constant_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4256
                self.base_expression()
                self.state = 4257
                self.match(VerilogParser.PLCL)
                self.state = 4258
                self.width_constant_expression()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 4260
                self.base_expression()
                self.state = 4261
                self.match(VerilogParser.MICL)
                self.state = 4262
                self.width_constant_expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Width_constant_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_width_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWidth_constant_expression" ):
                listener.enterWidth_constant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWidth_constant_expression" ):
                listener.exitWidth_constant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWidth_constant_expression" ):
                return visitor.visitWidth_constant_expression(self)
            else:
                return visitor.visitChildren(self)




    def width_constant_expression(self):

        localctx = VerilogParser.Width_constant_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 632, self.RULE_width_constant_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4266
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Constant_primaryContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(VerilogParser.NumberContext,0)


        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def constant_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Constant_concatenationContext,0)


        def constant_multiple_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Constant_multiple_concatenationContext,0)


        def constant_function_call(self):
            return self.getTypedRuleContext(VerilogParser.Constant_function_callContext,0)


        def constant_system_function_call(self):
            return self.getTypedRuleContext(VerilogParser.Constant_system_function_callContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def string_(self):
            return self.getTypedRuleContext(VerilogParser.String_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_constant_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_primary" ):
                listener.enterConstant_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_primary" ):
                listener.exitConstant_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_primary" ):
                return visitor.visitConstant_primary(self)
            else:
                return visitor.visitChildren(self)




    def constant_primary(self):

        localctx = VerilogParser.Constant_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 634, self.RULE_constant_primary)
        try:
            self.state = 4285
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,444,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4268
                self.number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4269
                self.identifier()
                self.state = 4274
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,443,self._ctx)
                if la_ == 1:
                    self.state = 4270
                    self.match(VerilogParser.LB)
                    self.state = 4271
                    self.constant_range_expression()
                    self.state = 4272
                    self.match(VerilogParser.RB)


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4276
                self.constant_concatenation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 4277
                self.constant_multiple_concatenation()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 4278
                self.constant_function_call()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 4279
                self.constant_system_function_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 4280
                self.match(VerilogParser.LP)
                self.state = 4281
                self.constant_mintypmax_expression()
                self.state = 4282
                self.match(VerilogParser.RP)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 4284
                self.string_()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_path_primaryContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(VerilogParser.NumberContext,0)


        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def module_path_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_concatenationContext,0)


        def module_path_multiple_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_multiple_concatenationContext,0)


        def function_call(self):
            return self.getTypedRuleContext(VerilogParser.Function_callContext,0)


        def system_function_call(self):
            return self.getTypedRuleContext(VerilogParser.System_function_callContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def module_path_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_primary" ):
                listener.enterModule_path_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_primary" ):
                listener.exitModule_path_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_primary" ):
                return visitor.visitModule_path_primary(self)
            else:
                return visitor.visitChildren(self)




    def module_path_primary(self):

        localctx = VerilogParser.Module_path_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 636, self.RULE_module_path_primary)
        try:
            self.state = 4297
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,445,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4287
                self.number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4288
                self.identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4289
                self.module_path_concatenation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 4290
                self.module_path_multiple_concatenation()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 4291
                self.function_call()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 4292
                self.system_function_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 4293
                self.match(VerilogParser.LP)
                self.state = 4294
                self.module_path_mintypmax_expression()
                self.state = 4295
                self.match(VerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class PrimaryContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(VerilogParser.NumberContext,0)


        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def select_(self):
            return self.getTypedRuleContext(VerilogParser.Select_Context,0)


        def concatenation(self):
            return self.getTypedRuleContext(VerilogParser.ConcatenationContext,0)


        def multiple_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Multiple_concatenationContext,0)


        def function_call(self):
            return self.getTypedRuleContext(VerilogParser.Function_callContext,0)


        def system_function_call(self):
            return self.getTypedRuleContext(VerilogParser.System_function_callContext,0)


        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def string_(self):
            return self.getTypedRuleContext(VerilogParser.String_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrimary" ):
                listener.enterPrimary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrimary" ):
                listener.exitPrimary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrimary" ):
                return visitor.visitPrimary(self)
            else:
                return visitor.visitChildren(self)




    def primary(self):

        localctx = VerilogParser.PrimaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 638, self.RULE_primary)
        try:
            self.state = 4313
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,447,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4299
                self.number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4300
                self.hierarchical_identifier()
                self.state = 4302
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,446,self._ctx)
                if la_ == 1:
                    self.state = 4301
                    self.select_()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4304
                self.concatenation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 4305
                self.multiple_concatenation()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 4306
                self.function_call()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 4307
                self.system_function_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 4308
                self.match(VerilogParser.LP)
                self.state = 4309
                self.mintypmax_expression()
                self.state = 4310
                self.match(VerilogParser.RP)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 4312
                self.string_()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Select_Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Range_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def bit_select(self):
            return self.getTypedRuleContext(VerilogParser.Bit_selectContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_select_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSelect_" ):
                listener.enterSelect_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSelect_" ):
                listener.exitSelect_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSelect_" ):
                return visitor.visitSelect_(self)
            else:
                return visitor.visitChildren(self)




    def select_(self):

        localctx = VerilogParser.Select_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 640, self.RULE_select_)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4316
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,448,self._ctx)
            if la_ == 1:
                self.state = 4315
                self.bit_select()


            self.state = 4318
            self.match(VerilogParser.LB)
            self.state = 4319
            self.range_expression()
            self.state = 4320
            self.match(VerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Bit_selectContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LB)
            else:
                return self.getToken(VerilogParser.LB, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RB(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RB)
            else:
                return self.getToken(VerilogParser.RB, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_bit_select

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBit_select" ):
                listener.enterBit_select(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBit_select" ):
                listener.exitBit_select(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBit_select" ):
                return visitor.visitBit_select(self)
            else:
                return visitor.visitChildren(self)




    def bit_select(self):

        localctx = VerilogParser.Bit_selectContext(self, self._ctx, self.state)
        self.enterRule(localctx, 642, self.RULE_bit_select)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4326 
            self._errHandler.sync(self)
            _alt = 1
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt == 1:
                    self.state = 4322
                    self.match(VerilogParser.LB)
                    self.state = 4323
                    self.expression(0)
                    self.state = 4324
                    self.match(VerilogParser.RB)

                else:
                    raise NoViableAltException(self)
                self.state = 4328 
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,449,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Net_lvalueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def const_select(self):
            return self.getTypedRuleContext(VerilogParser.Const_selectContext,0)


        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def net_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Net_lvalueContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,i)


        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_net_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_lvalue" ):
                listener.enterNet_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_lvalue" ):
                listener.exitNet_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_lvalue" ):
                return visitor.visitNet_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def net_lvalue(self):

        localctx = VerilogParser.Net_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 644, self.RULE_net_lvalue)
        self._la = 0 # Token type
        try:
            self.state = 4345
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4330
                self.hierarchical_identifier()
                self.state = 4332
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 4331
                    self.const_select()


                pass
            elif token in [VerilogParser.LC]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4334
                self.match(VerilogParser.LC)
                self.state = 4335
                self.net_lvalue()
                self.state = 4340
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 4336
                    self.match(VerilogParser.CO)
                    self.state = 4337
                    self.net_lvalue()
                    self.state = 4342
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4343
                self.match(VerilogParser.RC)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Const_selectContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(VerilogParser.LB, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RB(self):
            return self.getToken(VerilogParser.RB, 0)

        def const_bit_select(self):
            return self.getTypedRuleContext(VerilogParser.Const_bit_selectContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_const_select

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConst_select" ):
                listener.enterConst_select(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConst_select" ):
                listener.exitConst_select(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConst_select" ):
                return visitor.visitConst_select(self)
            else:
                return visitor.visitChildren(self)




    def const_select(self):

        localctx = VerilogParser.Const_selectContext(self, self._ctx, self.state)
        self.enterRule(localctx, 646, self.RULE_const_select)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4348
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,453,self._ctx)
            if la_ == 1:
                self.state = 4347
                self.const_bit_select()


            self.state = 4350
            self.match(VerilogParser.LB)
            self.state = 4351
            self.constant_range_expression()
            self.state = 4352
            self.match(VerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Const_bit_selectContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LB)
            else:
                return self.getToken(VerilogParser.LB, i)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def RB(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RB)
            else:
                return self.getToken(VerilogParser.RB, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_const_bit_select

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConst_bit_select" ):
                listener.enterConst_bit_select(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConst_bit_select" ):
                listener.exitConst_bit_select(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConst_bit_select" ):
                return visitor.visitConst_bit_select(self)
            else:
                return visitor.visitChildren(self)




    def const_bit_select(self):

        localctx = VerilogParser.Const_bit_selectContext(self, self._ctx, self.state)
        self.enterRule(localctx, 648, self.RULE_const_bit_select)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4358 
            self._errHandler.sync(self)
            _alt = 1
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt == 1:
                    self.state = 4354
                    self.match(VerilogParser.LB)
                    self.state = 4355
                    self.constant_expression(0)
                    self.state = 4356
                    self.match(VerilogParser.RB)

                else:
                    raise NoViableAltException(self)
                self.state = 4360 
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,454,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Variable_lvalueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def select_(self):
            return self.getTypedRuleContext(VerilogParser.Select_Context,0)


        def LC(self):
            return self.getToken(VerilogParser.LC, 0)

        def variable_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Variable_lvalueContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,i)


        def RC(self):
            return self.getToken(VerilogParser.RC, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_variable_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_lvalue" ):
                listener.enterVariable_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_lvalue" ):
                listener.exitVariable_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_lvalue" ):
                return visitor.visitVariable_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def variable_lvalue(self):

        localctx = VerilogParser.Variable_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 650, self.RULE_variable_lvalue)
        self._la = 0 # Token type
        try:
            self.state = 4377
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4362
                self.hierarchical_identifier()
                self.state = 4364
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LB:
                    self.state = 4363
                    self.select_()


                pass
            elif token in [VerilogParser.LC]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4366
                self.match(VerilogParser.LC)
                self.state = 4367
                self.variable_lvalue()
                self.state = 4372
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.CO:
                    self.state = 4368
                    self.match(VerilogParser.CO)
                    self.state = 4369
                    self.variable_lvalue()
                    self.state = 4374
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4375
                self.match(VerilogParser.RC)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Unary_operatorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PL(self):
            return self.getToken(VerilogParser.PL, 0)

        def MI(self):
            return self.getToken(VerilogParser.MI, 0)

        def EM(self):
            return self.getToken(VerilogParser.EM, 0)

        def TI(self):
            return self.getToken(VerilogParser.TI, 0)

        def AM(self):
            return self.getToken(VerilogParser.AM, 0)

        def TIAM(self):
            return self.getToken(VerilogParser.TIAM, 0)

        def VL(self):
            return self.getToken(VerilogParser.VL, 0)

        def TIVL(self):
            return self.getToken(VerilogParser.TIVL, 0)

        def CA(self):
            return self.getToken(VerilogParser.CA, 0)

        def TICA(self):
            return self.getToken(VerilogParser.TICA, 0)

        def CATI(self):
            return self.getToken(VerilogParser.CATI, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_unary_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_operator" ):
                listener.enterUnary_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_operator" ):
                listener.exitUnary_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_operator" ):
                return visitor.visitUnary_operator(self)
            else:
                return visitor.visitChildren(self)




    def unary_operator(self):

        localctx = VerilogParser.Unary_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 652, self.RULE_unary_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4379
            _la = self._input.LA(1)
            if not(((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.MI - 137)) | (1 << (VerilogParser.PL - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Unary_module_path_operatorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EM(self):
            return self.getToken(VerilogParser.EM, 0)

        def TI(self):
            return self.getToken(VerilogParser.TI, 0)

        def AM(self):
            return self.getToken(VerilogParser.AM, 0)

        def TIAM(self):
            return self.getToken(VerilogParser.TIAM, 0)

        def VL(self):
            return self.getToken(VerilogParser.VL, 0)

        def TIVL(self):
            return self.getToken(VerilogParser.TIVL, 0)

        def CA(self):
            return self.getToken(VerilogParser.CA, 0)

        def TICA(self):
            return self.getToken(VerilogParser.TICA, 0)

        def CATI(self):
            return self.getToken(VerilogParser.CATI, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_unary_module_path_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_module_path_operator" ):
                listener.enterUnary_module_path_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_module_path_operator" ):
                listener.exitUnary_module_path_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_module_path_operator" ):
                return visitor.visitUnary_module_path_operator(self)
            else:
                return visitor.visitChildren(self)




    def unary_module_path_operator(self):

        localctx = VerilogParser.Unary_module_path_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 654, self.RULE_unary_module_path_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4381
            _la = self._input.LA(1)
            if not(((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.AM - 137)) | (1 << (VerilogParser.CA - 137)) | (1 << (VerilogParser.CATI - 137)) | (1 << (VerilogParser.EM - 137)) | (1 << (VerilogParser.TI - 137)) | (1 << (VerilogParser.TIAM - 137)) | (1 << (VerilogParser.TICA - 137)) | (1 << (VerilogParser.TIVL - 137)) | (1 << (VerilogParser.VL - 137)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class NumberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def decimal_number(self):
            return self.getTypedRuleContext(VerilogParser.Decimal_numberContext,0)


        def octal_number(self):
            return self.getTypedRuleContext(VerilogParser.Octal_numberContext,0)


        def binary_number(self):
            return self.getTypedRuleContext(VerilogParser.Binary_numberContext,0)


        def hex_number(self):
            return self.getTypedRuleContext(VerilogParser.Hex_numberContext,0)


        def real_number(self):
            return self.getTypedRuleContext(VerilogParser.Real_numberContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNumber" ):
                listener.enterNumber(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNumber" ):
                listener.exitNumber(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNumber" ):
                return visitor.visitNumber(self)
            else:
                return visitor.visitChildren(self)




    def number(self):

        localctx = VerilogParser.NumberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 656, self.RULE_number)
        try:
            self.state = 4388
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,458,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4383
                self.decimal_number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4384
                self.octal_number()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4385
                self.binary_number()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 4386
                self.hex_number()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 4387
                self.real_number()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Real_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def fixed_point_number(self):
            return self.getTypedRuleContext(VerilogParser.Fixed_point_numberContext,0)


        def exponential_number(self):
            return self.getTypedRuleContext(VerilogParser.Exponential_numberContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_real_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_number" ):
                listener.enterReal_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_number" ):
                listener.exitReal_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_number" ):
                return visitor.visitReal_number(self)
            else:
                return visitor.visitChildren(self)




    def real_number(self):

        localctx = VerilogParser.Real_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 658, self.RULE_real_number)
        try:
            self.state = 4392
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.FIXED_POINT_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4390
                self.fixed_point_number()
                pass
            elif token in [VerilogParser.EXPONENTIAL_NUMBER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4391
                self.exponential_number()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Decimal_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def unsigned_number(self):
            return self.getTypedRuleContext(VerilogParser.Unsigned_numberContext,0)


        def decimal_base(self):
            return self.getTypedRuleContext(VerilogParser.Decimal_baseContext,0)


        def decimal_value(self):
            return self.getTypedRuleContext(VerilogParser.Decimal_valueContext,0)


        def size(self):
            return self.getTypedRuleContext(VerilogParser.SizeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_decimal_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDecimal_number" ):
                listener.enterDecimal_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDecimal_number" ):
                listener.exitDecimal_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDecimal_number" ):
                return visitor.visitDecimal_number(self)
            else:
                return visitor.visitChildren(self)




    def decimal_number(self):

        localctx = VerilogParser.Decimal_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 660, self.RULE_decimal_number)
        self._la = 0 # Token type
        try:
            self.state = 4401
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,461,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4394
                self.unsigned_number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4396
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.UNSIGNED_NUMBER:
                    self.state = 4395
                    self.size()


                self.state = 4398
                self.decimal_base()
                self.state = 4399
                self.decimal_value()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Binary_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def binary_base(self):
            return self.getTypedRuleContext(VerilogParser.Binary_baseContext,0)


        def binary_value(self):
            return self.getTypedRuleContext(VerilogParser.Binary_valueContext,0)


        def size(self):
            return self.getTypedRuleContext(VerilogParser.SizeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_binary_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_number" ):
                listener.enterBinary_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_number" ):
                listener.exitBinary_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_number" ):
                return visitor.visitBinary_number(self)
            else:
                return visitor.visitChildren(self)




    def binary_number(self):

        localctx = VerilogParser.Binary_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 662, self.RULE_binary_number)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4404
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 4403
                self.size()


            self.state = 4406
            self.binary_base()
            self.state = 4407
            self.binary_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Octal_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def octal_base(self):
            return self.getTypedRuleContext(VerilogParser.Octal_baseContext,0)


        def octal_value(self):
            return self.getTypedRuleContext(VerilogParser.Octal_valueContext,0)


        def size(self):
            return self.getTypedRuleContext(VerilogParser.SizeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_octal_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOctal_number" ):
                listener.enterOctal_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOctal_number" ):
                listener.exitOctal_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOctal_number" ):
                return visitor.visitOctal_number(self)
            else:
                return visitor.visitChildren(self)




    def octal_number(self):

        localctx = VerilogParser.Octal_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 664, self.RULE_octal_number)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4410
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 4409
                self.size()


            self.state = 4412
            self.octal_base()
            self.state = 4413
            self.octal_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Hex_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hex_base(self):
            return self.getTypedRuleContext(VerilogParser.Hex_baseContext,0)


        def hex_value(self):
            return self.getTypedRuleContext(VerilogParser.Hex_valueContext,0)


        def size(self):
            return self.getTypedRuleContext(VerilogParser.SizeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hex_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHex_number" ):
                listener.enterHex_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHex_number" ):
                listener.exitHex_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHex_number" ):
                return visitor.visitHex_number(self)
            else:
                return visitor.visitChildren(self)




    def hex_number(self):

        localctx = VerilogParser.Hex_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 666, self.RULE_hex_number)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4416
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.UNSIGNED_NUMBER:
                self.state = 4415
                self.size()


            self.state = 4418
            self.hex_base()
            self.state = 4419
            self.hex_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class SizeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def UNSIGNED_NUMBER(self):
            return self.getToken(VerilogParser.UNSIGNED_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_size

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSize" ):
                listener.enterSize(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSize" ):
                listener.exitSize(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSize" ):
                return visitor.visitSize(self)
            else:
                return visitor.visitChildren(self)




    def size(self):

        localctx = VerilogParser.SizeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 668, self.RULE_size)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4421
            self.match(VerilogParser.UNSIGNED_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Fixed_point_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FIXED_POINT_NUMBER(self):
            return self.getToken(VerilogParser.FIXED_POINT_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_fixed_point_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFixed_point_number" ):
                listener.enterFixed_point_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFixed_point_number" ):
                listener.exitFixed_point_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFixed_point_number" ):
                return visitor.visitFixed_point_number(self)
            else:
                return visitor.visitChildren(self)




    def fixed_point_number(self):

        localctx = VerilogParser.Fixed_point_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 670, self.RULE_fixed_point_number)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4423
            self.match(VerilogParser.FIXED_POINT_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Exponential_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EXPONENTIAL_NUMBER(self):
            return self.getToken(VerilogParser.EXPONENTIAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_exponential_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExponential_number" ):
                listener.enterExponential_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExponential_number" ):
                listener.exitExponential_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExponential_number" ):
                return visitor.visitExponential_number(self)
            else:
                return visitor.visitChildren(self)




    def exponential_number(self):

        localctx = VerilogParser.Exponential_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 672, self.RULE_exponential_number)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4425
            self.match(VerilogParser.EXPONENTIAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Unsigned_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def UNSIGNED_NUMBER(self):
            return self.getToken(VerilogParser.UNSIGNED_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_unsigned_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnsigned_number" ):
                listener.enterUnsigned_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnsigned_number" ):
                listener.exitUnsigned_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnsigned_number" ):
                return visitor.visitUnsigned_number(self)
            else:
                return visitor.visitChildren(self)




    def unsigned_number(self):

        localctx = VerilogParser.Unsigned_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 674, self.RULE_unsigned_number)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4427
            self.match(VerilogParser.UNSIGNED_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Decimal_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def UNSIGNED_NUMBER(self):
            return self.getToken(VerilogParser.UNSIGNED_NUMBER, 0)

        def X_OR_Z_UNDERSCORE(self):
            return self.getToken(VerilogParser.X_OR_Z_UNDERSCORE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_decimal_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDecimal_value" ):
                listener.enterDecimal_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDecimal_value" ):
                listener.exitDecimal_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDecimal_value" ):
                return visitor.visitDecimal_value(self)
            else:
                return visitor.visitChildren(self)




    def decimal_value(self):

        localctx = VerilogParser.Decimal_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 676, self.RULE_decimal_value)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4429
            _la = self._input.LA(1)
            if not(_la==VerilogParser.UNSIGNED_NUMBER or _la==VerilogParser.X_OR_Z_UNDERSCORE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Binary_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def BINARY_VALUE(self):
            return self.getToken(VerilogParser.BINARY_VALUE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_binary_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_value" ):
                listener.enterBinary_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_value" ):
                listener.exitBinary_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_value" ):
                return visitor.visitBinary_value(self)
            else:
                return visitor.visitChildren(self)




    def binary_value(self):

        localctx = VerilogParser.Binary_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 678, self.RULE_binary_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4431
            self.match(VerilogParser.BINARY_VALUE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Octal_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def OCTAL_VALUE(self):
            return self.getToken(VerilogParser.OCTAL_VALUE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_octal_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOctal_value" ):
                listener.enterOctal_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOctal_value" ):
                listener.exitOctal_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOctal_value" ):
                return visitor.visitOctal_value(self)
            else:
                return visitor.visitChildren(self)




    def octal_value(self):

        localctx = VerilogParser.Octal_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 680, self.RULE_octal_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4433
            self.match(VerilogParser.OCTAL_VALUE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Hex_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HEX_VALUE(self):
            return self.getToken(VerilogParser.HEX_VALUE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_hex_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHex_value" ):
                listener.enterHex_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHex_value" ):
                listener.exitHex_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHex_value" ):
                return visitor.visitHex_value(self)
            else:
                return visitor.visitChildren(self)




    def hex_value(self):

        localctx = VerilogParser.Hex_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 682, self.RULE_hex_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4435
            self.match(VerilogParser.HEX_VALUE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Decimal_baseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_BASE(self):
            return self.getToken(VerilogParser.DECIMAL_BASE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_decimal_base

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDecimal_base" ):
                listener.enterDecimal_base(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDecimal_base" ):
                listener.exitDecimal_base(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDecimal_base" ):
                return visitor.visitDecimal_base(self)
            else:
                return visitor.visitChildren(self)




    def decimal_base(self):

        localctx = VerilogParser.Decimal_baseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 684, self.RULE_decimal_base)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4437
            self.match(VerilogParser.DECIMAL_BASE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Binary_baseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def BINARY_BASE(self):
            return self.getToken(VerilogParser.BINARY_BASE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_binary_base

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_base" ):
                listener.enterBinary_base(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_base" ):
                listener.exitBinary_base(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_base" ):
                return visitor.visitBinary_base(self)
            else:
                return visitor.visitChildren(self)




    def binary_base(self):

        localctx = VerilogParser.Binary_baseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 686, self.RULE_binary_base)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4439
            self.match(VerilogParser.BINARY_BASE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Octal_baseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def OCTAL_BASE(self):
            return self.getToken(VerilogParser.OCTAL_BASE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_octal_base

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOctal_base" ):
                listener.enterOctal_base(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOctal_base" ):
                listener.exitOctal_base(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOctal_base" ):
                return visitor.visitOctal_base(self)
            else:
                return visitor.visitChildren(self)




    def octal_base(self):

        localctx = VerilogParser.Octal_baseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 688, self.RULE_octal_base)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4441
            self.match(VerilogParser.OCTAL_BASE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Hex_baseContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HEX_BASE(self):
            return self.getToken(VerilogParser.HEX_BASE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_hex_base

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHex_base" ):
                listener.enterHex_base(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHex_base" ):
                listener.exitHex_base(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHex_base" ):
                return visitor.visitHex_base(self)
            else:
                return visitor.visitChildren(self)




    def hex_base(self):

        localctx = VerilogParser.Hex_baseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 690, self.RULE_hex_base)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4443
            self.match(VerilogParser.HEX_BASE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class String_Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def STRING(self):
            return self.getToken(VerilogParser.STRING, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_string_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterString_" ):
                listener.enterString_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitString_" ):
                listener.exitString_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitString_" ):
                return visitor.visitString_(self)
            else:
                return visitor.visitChildren(self)




    def string_(self):

        localctx = VerilogParser.String_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 692, self.RULE_string_)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4445
            self.match(VerilogParser.STRING)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Attribute_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(VerilogParser.LP, 0)

        def AS(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.AS)
            else:
                return self.getToken(VerilogParser.AS, i)

        def attr_spec(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attr_specContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attr_specContext,i)


        def RP(self):
            return self.getToken(VerilogParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.CO)
            else:
                return self.getToken(VerilogParser.CO, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_attribute_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttribute_instance" ):
                listener.enterAttribute_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttribute_instance" ):
                listener.exitAttribute_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttribute_instance" ):
                return visitor.visitAttribute_instance(self)
            else:
                return visitor.visitChildren(self)




    def attribute_instance(self):

        localctx = VerilogParser.Attribute_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 694, self.RULE_attribute_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4447
            self.match(VerilogParser.LP)
            self.state = 4448
            self.match(VerilogParser.AS)
            self.state = 4449
            self.attr_spec()
            self.state = 4454
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.CO:
                self.state = 4450
                self.match(VerilogParser.CO)
                self.state = 4451
                self.attr_spec()
                self.state = 4456
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4457
            self.match(VerilogParser.AS)
            self.state = 4458
            self.match(VerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Attr_specContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_name(self):
            return self.getTypedRuleContext(VerilogParser.Attr_nameContext,0)


        def EQ(self):
            return self.getToken(VerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_attr_spec

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_spec" ):
                listener.enterAttr_spec(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_spec" ):
                listener.exitAttr_spec(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_spec" ):
                return visitor.visitAttr_spec(self)
            else:
                return visitor.visitChildren(self)




    def attr_spec(self):

        localctx = VerilogParser.Attr_specContext(self, self._ctx, self.state)
        self.enterRule(localctx, 696, self.RULE_attr_spec)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4460
            self.attr_name()
            self.state = 4463
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.EQ:
                self.state = 4461
                self.match(VerilogParser.EQ)
                self.state = 4462
                self.constant_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Attr_nameContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_attr_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_name" ):
                listener.enterAttr_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_name" ):
                listener.exitAttr_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_name" ):
                return visitor.visitAttr_name(self)
            else:
                return visitor.visitChildren(self)




    def attr_name(self):

        localctx = VerilogParser.Attr_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 698, self.RULE_attr_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4465
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Block_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_identifier" ):
                listener.enterBlock_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_identifier" ):
                listener.exitBlock_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_identifier" ):
                return visitor.visitBlock_identifier(self)
            else:
                return visitor.visitChildren(self)




    def block_identifier(self):

        localctx = VerilogParser.Block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 700, self.RULE_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4467
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Cell_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_cell_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCell_identifier" ):
                listener.enterCell_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCell_identifier" ):
                listener.exitCell_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCell_identifier" ):
                return visitor.visitCell_identifier(self)
            else:
                return visitor.visitChildren(self)




    def cell_identifier(self):

        localctx = VerilogParser.Cell_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 702, self.RULE_cell_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4469
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Config_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_config_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_identifier" ):
                listener.enterConfig_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_identifier" ):
                listener.exitConfig_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_identifier" ):
                return visitor.visitConfig_identifier(self)
            else:
                return visitor.visitChildren(self)




    def config_identifier(self):

        localctx = VerilogParser.Config_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 704, self.RULE_config_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4471
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Escaped_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ESCAPED_IDENTIFIER(self):
            return self.getToken(VerilogParser.ESCAPED_IDENTIFIER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_escaped_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEscaped_identifier" ):
                listener.enterEscaped_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEscaped_identifier" ):
                listener.exitEscaped_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEscaped_identifier" ):
                return visitor.visitEscaped_identifier(self)
            else:
                return visitor.visitChildren(self)




    def escaped_identifier(self):

        localctx = VerilogParser.Escaped_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 706, self.RULE_escaped_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4473
            self.match(VerilogParser.ESCAPED_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Event_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_event_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_identifier" ):
                listener.enterEvent_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_identifier" ):
                listener.exitEvent_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_identifier" ):
                return visitor.visitEvent_identifier(self)
            else:
                return visitor.visitChildren(self)




    def event_identifier(self):

        localctx = VerilogParser.Event_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 708, self.RULE_event_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4475
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Function_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_identifier" ):
                listener.enterFunction_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_identifier" ):
                listener.exitFunction_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_identifier" ):
                return visitor.visitFunction_identifier(self)
            else:
                return visitor.visitChildren(self)




    def function_identifier(self):

        localctx = VerilogParser.Function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 710, self.RULE_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4477
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Gate_instance_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_gate_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGate_instance_identifier" ):
                listener.enterGate_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGate_instance_identifier" ):
                listener.exitGate_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGate_instance_identifier" ):
                return visitor.visitGate_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def gate_instance_identifier(self):

        localctx = VerilogParser.Gate_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 712, self.RULE_gate_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4479
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Generate_block_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_generate_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block_identifier" ):
                listener.enterGenerate_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block_identifier" ):
                listener.exitGenerate_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block_identifier" ):
                return visitor.visitGenerate_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def generate_block_identifier(self):

        localctx = VerilogParser.Generate_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 714, self.RULE_generate_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4481
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Genvar_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_identifier" ):
                listener.enterGenvar_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_identifier" ):
                listener.exitGenvar_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_identifier" ):
                return visitor.visitGenvar_identifier(self)
            else:
                return visitor.visitChildren(self)




    def genvar_identifier(self):

        localctx = VerilogParser.Genvar_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 716, self.RULE_genvar_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4483
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Hierarchical_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def hier_ref(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Hier_refContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Hier_refContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_identifier" ):
                listener.enterHierarchical_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_identifier" ):
                listener.exitHierarchical_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_identifier" ):
                return visitor.visitHierarchical_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_identifier(self):

        localctx = VerilogParser.Hierarchical_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 718, self.RULE_hierarchical_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4488
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,467,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 4485
                    self.hier_ref() 
                self.state = 4490
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,467,self._ctx)

            self.state = 4491
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Hier_refContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def DT(self):
            return self.getToken(VerilogParser.DT, 0)

        def const_bit_select(self):
            return self.getTypedRuleContext(VerilogParser.Const_bit_selectContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hier_ref

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHier_ref" ):
                listener.enterHier_ref(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHier_ref" ):
                listener.exitHier_ref(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHier_ref" ):
                return visitor.visitHier_ref(self)
            else:
                return visitor.visitChildren(self)




    def hier_ref(self):

        localctx = VerilogParser.Hier_refContext(self, self._ctx, self.state)
        self.enterRule(localctx, 720, self.RULE_hier_ref)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4493
            self.identifier()
            self.state = 4495
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LB:
                self.state = 4494
                self.const_bit_select()


            self.state = 4497
            self.match(VerilogParser.DT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class IdentifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def escaped_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Escaped_identifierContext,0)


        def simple_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Simple_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIdentifier" ):
                listener.enterIdentifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIdentifier" ):
                listener.exitIdentifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIdentifier" ):
                return visitor.visitIdentifier(self)
            else:
                return visitor.visitChildren(self)




    def identifier(self):

        localctx = VerilogParser.IdentifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 722, self.RULE_identifier)
        try:
            self.state = 4501
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4499
                self.escaped_identifier()
                pass
            elif token in [VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4500
                self.simple_identifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Input_port_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_input_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_port_identifier" ):
                listener.enterInput_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_port_identifier" ):
                listener.exitInput_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_port_identifier" ):
                return visitor.visitInput_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def input_port_identifier(self):

        localctx = VerilogParser.Input_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 724, self.RULE_input_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4503
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Instance_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInstance_identifier" ):
                listener.enterInstance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInstance_identifier" ):
                listener.exitInstance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInstance_identifier" ):
                return visitor.visitInstance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def instance_identifier(self):

        localctx = VerilogParser.Instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 726, self.RULE_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4505
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Library_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_library_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_identifier" ):
                listener.enterLibrary_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_identifier" ):
                listener.exitLibrary_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_identifier" ):
                return visitor.visitLibrary_identifier(self)
            else:
                return visitor.visitChildren(self)




    def library_identifier(self):

        localctx = VerilogParser.Library_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 728, self.RULE_library_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4507
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_identifier" ):
                listener.enterModule_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_identifier" ):
                listener.exitModule_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_identifier" ):
                return visitor.visitModule_identifier(self)
            else:
                return visitor.visitChildren(self)




    def module_identifier(self):

        localctx = VerilogParser.Module_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 730, self.RULE_module_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4509
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Module_instance_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instance_identifier" ):
                listener.enterModule_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instance_identifier" ):
                listener.exitModule_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instance_identifier" ):
                return visitor.visitModule_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def module_instance_identifier(self):

        localctx = VerilogParser.Module_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 732, self.RULE_module_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4511
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Net_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_identifier" ):
                listener.enterNet_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_identifier" ):
                listener.exitNet_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_identifier" ):
                return visitor.visitNet_identifier(self)
            else:
                return visitor.visitChildren(self)




    def net_identifier(self):

        localctx = VerilogParser.Net_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 734, self.RULE_net_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4513
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Output_port_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_output_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_port_identifier" ):
                listener.enterOutput_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_port_identifier" ):
                listener.exitOutput_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_port_identifier" ):
                return visitor.visitOutput_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def output_port_identifier(self):

        localctx = VerilogParser.Output_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 736, self.RULE_output_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4515
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Parameter_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_identifier" ):
                listener.enterParameter_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_identifier" ):
                listener.exitParameter_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_identifier" ):
                return visitor.visitParameter_identifier(self)
            else:
                return visitor.visitChildren(self)




    def parameter_identifier(self):

        localctx = VerilogParser.Parameter_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 738, self.RULE_parameter_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4517
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Port_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_identifier" ):
                listener.enterPort_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_identifier" ):
                listener.exitPort_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_identifier" ):
                return visitor.visitPort_identifier(self)
            else:
                return visitor.visitChildren(self)




    def port_identifier(self):

        localctx = VerilogParser.Port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 740, self.RULE_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4519
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Real_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_real_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_identifier" ):
                listener.enterReal_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_identifier" ):
                listener.exitReal_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_identifier" ):
                return visitor.visitReal_identifier(self)
            else:
                return visitor.visitChildren(self)




    def real_identifier(self):

        localctx = VerilogParser.Real_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 742, self.RULE_real_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4521
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Simple_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SIMPLE_IDENTIFIER(self):
            return self.getToken(VerilogParser.SIMPLE_IDENTIFIER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_simple_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_identifier" ):
                listener.enterSimple_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_identifier" ):
                listener.exitSimple_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_identifier" ):
                return visitor.visitSimple_identifier(self)
            else:
                return visitor.visitChildren(self)




    def simple_identifier(self):

        localctx = VerilogParser.Simple_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 744, self.RULE_simple_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4523
            self.match(VerilogParser.SIMPLE_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Specparam_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specparam_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_identifier" ):
                listener.enterSpecparam_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_identifier" ):
                listener.exitSpecparam_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_identifier" ):
                return visitor.visitSpecparam_identifier(self)
            else:
                return visitor.visitChildren(self)




    def specparam_identifier(self):

        localctx = VerilogParser.Specparam_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 746, self.RULE_specparam_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4525
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class System_function_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SYSTEM_TF_IDENTIFIER(self):
            return self.getToken(VerilogParser.SYSTEM_TF_IDENTIFIER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_system_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_function_identifier" ):
                listener.enterSystem_function_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_function_identifier" ):
                listener.exitSystem_function_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_function_identifier" ):
                return visitor.visitSystem_function_identifier(self)
            else:
                return visitor.visitChildren(self)




    def system_function_identifier(self):

        localctx = VerilogParser.System_function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 748, self.RULE_system_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4527
            self.match(VerilogParser.SYSTEM_TF_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class System_task_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SYSTEM_TF_IDENTIFIER(self):
            return self.getToken(VerilogParser.SYSTEM_TF_IDENTIFIER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_system_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_task_identifier" ):
                listener.enterSystem_task_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_task_identifier" ):
                listener.exitSystem_task_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_task_identifier" ):
                return visitor.visitSystem_task_identifier(self)
            else:
                return visitor.visitChildren(self)




    def system_task_identifier(self):

        localctx = VerilogParser.System_task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 750, self.RULE_system_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4529
            self.match(VerilogParser.SYSTEM_TF_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Task_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_identifier" ):
                listener.enterTask_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_identifier" ):
                listener.exitTask_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_identifier" ):
                return visitor.visitTask_identifier(self)
            else:
                return visitor.visitChildren(self)




    def task_identifier(self):

        localctx = VerilogParser.Task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 752, self.RULE_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4531
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Terminal_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_terminal_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTerminal_identifier" ):
                listener.enterTerminal_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTerminal_identifier" ):
                listener.exitTerminal_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTerminal_identifier" ):
                return visitor.visitTerminal_identifier(self)
            else:
                return visitor.visitChildren(self)




    def terminal_identifier(self):

        localctx = VerilogParser.Terminal_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 754, self.RULE_terminal_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4533
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Topmodule_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_topmodule_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTopmodule_identifier" ):
                listener.enterTopmodule_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTopmodule_identifier" ):
                listener.exitTopmodule_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTopmodule_identifier" ):
                return visitor.visitTopmodule_identifier(self)
            else:
                return visitor.visitChildren(self)




    def topmodule_identifier(self):

        localctx = VerilogParser.Topmodule_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 756, self.RULE_topmodule_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4535
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_identifier" ):
                listener.enterUdp_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_identifier" ):
                listener.exitUdp_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_identifier" ):
                return visitor.visitUdp_identifier(self)
            else:
                return visitor.visitChildren(self)




    def udp_identifier(self):

        localctx = VerilogParser.Udp_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 758, self.RULE_udp_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4537
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Udp_instance_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_instance_identifier" ):
                listener.enterUdp_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_instance_identifier" ):
                listener.exitUdp_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_instance_identifier" ):
                return visitor.visitUdp_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def udp_instance_identifier(self):

        localctx = VerilogParser.Udp_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 760, self.RULE_udp_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4539
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx

    class Variable_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_identifier" ):
                listener.enterVariable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_identifier" ):
                listener.exitVariable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_identifier" ):
                return visitor.visitVariable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def variable_identifier(self):

        localctx = VerilogParser.Variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 762, self.RULE_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4541
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx



    def sempred(self, localctx:RuleContext, ruleIndex:int, predIndex:int):
        if self._predicates == None:
            self._predicates = dict()
        self._predicates[193] = self.event_expression_sempred
        self._predicates[305] = self.constant_expression_sempred
        self._predicates[309] = self.expression_sempred
        self._predicates[312] = self.module_path_expression_sempred
        pred = self._predicates.get(ruleIndex, None)
        if pred is None:
            raise Exception("No predicate with index:" + str(ruleIndex))
        else:
            return pred(localctx, predIndex)

    def event_expression_sempred(self, localctx:Event_expressionContext, predIndex:int):
            if predIndex == 0:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 1:
                return self.precpred(self._ctx, 1)
         

    def constant_expression_sempred(self, localctx:Constant_expressionContext, predIndex:int):
            if predIndex == 2:
                return self.precpred(self._ctx, 12)
         

            if predIndex == 3:
                return self.precpred(self._ctx, 11)
         

            if predIndex == 4:
                return self.precpred(self._ctx, 10)
         

            if predIndex == 5:
                return self.precpred(self._ctx, 9)
         

            if predIndex == 6:
                return self.precpred(self._ctx, 8)
         

            if predIndex == 7:
                return self.precpred(self._ctx, 7)
         

            if predIndex == 8:
                return self.precpred(self._ctx, 6)
         

            if predIndex == 9:
                return self.precpred(self._ctx, 5)
         

            if predIndex == 10:
                return self.precpred(self._ctx, 4)
         

            if predIndex == 11:
                return self.precpred(self._ctx, 3)
         

            if predIndex == 12:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 13:
                return self.precpred(self._ctx, 1)
         

    def expression_sempred(self, localctx:ExpressionContext, predIndex:int):
            if predIndex == 14:
                return self.precpred(self._ctx, 12)
         

            if predIndex == 15:
                return self.precpred(self._ctx, 11)
         

            if predIndex == 16:
                return self.precpred(self._ctx, 10)
         

            if predIndex == 17:
                return self.precpred(self._ctx, 9)
         

            if predIndex == 18:
                return self.precpred(self._ctx, 8)
         

            if predIndex == 19:
                return self.precpred(self._ctx, 7)
         

            if predIndex == 20:
                return self.precpred(self._ctx, 6)
         

            if predIndex == 21:
                return self.precpred(self._ctx, 5)
         

            if predIndex == 22:
                return self.precpred(self._ctx, 4)
         

            if predIndex == 23:
                return self.precpred(self._ctx, 3)
         

            if predIndex == 24:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 25:
                return self.precpred(self._ctx, 1)
         

    def module_path_expression_sempred(self, localctx:Module_path_expressionContext, predIndex:int):
            if predIndex == 26:
                return self.precpred(self._ctx, 7)
         

            if predIndex == 27:
                return self.precpred(self._ctx, 6)
         

            if predIndex == 28:
                return self.precpred(self._ctx, 5)
         

            if predIndex == 29:
                return self.precpred(self._ctx, 4)
         

            if predIndex == 30:
                return self.precpred(self._ctx, 3)
         

            if predIndex == 31:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 32:
                return self.precpred(self._ctx, 1)
         




