// File: Logic.v
// Generated by MyHDL 0.9.0
// Date: Sun Jul 12 13:49:42 2015


`timescale 1ns/10ps

module Logic (
    flags,
    position
);


output [3:0] flags;
reg [3:0] flags;
output signed [27:0] position;
reg signed [27:0] position;

reg [31:0] conc;





initial begin: LOGIC_DOIT
    flags <= 4;
    position <= 28;
    # 10;
    conc <= {flags, position};
    # 10;
    $write("%0d", conc);
    $write("\n");
end

endmodule
