-- File: Logic.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:49 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity Logic is
    port (
        flags: inout unsigned(3 downto 0);
        position: inout signed (27 downto 0)
    );
end entity Logic;


architecture MyHDL of Logic is





signal conc: unsigned(31 downto 0);

begin





LOGIC_DOIT: process is
    variable L: line;
begin
    flags <= to_unsigned(4, 4);
    position <= to_signed(28, 28);
    wait for 10 * 1 ns;
    conc <= unsigned'(flags & unsigned(position));
    wait for 10 * 1 ns;
    write(L, to_integer(conc));
    writeline(output, L);
    wait;
end process LOGIC_DOIT;

end architecture MyHDL;
