-- File: module.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:48 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity module is
    port (
        sigin: in unsigned(1 downto 0);
        sigout: out unsigned(1 downto 0)
    );
end entity module;


architecture MyHDL of module is






begin





MODULE_OUTPUT: process (sigin) is
begin
    sigout <= sigin(2-1 downto 0);
end process MODULE_OUTPUT;

end architecture MyHDL;
