// File: bug_1740778.v
// Generated by MyHDL 0.9.0
// Date: Sun Jul 12 13:49:37 2015


`timescale 1ns/10ps

module bug_1740778 (

);
// Conversion of min and max attribute.
// 
//     


wire [6:0] s;


assign s = 0;



initial begin: BUG_1740778_LOGIC
    reg signed [7-1:0] v;
    v = 0;
    # 10;
    $write("%0d", -15);
    $write("\n");
    $write("%0d", 45);
    $write("\n");
    $write("%0d", s);
    $write("\n");
    $write("%0d", -13);
    $write("\n");
    $write("%0d", 46);
    $write("\n");
end

endmodule
