-- File: bug_43.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:48 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity bug_43 is
    port (
        sigin: in unsigned(3 downto 0);
        sigout: out unsigned(3 downto 0)
    );
end entity bug_43;


architecture MyHDL of bug_43 is






begin





BUG_43_OUTPUT: process (sigin) is
    variable tmp: unsigned(1 downto 0);
begin
    sigout <= resize(unsigned'(sigin(0) & sigin(2)), 4);
    tmp := unsigned'(sigin(0) & sigin(2));
    sigout <= resize(tmp, 4);
end process BUG_43_OUTPUT;

end architecture MyHDL;
