-- File: issue_98.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:26:44 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity issue_98 is
    port (
        sda: inout unsigned(0 downto 0);
        scl: inout unsigned(0 downto 0);
        sda_i: out unsigned(0 downto 0);
        sda_o: in unsigned(0 downto 0);
        scl_i: out unsigned(0 downto 0);
        scl_o: in unsigned(0 downto 0)
    );
end entity issue_98;


architecture MyHDL of issue_98 is





signal scl_d: unsigned(0 downto 0);
signal sda_d: unsigned(0 downto 0);

begin



scl <= scl_d;
sda <= sda_d;



sda_i <= sda;
sda_d <= to_unsigned(0, 1) when (not bool(sda_o)) else (others => 'Z');
scl_i <= scl;
scl_d <= (others => 'Z') when (not bool(scl_o)) else to_unsigned(1, 1);

end architecture MyHDL;
