// File: issue_98.v
// Generated by MyHDL 0.9.0
// Date: Sun Jul 12 13:49:44 2015


`timescale 1ns/10ps

module issue_98 (
    sda,
    scl,
    sda_i,
    sda_o,
    scl_i,
    scl_o
);


output [0:0] sda;
wire [0:0] sda;
output [0:0] scl;
wire [0:0] scl;
output [0:0] sda_i;
wire [0:0] sda_i;
input [0:0] sda_o;
output [0:0] scl_i;
wire [0:0] scl_i;
input [0:0] scl_o;

wire [0:0] scl_d;



assign scl = scl_d;




assign sda_i = sda;
assign scl_i = scl;
assign scl_d = 'bz;

endmodule
