-- File: bug_28.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:47 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity bug_28 is
    port (
        dout: out unsigned(15 downto 0);
        channel: in unsigned(3 downto 0)
    );
end entity bug_28;


architecture MyHDL of bug_28 is






begin






dout <= (32816 + shift_left(resize(channel, 16), 10));

end architecture MyHDL;
