// File: bug_43.v
// Generated by MyHDL 0.9.0
// Date: Sun Jul 12 13:49:41 2015


`timescale 1ns/10ps

module bug_43 (
    sigin,
    sigout
);


input [3:0] sigin;
output [3:0] sigout;
reg [3:0] sigout;






always @(sigin) begin: BUG_43_OUTPUT
    reg [2-1:0] tmp;
    sigout = {sigin[0], sigin[2]};
    tmp = {sigin[0], sigin[2]};
    sigout = tmp;
end

endmodule
