// File: dut.v
// Generated by MyHDL 0.9.0
// Date: Sun Jul 12 13:49:41 2015


`timescale 1ns/10ps

module dut (

);



reg [6:0] count;





initial begin: DUT_SEQ
    integer i;
    count <= 50;
    for (i=0; i<300; i=i+1) begin
        # 10;
        $write("%0d", count);
        $write("\n");
        if ((($signed({1'b0, count}) - 1) < 0)) begin
            count <= 97;
        end
        else begin
            count <= (count - 1);
        end
    end
end

endmodule
