-- File: bug_1835792.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:45 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity bug_1835792 is
end entity bug_1835792;
-- Semicolon conversion
-- 
--     

architecture MyHDL of bug_1835792 is






begin





BUG_1835792_LOGIC: process is
    variable L: line;
    variable v: signed(6 downto 0);
begin
    v := to_signed(0, 7);
    wait for 10 * 1 ns;
    write(L, -15);
    writeline(output, L);
    write(L, 45);
    writeline(output, L);
    wait;
end process BUG_1835792_LOGIC;

end architecture MyHDL;
