-- File: bug_1740778.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:44 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity bug_1740778 is
end entity bug_1740778;
-- Conversion of min and max attribute.
-- 
--     

architecture MyHDL of bug_1740778 is





signal s: signed (6 downto 0);

begin


s <= to_signed(0, 7);



BUG_1740778_LOGIC: process is
    variable L: line;
    variable v: signed(6 downto 0);
begin
    v := to_signed(0, 7);
    wait for 10 * 1 ns;
    write(L, -15);
    writeline(output, L);
    write(L, 45);
    writeline(output, L);
    write(L, to_integer(s));
    writeline(output, L);
    write(L, -13);
    writeline(output, L);
    write(L, 46);
    writeline(output, L);
    wait;
end process BUG_1740778_LOGIC;

end architecture MyHDL;
