-- File: issue_18.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:50 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity issue_18 is
    port (
        dout: out std_logic_vector(7 downto 0);
        din: in std_logic_vector(7 downto 0);
        addr: in std_logic_vector(6 downto 0);
        we: in std_logic;
        clk: in std_logic
    );
end entity issue_18;
-- Ram model 

architecture MyHDL of issue_18 is





signal dout_num: unsigned(7 downto 0);
signal din_num: unsigned(7 downto 0);
signal addr_num: unsigned(6 downto 0);
type t_array_mem is array(0 to 128-1) of unsigned(7 downto 0);
signal mem: t_array_mem;

begin

dout <= std_logic_vector(dout_num);
din_num <= unsigned(din);
addr_num <= unsigned(addr);




ISSUE_18_WRITE: process (clk) is
begin
    if rising_edge(clk) then
        if bool(we) then
            mem(to_integer(addr_num)) <= din_num;
        end if;
    end if;
end process ISSUE_18_WRITE;



dout_num <= mem(to_integer(addr_num));

end architecture MyHDL;
