-- File: issue_98_2.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:50 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity issue_98_2 is
    port (
        sda: inout unsigned(1 downto 0);
        scl: inout unsigned(1 downto 0);
        sda_i: out unsigned(1 downto 0);
        sda_o: in unsigned(1 downto 0);
        scl_i: out unsigned(1 downto 0);
        scl_o: in unsigned(1 downto 0)
    );
end entity issue_98_2;


architecture MyHDL of issue_98_2 is





signal scl_d: unsigned(1 downto 0);

begin



scl <= scl_d;




sda_i <= sda;
scl_i <= scl;
scl_d <= (others => 'Z');

end architecture MyHDL;
