-- File: bug_boolconst.vhd
-- Generated by MyHDL 0.9.0
-- Date: Sun Jul 12 13:49:49 2015


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_090.all;

entity bug_boolconst is
    port (
        sigin: in std_logic;
        sigout: out std_logic
    );
end entity bug_boolconst;


architecture MyHDL of bug_boolconst is


constant BOOL_CONDITION_1: integer := 1;
constant BOOL_CONDITION_0: integer := 0;
constant INT_CONDITION_1: integer := 1;
constant INT_CONDITION_0: integer := 0;




begin





BUG_BOOLCONST_OUTPUT: process (sigin) is
begin
    sigout <= '0';
    if bool(INT_CONDITION_0) then
        sigout <= sigin;
    end if;
    if bool(BOOL_CONDITION_0) then
        sigout <= sigin;
    end if;
    if (not bool(INT_CONDITION_0)) then
        sigout <= sigin;
    end if;
    if (not bool(BOOL_CONDITION_0)) then
        sigout <= sigin;
    end if;
    if bool(INT_CONDITION_1) then
        sigout <= sigin;
    end if;
    if bool(BOOL_CONDITION_1) then
        sigout <= sigin;
    end if;
    if (not bool(INT_CONDITION_1)) then
        sigout <= sigin;
    end if;
    if (not bool(BOOL_CONDITION_1)) then
        sigout <= sigin;
    end if;
end process BUG_BOOLCONST_OUTPUT;

end architecture MyHDL;
