// File: test_bench.v
// Generated by MyHDL 0.10
// Date: Tue May  8 20:56:26 2018


`timescale 1ns/10ps

module test_bench (

);



reg Test11_test0_self_clock;
reg Test21_test0_self_clock;



initial begin: TEST_BENCH_TEST11_TEST0_FUNC
    integer i;
    i = 0;
    while ((i <= 100)) begin
        # 10;
        Test11_test0_self_clock <= (!Test11_test0_self_clock);
        i = (i + 1);
    end
end


initial begin: TEST_BENCH_TEST21_TEST0_FUNC
    integer i;
    i = 0;
    while ((i <= 100)) begin
        # 10;
        Test21_test0_self_clock <= (!Test21_test0_self_clock);
        i = (i + 1);
    end
end

endmodule
