// File: issue_117_2.v
// Generated by MyHDL 0.10
// Date: Tue May  8 20:56:17 2018


`timescale 1ns/10ps

module issue_117_2 (
    clk,
    sdi,
    pdo,
    sel
);


input clk;
input sdi;
output [7:0] pdo;
reg [7:0] pdo;
input [1:0] sel;

reg [7:0] delay_reg;



always @(posedge clk) begin: ISSUE_117_2_RTL
    case (sel)
        'h0: begin
            delay_reg <= {1'b0, delay_reg[((8 - 1) - 1)-1:1], sdi};
        end
        'h1: begin
            delay_reg <= {delay_reg[(8 - 1)-1:(1 + 1)], 1'b0, sdi};
        end
        'h2: begin
            delay_reg <= {delay_reg[(8 - 1)-1:(1 + 1)], sdi, 1'b0};
            pdo <= delay_reg;
        end
    endcase
end

endmodule
