// File: bench_converts.v
// Generated by MyHDL 0.10
// Date: Tue May  8 20:56:27 2018


`timescale 1ns/10ps

module bench_converts (

);



reg [7:0] y;
reg [7:0] x;
reg reset;
reg clock;



always @(posedge clock, negedge reset) begin: BENCH_CONVERTS_CASE20_BEH_DECODE
    if (reset == 0) begin
        y <= 0;
    end
    else begin
        case (x)
            'h1: begin
                y <= 4;
            end
            'h2: begin
                y <= 1;
            end
            'h3: begin
                y <= 2;
            end
            (-'h1): begin
                y <= 3;
            end
            default: begin
                y <= 0;
            end
        endcase
    end
end


initial begin: BENCH_CONVERTS_TBCLK
    clock <= 0;
    while (1'b1) begin
        # 5;
        clock <= (!clock);
    end
end


initial begin: BENCH_CONVERTS_TBSTIM
    integer ii;
    reset <= 1'b0;
    # 10;
    reset <= (!1'b0);
    @(posedge clock);
    for (ii=0; ii<18; ii=ii+1) begin
        case (ii)
            0: x <= 1;
            1: x <= 2;
            2: x <= 3;
            3: x <= 4;
            4: x <= 11;
            5: x <= 9;
            6: x <= 10;
            7: x <= 7;
            8: x <= 2;
            9: x <= 7;
            10: x <= 9;
            11: x <= 2;
            12: x <= 5;
            13: x <= 2;
            14: x <= 0;
            15: x <= 4;
            16: x <= 11;
            default: x <= 2;
        endcase
        @(posedge clock);
        $write("x: ");
        $write("%0d", x);
        $write(",  y: ");
        $write("%0d", y);
        $write("\n");
    end
    $finish;
end

endmodule
