// File: issue_134.v
// Generated by MyHDL 0.10
// Date: Tue May  8 20:56:21 2018


`timescale 1ns/10ps

module issue_134 (
    inverta_sigin,
    invertb_sigin,
    inverta_sigout,
    invertb_sigout
);
// Instantiate an inverter for each signal 

input inverta_sigin;
input invertb_sigin;
output inverta_sigout;
wire inverta_sigout;
output invertb_sigout;
wire invertb_sigout;





assign inverta_sigout = (!inverta_sigin);



assign invertb_sigout = (!invertb_sigin);

endmodule
