// File: bug_1740778.v
// Generated by MyHDL 0.10
// Date: Tue May  8 20:56:14 2018


`timescale 1ns/10ps

module bug_1740778 (

);
// Conversion of min and max attribute.
// 
//     


wire [6:0] s;

assign s = 7'd0;


initial begin: BUG_1740778_LOGIC
    reg signed [7-1:0] v;
    v = 0;
    # 10;
    $write("%0d", -15);
    $write("\n");
    $write("%0d", 45);
    $write("\n");
    $write("%h", s);
    $write("\n");
    $write("%0d", -13);
    $write("\n");
    $write("%0d", 46);
    $write("\n");
end

endmodule
