// File: Logic.v
// Generated by MyHDL 0.10
// Date: Tue May  8 20:56:16 2018


`timescale 1ns/10ps

module Logic (
    flags,
    position
);


output [3:0] flags;
reg [3:0] flags;
output signed [27:0] position;
reg signed [27:0] position;

reg [31:0] conc;



initial begin: LOGIC_DOIT
    flags <= 4;
    position <= 28;
    # 10;
    conc <= {flags, position};
    # 10;
    $write("%h", conc);
    $write("\n");
end

endmodule
