// File: issue_98_3.v
// Generated by MyHDL 0.10
// Date: Tue May  8 20:56:27 2018


`timescale 1ns/10ps

module issue_98_3 (
    sda,
    scl,
    sda_i,
    sda_o,
    scl_i,
    scl_o
);


inout [0:0] sda;
wire [0:0] sda;
inout [0:0] scl;
wire [0:0] scl;
output [0:0] sda_i;
wire [0:0] sda_i;
input [0:0] sda_o;
output [0:0] scl_i;
wire [0:0] scl_i;
input [0:0] scl_o;

wire [0:0] sda_d;
wire [0:0] scl_d;

assign sda = sda_d;
assign scl = scl_d;



assign sda_i = sda;
assign sda_d = (!sda_o) ? 0 : 'bz;
assign scl_i = scl;
assign scl_d = (!scl_o) ? 'bz : 1;

endmodule
