-- File: bug_3529686.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:40 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity bug_3529686 is
    port (
        clr: in std_logic;
        clk: in std_logic;
        run: in std_logic;
        ack: in std_logic;
        serialout: out std_logic
    );
end entity bug_3529686;


architecture MyHDL of bug_3529686 is




begin




BUG_3529686_FSM: process (clk, clr) is
begin
    if (clr = '0') then
        serialout <= '0';
    elsif rising_edge(clk) or rising_edge(clr) then
        if (ack = '0') then
            serialout <= '0';
        elsif (run = '1') then
            serialout <= '1';
        end if;
    end if;
end process BUG_3529686_FSM;

end architecture MyHDL;
