// File: issue_133.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:45 2023


`timescale 1ns/10ps

module issue_133 (

);



wire [255:0] large_signal;
reg z;

assign large_signal = 256'd123456789123456;


initial begin: ISSUE_133_CHECK
    z <= large_signal[10];
    # 10;
    $write("%h", large_signal[31-1:0]);
    $write("\n");
    $write("%h", large_signal[62-1:31]);
    $write("\n");
    $write("%h", large_signal[93-1:62]);
    $write("\n");
end

endmodule
