-- File: issue_13.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:30 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity issue_13 is
    port (
        reset: in std_logic;
        clk: in std_logic;
        d: in unsigned(31 downto 0);
        en: in std_logic;
        q: out unsigned(7 downto 0)
    );
end entity issue_13;


architecture MyHDL of issue_13 is




function MYHDL97_calculateHec(
    header: in unsigned
    ) return integer is
    variable hec: unsigned(7 downto 0);
    variable bit: std_logic;
begin
    hec := to_unsigned(0, 8);
    for ii in 32-1 downto 0 loop
        bit := header(ii);
        hec(8-1 downto 0) := unsigned'(hec(7-1 downto 2) & ((bit xor hec(1)) xor hec(7)) & ((bit xor hec(0)) xor hec(7)) & (bit xor hec(7)));
    end loop;
    return (hec xor to_unsigned(85, 8));
end function MYHDL97_calculateHec;

begin




ISSUE_13_LOGIC: process (clk) is
begin
    if rising_edge(clk) then
        if (reset = '1') then
            q <= to_unsigned(0, 8);
        else
            if bool(en) then
                q <= to_unsigned(MYHDL97_calculateHec(d), 8);
            end if;
        end if;
    end if;
end process ISSUE_13_LOGIC;

end architecture MyHDL;
