-- File: issue_117_1.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:25 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity issue_117_1 is
    port (
        clk: in std_logic;
        sdi: in std_logic;
        pdo: out unsigned(7 downto 0);
        sel: in unsigned(1 downto 0)
    );
end entity issue_117_1;


architecture MyHDL of issue_117_1 is



signal delay_reg: unsigned(7 downto 0);

begin




ISSUE_117_1_RTL: process (clk) is
begin
    if rising_edge(clk) then
        case sel is
            when "00" =>
                delay_reg <= resize(unsigned'('0' & delay_reg(((8 - 1) - 1)-1 downto 1) & sdi), 8);
            when "01" =>
                delay_reg <= resize(unsigned'(delay_reg((8 - 1)-1 downto (1 + 1)) & '0' & sdi), 8);
            when others => -- "10"
                delay_reg <= resize(unsigned'(delay_reg((8 - 1)-1 downto (1 + 1)) & sdi & '0'), 8);
                pdo <= delay_reg;
        end case;
    end if;
end process ISSUE_117_1_RTL;

end architecture MyHDL;
