// File: issue_134.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:45 2023


`timescale 1ns/10ps

module issue_134 (
    ab_in_a,
    ab_in_b,
    ab_out_a,
    ab_out_b
);
// Instantiate an inverter for each signal 

input ab_in_a;
input ab_in_b;
output ab_out_a;
wire ab_out_a;
output ab_out_b;
wire ab_out_b;





assign ab_out_a = (!ab_in_a);



assign ab_out_b = (!ab_in_b);

endmodule
