// File: issue_13.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:45 2023


`timescale 1ns/10ps

module issue_13 (
    reset,
    clk,
    d,
    en,
    q
);


input reset;
input clk;
input [31:0] d;
input en;
output [7:0] q;
reg [7:0] q;



function integer MYHDL97_calculateHec;
    input [32-1:0] header;
    reg [8-1:0] hec;
    integer ii;
    reg bit;
begin: MYHDL100_RETURN
    hec = 8'h0;
    for (ii=32-1; ii>=0; ii=ii-1) begin
        bit = header[ii];
        hec[8-1:0] = {hec[7-1:2], ((bit ^ hec[1]) ^ hec[7]), ((bit ^ hec[0]) ^ hec[7]), (bit ^ hec[7])};
    end
    MYHDL97_calculateHec = (hec ^ 85);
    disable MYHDL100_RETURN;
end
endfunction


always @(posedge clk) begin: ISSUE_13_LOGIC
    if (reset == 1) begin
        q <= 0;
    end
    else begin
        if (en) begin
            q <= MYHDL97_calculateHec(d);
        end
    end
end

endmodule
