// File: bug_boolconst.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:40 2023


`timescale 1ns/10ps

module bug_boolconst (
    sigin,
    sigout
);


input sigin;
output sigout;
reg sigout;




always @(sigin) begin: BUG_BOOLCONST_OUTPUT
    sigout = 0;
    if (0) begin
        sigout = sigin;
    end
    if (1'b0) begin
        sigout = sigin;
    end
    if ((!0)) begin
        sigout = sigin;
    end
    if ((!1'b0)) begin
        sigout = sigin;
    end
    if (1) begin
        sigout = sigin;
    end
    if (1'b1) begin
        sigout = sigin;
    end
    if ((!1)) begin
        sigout = sigin;
    end
    if ((!1'b1)) begin
        sigout = sigin;
    end
end

endmodule
