-- File: bug_boolconst.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:25 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity bug_boolconst is
    port (
        sigin: in std_logic;
        sigout: out std_logic
    );
end entity bug_boolconst;


architecture MyHDL of bug_boolconst is




begin




BUG_BOOLCONST_OUTPUT: process (sigin) is
begin
    sigout <= '0';
    if False then
        sigout <= sigin;
    end if;
    if False then
        sigout <= sigin;
    end if;
    if (not False) then
        sigout <= sigin;
    end if;
    if (not False) then
        sigout <= sigin;
    end if;
    if True then
        sigout <= sigin;
    end if;
    if True then
        sigout <= sigin;
    end if;
    if (not True) then
        sigout <= sigin;
    end if;
    if (not True) then
        sigout <= sigin;
    end if;
end process BUG_BOOLCONST_OUTPUT;

end architecture MyHDL;
