// File: bug_3577799.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:40 2023


`timescale 1ns/10ps

module bug_3577799 (
    clk,
    reset_clk,
    wr_data,
    wr,
    rd_data
);


input clk;
input reset_clk;
input [15:0] wr_data;
input wr;
output [15:0] rd_data;
reg [15:0] rd_data;




always @(posedge clk) begin: BUG_3577799_SEQ
    integer count;
    if (reset_clk) begin
        count = 0;
    end
    else begin
        if (wr) begin
            if ((count < 8)) begin
                rd_data <= wr_data;
                count = (count + 1);
            end
        end
    end
end

endmodule
