-- File: bug_1835797.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:23 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity bug_1835797 is
end entity bug_1835797;
-- Docstring in the middle.
-- 
--     

architecture MyHDL of bug_1835797 is




begin




BUG_1835797_LOGIC: process is
    variable L: line;
    variable v: signed(6 downto 0);
begin
    v := to_signed(0, 7);
    -- Wrongly placed docstring
    wait for 10 * 1 ns;
    write(L, to_string(-15));
    writeline(output, L);
    write(L, to_string(45));
    writeline(output, L);
    wait;
end process BUG_1835797_LOGIC;

end architecture MyHDL;
