-- File: module_42.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:40 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity module_42 is
    port (
        sigin: in unsigned(1 downto 0);
        sigout: out unsigned(1 downto 0)
    );
end entity module_42;


architecture MyHDL of module_42 is




begin





sigout <= sigin(2-1 downto 0);

end architecture MyHDL;
