-- File: mpegChannel.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:36 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity mpegChannel is
    port (
        clk: in std_logic;
        rst: in std_logic
    );
end entity mpegChannel;


architecture MyHDL of mpegChannel is



signal s_tx_data_xor_mask_r: unsigned(31 downto 0);

begin




MPEGCHANNEL_FSM_SEQ: process (clk, rst) is
begin
    if (rst = '1') then
        s_tx_data_xor_mask_r <= to_unsigned(0, 32);
    elsif rising_edge(clk) then
        for i in 0 to 4-1 loop
            case i is
                when 0 =>
                    s_tx_data_xor_mask_r((1 + 7)-1 downto 0) <= to_unsigned(0, 8);
                when 1 =>
                    s_tx_data_xor_mask_r((1 + 15)-1 downto 8) <= to_unsigned(1, 8);
                when 2 =>
                    s_tx_data_xor_mask_r((1 + 23)-1 downto 16) <= to_unsigned(2, 8);
                when others =>
                    s_tx_data_xor_mask_r((1 + 31)-1 downto 24) <= to_unsigned(3, 8);
            end case;
        end loop;
    end if;
end process MPEGCHANNEL_FSM_SEQ;

end architecture MyHDL;
