// File: mytest_bench.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:51 2023


`timescale 1ns/10ps

module mytest_bench (

);



reg MyTest10_test0_self_clock;
reg MyTest20_test0_self_clock;



initial begin: MYTEST_BENCH_MYTEST10_TEST0_FUNC
    integer i;
    i = 0;
    while ((i <= 100)) begin
        # 10;
        MyTest10_test0_self_clock <= (!MyTest10_test0_self_clock);
        i = (i + 1);
    end
end


initial begin: MYTEST_BENCH_MYTEST20_TEST0_FUNC
    integer i;
    i = 0;
    while ((i <= 100)) begin
        # 10;
        MyTest20_test0_self_clock <= (!MyTest20_test0_self_clock);
        i = (i + 1);
    end
end

endmodule
