-- File: issue_134.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:30 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity issue_134 is
    port (
        ab_in_a: in std_logic;
        ab_in_b: in std_logic;
        ab_out_a: out std_logic;
        ab_out_b: out std_logic
    );
end entity issue_134;
-- Instantiate an inverter for each signal 

architecture MyHDL of issue_134 is




begin





ab_out_a <= stdl((not bool(ab_in_a)));


ab_out_b <= stdl((not bool(ab_in_b)));

end architecture MyHDL;
