// File: dut.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:40 2023


`timescale 1ns/10ps

module dut (

);



reg [6:0] count;



initial begin: DUT_SEQ
    integer dummy;
    count <= 50;
    for (dummy=0; dummy<300; dummy=dummy+1) begin
        # 10;
        $write("%h", count);
        $write("\n");
        if ((($signed({1'b0, count}) - 1) < 0)) begin
            count <= 97;
        end
        else begin
            count <= (count - 1);
        end
    end
end

endmodule
