-- File: mytest_bench.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:36 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity mytest_bench is
end entity mytest_bench;


architecture MyHDL of mytest_bench is



signal MyTest10_test0_self_clock: std_logic;
signal MyTest20_test0_self_clock: std_logic;

begin




MYTEST_BENCH_MYTEST10_TEST0_FUNC: process is
    variable i: integer;
begin
    i := 0;
    while (i <= 100) loop
        wait for 10 * 1 ns;
        MyTest10_test0_self_clock <= stdl((not bool(MyTest10_test0_self_clock)));
        i := (i + 1);
    end loop;
    wait;
end process MYTEST_BENCH_MYTEST10_TEST0_FUNC;

MYTEST_BENCH_MYTEST20_TEST0_FUNC: process is
    variable i: integer;
begin
    i := 0;
    while (i <= 100) loop
        wait for 10 * 1 ns;
        MyTest20_test0_self_clock <= stdl((not bool(MyTest20_test0_self_clock)));
        i := (i + 1);
    end loop;
    wait;
end process MYTEST_BENCH_MYTEST20_TEST0_FUNC;

end architecture MyHDL;
