// File: mpegChannel.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:51 2023


`timescale 1ns/10ps

module mpegChannel (
    clk,
    rst
);


input clk;
input rst;

reg [31:0] s_tx_data_xor_mask_r;



always @(posedge clk, posedge rst) begin: MPEGCHANNEL_FSM_SEQ
    integer i;
    if (rst == 1) begin
        s_tx_data_xor_mask_r <= 0;
    end
    else begin
        for (i=0; i<4; i=i+1) begin
            case (i)
                'h0: begin
                    s_tx_data_xor_mask_r[(1 + 7)-1:0] <= 0;
                end
                'h1: begin
                    s_tx_data_xor_mask_r[(1 + 15)-1:8] <= 1;
                end
                'h2: begin
                    s_tx_data_xor_mask_r[(1 + 23)-1:16] <= 2;
                end
                default: begin
                    s_tx_data_xor_mask_r[(1 + 31)-1:24] <= 3;
                end
            endcase
        end
    end
end

endmodule
