-- File: issue_98_3.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:36 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity issue_98_3 is
    port (
        sda: inout unsigned(0 downto 0);
        scl: inout unsigned(0 downto 0);
        sda_i: out unsigned(0 downto 0);
        sda_o: in unsigned(0 downto 0);
        scl_i: out unsigned(0 downto 0);
        scl_o: in unsigned(0 downto 0)
    );
end entity issue_98_3;


architecture MyHDL of issue_98_3 is



signal scl_d: unsigned(0 downto 0);
signal sda_d: unsigned(0 downto 0);

begin



sda <= sda_d;
scl <= scl_d;


sda_i <= sda;
sda_d <= tern_op(cond => (not bool(sda_o)), if_true => to_unsigned(0, 1), if_false => "Z");
scl_i <= scl;
scl_d <= tern_op(cond => (not bool(scl_o)), if_true => "Z", if_false => to_unsigned(1, 1));

end architecture MyHDL;
