-- File: dut.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:24 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity dut is
end entity dut;


architecture MyHDL of dut is



signal count: unsigned(6 downto 0);

begin




DUT_SEQ: process is
    variable L: line;
begin
    count <= to_unsigned(50, 7);
    for dummy in 0 to 300-1 loop
        wait for 10 * 1 ns;
        write(L, to_hstring(count));
        writeline(output, L);
        if ((signed(resize(count, 8)) - 1) < 0) then
            count <= to_unsigned(97, 7);
        else
            count <= (count - 1);
        end if;
    end loop;
    wait;
end process DUT_SEQ;

end architecture MyHDL;
