-- File: issue_133.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:30 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity issue_133 is
end entity issue_133;


architecture MyHDL of issue_133 is



signal large_signal: unsigned(255 downto 0);
signal z: std_logic;

begin


large_signal <= unsigned'("0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011100000100100010000110000011111001000110000000");


ISSUE_133_CHECK: process is
    variable L: line;
begin
    z <= large_signal(10);
    wait for 10 * 1 ns;
    write(L, to_hstring(large_signal(31-1 downto 0)));
    writeline(output, L);
    write(L, to_hstring(large_signal(62-1 downto 31)));
    writeline(output, L);
    write(L, to_hstring(large_signal(93-1 downto 62)));
    writeline(output, L);
    wait;
end process ISSUE_133_CHECK;

end architecture MyHDL;
