-- File: pcie_legacyint_next_state_logic_2.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:25 2023



package pck_pcie_legacyint_next_state_logic_2 is

attribute enum_encoding: string;

type t_enum_t_state_1 is (
	WAIT_POSEDGE,
	WAIT_NEGEDGE
	);
attribute enum_encoding of t_enum_t_state_1: type is "01 10";

end package pck_pcie_legacyint_next_state_logic_2;

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

use work.pck_pcie_legacyint_next_state_logic_2.all;

entity pcie_legacyint_next_state_logic_2 is
    port (
        state_i: in t_enum_t_state_1;
        next_state_o: out t_enum_t_state_1;
        next_state_en_o: out std_logic;
        interrupt_pending_i: in std_logic;
        interrupt_assert_o: out std_logic
    );
end entity pcie_legacyint_next_state_logic_2;


architecture MyHDL of pcie_legacyint_next_state_logic_2 is




begin




PCIE_LEGACYINT_NEXT_STATE_LOGIC_2_SM_OUTPUT: process (state_i, interrupt_pending_i) is
begin
    case state_i is
        when WAIT_POSEDGE =>
            interrupt_assert_o <= '0';
            next_state_en_o <= interrupt_pending_i;
            next_state_o <= WAIT_NEGEDGE;
        when WAIT_NEGEDGE =>
            interrupt_assert_o <= '1';
            next_state_en_o <= stdl((not bool(interrupt_pending_i)));
            next_state_o <= WAIT_POSEDGE;
        when others =>
            interrupt_assert_o <= '0';
            next_state_en_o <= '1';
            next_state_o <= WAIT_POSEDGE;
    end case;
end process PCIE_LEGACYINT_NEXT_STATE_LOGIC_2_SM_OUTPUT;

end architecture MyHDL;
