-- File: issue_98_1.vhd
-- Generated by MyHDL 0.11.42
-- Date: Sun Jun 18 18:40:36 2023


library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;
use std.textio.all;

use work.pck_myhdl_01142.all;

entity issue_98_1 is
    port (
        sda: inout std_logic;
        scl: inout std_logic;
        sda_i: out std_logic;
        sda_o: in std_logic;
        scl_i: out std_logic;
        scl_o: in std_logic
    );
end entity issue_98_1;


architecture MyHDL of issue_98_1 is



signal scl_d: std_logic;
signal sda_d: std_logic;

begin



sda <= sda_d;
scl <= scl_d;


sda_i <= sda;
sda_d <= tern_op(cond => (not bool(sda_o)), if_true => '0', if_false => 'Z');
scl_i <= scl;
scl_d <= tern_op(cond => (not bool(scl_o)), if_true => 'Z', if_false => '1');

end architecture MyHDL;
