// File: issue_98_1.v
// Generated by MyHDL 0.11.42
// Date: Sun Jun 18 18:40:52 2023


`timescale 1ns/10ps

module issue_98_1 (
    sda,
    scl,
    sda_i,
    sda_o,
    scl_i,
    scl_o
);


inout sda;
wire sda;
inout scl;
wire scl;
output sda_i;
wire sda_i;
input sda_o;
output scl_i;
wire scl_i;
input scl_o;

wire scl_d;
wire sda_d;

assign sda = sda_d;
assign scl = scl_d;



assign sda_i = sda;
assign sda_d = (!sda_o) ? 0 : 'bz;
assign scl_i = scl;
assign scl_d = (!scl_o) ? 'bz : 1;

endmodule
