myhdl_lib
===========

.. image:: https://travis-ci.org/nkavaldj/myhdl_lib.svg?branch=master
  :target: https://travis-ci.org/nkavaldj/myhdl_lib

A MyHDL library of generic design components, e.g. memory, fifo, multiplexor, de-multiplexor, arbiter, etc. All components are tested with Icarus Verilog simulator.

Work in progres ...

Documentation (WiP) is available at: https://github.com/nkavaldj/myhdl_lib/wiki

