# This Source Code Form is subject to the terms of the Mozilla Public
# License, v. 2.0.  If a copy of the MPL was not distributed with this
# file, You can obtain one at http://mozilla.org/MPL/2.0/.
#
# Copyright 1997 - July 2008 CWI, August 2008 - 2016 MonetDB B.V.

# This file was generated by using the script 01_calc.mal.sh.

module calc;

pattern iszero(v:bte) :bit
address CMDvarISZERO
comment "Unary check for zero of V";

pattern iszero(v:sht) :bit
address CMDvarISZERO
comment "Unary check for zero of V";

pattern iszero(v:int) :bit
address CMDvarISZERO
comment "Unary check for zero of V";

pattern iszero(v:lng) :bit
address CMDvarISZERO
comment "Unary check for zero of V";

pattern iszero(v:flt) :bit
address CMDvarISZERO
comment "Unary check for zero of V";

pattern iszero(v:dbl) :bit
address CMDvarISZERO
comment "Unary check for zero of V";


pattern isnil(v:any) :bit
address CMDvarISNIL
comment "Unary check for nil of V";


pattern isnotnil(v:any) :bit
address CMDvarISNOTNIL
comment "Unary check for notnil of V";


pattern not(v:bit) :bit
address CMDvarNOT
comment "Return the Boolean inverse";

pattern not(v:bte) :bte
address CMDvarNOT
comment "Unary bitwise not of V";

pattern not(v:sht) :sht
address CMDvarNOT
comment "Unary bitwise not of V";

pattern not(v:int) :int
address CMDvarNOT
comment "Unary bitwise not of V";

pattern not(v:lng) :lng
address CMDvarNOT
comment "Unary bitwise not of V";


pattern sign(v:bte) :bte
address CMDvarSIGN
comment "Unary sign (-1,0,1) of V";

pattern sign(v:sht) :bte
address CMDvarSIGN
comment "Unary sign (-1,0,1) of V";

pattern sign(v:int) :bte
address CMDvarSIGN
comment "Unary sign (-1,0,1) of V";

pattern sign(v:lng) :bte
address CMDvarSIGN
comment "Unary sign (-1,0,1) of V";

pattern sign(v:flt) :bte
address CMDvarSIGN
comment "Unary sign (-1,0,1) of V";

pattern sign(v:dbl) :bte
address CMDvarSIGN
comment "Unary sign (-1,0,1) of V";


pattern abs(v:bte) :bte
address CMDvarABS
comment "Unary absolute value of V";

pattern abs(v:sht) :sht
address CMDvarABS
comment "Unary absolute value of V";

pattern abs(v:int) :int
address CMDvarABS
comment "Unary absolute value of V";

pattern abs(v:lng) :lng
address CMDvarABS
comment "Unary absolute value of V";

pattern abs(v:flt) :flt
address CMDvarABS
comment "Unary absolute value of V";

pattern abs(v:dbl) :dbl
address CMDvarABS
comment "Unary absolute value of V";


pattern -(v:bte) :bte
address CMDvarNEG
comment "Unary negation of V";

pattern -(v:sht) :sht
address CMDvarNEG
comment "Unary negation of V";

pattern -(v:int) :int
address CMDvarNEG
comment "Unary negation of V";

pattern -(v:lng) :lng
address CMDvarNEG
comment "Unary negation of V";

pattern -(v:flt) :flt
address CMDvarNEG
comment "Unary negation of V";

pattern -(v:dbl) :dbl
address CMDvarNEG
comment "Unary negation of V";


pattern ++(v:bte) :bte
address CMDvarINCRsignal
comment "Unary V + 1";

pattern ++(v:sht) :sht
address CMDvarINCRsignal
comment "Unary V + 1";

pattern ++(v:int) :int
address CMDvarINCRsignal
comment "Unary V + 1";

pattern ++(v:lng) :lng
address CMDvarINCRsignal
comment "Unary V + 1";

pattern ++(v:flt) :flt
address CMDvarINCRsignal
comment "Unary V + 1";

pattern ++(v:dbl) :dbl
address CMDvarINCRsignal
comment "Unary V + 1";


pattern --(v:bte) :bte
address CMDvarDECRsignal
comment "Unary V - 1";

pattern --(v:sht) :sht
address CMDvarDECRsignal
comment "Unary V - 1";

pattern --(v:int) :int
address CMDvarDECRsignal
comment "Unary V - 1";

pattern --(v:lng) :lng
address CMDvarDECRsignal
comment "Unary V - 1";

pattern --(v:flt) :flt
address CMDvarDECRsignal
comment "Unary V - 1";

pattern --(v:dbl) :dbl
address CMDvarDECRsignal
comment "Unary V - 1";


pattern +(v1:bte,v2:bte) :sht
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:bte,v2:sht) :int
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:bte,v2:int) :lng
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:bte,v2:flt) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:sht,v2:bte) :int
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:sht,v2:sht) :int
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:sht,v2:int) :lng
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:sht,v2:flt) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:int,v2:bte) :lng
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:int,v2:sht) :lng
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:int,v2:int) :lng
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:int,v2:flt) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:lng,v2:flt) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:flt,v2:bte) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:flt,v2:sht) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:flt,v2:int) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:flt,v2:lng) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";

pattern +(v1:flt,v2:flt) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, guarantee no overflow by returning larger type";


pattern -(v1:bte,v2:bte) :sht
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:bte,v2:sht) :int
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:bte,v2:int) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:bte,v2:flt) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:sht,v2:bte) :int
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:sht,v2:sht) :int
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:sht,v2:int) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:sht,v2:flt) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:int,v2:bte) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:int,v2:sht) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:int,v2:int) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:int,v2:flt) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:lng,v2:flt) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:flt,v2:bte) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:flt,v2:sht) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:flt,v2:int) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:flt,v2:lng) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";

pattern -(v1:flt,v2:flt) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, guarantee no overflow by returning larger type";


pattern *(v1:bte,v2:bte) :sht
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:bte,v2:sht) :int
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:bte,v2:int) :lng
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:bte,v2:flt) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:sht,v2:bte) :int
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:sht,v2:sht) :int
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:sht,v2:int) :lng
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:sht,v2:flt) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:int,v2:bte) :lng
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:int,v2:sht) :lng
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:int,v2:int) :lng
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:int,v2:flt) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:lng,v2:flt) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:flt,v2:bte) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:flt,v2:sht) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:flt,v2:int) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:flt,v2:lng) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";

pattern *(v1:flt,v2:flt) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, guarantee no overflow by returning larger type";


pattern +(v1:bte,v2:bte) :bte
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:bte,v2:bte) :bte
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:bte,v2:sht) :sht
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:bte,v2:sht) :sht
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:bte,v2:int) :int
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:bte,v2:int) :int
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:bte,v2:lng) :lng
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:bte,v2:lng) :lng
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:bte,v2:flt) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:bte,v2:flt) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:bte,v2:dbl) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:bte,v2:dbl) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:sht,v2:bte) :sht
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:sht,v2:bte) :sht
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:sht,v2:sht) :sht
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:sht,v2:sht) :sht
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:sht,v2:int) :int
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:sht,v2:int) :int
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:sht,v2:lng) :lng
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:sht,v2:lng) :lng
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:sht,v2:flt) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:sht,v2:flt) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:sht,v2:dbl) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:sht,v2:dbl) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:int,v2:bte) :int
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:int,v2:bte) :int
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:int,v2:sht) :int
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:int,v2:sht) :int
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:int,v2:int) :int
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:int,v2:int) :int
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:int,v2:lng) :lng
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:int,v2:lng) :lng
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:int,v2:flt) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:int,v2:flt) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:int,v2:dbl) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:int,v2:dbl) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:lng,v2:bte) :lng
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:lng,v2:bte) :lng
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:lng,v2:sht) :lng
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:lng,v2:sht) :lng
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:lng,v2:int) :lng
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:lng,v2:int) :lng
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:lng,v2:lng) :lng
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:lng,v2:lng) :lng
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:lng,v2:flt) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:lng,v2:flt) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:lng,v2:dbl) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:lng,v2:dbl) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:flt,v2:bte) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:flt,v2:bte) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:flt,v2:sht) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:flt,v2:sht) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:flt,v2:int) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:flt,v2:int) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:flt,v2:lng) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:flt,v2:lng) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:flt,v2:flt) :flt
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:flt,v2:flt) :flt
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:flt,v2:dbl) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:flt,v2:dbl) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:dbl,v2:bte) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:dbl,v2:bte) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:dbl,v2:sht) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:dbl,v2:sht) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:dbl,v2:int) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:dbl,v2:int) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:dbl,v2:lng) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:dbl,v2:lng) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:dbl,v2:flt) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:dbl,v2:flt) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";

pattern +(v1:dbl,v2:dbl) :dbl
address CMDvarADDsignal
comment "Return V1 + V2, signal error on overflow";
pattern add_noerror(v1:dbl,v2:dbl) :dbl
address CMDvarADD
comment "Return V1 + V2, overflow causes NIL value";


pattern -(v1:bte,v2:bte) :bte
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:bte,v2:bte) :bte
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:bte,v2:sht) :sht
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:bte,v2:sht) :sht
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:bte,v2:int) :int
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:bte,v2:int) :int
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:bte,v2:lng) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:bte,v2:lng) :lng
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:bte,v2:flt) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:bte,v2:flt) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:bte,v2:dbl) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:bte,v2:dbl) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:sht,v2:bte) :sht
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:sht,v2:bte) :sht
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:sht,v2:sht) :sht
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:sht,v2:sht) :sht
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:sht,v2:int) :int
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:sht,v2:int) :int
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:sht,v2:lng) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:sht,v2:lng) :lng
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:sht,v2:flt) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:sht,v2:flt) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:sht,v2:dbl) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:sht,v2:dbl) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:int,v2:bte) :int
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:int,v2:bte) :int
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:int,v2:sht) :int
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:int,v2:sht) :int
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:int,v2:int) :int
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:int,v2:int) :int
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:int,v2:lng) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:int,v2:lng) :lng
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:int,v2:flt) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:int,v2:flt) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:int,v2:dbl) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:int,v2:dbl) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:lng,v2:bte) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:lng,v2:bte) :lng
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:lng,v2:sht) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:lng,v2:sht) :lng
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:lng,v2:int) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:lng,v2:int) :lng
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:lng,v2:lng) :lng
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:lng,v2:lng) :lng
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:lng,v2:flt) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:lng,v2:flt) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:lng,v2:dbl) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:lng,v2:dbl) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:flt,v2:bte) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:flt,v2:bte) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:flt,v2:sht) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:flt,v2:sht) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:flt,v2:int) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:flt,v2:int) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:flt,v2:lng) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:flt,v2:lng) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:flt,v2:flt) :flt
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:flt,v2:flt) :flt
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:flt,v2:dbl) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:flt,v2:dbl) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:dbl,v2:bte) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:dbl,v2:bte) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:dbl,v2:sht) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:dbl,v2:sht) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:dbl,v2:int) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:dbl,v2:int) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:dbl,v2:lng) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:dbl,v2:lng) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:dbl,v2:flt) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:dbl,v2:flt) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";

pattern -(v1:dbl,v2:dbl) :dbl
address CMDvarSUBsignal
comment "Return V1 - V2, signal error on overflow";
pattern sub_noerror(v1:dbl,v2:dbl) :dbl
address CMDvarSUB
comment "Return V1 - V2, overflow causes NIL value";


pattern *(v1:bte,v2:bte) :bte
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:bte,v2:bte) :bte
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:bte,v2:sht) :sht
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:bte,v2:sht) :sht
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:bte,v2:int) :int
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:bte,v2:int) :int
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:bte,v2:lng) :lng
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:bte,v2:lng) :lng
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:bte,v2:flt) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:bte,v2:flt) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:bte,v2:dbl) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:bte,v2:dbl) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:sht,v2:bte) :sht
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:sht,v2:bte) :sht
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:sht,v2:sht) :sht
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:sht,v2:sht) :sht
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:sht,v2:int) :int
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:sht,v2:int) :int
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:sht,v2:lng) :lng
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:sht,v2:lng) :lng
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:sht,v2:flt) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:sht,v2:flt) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:sht,v2:dbl) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:sht,v2:dbl) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:int,v2:bte) :int
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:int,v2:bte) :int
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:int,v2:sht) :int
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:int,v2:sht) :int
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:int,v2:int) :int
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:int,v2:int) :int
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:int,v2:lng) :lng
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:int,v2:lng) :lng
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:int,v2:flt) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:int,v2:flt) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:int,v2:dbl) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:int,v2:dbl) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:lng,v2:bte) :lng
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:lng,v2:bte) :lng
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:lng,v2:sht) :lng
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:lng,v2:sht) :lng
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:lng,v2:int) :lng
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:lng,v2:int) :lng
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:lng,v2:lng) :lng
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:lng,v2:lng) :lng
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:lng,v2:flt) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:lng,v2:flt) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:lng,v2:dbl) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:lng,v2:dbl) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:flt,v2:bte) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:flt,v2:bte) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:flt,v2:sht) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:flt,v2:sht) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:flt,v2:int) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:flt,v2:int) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:flt,v2:lng) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:flt,v2:lng) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:flt,v2:flt) :flt
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:flt,v2:flt) :flt
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:flt,v2:dbl) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:flt,v2:dbl) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:dbl,v2:bte) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:dbl,v2:bte) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:dbl,v2:sht) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:dbl,v2:sht) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:dbl,v2:int) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:dbl,v2:int) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:dbl,v2:lng) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:dbl,v2:lng) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:dbl,v2:flt) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:dbl,v2:flt) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";

pattern *(v1:dbl,v2:dbl) :dbl
address CMDvarMULsignal
comment "Return V1 * V2, signal error on overflow";
pattern mul_noerror(v1:dbl,v2:dbl) :dbl
address CMDvarMUL
comment "Return V1 * V2, overflow causes NIL value";


command +(v1:str,v2:str) :str
address CMDvarADDstr
comment "Concatenate LEFT and RIGHT";
command +(v1:str,i:int) :str
address CMDvarADDstrint
comment "Concatenate LEFT and string representation of RIGHT";

pattern /(v1:bte,v2:bte) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:bte) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:bte) :bte
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:bte,v2:bte) :bte
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:bte,v2:sht) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:sht) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:sht) :bte
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:bte,v2:sht) :bte
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:bte,v2:int) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:int) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:int) :bte
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:bte,v2:int) :bte
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:bte,v2:lng) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:lng) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:lng) :bte
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:bte,v2:lng) :bte
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:bte,v2:flt) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:bte,v2:flt) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:bte,v2:flt) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:bte,v2:dbl) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:bte,v2:dbl) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:sht,v2:bte) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:bte) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:bte) :sht
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:sht,v2:bte) :sht
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:sht,v2:sht) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:sht) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:sht) :sht
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:sht,v2:sht) :sht
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:sht,v2:int) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:int) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:int) :sht
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:sht,v2:int) :sht
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:sht,v2:lng) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:lng) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:lng) :sht
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:sht,v2:lng) :sht
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:sht,v2:flt) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:sht,v2:flt) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:sht,v2:flt) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:sht,v2:dbl) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:sht,v2:dbl) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:int,v2:bte) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:bte) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:bte) :int
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:int,v2:bte) :int
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:int,v2:sht) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:sht) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:sht) :int
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:int,v2:sht) :int
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:int,v2:int) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:int) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:int) :int
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:int,v2:int) :int
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:int,v2:lng) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:lng) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:lng) :int
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:int,v2:lng) :int
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:int,v2:flt) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:int,v2:flt) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:int,v2:flt) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:int,v2:dbl) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:int,v2:dbl) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:lng,v2:bte) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:bte) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:bte) :lng
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:lng,v2:bte) :lng
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:lng,v2:sht) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:sht) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:sht) :lng
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:lng,v2:sht) :lng
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:lng,v2:int) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:int) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:int) :lng
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:lng,v2:int) :lng
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:lng,v2:lng) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:lng) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:lng) :lng
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:lng,v2:lng) :lng
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:lng,v2:flt) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:lng,v2:flt) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:lng,v2:flt) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:lng,v2:dbl) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:lng,v2:dbl) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:flt,v2:bte) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:flt,v2:bte) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:flt,v2:bte) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:flt,v2:sht) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:flt,v2:sht) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:flt,v2:sht) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:flt,v2:int) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:flt,v2:int) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:flt,v2:int) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:flt,v2:lng) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:flt,v2:lng) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:flt,v2:lng) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:flt,v2:flt) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern /(v1:flt,v2:flt) :flt
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:flt,v2:flt) :flt
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:flt,v2:dbl) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:flt,v2:dbl) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:dbl,v2:bte) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:dbl,v2:bte) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:dbl,v2:sht) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:dbl,v2:sht) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:dbl,v2:int) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:dbl,v2:int) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:dbl,v2:lng) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:dbl,v2:lng) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:dbl,v2:flt) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:dbl,v2:flt) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";

pattern /(v1:dbl,v2:dbl) :dbl
address CMDvarDIVsignal
comment "Return V1 / V2, signal error on overflow";
pattern div_noerror(v1:dbl,v2:dbl) :dbl
address CMDvarDIV
comment "Return V1 / V2, overflow causes NIL value";


pattern %(v1:bte,v2:bte) :bte
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:bte,v2:bte) :bte
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:bte,v2:sht) :bte
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:bte,v2:sht) :bte
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:bte,v2:int) :bte
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:bte,v2:int) :bte
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:bte,v2:lng) :bte
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:bte,v2:lng) :bte
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:bte,v2:flt) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:bte,v2:flt) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:bte,v2:dbl) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:bte,v2:dbl) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:sht,v2:bte) :bte
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:sht,v2:bte) :bte
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:sht,v2:sht) :sht
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:sht,v2:sht) :sht
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:sht,v2:int) :sht
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:sht,v2:int) :sht
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:sht,v2:lng) :sht
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:sht,v2:lng) :sht
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:sht,v2:flt) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:sht,v2:flt) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:sht,v2:dbl) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:sht,v2:dbl) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:int,v2:bte) :bte
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:int,v2:bte) :bte
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:int,v2:sht) :sht
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:int,v2:sht) :sht
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:int,v2:int) :int
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:int,v2:int) :int
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:int,v2:lng) :int
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:int,v2:lng) :int
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:int,v2:flt) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:int,v2:flt) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:int,v2:dbl) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:int,v2:dbl) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:lng,v2:bte) :bte
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:lng,v2:bte) :bte
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:lng,v2:sht) :sht
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:lng,v2:sht) :sht
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:lng,v2:int) :int
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:lng,v2:int) :int
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:lng,v2:lng) :lng
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:lng,v2:lng) :lng
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:lng,v2:flt) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:lng,v2:flt) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:lng,v2:dbl) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:lng,v2:dbl) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:flt,v2:bte) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:flt,v2:bte) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:flt,v2:sht) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:flt,v2:sht) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:flt,v2:int) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:flt,v2:int) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:flt,v2:lng) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:flt,v2:lng) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:flt,v2:flt) :flt
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:flt,v2:flt) :flt
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:flt,v2:dbl) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:flt,v2:dbl) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:dbl,v2:bte) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:dbl,v2:bte) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:dbl,v2:sht) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:dbl,v2:sht) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:dbl,v2:int) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:dbl,v2:int) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:dbl,v2:lng) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:dbl,v2:lng) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:dbl,v2:flt) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:dbl,v2:flt) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";

pattern %(v1:dbl,v2:dbl) :dbl
address CMDvarMODsignal
comment "Return V1 % V2, signal error on divide by zero";
pattern mod_noerror(v1:dbl,v2:dbl) :dbl
address CMDvarMOD
comment "Return V1 % V2, divide by zero causes NIL value";


pattern and(v1:bit,v2:bit) :bit
address CMDvarAND
comment "Return V1 AND V2";

pattern and(v1:bte,v2:bte) :bte
address CMDvarAND
comment "Return V1 AND V2";

pattern and(v1:sht,v2:sht) :sht
address CMDvarAND
comment "Return V1 AND V2";

pattern and(v1:int,v2:int) :int
address CMDvarAND
comment "Return V1 AND V2";

pattern and(v1:lng,v2:lng) :lng
address CMDvarAND
comment "Return V1 AND V2";


pattern or(v1:bit,v2:bit) :bit
address CMDvarOR
comment "Return V1 OR V2";

pattern or(v1:bte,v2:bte) :bte
address CMDvarOR
comment "Return V1 OR V2";

pattern or(v1:sht,v2:sht) :sht
address CMDvarOR
comment "Return V1 OR V2";

pattern or(v1:int,v2:int) :int
address CMDvarOR
comment "Return V1 OR V2";

pattern or(v1:lng,v2:lng) :lng
address CMDvarOR
comment "Return V1 OR V2";


pattern xor(v1:bit,v2:bit) :bit
address CMDvarXOR
comment "Return V1 XOR V2";

pattern xor(v1:bte,v2:bte) :bte
address CMDvarXOR
comment "Return V1 XOR V2";

pattern xor(v1:sht,v2:sht) :sht
address CMDvarXOR
comment "Return V1 XOR V2";

pattern xor(v1:int,v2:int) :int
address CMDvarXOR
comment "Return V1 XOR V2";

pattern xor(v1:lng,v2:lng) :lng
address CMDvarXOR
comment "Return V1 XOR V2";


pattern <<(v1:bte,v2:bte) :bte
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:bte,v2:bte) :bte
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:bte,v2:sht) :bte
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:bte,v2:sht) :bte
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:bte,v2:int) :bte
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:bte,v2:int) :bte
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:bte,v2:lng) :bte
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:bte,v2:lng) :bte
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:sht,v2:bte) :sht
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:sht,v2:bte) :sht
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:sht,v2:sht) :sht
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:sht,v2:sht) :sht
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:sht,v2:int) :sht
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:sht,v2:int) :sht
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:sht,v2:lng) :sht
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:sht,v2:lng) :sht
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:int,v2:bte) :int
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:int,v2:bte) :int
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:int,v2:sht) :int
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:int,v2:sht) :int
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:int,v2:int) :int
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:int,v2:int) :int
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:int,v2:lng) :int
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:int,v2:lng) :int
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:lng,v2:bte) :lng
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:lng,v2:bte) :lng
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:lng,v2:sht) :lng
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:lng,v2:sht) :lng
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:lng,v2:int) :lng
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:lng,v2:int) :lng
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";

pattern <<(v1:lng,v2:lng) :lng
address CMDvarLSHsignal
comment "Return V1 << V2, raise error on out of range second operand";
pattern lsh_noerror(v1:lng,v2:lng) :lng
address CMDvarLSH
comment "Return V1 << V2, out of range second operand causes NIL value";


pattern >>(v1:bte,v2:bte) :bte
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:bte,v2:bte) :bte
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:bte,v2:sht) :bte
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:bte,v2:sht) :bte
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:bte,v2:int) :bte
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:bte,v2:int) :bte
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:bte,v2:lng) :bte
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:bte,v2:lng) :bte
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:sht,v2:bte) :sht
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:sht,v2:bte) :sht
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:sht,v2:sht) :sht
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:sht,v2:sht) :sht
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:sht,v2:int) :sht
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:sht,v2:int) :sht
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:sht,v2:lng) :sht
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:sht,v2:lng) :sht
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:int,v2:bte) :int
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:int,v2:bte) :int
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:int,v2:sht) :int
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:int,v2:sht) :int
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:int,v2:int) :int
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:int,v2:int) :int
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:int,v2:lng) :int
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:int,v2:lng) :int
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:lng,v2:bte) :lng
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:lng,v2:bte) :lng
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:lng,v2:sht) :lng
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:lng,v2:sht) :lng
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:lng,v2:int) :lng
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:lng,v2:int) :lng
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";

pattern >>(v1:lng,v2:lng) :lng
address CMDvarRSHsignal
comment "Return V1 >> V2, raise error on out of range second operand";
pattern rsh_noerror(v1:lng,v2:lng) :lng
address CMDvarRSH
comment "Return V1 >> V2, out of range second operand causes NIL value";


pattern <(v1:bit,v2:bit) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:str,v2:str) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:oid,v2:oid) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:bte,v2:bte) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:bte,v2:sht) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:bte,v2:int) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:bte,v2:lng) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:bte,v2:flt) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:bte,v2:dbl) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:sht,v2:bte) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:sht,v2:sht) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:sht,v2:int) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:sht,v2:lng) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:sht,v2:flt) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:sht,v2:dbl) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:int,v2:bte) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:int,v2:sht) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:int,v2:int) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:int,v2:lng) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:int,v2:flt) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:int,v2:dbl) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:lng,v2:bte) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:lng,v2:sht) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:lng,v2:int) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:lng,v2:lng) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:lng,v2:flt) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:lng,v2:dbl) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:flt,v2:bte) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:flt,v2:sht) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:flt,v2:int) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:flt,v2:lng) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:flt,v2:flt) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:flt,v2:dbl) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:dbl,v2:bte) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:dbl,v2:sht) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:dbl,v2:int) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:dbl,v2:lng) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:dbl,v2:flt) :bit
address CMDvarLT
comment "Return V1 < V2";

pattern <(v1:dbl,v2:dbl) :bit
address CMDvarLT
comment "Return V1 < V2";


pattern <=(v1:bit,v2:bit) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:str,v2:str) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:oid,v2:oid) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:bte,v2:bte) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:bte,v2:sht) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:bte,v2:int) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:bte,v2:lng) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:bte,v2:flt) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:bte,v2:dbl) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:sht,v2:bte) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:sht,v2:sht) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:sht,v2:int) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:sht,v2:lng) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:sht,v2:flt) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:sht,v2:dbl) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:int,v2:bte) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:int,v2:sht) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:int,v2:int) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:int,v2:lng) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:int,v2:flt) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:int,v2:dbl) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:lng,v2:bte) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:lng,v2:sht) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:lng,v2:int) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:lng,v2:lng) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:lng,v2:flt) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:lng,v2:dbl) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:flt,v2:bte) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:flt,v2:sht) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:flt,v2:int) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:flt,v2:lng) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:flt,v2:flt) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:flt,v2:dbl) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:dbl,v2:bte) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:dbl,v2:sht) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:dbl,v2:int) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:dbl,v2:lng) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:dbl,v2:flt) :bit
address CMDvarLE
comment "Return V1 <= V2";

pattern <=(v1:dbl,v2:dbl) :bit
address CMDvarLE
comment "Return V1 <= V2";


pattern >(v1:bit,v2:bit) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:str,v2:str) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:oid,v2:oid) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:bte,v2:bte) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:bte,v2:sht) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:bte,v2:int) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:bte,v2:lng) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:bte,v2:flt) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:bte,v2:dbl) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:sht,v2:bte) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:sht,v2:sht) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:sht,v2:int) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:sht,v2:lng) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:sht,v2:flt) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:sht,v2:dbl) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:int,v2:bte) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:int,v2:sht) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:int,v2:int) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:int,v2:lng) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:int,v2:flt) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:int,v2:dbl) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:lng,v2:bte) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:lng,v2:sht) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:lng,v2:int) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:lng,v2:lng) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:lng,v2:flt) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:lng,v2:dbl) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:flt,v2:bte) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:flt,v2:sht) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:flt,v2:int) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:flt,v2:lng) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:flt,v2:flt) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:flt,v2:dbl) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:dbl,v2:bte) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:dbl,v2:sht) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:dbl,v2:int) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:dbl,v2:lng) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:dbl,v2:flt) :bit
address CMDvarGT
comment "Return V1 > V2";

pattern >(v1:dbl,v2:dbl) :bit
address CMDvarGT
comment "Return V1 > V2";


pattern >=(v1:bit,v2:bit) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:str,v2:str) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:oid,v2:oid) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:bte,v2:bte) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:bte,v2:sht) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:bte,v2:int) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:bte,v2:lng) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:bte,v2:flt) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:bte,v2:dbl) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:sht,v2:bte) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:sht,v2:sht) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:sht,v2:int) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:sht,v2:lng) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:sht,v2:flt) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:sht,v2:dbl) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:int,v2:bte) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:int,v2:sht) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:int,v2:int) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:int,v2:lng) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:int,v2:flt) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:int,v2:dbl) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:lng,v2:bte) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:lng,v2:sht) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:lng,v2:int) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:lng,v2:lng) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:lng,v2:flt) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:lng,v2:dbl) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:flt,v2:bte) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:flt,v2:sht) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:flt,v2:int) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:flt,v2:lng) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:flt,v2:flt) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:flt,v2:dbl) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:dbl,v2:bte) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:dbl,v2:sht) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:dbl,v2:int) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:dbl,v2:lng) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:dbl,v2:flt) :bit
address CMDvarGE
comment "Return V1 >= V2";

pattern >=(v1:dbl,v2:dbl) :bit
address CMDvarGE
comment "Return V1 >= V2";


pattern ==(v1:bit,v2:bit) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:str,v2:str) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:oid,v2:oid) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:bte,v2:bte) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:bte,v2:sht) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:bte,v2:int) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:bte,v2:lng) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:bte,v2:flt) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:bte,v2:dbl) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:sht,v2:bte) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:sht,v2:sht) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:sht,v2:int) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:sht,v2:lng) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:sht,v2:flt) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:sht,v2:dbl) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:int,v2:bte) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:int,v2:sht) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:int,v2:int) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:int,v2:lng) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:int,v2:flt) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:int,v2:dbl) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:lng,v2:bte) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:lng,v2:sht) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:lng,v2:int) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:lng,v2:lng) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:lng,v2:flt) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:lng,v2:dbl) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:flt,v2:bte) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:flt,v2:sht) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:flt,v2:int) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:flt,v2:lng) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:flt,v2:flt) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:flt,v2:dbl) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:dbl,v2:bte) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:dbl,v2:sht) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:dbl,v2:int) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:dbl,v2:lng) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:dbl,v2:flt) :bit
address CMDvarEQ
comment "Return V1 == V2";

pattern ==(v1:dbl,v2:dbl) :bit
address CMDvarEQ
comment "Return V1 == V2";


pattern !=(v1:bit,v2:bit) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:str,v2:str) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:oid,v2:oid) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:bte,v2:bte) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:bte,v2:sht) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:bte,v2:int) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:bte,v2:lng) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:bte,v2:flt) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:bte,v2:dbl) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:sht,v2:bte) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:sht,v2:sht) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:sht,v2:int) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:sht,v2:lng) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:sht,v2:flt) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:sht,v2:dbl) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:int,v2:bte) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:int,v2:sht) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:int,v2:int) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:int,v2:lng) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:int,v2:flt) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:int,v2:dbl) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:lng,v2:bte) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:lng,v2:sht) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:lng,v2:int) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:lng,v2:lng) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:lng,v2:flt) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:lng,v2:dbl) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:flt,v2:bte) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:flt,v2:sht) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:flt,v2:int) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:flt,v2:lng) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:flt,v2:flt) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:flt,v2:dbl) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:dbl,v2:bte) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:dbl,v2:sht) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:dbl,v2:int) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:dbl,v2:lng) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:dbl,v2:flt) :bit
address CMDvarNE
comment "Return V1 != V2";

pattern !=(v1:dbl,v2:dbl) :bit
address CMDvarNE
comment "Return V1 != V2";


pattern cmp(v1:bit,v2:bit) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:str,v2:str) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:oid,v2:oid) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:bte,v2:bte) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:bte,v2:sht) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:bte,v2:int) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:bte,v2:lng) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:bte,v2:flt) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:bte,v2:dbl) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:sht,v2:bte) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:sht,v2:sht) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:sht,v2:int) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:sht,v2:lng) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:sht,v2:flt) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:sht,v2:dbl) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:int,v2:bte) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:int,v2:sht) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:int,v2:int) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:int,v2:lng) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:int,v2:flt) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:int,v2:dbl) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:lng,v2:bte) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:lng,v2:sht) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:lng,v2:int) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:lng,v2:lng) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:lng,v2:flt) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:lng,v2:dbl) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:flt,v2:bte) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:flt,v2:sht) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:flt,v2:int) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:flt,v2:lng) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:flt,v2:flt) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:flt,v2:dbl) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:dbl,v2:bte) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:dbl,v2:sht) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:dbl,v2:int) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:dbl,v2:lng) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:dbl,v2:flt) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";

pattern cmp(v1:dbl,v2:dbl) :bte
address CMDvarCMP
comment "Return -1/0/1 if V1 </==/> V2";


pattern between(b:any_1,lo:any_1,hi:any_1) :bit
address CMDvarBETWEEN
comment "B between LO and HI inclusive";

pattern between_symmetric(b:any_1,v1:any_1,v2:any_1) :bit
address CMDvarBETWEENsymmetric
comment "B between V1 and V2 (or vice versa) inclusive";

pattern void(v:void) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:bit) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:bte) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:sht) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:int) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:lng) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:flt) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:dbl) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:oid) :void
address CMDvarCONVERT
comment "Cast VALUE to void";

pattern void(v:str) :void
address CMDvarCONVERT
comment "Cast VALUE to void";


pattern bit(v:void) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:bit) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:bte) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:sht) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:int) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:lng) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:flt) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:dbl) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:oid) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";

pattern bit(v:str) :bit
address CMDvarCONVERT
comment "Cast VALUE to bit";


pattern bte(v:void) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:bit) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:bte) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:sht) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:int) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:lng) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:flt) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:dbl) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:oid) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";

pattern bte(v:str) :bte
address CMDvarCONVERT
comment "Cast VALUE to bte";


pattern sht(v:void) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:bit) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:bte) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:sht) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:int) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:lng) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:flt) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:dbl) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:oid) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";

pattern sht(v:str) :sht
address CMDvarCONVERT
comment "Cast VALUE to sht";


pattern int(v:void) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:bit) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:bte) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:sht) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:int) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:lng) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:flt) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:dbl) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:oid) :int
address CMDvarCONVERT
comment "Cast VALUE to int";

pattern int(v:str) :int
address CMDvarCONVERT
comment "Cast VALUE to int";


pattern lng(v:void) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:bit) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:bte) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:sht) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:int) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:lng) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:flt) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:dbl) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:oid) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";

pattern lng(v:str) :lng
address CMDvarCONVERT
comment "Cast VALUE to lng";


pattern flt(v:void) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:bit) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:bte) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:sht) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:int) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:lng) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:flt) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:dbl) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:oid) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";

pattern flt(v:str) :flt
address CMDvarCONVERT
comment "Cast VALUE to flt";


pattern dbl(v:void) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:bit) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:bte) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:sht) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:int) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:lng) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:flt) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:dbl) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:oid) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";

pattern dbl(v:str) :dbl
address CMDvarCONVERT
comment "Cast VALUE to dbl";


pattern oid(v:void) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:bit) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:bte) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:sht) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:int) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:lng) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:flt) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:dbl) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:oid) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";

pattern oid(v:str) :oid
address CMDvarCONVERT
comment "Cast VALUE to oid";


pattern str(v:any) :str
address CMDvarCONVERT
comment "Cast VALUE to str";


pattern min(v1:any_1, v2:any_1) :any_1
address CALCmin
comment "Return min of V1 and V2";

pattern min_no_nil(v1:any_1, v2:any_1) :any_1
address CALCmin_no_nil
comment "Return min of V1 and V2, ignoring nil values";

pattern max(v1:any_1, v2:any_1) :any_1
address CALCmax
comment "Return max of V1 and V2";

pattern max_no_nil(v1:any_1, v2:any_1) :any_1
address CALCmax_no_nil
comment "Return max of V1 and V2, ignoring nil values";

command ptr(v:ptr) :ptr
address CMDvarCONVERTptr
comment "Cast VALUE to ptr";

pattern setoid(v:int) :void
address CMDsetoid;
pattern setoid(v:oid) :void
address CMDsetoid;
pattern setoid(v:lng) :void
address CMDsetoid;

pattern ifthenelse(b:bit,t:any_1,f:any_1):any_1
address CALCswitchbit
comment "If VALUE is true return MIDDLE else RIGHT";

command length(s:str) :int
address CMDstrlength
comment "Length of STRING";

module aggr;

pattern sum(b:bat[:bte]) :bte
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],nil_if_empty:bit) :bte
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],s:bat[:oid]) :bte
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :bte
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:bte]) :sht
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],nil_if_empty:bit) :sht
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],s:bat[:oid]) :sht
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :sht
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:bte]) :int
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],nil_if_empty:bit) :int
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],s:bat[:oid]) :int
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :int
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:bte]) :lng
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],nil_if_empty:bit) :lng
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],s:bat[:oid]) :lng
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :lng
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:bte]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:bte],s:bat[:oid]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:sht]) :sht
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:sht],nil_if_empty:bit) :sht
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:sht],s:bat[:oid]) :sht
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:sht],s:bat[:oid],nil_if_empty:bit) :sht
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:sht]) :int
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:sht],nil_if_empty:bit) :int
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:sht],s:bat[:oid]) :int
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:sht],s:bat[:oid],nil_if_empty:bit) :int
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:sht]) :lng
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:sht],nil_if_empty:bit) :lng
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:sht],s:bat[:oid]) :lng
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:sht],s:bat[:oid],nil_if_empty:bit) :lng
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:sht]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:sht],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:sht],s:bat[:oid]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:sht],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:int]) :int
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:int],nil_if_empty:bit) :int
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:int],s:bat[:oid]) :int
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:int],s:bat[:oid],nil_if_empty:bit) :int
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:int]) :lng
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:int],nil_if_empty:bit) :lng
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:int],s:bat[:oid]) :lng
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:int],s:bat[:oid],nil_if_empty:bit) :lng
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:int]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:int],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:int],s:bat[:oid]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:int],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:lng]) :lng
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:lng],nil_if_empty:bit) :lng
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:lng],s:bat[:oid]) :lng
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:lng],s:bat[:oid],nil_if_empty:bit) :lng
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:lng]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:lng],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:lng],s:bat[:oid]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:lng],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:flt]) :flt
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:flt],nil_if_empty:bit) :flt
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:flt],s:bat[:oid]) :flt
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:flt],s:bat[:oid],nil_if_empty:bit) :flt
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:flt]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:flt],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:flt],s:bat[:oid]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:flt],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern sum(b:bat[:dbl]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:dbl],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B.";
pattern sum(b:bat[:dbl],s:bat[:oid]) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";
pattern sum(b:bat[:dbl],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATsum
comment "Calculate aggregate sum of B with candidate list.";

pattern prod(b:bat[:bte]) :bte
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],nil_if_empty:bit) :bte
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],s:bat[:oid]) :bte
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :bte
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:bte]) :sht
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],nil_if_empty:bit) :sht
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],s:bat[:oid]) :sht
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :sht
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:bte]) :int
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],nil_if_empty:bit) :int
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],s:bat[:oid]) :int
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :int
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:bte]) :lng
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],nil_if_empty:bit) :lng
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],s:bat[:oid]) :lng
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :lng
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:bte]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:bte],s:bat[:oid]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:bte],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:sht]) :sht
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:sht],nil_if_empty:bit) :sht
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:sht],s:bat[:oid]) :sht
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:sht],s:bat[:oid],nil_if_empty:bit) :sht
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:sht]) :int
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:sht],nil_if_empty:bit) :int
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:sht],s:bat[:oid]) :int
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:sht],s:bat[:oid],nil_if_empty:bit) :int
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:sht]) :lng
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:sht],nil_if_empty:bit) :lng
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:sht],s:bat[:oid]) :lng
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:sht],s:bat[:oid],nil_if_empty:bit) :lng
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:sht]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:sht],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:sht],s:bat[:oid]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:sht],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:int]) :int
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:int],nil_if_empty:bit) :int
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:int],s:bat[:oid]) :int
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:int],s:bat[:oid],nil_if_empty:bit) :int
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:int]) :lng
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:int],nil_if_empty:bit) :lng
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:int],s:bat[:oid]) :lng
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:int],s:bat[:oid],nil_if_empty:bit) :lng
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:int]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:int],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:int],s:bat[:oid]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:int],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:lng]) :lng
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:lng],nil_if_empty:bit) :lng
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:lng],s:bat[:oid]) :lng
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:lng],s:bat[:oid],nil_if_empty:bit) :lng
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:lng]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:lng],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:lng],s:bat[:oid]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:lng],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:flt]) :flt
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:flt],nil_if_empty:bit) :flt
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:flt],s:bat[:oid]) :flt
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:flt],s:bat[:oid],nil_if_empty:bit) :flt
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:flt]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:flt],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:flt],s:bat[:oid]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:flt],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

pattern prod(b:bat[:dbl]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:dbl],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B.";
pattern prod(b:bat[:dbl],s:bat[:oid]) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";
pattern prod(b:bat[:dbl],s:bat[:oid],nil_if_empty:bit) :dbl
address CMDBATprod
comment "Calculate aggregate product of B with candidate list.";

