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setup.py
doc/architecture.dia
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litedram/__init__.py
litedram/common.py
litedram/dfii.py
litedram/gen.py
litedram/init.py
litedram/modules.py
litedram.egg-info/PKG-INFO
litedram.egg-info/SOURCES.txt
litedram.egg-info/dependency_links.txt
litedram.egg-info/entry_points.txt
litedram.egg-info/requires.txt
litedram.egg-info/top_level.txt
litedram/core/__init__.py
litedram/core/bandwidth.py
litedram/core/bankmachine.py
litedram/core/controller.py
litedram/core/crossbar.py
litedram/core/multiplexer.py
litedram/core/refresher.py
litedram/frontend/__init__.py
litedram/frontend/adapter.py
litedram/frontend/axi.py
litedram/frontend/bist.py
litedram/frontend/dma.py
litedram/frontend/ecc.py
litedram/frontend/fifo.py
litedram/frontend/wishbone.py
litedram/phy/__init__.py
litedram/phy/dfi.py
litedram/phy/ecp5ddrphy.py
litedram/phy/gensdrphy.py
litedram/phy/gw2ddrphy.py
litedram/phy/model.py
litedram/phy/s6ddrphy.py
litedram/phy/s7common.py
litedram/phy/s7ddrphy.py
litedram/phy/sim_utils.py
litedram/phy/usddrphy.py
litedram/phy/utils.py
litedram/phy/lpddr4/README.md
litedram/phy/lpddr4/__init__.py
litedram/phy/lpddr4/basephy.py
litedram/phy/lpddr4/commands.py
litedram/phy/lpddr4/s7phy.py
litedram/phy/lpddr4/sim.py
litedram/phy/lpddr4/simphy.py
litedram/phy/lpddr4/simsoc.py
litedram/phy/lpddr5/__init__.py
litedram/phy/lpddr5/basephy.py
litedram/phy/lpddr5/commands.py
litedram/phy/lpddr5/s7phy.py
litedram/phy/lpddr5/sim.py
litedram/phy/lpddr5/simphy.py
litedram/phy/lpddr5/simsoc.py
litedram/phy/rpc/README.md
litedram/phy/rpc/__init__.py
litedram/phy/rpc/arty.py
litedram/phy/rpc/basephy.py
litedram/phy/rpc/commands.py
litedram/phy/rpc/s7phy.py
litedram/phy/rpc/simphy.py
litedram/phy/rpc/simsoc.py