{% extends "base_documentation.j2" %}

{% block architecture_overview %}
## Architecture Overview

{%- for prop in isa.properties %}
- **{{ prop.name }}**: {{ prop.value }}
{%- endfor %}
{% endblock %}

{% block registers_section %}
## Registers

### General Purpose Registers

{%- for reg in isa.registers %}
{%- if reg.type == 'gpr' %}
#### {{ reg.name }}
- **Type**: General Purpose Register
- **Width**: {{ reg.width }} bits
{% if reg.is_register_file() %}
- **Count**: {{ reg.count }} registers ({{ reg.name }}[0] to {{ reg.name }}[{{ reg.count - 1 }}])
{% endif %}
{%- elif reg.type == 'vec' %}
#### {{ reg.name }}
- **Type**: Vector Register
- **Width**: {{ reg.width }} bits
- **Lanes**: {{ reg.lanes }}
- **Element Width**: {{ reg.element_width }} bits
{%- if reg.is_register_file() %}
- **Count**: {{ reg.count }} vector registers
{%- endif %}
{%- if reg.fields %}
- **Fields**:
{%- for field in reg.fields %}
  - `{{ field.name }}`: bits [{{ field.msb }}:{{ field.lsb }}]
{%- endfor %}
{%- endif %}

{%- endif %}
{% endfor %}

### Special Function Registers

{% for reg in isa.registers %}
{% if reg.type == 'sfr' %}
#### {{ reg.name }}
- **Type**: Special Function Register
- **Width**: {{ reg.width }} bits
{%- if reg.fields %}
- **Fields**:
{%- for field in reg.fields %}
  - `{{ field.name }}`: bits [{{ field.msb }}:{{ field.lsb }}]
{%- endfor %}
{%- endif %}

{% endif %}
{% endfor %}
{% endblock %}

{% block formats_section %}
## Instruction Formats

{%- for fmt in isa.formats %}
### {{ fmt.name }}

- **Width**: {{ fmt.width }} bits

**Field Layout**:

| Field | Bits | Width | Description |
|-------|------|-------|-------------|
{%- for field in fmt.fields %}
| `{{ field.name }}` | [{{ field.msb }}:{{ field.lsb }}] | {{ field.width() }} | |
{%- endfor %}

**Bit Layout**:
```
{%- set max_bit = fmt.width - 1 %}
{%- set bit_layout = [] %}
{%- for i in range(max_bit, -1, -1) %}
{%- set found = False %}
{%- for field in fmt.fields %}
{%- if i >= field.lsb and i <= field.msb %}
{%- if not found %}
{%- set _ = bit_layout.append(field.name[0].upper()) %}
{%- set found = True %}
{%- endif %}
{%- endif %}
{%- endfor %}
{%- if not found %}
{%- set _ = bit_layout.append('-') %}
{%- endif %}
{%- endfor %}
{{ bit_layout | join('') }}
```

{%- if fmt.identification_fields %}
- **Identification Fields**: {{ fmt.identification_fields | join(', ') }}
{%- endif %}

{%- endfor %}

{%- for bundle_fmt in isa.bundle_formats %}
### {{ bundle_fmt.name }}
- **Width**: {{ bundle_fmt.width }} bits
- **Slots**:
{%- for slot in bundle_fmt.slots %}
  - `{{ slot.name }}`: bits [{{ slot.msb }}:{{ slot.lsb }}] ({{ slot.width() }} bits)
{%- endfor %}
{%- if bundle_fmt.identification_fields %}
- **Identification Fields**: {{ bundle_fmt.identification_fields | join(', ') }}
{%- endif %}

{%- endfor %}
{% endblock %}

{% block instructions_section %}
## Instruction Set

{%- for instr in isa.instructions %}
### {{ instr.mnemonic.upper() }}

**Format**: {% if instr.format %}{{ instr.format.name }}{% else %}N/A{% endif %}

{%- if instr.operands %}
**Operands**: {%- for op in instr.operands %}{{ op }}{% if not loop.last %}, {% endif %}{%- endfor %}
{%- endif %}

{%- if instr.encoding %}
**Encoding**:
{%- for assignment in instr.encoding.assignments %}
- `{{ assignment.field }}` = `0x{{ "%x"|format(assignment.value) }}`
{%- endfor %}
{%- endif %}

{%- if instr.behavior %}
**Behavior**:
```
{%- for stmt in instr.behavior.statements %}
{{ format_rtl_statement(stmt) }}
{%- endfor %}
```
{%- endif %}

{%- if instr.assembly_syntax %}
- **Assembly Syntax**: `{{ instr.assembly_syntax }}`
{%- endif %}

---

{%- endfor %}
{% endblock %}

