Metadata-Version: 2.0
Name: HdlLib
Version: 0.1
Summary: VHDL source management : parse, organize, assemble, generate testbenches
Home-page: https://gitlab.com/Yabolo/HdlLib
Author: Matthieu PAYET
Author-email: matthieu.payet@free.fr
License: GPLv3
Keywords: FPGA VHDL IP testbench test parser circuit system design RTL HDL
Platform: UNKNOWN
Classifier: Development Status :: 3 - Alpha
Classifier: Intended Audience :: Developers
Classifier: Topic :: Software Development :: Build Tools
Classifier: License :: OSI Approved :: GNU General Public License v3 (GPLv3)
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.3
Classifier: Programming Language :: Python :: 3.4
Classifier: Programming Language :: Python :: 3.5
Requires-Dist: cairosvg
Requires-Dist: cffi
Requires-Dist: lxml
Provides-Extra: dev
Requires-Dist: check-manifest; extra == 'dev'
Provides-Extra: test
Requires-Dist: coverage; extra == 'test'


HdlLib  
=========

HdlLib is a Python module for dealing with VHDL files :
* Manage a VHDL library,
* Assemble IPs,
* Generate testbenches,
* Parse VHDL entities,
* Generate synoptics of entity interfaces.

***

> This is the README file for the Python project.

***

Installation :
--------------

### From Pypi (recommanded)

```
pip install HdlLib
```

This will setup the commands to be available from a terminal and install the Python package.

HdlLib is only compatible with Python3.x (incompatible with Python2).

Usage :
-------

### By command line
`HdlLib --help` will print the available sub-command options. Currently, these are available :

| Sub-command     | Description                                                                 |
|-----------------|-----------------------------------------------------------------------------|
| addlib          | generate *.xml library file from VHDL sources (interactive).                |
| tbgen           | generate Alstom's tbgen testbench files (VHDL + scenario file) from a VHDL sources (interactive) and a synoptic *.png image of the entity parsed.      |
| synoptic        | generate a synoptic *.png image of the entity parsed from VHDL source file. |
| parseregression | perform regression test of the VHDL parser on every VHDL file found in the given directory (recursively). |

### As a python package

See the documentation.

***

>HdlLib is distributed with a GPLv3 license.
See LICENSE.txt for details.

***

Matthieu PAYET <matthieu.payet@free.fr>

More on Matthieu's website : https://mpayet.net




