# FVM

FVM is the first publicly available, general-purpose, open-source Formal
Verification Methodology for VHDL designs.

## Features

* Defined methodology with detailed steps.
* A helper tool that helps writing formal properties (`drom2psl`).
* A build and test framework that acts as an interface to the software tools.
* Thorough documentation, examples and training materials.

## Documentation

This README.md is intentionally short. Please see the documentation at
[https://fvm.us.es](https://fvm.us.es), where you will find installation
instructions, a getting started section, an introduction to Formal
Verification, an introduction to FVM, example designs that have been formally
verified with FVM, techniques to reduce proof complexity, and more!

## Funding

The FVM has been funded by the European Space Agency, through its Open Space
Innovation Platform (OSIP), specifically through the activity [Lowering the
adoption barriers for Formal Verification of ASIC and FPGA designs in the Space
sector](https://activities.esa.int/4000144681). See the Acknowledgment section
of the documentation for more information.

