Metadata-Version: 2.4
Name: fvm-formal
Version: 0.1.16
Summary: A Formal Verification Methodology for ASIC and FPGA designs
Author-email: Hipolito Guzmán-Miranda <hguzman@us.es>, Marcos López García <marlopgar40@alum.us.es>
License-Expression: Apache-2.0
Project-URL: homepage, https://fvm.us.es
Requires-Python: >=3.9
Description-Content-Type: text/markdown
License-File: LICENSE
Requires-Dist: icecream>=2.1.3
Requires-Dist: junit-xml>=1.9
Requires-Dist: loguru>=0.7.3
Requires-Dist: pathlib>=1.0.1
Requires-Dist: pyyaml>=6.0.3
Requires-Dist: rich>=14.2.0
Requires-Dist: termcolor>=3.1.0
Requires-Dist: wavedrom>=2.0.3.post3
Dynamic: license-file

# FVM

FVM is the first publicly available, general-purpose, open-source Formal
Verification Methodology for VHDL designs.

## Features

* Defined methodology with detailed steps.
* A helper tool that helps writing formal properties (`drom2psl`).
* A build and test framework that acts as an interface to the software tools.
* Thorough documentation, examples and training materials.

## Documentation

This README.md is intentionally short. Please see the documentation at
[https://fvm.us.es](https://fvm.us.es), where you will find installation
instructions, a getting started section, an introduction to Formal
Verification, an introduction to FVM, example designs that have been formally
verified with FVM, techniques to reduce proof complexity, and more!

## Funding

The FVM has been funded by the European Space Agency, through its Open Space
Innovation Platform (OSIP), specifically through the activity [Lowering the
adoption barriers for Formal Verification of ASIC and FPGA designs in the Space
sector](https://activities.esa.int/4000144681). See the Acknowledgment section
of the documentation for more information.

