1.8.4 2018-08-18 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Fix matching of default target for CAPI2 cores
* Fix VHDL 2008 usage for GHDL
* Add support for nextpnr in the icestorm backend
* Allow setting user-agent in url provider

* + improved error handling, bug fixes and refactoring

Contributors:
Euripedes Rocha <rocha.euripedes@gmail.com>
Olof Kindgren <olof.kindgren@gmail.com>

1.8.3 2018-07-24 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Allow setting default timescale for Icarus
* Support VHDL libraries in Quartus backend
* Search for cores in subdirectories of other cores
* Allow overriding parameter default values per target

* + improved error handling, bug fixes and refactoring

Contributors:
Anonymous
Olof Kindgren <olof.kindgren@gmail.com>
Philipp Wagner <philipp.wagner@tum.de>
Piotr Esden-Tempski <piotr@esden.net>

1.8.2 2018-06-27 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Ignore directory tree with a FUSESOC_IGNORE file
* Add lint mode for verilator backend
* Split out backends to separate edalize module
* Add spyglass backend
* CAPI2: Allow toplevel to be specified as string
* CAPI2: Expand environment variables in file names

* + improved error handling, bug fixes and refactoring

Contributors:
Olof Kindgren <olof.kindgren@gmail.com>
Philipp Wagner <philipp.wagner@tum.de>

1.8.1 2018-03-22 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Implement sync-type to determine library provider
* Add support for all tools in CAPI2
* Disable logfile by default
* Add bash completion script
* Add --global flag to select fusesoc.conf file
* Redefine script (hooks) section in EDA API
* Add hooks support for CAPI2

* + improved error handling, bug fixes and refactoring

Contributors:
Andrew Wygle <awygle@gmail.com>
Olof Kindgren <olof.kindgren@gmail.com>
Philipp Wagner <philipp.wagner@tum.de>

1.8 2018-01-31 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Add BMM and PCF as valid file types
* Support verilog defines in icestorm backend
* Add --no-export option
* Added versioning to EDA API
* Improved path handling under cygwin
* Support user files in all backends
* Added copyto option
* Exit isim properly after simulations
* Add yosys_synth_options
* Fix quoting of vlogparam strings in ISE
* Pass arguments to ghdl in correct order
* Support multiple toplevels in xsim
* Add command-line option for specifying config file
* Add library add command
* Add library sections in config file
* Add run command
* Add experimental CAPI2 support
* Add target and tool switches to build command

* + improved error handling, bug fixes and refactoring

Contributors:
Ahmed Alsawi <ahmedalsawi2012@gmail.com>
Andrew Wygle <awygle@gmail.com>
Hatim Kanchwala <hatim@hatimak.me>
Jack Gassett <jack.gassett@gadgetfactory.net>
Olof Kindgren <olof.kindgren@gmail.com>
Philipp Wagner <philipp.wagner@tum.de>
Thomas Hornschuh <thomas@hornschuh-family.de>
William D. Jones <thor0505@comcast.net>

1.7 2017-07-21 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Exit with error code when synthesis fails
* Add --version command-line switch
* Improve logging
* Support setting verilog defines in quartus from cli
* Support multiple top-levels in isim
* Removed unmaintained submodule provider
* Remove broken system-info command
* Allow IP-XACT files in subdirectories
* Add UCF as valid file type
* Correctly escape parameters before passing to tools
* Rewrite icarus backend to make reruns easier
* Deprecate verilator define_files
* Separate frontend and backend through EDA API
* Report return code from scripts on failure
* Fix Windows compatibility for Vivado backend
* Fix revision parsing of VLNV names
* vivado: Make our run the default run
* More robust parsing of core files
* + improved error handling, bug fixes and refactoring

Contributors:
Antony Pavlov <antonynpavlov@gmail.com>
Ben Reynwar <ben@reynwar.net>
Olof Kindgren <olof.kindgren@gmail.com>
Philipp Wagner <philipp.wagner@tum.de>

1.6.1 2017-03-21 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Add cmdlineargs support for verilator
* Update dependencies to fix problems with pip
* Support setting verilog verilog defines in ISE from cli
* Add unit tests
* Fix mixing of VHDL2008 and other versions in ghdl
* Support specifying all backend files as filesets
* Remove unused environment variables
* + improved error handling, bug fixes and refactoring

Contributors:
Olof Kindgren <olof.kindgren@gmail.com>
Staf Verhaegen <staf@stafverhaegen.be>
Stefan Wallentowitz <stefan@wallentowitz.de>

1.6 2016-12-11 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Use git-apply to avoid calling external patch command
* Use VLNV identifiers for cores
* Improved dependency handling using simplesat solver
* Allow loading core libraries from env var FUSESOC_CORES
* Add list-paths command
* Allow setting vlog `define from command-line
* Add Vivado backend
* Improve windows compatibility for modelsim and quartus
* Allow loading tclSource files in quartus
* Require valid file types for filesets
* Improve formatting of documentation for github
* Improved documentation
* Add option to setup EDA project without running build
* Add support for multiple top-level testbenches
* Make .system files optional
* Dropped support for Python 3.2 and 3.3
* Improved flow for Modelsim simulations
* Add Riviera Pro simulator support
* Add new standard core library to eventually replace orpsoc-cores
* Added tutorial for creating cores
* + improved error handling, bug fixes and refactoring

Contributors:
Antony Pavlov <antonynpavlov@gmail.com>
Olof Kindgren <olof.kindgren@gmail.com>
Philipp Wagner <philipp.wagner@tum.de>
Stefan Wallentowitz <stefan@wallentowitz.de>

1.5 2016-07-12 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Improve plusargs handling
* Fix core-info for verilator sections
* Allow multiple top-level modules in Icarus
* Fix VHDL and SystemVerilog support in ISIM
* Add support for the GHDL simulator
* Add support for Vivado Logicore cores
* Add support for ISE CoreGen cores
* Support IP-XACT 2009 and 2014 versions
* Add icestorm backend
* Allow settings default values for parameters
* Add support for Altera qip files
* Add CI testing with Travis and appveyor
* Experimental Windows support
* Allow Modelsim to run user TCL files
* Parallelize verilator jobs to speed up compilation
* + improved error handling, bug fixes and refactoring

Contributors:
Andrzej Radecki <ndrwrdck@gmail.com>
Neil Turley <neilpturley@gmail.com>
Olof Kindgren <olof.kindgren@gmail.com>
Philipp Wagner <philipp.wagner@tum.de>
Stefan Wallentowitz <stefan@wallentowitz.de>

1.4 2016-01-29 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Allow setting top-level parameters in backends
* Allow FuseSoC to handle verilator CLI arguments
* Parse command-line before building sim model
* Support plusargs in XSIM
* Initial IP-Xact support (FileSets and description)
* Add distutils-based build system and add to pypi
* Support mixed-language (VHDL, verilog, SV) in ModelSim
* Support mixed-language (VHDL, verilog, SV) in XSIM
* Add fileset sections (replaces vhdl/verilog sections)
* Allow per-file attributes in .core
* + improved error handlig, bug fixes and refactoring

Contributors:
Chris Higgs <chris.higgs@potentialventures.com>
Franck Jullien <franck.jullien@gmail.com>
Olof Kindgren <olof.kindgren@gmail.com>

1.3 2015-11-16 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Add item to .core files to explicitly apply patches
* Export FuseSoC dirs as env vars to external commands
* Use relative paths everywhere
* Always rebuild sim model, except when --keep is used
* Prettify core-info output
* Generate CAPI directly from section.py
* Add more helpful data types to section members
* Support multiple top-level testbenches
* Add git provider
* Add pgm option to ISE backend
* Add support for Xilinx ISIM Simulator
* Abort FuseSoC on scripts with non-zero return code
* Run scripts from all core deps in simulations
* Add parameter section (replaces plusargs)
* Add support for Xilinx XSIM Simulator
* + improved error handling, bug fixes and refactoring

Contributors:
Andrzej Radecki <ndrwrdck@gmail.com>
Franck Jullien <franck.jullien@gmail.com>
Jeffrey Esquivel S <jeff@estudiomanati.com>
Leonardo Lessa <llessa@users.noreply.github.com>
Lukas Rinderer <lukas@gastro-plan.at>
Michael Gielda <mgielda@antmicro.com>
Olof Kindgren <olof.kindgren@gmail.com>

1.2 2015-02-24 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Allow files in core root to overlay files in cache
* Add support for pre_build_scripts in cores
* Fix checks for SystemC environment variables
* Allow absolute file paths in core files
* Add --verbose flag for detailed output
* Add --monochrome flag for monochrome output
* Report all sections in core-info
* Allow cores to specify themselves as non-cachable
* Allow symlinks in core libraries
* Add update command to update core libraries
* Add init command for initial setup of core libraries
* Remove deprecated --systems-root flag
* Add configure flag to optionally disable SVN providers
* Allow cores to be located anywhere in the core libraries
* Add 32/64-bit autodetection with override
* Add git submodule provider
* Generate detailed ISE map report
* + improved error handling, bug fixes and refactoring

Contributors:
Christian Svensson <blue@cmd.nu>
Franck Jullien <franck.jullien@gmail.com>
Jeremy Bennett <jeremy.bennett@embecosm.com>
Olof Kindgren <olof.kindgren@gmail.com>
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>

1.1 2014-04-15 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Support system-installed Verilator
* Allow tool-specific dependencies
* Allow custom names on synthesis/simulator top levels
* Allow subdirectories in cores_root
* Colorized status output
* Improved exception handling
* Allow verilator test benches to access functions in other cores
* Allow passing options directly to backend tools
* Add preliminary VHDL support
* Integrate Altera Qsys generation in Quartus flow
* Add support for building with Xilinx ISE
* + lots of bug fixes and refactoring

Contributors:
carlos <carlos@marte.inesc-id.pt>
Franck Jullien <franck.jullien@gmail.com>
Olof Kindgren <olof.kindgren@gmail.com>
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
Kenneth Lorthioir <ibelimb@gmail.com>
Jose T. de Sousa <jts@inesc-id.pt>

1.0 2014-02-22 Olof Kindgren <olof.kindgren@gmail.com>
======================================================
* Renamed version of ORPSoC 3.2 without any functional changes
