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module $TOP_MODULE_NAME$(
//- Global Control ------------------
(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out0_V, ASSOCIATED_RESET = ap_rst_n" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input   ap_clk,
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
input   ap_rst_n,

output $COUNT_RANGE$ count,
output $COUNT_RANGE$ maxcount,

//- AXI Stream - Input --------------
output   in0_V_TREADY,
input   in0_V_TVALID,
input  $IN_RANGE$ in0_V_TDATA,

//- AXI Stream - Output --------------
input   out0_V_TREADY,
output   out0_V_TVALID,
output  $OUT_RANGE$ out0_V_TDATA
);

	localparam fifo_core = "$FIFO_CORE$";

	case(fifo_core)
	"sim_fifo_gauge":
		fifo_gauge #(.WIDTH($WIDTH$), .COUNT_WIDTH($COUNT_WIDTH$)) fifo (
			.clk(ap_clk), .rst(!ap_rst_n),
			.idat(in0_V_TDATA), .ivld(in0_V_TVALID), .irdy(in0_V_TREADY),
			.odat(out0_V_TDATA), .ovld(out0_V_TVALID), .ordy(out0_V_TREADY),
			.count(count), .maxcount(maxcount)
		);
	"q_srl":
		Q_srl #(
		.depth($DEPTH$),
		.width($WIDTH$)
		)
		impl
		(
		.clock(ap_clk),
		.reset(!ap_rst_n),
		.count(count),
		.maxcount(maxcount),
		.i_d(in0_V_TDATA),
		.i_v(in0_V_TVALID),
		.i_r(in0_V_TREADY),
		.o_d(out0_V_TDATA),
		.o_v(out0_V_TVALID),
		.o_r(out0_V_TREADY)
		);
	default: initial begin
			$error("Unrecognized FIFO_CORE '%s'", FIFO_CORE);
			$finish;
		end
		endcase

endmodule
