# Copyright (C) 2020, Xilinx, Inc.
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import os
import qonnx.custom_op.registry as registry
from qonnx.transformation.base import Transformation

from finn.util.fpgadataflow import is_hls_node, is_rtl_node


class ReplaceVerilogRelPaths(Transformation):
    """Convert ./ relative file paths to absolute ones for generated Verilog"""

    def __init__(self):
        super().__init__()

    def apply(self, model):
        for node in model.graph.node:
            if is_hls_node(node) or is_rtl_node(node):
                try:
                    # lookup op_type in registry of CustomOps
                    inst = registry.getCustomOp(node)
                    # find the IP gen dir
                    ipgen_path = inst.get_nodeattr("ipgen_path")
                    if ipgen_path is not None and os.path.isdir(ipgen_path):
                        for dname, dirs, files in os.walk(ipgen_path):
                            for fname in files:
                                if fname.endswith(".v"):
                                    fpath = os.path.join(dname, fname)
                                    with open(fpath, "r") as f:
                                        s = f.read()
                                    old = '$readmemh(".'
                                    new = '$readmemh("%s' % dname
                                    s = s.replace(old, new)
                                    old = '"./'
                                    new = '"%s/' % dname
                                    s = s.replace(old, new)
                                    with open(fpath, "w") as f:
                                        f.write(s)
                except KeyError:
                    pass
        return (model, False)
