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module $TOP_MODULE_NAME$ (
	(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out0_V, ASSOCIATED_RESET ap_rst_n" *)
	(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
	input  ap_clk,
	(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
	input  ap_rst_n,
	input  [IN_WIDTH_PADDED-1:0] in0_V_TDATA,
	input  in0_V_TVALID,
	output in0_V_TREADY,
	output [OUT_WIDTH_PADDED-1:0] out0_V_TDATA,
	output out0_V_TVALID,
	input  out0_V_TREADY
);

// top-level parameters (set via code-generation)
parameter BIT_WIDTH = $BIT_WIDTH$;
parameter SIMD = $SIMD$;
parameter MMV_IN = $MMV_IN$;
parameter MMV_OUT = $MMV_OUT$;
parameter IN_WIDTH_PADDED = $IN_WIDTH_PADDED$;
parameter OUT_WIDTH_PADDED = $OUT_WIDTH_PADDED$;

// derived constants
parameter BUF_IN_WIDTH = BIT_WIDTH * SIMD * MMV_IN;
parameter BUF_OUT_WIDTH = BIT_WIDTH * SIMD * MMV_OUT;

$TOP_MODULE_NAME$_impl #(
	.BIT_WIDTH(BIT_WIDTH),
	.SIMD(SIMD),
	.MMV_IN(MMV_IN),
	.MMV_OUT(MMV_OUT)
) impl (
	.ap_clk(ap_clk),
	.ap_rst_n(ap_rst_n),
	.in0_V_V_TDATA(in0_V_TDATA[BUF_IN_WIDTH-1:0]),
	.in0_V_V_TVALID(in0_V_TVALID),
	.in0_V_V_TREADY(in0_V_TREADY),
	.out_V_V_TDATA(out0_V_TDATA[BUF_OUT_WIDTH-1:0]),
	.out_V_V_TVALID(out0_V_TVALID),
	.out_V_V_TREADY(out0_V_TREADY)
);

if (OUT_WIDTH_PADDED > BUF_OUT_WIDTH) begin
	assign out0_V_TDATA[OUT_WIDTH_PADDED-1:BUF_OUT_WIDTH] = {(OUT_WIDTH_PADDED-BUF_OUT_WIDTH){1'b0}};
end

endmodule // $TOP_MODULE_NAME$
