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module $TOP_MODULE_NAME$(
//- Global Control ------------------
(* X_INTERFACE_PARAMETER = "ASSOCIATED_BUSIF in0_V:out0_V:s_axilite, ASSOCIATED_RESET = ap_rst_n" *)
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 ap_clk CLK" *)
input   ap_clk,
(* X_INTERFACE_PARAMETER = "POLARITY ACTIVE_LOW" *)
input   ap_rst_n,

//- AXI Lite ------------------------
// Writing
input	       s_axilite_AWVALID,
output	       s_axilite_AWREADY,
input	[4:0]  s_axilite_AWADDR,

input	        s_axilite_WVALID,
output	        s_axilite_WREADY,
input	[31:0]  s_axilite_WDATA,
input	[ 3:0]  s_axilite_WSTRB,

output	       s_axilite_BVALID,
input	       s_axilite_BREADY,
output	[1:0]  s_axilite_BRESP,

// Reading
input	       s_axilite_ARVALID,
output	       s_axilite_ARREADY,
input	[4:0]  s_axilite_ARADDR,

output	        s_axilite_RVALID,
input	        s_axilite_RREADY,
output	[31:0]  s_axilite_RDATA,
output	[ 1:0]  s_axilite_RRESP,

//- AXI Stream - Input --------------
output	in0_V_TREADY,
input	in0_V_TVALID,
input	[$STREAM_BITS$-1:0]  in0_V_TDATA,

//- AXI Stream - Output -------------
input	out0_V_TREADY,
output	out0_V_TVALID,
output	[$STREAM_BITS$-1:0]  out0_V_TDATA
);


fmpadding_axi #(
.XCOUNTER_BITS($XCOUNTER_BITS$),
.YCOUNTER_BITS($YCOUNTER_BITS$),
.NUM_CHANNELS($NUM_CHANNELS$),
.SIMD($SIMD$),
.ELEM_BITS($ELEM_BITS$),
.INIT_XON($INIT_XON$),
.INIT_XOFF($INIT_XOFF$),
.INIT_XEND($INIT_XEND$),
.INIT_YON($INIT_YON$),
.INIT_YOFF($INIT_YOFF$),
.INIT_YEND($INIT_YEND$)
)
impl
(
 .ap_clk(ap_clk),
 .ap_rst_n(ap_rst_n),
 .s_axilite_AWVALID(s_axilite_AWVALID),
 .s_axilite_AWREADY(s_axilite_AWREADY),
 .s_axilite_AWADDR(s_axilite_AWADDR),
 .s_axilite_WVALID(s_axilite_WVALID),
 .s_axilite_WREADY(s_axilite_WREADY),
 .s_axilite_WDATA(s_axilite_WDATA),
 .s_axilite_WSTRB(s_axilite_WSTRB),
 .s_axilite_BVALID(s_axilite_BVALID),
 .s_axilite_BREADY(s_axilite_BREADY),
 .s_axilite_BRESP(s_axilite_BRESP),
 .s_axilite_ARVALID(s_axilite_ARVALID),
 .s_axilite_ARREADY(s_axilite_ARREADY),
 .s_axilite_ARADDR(s_axilite_ARADDR),
 .s_axilite_RVALID(s_axilite_RVALID),
 .s_axilite_RREADY(s_axilite_RREADY),
 .s_axilite_RDATA(s_axilite_RDATA),
 .s_axilite_RRESP(s_axilite_RRESP),
 .s_axis_tready(in0_V_TREADY),
 .s_axis_tvalid(in0_V_TVALID),
 .s_axis_tdata(in0_V_TDATA),
 .m_axis_tready(out0_V_TREADY),
 .m_axis_tvalid(out0_V_TVALID),
 .m_axis_tdata(out0_V_TDATA)
);

endmodule
