# Copyright (c) 2021, Xilinx
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import pytest

import numpy as np
import onnx
import os
import torch
from io import BytesIO
from qonnx.core.datatype import DataType
from qonnx.core.modelwrapper import ModelWrapper
from qonnx.transformation.general import GiveUniqueNodeNames
from qonnx.util.basic import gen_finn_dt_tensor
from torch import nn

from finn.core.onnx_exec import execute_onnx
from finn.transformation.fpgadataflow.compile_cppsim import CompileCppSim
from finn.transformation.fpgadataflow.convert_to_hw_layers import InferConcatLayer
from finn.transformation.fpgadataflow.create_stitched_ip import CreateStitchedIP
from finn.transformation.fpgadataflow.hlssynth_ip import HLSSynthIP
from finn.transformation.fpgadataflow.insert_fifo import InsertFIFO
from finn.transformation.fpgadataflow.prepare_cppsim import PrepareCppSim
from finn.transformation.fpgadataflow.prepare_ip import PrepareIP
from finn.transformation.fpgadataflow.prepare_rtlsim import PrepareRTLSim
from finn.transformation.fpgadataflow.set_exec_mode import SetExecMode
from finn.transformation.fpgadataflow.specialize_layers import SpecializeLayers


def make_concat_model(i_shapes, idts):
    class ConcatModel(nn.Module):
        def forward(self, *args):
            return torch.cat(args, -1)

    torch_model = ConcatModel()
    torch_model.eval()
    input_t = []
    for i_shape in i_shapes:
        input_t.append(torch.zeros(i_shape, dtype=torch.float32))
    input_t = tuple(input_t)
    model_bytes = BytesIO()
    torch.onnx.export(torch_model, input_t, model_bytes, opset_version=11)
    model = onnx.ModelProto.FromString(model_bytes.getvalue())
    model = ModelWrapper(model)
    for inp, idt in zip(model.graph.input, idts):
        model.set_tensor_datatype(inp.name, idt)
    return model


@pytest.mark.xfail(
    "2022" in os.environ["XILINX_VITIS"], reason="Fails with older Vitis HLS versions"
)
@pytest.mark.parametrize("exec_mode", ["cppsim", "rtlsim"])
# input datatypes and expected inferred out datatype
@pytest.mark.parametrize(
    "test_idts", [([DataType["INT3"], DataType["UINT4"], DataType["UINT6"]], DataType["INT7"])]
)
@pytest.mark.fpgadataflow
@pytest.mark.vivado
@pytest.mark.slow
def test_fpgadataflow_concat(exec_mode, test_idts):
    idts = test_idts[0]
    exp_odt = test_idts[1]
    i_shapes = [(1, 2, 4), (1, 2, 6), (1, 2, 1)]
    i_data = [gen_finn_dt_tensor(idt, x) for x, idt in zip(i_shapes, idts)]
    model = make_concat_model(i_shapes, idts)
    assert len(i_shapes) == len(model.graph.input)
    assert len(model.graph.output) == 1
    exp_oshape = list(i_shapes[0][:-1]) + [sum(x[-1] for x in i_shapes)]
    oname = model.graph.output[0].name
    assert model.get_tensor_shape(oname) == exp_oshape
    exp_out = np.concatenate(i_data, axis=-1)
    inp_dict = {}
    for i in range(len(i_shapes)):
        inp_dict[model.graph.input[i].name] = i_data[i]
    ret = execute_onnx(model, inp_dict)
    assert (ret[oname] == exp_out).all()
    # call transformation to convert to HW and verify conversion
    model = model.transform(InferConcatLayer())
    assert model.graph.node[0].op_type == "StreamingConcat"
    assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow"
    assert model.get_tensor_datatype(model.graph.output[0].name) == exp_odt
    ret = execute_onnx(model, inp_dict)
    assert (ret[oname] == exp_out).all()
    model = model.transform(SpecializeLayers("xc7z020clg400-1"))
    assert model.graph.node[0].op_type == "StreamingConcat_hls"
    assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow.hls"
    if exec_mode == "cppsim":
        model = model.transform(GiveUniqueNodeNames())
        model = model.transform(PrepareCppSim())
        model = model.transform(CompileCppSim())
        model = model.transform(SetExecMode("cppsim"))
    elif exec_mode == "rtlsim":
        model = model.transform(GiveUniqueNodeNames())
        model = model.transform(PrepareIP("xc7z020clg400-1", 10))
        model = model.transform(HLSSynthIP())
        model = model.transform(SetExecMode("rtlsim"))
        model = model.transform(PrepareRTLSim())
    ret_sim = execute_onnx(model, inp_dict)
    assert (exp_out == ret_sim[oname]).all()


@pytest.mark.xfail(
    "2022" in os.environ["XILINX_VITIS"], reason="Fails with older Vitis HLS versions"
)
@pytest.mark.fpgadataflow
@pytest.mark.vivado
@pytest.mark.slow
def test_fpgadataflow_concat_stitchedip():
    idts = [DataType["INT3"], DataType["UINT4"], DataType["UINT6"]]
    exp_odt = DataType["INT7"]
    fpga_part = "xc7z020clg400-1"
    clk_ns = 10
    i_shapes = [(1, 2, 4), (1, 2, 6), (1, 2, 1)]
    i_data = [gen_finn_dt_tensor(idt, x) for x, idt in zip(i_shapes, idts)]
    model = make_concat_model(i_shapes, idts)
    assert len(i_shapes) == len(model.graph.input)
    assert len(model.graph.output) == 1
    exp_oshape = list(i_shapes[0][:-1]) + [sum(x[-1] for x in i_shapes)]
    oname = model.graph.output[0].name
    assert model.get_tensor_shape(oname) == exp_oshape
    exp_out = np.concatenate(i_data, axis=-1)
    inp_dict = {}
    for i in range(len(i_shapes)):
        inp_dict[model.graph.input[i].name] = i_data[i]
    ret = execute_onnx(model, inp_dict)
    assert (ret[oname] == exp_out).all()
    # call transformation to convert to HW and verify conversion
    model = model.transform(InferConcatLayer())
    assert model.graph.node[0].op_type == "StreamingConcat"
    assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow"
    assert model.get_tensor_datatype(model.graph.output[0].name) == exp_odt
    model = model.transform(SpecializeLayers(fpga_part))
    assert model.graph.node[0].op_type == "StreamingConcat_hls"
    assert model.graph.node[0].domain == "finn.custom_op.fpgadataflow.hls"
    model = model.transform(InsertFIFO(create_shallow_fifos=True))
    model = model.transform(SpecializeLayers(fpga_part))
    model = model.transform(GiveUniqueNodeNames())
    model = model.transform(PrepareIP(fpga_part, clk_ns))
    model = model.transform(HLSSynthIP())
    model = model.transform(
        CreateStitchedIP(
            fpga_part,
            clk_ns,
            vitis=False,
        )
    )
    model.set_metadata_prop("exec_mode", "rtlsim")
    ret_sim = execute_onnx(model, inp_dict)
    assert (exp_out == ret_sim[oname]).all()
