# Chip Gallery

```{image} ../figs/FORTE_tapeouts.svg
:alt: |-
:  Chips
:  eFPGA_RISCV_TSMC180:
:    eFPGA (ver.1) with RISC-V core and 1K DPRAM
:    FORTE-ENG1
:  eFPGA_STRIVE_sky130:
:    1440 LUT4s + 180 LUT5s + dual-port memories for RF and FIFOs
:    https://github.com/FPGA-Research/eFPGA---RTL-to-GDS-with-SKY130
:  eFPGA_caravel_sky130:
:    CLBs, DSPs, RegFiles, BBRAMs
:    Google Shuttle - MPW-2
:    https://github.com/nguyendao-uom/eFPGA_v3_caravel
:  eFPGA_caravel_sky130:
:    CLBs, DSPs, RegFiles, BBRAMs with custom cells
:    Google Shuttle - MPW-3
:    https://github.com/FPGA-Research/FABulous-Sky---a-heterogeneous-FPGA-fabric-in-Skywater130
:  eFPGA_RISCV_sky130:
:    RISCV with eFPGA for  tensorflow micro applications
:    Google Shuttle - MPW-3
:    https://github.com/nguyendao-uom/fuserisc_ver2
:  ICESOC_caravel:
:    Ibex-Crypto-eFPGA for cryptography
:    Google Shuttle - MPW-4
:    https://github.com/nguyendao-uom/ICESOC
:  Open_eFPGA:
:    Full-opensource eFPGA with OpenLane and SKY130
:    Google Shuttle - MPW5
:    https://github.com/nguyendao-uom/open_eFPGA
:  Open_ReRAM_eFPGA:
:    Full-opensource Reram_based eFPGA SKY130
:    Google Shuttle - MPW4
:    https://github.com/nguyendao-uom/rram_testchip
:width: 800
```
