-- Automatically generated by WhishList - https://gitlab.cern.ch/msilvaol/wishlist
-- File name: {{ name.lower() }}_instantiation
-- Description : {{ description }}

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.{{ name.lower() }}_pkg.all;

entity {{ name.lower() }}_accumulators is
end entity;

architecture rtl of {{ name.lower() }}_accumulators is

signal {{ name.lower() }}_control : {{ name.lower() }}_control_record_type;
signal {{ name.lower() }}_status : {{ name.lower() }}_status_record_type;

signal clk : std_logic;
signal read : std_logic;
signal write : std_logic;
signal address : std_logic_vector({{ address_width-1 }} downto 0);
signal data_in : std_logic_vector({{ address_width-1 }} downto 0);
signal data_out : std_logic_vector({{ address_width-1 }} downto 0);
signal write_ack : std_logic;
signal read_ack : std_logic;
signal error : std_logic;

begin
{# Iterating through registers #}
-- Setting status registers and dumping control registers as a commented line
{%- for register in registers %}
    {%- if register.permission == 'r' and 'accumulator' in register.description %}


    accumulator_{{ register.name.replace('(','_').replace(')','') }}: entity work.accumulator
        generic map (
        {%- if register.width > 1 %}
            WIDTH_O            => status_{{ '.'.join(get_node_names(register, direction='status')['full_name'].split('.')[-2:]) }}'length,
        {%- else %}
            WIDTH_O            => 1,
        {%- endif %}
            WIDTH_I            => 1,
            SYNCHRONISE_INPUT  => false,
            INCREMENT_MODE     => 2,
            SHADOW_REGISTER    => true)
        port map (
        {%- if register.clock is defined %}
            clk_i         => {{ register.clock }},
            rst_i         => clear_load_{{ register.clock }},
            load_i        => clear_load_{{ register.clock }},
        {%- else %}
            clk_i         => ps_sys_clk,
            rst_i         => clear_load,
            load_i        => clear_load,
        {%- endif %}
            ena_i         => '1',
        {%- if register.name.startswith('not_') %}
            input_i(0)    => not (to_X01({{ register.name.split('not_')[-1] }})),
        {%- else %}
            {%- if 'clk' in register.name %}
            input_i(0)    => '1',
            {%- else %}
            input_i(0)    => {{ register.name }},
            {%- endif %}
        {%- endif %}
        {%- if register.width > 1 %}
            accumulator_o => status_{{ '.'.join(get_node_names(register, direction='status')['full_name'].split('.')[-2:]) }});
        {%- else %}
            accumulator_o(0) => status_{{ '.'.join(get_node_names(register, direction='status')['full_name'].split('.')[-2:]) }});
        {%- endif %}
    {%- endif %}

{%- endfor %}




end architecture;
