-- Automatically generated by WhishList - https://gitlab.cern.ch/msilvaol/wishlist
-- File name: {{ name.lower() }}_instantiation
-- Description : {{ description }}

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.{{ name.lower() }}_pkg.all;

entity {{ name.lower() }}_instantiation is
end entity;

architecture rtl of {{ name.lower() }}_instantiation is

signal {{ name.lower() }}_control : {{ name.lower() }}_control_record_type;
signal {{ name.lower() }}_status : {{ name.lower() }}_status_record_type;

signal clk : std_logic;
signal read : std_logic;
signal write : std_logic;
signal address : std_logic_vector({{ address_width-1 }} downto 0);
signal data_in : std_logic_vector({{ address_width-1 }} downto 0);
signal data_out : std_logic_vector({{ address_width-1 }} downto 0);
signal write_ack : std_logic;
signal read_ack : std_logic;
signal error : std_logic;

begin
{# Iterating through registers #}
-- Setting status registers and dumping control registers as a commented line
{%- for register in registers %}
    {%- if register.permission == 'r' %}
{{ get_node_names(register, direction='status')['full_name'] }} <= {{ get_node_names(register, direction='status')['stimulus'] }}; -- ({{ register.stimulus }})
    {%- else %}
-- <= {{ get_node_names(register, direction='control')['full_name'] }};
    {%- endif %}
{%- endfor %}


{{ name.lower() }}_address_decoder_inst : entity work.{{ name.lower() }}_address_decoder
port map(
    clk_i => clk,
    read_i => read,
    write_i => write,
    address_i => address,
    data_i => data_in,
    data_o => data_out,
    write_ack_o => write_ack,
    read_ack_o => read_ack,
    error_o => error,
    {{ name.lower() }}_status_i => {{ name.lower() }}_status,
    {{ name.lower() }}_control_o =>  {{ name.lower() }}_control
);


end architecture;
