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LICENSE
NEWS
README.rst
dev-requirements.txt
pyproject.toml
tox.ini
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doc/edalize.rst
doc/genindex.rst
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doc/make.bat
doc/py-modindex.rst
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doc/dev/extend.rst
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doc/edam/api.rst
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doc/edam/gowin.gv
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doc/edam/lint.gv
doc/edam/sim.gv
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tests/test_veriblelint/lint/verible-verilog-lint.cmd
tests/test_verilator/Makefile
tests/test_verilator/Vtop_module
tests/test_verilator/run.cmd
tests/test_verilator/binary/config.mk
tests/test_verilator/binary/test_verilator_0.vc
tests/test_verilator/cc/config.mk
tests/test_verilator/cc/test_verilator_0.vc
tests/test_verilator/dpi-hdr-only/config.mk
tests/test_verilator/dpi-hdr-only/test_verilator_0.vc
tests/test_verilator/lint-only/config.mk
tests/test_verilator/lint-only/test_verilator_0.vc
tests/test_verilator/preprocess-only/config.mk
tests/test_verilator/preprocess-only/test_verilator_0.vc
tests/test_verilator/sc/config.mk
tests/test_verilator/sc/test_verilator_0.vc
tests/test_verilator/xml-only/config.mk
tests/test_verilator/xml-only/test_verilator_0.vc
tests/test_vivado/Makefile
tests/test_vivado/test_vivado_0.tcl
tests/test_vivado/test_vivado_0_pgm.tcl
tests/test_vivado/test_vivado_0_run.tcl
tests/test_vivado/test_vivado_0_synth.tcl
tests/test_vivado/vivado.cmd
tests/test_vivado/board_file/Makefile
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tests/test_vivado/board_file/test_vivado_0_pgm.tcl
tests/test_vivado/board_file/test_vivado_0_run.tcl
tests/test_vivado/board_file/test_vivado_0_synth.tcl
tests/test_vivado/board_file/test_vivado_minimal_0.tcl
tests/test_vivado/board_file/test_vivado_minimal_0_pgm.tcl
tests/test_vivado/board_file/test_vivado_minimal_0_run.tcl
tests/test_vivado/board_file/test_vivado_minimal_0_synth.tcl
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tests/test_vivado/edif_netlist/Makefile
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tests/test_vivado/edif_netlist/test_vivado_0_pgm.tcl
tests/test_vivado/edif_netlist/test_vivado_0_run.tcl
tests/test_vivado/edif_netlist/test_vivado_0_synth.tcl
tests/test_vivado/edif_netlist/vivado.cmd
tests/test_vivado/edif_netlist_no_link_design/Makefile
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tests/test_vivado/edif_netlist_no_link_design/test_vivado_0_pgm.tcl
tests/test_vivado/edif_netlist_no_link_design/test_vivado_0_run.tcl
tests/test_vivado/edif_netlist_no_link_design/test_vivado_0_synth.tcl
tests/test_vivado/edif_netlist_no_link_design/vivado.cmd
tests/test_vivado/minimal/Makefile
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tests/test_vivado/minimal/test_vivado_minimal_0_pgm.tcl
tests/test_vivado/minimal/test_vivado_minimal_0_run.tcl
tests/test_vivado/minimal/test_vivado_minimal_0_synth.tcl
tests/test_vivado/minimal/vivado.cmd
tests/test_vivado/yosys/Makefile
tests/test_vivado/yosys/edalize_yosys_procs.tcl
tests/test_vivado/yosys/edalize_yosys_template.tcl
tests/test_vivado/yosys/test_vivado_yosys_0.tcl
tests/test_vivado/yosys/test_vivado_yosys_0_pgm.tcl
tests/test_vivado/yosys/test_vivado_yosys_0_run.tcl
tests/test_vivado/yosys/vivado.cmd
tests/test_vivado/yosys/yosys.cmd
tests/test_vpr/vpr/Makefile
tests/test_vunit/run.py
tests/test_vunit/minimal/tb_minimal.vhd
tests/test_vunit/vunit_mock/vunit/__init__.py
tests/test_vunit/vunit_mock/vunit/ui.py
tests/test_vunit/vunit_mock/vunit/vhdl_standard.py
tests/test_xcelium/Makefile
tests/test_xcelium/edalize_build_rtl.f
tests/test_xcelium/edalize_main.f
tests/test_xcelium/xrun.cmd
tests/test_xsim/Makefile
tests/test_xsim/config.mk
tests/test_xsim/test_xsim_0.prj
tests/test_xsim/xelab.cmd
tests/test_xsim/xsim.cmd
tests/test_xsim/mfc/Makefile
tests/test_xsim/mfc/config.mk
tests/test_xsim/mfc/test_xsim_0.prj
tests/test_xsim/mfc/xelab.cmd
tests/test_xsim/mfc/xsim.cmd
tests/test_yosys/custom_output_name/Makefile
tests/test_yosys/default_output_name/Makefile
tests/tools/ecppack/Makefile
tests/tools/efinity/Makefile
tests/tools/efinity/design.xml
tests/tools/gowin/edalize_gowin_template.tcl
tests/tools/gowin/minimal/edalize_gowin_template.tcl
tests/tools/gowinpack/gowin/Makefile
tests/tools/gowinpack/gowin-family/Makefile
tests/tools/icarus/Makefile
tests/tools/icarus/design.scr
tests/tools/icarus/multitop/Makefile
tests/tools/icarus/multitop/design.scr
tests/tools/icepack/Makefile
tests/tools/nextpnr/ecp5/Makefile
tests/tools/nextpnr/himbaechel/Makefile
tests/tools/nextpnr/himbaechel-family/Makefile
tests/tools/nextpnr/minimal/Makefile
tests/tools/openfpgaloader/gowin-tangnano9k/Makefile
tests/tools/vcs/2stage_basic/Makefile
tests/tools/vcs/2stage_basic/parameters.txt
tests/tools/vcs/2stage_basic/synopsys_sim.setup
tests/tools/vcs/2stage_basic/vcs.f
tests/tools/vcs/2stage_minimal/Makefile
tests/tools/vcs/2stage_minimal/parameters.txt
tests/tools/vcs/2stage_minimal/synopsys_sim.setup
tests/tools/vcs/2stage_minimal/vcs.f
tests/tools/vcs/basic/Makefile
tests/tools/vcs/basic/libx.f
tests/tools/vcs/basic/parameters.txt
tests/tools/vcs/basic/synopsys_sim.setup
tests/tools/vcs/basic/vcs.f
tests/tools/vcs/basic/work.f
tests/tools/vcs/basic/work_1.f
tests/tools/vcs/basic/work_2.f
tests/tools/vcs/basic/work_3.f
tests/tools/vcs/basic/work_4.f
tests/tools/vcs/basic/work_5.f
tests/tools/vcs/basic/work_6.f
tests/tools/vcs/minimal/Makefile
tests/tools/vcs/minimal/libx.f
tests/tools/vcs/minimal/parameters.txt
tests/tools/vcs/minimal/synopsys_sim.setup
tests/tools/vcs/minimal/vcs.f
tests/tools/vcs/minimal/work.f
tests/tools/vcs/minimal/work_1.f
tests/tools/vcs/minimal/work_2.f
tests/tools/vcs/minimal/work_3.f
tests/tools/vcs/minimal/work_4.f
tests/tools/vcs/minimal/work_5.f
tests/tools/vcs/minimal/work_6.f
tests/tools/verilator/Makefile
tests/tools/verilator/design.vc
tests/tools/verilator/minimal/Makefile
tests/tools/verilator/minimal/design.vc
tests/tools/vivado/Makefile
tests/tools/vivado/design.tcl
tests/tools/vivado/design_netlist.tcl
tests/tools/vivado/design_pgm.tcl
tests/tools/vivado/design_run.tcl
tests/tools/vivado/design_synth.tcl
tests/tools/vivado/tags/Makefile
tests/tools/vivado/tags/design.tcl
tests/tools/vivado/tags/design_netlist.tcl
tests/tools/vivado/tags/design_pgm.tcl
tests/tools/vivado/tags/design_run.tcl
tests/tools/vivado/tags/design_synth.tcl
tests/tools/xcelium/Makefile
tests/tools/xcelium/xrun.f
tests/tools/xcelium/minimal/Makefile
tests/tools/xcelium/minimal/xrun.f
tests/tools/yosys/ecp5-blif/Makefile
tests/tools/yosys/ecp5-blif/edalize_yosys_procs.tcl
tests/tools/yosys/ecp5-blif/edalize_yosys_template.tcl
tests/tools/yosys/ecp5-edif/Makefile
tests/tools/yosys/ecp5-edif/edalize_yosys_procs.tcl
tests/tools/yosys/ecp5-edif/edalize_yosys_template.tcl
tests/tools/yosys/ecp5-json/Makefile
tests/tools/yosys/ecp5-json/edalize_yosys_procs.tcl
tests/tools/yosys/ecp5-json/edalize_yosys_template.tcl
tests/tools/yosys/ecp5-verilog/Makefile
tests/tools/yosys/ecp5-verilog/edalize_yosys_procs.tcl
tests/tools/yosys/ecp5-verilog/edalize_yosys_template.tcl
tests/tools/yosys/ice40-blif/Makefile
tests/tools/yosys/ice40-blif/edalize_yosys_procs.tcl
tests/tools/yosys/ice40-blif/edalize_yosys_template.tcl
tests/tools/yosys/ice40-edif/Makefile
tests/tools/yosys/ice40-edif/edalize_yosys_procs.tcl
tests/tools/yosys/ice40-edif/edalize_yosys_template.tcl
tests/tools/yosys/ice40-json/Makefile
tests/tools/yosys/ice40-json/edalize_yosys_procs.tcl
tests/tools/yosys/ice40-json/edalize_yosys_template.tcl
tests/tools/yosys/ice40-verilog/Makefile
tests/tools/yosys/ice40-verilog/edalize_yosys_procs.tcl
tests/tools/yosys/ice40-verilog/edalize_yosys_template.tcl
tests/tools/yosys/minimal/Makefile
tests/tools/yosys/minimal/edalize_yosys_procs.tcl
tests/tools/yosys/minimal/edalize_yosys_template.tcl
tests/tools/yosys/template/Makefile
tests/tools/yosys/template/edalize_yosys_procs.tcl
tests/tools/yosys/xilinx-blif/Makefile
tests/tools/yosys/xilinx-blif/edalize_yosys_procs.tcl
tests/tools/yosys/xilinx-blif/edalize_yosys_template.tcl
tests/tools/yosys/xilinx-edif/Makefile
tests/tools/yosys/xilinx-edif/edalize_yosys_procs.tcl
tests/tools/yosys/xilinx-edif/edalize_yosys_template.tcl
tests/tools/yosys/xilinx-json/Makefile
tests/tools/yosys/xilinx-json/edalize_yosys_procs.tcl
tests/tools/yosys/xilinx-json/edalize_yosys_template.tcl
tests/tools/yosys/xilinx-verilog/Makefile
tests/tools/yosys/xilinx-verilog/edalize_yosys_procs.tcl
tests/tools/yosys/xilinx-verilog/edalize_yosys_template.tcl