# Generated from SystemVerilogPreParser.g4 by ANTLR 4.11.1
# encoding: utf-8
from antlr4 import *
from io import StringIO
import sys
if sys.version_info[1] > 5:
	from typing import TextIO
else:
	from typing.io import TextIO

def serializedATN():
    return [
        4,1,419,342,2,0,7,0,2,1,7,1,2,2,7,2,2,3,7,3,2,4,7,4,2,5,7,5,2,6,
        7,6,2,7,7,7,2,8,7,8,2,9,7,9,2,10,7,10,2,11,7,11,2,12,7,12,2,13,7,
        13,2,14,7,14,2,15,7,15,2,16,7,16,2,17,7,17,2,18,7,18,2,19,7,19,2,
        20,7,20,2,21,7,21,2,22,7,22,2,23,7,23,2,24,7,24,2,25,7,25,2,26,7,
        26,2,27,7,27,2,28,7,28,2,29,7,29,2,30,7,30,2,31,7,31,2,32,7,32,2,
        33,7,33,2,34,7,34,2,35,7,35,2,36,7,36,2,37,7,37,2,38,7,38,2,39,7,
        39,2,40,7,40,2,41,7,41,2,42,7,42,2,43,7,43,2,44,7,44,2,45,7,45,2,
        46,7,46,2,47,7,47,2,48,7,48,1,0,5,0,100,8,0,10,0,12,0,103,9,0,1,
        1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,
        1,1,1,1,1,1,1,3,1,125,8,1,1,2,1,2,1,2,1,2,1,2,1,2,1,3,1,3,1,3,1,
        4,1,4,1,4,1,4,1,5,1,5,1,6,1,6,1,6,1,6,1,7,1,7,1,7,1,7,1,7,1,8,1,
        8,1,8,1,9,1,9,1,9,1,10,1,10,1,10,1,11,1,11,1,11,1,12,1,12,1,13,1,
        13,5,13,167,8,13,10,13,12,13,170,9,13,1,14,1,14,1,15,1,15,1,15,1,
        15,1,15,5,15,179,8,15,10,15,12,15,182,9,15,1,15,3,15,185,8,15,1,
        15,1,15,1,16,1,16,1,16,1,16,1,16,5,16,194,8,16,10,16,12,16,197,9,
        16,1,16,3,16,200,8,16,1,16,1,16,1,17,1,17,1,17,1,17,1,17,1,17,1,
        17,1,17,1,17,1,17,1,17,3,17,215,8,17,1,18,1,18,1,19,1,19,1,19,1,
        19,1,19,1,19,1,19,1,19,1,20,1,20,1,20,1,21,1,21,1,22,1,22,1,23,1,
        23,1,24,1,24,1,25,1,25,1,26,1,26,1,27,1,27,1,27,1,27,1,27,1,27,5,
        27,248,8,27,10,27,12,27,251,9,27,1,28,1,28,1,29,1,29,1,29,1,30,1,
        30,1,31,1,31,1,31,1,31,1,31,1,31,5,31,266,8,31,10,31,12,31,269,9,
        31,3,31,271,8,31,1,32,1,32,1,32,3,32,276,8,32,1,32,1,32,1,33,1,33,
        1,34,1,34,1,35,1,35,1,35,1,35,5,35,288,8,35,10,35,12,35,291,9,35,
        1,35,1,35,1,35,1,35,1,35,3,35,298,8,35,1,36,1,36,1,36,1,37,1,37,
        1,38,1,38,1,39,1,39,1,39,1,39,1,39,1,40,1,40,1,40,1,41,1,41,1,41,
        1,42,1,42,1,42,1,43,1,43,1,43,1,43,1,43,1,43,1,44,1,44,1,44,1,44,
        1,45,1,45,1,46,1,46,1,46,1,46,1,47,1,47,1,47,1,48,1,48,1,48,0,0,
        49,0,2,4,6,8,10,12,14,16,18,20,22,24,26,28,30,32,34,36,38,40,42,
        44,46,48,50,52,54,56,58,60,62,64,66,68,70,72,74,76,78,80,82,84,86,
        88,90,92,94,96,0,0,333,0,101,1,0,0,0,2,124,1,0,0,0,4,126,1,0,0,0,
        6,132,1,0,0,0,8,135,1,0,0,0,10,139,1,0,0,0,12,141,1,0,0,0,14,145,
        1,0,0,0,16,150,1,0,0,0,18,153,1,0,0,0,20,156,1,0,0,0,22,159,1,0,
        0,0,24,162,1,0,0,0,26,168,1,0,0,0,28,171,1,0,0,0,30,173,1,0,0,0,
        32,188,1,0,0,0,34,203,1,0,0,0,36,216,1,0,0,0,38,218,1,0,0,0,40,226,
        1,0,0,0,42,229,1,0,0,0,44,231,1,0,0,0,46,233,1,0,0,0,48,235,1,0,
        0,0,50,237,1,0,0,0,52,239,1,0,0,0,54,249,1,0,0,0,56,252,1,0,0,0,
        58,254,1,0,0,0,60,257,1,0,0,0,62,259,1,0,0,0,64,275,1,0,0,0,66,279,
        1,0,0,0,68,281,1,0,0,0,70,297,1,0,0,0,72,299,1,0,0,0,74,302,1,0,
        0,0,76,304,1,0,0,0,78,306,1,0,0,0,80,311,1,0,0,0,82,314,1,0,0,0,
        84,317,1,0,0,0,86,320,1,0,0,0,88,326,1,0,0,0,90,330,1,0,0,0,92,332,
        1,0,0,0,94,336,1,0,0,0,96,339,1,0,0,0,98,100,3,2,1,0,99,98,1,0,0,
        0,100,103,1,0,0,0,101,99,1,0,0,0,101,102,1,0,0,0,102,1,1,0,0,0,103,
        101,1,0,0,0,104,125,3,4,2,0,105,125,3,6,3,0,106,125,3,8,4,0,107,
        125,3,16,8,0,108,125,3,18,9,0,109,125,3,22,11,0,110,125,3,30,15,
        0,111,125,3,32,16,0,112,125,3,34,17,0,113,125,3,38,19,0,114,125,
        3,40,20,0,115,125,3,58,29,0,116,125,3,62,31,0,117,125,3,72,36,0,
        118,125,3,78,39,0,119,125,3,80,40,0,120,125,3,86,43,0,121,125,3,
        88,44,0,122,125,3,92,46,0,123,125,3,94,47,0,124,104,1,0,0,0,124,
        105,1,0,0,0,124,106,1,0,0,0,124,107,1,0,0,0,124,108,1,0,0,0,124,
        109,1,0,0,0,124,110,1,0,0,0,124,111,1,0,0,0,124,112,1,0,0,0,124,
        113,1,0,0,0,124,114,1,0,0,0,124,115,1,0,0,0,124,116,1,0,0,0,124,
        117,1,0,0,0,124,118,1,0,0,0,124,119,1,0,0,0,124,120,1,0,0,0,124,
        121,1,0,0,0,124,122,1,0,0,0,124,123,1,0,0,0,125,3,1,0,0,0,126,127,
        5,137,0,0,127,128,5,381,0,0,128,129,5,86,0,0,129,130,3,96,48,0,130,
        131,5,86,0,0,131,5,1,0,0,0,132,133,5,137,0,0,133,134,5,382,0,0,134,
        7,1,0,0,0,135,136,5,137,0,0,136,137,5,383,0,0,137,138,3,10,5,0,138,
        9,1,0,0,0,139,140,5,405,0,0,140,11,1,0,0,0,141,142,5,137,0,0,142,
        143,5,385,0,0,143,144,3,26,13,0,144,13,1,0,0,0,145,146,5,137,0,0,
        146,147,5,386,0,0,147,148,3,48,24,0,148,149,3,26,13,0,149,15,1,0,
        0,0,150,151,5,137,0,0,151,152,5,387,0,0,152,17,1,0,0,0,153,154,5,
        137,0,0,154,155,5,388,0,0,155,19,1,0,0,0,156,157,5,137,0,0,157,158,
        5,389,0,0,158,21,1,0,0,0,159,160,5,137,0,0,160,161,5,390,0,0,161,
        23,1,0,0,0,162,163,5,409,0,0,163,25,1,0,0,0,164,167,3,74,37,0,165,
        167,3,2,1,0,166,164,1,0,0,0,166,165,1,0,0,0,167,170,1,0,0,0,168,
        166,1,0,0,0,168,169,1,0,0,0,169,27,1,0,0,0,170,168,1,0,0,0,171,172,
        5,365,0,0,172,29,1,0,0,0,173,174,5,137,0,0,174,175,5,391,0,0,175,
        176,3,48,24,0,176,180,3,26,13,0,177,179,3,14,7,0,178,177,1,0,0,0,
        179,182,1,0,0,0,180,178,1,0,0,0,180,181,1,0,0,0,181,184,1,0,0,0,
        182,180,1,0,0,0,183,185,3,12,6,0,184,183,1,0,0,0,184,185,1,0,0,0,
        185,186,1,0,0,0,186,187,3,20,10,0,187,31,1,0,0,0,188,189,5,137,0,
        0,189,190,5,392,0,0,190,191,3,48,24,0,191,195,3,26,13,0,192,194,
        3,14,7,0,193,192,1,0,0,0,194,197,1,0,0,0,195,193,1,0,0,0,195,196,
        1,0,0,0,196,199,1,0,0,0,197,195,1,0,0,0,198,200,3,12,6,0,199,198,
        1,0,0,0,199,200,1,0,0,0,200,201,1,0,0,0,201,202,3,20,10,0,202,33,
        1,0,0,0,203,204,5,137,0,0,204,214,5,393,0,0,205,206,5,86,0,0,206,
        207,3,24,12,0,207,208,5,86,0,0,208,215,1,0,0,0,209,210,5,186,0,0,
        210,211,3,24,12,0,211,212,5,141,0,0,212,215,1,0,0,0,213,215,3,80,
        40,0,214,205,1,0,0,0,214,209,1,0,0,0,214,213,1,0,0,0,215,35,1,0,
        0,0,216,217,5,370,0,0,217,37,1,0,0,0,218,219,5,137,0,0,219,220,5,
        394,0,0,220,221,3,60,30,0,221,222,5,86,0,0,222,223,3,24,12,0,223,
        224,5,86,0,0,224,225,3,36,18,0,225,39,1,0,0,0,226,227,5,137,0,0,
        227,228,5,395,0,0,228,41,1,0,0,0,229,230,5,410,0,0,230,43,1,0,0,
        0,231,232,5,411,0,0,232,45,1,0,0,0,233,234,5,412,0,0,234,47,1,0,
        0,0,235,236,5,419,0,0,236,49,1,0,0,0,237,238,5,407,0,0,238,51,1,
        0,0,0,239,240,5,413,0,0,240,53,1,0,0,0,241,248,5,414,0,0,242,248,
        3,42,21,0,243,248,3,44,22,0,244,248,3,46,23,0,245,248,3,52,26,0,
        246,248,3,76,38,0,247,241,1,0,0,0,247,242,1,0,0,0,247,243,1,0,0,
        0,247,244,1,0,0,0,247,245,1,0,0,0,247,246,1,0,0,0,248,251,1,0,0,
        0,249,247,1,0,0,0,249,250,1,0,0,0,250,55,1,0,0,0,251,249,1,0,0,0,
        252,253,5,403,0,0,253,57,1,0,0,0,254,255,5,137,0,0,255,256,5,396,
        0,0,256,59,1,0,0,0,257,258,5,370,0,0,258,61,1,0,0,0,259,260,5,137,
        0,0,260,261,5,397,0,0,261,270,3,68,34,0,262,267,3,64,32,0,263,264,
        5,50,0,0,264,266,3,64,32,0,265,263,1,0,0,0,266,269,1,0,0,0,267,265,
        1,0,0,0,267,268,1,0,0,0,268,271,1,0,0,0,269,267,1,0,0,0,270,262,
        1,0,0,0,270,271,1,0,0,0,271,63,1,0,0,0,272,273,3,66,33,0,273,274,
        5,117,0,0,274,276,1,0,0,0,275,272,1,0,0,0,275,276,1,0,0,0,276,277,
        1,0,0,0,277,278,3,70,35,0,278,65,1,0,0,0,279,280,5,365,0,0,280,67,
        1,0,0,0,281,282,5,365,0,0,282,69,1,0,0,0,283,284,5,185,0,0,284,289,
        3,64,32,0,285,286,5,50,0,0,286,288,3,64,32,0,287,285,1,0,0,0,288,
        291,1,0,0,0,289,287,1,0,0,0,289,290,1,0,0,0,290,292,1,0,0,0,291,
        289,1,0,0,0,292,293,5,264,0,0,293,298,1,0,0,0,294,298,3,60,30,0,
        295,298,3,76,38,0,296,298,3,28,14,0,297,283,1,0,0,0,297,294,1,0,
        0,0,297,295,1,0,0,0,297,296,1,0,0,0,298,71,1,0,0,0,299,300,5,137,
        0,0,300,301,5,398,0,0,301,73,1,0,0,0,302,303,5,415,0,0,303,75,1,
        0,0,0,304,305,5,366,0,0,305,77,1,0,0,0,306,307,5,137,0,0,307,308,
        5,384,0,0,308,309,3,50,25,0,309,310,3,54,27,0,310,79,1,0,0,0,311,
        312,5,137,0,0,312,313,3,56,28,0,313,81,1,0,0,0,314,315,5,417,0,0,
        315,316,5,416,0,0,316,83,1,0,0,0,317,318,5,417,0,0,318,319,5,416,
        0,0,319,85,1,0,0,0,320,321,5,137,0,0,321,322,5,399,0,0,322,323,3,
        84,42,0,323,324,5,282,0,0,324,325,3,82,41,0,325,87,1,0,0,0,326,327,
        5,137,0,0,327,328,5,400,0,0,328,329,3,90,45,0,329,89,1,0,0,0,330,
        331,5,418,0,0,331,91,1,0,0,0,332,333,5,137,0,0,333,334,5,401,0,0,
        334,335,3,48,24,0,335,93,1,0,0,0,336,337,5,137,0,0,337,338,5,402,
        0,0,338,95,1,0,0,0,339,340,5,404,0,0,340,97,1,0,0,0,16,101,124,166,
        168,180,184,195,199,214,247,249,267,270,275,289,297
    ]

class SystemVerilogPreParser ( Parser ):

    grammarFileName = "SystemVerilogPreParser.g4"

    atn = ATNDeserializer().deserialize(serializedATN())

    decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ]

    sharedContextCache = PredictionContextCache()

    literalNames = [ "<INVALID>", "'accept_on'", "'alias'", "'always'", 
                     "'always_comb'", "'always_ff'", "'always_latch'", "'&'", 
                     "'&&'", "'&&&'", "'&='", "'and'", "'''", "'*'", "'**'", 
                     "'*='", "'*>'", "'assert'", "'assign'", "'assume'", 
                     "'@'", "'@@'", "'automatic'", "'before'", "'begin'", 
                     "'bind'", "'bins'", "'binsof'", "'bit'", "'break'", 
                     "'buf'", "'bufif1'", "'bufif0'", "'byte'", "'^'", "'^='", 
                     "'case'", "'casex'", "'casez'", "'^~'", "'cell'", "'chandle'", 
                     "'checker'", "':'", "'class'", "'::'", "':='", "'clocking'", 
                     "':/'", "'cmos'", "','", "'config'", "'const'", "'constraint'", 
                     "'context'", "'continue'", "'cover'", "'covergroup'", 
                     "'coverpoint'", "'cross'", "'deassign'", "'default'", 
                     "'defparam'", "'design'", "'disable'", "'dist'", "'$'", 
                     "'$error'", "'$fatal'", "'$fullskew'", "'$hold'", "'$info'", 
                     "'$nochange'", "'$period'", "'$recovery'", "'$recrem'", 
                     "'$removal'", "'$root'", "'$setup'", "'$setuphold'", 
                     "'$skew'", "'$timeskew'", "'$unit'", "'$warning'", 
                     "'$width'", "'do'", "'\"'", "'\"DPI\"'", "'\"DPI-C\"'", 
                     "'.'", "'.*'", "'edge'", "'else'", "'!'", "'!='", "'!=='", 
                     "'!=?'", "'end'", "'endcase'", "'endchecker'", "'endclass'", 
                     "'endclocking'", "'endconfig'", "'endfunction'", "'endgenerate'", 
                     "'endgroup'", "'endinterface'", "'endmodule'", "'endpackage'", 
                     "'endprimitive'", "'endprogram'", "'endproperty'", 
                     "'endsequence'", "'endspecify'", "'endtable'", "'endtask'", 
                     "'enum'", "'='", "'=='", "'==='", "'==?'", "'=>'", 
                     "'event'", "'eventually'", "'expect'", "'export'", 
                     "'extends'", "'extern'", "'final'", "'first_match'", 
                     "'for'", "'force'", "'foreach'", "'forever'", "'fork'", 
                     "'forkjoin'", "'function'", "<INVALID>", "'generate'", 
                     "'genvar'", "'global'", "'>'", "'>='", "'>>'", "'>>='", 
                     "'>>>'", "'>>>='", "'#'", "'#=#'", "'##'", "'#-#'", 
                     "'highz1'", "'highz0'", "'if'", "'iff'", "'ifnone'", 
                     "'ignore_bins'", "'illegal_bins'", "'implements'", 
                     "'implies'", "'import'", "'include'", "'initial'", 
                     "'inout'", "'input'", "'inside'", "'instance'", "'int'", 
                     "'integer'", "'interconnect'", "'interface'", "'intersect'", 
                     "'join'", "'join_any'", "'join_none'", "'large'", "'['", 
                     "'{'", "'let'", "'liblist'", "'library'", "'local'", 
                     "'localparam'", "'logic'", "'longint'", "'('", "'<'", 
                     "'<='", "'<<'", "'<<='", "'<<<'", "'<<<='", "'<->'", 
                     "'macromodule'", "'matches'", "'medium'", "'-'", "'-:'", 
                     "'-='", "'->'", "'->>'", "'-incdir'", "'--'", "'%'", 
                     "'modport'", "'module'", "'%='", "'nand'", "'negedge'", 
                     "'nettype'", "'new'", "'nexttime'", "'nmos'", "'nor'", 
                     "'noshowcancelled'", "'not'", "'notif1'", "'notif0'", 
                     "'null'", "'1step'", "'option'", "'or'", "'output'", 
                     "'package'", "'packed'", "'parameter'", "'PATHPULSE$'", 
                     "'+'", "'+:'", "'+='", "'++'", "'pmos'", "'posedge'", 
                     "'primitive'", "'priority'", "'program'", "'property'", 
                     "'protected'", "'pulldown'", "'pull1'", "'pullup'", 
                     "'pull0'", "'pulsestyle_ondetect'", "'pulsestyle_onevent'", 
                     "'pure'", "'?'", "'rand'", "'randc'", "'randcase'", 
                     "'randomize'", "'randsequence'", "']'", "'}'", "'rcmos'", 
                     "'real'", "'realtime'", "'ref'", "'reg'", "'reject_on'", 
                     "'release'", "'repeat'", "'restrict'", "'return'", 
                     "'rnmos'", "')'", "'rpmos'", "'rtran'", "'rtranif1'", 
                     "'rtranif0'", "'s_always'", "'s_eventually'", "'s_nexttime'", 
                     "'s_until'", "'s_until_with'", "'sample'", "';'", "'scalared'", 
                     "'sequence'", "'shortint'", "'shortreal'", "'showcancelled'", 
                     "'signed'", "'/'", "'/='", "'small'", "'soft'", "'solve'", 
                     "'specify'", "'specparam'", "'static'", "'std'", "'string'", 
                     "'strong'", "'strong1'", "'strong0'", "'struct'", "'super'", 
                     "'supply1'", "'supply0'", "'sync_accept_on'", "'sync_reject_on'", 
                     "'table'", "'tagged'", "'task'", "'this'", "'throughout'", 
                     "'~'", "'~&'", "'~^'", "'time'", "'timeprecision'", 
                     "'timeunit'", "'~|'", "'tran'", "'tranif1'", "'tranif0'", 
                     "'tri'", "'triand'", "'tri1'", "'trior'", "'trireg'", 
                     "'tri0'", "'type'", "'type_option'", "'typedef'", "'union'", 
                     "'unique'", "'unique0'", "'unsigned'", "'until'", "'until_with'", 
                     "'untyped'", "'use'", "'uwire'", "'var'", "'vectored'", 
                     "'virtual'", "'|'", "'|='", "'|=>'", "'|->'", "'||'", 
                     "'void'", "'wait'", "'wait_order'", "'wand'", "'weak'", 
                     "'weak1'", "'weak0'", "'while'", "'wildcard'", "'wire'", 
                     "'with'", "'within'", "'wor'", "'xnor'", "'xor'", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "'celldefine'", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "'end_keywords'", "'endcelldefine'", "<INVALID>", 
                     "'__FILE__'", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "'__LINE__'", "'nounconnected_drive'", 
                     "<INVALID>", "'resetall'", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "'undefineall'", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "'``'", "<INVALID>", "'`\\`\"'", "'`\"'" ]

    symbolicNames = [ "<INVALID>", "ACCEPT_ON", "ALIAS", "ALWAYS", "ALWAYS_COMB", 
                      "ALWAYS_FF", "ALWAYS_LATCH", "AM", "AMAM", "AMAMAM", 
                      "AMEQ", "AND", "AP", "AS", "ASAS", "ASEQ", "ASGT", 
                      "ASSERT", "ASSIGN", "ASSUME", "AT", "ATAT", "AUTOMATIC", 
                      "BEFORE", "BEGIN", "BIND", "BINS", "BINSOF", "BIT", 
                      "BREAK", "BUF", "BUFIFONE", "BUFIFZERO", "BYTE", "CA", 
                      "CAEQ", "CASE", "CASEX", "CASEZ", "CATI", "CELL", 
                      "CHANDLE", "CHECKER", "CL", "CLASS", "CLCL", "CLEQ", 
                      "CLOCKING", "CLSL", "CMOS", "CO", "CONFIG", "CONST", 
                      "CONSTRAINT", "CONTEXT", "CONTINUE", "COVER", "COVERGROUP", 
                      "COVERPOINT", "CROSS", "DEASSIGN", "DEFAULT", "DEFPARAM", 
                      "DESIGN", "DISABLE", "DIST", "DL", "DLERROR", "DLFATAL", 
                      "DLFULLSKEW", "DLHOLD", "DLINFO", "DLNOCHANGE", "DLPERIOD", 
                      "DLRECOVERY", "DLRECREM", "DLREMOVAL", "DLROOT", "DLSETUP", 
                      "DLSETUPHOLD", "DLSKEW", "DLTIMESKEW", "DLUNIT", "DLWARNING", 
                      "DLWIDTH", "DO", "DQ", "DQDPIDQ", "DQDPIMICDQ", "DT", 
                      "DTAS", "EDGE", "ELSE", "EM", "EMEQ", "EMEQEQ", "EMEQQM", 
                      "END", "ENDCASE", "ENDCHECKER", "ENDCLASS", "ENDCLOCKING", 
                      "ENDCONFIG", "ENDFUNCTION", "ENDGENERATE", "ENDGROUP", 
                      "ENDINTERFACE", "ENDMODULE", "ENDPACKAGE", "ENDPRIMITIVE", 
                      "ENDPROGRAM", "ENDPROPERTY", "ENDSEQUENCE", "ENDSPECIFY", 
                      "ENDTABLE", "ENDTASK", "ENUM", "EQ", "EQEQ", "EQEQEQ", 
                      "EQEQQM", "EQGT", "EVENT", "EVENTUALLY", "EXPECT", 
                      "EXPORT", "EXTENDS", "EXTERN", "FINAL", "FIRST_MATCH", 
                      "FOR", "FORCE", "FOREACH", "FOREVER", "FORK", "FORKJOIN", 
                      "FUNCTION", "GA", "GENERATE", "GENVAR", "GLOBAL", 
                      "GT", "GTEQ", "GTGT", "GTGTEQ", "GTGTGT", "GTGTGTEQ", 
                      "HA", "HAEQHA", "HAHA", "HAMIHA", "HIGHZONE", "HIGHZZERO", 
                      "IF", "IFF", "IFNONE", "IGNORE_BINS", "ILLEGAL_BINS", 
                      "IMPLEMENTS", "IMPLIES", "IMPORT", "INCLUDE", "INITIAL", 
                      "INOUT", "INPUT", "INSIDE", "INSTANCE", "INT", "INTEGER", 
                      "INTERCONNECT", "INTERFACE", "INTERSECT", "JOIN", 
                      "JOIN_ANY", "JOIN_NONE", "LARGE", "LB", "LC", "LET", 
                      "LIBLIST", "LIBRARY", "LOCAL", "LOCALPARAM", "LOGIC", 
                      "LONGINT", "LP", "LT", "LTEQ", "LTLT", "LTLTEQ", "LTLTLT", 
                      "LTLTLTEQ", "LTMIGT", "MACROMODULE", "MATCHES", "MEDIUM", 
                      "MI", "MICL", "MIEQ", "MIGT", "MIGTGT", "MIINCDIR", 
                      "MIMI", "MO", "MODPORT", "MODULE", "MOEQ", "NAND", 
                      "NEGEDGE", "NETTYPE", "NEW", "NEXTTIME", "NMOS", "NOR", 
                      "NOSHOWCANCELLED", "NOT", "NOTIFONE", "NOTIFZERO", 
                      "NULL", "ONESTEP", "OPTION", "OR", "OUTPUT", "PACKAGE", 
                      "PACKED", "PARAMETER", "PATHPULSEDL", "PL", "PLCL", 
                      "PLEQ", "PLPL", "PMOS", "POSEDGE", "PRIMITIVE", "PRIORITY", 
                      "PROGRAM", "PROPERTY", "PROTECTED", "PULLDOWN", "PULLONE", 
                      "PULLUP", "PULLZERO", "PULSESTYLE_ONDETECT", "PULSESTYLE_ONEVENT", 
                      "PURE", "QM", "RAND", "RANDC", "RANDCASE", "RANDOMIZE", 
                      "RANDSEQUENCE", "RB", "RC", "RCMOS", "REAL", "REALTIME", 
                      "REF", "REG", "REJECT_ON", "RELEASE", "REPEAT", "RESTRICT", 
                      "RETURN", "RNMOS", "RP", "RPMOS", "RTRAN", "RTRANIFONE", 
                      "RTRANIFZERO", "S_ALWAYS", "S_EVENTUALLY", "S_NEXTTIME", 
                      "S_UNTIL", "S_UNTIL_WITH", "SAMPLE", "SC", "SCALARED", 
                      "SEQUENCE", "SHORTINT", "SHORTREAL", "SHOWCANCELLED", 
                      "SIGNED", "SL", "SLEQ", "SMALL", "SOFT", "SOLVE", 
                      "SPECIFY", "SPECPARAM", "STATIC", "STD", "STRING", 
                      "STRONG", "STRONGONE", "STRONGZERO", "STRUCT", "SUPER", 
                      "SUPPLYONE", "SUPPLYZERO", "SYNC_ACCEPT_ON", "SYNC_REJECT_ON", 
                      "TABLE", "TAGGED", "TASK", "THIS", "THROUGHOUT", "TI", 
                      "TIAM", "TICA", "TIME", "TIMEPRECISION", "TIMEUNIT", 
                      "TIVL", "TRAN", "TRANIFONE", "TRANIFZERO", "TRI", 
                      "TRIAND", "TRIONE", "TRIOR", "TRIREG", "TRIZERO", 
                      "TYPE", "TYPE_OPTION", "TYPEDEF", "UNION", "UNIQUE", 
                      "UNIQUEZERO", "UNSIGNED", "UNTIL", "UNTIL_WITH", "UNTYPED", 
                      "USE", "UWIRE", "VAR", "VECTORED", "VIRTUAL", "VL", 
                      "VLEQ", "VLEQGT", "VLMIGT", "VLVL", "VOID", "WAIT", 
                      "WAIT_ORDER", "WAND", "WEAK", "WEAKONE", "WEAKZERO", 
                      "WHILE", "WILDCARD", "WIRE", "WITH", "WITHIN", "WOR", 
                      "XNOR", "XOR", "BINARY_BASE", "COMMENT", "DECIMAL_BASE", 
                      "ESCAPED_IDENTIFIER", "EXPONENTIAL_NUMBER", "FIXED_POINT_NUMBER", 
                      "HEX_BASE", "OCTAL_BASE", "SIMPLE_IDENTIFIER", "STRING_LITERAL", 
                      "SYSTEM_TF_IDENTIFIER", "TIME_LITERAL", "UNBASED_UNSIZED_LITERAL", 
                      "UNSIGNED_NUMBER", "WHITE_SPACE", "ZERO_OR_ONE_X_OR_Z", 
                      "BINARY_VALUE", "X_OR_Z_UNDERSCORE", "HEX_VALUE", 
                      "FILE_PATH_SPEC", "OCTAL_VALUE", "EDGE_SYMBOL", "LEVEL_ONLY_SYMBOL", 
                      "OUTPUT_OR_LEVEL_SYMBOL", "BEGIN_KEYWORDS_DIRECTIVE", 
                      "CELLDEFINE_DIRECTIVE", "DEFAULT_NETTYPE_DIRECTIVE", 
                      "DEFINE_DIRECTIVE", "ELSE_DIRECTIVE", "ELSIF_DIRECTIVE", 
                      "END_KEYWORDS_DIRECTIVE", "ENDCELLDEFINE_DIRECTIVE", 
                      "ENDIF_DIRECTIVE", "FILE_DIRECTIVE", "IFDEF_DIRECTIVE", 
                      "IFNDEF_DIRECTIVE", "INCLUDE_DIRECTIVE", "LINE_DIRECTIVE", 
                      "LINE_DIRECTIVE_", "NOUNCONNECTED_DRIVE_DIRECTIVE", 
                      "PRAGMA_DIRECTIVE", "RESETALL_DIRECTIVE", "TIMESCALE_DIRECTIVE", 
                      "UNCONNECTED_DRIVE_DIRECTIVE", "UNDEF_DIRECTIVE", 
                      "UNDEFINEALL_DIRECTIVE", "MACRO_USAGE", "VERSION_SPECIFIER", 
                      "DEFAULT_NETTYPE_VALUE", "COMMENT_4", "MACRO_NAME", 
                      "WHITE_SPACE_6", "FILENAME", "MACRO_DELIMITER", "MACRO_ESC_NEWLINE", 
                      "MACRO_ESC_QUOTE", "MACRO_QUOTE", "MACRO_TEXT", "SOURCE_TEXT", 
                      "TIME_UNIT", "TIME_VALUE", "UNCONNECTED_DRIVE_VALUE", 
                      "MACRO_IDENTIFIER" ]

    RULE_source_text = 0
    RULE_compiler_directive = 1
    RULE_begin_keywords_directive = 2
    RULE_celldefine_directive = 3
    RULE_default_nettype_directive = 4
    RULE_default_nettype_value = 5
    RULE_else_directive = 6
    RULE_elsif_directive = 7
    RULE_end_keywords_directive = 8
    RULE_endcelldefine_directive = 9
    RULE_endif_directive = 10
    RULE_file_directive = 11
    RULE_filename = 12
    RULE_group_of_lines = 13
    RULE_identifier = 14
    RULE_ifdef_directive = 15
    RULE_ifndef_directive = 16
    RULE_include_directive = 17
    RULE_level = 18
    RULE_line_directive = 19
    RULE_line_directive_ = 20
    RULE_macro_delimiter = 21
    RULE_macro_esc_newline = 22
    RULE_macro_esc_quote = 23
    RULE_macro_identifier = 24
    RULE_macro_name = 25
    RULE_macro_quote = 26
    RULE_macro_text = 27
    RULE_macro_usage = 28
    RULE_nounconnected_drive_directive = 29
    RULE_number = 30
    RULE_pragma_directive = 31
    RULE_pragma_expression = 32
    RULE_pragma_keyword = 33
    RULE_pragma_name = 34
    RULE_pragma_value = 35
    RULE_resetall_directive = 36
    RULE_source_text_ = 37
    RULE_string_literal = 38
    RULE_text_macro_definition = 39
    RULE_text_macro_usage = 40
    RULE_time_precision = 41
    RULE_time_unit = 42
    RULE_timescale_directive = 43
    RULE_unconnected_drive_directive = 44
    RULE_unconnected_drive_value = 45
    RULE_undef_directive = 46
    RULE_undefineall_directive = 47
    RULE_version_specifier = 48

    ruleNames =  [ "source_text", "compiler_directive", "begin_keywords_directive", 
                   "celldefine_directive", "default_nettype_directive", 
                   "default_nettype_value", "else_directive", "elsif_directive", 
                   "end_keywords_directive", "endcelldefine_directive", 
                   "endif_directive", "file_directive", "filename", "group_of_lines", 
                   "identifier", "ifdef_directive", "ifndef_directive", 
                   "include_directive", "level", "line_directive", "line_directive_", 
                   "macro_delimiter", "macro_esc_newline", "macro_esc_quote", 
                   "macro_identifier", "macro_name", "macro_quote", "macro_text", 
                   "macro_usage", "nounconnected_drive_directive", "number", 
                   "pragma_directive", "pragma_expression", "pragma_keyword", 
                   "pragma_name", "pragma_value", "resetall_directive", 
                   "source_text_", "string_literal", "text_macro_definition", 
                   "text_macro_usage", "time_precision", "time_unit", "timescale_directive", 
                   "unconnected_drive_directive", "unconnected_drive_value", 
                   "undef_directive", "undefineall_directive", "version_specifier" ]

    EOF = Token.EOF
    ACCEPT_ON=1
    ALIAS=2
    ALWAYS=3
    ALWAYS_COMB=4
    ALWAYS_FF=5
    ALWAYS_LATCH=6
    AM=7
    AMAM=8
    AMAMAM=9
    AMEQ=10
    AND=11
    AP=12
    AS=13
    ASAS=14
    ASEQ=15
    ASGT=16
    ASSERT=17
    ASSIGN=18
    ASSUME=19
    AT=20
    ATAT=21
    AUTOMATIC=22
    BEFORE=23
    BEGIN=24
    BIND=25
    BINS=26
    BINSOF=27
    BIT=28
    BREAK=29
    BUF=30
    BUFIFONE=31
    BUFIFZERO=32
    BYTE=33
    CA=34
    CAEQ=35
    CASE=36
    CASEX=37
    CASEZ=38
    CATI=39
    CELL=40
    CHANDLE=41
    CHECKER=42
    CL=43
    CLASS=44
    CLCL=45
    CLEQ=46
    CLOCKING=47
    CLSL=48
    CMOS=49
    CO=50
    CONFIG=51
    CONST=52
    CONSTRAINT=53
    CONTEXT=54
    CONTINUE=55
    COVER=56
    COVERGROUP=57
    COVERPOINT=58
    CROSS=59
    DEASSIGN=60
    DEFAULT=61
    DEFPARAM=62
    DESIGN=63
    DISABLE=64
    DIST=65
    DL=66
    DLERROR=67
    DLFATAL=68
    DLFULLSKEW=69
    DLHOLD=70
    DLINFO=71
    DLNOCHANGE=72
    DLPERIOD=73
    DLRECOVERY=74
    DLRECREM=75
    DLREMOVAL=76
    DLROOT=77
    DLSETUP=78
    DLSETUPHOLD=79
    DLSKEW=80
    DLTIMESKEW=81
    DLUNIT=82
    DLWARNING=83
    DLWIDTH=84
    DO=85
    DQ=86
    DQDPIDQ=87
    DQDPIMICDQ=88
    DT=89
    DTAS=90
    EDGE=91
    ELSE=92
    EM=93
    EMEQ=94
    EMEQEQ=95
    EMEQQM=96
    END=97
    ENDCASE=98
    ENDCHECKER=99
    ENDCLASS=100
    ENDCLOCKING=101
    ENDCONFIG=102
    ENDFUNCTION=103
    ENDGENERATE=104
    ENDGROUP=105
    ENDINTERFACE=106
    ENDMODULE=107
    ENDPACKAGE=108
    ENDPRIMITIVE=109
    ENDPROGRAM=110
    ENDPROPERTY=111
    ENDSEQUENCE=112
    ENDSPECIFY=113
    ENDTABLE=114
    ENDTASK=115
    ENUM=116
    EQ=117
    EQEQ=118
    EQEQEQ=119
    EQEQQM=120
    EQGT=121
    EVENT=122
    EVENTUALLY=123
    EXPECT=124
    EXPORT=125
    EXTENDS=126
    EXTERN=127
    FINAL=128
    FIRST_MATCH=129
    FOR=130
    FORCE=131
    FOREACH=132
    FOREVER=133
    FORK=134
    FORKJOIN=135
    FUNCTION=136
    GA=137
    GENERATE=138
    GENVAR=139
    GLOBAL=140
    GT=141
    GTEQ=142
    GTGT=143
    GTGTEQ=144
    GTGTGT=145
    GTGTGTEQ=146
    HA=147
    HAEQHA=148
    HAHA=149
    HAMIHA=150
    HIGHZONE=151
    HIGHZZERO=152
    IF=153
    IFF=154
    IFNONE=155
    IGNORE_BINS=156
    ILLEGAL_BINS=157
    IMPLEMENTS=158
    IMPLIES=159
    IMPORT=160
    INCLUDE=161
    INITIAL=162
    INOUT=163
    INPUT=164
    INSIDE=165
    INSTANCE=166
    INT=167
    INTEGER=168
    INTERCONNECT=169
    INTERFACE=170
    INTERSECT=171
    JOIN=172
    JOIN_ANY=173
    JOIN_NONE=174
    LARGE=175
    LB=176
    LC=177
    LET=178
    LIBLIST=179
    LIBRARY=180
    LOCAL=181
    LOCALPARAM=182
    LOGIC=183
    LONGINT=184
    LP=185
    LT=186
    LTEQ=187
    LTLT=188
    LTLTEQ=189
    LTLTLT=190
    LTLTLTEQ=191
    LTMIGT=192
    MACROMODULE=193
    MATCHES=194
    MEDIUM=195
    MI=196
    MICL=197
    MIEQ=198
    MIGT=199
    MIGTGT=200
    MIINCDIR=201
    MIMI=202
    MO=203
    MODPORT=204
    MODULE=205
    MOEQ=206
    NAND=207
    NEGEDGE=208
    NETTYPE=209
    NEW=210
    NEXTTIME=211
    NMOS=212
    NOR=213
    NOSHOWCANCELLED=214
    NOT=215
    NOTIFONE=216
    NOTIFZERO=217
    NULL=218
    ONESTEP=219
    OPTION=220
    OR=221
    OUTPUT=222
    PACKAGE=223
    PACKED=224
    PARAMETER=225
    PATHPULSEDL=226
    PL=227
    PLCL=228
    PLEQ=229
    PLPL=230
    PMOS=231
    POSEDGE=232
    PRIMITIVE=233
    PRIORITY=234
    PROGRAM=235
    PROPERTY=236
    PROTECTED=237
    PULLDOWN=238
    PULLONE=239
    PULLUP=240
    PULLZERO=241
    PULSESTYLE_ONDETECT=242
    PULSESTYLE_ONEVENT=243
    PURE=244
    QM=245
    RAND=246
    RANDC=247
    RANDCASE=248
    RANDOMIZE=249
    RANDSEQUENCE=250
    RB=251
    RC=252
    RCMOS=253
    REAL=254
    REALTIME=255
    REF=256
    REG=257
    REJECT_ON=258
    RELEASE=259
    REPEAT=260
    RESTRICT=261
    RETURN=262
    RNMOS=263
    RP=264
    RPMOS=265
    RTRAN=266
    RTRANIFONE=267
    RTRANIFZERO=268
    S_ALWAYS=269
    S_EVENTUALLY=270
    S_NEXTTIME=271
    S_UNTIL=272
    S_UNTIL_WITH=273
    SAMPLE=274
    SC=275
    SCALARED=276
    SEQUENCE=277
    SHORTINT=278
    SHORTREAL=279
    SHOWCANCELLED=280
    SIGNED=281
    SL=282
    SLEQ=283
    SMALL=284
    SOFT=285
    SOLVE=286
    SPECIFY=287
    SPECPARAM=288
    STATIC=289
    STD=290
    STRING=291
    STRONG=292
    STRONGONE=293
    STRONGZERO=294
    STRUCT=295
    SUPER=296
    SUPPLYONE=297
    SUPPLYZERO=298
    SYNC_ACCEPT_ON=299
    SYNC_REJECT_ON=300
    TABLE=301
    TAGGED=302
    TASK=303
    THIS=304
    THROUGHOUT=305
    TI=306
    TIAM=307
    TICA=308
    TIME=309
    TIMEPRECISION=310
    TIMEUNIT=311
    TIVL=312
    TRAN=313
    TRANIFONE=314
    TRANIFZERO=315
    TRI=316
    TRIAND=317
    TRIONE=318
    TRIOR=319
    TRIREG=320
    TRIZERO=321
    TYPE=322
    TYPE_OPTION=323
    TYPEDEF=324
    UNION=325
    UNIQUE=326
    UNIQUEZERO=327
    UNSIGNED=328
    UNTIL=329
    UNTIL_WITH=330
    UNTYPED=331
    USE=332
    UWIRE=333
    VAR=334
    VECTORED=335
    VIRTUAL=336
    VL=337
    VLEQ=338
    VLEQGT=339
    VLMIGT=340
    VLVL=341
    VOID=342
    WAIT=343
    WAIT_ORDER=344
    WAND=345
    WEAK=346
    WEAKONE=347
    WEAKZERO=348
    WHILE=349
    WILDCARD=350
    WIRE=351
    WITH=352
    WITHIN=353
    WOR=354
    XNOR=355
    XOR=356
    BINARY_BASE=357
    COMMENT=358
    DECIMAL_BASE=359
    ESCAPED_IDENTIFIER=360
    EXPONENTIAL_NUMBER=361
    FIXED_POINT_NUMBER=362
    HEX_BASE=363
    OCTAL_BASE=364
    SIMPLE_IDENTIFIER=365
    STRING_LITERAL=366
    SYSTEM_TF_IDENTIFIER=367
    TIME_LITERAL=368
    UNBASED_UNSIZED_LITERAL=369
    UNSIGNED_NUMBER=370
    WHITE_SPACE=371
    ZERO_OR_ONE_X_OR_Z=372
    BINARY_VALUE=373
    X_OR_Z_UNDERSCORE=374
    HEX_VALUE=375
    FILE_PATH_SPEC=376
    OCTAL_VALUE=377
    EDGE_SYMBOL=378
    LEVEL_ONLY_SYMBOL=379
    OUTPUT_OR_LEVEL_SYMBOL=380
    BEGIN_KEYWORDS_DIRECTIVE=381
    CELLDEFINE_DIRECTIVE=382
    DEFAULT_NETTYPE_DIRECTIVE=383
    DEFINE_DIRECTIVE=384
    ELSE_DIRECTIVE=385
    ELSIF_DIRECTIVE=386
    END_KEYWORDS_DIRECTIVE=387
    ENDCELLDEFINE_DIRECTIVE=388
    ENDIF_DIRECTIVE=389
    FILE_DIRECTIVE=390
    IFDEF_DIRECTIVE=391
    IFNDEF_DIRECTIVE=392
    INCLUDE_DIRECTIVE=393
    LINE_DIRECTIVE=394
    LINE_DIRECTIVE_=395
    NOUNCONNECTED_DRIVE_DIRECTIVE=396
    PRAGMA_DIRECTIVE=397
    RESETALL_DIRECTIVE=398
    TIMESCALE_DIRECTIVE=399
    UNCONNECTED_DRIVE_DIRECTIVE=400
    UNDEF_DIRECTIVE=401
    UNDEFINEALL_DIRECTIVE=402
    MACRO_USAGE=403
    VERSION_SPECIFIER=404
    DEFAULT_NETTYPE_VALUE=405
    COMMENT_4=406
    MACRO_NAME=407
    WHITE_SPACE_6=408
    FILENAME=409
    MACRO_DELIMITER=410
    MACRO_ESC_NEWLINE=411
    MACRO_ESC_QUOTE=412
    MACRO_QUOTE=413
    MACRO_TEXT=414
    SOURCE_TEXT=415
    TIME_UNIT=416
    TIME_VALUE=417
    UNCONNECTED_DRIVE_VALUE=418
    MACRO_IDENTIFIER=419

    def __init__(self, input:TokenStream, output:TextIO = sys.stdout):
        super().__init__(input, output)
        self.checkVersion("4.11.1")
        self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache)
        self._predicates = None




    class Source_textContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def compiler_directive(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Compiler_directiveContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Compiler_directiveContext,i)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_source_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSource_text" ):
                listener.enterSource_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSource_text" ):
                listener.exitSource_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSource_text" ):
                return visitor.visitSource_text(self)
            else:
                return visitor.visitChildren(self)




    def source_text(self):

        localctx = SystemVerilogPreParser.Source_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 0, self.RULE_source_text)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 101
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==137:
                self.state = 98
                self.compiler_directive()
                self.state = 103
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Compiler_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def begin_keywords_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Begin_keywords_directiveContext,0)


        def celldefine_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Celldefine_directiveContext,0)


        def default_nettype_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Default_nettype_directiveContext,0)


        def end_keywords_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.End_keywords_directiveContext,0)


        def endcelldefine_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Endcelldefine_directiveContext,0)


        def file_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.File_directiveContext,0)


        def ifdef_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Ifdef_directiveContext,0)


        def ifndef_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Ifndef_directiveContext,0)


        def include_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Include_directiveContext,0)


        def line_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Line_directiveContext,0)


        def line_directive_(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Line_directive_Context,0)


        def nounconnected_drive_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Nounconnected_drive_directiveContext,0)


        def pragma_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Pragma_directiveContext,0)


        def resetall_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Resetall_directiveContext,0)


        def text_macro_definition(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Text_macro_definitionContext,0)


        def text_macro_usage(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Text_macro_usageContext,0)


        def timescale_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Timescale_directiveContext,0)


        def unconnected_drive_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Unconnected_drive_directiveContext,0)


        def undef_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Undef_directiveContext,0)


        def undefineall_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Undefineall_directiveContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_compiler_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCompiler_directive" ):
                listener.enterCompiler_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCompiler_directive" ):
                listener.exitCompiler_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCompiler_directive" ):
                return visitor.visitCompiler_directive(self)
            else:
                return visitor.visitChildren(self)




    def compiler_directive(self):

        localctx = SystemVerilogPreParser.Compiler_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 2, self.RULE_compiler_directive)
        try:
            self.state = 124
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,1,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 104
                self.begin_keywords_directive()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 105
                self.celldefine_directive()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 106
                self.default_nettype_directive()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 107
                self.end_keywords_directive()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 108
                self.endcelldefine_directive()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 109
                self.file_directive()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 110
                self.ifdef_directive()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 111
                self.ifndef_directive()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 112
                self.include_directive()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 113
                self.line_directive()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 114
                self.line_directive_()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 115
                self.nounconnected_drive_directive()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 116
                self.pragma_directive()
                pass

            elif la_ == 14:
                self.enterOuterAlt(localctx, 14)
                self.state = 117
                self.resetall_directive()
                pass

            elif la_ == 15:
                self.enterOuterAlt(localctx, 15)
                self.state = 118
                self.text_macro_definition()
                pass

            elif la_ == 16:
                self.enterOuterAlt(localctx, 16)
                self.state = 119
                self.text_macro_usage()
                pass

            elif la_ == 17:
                self.enterOuterAlt(localctx, 17)
                self.state = 120
                self.timescale_directive()
                pass

            elif la_ == 18:
                self.enterOuterAlt(localctx, 18)
                self.state = 121
                self.unconnected_drive_directive()
                pass

            elif la_ == 19:
                self.enterOuterAlt(localctx, 19)
                self.state = 122
                self.undef_directive()
                pass

            elif la_ == 20:
                self.enterOuterAlt(localctx, 20)
                self.state = 123
                self.undefineall_directive()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Begin_keywords_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def BEGIN_KEYWORDS_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.BEGIN_KEYWORDS_DIRECTIVE, 0)

        def DQ(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogPreParser.DQ)
            else:
                return self.getToken(SystemVerilogPreParser.DQ, i)

        def version_specifier(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Version_specifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_begin_keywords_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBegin_keywords_directive" ):
                listener.enterBegin_keywords_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBegin_keywords_directive" ):
                listener.exitBegin_keywords_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBegin_keywords_directive" ):
                return visitor.visitBegin_keywords_directive(self)
            else:
                return visitor.visitChildren(self)




    def begin_keywords_directive(self):

        localctx = SystemVerilogPreParser.Begin_keywords_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 4, self.RULE_begin_keywords_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 126
            self.match(SystemVerilogPreParser.GA)
            self.state = 127
            self.match(SystemVerilogPreParser.BEGIN_KEYWORDS_DIRECTIVE)
            self.state = 128
            self.match(SystemVerilogPreParser.DQ)
            self.state = 129
            self.version_specifier()
            self.state = 130
            self.match(SystemVerilogPreParser.DQ)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Celldefine_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def CELLDEFINE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.CELLDEFINE_DIRECTIVE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_celldefine_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCelldefine_directive" ):
                listener.enterCelldefine_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCelldefine_directive" ):
                listener.exitCelldefine_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCelldefine_directive" ):
                return visitor.visitCelldefine_directive(self)
            else:
                return visitor.visitChildren(self)




    def celldefine_directive(self):

        localctx = SystemVerilogPreParser.Celldefine_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 6, self.RULE_celldefine_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 132
            self.match(SystemVerilogPreParser.GA)
            self.state = 133
            self.match(SystemVerilogPreParser.CELLDEFINE_DIRECTIVE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Default_nettype_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def DEFAULT_NETTYPE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.DEFAULT_NETTYPE_DIRECTIVE, 0)

        def default_nettype_value(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Default_nettype_valueContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_default_nettype_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefault_nettype_directive" ):
                listener.enterDefault_nettype_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefault_nettype_directive" ):
                listener.exitDefault_nettype_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefault_nettype_directive" ):
                return visitor.visitDefault_nettype_directive(self)
            else:
                return visitor.visitChildren(self)




    def default_nettype_directive(self):

        localctx = SystemVerilogPreParser.Default_nettype_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 8, self.RULE_default_nettype_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 135
            self.match(SystemVerilogPreParser.GA)
            self.state = 136
            self.match(SystemVerilogPreParser.DEFAULT_NETTYPE_DIRECTIVE)
            self.state = 137
            self.default_nettype_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Default_nettype_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DEFAULT_NETTYPE_VALUE(self):
            return self.getToken(SystemVerilogPreParser.DEFAULT_NETTYPE_VALUE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_default_nettype_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefault_nettype_value" ):
                listener.enterDefault_nettype_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefault_nettype_value" ):
                listener.exitDefault_nettype_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefault_nettype_value" ):
                return visitor.visitDefault_nettype_value(self)
            else:
                return visitor.visitChildren(self)




    def default_nettype_value(self):

        localctx = SystemVerilogPreParser.Default_nettype_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 10, self.RULE_default_nettype_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 139
            self.match(SystemVerilogPreParser.DEFAULT_NETTYPE_VALUE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Else_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def ELSE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.ELSE_DIRECTIVE, 0)

        def group_of_lines(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Group_of_linesContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_else_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterElse_directive" ):
                listener.enterElse_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitElse_directive" ):
                listener.exitElse_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitElse_directive" ):
                return visitor.visitElse_directive(self)
            else:
                return visitor.visitChildren(self)




    def else_directive(self):

        localctx = SystemVerilogPreParser.Else_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 12, self.RULE_else_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 141
            self.match(SystemVerilogPreParser.GA)
            self.state = 142
            self.match(SystemVerilogPreParser.ELSE_DIRECTIVE)
            self.state = 143
            self.group_of_lines()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Elsif_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def ELSIF_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.ELSIF_DIRECTIVE, 0)

        def macro_identifier(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Macro_identifierContext,0)


        def group_of_lines(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Group_of_linesContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_elsif_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterElsif_directive" ):
                listener.enterElsif_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitElsif_directive" ):
                listener.exitElsif_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitElsif_directive" ):
                return visitor.visitElsif_directive(self)
            else:
                return visitor.visitChildren(self)




    def elsif_directive(self):

        localctx = SystemVerilogPreParser.Elsif_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 14, self.RULE_elsif_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 145
            self.match(SystemVerilogPreParser.GA)
            self.state = 146
            self.match(SystemVerilogPreParser.ELSIF_DIRECTIVE)
            self.state = 147
            self.macro_identifier()
            self.state = 148
            self.group_of_lines()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class End_keywords_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def END_KEYWORDS_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.END_KEYWORDS_DIRECTIVE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_end_keywords_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnd_keywords_directive" ):
                listener.enterEnd_keywords_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnd_keywords_directive" ):
                listener.exitEnd_keywords_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnd_keywords_directive" ):
                return visitor.visitEnd_keywords_directive(self)
            else:
                return visitor.visitChildren(self)




    def end_keywords_directive(self):

        localctx = SystemVerilogPreParser.End_keywords_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 16, self.RULE_end_keywords_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 150
            self.match(SystemVerilogPreParser.GA)
            self.state = 151
            self.match(SystemVerilogPreParser.END_KEYWORDS_DIRECTIVE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Endcelldefine_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def ENDCELLDEFINE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.ENDCELLDEFINE_DIRECTIVE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_endcelldefine_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEndcelldefine_directive" ):
                listener.enterEndcelldefine_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEndcelldefine_directive" ):
                listener.exitEndcelldefine_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEndcelldefine_directive" ):
                return visitor.visitEndcelldefine_directive(self)
            else:
                return visitor.visitChildren(self)




    def endcelldefine_directive(self):

        localctx = SystemVerilogPreParser.Endcelldefine_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 18, self.RULE_endcelldefine_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 153
            self.match(SystemVerilogPreParser.GA)
            self.state = 154
            self.match(SystemVerilogPreParser.ENDCELLDEFINE_DIRECTIVE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Endif_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def ENDIF_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.ENDIF_DIRECTIVE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_endif_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEndif_directive" ):
                listener.enterEndif_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEndif_directive" ):
                listener.exitEndif_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEndif_directive" ):
                return visitor.visitEndif_directive(self)
            else:
                return visitor.visitChildren(self)




    def endif_directive(self):

        localctx = SystemVerilogPreParser.Endif_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 20, self.RULE_endif_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 156
            self.match(SystemVerilogPreParser.GA)
            self.state = 157
            self.match(SystemVerilogPreParser.ENDIF_DIRECTIVE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class File_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def FILE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.FILE_DIRECTIVE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_file_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_directive" ):
                listener.enterFile_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_directive" ):
                listener.exitFile_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_directive" ):
                return visitor.visitFile_directive(self)
            else:
                return visitor.visitChildren(self)




    def file_directive(self):

        localctx = SystemVerilogPreParser.File_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 22, self.RULE_file_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 159
            self.match(SystemVerilogPreParser.GA)
            self.state = 160
            self.match(SystemVerilogPreParser.FILE_DIRECTIVE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class FilenameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FILENAME(self):
            return self.getToken(SystemVerilogPreParser.FILENAME, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_filename

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFilename" ):
                listener.enterFilename(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFilename" ):
                listener.exitFilename(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFilename" ):
                return visitor.visitFilename(self)
            else:
                return visitor.visitChildren(self)




    def filename(self):

        localctx = SystemVerilogPreParser.FilenameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 24, self.RULE_filename)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 162
            self.match(SystemVerilogPreParser.FILENAME)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Group_of_linesContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def source_text_(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Source_text_Context)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Source_text_Context,i)


        def compiler_directive(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Compiler_directiveContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Compiler_directiveContext,i)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_group_of_lines

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGroup_of_lines" ):
                listener.enterGroup_of_lines(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGroup_of_lines" ):
                listener.exitGroup_of_lines(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGroup_of_lines" ):
                return visitor.visitGroup_of_lines(self)
            else:
                return visitor.visitChildren(self)




    def group_of_lines(self):

        localctx = SystemVerilogPreParser.Group_of_linesContext(self, self._ctx, self.state)
        self.enterRule(localctx, 26, self.RULE_group_of_lines)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 168
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,3,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 166
                    self._errHandler.sync(self)
                    token = self._input.LA(1)
                    if token in [415]:
                        self.state = 164
                        self.source_text_()
                        pass
                    elif token in [137]:
                        self.state = 165
                        self.compiler_directive()
                        pass
                    else:
                        raise NoViableAltException(self)
             
                self.state = 170
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,3,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class IdentifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SIMPLE_IDENTIFIER(self):
            return self.getToken(SystemVerilogPreParser.SIMPLE_IDENTIFIER, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIdentifier" ):
                listener.enterIdentifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIdentifier" ):
                listener.exitIdentifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIdentifier" ):
                return visitor.visitIdentifier(self)
            else:
                return visitor.visitChildren(self)




    def identifier(self):

        localctx = SystemVerilogPreParser.IdentifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 28, self.RULE_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 171
            self.match(SystemVerilogPreParser.SIMPLE_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ifdef_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def IFDEF_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.IFDEF_DIRECTIVE, 0)

        def macro_identifier(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Macro_identifierContext,0)


        def group_of_lines(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Group_of_linesContext,0)


        def endif_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Endif_directiveContext,0)


        def elsif_directive(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Elsif_directiveContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Elsif_directiveContext,i)


        def else_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Else_directiveContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_ifdef_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIfdef_directive" ):
                listener.enterIfdef_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIfdef_directive" ):
                listener.exitIfdef_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIfdef_directive" ):
                return visitor.visitIfdef_directive(self)
            else:
                return visitor.visitChildren(self)




    def ifdef_directive(self):

        localctx = SystemVerilogPreParser.Ifdef_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 30, self.RULE_ifdef_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 173
            self.match(SystemVerilogPreParser.GA)
            self.state = 174
            self.match(SystemVerilogPreParser.IFDEF_DIRECTIVE)
            self.state = 175
            self.macro_identifier()
            self.state = 176
            self.group_of_lines()
            self.state = 180
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,4,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 177
                    self.elsif_directive() 
                self.state = 182
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,4,self._ctx)

            self.state = 184
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,5,self._ctx)
            if la_ == 1:
                self.state = 183
                self.else_directive()


            self.state = 186
            self.endif_directive()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ifndef_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def IFNDEF_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.IFNDEF_DIRECTIVE, 0)

        def macro_identifier(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Macro_identifierContext,0)


        def group_of_lines(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Group_of_linesContext,0)


        def endif_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Endif_directiveContext,0)


        def elsif_directive(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Elsif_directiveContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Elsif_directiveContext,i)


        def else_directive(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Else_directiveContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_ifndef_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIfndef_directive" ):
                listener.enterIfndef_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIfndef_directive" ):
                listener.exitIfndef_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIfndef_directive" ):
                return visitor.visitIfndef_directive(self)
            else:
                return visitor.visitChildren(self)




    def ifndef_directive(self):

        localctx = SystemVerilogPreParser.Ifndef_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 32, self.RULE_ifndef_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 188
            self.match(SystemVerilogPreParser.GA)
            self.state = 189
            self.match(SystemVerilogPreParser.IFNDEF_DIRECTIVE)
            self.state = 190
            self.macro_identifier()
            self.state = 191
            self.group_of_lines()
            self.state = 195
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,6,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 192
                    self.elsif_directive() 
                self.state = 197
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,6,self._ctx)

            self.state = 199
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,7,self._ctx)
            if la_ == 1:
                self.state = 198
                self.else_directive()


            self.state = 201
            self.endif_directive()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Include_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def INCLUDE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.INCLUDE_DIRECTIVE, 0)

        def DQ(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogPreParser.DQ)
            else:
                return self.getToken(SystemVerilogPreParser.DQ, i)

        def filename(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.FilenameContext,0)


        def LT(self):
            return self.getToken(SystemVerilogPreParser.LT, 0)

        def GT(self):
            return self.getToken(SystemVerilogPreParser.GT, 0)

        def text_macro_usage(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Text_macro_usageContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_include_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInclude_directive" ):
                listener.enterInclude_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInclude_directive" ):
                listener.exitInclude_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInclude_directive" ):
                return visitor.visitInclude_directive(self)
            else:
                return visitor.visitChildren(self)




    def include_directive(self):

        localctx = SystemVerilogPreParser.Include_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 34, self.RULE_include_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 203
            self.match(SystemVerilogPreParser.GA)
            self.state = 204
            self.match(SystemVerilogPreParser.INCLUDE_DIRECTIVE)
            self.state = 214
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [86]:
                self.state = 205
                self.match(SystemVerilogPreParser.DQ)
                self.state = 206
                self.filename()
                self.state = 207
                self.match(SystemVerilogPreParser.DQ)
                pass
            elif token in [186]:
                self.state = 209
                self.match(SystemVerilogPreParser.LT)
                self.state = 210
                self.filename()
                self.state = 211
                self.match(SystemVerilogPreParser.GT)
                pass
            elif token in [137]:
                self.state = 213
                self.text_macro_usage()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class LevelContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def UNSIGNED_NUMBER(self):
            return self.getToken(SystemVerilogPreParser.UNSIGNED_NUMBER, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_level

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLevel" ):
                listener.enterLevel(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLevel" ):
                listener.exitLevel(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLevel" ):
                return visitor.visitLevel(self)
            else:
                return visitor.visitChildren(self)




    def level(self):

        localctx = SystemVerilogPreParser.LevelContext(self, self._ctx, self.state)
        self.enterRule(localctx, 36, self.RULE_level)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 216
            self.match(SystemVerilogPreParser.UNSIGNED_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Line_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def LINE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.LINE_DIRECTIVE, 0)

        def number(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.NumberContext,0)


        def DQ(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogPreParser.DQ)
            else:
                return self.getToken(SystemVerilogPreParser.DQ, i)

        def filename(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.FilenameContext,0)


        def level(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.LevelContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_line_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLine_directive" ):
                listener.enterLine_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLine_directive" ):
                listener.exitLine_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLine_directive" ):
                return visitor.visitLine_directive(self)
            else:
                return visitor.visitChildren(self)




    def line_directive(self):

        localctx = SystemVerilogPreParser.Line_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 38, self.RULE_line_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 218
            self.match(SystemVerilogPreParser.GA)
            self.state = 219
            self.match(SystemVerilogPreParser.LINE_DIRECTIVE)
            self.state = 220
            self.number()
            self.state = 221
            self.match(SystemVerilogPreParser.DQ)
            self.state = 222
            self.filename()
            self.state = 223
            self.match(SystemVerilogPreParser.DQ)
            self.state = 224
            self.level()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Line_directive_Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def LINE_DIRECTIVE_(self):
            return self.getToken(SystemVerilogPreParser.LINE_DIRECTIVE_, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_line_directive_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLine_directive_" ):
                listener.enterLine_directive_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLine_directive_" ):
                listener.exitLine_directive_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLine_directive_" ):
                return visitor.visitLine_directive_(self)
            else:
                return visitor.visitChildren(self)




    def line_directive_(self):

        localctx = SystemVerilogPreParser.Line_directive_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 40, self.RULE_line_directive_)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 226
            self.match(SystemVerilogPreParser.GA)
            self.state = 227
            self.match(SystemVerilogPreParser.LINE_DIRECTIVE_)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Macro_delimiterContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MACRO_DELIMITER(self):
            return self.getToken(SystemVerilogPreParser.MACRO_DELIMITER, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_macro_delimiter

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMacro_delimiter" ):
                listener.enterMacro_delimiter(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMacro_delimiter" ):
                listener.exitMacro_delimiter(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMacro_delimiter" ):
                return visitor.visitMacro_delimiter(self)
            else:
                return visitor.visitChildren(self)




    def macro_delimiter(self):

        localctx = SystemVerilogPreParser.Macro_delimiterContext(self, self._ctx, self.state)
        self.enterRule(localctx, 42, self.RULE_macro_delimiter)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 229
            self.match(SystemVerilogPreParser.MACRO_DELIMITER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Macro_esc_newlineContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MACRO_ESC_NEWLINE(self):
            return self.getToken(SystemVerilogPreParser.MACRO_ESC_NEWLINE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_macro_esc_newline

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMacro_esc_newline" ):
                listener.enterMacro_esc_newline(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMacro_esc_newline" ):
                listener.exitMacro_esc_newline(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMacro_esc_newline" ):
                return visitor.visitMacro_esc_newline(self)
            else:
                return visitor.visitChildren(self)




    def macro_esc_newline(self):

        localctx = SystemVerilogPreParser.Macro_esc_newlineContext(self, self._ctx, self.state)
        self.enterRule(localctx, 44, self.RULE_macro_esc_newline)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 231
            self.match(SystemVerilogPreParser.MACRO_ESC_NEWLINE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Macro_esc_quoteContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MACRO_ESC_QUOTE(self):
            return self.getToken(SystemVerilogPreParser.MACRO_ESC_QUOTE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_macro_esc_quote

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMacro_esc_quote" ):
                listener.enterMacro_esc_quote(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMacro_esc_quote" ):
                listener.exitMacro_esc_quote(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMacro_esc_quote" ):
                return visitor.visitMacro_esc_quote(self)
            else:
                return visitor.visitChildren(self)




    def macro_esc_quote(self):

        localctx = SystemVerilogPreParser.Macro_esc_quoteContext(self, self._ctx, self.state)
        self.enterRule(localctx, 46, self.RULE_macro_esc_quote)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 233
            self.match(SystemVerilogPreParser.MACRO_ESC_QUOTE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Macro_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MACRO_IDENTIFIER(self):
            return self.getToken(SystemVerilogPreParser.MACRO_IDENTIFIER, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_macro_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMacro_identifier" ):
                listener.enterMacro_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMacro_identifier" ):
                listener.exitMacro_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMacro_identifier" ):
                return visitor.visitMacro_identifier(self)
            else:
                return visitor.visitChildren(self)




    def macro_identifier(self):

        localctx = SystemVerilogPreParser.Macro_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 48, self.RULE_macro_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 235
            self.match(SystemVerilogPreParser.MACRO_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Macro_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MACRO_NAME(self):
            return self.getToken(SystemVerilogPreParser.MACRO_NAME, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_macro_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMacro_name" ):
                listener.enterMacro_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMacro_name" ):
                listener.exitMacro_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMacro_name" ):
                return visitor.visitMacro_name(self)
            else:
                return visitor.visitChildren(self)




    def macro_name(self):

        localctx = SystemVerilogPreParser.Macro_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 50, self.RULE_macro_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 237
            self.match(SystemVerilogPreParser.MACRO_NAME)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Macro_quoteContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MACRO_QUOTE(self):
            return self.getToken(SystemVerilogPreParser.MACRO_QUOTE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_macro_quote

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMacro_quote" ):
                listener.enterMacro_quote(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMacro_quote" ):
                listener.exitMacro_quote(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMacro_quote" ):
                return visitor.visitMacro_quote(self)
            else:
                return visitor.visitChildren(self)




    def macro_quote(self):

        localctx = SystemVerilogPreParser.Macro_quoteContext(self, self._ctx, self.state)
        self.enterRule(localctx, 52, self.RULE_macro_quote)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 239
            self.match(SystemVerilogPreParser.MACRO_QUOTE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Macro_textContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MACRO_TEXT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogPreParser.MACRO_TEXT)
            else:
                return self.getToken(SystemVerilogPreParser.MACRO_TEXT, i)

        def macro_delimiter(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Macro_delimiterContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Macro_delimiterContext,i)


        def macro_esc_newline(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Macro_esc_newlineContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Macro_esc_newlineContext,i)


        def macro_esc_quote(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Macro_esc_quoteContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Macro_esc_quoteContext,i)


        def macro_quote(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Macro_quoteContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Macro_quoteContext,i)


        def string_literal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.String_literalContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.String_literalContext,i)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_macro_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMacro_text" ):
                listener.enterMacro_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMacro_text" ):
                listener.exitMacro_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMacro_text" ):
                return visitor.visitMacro_text(self)
            else:
                return visitor.visitChildren(self)




    def macro_text(self):

        localctx = SystemVerilogPreParser.Macro_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 54, self.RULE_macro_text)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 249
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la - 366)) & ~0x3f) == 0 and ((1 << (_la - 366)) & 545357767376897) != 0:
                self.state = 247
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [414]:
                    self.state = 241
                    self.match(SystemVerilogPreParser.MACRO_TEXT)
                    pass
                elif token in [410]:
                    self.state = 242
                    self.macro_delimiter()
                    pass
                elif token in [411]:
                    self.state = 243
                    self.macro_esc_newline()
                    pass
                elif token in [412]:
                    self.state = 244
                    self.macro_esc_quote()
                    pass
                elif token in [413]:
                    self.state = 245
                    self.macro_quote()
                    pass
                elif token in [366]:
                    self.state = 246
                    self.string_literal()
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 251
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Macro_usageContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MACRO_USAGE(self):
            return self.getToken(SystemVerilogPreParser.MACRO_USAGE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_macro_usage

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMacro_usage" ):
                listener.enterMacro_usage(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMacro_usage" ):
                listener.exitMacro_usage(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMacro_usage" ):
                return visitor.visitMacro_usage(self)
            else:
                return visitor.visitChildren(self)




    def macro_usage(self):

        localctx = SystemVerilogPreParser.Macro_usageContext(self, self._ctx, self.state)
        self.enterRule(localctx, 56, self.RULE_macro_usage)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 252
            self.match(SystemVerilogPreParser.MACRO_USAGE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Nounconnected_drive_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def NOUNCONNECTED_DRIVE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.NOUNCONNECTED_DRIVE_DIRECTIVE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_nounconnected_drive_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNounconnected_drive_directive" ):
                listener.enterNounconnected_drive_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNounconnected_drive_directive" ):
                listener.exitNounconnected_drive_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNounconnected_drive_directive" ):
                return visitor.visitNounconnected_drive_directive(self)
            else:
                return visitor.visitChildren(self)




    def nounconnected_drive_directive(self):

        localctx = SystemVerilogPreParser.Nounconnected_drive_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 58, self.RULE_nounconnected_drive_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 254
            self.match(SystemVerilogPreParser.GA)
            self.state = 255
            self.match(SystemVerilogPreParser.NOUNCONNECTED_DRIVE_DIRECTIVE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class NumberContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def UNSIGNED_NUMBER(self):
            return self.getToken(SystemVerilogPreParser.UNSIGNED_NUMBER, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNumber" ):
                listener.enterNumber(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNumber" ):
                listener.exitNumber(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNumber" ):
                return visitor.visitNumber(self)
            else:
                return visitor.visitChildren(self)




    def number(self):

        localctx = SystemVerilogPreParser.NumberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 60, self.RULE_number)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 257
            self.match(SystemVerilogPreParser.UNSIGNED_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pragma_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def PRAGMA_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.PRAGMA_DIRECTIVE, 0)

        def pragma_name(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Pragma_nameContext,0)


        def pragma_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Pragma_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Pragma_expressionContext,i)


        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogPreParser.CO)
            else:
                return self.getToken(SystemVerilogPreParser.CO, i)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_pragma_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPragma_directive" ):
                listener.enterPragma_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPragma_directive" ):
                listener.exitPragma_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPragma_directive" ):
                return visitor.visitPragma_directive(self)
            else:
                return visitor.visitChildren(self)




    def pragma_directive(self):

        localctx = SystemVerilogPreParser.Pragma_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 62, self.RULE_pragma_directive)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 259
            self.match(SystemVerilogPreParser.GA)
            self.state = 260
            self.match(SystemVerilogPreParser.PRAGMA_DIRECTIVE)
            self.state = 261
            self.pragma_name()
            self.state = 270
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==185 or (((_la - 365)) & ~0x3f) == 0 and ((1 << (_la - 365)) & 35) != 0:
                self.state = 262
                self.pragma_expression()
                self.state = 267
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==50:
                    self.state = 263
                    self.match(SystemVerilogPreParser.CO)
                    self.state = 264
                    self.pragma_expression()
                    self.state = 269
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pragma_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pragma_value(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Pragma_valueContext,0)


        def pragma_keyword(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Pragma_keywordContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogPreParser.EQ, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_pragma_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPragma_expression" ):
                listener.enterPragma_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPragma_expression" ):
                listener.exitPragma_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPragma_expression" ):
                return visitor.visitPragma_expression(self)
            else:
                return visitor.visitChildren(self)




    def pragma_expression(self):

        localctx = SystemVerilogPreParser.Pragma_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 64, self.RULE_pragma_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 275
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,13,self._ctx)
            if la_ == 1:
                self.state = 272
                self.pragma_keyword()
                self.state = 273
                self.match(SystemVerilogPreParser.EQ)


            self.state = 277
            self.pragma_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pragma_keywordContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SIMPLE_IDENTIFIER(self):
            return self.getToken(SystemVerilogPreParser.SIMPLE_IDENTIFIER, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_pragma_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPragma_keyword" ):
                listener.enterPragma_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPragma_keyword" ):
                listener.exitPragma_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPragma_keyword" ):
                return visitor.visitPragma_keyword(self)
            else:
                return visitor.visitChildren(self)




    def pragma_keyword(self):

        localctx = SystemVerilogPreParser.Pragma_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 66, self.RULE_pragma_keyword)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 279
            self.match(SystemVerilogPreParser.SIMPLE_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pragma_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SIMPLE_IDENTIFIER(self):
            return self.getToken(SystemVerilogPreParser.SIMPLE_IDENTIFIER, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_pragma_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPragma_name" ):
                listener.enterPragma_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPragma_name" ):
                listener.exitPragma_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPragma_name" ):
                return visitor.visitPragma_name(self)
            else:
                return visitor.visitChildren(self)




    def pragma_name(self):

        localctx = SystemVerilogPreParser.Pragma_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 68, self.RULE_pragma_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 281
            self.match(SystemVerilogPreParser.SIMPLE_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pragma_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogPreParser.LP, 0)

        def pragma_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogPreParser.Pragma_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogPreParser.Pragma_expressionContext,i)


        def RP(self):
            return self.getToken(SystemVerilogPreParser.RP, 0)

        def CO(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogPreParser.CO)
            else:
                return self.getToken(SystemVerilogPreParser.CO, i)

        def number(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.NumberContext,0)


        def string_literal(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.String_literalContext,0)


        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_pragma_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPragma_value" ):
                listener.enterPragma_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPragma_value" ):
                listener.exitPragma_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPragma_value" ):
                return visitor.visitPragma_value(self)
            else:
                return visitor.visitChildren(self)




    def pragma_value(self):

        localctx = SystemVerilogPreParser.Pragma_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 70, self.RULE_pragma_value)
        self._la = 0 # Token type
        try:
            self.state = 297
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [185]:
                self.enterOuterAlt(localctx, 1)
                self.state = 283
                self.match(SystemVerilogPreParser.LP)
                self.state = 284
                self.pragma_expression()
                self.state = 289
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==50:
                    self.state = 285
                    self.match(SystemVerilogPreParser.CO)
                    self.state = 286
                    self.pragma_expression()
                    self.state = 291
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 292
                self.match(SystemVerilogPreParser.RP)
                pass
            elif token in [370]:
                self.enterOuterAlt(localctx, 2)
                self.state = 294
                self.number()
                pass
            elif token in [366]:
                self.enterOuterAlt(localctx, 3)
                self.state = 295
                self.string_literal()
                pass
            elif token in [365]:
                self.enterOuterAlt(localctx, 4)
                self.state = 296
                self.identifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Resetall_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def RESETALL_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.RESETALL_DIRECTIVE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_resetall_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterResetall_directive" ):
                listener.enterResetall_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitResetall_directive" ):
                listener.exitResetall_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitResetall_directive" ):
                return visitor.visitResetall_directive(self)
            else:
                return visitor.visitChildren(self)




    def resetall_directive(self):

        localctx = SystemVerilogPreParser.Resetall_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 72, self.RULE_resetall_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 299
            self.match(SystemVerilogPreParser.GA)
            self.state = 300
            self.match(SystemVerilogPreParser.RESETALL_DIRECTIVE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Source_text_Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SOURCE_TEXT(self):
            return self.getToken(SystemVerilogPreParser.SOURCE_TEXT, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_source_text_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSource_text_" ):
                listener.enterSource_text_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSource_text_" ):
                listener.exitSource_text_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSource_text_" ):
                return visitor.visitSource_text_(self)
            else:
                return visitor.visitChildren(self)




    def source_text_(self):

        localctx = SystemVerilogPreParser.Source_text_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 74, self.RULE_source_text_)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 302
            self.match(SystemVerilogPreParser.SOURCE_TEXT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class String_literalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def STRING_LITERAL(self):
            return self.getToken(SystemVerilogPreParser.STRING_LITERAL, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_string_literal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterString_literal" ):
                listener.enterString_literal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitString_literal" ):
                listener.exitString_literal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitString_literal" ):
                return visitor.visitString_literal(self)
            else:
                return visitor.visitChildren(self)




    def string_literal(self):

        localctx = SystemVerilogPreParser.String_literalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 76, self.RULE_string_literal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 304
            self.match(SystemVerilogPreParser.STRING_LITERAL)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Text_macro_definitionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def DEFINE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.DEFINE_DIRECTIVE, 0)

        def macro_name(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Macro_nameContext,0)


        def macro_text(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Macro_textContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_text_macro_definition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterText_macro_definition" ):
                listener.enterText_macro_definition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitText_macro_definition" ):
                listener.exitText_macro_definition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitText_macro_definition" ):
                return visitor.visitText_macro_definition(self)
            else:
                return visitor.visitChildren(self)




    def text_macro_definition(self):

        localctx = SystemVerilogPreParser.Text_macro_definitionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 78, self.RULE_text_macro_definition)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 306
            self.match(SystemVerilogPreParser.GA)
            self.state = 307
            self.match(SystemVerilogPreParser.DEFINE_DIRECTIVE)
            self.state = 308
            self.macro_name()
            self.state = 309
            self.macro_text()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Text_macro_usageContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def macro_usage(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Macro_usageContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_text_macro_usage

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterText_macro_usage" ):
                listener.enterText_macro_usage(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitText_macro_usage" ):
                listener.exitText_macro_usage(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitText_macro_usage" ):
                return visitor.visitText_macro_usage(self)
            else:
                return visitor.visitChildren(self)




    def text_macro_usage(self):

        localctx = SystemVerilogPreParser.Text_macro_usageContext(self, self._ctx, self.state)
        self.enterRule(localctx, 80, self.RULE_text_macro_usage)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 311
            self.match(SystemVerilogPreParser.GA)
            self.state = 312
            self.macro_usage()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Time_precisionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TIME_VALUE(self):
            return self.getToken(SystemVerilogPreParser.TIME_VALUE, 0)

        def TIME_UNIT(self):
            return self.getToken(SystemVerilogPreParser.TIME_UNIT, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_time_precision

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTime_precision" ):
                listener.enterTime_precision(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTime_precision" ):
                listener.exitTime_precision(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTime_precision" ):
                return visitor.visitTime_precision(self)
            else:
                return visitor.visitChildren(self)




    def time_precision(self):

        localctx = SystemVerilogPreParser.Time_precisionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 82, self.RULE_time_precision)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 314
            self.match(SystemVerilogPreParser.TIME_VALUE)
            self.state = 315
            self.match(SystemVerilogPreParser.TIME_UNIT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Time_unitContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TIME_VALUE(self):
            return self.getToken(SystemVerilogPreParser.TIME_VALUE, 0)

        def TIME_UNIT(self):
            return self.getToken(SystemVerilogPreParser.TIME_UNIT, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_time_unit

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTime_unit" ):
                listener.enterTime_unit(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTime_unit" ):
                listener.exitTime_unit(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTime_unit" ):
                return visitor.visitTime_unit(self)
            else:
                return visitor.visitChildren(self)




    def time_unit(self):

        localctx = SystemVerilogPreParser.Time_unitContext(self, self._ctx, self.state)
        self.enterRule(localctx, 84, self.RULE_time_unit)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 317
            self.match(SystemVerilogPreParser.TIME_VALUE)
            self.state = 318
            self.match(SystemVerilogPreParser.TIME_UNIT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Timescale_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def TIMESCALE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.TIMESCALE_DIRECTIVE, 0)

        def time_unit(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Time_unitContext,0)


        def SL(self):
            return self.getToken(SystemVerilogPreParser.SL, 0)

        def time_precision(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Time_precisionContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_timescale_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTimescale_directive" ):
                listener.enterTimescale_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTimescale_directive" ):
                listener.exitTimescale_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTimescale_directive" ):
                return visitor.visitTimescale_directive(self)
            else:
                return visitor.visitChildren(self)




    def timescale_directive(self):

        localctx = SystemVerilogPreParser.Timescale_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 86, self.RULE_timescale_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 320
            self.match(SystemVerilogPreParser.GA)
            self.state = 321
            self.match(SystemVerilogPreParser.TIMESCALE_DIRECTIVE)
            self.state = 322
            self.time_unit()
            self.state = 323
            self.match(SystemVerilogPreParser.SL)
            self.state = 324
            self.time_precision()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unconnected_drive_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def UNCONNECTED_DRIVE_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.UNCONNECTED_DRIVE_DIRECTIVE, 0)

        def unconnected_drive_value(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Unconnected_drive_valueContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_unconnected_drive_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnconnected_drive_directive" ):
                listener.enterUnconnected_drive_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnconnected_drive_directive" ):
                listener.exitUnconnected_drive_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnconnected_drive_directive" ):
                return visitor.visitUnconnected_drive_directive(self)
            else:
                return visitor.visitChildren(self)




    def unconnected_drive_directive(self):

        localctx = SystemVerilogPreParser.Unconnected_drive_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 88, self.RULE_unconnected_drive_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 326
            self.match(SystemVerilogPreParser.GA)
            self.state = 327
            self.match(SystemVerilogPreParser.UNCONNECTED_DRIVE_DIRECTIVE)
            self.state = 328
            self.unconnected_drive_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unconnected_drive_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def UNCONNECTED_DRIVE_VALUE(self):
            return self.getToken(SystemVerilogPreParser.UNCONNECTED_DRIVE_VALUE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_unconnected_drive_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnconnected_drive_value" ):
                listener.enterUnconnected_drive_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnconnected_drive_value" ):
                listener.exitUnconnected_drive_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnconnected_drive_value" ):
                return visitor.visitUnconnected_drive_value(self)
            else:
                return visitor.visitChildren(self)




    def unconnected_drive_value(self):

        localctx = SystemVerilogPreParser.Unconnected_drive_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 90, self.RULE_unconnected_drive_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 330
            self.match(SystemVerilogPreParser.UNCONNECTED_DRIVE_VALUE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Undef_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def UNDEF_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.UNDEF_DIRECTIVE, 0)

        def macro_identifier(self):
            return self.getTypedRuleContext(SystemVerilogPreParser.Macro_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_undef_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUndef_directive" ):
                listener.enterUndef_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUndef_directive" ):
                listener.exitUndef_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUndef_directive" ):
                return visitor.visitUndef_directive(self)
            else:
                return visitor.visitChildren(self)




    def undef_directive(self):

        localctx = SystemVerilogPreParser.Undef_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 92, self.RULE_undef_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 332
            self.match(SystemVerilogPreParser.GA)
            self.state = 333
            self.match(SystemVerilogPreParser.UNDEF_DIRECTIVE)
            self.state = 334
            self.macro_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Undefineall_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GA(self):
            return self.getToken(SystemVerilogPreParser.GA, 0)

        def UNDEFINEALL_DIRECTIVE(self):
            return self.getToken(SystemVerilogPreParser.UNDEFINEALL_DIRECTIVE, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_undefineall_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUndefineall_directive" ):
                listener.enterUndefineall_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUndefineall_directive" ):
                listener.exitUndefineall_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUndefineall_directive" ):
                return visitor.visitUndefineall_directive(self)
            else:
                return visitor.visitChildren(self)




    def undefineall_directive(self):

        localctx = SystemVerilogPreParser.Undefineall_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 94, self.RULE_undefineall_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 336
            self.match(SystemVerilogPreParser.GA)
            self.state = 337
            self.match(SystemVerilogPreParser.UNDEFINEALL_DIRECTIVE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Version_specifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def VERSION_SPECIFIER(self):
            return self.getToken(SystemVerilogPreParser.VERSION_SPECIFIER, 0)

        def getRuleIndex(self):
            return SystemVerilogPreParser.RULE_version_specifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVersion_specifier" ):
                listener.enterVersion_specifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVersion_specifier" ):
                listener.exitVersion_specifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVersion_specifier" ):
                return visitor.visitVersion_specifier(self)
            else:
                return visitor.visitChildren(self)




    def version_specifier(self):

        localctx = SystemVerilogPreParser.Version_specifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 96, self.RULE_version_specifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 339
            self.match(SystemVerilogPreParser.VERSION_SPECIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx





