from typing import Literal, Union

SYNTHESIS_DIRECTIVE = Union[
    Literal["default"],
    Literal["RuntimeOptimized"],
    Literal["AreaOptimized_high"],
    Literal["AreaOptimized_medium"],
    Literal["AlternateRoutability"],
    Literal["AreaMapLargeShiftRegToBRAM"],
    Literal["AreaMultThresholdDSP"],
    Literal["FewerCarryChains"],
    Literal["PerformanceOptimized"],
    Literal["LogicCompaction"],
    Literal["PowerOptimized_high"],
    Literal["PowerOptimized_medium"],
]
PLACE_DIRECTIVE = Union[
    Literal["Explore"],
    Literal["EarlyBlockPlacement"],
    Literal["WLDrivenBlockPlacement"],
    Literal["ExtraNetDelay_high"],
    Literal["ExtraNetDelay_low"],
    Literal["AltSpreadLogic_high"],
    Literal["AltSpreadLogic_medium"],
    Literal["AltSpreadLogic_low"],
    Literal["ExtraPostPlacementOpt"],
    Literal["ExtraTimingOpt"],
    Literal["SSI_SpreadLogic_high"],
    Literal["SSI_SpreadLogic_low"],
    Literal["SSI_SpreadSLLs"],
    Literal["SSI_BalanceSLLs"],
    Literal["SSI_BalanceSLRs"],
    Literal["SSI_HighUtilSLRs"],
    Literal["RuntimeOptimized"],
    Literal["Quick"],
    Literal["RQS"],
    Literal["Auto_1"],
    Literal["Auto_2"],
    Literal["Auto_3"],
]
ROUTE_DIRECTIVE = Union[
    Literal["Explore"],
    Literal["AggressiveExplore"],
    Literal["NoTimingRelaxation"],
    Literal["MoreGlobalIterations"],
    Literal["HigherDelayCost"],
    Literal["AdvancedSkewModeling"],
    Literal["AlternateCLBRouting"],
    Literal["RuntimeOptimized"],
    Literal["Quick"],
    Literal["Default"],
]
