# Generated from SystemVerilogPreParser.g4 by ANTLR 4.11.1
from antlr4 import *
if __name__ is not None and "." in __name__:
    from .SystemVerilogPreParser import SystemVerilogPreParser
else:
    from SystemVerilogPreParser import SystemVerilogPreParser

# This class defines a complete listener for a parse tree produced by SystemVerilogPreParser.
class SystemVerilogPreParserListener(ParseTreeListener):

    # Enter a parse tree produced by SystemVerilogPreParser#source_text.
    def enterSource_text(self, ctx:SystemVerilogPreParser.Source_textContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#source_text.
    def exitSource_text(self, ctx:SystemVerilogPreParser.Source_textContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#compiler_directive.
    def enterCompiler_directive(self, ctx:SystemVerilogPreParser.Compiler_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#compiler_directive.
    def exitCompiler_directive(self, ctx:SystemVerilogPreParser.Compiler_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#begin_keywords_directive.
    def enterBegin_keywords_directive(self, ctx:SystemVerilogPreParser.Begin_keywords_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#begin_keywords_directive.
    def exitBegin_keywords_directive(self, ctx:SystemVerilogPreParser.Begin_keywords_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#celldefine_directive.
    def enterCelldefine_directive(self, ctx:SystemVerilogPreParser.Celldefine_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#celldefine_directive.
    def exitCelldefine_directive(self, ctx:SystemVerilogPreParser.Celldefine_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#default_nettype_directive.
    def enterDefault_nettype_directive(self, ctx:SystemVerilogPreParser.Default_nettype_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#default_nettype_directive.
    def exitDefault_nettype_directive(self, ctx:SystemVerilogPreParser.Default_nettype_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#default_nettype_value.
    def enterDefault_nettype_value(self, ctx:SystemVerilogPreParser.Default_nettype_valueContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#default_nettype_value.
    def exitDefault_nettype_value(self, ctx:SystemVerilogPreParser.Default_nettype_valueContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#else_directive.
    def enterElse_directive(self, ctx:SystemVerilogPreParser.Else_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#else_directive.
    def exitElse_directive(self, ctx:SystemVerilogPreParser.Else_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#elsif_directive.
    def enterElsif_directive(self, ctx:SystemVerilogPreParser.Elsif_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#elsif_directive.
    def exitElsif_directive(self, ctx:SystemVerilogPreParser.Elsif_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#end_keywords_directive.
    def enterEnd_keywords_directive(self, ctx:SystemVerilogPreParser.End_keywords_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#end_keywords_directive.
    def exitEnd_keywords_directive(self, ctx:SystemVerilogPreParser.End_keywords_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#endcelldefine_directive.
    def enterEndcelldefine_directive(self, ctx:SystemVerilogPreParser.Endcelldefine_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#endcelldefine_directive.
    def exitEndcelldefine_directive(self, ctx:SystemVerilogPreParser.Endcelldefine_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#endif_directive.
    def enterEndif_directive(self, ctx:SystemVerilogPreParser.Endif_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#endif_directive.
    def exitEndif_directive(self, ctx:SystemVerilogPreParser.Endif_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#file_directive.
    def enterFile_directive(self, ctx:SystemVerilogPreParser.File_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#file_directive.
    def exitFile_directive(self, ctx:SystemVerilogPreParser.File_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#filename.
    def enterFilename(self, ctx:SystemVerilogPreParser.FilenameContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#filename.
    def exitFilename(self, ctx:SystemVerilogPreParser.FilenameContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#group_of_lines.
    def enterGroup_of_lines(self, ctx:SystemVerilogPreParser.Group_of_linesContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#group_of_lines.
    def exitGroup_of_lines(self, ctx:SystemVerilogPreParser.Group_of_linesContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#identifier.
    def enterIdentifier(self, ctx:SystemVerilogPreParser.IdentifierContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#identifier.
    def exitIdentifier(self, ctx:SystemVerilogPreParser.IdentifierContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#ifdef_directive.
    def enterIfdef_directive(self, ctx:SystemVerilogPreParser.Ifdef_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#ifdef_directive.
    def exitIfdef_directive(self, ctx:SystemVerilogPreParser.Ifdef_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#ifndef_directive.
    def enterIfndef_directive(self, ctx:SystemVerilogPreParser.Ifndef_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#ifndef_directive.
    def exitIfndef_directive(self, ctx:SystemVerilogPreParser.Ifndef_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#include_directive.
    def enterInclude_directive(self, ctx:SystemVerilogPreParser.Include_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#include_directive.
    def exitInclude_directive(self, ctx:SystemVerilogPreParser.Include_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#level.
    def enterLevel(self, ctx:SystemVerilogPreParser.LevelContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#level.
    def exitLevel(self, ctx:SystemVerilogPreParser.LevelContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#line_directive.
    def enterLine_directive(self, ctx:SystemVerilogPreParser.Line_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#line_directive.
    def exitLine_directive(self, ctx:SystemVerilogPreParser.Line_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#line_directive_.
    def enterLine_directive_(self, ctx:SystemVerilogPreParser.Line_directive_Context):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#line_directive_.
    def exitLine_directive_(self, ctx:SystemVerilogPreParser.Line_directive_Context):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#macro_delimiter.
    def enterMacro_delimiter(self, ctx:SystemVerilogPreParser.Macro_delimiterContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#macro_delimiter.
    def exitMacro_delimiter(self, ctx:SystemVerilogPreParser.Macro_delimiterContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#macro_esc_newline.
    def enterMacro_esc_newline(self, ctx:SystemVerilogPreParser.Macro_esc_newlineContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#macro_esc_newline.
    def exitMacro_esc_newline(self, ctx:SystemVerilogPreParser.Macro_esc_newlineContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#macro_esc_quote.
    def enterMacro_esc_quote(self, ctx:SystemVerilogPreParser.Macro_esc_quoteContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#macro_esc_quote.
    def exitMacro_esc_quote(self, ctx:SystemVerilogPreParser.Macro_esc_quoteContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#macro_identifier.
    def enterMacro_identifier(self, ctx:SystemVerilogPreParser.Macro_identifierContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#macro_identifier.
    def exitMacro_identifier(self, ctx:SystemVerilogPreParser.Macro_identifierContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#macro_name.
    def enterMacro_name(self, ctx:SystemVerilogPreParser.Macro_nameContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#macro_name.
    def exitMacro_name(self, ctx:SystemVerilogPreParser.Macro_nameContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#macro_quote.
    def enterMacro_quote(self, ctx:SystemVerilogPreParser.Macro_quoteContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#macro_quote.
    def exitMacro_quote(self, ctx:SystemVerilogPreParser.Macro_quoteContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#macro_text.
    def enterMacro_text(self, ctx:SystemVerilogPreParser.Macro_textContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#macro_text.
    def exitMacro_text(self, ctx:SystemVerilogPreParser.Macro_textContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#macro_usage.
    def enterMacro_usage(self, ctx:SystemVerilogPreParser.Macro_usageContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#macro_usage.
    def exitMacro_usage(self, ctx:SystemVerilogPreParser.Macro_usageContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#nounconnected_drive_directive.
    def enterNounconnected_drive_directive(self, ctx:SystemVerilogPreParser.Nounconnected_drive_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#nounconnected_drive_directive.
    def exitNounconnected_drive_directive(self, ctx:SystemVerilogPreParser.Nounconnected_drive_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#number.
    def enterNumber(self, ctx:SystemVerilogPreParser.NumberContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#number.
    def exitNumber(self, ctx:SystemVerilogPreParser.NumberContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#pragma_directive.
    def enterPragma_directive(self, ctx:SystemVerilogPreParser.Pragma_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#pragma_directive.
    def exitPragma_directive(self, ctx:SystemVerilogPreParser.Pragma_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#pragma_expression.
    def enterPragma_expression(self, ctx:SystemVerilogPreParser.Pragma_expressionContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#pragma_expression.
    def exitPragma_expression(self, ctx:SystemVerilogPreParser.Pragma_expressionContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#pragma_keyword.
    def enterPragma_keyword(self, ctx:SystemVerilogPreParser.Pragma_keywordContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#pragma_keyword.
    def exitPragma_keyword(self, ctx:SystemVerilogPreParser.Pragma_keywordContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#pragma_name.
    def enterPragma_name(self, ctx:SystemVerilogPreParser.Pragma_nameContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#pragma_name.
    def exitPragma_name(self, ctx:SystemVerilogPreParser.Pragma_nameContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#pragma_value.
    def enterPragma_value(self, ctx:SystemVerilogPreParser.Pragma_valueContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#pragma_value.
    def exitPragma_value(self, ctx:SystemVerilogPreParser.Pragma_valueContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#resetall_directive.
    def enterResetall_directive(self, ctx:SystemVerilogPreParser.Resetall_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#resetall_directive.
    def exitResetall_directive(self, ctx:SystemVerilogPreParser.Resetall_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#source_text_.
    def enterSource_text_(self, ctx:SystemVerilogPreParser.Source_text_Context):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#source_text_.
    def exitSource_text_(self, ctx:SystemVerilogPreParser.Source_text_Context):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#string_literal.
    def enterString_literal(self, ctx:SystemVerilogPreParser.String_literalContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#string_literal.
    def exitString_literal(self, ctx:SystemVerilogPreParser.String_literalContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#text_macro_definition.
    def enterText_macro_definition(self, ctx:SystemVerilogPreParser.Text_macro_definitionContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#text_macro_definition.
    def exitText_macro_definition(self, ctx:SystemVerilogPreParser.Text_macro_definitionContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#text_macro_usage.
    def enterText_macro_usage(self, ctx:SystemVerilogPreParser.Text_macro_usageContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#text_macro_usage.
    def exitText_macro_usage(self, ctx:SystemVerilogPreParser.Text_macro_usageContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#time_precision.
    def enterTime_precision(self, ctx:SystemVerilogPreParser.Time_precisionContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#time_precision.
    def exitTime_precision(self, ctx:SystemVerilogPreParser.Time_precisionContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#time_unit.
    def enterTime_unit(self, ctx:SystemVerilogPreParser.Time_unitContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#time_unit.
    def exitTime_unit(self, ctx:SystemVerilogPreParser.Time_unitContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#timescale_directive.
    def enterTimescale_directive(self, ctx:SystemVerilogPreParser.Timescale_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#timescale_directive.
    def exitTimescale_directive(self, ctx:SystemVerilogPreParser.Timescale_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#unconnected_drive_directive.
    def enterUnconnected_drive_directive(self, ctx:SystemVerilogPreParser.Unconnected_drive_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#unconnected_drive_directive.
    def exitUnconnected_drive_directive(self, ctx:SystemVerilogPreParser.Unconnected_drive_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#unconnected_drive_value.
    def enterUnconnected_drive_value(self, ctx:SystemVerilogPreParser.Unconnected_drive_valueContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#unconnected_drive_value.
    def exitUnconnected_drive_value(self, ctx:SystemVerilogPreParser.Unconnected_drive_valueContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#undef_directive.
    def enterUndef_directive(self, ctx:SystemVerilogPreParser.Undef_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#undef_directive.
    def exitUndef_directive(self, ctx:SystemVerilogPreParser.Undef_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#undefineall_directive.
    def enterUndefineall_directive(self, ctx:SystemVerilogPreParser.Undefineall_directiveContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#undefineall_directive.
    def exitUndefineall_directive(self, ctx:SystemVerilogPreParser.Undefineall_directiveContext):
        pass


    # Enter a parse tree produced by SystemVerilogPreParser#version_specifier.
    def enterVersion_specifier(self, ctx:SystemVerilogPreParser.Version_specifierContext):
        pass

    # Exit a parse tree produced by SystemVerilogPreParser#version_specifier.
    def exitVersion_specifier(self, ctx:SystemVerilogPreParser.Version_specifierContext):
        pass



del SystemVerilogPreParser