# Generated from VerilogParser.g4 by ANTLR 4.9.3
# encoding: utf-8
from antlr4 import *
from io import StringIO
import sys
if sys.version_info[1] > 5:
	from typing import TextIO
else:
	from typing.io import TextIO


def serializedATN():
    with StringIO() as buf:
        buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\u0180")
        buf.write("\u105a\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7")
        buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16")
        buf.write("\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23\t\23")
        buf.write("\4\24\t\24\4\25\t\25\4\26\t\26\4\27\t\27\4\30\t\30\4\31")
        buf.write("\t\31\4\32\t\32\4\33\t\33\4\34\t\34\4\35\t\35\4\36\t\36")
        buf.write("\4\37\t\37\4 \t \4!\t!\4\"\t\"\4#\t#\4$\t$\4%\t%\4&\t")
        buf.write("&\4\'\t\'\4(\t(\4)\t)\4*\t*\4+\t+\4,\t,\4-\t-\4.\t.\4")
        buf.write("/\t/\4\60\t\60\4\61\t\61\4\62\t\62\4\63\t\63\4\64\t\64")
        buf.write("\4\65\t\65\4\66\t\66\4\67\t\67\48\t8\49\t9\4:\t:\4;\t")
        buf.write(";\4<\t<\4=\t=\4>\t>\4?\t?\4@\t@\4A\tA\4B\tB\4C\tC\4D\t")
        buf.write("D\4E\tE\4F\tF\4G\tG\4H\tH\4I\tI\4J\tJ\4K\tK\4L\tL\4M\t")
        buf.write("M\4N\tN\4O\tO\4P\tP\4Q\tQ\4R\tR\4S\tS\4T\tT\4U\tU\4V\t")
        buf.write("V\4W\tW\4X\tX\4Y\tY\4Z\tZ\4[\t[\4\\\t\\\4]\t]\4^\t^\4")
        buf.write("_\t_\4`\t`\4a\ta\4b\tb\4c\tc\4d\td\4e\te\4f\tf\4g\tg\4")
        buf.write("h\th\4i\ti\4j\tj\4k\tk\4l\tl\4m\tm\4n\tn\4o\to\4p\tp\4")
        buf.write("q\tq\4r\tr\4s\ts\4t\tt\4u\tu\4v\tv\4w\tw\4x\tx\4y\ty\4")
        buf.write("z\tz\4{\t{\4|\t|\4}\t}\4~\t~\4\177\t\177\4\u0080\t\u0080")
        buf.write("\4\u0081\t\u0081\4\u0082\t\u0082\4\u0083\t\u0083\4\u0084")
        buf.write("\t\u0084\4\u0085\t\u0085\4\u0086\t\u0086\4\u0087\t\u0087")
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        buf.write("\4\u00f1\t\u00f1\4\u00f2\t\u00f2\4\u00f3\t\u00f3\4\u00f4")
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        buf.write("\t\u00fb\4\u00fc\t\u00fc\4\u00fd\t\u00fd\4\u00fe\t\u00fe")
        buf.write("\4\u00ff\t\u00ff\4\u0100\t\u0100\4\u0101\t\u0101\4\u0102")
        buf.write("\t\u0102\4\u0103\t\u0103\4\u0104\t\u0104\4\u0105\t\u0105")
        buf.write("\4\u0106\t\u0106\4\u0107\t\u0107\4\u0108\t\u0108\4\u0109")
        buf.write("\t\u0109\4\u010a\t\u010a\4\u010b\t\u010b\4\u010c\t\u010c")
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        buf.write("\4\u0114\t\u0114\4\u0115\t\u0115\4\u0116\t\u0116\4\u0117")
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        buf.write("\u0ff4\u0ffd\u101c\u1022")
        return buf.getvalue()


class VerilogParser ( Parser ):

    grammarFileName = "VerilogParser.g4"

    atn = ATNDeserializer().deserialize(serializedATN())

    decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ]

    sharedContextCache = PredictionContextCache()

    literalNames = [ "<INVALID>", "'always'", "'and'", "'assign'", "'automatic'", 
                     "'begin'", "'buf'", "'bufif0'", "'bufif1'", "'case'", 
                     "'casex'", "'casez'", "'cell'", "'cmos'", "'config'", 
                     "'deassign'", "'default'", "'defparam'", "'design'", 
                     "'disable'", "'edge'", "'else'", "'end'", "'endcase'", 
                     "'endconfig'", "'endfunction'", "'endgenerate'", "'endmodule'", 
                     "'endprimitive'", "'endspecify'", "'endtable'", "'endtask'", 
                     "'event'", "'for'", "'force'", "'forever'", "'fork'", 
                     "'function'", "'generate'", "'genvar'", "'highz0'", 
                     "'highz1'", "'if'", "'ifnone'", "'incdir'", "<INVALID>", 
                     "'initial'", "'inout'", "'input'", "'instance'", "'integer'", 
                     "'join'", "'large'", "'liblist'", "'library'", "'localparam'", 
                     "'macromodule'", "'medium'", "'module'", "'nand'", 
                     "'negedge'", "'nmos'", "'nor'", "'noshowcancelled'", 
                     "'not'", "'notif0'", "'notif1'", "'or'", "'output'", 
                     "'parameter'", "'pmos'", "'posedge'", "'primitive'", 
                     "'pull0'", "'pull1'", "'pulldown'", "'pullup'", "'pulsestyle_onevent'", 
                     "'pulsestyle_ondetect'", "'rcmos'", "'real'", "'realtime'", 
                     "'reg'", "'release'", "'repeat'", "'rnmos'", "'rpmos'", 
                     "'rtran'", "'rtranif0'", "'rtranif1'", "'scalared'", 
                     "'showcancelled'", "'signed'", "'small'", "'specify'", 
                     "'specparam'", "'strong0'", "'strong1'", "'supply0'", 
                     "'supply1'", "'table'", "'task'", "'time'", "'tran'", 
                     "'tranif0'", "'tranif1'", "'tri'", "'tri0'", "'tri1'", 
                     "'triand'", "'trior'", "'trireg'", "'unsigned'", "'use'", 
                     "'uwire'", "'vectored'", "'wait'", "'wand'", "'weak0'", 
                     "'weak1'", "'while'", "'wire'", "'wor'", "'xnor'", 
                     "'xor'", "'$display'", "'$displayb'", "'$displayh'", 
                     "'$displayo'", "'$write'", "'$writeb'", "'$writeh'", 
                     "'$writeo'", "'$strobe'", "'$strobeb'", "'$strobeh'", 
                     "'$strobeo'", "'$monitor'", "'$monitorb'", "'$monitorh'", 
                     "'$monitoro'", "'$monitoroff'", "'$monitoron'", "'$fclose'", 
                     "'$fdisplay'", "'$fdisplayb'", "'$fdisplayh'", "'$fdisplayo'", 
                     "'$fstrobe'", "'$fstrobeb'", "'$fstrobeh'", "'$fstrobeo'", 
                     "'$swrite'", "'$swriteb'", "'$swriteh'", "'$swriteo'", 
                     "'$fscanf'", "'$fread'", "'$fseek'", "'$fflush'", "'$feof'", 
                     "'$sdf_annotate'", "'$fopen'", "'$fwrite'", "'$fwriteb'", 
                     "'$fwriteh'", "'$fwriteo'", "'$fmonitor'", "'$fmonitorb'", 
                     "'$fmonitorh'", "'$fmonitoro'", "'$sformat'", "'$fgetc'", 
                     "'$ungetc'", "'$fgets'", "'$sscanf'", "'$rewind'", 
                     "'$ftell'", "'$ferror'", "'$readmemb'", "'$readmemh'", 
                     "'$printtimescale'", "'$timeformat'", "'$finish'", 
                     "'$stop'", "'$async$and$array'", "'$async$nand$array'", 
                     "'$async$or$array'", "'$async$nor$array'", "'$sync$and$array'", 
                     "'$sync$nand$array'", "'$sync$or$array'", "'$sync$nor$array'", 
                     "'$async$and$plane'", "'$async$nand$plane'", "'$async$or$plane'", 
                     "'$async$nor$plane'", "'$sync$and$plane'", "'$sync$nand$plane'", 
                     "'$sync$or$plane'", "'$sync$nor$plane'", "'$q_initialize'", 
                     "'$q_remove'", "'$q_exam'", "'$q_add'", "'$q_full'", 
                     "'$realtime'", "'$time'", "'$stime'", "'$bitstoreal'", 
                     "'$itor'", "'$signed'", "'$realtobits'", "'$rtoi'", 
                     "'$unsigned'", "'$random'", "'$dist_erlang'", "'$dist_normal'", 
                     "'$dist_t'", "'$dist_chi_square'", "'$dist_exponential'", 
                     "'$dist_poisson'", "'$dist_uniform'", "'$test$plusargs'", 
                     "'$value$plusargs'", "'$clog2'", "'$ln'", "'$log10'", 
                     "'$exp'", "'$sqrt'", "'$pow'", "'$floor'", "'$ceil'", 
                     "'$sin'", "'$cos'", "'$tan'", "'$asin'", "'$acos'", 
                     "'$atan'", "'$atan2'", "'$hypot'", "'$sinh'", "'$cosh'", 
                     "'$tanh'", "'$asinh'", "'$acosh'", "'$atanh'", "'$dumpfile'", 
                     "'$dumpvars'", "'$dumpoff'", "'$dumpon'", "'$dumpall'", 
                     "'$dumplimit'", "'$dumpflush'", "'$end'", "'$comment'", 
                     "'$date'", "'$enddefinitions'", "'$scope'", "'$timescale'", 
                     "'$upscope'", "'$var'", "'$version'", "'$dumpports'", 
                     "'$dumpportsoff'", "'$dumpportson'", "'$dumpportsall'", 
                     "'$dumpportslimit'", "'$dumpportsflush'", "'$vcdclose'", 
                     "'$setup'", "'$hold'", "'$setuphold'", "'$recovery'", 
                     "'$removal'", "'$recrem'", "'$skew'", "'$timeskew'", 
                     "'$fullskew'", "'$period'", "'$width'", "'$nochange'", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "'('", "')'", "'['", "']'", "'{'", "'}'", "'+'", "'-'", 
                     "'!'", "'~'", "'&'", "'~&'", "'|'", "'~|'", "'^'", 
                     "'~^'", "'^~'", "'*'", "'%'", "'=='", "'!='", "'==='", 
                     "'!=='", "'&&'", "'||'", "'**'", "'<'", "'<='", "'>'", 
                     "'>='", "'>>'", "'<<'", "'>>>'", "'<<<'", "'.'", "<INVALID>", 
                     "':'", "';'", "<INVALID>", "'='", "'?'", "'@'", "'#'", 
                     "<INVALID>", "'+:'", "'-:'", "'->'", "'=>'", "'*>'", 
                     "'&&&'", "'PATHPULSE$'", "<INVALID>", "'-incdir'", 
                     "<INVALID>", "'begin_keywords'", "'celldefine'", "'default_nettype'", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "'end_keywords'", 
                     "'endcelldefine'", "'endif'", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "'line'", "'nounconnected_drive'", "'resetall'", 
                     "'timescale'", "'unconnected_drive'" ]

    symbolicNames = [ "<INVALID>", "ALWAYS", "AND", "ASSIGN", "AUTOMATIC", 
                      "BEGIN", "BUF", "BUFIF0", "BUFIF1", "CASE", "CASEX", 
                      "CASEZ", "CELL", "CMOS", "CONFIG", "DEASSIGN", "DEFAULT", 
                      "DEFPARAM", "DESIGN", "DISABLE", "EDGE", "ELSE", "END", 
                      "ENDCASE", "ENDCONFIG", "ENDFUNCTION", "ENDGENERATE", 
                      "ENDMODULE", "ENDPRIMITIVE", "ENDSPECIFY", "ENDTABLE", 
                      "ENDTASK", "EVENT", "FOR", "FORCE", "FOREVER", "FORK", 
                      "FUNCTION", "GENERATE", "GENVAR", "HIGHZ0", "HIGHZ1", 
                      "IF", "IFNONE", "INCDIR", "INCLUDE", "INITIAL", "INOUT", 
                      "INPUT", "INSTANCE", "INTEGER", "JOIN", "LARGE", "LIBLIST", 
                      "LIBRARY", "LOCALPARAM", "MACROMODULE", "MEDIUM", 
                      "MODULE", "NAND", "NEGEDGE", "NMOS", "NOR", "NOSHOWCANCELLED", 
                      "NOT", "NOTIF0", "NOTIF1", "OR", "OUTPUT", "PARAMETER", 
                      "PMOS", "POSEDGE", "PRIMITIVE", "PULL0", "PULL1", 
                      "PULLDOWN", "PULLUP", "PULSESTYLE_ONEVENT", "PULSESTYLE_ONDETECT", 
                      "RCMOS", "REAL", "REALTIME", "REG", "RELEASE", "REPEAT", 
                      "RNMOS", "RPMOS", "RTRAN", "RTRANIF0", "RTRANIF1", 
                      "SCALARED", "SHOWCANCELLED", "SIGNED", "SMALL", "SPECIFY", 
                      "SPECPARAM", "STRONG0", "STRONG1", "SUPPLY0", "SUPPLY1", 
                      "TABLE", "TASK", "TIME", "TRAN", "TRANIF0", "TRANIF1", 
                      "TRI", "TRI0", "TRI1", "TRIAND", "TRIOR", "TRIREG", 
                      "UNSIGNED", "USE", "UWIRE", "VECTORED", "WAIT", "WAND", 
                      "WEAK0", "WEAK1", "WHILE", "WIRE", "WOR", "XNOR", 
                      "XOR", "DOLLAR_DISPLAY", "DOLLAR_DISPLAYB", "DOLLAR_DISPLAYH", 
                      "DOLLAR_DISPLAYO", "DOLLAR_WRITE", "DOLLAR_WRITEB", 
                      "DOLLAR_WRITEH", "DOLLAR_WRITEO", "DOLLAR_STROBE", 
                      "DOLLAR_STROBEB", "DOLLAR_STROBEH", "DOLLAR_STROBEO", 
                      "DOLLAR_MONITOR", "DOLLAR_MONITORB", "DOLLAR_MONITORH", 
                      "DOLLAR_MONITORO", "DOLLAR_MONITOROFF", "DOLLAR_MONITORON", 
                      "DOLLAR_FCLOSE", "DOLLAR_FDISPLAY", "DOLLAR_FDISPLAYB", 
                      "DOLLAR_FDISPLAYH", "DOLLAR_FDISPLAYO", "DOLLAR_FSTROBE", 
                      "DOLLAR_FSTROBEB", "DOLLAR_FSTROBEH", "DOLLAR_FSTROBEO", 
                      "DOLLAR_SWRITE", "DOLLAR_SWRITEB", "DOLLAR_SWRITEH", 
                      "DOLLAR_SWRITEO", "DOLLAR_FSCANF", "DOLLAR_FREAD", 
                      "DOLLAR_FSEEK", "DOLLAR_FFLUSH", "DOLLAR_FEOF", "DOLLAR_SDF_ANNOTATE", 
                      "DOLLAR_FOPEN", "DOLLAR_FWRITE", "DOLLAR_FWRITEB", 
                      "DOLLAR_FWRITEH", "DOLLAR_FWRITEO", "DOLLAR_FMONITOR", 
                      "DOLLAR_FMONITORB", "DOLLAR_FMONITORH", "DOLLAR_FMONITORO", 
                      "DOLLAR_SFORMAT", "DOLLAR_FGETC", "DOLLAR_UNGETC", 
                      "DOLLAR_FGETS", "DOLLAR_SSCANF", "DOLLAR_REWIND", 
                      "DOLLAR_FTELL", "DOLLAR_FERROR", "DOLLAR_READMEMB", 
                      "DOLLAR_READMEMH", "DOLLAR_PRINTTIMESCALE", "DOLLAR_TIMEFORMAT", 
                      "DOLLAR_FINISH", "DOLLAR_STOP", "DOLLAR_ASYNC_AND_ARRAY", 
                      "DOLLAR_ASYNC_NAND_ARRAY", "DOLLAR_ASYNC_OR_ARRAY", 
                      "DOLLAR_ASYNC_NOR_ARRAY", "DOLLAR_SYNC_AND_ARRAY", 
                      "DOLLAR_SYNC_NAND_ARRAY", "DOLLAR_SYNC_OR_ARRAY", 
                      "DOLLAR_SYNC_NOR_ARRAY", "DOLLAR_ASYNC_AND_PLANE", 
                      "DOLLAR_ASYNC_NAND_PLANE", "DOLLAR_ASYNC_OR_PLANE", 
                      "DOLLAR_ASYNC_NOR_PLANE", "DOLLAR_SYNC_AND_PLANE", 
                      "DOLLAR_SYNC_NAND_PLANE", "DOLLAR_SYNC_OR_PLANE", 
                      "DOLLAR_SYNC_NOR_PLANE", "DOLLAR_Q_INITIALIZE", "DOLLAR_Q_REMOVE", 
                      "DOLLAR_Q_EXAM", "DOLLAR_Q_ADD", "DOLLAR_Q_FULL", 
                      "DOLLAR_REALTIME", "DOLLAR_TIME", "DOLLAR_STIME", 
                      "DOLLAR_BITSTOREAL", "DOLLAR_ITOR", "DOLLAR_SIGNED", 
                      "DOLLAR_REALTOBITS", "DOLLAR_RTOI", "DOLLAR_UNSIGNED", 
                      "DOLLAR_RANDOM", "DOLLAR_DIST_ERLANG", "DOLLAR_DIST_NORMAL", 
                      "DOLLAR_DIST_T", "DOLLAR_DIST_CHI_SQUARE", "DOLLAR_DIST_EXPONENTIAL", 
                      "DOLLAR_DIST_POISSON", "DOLLAR_DIST_UNIFORM", "DOLLAR_TEST_PLUSARGS", 
                      "DOLLAR_VALUE_PLUSARGS", "DOLLAR_CLOG2", "DOLLAR_LN", 
                      "DOLLAR_LOG10", "DOLLAR_EXP", "DOLLAR_SQRT", "DOLLAR_POW", 
                      "DOLLAR_FLOOR", "DOLLAR_CEIL", "DOLLAR_SIN", "DOLLAR_COS", 
                      "DOLLAR_TAN", "DOLLAR_ASIN", "DOLLAR_ACOS", "DOLLAR_ATAN", 
                      "DOLLAR_ATAN2", "DOLLAR_HYPOT", "DOLLAR_SINH", "DOLLAR_COSH", 
                      "DOLLAR_TANH", "DOLLAR_ASINH", "DOLLAR_ACOSH", "DOLLAR_ATANH", 
                      "DOLLAR_DUMPFILE", "DOLLAR_DUMPVARS", "DOLLAR_DUMPOFF", 
                      "DOLLAR_DUMPON", "DOLLAR_DUMPALL", "DOLLAR_DUMPLIMIT", 
                      "DOLLAR_DUMPFLUSH", "DOLLAR_END", "DOLLAR_COMMENT", 
                      "DOLLAR_DATE", "DOLLAR_ENDDEFINITIONS", "DOLLAR_SCOPE", 
                      "DOLLAR_TIMESCALE", "DOLLAR_UPSCOPE", "DOLLAR_VAR", 
                      "DOLLAR_VERSION", "DOLLAR_DUMPPORTS", "DOLLAR_DUMPPORTSOFF", 
                      "DOLLAR_DUMPPORTSON", "DOLLAR_DUMPPORTSALL", "DOLLAR_DUMPPORTSLIMIT", 
                      "DOLLAR_DUMPPORTSFLUSH", "DOLLAR_VCDCLOSE", "DOLLAR_SETUP", 
                      "DOLLAR_HOLD", "DOLLAR_SETUPHOLD", "DOLLAR_RECOVERY", 
                      "DOLLAR_REMOVAL", "DOLLAR_RECREM", "DOLLAR_SKEW", 
                      "DOLLAR_TIMESKEW", "DOLLAR_FULLSKEW", "DOLLAR_PERIOD", 
                      "DOLLAR_WIDTH", "DOLLAR_NOCHANGE", "REAL_NUMBER", 
                      "DECIMAL_NUMBER", "BINARY_NUMBER", "OCTAL_NUMBER", 
                      "HEX_NUMBER", "STRING", "ONE_LINE_COMMENT", "BLOCK_COMMENT", 
                      "ESCAPED_IDENTIFIER", "SIMPLE_IDENTIFIER", "SYSTEM_TF_IDENTIFIER", 
                      "WHITE_SPACE_REGION", "LEFT_PARENTHESIS", "RIGHT_PARENTHESIS", 
                      "LEFT_BRACKET", "RIGHT_BRACKET", "LEFT_BRACE", "RIGHT_BRACE", 
                      "PLUS", "MINUS", "EXCLAMATION_MARK", "TILDE", "AMPERSAND", 
                      "TILDE_AMPERSAND", "VERTICAL_BAR", "TILDE_VERTICAL_BAR", 
                      "CARET", "TILDE_CARET", "CARET_TILDE", "ASTERISK", 
                      "PERCENT", "DOUBLE_EQUAL", "EXCLAMATION_MARK_EQUAL", 
                      "TRIPLE_EQUAL", "EXCLAMATION_MARK_DOUBLE_EQUAL", "DOUBLE_AMPERSAND", 
                      "DOUBLE_VERTICAL_BAR", "DOUBLE_ASTERISK", "LESS_THAN", 
                      "LESS_THAN_EQUAL", "GREATER_THAN", "GREATER_THAN_EQUAL", 
                      "DOUBLE_GREATER_THAN", "DOUBLE_LESS_THAN", "TRIPLE_GREATER_THAN", 
                      "TRIPLE_LESS_THAN", "DOT", "COMMA", "COLON", "SEMICOLON", 
                      "SLASH", "EQUAL", "QUESTION_MARK", "AT", "HASH", "GRAVE_ACCENT", 
                      "PLUS_COLON", "MINUS_COLON", "MINUS_GREATER_THAN", 
                      "EQUAL_GREATER_THAN", "ASTERISK_GREATER_THAN", "TRIPLE_AMPERSAND", 
                      "PATHPULSE_DOLLAR", "FILE_PATH_SPEC", "MINUS_INCDIR", 
                      "LIBRARY_NEWLINE", "DIRECTIVE_BEGIN_KEYWORDS", "DIRECTIVE_CELLDEFINE", 
                      "DIRECTIVE_DEFAULT_NETTYPE", "DIRECTIVE_DEFINE", "DIRECTIVE_ELSE", 
                      "DIRECTIVE_ELSIF", "DIRECTIVE_END_KEYWORDS", "DIRECTIVE_ENDCELLDEFINE", 
                      "DIRECTIVE_ENDIF", "DIRECTIVE_IFDEF", "DIRECTIVE_IFNDEF", 
                      "DIRECTIVE_INCLUDE", "DIRECTIVE_LINE", "DIRECTIVE_NOUNCONNECTED_DRIVE", 
                      "DIRECTIVE_RESETALL", "DIRECTIVE_TIMESCALE", "DIRECTIVE_UNCONNECTED_DRIVE", 
                      "DIRECTIVE_UNDEF", "DEFAULT_NETTYPE_VALUE", "TIME_UNIT", 
                      "UNCONNECTED_DRIVE_VALUE", "DIRECTIVE_NUMBER", "DIRECTIVE_STRING", 
                      "DIRECTIVE_IDENTIFIER", "DIRECTIVE_SLASH", "DIRECTIVE_COMMENT", 
                      "DIRECTIVE_WHITE_SPACE", "DIRECTIVE_NEWLINE", "MACRO_TEXT", 
                      "MACRO_TEXT_BACKSLASH_NEWLINE", "DIRECTIVE_LIST_OF_ARGUMENTS", 
                      "MACRO_USAGE_BACKSLASH_NEWLINE", "ANY_OTHER_TOKEN", 
                      "SOURCE_TEXT", "SOURCE_TEXT_BACKSLASH_NEWLINE" ]

    RULE_display_tasks = 0
    RULE_display_task_name = 1
    RULE_list_of_arguments = 2
    RULE_argument = 3
    RULE_strobe_tasks = 4
    RULE_strobe_task_name = 5
    RULE_monitor_tasks = 6
    RULE_monitor_task_name = 7
    RULE_file_open_function = 8
    RULE_file_close_task = 9
    RULE_multi_channel_descriptor = 10
    RULE_fd = 11
    RULE_file_name = 12
    RULE_type_ = 13
    RULE_file_output_tasks = 14
    RULE_file_output_task_name = 15
    RULE_load_memory_tasks = 16
    RULE_memory_name = 17
    RULE_start_addr = 18
    RULE_finish_addr = 19
    RULE_filename = 20
    RULE_finish_task = 21
    RULE_finish_number = 22
    RULE_stop_task = 23
    RULE_time_function = 24
    RULE_stime_function = 25
    RULE_realtime_function = 26
    RULE_conversion_functions = 27
    RULE_conversion_function_name = 28
    RULE_constant_argument = 29
    RULE_random_function = 30
    RULE_seed = 31
    RULE_dist_functions = 32
    RULE_start_ = 33
    RULE_end = 34
    RULE_mean = 35
    RULE_standard_deviation = 36
    RULE_degree_of_freedom = 37
    RULE_k_stage = 38
    RULE_math_functions = 39
    RULE_integer_math_functions = 40
    RULE_real_math_functions = 41
    RULE_single_argument_real_math_function_name = 42
    RULE_double_argument_real_math_function_name = 43
    RULE_dumpfile_task = 44
    RULE_dumpvars_task = 45
    RULE_list_of_modules_or_variables = 46
    RULE_module_or_variable = 47
    RULE_levels = 48
    RULE_dumpoff_task = 49
    RULE_dumpon_task = 50
    RULE_dumpall_task = 51
    RULE_dumplimit_task = 52
    RULE_file_size = 53
    RULE_dumpflush_task = 54
    RULE_dumpports_task = 55
    RULE_scope_list = 56
    RULE_file_pathname = 57
    RULE_dumpportsoff_task = 58
    RULE_dumpportson_task = 59
    RULE_dumpportsall_task = 60
    RULE_dumpportslimit_task = 61
    RULE_dumpportsflush_task = 62
    RULE_library_text = 63
    RULE_library_description = 64
    RULE_library_declaration = 65
    RULE_include_statement = 66
    RULE_source_text = 67
    RULE_description = 68
    RULE_module_declaration = 69
    RULE_module_keyword = 70
    RULE_module_parameter_port_list = 71
    RULE_list_of_ports = 72
    RULE_list_of_port_declarations = 73
    RULE_port = 74
    RULE_port_expression = 75
    RULE_port_reference = 76
    RULE_port_declaration = 77
    RULE_module_item = 78
    RULE_module_or_generate_item = 79
    RULE_module_or_generate_item_declaration = 80
    RULE_non_port_module_item = 81
    RULE_parameter_override = 82
    RULE_config_declaration = 83
    RULE_design_statement = 84
    RULE_config_rule_statement = 85
    RULE_default_clause = 86
    RULE_inst_clause = 87
    RULE_inst_name = 88
    RULE_cell_clause = 89
    RULE_liblist_clause = 90
    RULE_use_clause = 91
    RULE_local_parameter_declaration = 92
    RULE_parameter_declaration = 93
    RULE_specparam_declaration = 94
    RULE_parameter_type = 95
    RULE_inout_declaration = 96
    RULE_input_declaration = 97
    RULE_output_declaration = 98
    RULE_event_declaration = 99
    RULE_integer_declaration = 100
    RULE_net_declaration = 101
    RULE_real_declaration = 102
    RULE_realtime_declaration = 103
    RULE_reg_declaration = 104
    RULE_time_declaration = 105
    RULE_net_type = 106
    RULE_output_variable_type = 107
    RULE_real_type = 108
    RULE_variable_type = 109
    RULE_drive_strength = 110
    RULE_strength0 = 111
    RULE_strength1 = 112
    RULE_charge_strength = 113
    RULE_delay3 = 114
    RULE_delay2 = 115
    RULE_delay_value = 116
    RULE_list_of_defparam_assignments = 117
    RULE_list_of_event_identifiers = 118
    RULE_list_of_net_decl_assignments = 119
    RULE_list_of_net_identifiers = 120
    RULE_list_of_param_assignments = 121
    RULE_list_of_port_identifiers = 122
    RULE_list_of_real_identifiers = 123
    RULE_list_of_specparam_assignments = 124
    RULE_list_of_variable_identifiers = 125
    RULE_list_of_variable_port_identifiers = 126
    RULE_defparam_assignment = 127
    RULE_net_decl_assignment = 128
    RULE_param_assignment = 129
    RULE_specparam_assignment = 130
    RULE_pulse_control_specparam = 131
    RULE_error_limit_value = 132
    RULE_reject_limit_value = 133
    RULE_limit_value = 134
    RULE_dimension = 135
    RULE_range_ = 136
    RULE_function_declaration = 137
    RULE_function_item_declaration = 138
    RULE_function_port_list = 139
    RULE_function_range_or_type = 140
    RULE_task_declaration = 141
    RULE_task_item_declaration = 142
    RULE_task_port_list = 143
    RULE_task_port_item = 144
    RULE_tf_input_declaration = 145
    RULE_tf_output_declaration = 146
    RULE_tf_inout_declaration = 147
    RULE_task_port_type = 148
    RULE_block_item_declaration = 149
    RULE_list_of_block_variable_identifiers = 150
    RULE_list_of_block_real_identifiers = 151
    RULE_block_variable_type = 152
    RULE_block_real_type = 153
    RULE_gate_instantiation = 154
    RULE_cmos_switch_instance = 155
    RULE_enable_gate_instance = 156
    RULE_mos_switch_instance = 157
    RULE_n_input_gate_instance = 158
    RULE_n_output_gate_instance = 159
    RULE_pass_switch_instance = 160
    RULE_pass_enable_switch_instance = 161
    RULE_pull_gate_instance = 162
    RULE_name_of_gate_instance = 163
    RULE_pulldown_strength = 164
    RULE_pullup_strength = 165
    RULE_enable_terminal = 166
    RULE_inout_terminal = 167
    RULE_input_terminal = 168
    RULE_ncontrol_terminal = 169
    RULE_output_terminal = 170
    RULE_pcontrol_terminal = 171
    RULE_cmos_switchtype = 172
    RULE_enable_gatetype = 173
    RULE_mos_switchtype = 174
    RULE_n_input_gatetype = 175
    RULE_n_output_gatetype = 176
    RULE_pass_en_switchtype = 177
    RULE_pass_switchtype = 178
    RULE_module_instantiation = 179
    RULE_parameter_value_assignment = 180
    RULE_list_of_parameter_assignments = 181
    RULE_ordered_parameter_assignment = 182
    RULE_named_parameter_assignment = 183
    RULE_module_instance = 184
    RULE_name_of_module_instance = 185
    RULE_list_of_port_connections = 186
    RULE_ordered_port_connection = 187
    RULE_named_port_connection = 188
    RULE_generate_region = 189
    RULE_genvar_declaration = 190
    RULE_list_of_genvar_identifiers = 191
    RULE_loop_generate_construct = 192
    RULE_genvar_initialization = 193
    RULE_genvar_expression = 194
    RULE_genvar_iteration = 195
    RULE_genvar_primary = 196
    RULE_conditional_generate_construct = 197
    RULE_if_generate_construct = 198
    RULE_case_generate_construct = 199
    RULE_generate_block = 200
    RULE_generate_block_or_null = 201
    RULE_continuous_assign = 202
    RULE_list_of_net_assignments = 203
    RULE_net_assignment = 204
    RULE_initial_construct = 205
    RULE_always_construct = 206
    RULE_blocking_assignment = 207
    RULE_nonblocking_assignment = 208
    RULE_procedural_continuous_assignments = 209
    RULE_variable_assignment = 210
    RULE_par_block = 211
    RULE_seq_block = 212
    RULE_statement = 213
    RULE_statement_or_null = 214
    RULE_function_statement = 215
    RULE_delay_control = 216
    RULE_delay_or_event_control = 217
    RULE_disable_statement = 218
    RULE_event_control = 219
    RULE_event_trigger = 220
    RULE_event_expression = 221
    RULE_event_primary = 222
    RULE_procedural_timing_control = 223
    RULE_procedural_timing_control_statement = 224
    RULE_wait_statement = 225
    RULE_conditional_statement = 226
    RULE_case_statement = 227
    RULE_case_item = 228
    RULE_loop_statement = 229
    RULE_system_task_enable = 230
    RULE_task_enable = 231
    RULE_specify_block = 232
    RULE_specify_item = 233
    RULE_pulsestyle_declaration = 234
    RULE_showcancelled_declaration = 235
    RULE_path_declaration = 236
    RULE_simple_path_declaration = 237
    RULE_parallel_path_description = 238
    RULE_full_path_description = 239
    RULE_list_of_path_inputs = 240
    RULE_list_of_path_outputs = 241
    RULE_specify_input_terminal_descriptor = 242
    RULE_specify_output_terminal_descriptor = 243
    RULE_input_identifier = 244
    RULE_output_identifier = 245
    RULE_path_delay_value = 246
    RULE_list_of_path_delay_expressions = 247
    RULE_t_path_delay_expression = 248
    RULE_trise_path_delay_expression = 249
    RULE_tfall_path_delay_expression = 250
    RULE_tz_path_delay_expression = 251
    RULE_t01_path_delay_expression = 252
    RULE_t10_path_delay_expression = 253
    RULE_t0z_path_delay_expression = 254
    RULE_tz1_path_delay_expression = 255
    RULE_t1z_path_delay_expression = 256
    RULE_tz0_path_delay_expression = 257
    RULE_t0x_path_delay_expression = 258
    RULE_tx1_path_delay_expression = 259
    RULE_t1x_path_delay_expression = 260
    RULE_tx0_path_delay_expression = 261
    RULE_txz_path_delay_expression = 262
    RULE_tzx_path_delay_expression = 263
    RULE_path_delay_expression = 264
    RULE_edge_sensitive_path_declaration = 265
    RULE_parallel_edge_sensitive_path_description = 266
    RULE_full_edge_sensitive_path_description = 267
    RULE_data_source_expression = 268
    RULE_edge_identifier = 269
    RULE_state_dependent_path_declaration = 270
    RULE_polarity_operator = 271
    RULE_concatenation = 272
    RULE_constant_concatenation = 273
    RULE_constant_multiple_concatenation = 274
    RULE_module_path_concatenation = 275
    RULE_module_path_multiple_concatenation = 276
    RULE_multiple_concatenation = 277
    RULE_constant_function_call = 278
    RULE_constant_system_function_call = 279
    RULE_function_call = 280
    RULE_system_function_call = 281
    RULE_base_expression = 282
    RULE_constant_base_expression = 283
    RULE_constant_expression = 284
    RULE_constant_mintypmax_expression = 285
    RULE_constant_range_expression = 286
    RULE_dimension_constant_expression = 287
    RULE_expression = 288
    RULE_lsb_constant_expression = 289
    RULE_mintypmax_expression = 290
    RULE_module_path_expression = 291
    RULE_module_path_mintypmax_expression = 292
    RULE_msb_constant_expression = 293
    RULE_range_expression = 294
    RULE_width_constant_expression = 295
    RULE_constant_primary = 296
    RULE_module_path_primary = 297
    RULE_primary = 298
    RULE_net_lvalue = 299
    RULE_variable_lvalue = 300
    RULE_unary_operator = 301
    RULE_binary_operator = 302
    RULE_unary_module_path_operator = 303
    RULE_binary_module_path_operator = 304
    RULE_number = 305
    RULE_attribute_instance = 306
    RULE_attr_spec = 307
    RULE_attr_name = 308
    RULE_block_identifier = 309
    RULE_cell_identifier = 310
    RULE_config_identifier = 311
    RULE_event_identifier = 312
    RULE_function_identifier = 313
    RULE_gate_instance_identifier = 314
    RULE_generate_block_identifier = 315
    RULE_genvar_identifier = 316
    RULE_hierarchical_block_identifier = 317
    RULE_hierarchical_event_identifier = 318
    RULE_hierarchical_function_identifier = 319
    RULE_hierarchical_identifier = 320
    RULE_hierarchical_net_identifier = 321
    RULE_hierarchical_parameter_identifier = 322
    RULE_hierarchical_variable_identifier = 323
    RULE_hierarchical_task_identifier = 324
    RULE_identifier = 325
    RULE_inout_port_identifier = 326
    RULE_input_port_identifier = 327
    RULE_instance_identifier = 328
    RULE_library_identifier = 329
    RULE_module_identifier = 330
    RULE_module_instance_identifier = 331
    RULE_net_identifier = 332
    RULE_output_port_identifier = 333
    RULE_parameter_identifier = 334
    RULE_port_identifier = 335
    RULE_real_identifier = 336
    RULE_specparam_identifier = 337
    RULE_system_function_identifier = 338
    RULE_system_task_identifier = 339
    RULE_task_identifier = 340
    RULE_terminal_identifier = 341
    RULE_topmodule_identifier = 342
    RULE_udp_identifier = 343
    RULE_udp_instance_identifier = 344
    RULE_variable_identifier = 345

    ruleNames =  [ "display_tasks", "display_task_name", "list_of_arguments", 
                   "argument", "strobe_tasks", "strobe_task_name", "monitor_tasks", 
                   "monitor_task_name", "file_open_function", "file_close_task", 
                   "multi_channel_descriptor", "fd", "file_name", "type_", 
                   "file_output_tasks", "file_output_task_name", "load_memory_tasks", 
                   "memory_name", "start_addr", "finish_addr", "filename", 
                   "finish_task", "finish_number", "stop_task", "time_function", 
                   "stime_function", "realtime_function", "conversion_functions", 
                   "conversion_function_name", "constant_argument", "random_function", 
                   "seed", "dist_functions", "start_", "end", "mean", "standard_deviation", 
                   "degree_of_freedom", "k_stage", "math_functions", "integer_math_functions", 
                   "real_math_functions", "single_argument_real_math_function_name", 
                   "double_argument_real_math_function_name", "dumpfile_task", 
                   "dumpvars_task", "list_of_modules_or_variables", "module_or_variable", 
                   "levels", "dumpoff_task", "dumpon_task", "dumpall_task", 
                   "dumplimit_task", "file_size", "dumpflush_task", "dumpports_task", 
                   "scope_list", "file_pathname", "dumpportsoff_task", "dumpportson_task", 
                   "dumpportsall_task", "dumpportslimit_task", "dumpportsflush_task", 
                   "library_text", "library_description", "library_declaration", 
                   "include_statement", "source_text", "description", "module_declaration", 
                   "module_keyword", "module_parameter_port_list", "list_of_ports", 
                   "list_of_port_declarations", "port", "port_expression", 
                   "port_reference", "port_declaration", "module_item", 
                   "module_or_generate_item", "module_or_generate_item_declaration", 
                   "non_port_module_item", "parameter_override", "config_declaration", 
                   "design_statement", "config_rule_statement", "default_clause", 
                   "inst_clause", "inst_name", "cell_clause", "liblist_clause", 
                   "use_clause", "local_parameter_declaration", "parameter_declaration", 
                   "specparam_declaration", "parameter_type", "inout_declaration", 
                   "input_declaration", "output_declaration", "event_declaration", 
                   "integer_declaration", "net_declaration", "real_declaration", 
                   "realtime_declaration", "reg_declaration", "time_declaration", 
                   "net_type", "output_variable_type", "real_type", "variable_type", 
                   "drive_strength", "strength0", "strength1", "charge_strength", 
                   "delay3", "delay2", "delay_value", "list_of_defparam_assignments", 
                   "list_of_event_identifiers", "list_of_net_decl_assignments", 
                   "list_of_net_identifiers", "list_of_param_assignments", 
                   "list_of_port_identifiers", "list_of_real_identifiers", 
                   "list_of_specparam_assignments", "list_of_variable_identifiers", 
                   "list_of_variable_port_identifiers", "defparam_assignment", 
                   "net_decl_assignment", "param_assignment", "specparam_assignment", 
                   "pulse_control_specparam", "error_limit_value", "reject_limit_value", 
                   "limit_value", "dimension", "range_", "function_declaration", 
                   "function_item_declaration", "function_port_list", "function_range_or_type", 
                   "task_declaration", "task_item_declaration", "task_port_list", 
                   "task_port_item", "tf_input_declaration", "tf_output_declaration", 
                   "tf_inout_declaration", "task_port_type", "block_item_declaration", 
                   "list_of_block_variable_identifiers", "list_of_block_real_identifiers", 
                   "block_variable_type", "block_real_type", "gate_instantiation", 
                   "cmos_switch_instance", "enable_gate_instance", "mos_switch_instance", 
                   "n_input_gate_instance", "n_output_gate_instance", "pass_switch_instance", 
                   "pass_enable_switch_instance", "pull_gate_instance", 
                   "name_of_gate_instance", "pulldown_strength", "pullup_strength", 
                   "enable_terminal", "inout_terminal", "input_terminal", 
                   "ncontrol_terminal", "output_terminal", "pcontrol_terminal", 
                   "cmos_switchtype", "enable_gatetype", "mos_switchtype", 
                   "n_input_gatetype", "n_output_gatetype", "pass_en_switchtype", 
                   "pass_switchtype", "module_instantiation", "parameter_value_assignment", 
                   "list_of_parameter_assignments", "ordered_parameter_assignment", 
                   "named_parameter_assignment", "module_instance", "name_of_module_instance", 
                   "list_of_port_connections", "ordered_port_connection", 
                   "named_port_connection", "generate_region", "genvar_declaration", 
                   "list_of_genvar_identifiers", "loop_generate_construct", 
                   "genvar_initialization", "genvar_expression", "genvar_iteration", 
                   "genvar_primary", "conditional_generate_construct", "if_generate_construct", 
                   "case_generate_construct", "generate_block", "generate_block_or_null", 
                   "continuous_assign", "list_of_net_assignments", "net_assignment", 
                   "initial_construct", "always_construct", "blocking_assignment", 
                   "nonblocking_assignment", "procedural_continuous_assignments", 
                   "variable_assignment", "par_block", "seq_block", "statement", 
                   "statement_or_null", "function_statement", "delay_control", 
                   "delay_or_event_control", "disable_statement", "event_control", 
                   "event_trigger", "event_expression", "event_primary", 
                   "procedural_timing_control", "procedural_timing_control_statement", 
                   "wait_statement", "conditional_statement", "case_statement", 
                   "case_item", "loop_statement", "system_task_enable", 
                   "task_enable", "specify_block", "specify_item", "pulsestyle_declaration", 
                   "showcancelled_declaration", "path_declaration", "simple_path_declaration", 
                   "parallel_path_description", "full_path_description", 
                   "list_of_path_inputs", "list_of_path_outputs", "specify_input_terminal_descriptor", 
                   "specify_output_terminal_descriptor", "input_identifier", 
                   "output_identifier", "path_delay_value", "list_of_path_delay_expressions", 
                   "t_path_delay_expression", "trise_path_delay_expression", 
                   "tfall_path_delay_expression", "tz_path_delay_expression", 
                   "t01_path_delay_expression", "t10_path_delay_expression", 
                   "t0z_path_delay_expression", "tz1_path_delay_expression", 
                   "t1z_path_delay_expression", "tz0_path_delay_expression", 
                   "t0x_path_delay_expression", "tx1_path_delay_expression", 
                   "t1x_path_delay_expression", "tx0_path_delay_expression", 
                   "txz_path_delay_expression", "tzx_path_delay_expression", 
                   "path_delay_expression", "edge_sensitive_path_declaration", 
                   "parallel_edge_sensitive_path_description", "full_edge_sensitive_path_description", 
                   "data_source_expression", "edge_identifier", "state_dependent_path_declaration", 
                   "polarity_operator", "concatenation", "constant_concatenation", 
                   "constant_multiple_concatenation", "module_path_concatenation", 
                   "module_path_multiple_concatenation", "multiple_concatenation", 
                   "constant_function_call", "constant_system_function_call", 
                   "function_call", "system_function_call", "base_expression", 
                   "constant_base_expression", "constant_expression", "constant_mintypmax_expression", 
                   "constant_range_expression", "dimension_constant_expression", 
                   "expression", "lsb_constant_expression", "mintypmax_expression", 
                   "module_path_expression", "module_path_mintypmax_expression", 
                   "msb_constant_expression", "range_expression", "width_constant_expression", 
                   "constant_primary", "module_path_primary", "primary", 
                   "net_lvalue", "variable_lvalue", "unary_operator", "binary_operator", 
                   "unary_module_path_operator", "binary_module_path_operator", 
                   "number", "attribute_instance", "attr_spec", "attr_name", 
                   "block_identifier", "cell_identifier", "config_identifier", 
                   "event_identifier", "function_identifier", "gate_instance_identifier", 
                   "generate_block_identifier", "genvar_identifier", "hierarchical_block_identifier", 
                   "hierarchical_event_identifier", "hierarchical_function_identifier", 
                   "hierarchical_identifier", "hierarchical_net_identifier", 
                   "hierarchical_parameter_identifier", "hierarchical_variable_identifier", 
                   "hierarchical_task_identifier", "identifier", "inout_port_identifier", 
                   "input_port_identifier", "instance_identifier", "library_identifier", 
                   "module_identifier", "module_instance_identifier", "net_identifier", 
                   "output_port_identifier", "parameter_identifier", "port_identifier", 
                   "real_identifier", "specparam_identifier", "system_function_identifier", 
                   "system_task_identifier", "task_identifier", "terminal_identifier", 
                   "topmodule_identifier", "udp_identifier", "udp_instance_identifier", 
                   "variable_identifier" ]

    EOF = Token.EOF
    ALWAYS=1
    AND=2
    ASSIGN=3
    AUTOMATIC=4
    BEGIN=5
    BUF=6
    BUFIF0=7
    BUFIF1=8
    CASE=9
    CASEX=10
    CASEZ=11
    CELL=12
    CMOS=13
    CONFIG=14
    DEASSIGN=15
    DEFAULT=16
    DEFPARAM=17
    DESIGN=18
    DISABLE=19
    EDGE=20
    ELSE=21
    END=22
    ENDCASE=23
    ENDCONFIG=24
    ENDFUNCTION=25
    ENDGENERATE=26
    ENDMODULE=27
    ENDPRIMITIVE=28
    ENDSPECIFY=29
    ENDTABLE=30
    ENDTASK=31
    EVENT=32
    FOR=33
    FORCE=34
    FOREVER=35
    FORK=36
    FUNCTION=37
    GENERATE=38
    GENVAR=39
    HIGHZ0=40
    HIGHZ1=41
    IF=42
    IFNONE=43
    INCDIR=44
    INCLUDE=45
    INITIAL=46
    INOUT=47
    INPUT=48
    INSTANCE=49
    INTEGER=50
    JOIN=51
    LARGE=52
    LIBLIST=53
    LIBRARY=54
    LOCALPARAM=55
    MACROMODULE=56
    MEDIUM=57
    MODULE=58
    NAND=59
    NEGEDGE=60
    NMOS=61
    NOR=62
    NOSHOWCANCELLED=63
    NOT=64
    NOTIF0=65
    NOTIF1=66
    OR=67
    OUTPUT=68
    PARAMETER=69
    PMOS=70
    POSEDGE=71
    PRIMITIVE=72
    PULL0=73
    PULL1=74
    PULLDOWN=75
    PULLUP=76
    PULSESTYLE_ONEVENT=77
    PULSESTYLE_ONDETECT=78
    RCMOS=79
    REAL=80
    REALTIME=81
    REG=82
    RELEASE=83
    REPEAT=84
    RNMOS=85
    RPMOS=86
    RTRAN=87
    RTRANIF0=88
    RTRANIF1=89
    SCALARED=90
    SHOWCANCELLED=91
    SIGNED=92
    SMALL=93
    SPECIFY=94
    SPECPARAM=95
    STRONG0=96
    STRONG1=97
    SUPPLY0=98
    SUPPLY1=99
    TABLE=100
    TASK=101
    TIME=102
    TRAN=103
    TRANIF0=104
    TRANIF1=105
    TRI=106
    TRI0=107
    TRI1=108
    TRIAND=109
    TRIOR=110
    TRIREG=111
    UNSIGNED=112
    USE=113
    UWIRE=114
    VECTORED=115
    WAIT=116
    WAND=117
    WEAK0=118
    WEAK1=119
    WHILE=120
    WIRE=121
    WOR=122
    XNOR=123
    XOR=124
    DOLLAR_DISPLAY=125
    DOLLAR_DISPLAYB=126
    DOLLAR_DISPLAYH=127
    DOLLAR_DISPLAYO=128
    DOLLAR_WRITE=129
    DOLLAR_WRITEB=130
    DOLLAR_WRITEH=131
    DOLLAR_WRITEO=132
    DOLLAR_STROBE=133
    DOLLAR_STROBEB=134
    DOLLAR_STROBEH=135
    DOLLAR_STROBEO=136
    DOLLAR_MONITOR=137
    DOLLAR_MONITORB=138
    DOLLAR_MONITORH=139
    DOLLAR_MONITORO=140
    DOLLAR_MONITOROFF=141
    DOLLAR_MONITORON=142
    DOLLAR_FCLOSE=143
    DOLLAR_FDISPLAY=144
    DOLLAR_FDISPLAYB=145
    DOLLAR_FDISPLAYH=146
    DOLLAR_FDISPLAYO=147
    DOLLAR_FSTROBE=148
    DOLLAR_FSTROBEB=149
    DOLLAR_FSTROBEH=150
    DOLLAR_FSTROBEO=151
    DOLLAR_SWRITE=152
    DOLLAR_SWRITEB=153
    DOLLAR_SWRITEH=154
    DOLLAR_SWRITEO=155
    DOLLAR_FSCANF=156
    DOLLAR_FREAD=157
    DOLLAR_FSEEK=158
    DOLLAR_FFLUSH=159
    DOLLAR_FEOF=160
    DOLLAR_SDF_ANNOTATE=161
    DOLLAR_FOPEN=162
    DOLLAR_FWRITE=163
    DOLLAR_FWRITEB=164
    DOLLAR_FWRITEH=165
    DOLLAR_FWRITEO=166
    DOLLAR_FMONITOR=167
    DOLLAR_FMONITORB=168
    DOLLAR_FMONITORH=169
    DOLLAR_FMONITORO=170
    DOLLAR_SFORMAT=171
    DOLLAR_FGETC=172
    DOLLAR_UNGETC=173
    DOLLAR_FGETS=174
    DOLLAR_SSCANF=175
    DOLLAR_REWIND=176
    DOLLAR_FTELL=177
    DOLLAR_FERROR=178
    DOLLAR_READMEMB=179
    DOLLAR_READMEMH=180
    DOLLAR_PRINTTIMESCALE=181
    DOLLAR_TIMEFORMAT=182
    DOLLAR_FINISH=183
    DOLLAR_STOP=184
    DOLLAR_ASYNC_AND_ARRAY=185
    DOLLAR_ASYNC_NAND_ARRAY=186
    DOLLAR_ASYNC_OR_ARRAY=187
    DOLLAR_ASYNC_NOR_ARRAY=188
    DOLLAR_SYNC_AND_ARRAY=189
    DOLLAR_SYNC_NAND_ARRAY=190
    DOLLAR_SYNC_OR_ARRAY=191
    DOLLAR_SYNC_NOR_ARRAY=192
    DOLLAR_ASYNC_AND_PLANE=193
    DOLLAR_ASYNC_NAND_PLANE=194
    DOLLAR_ASYNC_OR_PLANE=195
    DOLLAR_ASYNC_NOR_PLANE=196
    DOLLAR_SYNC_AND_PLANE=197
    DOLLAR_SYNC_NAND_PLANE=198
    DOLLAR_SYNC_OR_PLANE=199
    DOLLAR_SYNC_NOR_PLANE=200
    DOLLAR_Q_INITIALIZE=201
    DOLLAR_Q_REMOVE=202
    DOLLAR_Q_EXAM=203
    DOLLAR_Q_ADD=204
    DOLLAR_Q_FULL=205
    DOLLAR_REALTIME=206
    DOLLAR_TIME=207
    DOLLAR_STIME=208
    DOLLAR_BITSTOREAL=209
    DOLLAR_ITOR=210
    DOLLAR_SIGNED=211
    DOLLAR_REALTOBITS=212
    DOLLAR_RTOI=213
    DOLLAR_UNSIGNED=214
    DOLLAR_RANDOM=215
    DOLLAR_DIST_ERLANG=216
    DOLLAR_DIST_NORMAL=217
    DOLLAR_DIST_T=218
    DOLLAR_DIST_CHI_SQUARE=219
    DOLLAR_DIST_EXPONENTIAL=220
    DOLLAR_DIST_POISSON=221
    DOLLAR_DIST_UNIFORM=222
    DOLLAR_TEST_PLUSARGS=223
    DOLLAR_VALUE_PLUSARGS=224
    DOLLAR_CLOG2=225
    DOLLAR_LN=226
    DOLLAR_LOG10=227
    DOLLAR_EXP=228
    DOLLAR_SQRT=229
    DOLLAR_POW=230
    DOLLAR_FLOOR=231
    DOLLAR_CEIL=232
    DOLLAR_SIN=233
    DOLLAR_COS=234
    DOLLAR_TAN=235
    DOLLAR_ASIN=236
    DOLLAR_ACOS=237
    DOLLAR_ATAN=238
    DOLLAR_ATAN2=239
    DOLLAR_HYPOT=240
    DOLLAR_SINH=241
    DOLLAR_COSH=242
    DOLLAR_TANH=243
    DOLLAR_ASINH=244
    DOLLAR_ACOSH=245
    DOLLAR_ATANH=246
    DOLLAR_DUMPFILE=247
    DOLLAR_DUMPVARS=248
    DOLLAR_DUMPOFF=249
    DOLLAR_DUMPON=250
    DOLLAR_DUMPALL=251
    DOLLAR_DUMPLIMIT=252
    DOLLAR_DUMPFLUSH=253
    DOLLAR_END=254
    DOLLAR_COMMENT=255
    DOLLAR_DATE=256
    DOLLAR_ENDDEFINITIONS=257
    DOLLAR_SCOPE=258
    DOLLAR_TIMESCALE=259
    DOLLAR_UPSCOPE=260
    DOLLAR_VAR=261
    DOLLAR_VERSION=262
    DOLLAR_DUMPPORTS=263
    DOLLAR_DUMPPORTSOFF=264
    DOLLAR_DUMPPORTSON=265
    DOLLAR_DUMPPORTSALL=266
    DOLLAR_DUMPPORTSLIMIT=267
    DOLLAR_DUMPPORTSFLUSH=268
    DOLLAR_VCDCLOSE=269
    DOLLAR_SETUP=270
    DOLLAR_HOLD=271
    DOLLAR_SETUPHOLD=272
    DOLLAR_RECOVERY=273
    DOLLAR_REMOVAL=274
    DOLLAR_RECREM=275
    DOLLAR_SKEW=276
    DOLLAR_TIMESKEW=277
    DOLLAR_FULLSKEW=278
    DOLLAR_PERIOD=279
    DOLLAR_WIDTH=280
    DOLLAR_NOCHANGE=281
    REAL_NUMBER=282
    DECIMAL_NUMBER=283
    BINARY_NUMBER=284
    OCTAL_NUMBER=285
    HEX_NUMBER=286
    STRING=287
    ONE_LINE_COMMENT=288
    BLOCK_COMMENT=289
    ESCAPED_IDENTIFIER=290
    SIMPLE_IDENTIFIER=291
    SYSTEM_TF_IDENTIFIER=292
    WHITE_SPACE_REGION=293
    LEFT_PARENTHESIS=294
    RIGHT_PARENTHESIS=295
    LEFT_BRACKET=296
    RIGHT_BRACKET=297
    LEFT_BRACE=298
    RIGHT_BRACE=299
    PLUS=300
    MINUS=301
    EXCLAMATION_MARK=302
    TILDE=303
    AMPERSAND=304
    TILDE_AMPERSAND=305
    VERTICAL_BAR=306
    TILDE_VERTICAL_BAR=307
    CARET=308
    TILDE_CARET=309
    CARET_TILDE=310
    ASTERISK=311
    PERCENT=312
    DOUBLE_EQUAL=313
    EXCLAMATION_MARK_EQUAL=314
    TRIPLE_EQUAL=315
    EXCLAMATION_MARK_DOUBLE_EQUAL=316
    DOUBLE_AMPERSAND=317
    DOUBLE_VERTICAL_BAR=318
    DOUBLE_ASTERISK=319
    LESS_THAN=320
    LESS_THAN_EQUAL=321
    GREATER_THAN=322
    GREATER_THAN_EQUAL=323
    DOUBLE_GREATER_THAN=324
    DOUBLE_LESS_THAN=325
    TRIPLE_GREATER_THAN=326
    TRIPLE_LESS_THAN=327
    DOT=328
    COMMA=329
    COLON=330
    SEMICOLON=331
    SLASH=332
    EQUAL=333
    QUESTION_MARK=334
    AT=335
    HASH=336
    GRAVE_ACCENT=337
    PLUS_COLON=338
    MINUS_COLON=339
    MINUS_GREATER_THAN=340
    EQUAL_GREATER_THAN=341
    ASTERISK_GREATER_THAN=342
    TRIPLE_AMPERSAND=343
    PATHPULSE_DOLLAR=344
    FILE_PATH_SPEC=345
    MINUS_INCDIR=346
    LIBRARY_NEWLINE=347
    DIRECTIVE_BEGIN_KEYWORDS=348
    DIRECTIVE_CELLDEFINE=349
    DIRECTIVE_DEFAULT_NETTYPE=350
    DIRECTIVE_DEFINE=351
    DIRECTIVE_ELSE=352
    DIRECTIVE_ELSIF=353
    DIRECTIVE_END_KEYWORDS=354
    DIRECTIVE_ENDCELLDEFINE=355
    DIRECTIVE_ENDIF=356
    DIRECTIVE_IFDEF=357
    DIRECTIVE_IFNDEF=358
    DIRECTIVE_INCLUDE=359
    DIRECTIVE_LINE=360
    DIRECTIVE_NOUNCONNECTED_DRIVE=361
    DIRECTIVE_RESETALL=362
    DIRECTIVE_TIMESCALE=363
    DIRECTIVE_UNCONNECTED_DRIVE=364
    DIRECTIVE_UNDEF=365
    DEFAULT_NETTYPE_VALUE=366
    TIME_UNIT=367
    UNCONNECTED_DRIVE_VALUE=368
    DIRECTIVE_NUMBER=369
    DIRECTIVE_STRING=370
    DIRECTIVE_IDENTIFIER=371
    DIRECTIVE_SLASH=372
    DIRECTIVE_COMMENT=373
    DIRECTIVE_WHITE_SPACE=374
    DIRECTIVE_NEWLINE=375
    MACRO_TEXT=376
    MACRO_TEXT_BACKSLASH_NEWLINE=377
    DIRECTIVE_LIST_OF_ARGUMENTS=378
    MACRO_USAGE_BACKSLASH_NEWLINE=379
    ANY_OTHER_TOKEN=380
    SOURCE_TEXT=381
    SOURCE_TEXT_BACKSLASH_NEWLINE=382

    def __init__(self, input:TokenStream, output:TextIO = sys.stdout):
        super().__init__(input, output)
        self.checkVersion("4.9.3")
        self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache)
        self._predicates = None




    class Display_tasksContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def display_task_name(self):
            return self.getTypedRuleContext(VerilogParser.Display_task_nameContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_argumentsContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_display_tasks

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDisplay_tasks" ):
                listener.enterDisplay_tasks(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDisplay_tasks" ):
                listener.exitDisplay_tasks(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDisplay_tasks" ):
                return visitor.visitDisplay_tasks(self)
            else:
                return visitor.visitChildren(self)




    def display_tasks(self):

        localctx = VerilogParser.Display_tasksContext(self, self._ctx, self.state)
        self.enterRule(localctx, 0, self.RULE_display_tasks)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 692
            self.display_task_name()
            self.state = 697
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 693
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 694
                self.list_of_arguments()
                self.state = 695
                self.match(VerilogParser.RIGHT_PARENTHESIS)


            self.state = 699
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Display_task_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DISPLAY(self):
            return self.getToken(VerilogParser.DOLLAR_DISPLAY, 0)

        def DOLLAR_DISPLAYB(self):
            return self.getToken(VerilogParser.DOLLAR_DISPLAYB, 0)

        def DOLLAR_DISPLAYO(self):
            return self.getToken(VerilogParser.DOLLAR_DISPLAYO, 0)

        def DOLLAR_DISPLAYH(self):
            return self.getToken(VerilogParser.DOLLAR_DISPLAYH, 0)

        def DOLLAR_WRITE(self):
            return self.getToken(VerilogParser.DOLLAR_WRITE, 0)

        def DOLLAR_WRITEB(self):
            return self.getToken(VerilogParser.DOLLAR_WRITEB, 0)

        def DOLLAR_WRITEO(self):
            return self.getToken(VerilogParser.DOLLAR_WRITEO, 0)

        def DOLLAR_WRITEH(self):
            return self.getToken(VerilogParser.DOLLAR_WRITEH, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_display_task_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDisplay_task_name" ):
                listener.enterDisplay_task_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDisplay_task_name" ):
                listener.exitDisplay_task_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDisplay_task_name" ):
                return visitor.visitDisplay_task_name(self)
            else:
                return visitor.visitChildren(self)




    def display_task_name(self):

        localctx = VerilogParser.Display_task_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 2, self.RULE_display_task_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 701
            _la = self._input.LA(1)
            if not(((((_la - 125)) & ~0x3f) == 0 and ((1 << (_la - 125)) & ((1 << (VerilogParser.DOLLAR_DISPLAY - 125)) | (1 << (VerilogParser.DOLLAR_DISPLAYB - 125)) | (1 << (VerilogParser.DOLLAR_DISPLAYH - 125)) | (1 << (VerilogParser.DOLLAR_DISPLAYO - 125)) | (1 << (VerilogParser.DOLLAR_WRITE - 125)) | (1 << (VerilogParser.DOLLAR_WRITEB - 125)) | (1 << (VerilogParser.DOLLAR_WRITEH - 125)) | (1 << (VerilogParser.DOLLAR_WRITEO - 125)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_argumentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def argument(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ArgumentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ArgumentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_arguments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_arguments" ):
                listener.enterList_of_arguments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_arguments" ):
                listener.exitList_of_arguments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_arguments" ):
                return visitor.visitList_of_arguments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_arguments(self):

        localctx = VerilogParser.List_of_argumentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 4, self.RULE_list_of_arguments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 704
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.REALTIME or _la==VerilogParser.TIME or ((((_la - 208)) & ~0x3f) == 0 and ((1 << (_la - 208)) & ((1 << (VerilogParser.DOLLAR_STIME - 208)) | (1 << (VerilogParser.DOLLAR_BITSTOREAL - 208)) | (1 << (VerilogParser.DOLLAR_ITOR - 208)) | (1 << (VerilogParser.DOLLAR_SIGNED - 208)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 208)) | (1 << (VerilogParser.DOLLAR_RTOI - 208)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 208)) | (1 << (VerilogParser.DOLLAR_RANDOM - 208)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 208)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 208)) | (1 << (VerilogParser.DOLLAR_DIST_T - 208)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 208)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 208)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 208)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 208)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 208)) | (1 << (VerilogParser.DOLLAR_LN - 208)) | (1 << (VerilogParser.DOLLAR_LOG10 - 208)) | (1 << (VerilogParser.DOLLAR_EXP - 208)) | (1 << (VerilogParser.DOLLAR_SQRT - 208)) | (1 << (VerilogParser.DOLLAR_POW - 208)) | (1 << (VerilogParser.DOLLAR_FLOOR - 208)) | (1 << (VerilogParser.DOLLAR_CEIL - 208)) | (1 << (VerilogParser.DOLLAR_SIN - 208)) | (1 << (VerilogParser.DOLLAR_COS - 208)) | (1 << (VerilogParser.DOLLAR_TAN - 208)) | (1 << (VerilogParser.DOLLAR_ASIN - 208)) | (1 << (VerilogParser.DOLLAR_ACOS - 208)) | (1 << (VerilogParser.DOLLAR_ATAN - 208)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 208)) | (1 << (VerilogParser.DOLLAR_HYPOT - 208)) | (1 << (VerilogParser.DOLLAR_SINH - 208)) | (1 << (VerilogParser.DOLLAR_COSH - 208)) | (1 << (VerilogParser.DOLLAR_TANH - 208)) | (1 << (VerilogParser.DOLLAR_ASINH - 208)) | (1 << (VerilogParser.DOLLAR_ACOSH - 208)) | (1 << (VerilogParser.DOLLAR_ATANH - 208)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                self.state = 703
                self.argument()


            self.state = 710
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 706
                self.match(VerilogParser.COMMA)
                self.state = 707
                self.argument()
                self.state = 712
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ArgumentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def time_function(self):
            return self.getTypedRuleContext(VerilogParser.Time_functionContext,0)


        def stime_function(self):
            return self.getTypedRuleContext(VerilogParser.Stime_functionContext,0)


        def realtime_function(self):
            return self.getTypedRuleContext(VerilogParser.Realtime_functionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_argument

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArgument" ):
                listener.enterArgument(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArgument" ):
                listener.exitArgument(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArgument" ):
                return visitor.visitArgument(self)
            else:
                return visitor.visitChildren(self)




    def argument(self):

        localctx = VerilogParser.ArgumentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 6, self.RULE_argument)
        try:
            self.state = 718
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,3,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 713
                self.expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 714
                self.constant_expression(0)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 715
                self.time_function()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 716
                self.stime_function()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 717
                self.realtime_function()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Strobe_tasksContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def strobe_task_name(self):
            return self.getTypedRuleContext(VerilogParser.Strobe_task_nameContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_argumentsContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_strobe_tasks

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrobe_tasks" ):
                listener.enterStrobe_tasks(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrobe_tasks" ):
                listener.exitStrobe_tasks(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrobe_tasks" ):
                return visitor.visitStrobe_tasks(self)
            else:
                return visitor.visitChildren(self)




    def strobe_tasks(self):

        localctx = VerilogParser.Strobe_tasksContext(self, self._ctx, self.state)
        self.enterRule(localctx, 8, self.RULE_strobe_tasks)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 720
            self.strobe_task_name()
            self.state = 725
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 721
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 722
                self.list_of_arguments()
                self.state = 723
                self.match(VerilogParser.RIGHT_PARENTHESIS)


            self.state = 727
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Strobe_task_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_STROBE(self):
            return self.getToken(VerilogParser.DOLLAR_STROBE, 0)

        def DOLLAR_STROBEB(self):
            return self.getToken(VerilogParser.DOLLAR_STROBEB, 0)

        def DOLLAR_STROBEO(self):
            return self.getToken(VerilogParser.DOLLAR_STROBEO, 0)

        def DOLLAR_STROBEH(self):
            return self.getToken(VerilogParser.DOLLAR_STROBEH, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_strobe_task_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrobe_task_name" ):
                listener.enterStrobe_task_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrobe_task_name" ):
                listener.exitStrobe_task_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrobe_task_name" ):
                return visitor.visitStrobe_task_name(self)
            else:
                return visitor.visitChildren(self)




    def strobe_task_name(self):

        localctx = VerilogParser.Strobe_task_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 10, self.RULE_strobe_task_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 729
            _la = self._input.LA(1)
            if not(((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (VerilogParser.DOLLAR_STROBE - 133)) | (1 << (VerilogParser.DOLLAR_STROBEB - 133)) | (1 << (VerilogParser.DOLLAR_STROBEH - 133)) | (1 << (VerilogParser.DOLLAR_STROBEO - 133)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Monitor_tasksContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def monitor_task_name(self):
            return self.getTypedRuleContext(VerilogParser.Monitor_task_nameContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_argumentsContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def DOLLAR_MONITORON(self):
            return self.getToken(VerilogParser.DOLLAR_MONITORON, 0)

        def DOLLAR_MONITOROFF(self):
            return self.getToken(VerilogParser.DOLLAR_MONITOROFF, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_monitor_tasks

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMonitor_tasks" ):
                listener.enterMonitor_tasks(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMonitor_tasks" ):
                listener.exitMonitor_tasks(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMonitor_tasks" ):
                return visitor.visitMonitor_tasks(self)
            else:
                return visitor.visitChildren(self)




    def monitor_tasks(self):

        localctx = VerilogParser.Monitor_tasksContext(self, self._ctx, self.state)
        self.enterRule(localctx, 12, self.RULE_monitor_tasks)
        self._la = 0 # Token type
        try:
            self.state = 744
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_MONITOR, VerilogParser.DOLLAR_MONITORB, VerilogParser.DOLLAR_MONITORH, VerilogParser.DOLLAR_MONITORO]:
                self.enterOuterAlt(localctx, 1)
                self.state = 731
                self.monitor_task_name()
                self.state = 736
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 732
                    self.match(VerilogParser.LEFT_PARENTHESIS)
                    self.state = 733
                    self.list_of_arguments()
                    self.state = 734
                    self.match(VerilogParser.RIGHT_PARENTHESIS)


                self.state = 738
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.DOLLAR_MONITORON]:
                self.enterOuterAlt(localctx, 2)
                self.state = 740
                self.match(VerilogParser.DOLLAR_MONITORON)
                self.state = 741
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.DOLLAR_MONITOROFF]:
                self.enterOuterAlt(localctx, 3)
                self.state = 742
                self.match(VerilogParser.DOLLAR_MONITOROFF)
                self.state = 743
                self.match(VerilogParser.SEMICOLON)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Monitor_task_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_MONITOR(self):
            return self.getToken(VerilogParser.DOLLAR_MONITOR, 0)

        def DOLLAR_MONITORB(self):
            return self.getToken(VerilogParser.DOLLAR_MONITORB, 0)

        def DOLLAR_MONITORO(self):
            return self.getToken(VerilogParser.DOLLAR_MONITORO, 0)

        def DOLLAR_MONITORH(self):
            return self.getToken(VerilogParser.DOLLAR_MONITORH, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_monitor_task_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMonitor_task_name" ):
                listener.enterMonitor_task_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMonitor_task_name" ):
                listener.exitMonitor_task_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMonitor_task_name" ):
                return visitor.visitMonitor_task_name(self)
            else:
                return visitor.visitChildren(self)




    def monitor_task_name(self):

        localctx = VerilogParser.Monitor_task_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 14, self.RULE_monitor_task_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 746
            _la = self._input.LA(1)
            if not(((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (VerilogParser.DOLLAR_MONITOR - 137)) | (1 << (VerilogParser.DOLLAR_MONITORB - 137)) | (1 << (VerilogParser.DOLLAR_MONITORH - 137)) | (1 << (VerilogParser.DOLLAR_MONITORO - 137)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class File_open_functionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def multi_channel_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Multi_channel_descriptorContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def DOLLAR_FOPEN(self):
            return self.getToken(VerilogParser.DOLLAR_FOPEN, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def file_name(self):
            return self.getTypedRuleContext(VerilogParser.File_nameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def fd(self):
            return self.getTypedRuleContext(VerilogParser.FdContext,0)


        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def type_(self):
            return self.getTypedRuleContext(VerilogParser.Type_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_file_open_function

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_open_function" ):
                listener.enterFile_open_function(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_open_function" ):
                listener.exitFile_open_function(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_open_function" ):
                return visitor.visitFile_open_function(self)
            else:
                return visitor.visitChildren(self)




    def file_open_function(self):

        localctx = VerilogParser.File_open_functionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 16, self.RULE_file_open_function)
        try:
            self.state = 766
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,7,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 748
                self.multi_channel_descriptor()
                self.state = 749
                self.match(VerilogParser.EQUAL)
                self.state = 750
                self.match(VerilogParser.DOLLAR_FOPEN)
                self.state = 751
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 752
                self.file_name()
                self.state = 753
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 754
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 756
                self.fd()
                self.state = 757
                self.match(VerilogParser.EQUAL)
                self.state = 758
                self.match(VerilogParser.DOLLAR_FOPEN)
                self.state = 759
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 760
                self.file_name()
                self.state = 761
                self.match(VerilogParser.COMMA)
                self.state = 762
                self.type_()
                self.state = 763
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 764
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class File_close_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_FCLOSE(self):
            return self.getToken(VerilogParser.DOLLAR_FCLOSE, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def multi_channel_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Multi_channel_descriptorContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def fd(self):
            return self.getTypedRuleContext(VerilogParser.FdContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_file_close_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_close_task" ):
                listener.enterFile_close_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_close_task" ):
                listener.exitFile_close_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_close_task" ):
                return visitor.visitFile_close_task(self)
            else:
                return visitor.visitChildren(self)




    def file_close_task(self):

        localctx = VerilogParser.File_close_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 18, self.RULE_file_close_task)
        try:
            self.state = 780
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,8,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 768
                self.match(VerilogParser.DOLLAR_FCLOSE)
                self.state = 769
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 770
                self.multi_channel_descriptor()
                self.state = 771
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 772
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 774
                self.match(VerilogParser.DOLLAR_FCLOSE)
                self.state = 775
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 776
                self.fd()
                self.state = 777
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 778
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Multi_channel_descriptorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_multi_channel_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMulti_channel_descriptor" ):
                listener.enterMulti_channel_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMulti_channel_descriptor" ):
                listener.exitMulti_channel_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMulti_channel_descriptor" ):
                return visitor.visitMulti_channel_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def multi_channel_descriptor(self):

        localctx = VerilogParser.Multi_channel_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 20, self.RULE_multi_channel_descriptor)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 782
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class FdContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_fd

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFd" ):
                listener.enterFd(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFd" ):
                listener.exitFd(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFd" ):
                return visitor.visitFd(self)
            else:
                return visitor.visitChildren(self)




    def fd(self):

        localctx = VerilogParser.FdContext(self, self._ctx, self.state)
        self.enterRule(localctx, 22, self.RULE_fd)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 784
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class File_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def STRING(self):
            return self.getToken(VerilogParser.STRING, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_file_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_name" ):
                listener.enterFile_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_name" ):
                listener.exitFile_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_name" ):
                return visitor.visitFile_name(self)
            else:
                return visitor.visitChildren(self)




    def file_name(self):

        localctx = VerilogParser.File_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 24, self.RULE_file_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 786
            self.match(VerilogParser.STRING)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Type_Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def STRING(self):
            return self.getToken(VerilogParser.STRING, 0)

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_type_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterType_" ):
                listener.enterType_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitType_" ):
                listener.exitType_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitType_" ):
                return visitor.visitType_(self)
            else:
                return visitor.visitChildren(self)




    def type_(self):

        localctx = VerilogParser.Type_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 26, self.RULE_type_)
        try:
            self.state = 790
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.STRING]:
                self.enterOuterAlt(localctx, 1)
                self.state = 788
                self.match(VerilogParser.STRING)
                pass
            elif token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 789
                self.variable_identifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class File_output_tasksContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def file_output_task_name(self):
            return self.getTypedRuleContext(VerilogParser.File_output_task_nameContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def multi_channel_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Multi_channel_descriptorContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_argumentsContext,0)


        def fd(self):
            return self.getTypedRuleContext(VerilogParser.FdContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_file_output_tasks

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_output_tasks" ):
                listener.enterFile_output_tasks(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_output_tasks" ):
                listener.exitFile_output_tasks(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_output_tasks" ):
                return visitor.visitFile_output_tasks(self)
            else:
                return visitor.visitChildren(self)




    def file_output_tasks(self):

        localctx = VerilogParser.File_output_tasksContext(self, self._ctx, self.state)
        self.enterRule(localctx, 28, self.RULE_file_output_tasks)
        self._la = 0 # Token type
        try:
            self.state = 812
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,12,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 792
                self.file_output_task_name()
                self.state = 793
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 794
                self.multi_channel_descriptor()
                self.state = 797
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 795
                    self.match(VerilogParser.COMMA)
                    self.state = 796
                    self.list_of_arguments()


                self.state = 799
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 800
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 802
                self.file_output_task_name()
                self.state = 803
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 804
                self.fd()
                self.state = 807
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 805
                    self.match(VerilogParser.COMMA)
                    self.state = 806
                    self.list_of_arguments()


                self.state = 809
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 810
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class File_output_task_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_FDISPLAY(self):
            return self.getToken(VerilogParser.DOLLAR_FDISPLAY, 0)

        def DOLLAR_FDISPLAYB(self):
            return self.getToken(VerilogParser.DOLLAR_FDISPLAYB, 0)

        def DOLLAR_FDISPLAYH(self):
            return self.getToken(VerilogParser.DOLLAR_FDISPLAYH, 0)

        def DOLLAR_FDISPLAYO(self):
            return self.getToken(VerilogParser.DOLLAR_FDISPLAYO, 0)

        def DOLLAR_FWRITE(self):
            return self.getToken(VerilogParser.DOLLAR_FWRITE, 0)

        def DOLLAR_FWRITEB(self):
            return self.getToken(VerilogParser.DOLLAR_FWRITEB, 0)

        def DOLLAR_FWRITEH(self):
            return self.getToken(VerilogParser.DOLLAR_FWRITEH, 0)

        def DOLLAR_FWRITEO(self):
            return self.getToken(VerilogParser.DOLLAR_FWRITEO, 0)

        def DOLLAR_FSTROBE(self):
            return self.getToken(VerilogParser.DOLLAR_FSTROBE, 0)

        def DOLLAR_FSTROBEB(self):
            return self.getToken(VerilogParser.DOLLAR_FSTROBEB, 0)

        def DOLLAR_FSTROBEH(self):
            return self.getToken(VerilogParser.DOLLAR_FSTROBEH, 0)

        def DOLLAR_FSTROBEO(self):
            return self.getToken(VerilogParser.DOLLAR_FSTROBEO, 0)

        def DOLLAR_FMONITOR(self):
            return self.getToken(VerilogParser.DOLLAR_FMONITOR, 0)

        def DOLLAR_FMONITORB(self):
            return self.getToken(VerilogParser.DOLLAR_FMONITORB, 0)

        def DOLLAR_FMONITORH(self):
            return self.getToken(VerilogParser.DOLLAR_FMONITORH, 0)

        def DOLLAR_FMONITORO(self):
            return self.getToken(VerilogParser.DOLLAR_FMONITORO, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_file_output_task_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_output_task_name" ):
                listener.enterFile_output_task_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_output_task_name" ):
                listener.exitFile_output_task_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_output_task_name" ):
                return visitor.visitFile_output_task_name(self)
            else:
                return visitor.visitChildren(self)




    def file_output_task_name(self):

        localctx = VerilogParser.File_output_task_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 30, self.RULE_file_output_task_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 814
            _la = self._input.LA(1)
            if not(((((_la - 144)) & ~0x3f) == 0 and ((1 << (_la - 144)) & ((1 << (VerilogParser.DOLLAR_FDISPLAY - 144)) | (1 << (VerilogParser.DOLLAR_FDISPLAYB - 144)) | (1 << (VerilogParser.DOLLAR_FDISPLAYH - 144)) | (1 << (VerilogParser.DOLLAR_FDISPLAYO - 144)) | (1 << (VerilogParser.DOLLAR_FSTROBE - 144)) | (1 << (VerilogParser.DOLLAR_FSTROBEB - 144)) | (1 << (VerilogParser.DOLLAR_FSTROBEH - 144)) | (1 << (VerilogParser.DOLLAR_FSTROBEO - 144)) | (1 << (VerilogParser.DOLLAR_FWRITE - 144)) | (1 << (VerilogParser.DOLLAR_FWRITEB - 144)) | (1 << (VerilogParser.DOLLAR_FWRITEH - 144)) | (1 << (VerilogParser.DOLLAR_FWRITEO - 144)) | (1 << (VerilogParser.DOLLAR_FMONITOR - 144)) | (1 << (VerilogParser.DOLLAR_FMONITORB - 144)) | (1 << (VerilogParser.DOLLAR_FMONITORH - 144)) | (1 << (VerilogParser.DOLLAR_FMONITORO - 144)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Load_memory_tasksContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_READMEMB(self):
            return self.getToken(VerilogParser.DOLLAR_READMEMB, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def filename(self):
            return self.getTypedRuleContext(VerilogParser.FilenameContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def memory_name(self):
            return self.getTypedRuleContext(VerilogParser.Memory_nameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def start_addr(self):
            return self.getTypedRuleContext(VerilogParser.Start_addrContext,0)


        def finish_addr(self):
            return self.getTypedRuleContext(VerilogParser.Finish_addrContext,0)


        def DOLLAR_READMEMH(self):
            return self.getToken(VerilogParser.DOLLAR_READMEMH, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_load_memory_tasks

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoad_memory_tasks" ):
                listener.enterLoad_memory_tasks(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoad_memory_tasks" ):
                listener.exitLoad_memory_tasks(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoad_memory_tasks" ):
                return visitor.visitLoad_memory_tasks(self)
            else:
                return visitor.visitChildren(self)




    def load_memory_tasks(self):

        localctx = VerilogParser.Load_memory_tasksContext(self, self._ctx, self.state)
        self.enterRule(localctx, 32, self.RULE_load_memory_tasks)
        self._la = 0 # Token type
        try:
            self.state = 848
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_READMEMB]:
                self.enterOuterAlt(localctx, 1)
                self.state = 816
                self.match(VerilogParser.DOLLAR_READMEMB)
                self.state = 817
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 818
                self.filename()
                self.state = 819
                self.match(VerilogParser.COMMA)
                self.state = 820
                self.memory_name()
                self.state = 827
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 821
                    self.match(VerilogParser.COMMA)
                    self.state = 822
                    self.start_addr()
                    self.state = 825
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==VerilogParser.COMMA:
                        self.state = 823
                        self.match(VerilogParser.COMMA)
                        self.state = 824
                        self.finish_addr()




                self.state = 829
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 830
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.DOLLAR_READMEMH]:
                self.enterOuterAlt(localctx, 2)
                self.state = 832
                self.match(VerilogParser.DOLLAR_READMEMH)
                self.state = 833
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 834
                self.filename()
                self.state = 835
                self.match(VerilogParser.COMMA)
                self.state = 836
                self.memory_name()
                self.state = 843
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 837
                    self.match(VerilogParser.COMMA)
                    self.state = 838
                    self.start_addr()
                    self.state = 841
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==VerilogParser.COMMA:
                        self.state = 839
                        self.match(VerilogParser.COMMA)
                        self.state = 840
                        self.finish_addr()




                self.state = 845
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 846
                self.match(VerilogParser.SEMICOLON)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Memory_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_memory_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMemory_name" ):
                listener.enterMemory_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMemory_name" ):
                listener.exitMemory_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMemory_name" ):
                return visitor.visitMemory_name(self)
            else:
                return visitor.visitChildren(self)




    def memory_name(self):

        localctx = VerilogParser.Memory_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 34, self.RULE_memory_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 850
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Start_addrContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_start_addr

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStart_addr" ):
                listener.enterStart_addr(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStart_addr" ):
                listener.exitStart_addr(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStart_addr" ):
                return visitor.visitStart_addr(self)
            else:
                return visitor.visitChildren(self)




    def start_addr(self):

        localctx = VerilogParser.Start_addrContext(self, self._ctx, self.state)
        self.enterRule(localctx, 36, self.RULE_start_addr)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 852
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Finish_addrContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_finish_addr

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFinish_addr" ):
                listener.enterFinish_addr(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFinish_addr" ):
                listener.exitFinish_addr(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFinish_addr" ):
                return visitor.visitFinish_addr(self)
            else:
                return visitor.visitChildren(self)




    def finish_addr(self):

        localctx = VerilogParser.Finish_addrContext(self, self._ctx, self.state)
        self.enterRule(localctx, 38, self.RULE_finish_addr)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 854
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class FilenameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def STRING(self):
            return self.getToken(VerilogParser.STRING, 0)

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_filename

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFilename" ):
                listener.enterFilename(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFilename" ):
                listener.exitFilename(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFilename" ):
                return visitor.visitFilename(self)
            else:
                return visitor.visitChildren(self)




    def filename(self):

        localctx = VerilogParser.FilenameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 40, self.RULE_filename)
        try:
            self.state = 858
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.STRING]:
                self.enterOuterAlt(localctx, 1)
                self.state = 856
                self.match(VerilogParser.STRING)
                pass
            elif token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 857
                self.variable_identifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Finish_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_FINISH(self):
            return self.getToken(VerilogParser.DOLLAR_FINISH, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def finish_number(self):
            return self.getTypedRuleContext(VerilogParser.Finish_numberContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_finish_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFinish_task" ):
                listener.enterFinish_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFinish_task" ):
                listener.exitFinish_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFinish_task" ):
                return visitor.visitFinish_task(self)
            else:
                return visitor.visitChildren(self)




    def finish_task(self):

        localctx = VerilogParser.Finish_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 42, self.RULE_finish_task)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 860
            self.match(VerilogParser.DOLLAR_FINISH)
            self.state = 865
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 861
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 862
                self.finish_number()
                self.state = 863
                self.match(VerilogParser.RIGHT_PARENTHESIS)


            self.state = 867
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Finish_numberContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_finish_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFinish_number" ):
                listener.enterFinish_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFinish_number" ):
                listener.exitFinish_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFinish_number" ):
                return visitor.visitFinish_number(self)
            else:
                return visitor.visitChildren(self)




    def finish_number(self):

        localctx = VerilogParser.Finish_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 44, self.RULE_finish_number)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 869
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Stop_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_STOP(self):
            return self.getToken(VerilogParser.DOLLAR_STOP, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def finish_number(self):
            return self.getTypedRuleContext(VerilogParser.Finish_numberContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_stop_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStop_task" ):
                listener.enterStop_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStop_task" ):
                listener.exitStop_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStop_task" ):
                return visitor.visitStop_task(self)
            else:
                return visitor.visitChildren(self)




    def stop_task(self):

        localctx = VerilogParser.Stop_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 46, self.RULE_stop_task)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 871
            self.match(VerilogParser.DOLLAR_STOP)
            self.state = 876
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 872
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 873
                self.finish_number()
                self.state = 874
                self.match(VerilogParser.RIGHT_PARENTHESIS)


            self.state = 878
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Time_functionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_time_function

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTime_function" ):
                listener.enterTime_function(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTime_function" ):
                listener.exitTime_function(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTime_function" ):
                return visitor.visitTime_function(self)
            else:
                return visitor.visitChildren(self)




    def time_function(self):

        localctx = VerilogParser.Time_functionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 48, self.RULE_time_function)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 880
            self.match(VerilogParser.TIME)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Stime_functionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_STIME(self):
            return self.getToken(VerilogParser.DOLLAR_STIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_stime_function

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStime_function" ):
                listener.enterStime_function(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStime_function" ):
                listener.exitStime_function(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStime_function" ):
                return visitor.visitStime_function(self)
            else:
                return visitor.visitChildren(self)




    def stime_function(self):

        localctx = VerilogParser.Stime_functionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 50, self.RULE_stime_function)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 882
            self.match(VerilogParser.DOLLAR_STIME)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Realtime_functionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_realtime_function

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRealtime_function" ):
                listener.enterRealtime_function(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRealtime_function" ):
                listener.exitRealtime_function(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRealtime_function" ):
                return visitor.visitRealtime_function(self)
            else:
                return visitor.visitChildren(self)




    def realtime_function(self):

        localctx = VerilogParser.Realtime_functionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 52, self.RULE_realtime_function)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 884
            self.match(VerilogParser.REALTIME)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Conversion_functionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def conversion_function_name(self):
            return self.getTypedRuleContext(VerilogParser.Conversion_function_nameContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def constant_argument(self):
            return self.getTypedRuleContext(VerilogParser.Constant_argumentContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_conversion_functions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConversion_functions" ):
                listener.enterConversion_functions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConversion_functions" ):
                listener.exitConversion_functions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConversion_functions" ):
                return visitor.visitConversion_functions(self)
            else:
                return visitor.visitChildren(self)




    def conversion_functions(self):

        localctx = VerilogParser.Conversion_functionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 54, self.RULE_conversion_functions)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 886
            self.conversion_function_name()
            self.state = 887
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 888
            self.constant_argument()
            self.state = 889
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Conversion_function_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_RTOI(self):
            return self.getToken(VerilogParser.DOLLAR_RTOI, 0)

        def DOLLAR_ITOR(self):
            return self.getToken(VerilogParser.DOLLAR_ITOR, 0)

        def DOLLAR_REALTOBITS(self):
            return self.getToken(VerilogParser.DOLLAR_REALTOBITS, 0)

        def DOLLAR_BITSTOREAL(self):
            return self.getToken(VerilogParser.DOLLAR_BITSTOREAL, 0)

        def DOLLAR_SIGNED(self):
            return self.getToken(VerilogParser.DOLLAR_SIGNED, 0)

        def DOLLAR_UNSIGNED(self):
            return self.getToken(VerilogParser.DOLLAR_UNSIGNED, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_conversion_function_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConversion_function_name" ):
                listener.enterConversion_function_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConversion_function_name" ):
                listener.exitConversion_function_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConversion_function_name" ):
                return visitor.visitConversion_function_name(self)
            else:
                return visitor.visitChildren(self)




    def conversion_function_name(self):

        localctx = VerilogParser.Conversion_function_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 56, self.RULE_conversion_function_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 891
            _la = self._input.LA(1)
            if not(((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_argumentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_constant_argument

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_argument" ):
                listener.enterConstant_argument(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_argument" ):
                listener.exitConstant_argument(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_argument" ):
                return visitor.visitConstant_argument(self)
            else:
                return visitor.visitChildren(self)




    def constant_argument(self):

        localctx = VerilogParser.Constant_argumentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 58, self.RULE_constant_argument)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 893
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Random_functionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_RANDOM(self):
            return self.getToken(VerilogParser.DOLLAR_RANDOM, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def seed(self):
            return self.getTypedRuleContext(VerilogParser.SeedContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_random_function

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRandom_function" ):
                listener.enterRandom_function(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRandom_function" ):
                listener.exitRandom_function(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRandom_function" ):
                return visitor.visitRandom_function(self)
            else:
                return visitor.visitChildren(self)




    def random_function(self):

        localctx = VerilogParser.Random_functionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 60, self.RULE_random_function)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 895
            self.match(VerilogParser.DOLLAR_RANDOM)
            self.state = 900
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,21,self._ctx)
            if la_ == 1:
                self.state = 896
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 897
                self.seed()
                self.state = 898
                self.match(VerilogParser.RIGHT_PARENTHESIS)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class SeedContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_seed

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSeed" ):
                listener.enterSeed(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSeed" ):
                listener.exitSeed(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSeed" ):
                return visitor.visitSeed(self)
            else:
                return visitor.visitChildren(self)




    def seed(self):

        localctx = VerilogParser.SeedContext(self, self._ctx, self.state)
        self.enterRule(localctx, 62, self.RULE_seed)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 902
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dist_functionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DIST_UNIFORM(self):
            return self.getToken(VerilogParser.DOLLAR_DIST_UNIFORM, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def seed(self):
            return self.getTypedRuleContext(VerilogParser.SeedContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def start_(self):
            return self.getTypedRuleContext(VerilogParser.Start_Context,0)


        def end(self):
            return self.getTypedRuleContext(VerilogParser.EndContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def DOLLAR_DIST_NORMAL(self):
            return self.getToken(VerilogParser.DOLLAR_DIST_NORMAL, 0)

        def mean(self):
            return self.getTypedRuleContext(VerilogParser.MeanContext,0)


        def standard_deviation(self):
            return self.getTypedRuleContext(VerilogParser.Standard_deviationContext,0)


        def DOLLAR_DIST_EXPONENTIAL(self):
            return self.getToken(VerilogParser.DOLLAR_DIST_EXPONENTIAL, 0)

        def DOLLAR_DIST_POISSON(self):
            return self.getToken(VerilogParser.DOLLAR_DIST_POISSON, 0)

        def DOLLAR_DIST_CHI_SQUARE(self):
            return self.getToken(VerilogParser.DOLLAR_DIST_CHI_SQUARE, 0)

        def degree_of_freedom(self):
            return self.getTypedRuleContext(VerilogParser.Degree_of_freedomContext,0)


        def DOLLAR_DIST_T(self):
            return self.getToken(VerilogParser.DOLLAR_DIST_T, 0)

        def DOLLAR_DIST_ERLANG(self):
            return self.getToken(VerilogParser.DOLLAR_DIST_ERLANG, 0)

        def k_stage(self):
            return self.getTypedRuleContext(VerilogParser.K_stageContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_dist_functions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDist_functions" ):
                listener.enterDist_functions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDist_functions" ):
                listener.exitDist_functions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDist_functions" ):
                return visitor.visitDist_functions(self)
            else:
                return visitor.visitChildren(self)




    def dist_functions(self):

        localctx = VerilogParser.Dist_functionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 64, self.RULE_dist_functions)
        try:
            self.state = 959
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_DIST_UNIFORM]:
                self.enterOuterAlt(localctx, 1)
                self.state = 904
                self.match(VerilogParser.DOLLAR_DIST_UNIFORM)
                self.state = 905
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 906
                self.seed()
                self.state = 907
                self.match(VerilogParser.COMMA)
                self.state = 908
                self.start_()
                self.state = 909
                self.match(VerilogParser.COMMA)
                self.state = 910
                self.end()
                self.state = 911
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            elif token in [VerilogParser.DOLLAR_DIST_NORMAL]:
                self.enterOuterAlt(localctx, 2)
                self.state = 913
                self.match(VerilogParser.DOLLAR_DIST_NORMAL)
                self.state = 914
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 915
                self.seed()
                self.state = 916
                self.match(VerilogParser.COMMA)
                self.state = 917
                self.mean()
                self.state = 918
                self.match(VerilogParser.COMMA)
                self.state = 919
                self.standard_deviation()
                self.state = 920
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            elif token in [VerilogParser.DOLLAR_DIST_EXPONENTIAL]:
                self.enterOuterAlt(localctx, 3)
                self.state = 922
                self.match(VerilogParser.DOLLAR_DIST_EXPONENTIAL)
                self.state = 923
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 924
                self.seed()
                self.state = 925
                self.match(VerilogParser.COMMA)
                self.state = 926
                self.mean()
                self.state = 927
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            elif token in [VerilogParser.DOLLAR_DIST_POISSON]:
                self.enterOuterAlt(localctx, 4)
                self.state = 929
                self.match(VerilogParser.DOLLAR_DIST_POISSON)
                self.state = 930
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 931
                self.seed()
                self.state = 932
                self.match(VerilogParser.COMMA)
                self.state = 933
                self.mean()
                self.state = 934
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            elif token in [VerilogParser.DOLLAR_DIST_CHI_SQUARE]:
                self.enterOuterAlt(localctx, 5)
                self.state = 936
                self.match(VerilogParser.DOLLAR_DIST_CHI_SQUARE)
                self.state = 937
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 938
                self.seed()
                self.state = 939
                self.match(VerilogParser.COMMA)
                self.state = 940
                self.degree_of_freedom()
                self.state = 941
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            elif token in [VerilogParser.DOLLAR_DIST_T]:
                self.enterOuterAlt(localctx, 6)
                self.state = 943
                self.match(VerilogParser.DOLLAR_DIST_T)
                self.state = 944
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 945
                self.seed()
                self.state = 946
                self.match(VerilogParser.COMMA)
                self.state = 947
                self.degree_of_freedom()
                self.state = 948
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            elif token in [VerilogParser.DOLLAR_DIST_ERLANG]:
                self.enterOuterAlt(localctx, 7)
                self.state = 950
                self.match(VerilogParser.DOLLAR_DIST_ERLANG)
                self.state = 951
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 952
                self.seed()
                self.state = 953
                self.match(VerilogParser.COMMA)
                self.state = 954
                self.k_stage()
                self.state = 955
                self.match(VerilogParser.COMMA)
                self.state = 956
                self.mean()
                self.state = 957
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Start_Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_start_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStart_" ):
                listener.enterStart_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStart_" ):
                listener.exitStart_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStart_" ):
                return visitor.visitStart_(self)
            else:
                return visitor.visitChildren(self)




    def start_(self):

        localctx = VerilogParser.Start_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 66, self.RULE_start_)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 961
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class EndContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_end

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnd" ):
                listener.enterEnd(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnd" ):
                listener.exitEnd(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnd" ):
                return visitor.visitEnd(self)
            else:
                return visitor.visitChildren(self)




    def end(self):

        localctx = VerilogParser.EndContext(self, self._ctx, self.state)
        self.enterRule(localctx, 68, self.RULE_end)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 963
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class MeanContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_mean

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMean" ):
                listener.enterMean(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMean" ):
                listener.exitMean(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMean" ):
                return visitor.visitMean(self)
            else:
                return visitor.visitChildren(self)




    def mean(self):

        localctx = VerilogParser.MeanContext(self, self._ctx, self.state)
        self.enterRule(localctx, 70, self.RULE_mean)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 965
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Standard_deviationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_standard_deviation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStandard_deviation" ):
                listener.enterStandard_deviation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStandard_deviation" ):
                listener.exitStandard_deviation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStandard_deviation" ):
                return visitor.visitStandard_deviation(self)
            else:
                return visitor.visitChildren(self)




    def standard_deviation(self):

        localctx = VerilogParser.Standard_deviationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 72, self.RULE_standard_deviation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 967
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Degree_of_freedomContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_degree_of_freedom

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDegree_of_freedom" ):
                listener.enterDegree_of_freedom(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDegree_of_freedom" ):
                listener.exitDegree_of_freedom(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDegree_of_freedom" ):
                return visitor.visitDegree_of_freedom(self)
            else:
                return visitor.visitChildren(self)




    def degree_of_freedom(self):

        localctx = VerilogParser.Degree_of_freedomContext(self, self._ctx, self.state)
        self.enterRule(localctx, 74, self.RULE_degree_of_freedom)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 969
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class K_stageContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_k_stage

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterK_stage" ):
                listener.enterK_stage(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitK_stage" ):
                listener.exitK_stage(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitK_stage" ):
                return visitor.visitK_stage(self)
            else:
                return visitor.visitChildren(self)




    def k_stage(self):

        localctx = VerilogParser.K_stageContext(self, self._ctx, self.state)
        self.enterRule(localctx, 76, self.RULE_k_stage)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 971
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Math_functionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def integer_math_functions(self):
            return self.getTypedRuleContext(VerilogParser.Integer_math_functionsContext,0)


        def real_math_functions(self):
            return self.getTypedRuleContext(VerilogParser.Real_math_functionsContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_math_functions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMath_functions" ):
                listener.enterMath_functions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMath_functions" ):
                listener.exitMath_functions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMath_functions" ):
                return visitor.visitMath_functions(self)
            else:
                return visitor.visitChildren(self)




    def math_functions(self):

        localctx = VerilogParser.Math_functionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 78, self.RULE_math_functions)
        try:
            self.state = 975
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_CLOG2]:
                self.enterOuterAlt(localctx, 1)
                self.state = 973
                self.integer_math_functions()
                pass
            elif token in [VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH]:
                self.enterOuterAlt(localctx, 2)
                self.state = 974
                self.real_math_functions()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Integer_math_functionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_CLOG2(self):
            return self.getToken(VerilogParser.DOLLAR_CLOG2, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def constant_argument(self):
            return self.getTypedRuleContext(VerilogParser.Constant_argumentContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_integer_math_functions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInteger_math_functions" ):
                listener.enterInteger_math_functions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInteger_math_functions" ):
                listener.exitInteger_math_functions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInteger_math_functions" ):
                return visitor.visitInteger_math_functions(self)
            else:
                return visitor.visitChildren(self)




    def integer_math_functions(self):

        localctx = VerilogParser.Integer_math_functionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 80, self.RULE_integer_math_functions)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 977
            self.match(VerilogParser.DOLLAR_CLOG2)
            self.state = 978
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 979
            self.constant_argument()
            self.state = 980
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Real_math_functionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def single_argument_real_math_function_name(self):
            return self.getTypedRuleContext(VerilogParser.Single_argument_real_math_function_nameContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def constant_argument(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_argumentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_argumentContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def double_argument_real_math_function_name(self):
            return self.getTypedRuleContext(VerilogParser.Double_argument_real_math_function_nameContext,0)


        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_real_math_functions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_math_functions" ):
                listener.enterReal_math_functions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_math_functions" ):
                listener.exitReal_math_functions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_math_functions" ):
                return visitor.visitReal_math_functions(self)
            else:
                return visitor.visitChildren(self)




    def real_math_functions(self):

        localctx = VerilogParser.Real_math_functionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 82, self.RULE_real_math_functions)
        try:
            self.state = 994
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH]:
                self.enterOuterAlt(localctx, 1)
                self.state = 982
                self.single_argument_real_math_function_name()
                self.state = 983
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 984
                self.constant_argument()
                self.state = 985
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            elif token in [VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 987
                self.double_argument_real_math_function_name()
                self.state = 988
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 989
                self.constant_argument()
                self.state = 990
                self.match(VerilogParser.COMMA)
                self.state = 991
                self.constant_argument()
                self.state = 992
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Single_argument_real_math_function_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_LN(self):
            return self.getToken(VerilogParser.DOLLAR_LN, 0)

        def DOLLAR_LOG10(self):
            return self.getToken(VerilogParser.DOLLAR_LOG10, 0)

        def DOLLAR_EXP(self):
            return self.getToken(VerilogParser.DOLLAR_EXP, 0)

        def DOLLAR_SQRT(self):
            return self.getToken(VerilogParser.DOLLAR_SQRT, 0)

        def DOLLAR_FLOOR(self):
            return self.getToken(VerilogParser.DOLLAR_FLOOR, 0)

        def DOLLAR_CEIL(self):
            return self.getToken(VerilogParser.DOLLAR_CEIL, 0)

        def DOLLAR_SIN(self):
            return self.getToken(VerilogParser.DOLLAR_SIN, 0)

        def DOLLAR_COS(self):
            return self.getToken(VerilogParser.DOLLAR_COS, 0)

        def DOLLAR_TAN(self):
            return self.getToken(VerilogParser.DOLLAR_TAN, 0)

        def DOLLAR_ASIN(self):
            return self.getToken(VerilogParser.DOLLAR_ASIN, 0)

        def DOLLAR_ACOS(self):
            return self.getToken(VerilogParser.DOLLAR_ACOS, 0)

        def DOLLAR_ATAN(self):
            return self.getToken(VerilogParser.DOLLAR_ATAN, 0)

        def DOLLAR_SINH(self):
            return self.getToken(VerilogParser.DOLLAR_SINH, 0)

        def DOLLAR_COSH(self):
            return self.getToken(VerilogParser.DOLLAR_COSH, 0)

        def DOLLAR_TANH(self):
            return self.getToken(VerilogParser.DOLLAR_TANH, 0)

        def DOLLAR_ASINH(self):
            return self.getToken(VerilogParser.DOLLAR_ASINH, 0)

        def DOLLAR_ACOSH(self):
            return self.getToken(VerilogParser.DOLLAR_ACOSH, 0)

        def DOLLAR_ATANH(self):
            return self.getToken(VerilogParser.DOLLAR_ATANH, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_single_argument_real_math_function_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSingle_argument_real_math_function_name" ):
                listener.enterSingle_argument_real_math_function_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSingle_argument_real_math_function_name" ):
                listener.exitSingle_argument_real_math_function_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSingle_argument_real_math_function_name" ):
                return visitor.visitSingle_argument_real_math_function_name(self)
            else:
                return visitor.visitChildren(self)




    def single_argument_real_math_function_name(self):

        localctx = VerilogParser.Single_argument_real_math_function_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 84, self.RULE_single_argument_real_math_function_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 996
            _la = self._input.LA(1)
            if not(((((_la - 226)) & ~0x3f) == 0 and ((1 << (_la - 226)) & ((1 << (VerilogParser.DOLLAR_LN - 226)) | (1 << (VerilogParser.DOLLAR_LOG10 - 226)) | (1 << (VerilogParser.DOLLAR_EXP - 226)) | (1 << (VerilogParser.DOLLAR_SQRT - 226)) | (1 << (VerilogParser.DOLLAR_FLOOR - 226)) | (1 << (VerilogParser.DOLLAR_CEIL - 226)) | (1 << (VerilogParser.DOLLAR_SIN - 226)) | (1 << (VerilogParser.DOLLAR_COS - 226)) | (1 << (VerilogParser.DOLLAR_TAN - 226)) | (1 << (VerilogParser.DOLLAR_ASIN - 226)) | (1 << (VerilogParser.DOLLAR_ACOS - 226)) | (1 << (VerilogParser.DOLLAR_ATAN - 226)) | (1 << (VerilogParser.DOLLAR_SINH - 226)) | (1 << (VerilogParser.DOLLAR_COSH - 226)) | (1 << (VerilogParser.DOLLAR_TANH - 226)) | (1 << (VerilogParser.DOLLAR_ASINH - 226)) | (1 << (VerilogParser.DOLLAR_ACOSH - 226)) | (1 << (VerilogParser.DOLLAR_ATANH - 226)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Double_argument_real_math_function_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_POW(self):
            return self.getToken(VerilogParser.DOLLAR_POW, 0)

        def DOLLAR_ATAN2(self):
            return self.getToken(VerilogParser.DOLLAR_ATAN2, 0)

        def DOLLAR_HYPOT(self):
            return self.getToken(VerilogParser.DOLLAR_HYPOT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_double_argument_real_math_function_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDouble_argument_real_math_function_name" ):
                listener.enterDouble_argument_real_math_function_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDouble_argument_real_math_function_name" ):
                listener.exitDouble_argument_real_math_function_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDouble_argument_real_math_function_name" ):
                return visitor.visitDouble_argument_real_math_function_name(self)
            else:
                return visitor.visitChildren(self)




    def double_argument_real_math_function_name(self):

        localctx = VerilogParser.Double_argument_real_math_function_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 86, self.RULE_double_argument_real_math_function_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 998
            _la = self._input.LA(1)
            if not(((((_la - 230)) & ~0x3f) == 0 and ((1 << (_la - 230)) & ((1 << (VerilogParser.DOLLAR_POW - 230)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 230)) | (1 << (VerilogParser.DOLLAR_HYPOT - 230)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpfile_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPFILE(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPFILE, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def filename(self):
            return self.getTypedRuleContext(VerilogParser.FilenameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpfile_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpfile_task" ):
                listener.enterDumpfile_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpfile_task" ):
                listener.exitDumpfile_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpfile_task" ):
                return visitor.visitDumpfile_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpfile_task(self):

        localctx = VerilogParser.Dumpfile_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 88, self.RULE_dumpfile_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1000
            self.match(VerilogParser.DOLLAR_DUMPFILE)
            self.state = 1001
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1002
            self.filename()
            self.state = 1003
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 1004
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpvars_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPVARS(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPVARS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def levels(self):
            return self.getTypedRuleContext(VerilogParser.LevelsContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def list_of_modules_or_variables(self):
            return self.getTypedRuleContext(VerilogParser.List_of_modules_or_variablesContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_dumpvars_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpvars_task" ):
                listener.enterDumpvars_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpvars_task" ):
                listener.exitDumpvars_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpvars_task" ):
                return visitor.visitDumpvars_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpvars_task(self):

        localctx = VerilogParser.Dumpvars_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 90, self.RULE_dumpvars_task)
        self._la = 0 # Token type
        try:
            self.state = 1018
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,26,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1006
                self.match(VerilogParser.DOLLAR_DUMPVARS)
                self.state = 1007
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1008
                self.match(VerilogParser.DOLLAR_DUMPVARS)
                self.state = 1009
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1010
                self.levels()
                self.state = 1013
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 1011
                    self.match(VerilogParser.COMMA)
                    self.state = 1012
                    self.list_of_modules_or_variables()


                self.state = 1015
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 1016
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_modules_or_variablesContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_or_variable(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_or_variableContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_or_variableContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_modules_or_variables

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_modules_or_variables" ):
                listener.enterList_of_modules_or_variables(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_modules_or_variables" ):
                listener.exitList_of_modules_or_variables(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_modules_or_variables" ):
                return visitor.visitList_of_modules_or_variables(self)
            else:
                return visitor.visitChildren(self)




    def list_of_modules_or_variables(self):

        localctx = VerilogParser.List_of_modules_or_variablesContext(self, self._ctx, self.state)
        self.enterRule(localctx, 92, self.RULE_list_of_modules_or_variables)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1020
            self.module_or_variable()
            self.state = 1025
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1021
                self.match(VerilogParser.COMMA)
                self.state = 1022
                self.module_or_variable()
                self.state = 1027
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_or_variableContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Module_identifierContext,0)


        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_or_variable

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_or_variable" ):
                listener.enterModule_or_variable(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_or_variable" ):
                listener.exitModule_or_variable(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_or_variable" ):
                return visitor.visitModule_or_variable(self)
            else:
                return visitor.visitChildren(self)




    def module_or_variable(self):

        localctx = VerilogParser.Module_or_variableContext(self, self._ctx, self.state)
        self.enterRule(localctx, 94, self.RULE_module_or_variable)
        try:
            self.state = 1030
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,28,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1028
                self.module_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1029
                self.variable_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class LevelsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_levels

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLevels" ):
                listener.enterLevels(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLevels" ):
                listener.exitLevels(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLevels" ):
                return visitor.visitLevels(self)
            else:
                return visitor.visitChildren(self)




    def levels(self):

        localctx = VerilogParser.LevelsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 96, self.RULE_levels)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1032
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpoff_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPOFF(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPOFF, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpoff_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpoff_task" ):
                listener.enterDumpoff_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpoff_task" ):
                listener.exitDumpoff_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpoff_task" ):
                return visitor.visitDumpoff_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpoff_task(self):

        localctx = VerilogParser.Dumpoff_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 98, self.RULE_dumpoff_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1034
            self.match(VerilogParser.DOLLAR_DUMPOFF)
            self.state = 1035
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpon_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPON(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPON, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpon_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpon_task" ):
                listener.enterDumpon_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpon_task" ):
                listener.exitDumpon_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpon_task" ):
                return visitor.visitDumpon_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpon_task(self):

        localctx = VerilogParser.Dumpon_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 100, self.RULE_dumpon_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1037
            self.match(VerilogParser.DOLLAR_DUMPON)
            self.state = 1038
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpall_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPALL(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPALL, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpall_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpall_task" ):
                listener.enterDumpall_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpall_task" ):
                listener.exitDumpall_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpall_task" ):
                return visitor.visitDumpall_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpall_task(self):

        localctx = VerilogParser.Dumpall_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 102, self.RULE_dumpall_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1040
            self.match(VerilogParser.DOLLAR_DUMPALL)
            self.state = 1041
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumplimit_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPLIMIT(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPLIMIT, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def file_size(self):
            return self.getTypedRuleContext(VerilogParser.File_sizeContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumplimit_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumplimit_task" ):
                listener.enterDumplimit_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumplimit_task" ):
                listener.exitDumplimit_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumplimit_task" ):
                return visitor.visitDumplimit_task(self)
            else:
                return visitor.visitChildren(self)




    def dumplimit_task(self):

        localctx = VerilogParser.Dumplimit_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 104, self.RULE_dumplimit_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1043
            self.match(VerilogParser.DOLLAR_DUMPLIMIT)
            self.state = 1044
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1045
            self.file_size()
            self.state = 1046
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 1047
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class File_sizeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_file_size

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_size" ):
                listener.enterFile_size(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_size" ):
                listener.exitFile_size(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_size" ):
                return visitor.visitFile_size(self)
            else:
                return visitor.visitChildren(self)




    def file_size(self):

        localctx = VerilogParser.File_sizeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 106, self.RULE_file_size)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1049
            self.match(VerilogParser.DECIMAL_NUMBER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpflush_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPFLUSH(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPFLUSH, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpflush_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpflush_task" ):
                listener.enterDumpflush_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpflush_task" ):
                listener.exitDumpflush_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpflush_task" ):
                return visitor.visitDumpflush_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpflush_task(self):

        localctx = VerilogParser.Dumpflush_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 108, self.RULE_dumpflush_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1051
            self.match(VerilogParser.DOLLAR_DUMPFLUSH)
            self.state = 1052
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpports_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPPORTS(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPPORTS, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def scope_list(self):
            return self.getTypedRuleContext(VerilogParser.Scope_listContext,0)


        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def file_pathname(self):
            return self.getTypedRuleContext(VerilogParser.File_pathnameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpports_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpports_task" ):
                listener.enterDumpports_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpports_task" ):
                listener.exitDumpports_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpports_task" ):
                return visitor.visitDumpports_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpports_task(self):

        localctx = VerilogParser.Dumpports_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 110, self.RULE_dumpports_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1054
            self.match(VerilogParser.DOLLAR_DUMPPORTS)
            self.state = 1055
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1056
            self.scope_list()
            self.state = 1057
            self.match(VerilogParser.COMMA)
            self.state = 1058
            self.file_pathname()
            self.state = 1059
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 1060
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Scope_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_identifierContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_scope_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterScope_list" ):
                listener.enterScope_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitScope_list" ):
                listener.exitScope_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitScope_list" ):
                return visitor.visitScope_list(self)
            else:
                return visitor.visitChildren(self)




    def scope_list(self):

        localctx = VerilogParser.Scope_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 112, self.RULE_scope_list)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1062
            self.module_identifier()
            self.state = 1067
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,29,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1063
                    self.match(VerilogParser.COMMA)
                    self.state = 1064
                    self.module_identifier() 
                self.state = 1069
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,29,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class File_pathnameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def STRING(self):
            return self.getToken(VerilogParser.STRING, 0)

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_file_pathname

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFile_pathname" ):
                listener.enterFile_pathname(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFile_pathname" ):
                listener.exitFile_pathname(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFile_pathname" ):
                return visitor.visitFile_pathname(self)
            else:
                return visitor.visitChildren(self)




    def file_pathname(self):

        localctx = VerilogParser.File_pathnameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 114, self.RULE_file_pathname)
        try:
            self.state = 1073
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,30,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1070
                self.match(VerilogParser.STRING)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1071
                self.variable_identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1072
                self.expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpportsoff_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPPORTSOFF(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPPORTSOFF, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def file_pathname(self):
            return self.getTypedRuleContext(VerilogParser.File_pathnameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpportsoff_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpportsoff_task" ):
                listener.enterDumpportsoff_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpportsoff_task" ):
                listener.exitDumpportsoff_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpportsoff_task" ):
                return visitor.visitDumpportsoff_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpportsoff_task(self):

        localctx = VerilogParser.Dumpportsoff_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 116, self.RULE_dumpportsoff_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1075
            self.match(VerilogParser.DOLLAR_DUMPPORTSOFF)
            self.state = 1076
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1077
            self.file_pathname()
            self.state = 1078
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 1079
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpportson_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPPORTSON(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPPORTSON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def file_pathname(self):
            return self.getTypedRuleContext(VerilogParser.File_pathnameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpportson_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpportson_task" ):
                listener.enterDumpportson_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpportson_task" ):
                listener.exitDumpportson_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpportson_task" ):
                return visitor.visitDumpportson_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpportson_task(self):

        localctx = VerilogParser.Dumpportson_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 118, self.RULE_dumpportson_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1081
            self.match(VerilogParser.DOLLAR_DUMPPORTSON)
            self.state = 1082
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1083
            self.file_pathname()
            self.state = 1084
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 1085
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpportsall_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPPORTSALL(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPPORTSALL, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def file_pathname(self):
            return self.getTypedRuleContext(VerilogParser.File_pathnameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpportsall_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpportsall_task" ):
                listener.enterDumpportsall_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpportsall_task" ):
                listener.exitDumpportsall_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpportsall_task" ):
                return visitor.visitDumpportsall_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpportsall_task(self):

        localctx = VerilogParser.Dumpportsall_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 120, self.RULE_dumpportsall_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1087
            self.match(VerilogParser.DOLLAR_DUMPPORTSALL)
            self.state = 1088
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1089
            self.file_pathname()
            self.state = 1090
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 1091
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpportslimit_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPPORTSLIMIT(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPPORTSLIMIT, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def file_size(self):
            return self.getTypedRuleContext(VerilogParser.File_sizeContext,0)


        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def file_pathname(self):
            return self.getTypedRuleContext(VerilogParser.File_pathnameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpportslimit_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpportslimit_task" ):
                listener.enterDumpportslimit_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpportslimit_task" ):
                listener.exitDumpportslimit_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpportslimit_task" ):
                return visitor.visitDumpportslimit_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpportslimit_task(self):

        localctx = VerilogParser.Dumpportslimit_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 122, self.RULE_dumpportslimit_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1093
            self.match(VerilogParser.DOLLAR_DUMPPORTSLIMIT)
            self.state = 1094
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1095
            self.file_size()
            self.state = 1096
            self.match(VerilogParser.COMMA)
            self.state = 1097
            self.file_pathname()
            self.state = 1098
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 1099
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dumpportsflush_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOLLAR_DUMPPORTSFLUSH(self):
            return self.getToken(VerilogParser.DOLLAR_DUMPPORTSFLUSH, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def file_pathname(self):
            return self.getTypedRuleContext(VerilogParser.File_pathnameContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dumpportsflush_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDumpportsflush_task" ):
                listener.enterDumpportsflush_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDumpportsflush_task" ):
                listener.exitDumpportsflush_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDumpportsflush_task" ):
                return visitor.visitDumpportsflush_task(self)
            else:
                return visitor.visitChildren(self)




    def dumpportsflush_task(self):

        localctx = VerilogParser.Dumpportsflush_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 124, self.RULE_dumpportsflush_task)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1101
            self.match(VerilogParser.DOLLAR_DUMPPORTSFLUSH)
            self.state = 1102
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1103
            self.file_pathname()
            self.state = 1104
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 1105
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Library_textContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def library_description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Library_descriptionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Library_descriptionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_library_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_text" ):
                listener.enterLibrary_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_text" ):
                listener.exitLibrary_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_text" ):
                return visitor.visitLibrary_text(self)
            else:
                return visitor.visitChildren(self)




    def library_text(self):

        localctx = VerilogParser.Library_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 126, self.RULE_library_text)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1110
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.CONFIG) | (1 << VerilogParser.INCLUDE) | (1 << VerilogParser.LIBRARY))) != 0):
                self.state = 1107
                self.library_description()
                self.state = 1112
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Library_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def library_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Library_declarationContext,0)


        def include_statement(self):
            return self.getTypedRuleContext(VerilogParser.Include_statementContext,0)


        def config_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Config_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_library_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_description" ):
                listener.enterLibrary_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_description" ):
                listener.exitLibrary_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_description" ):
                return visitor.visitLibrary_description(self)
            else:
                return visitor.visitChildren(self)




    def library_description(self):

        localctx = VerilogParser.Library_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 128, self.RULE_library_description)
        try:
            self.state = 1116
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.LIBRARY]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1113
                self.library_declaration()
                pass
            elif token in [VerilogParser.INCLUDE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1114
                self.include_statement()
                pass
            elif token in [VerilogParser.CONFIG]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1115
                self.config_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Library_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LIBRARY(self):
            return self.getToken(VerilogParser.LIBRARY, 0)

        def library_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Library_identifierContext,0)


        def FILE_PATH_SPEC(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.FILE_PATH_SPEC)
            else:
                return self.getToken(VerilogParser.FILE_PATH_SPEC, i)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def MINUS_INCDIR(self):
            return self.getToken(VerilogParser.MINUS_INCDIR, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_library_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_declaration" ):
                listener.enterLibrary_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_declaration" ):
                listener.exitLibrary_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_declaration" ):
                return visitor.visitLibrary_declaration(self)
            else:
                return visitor.visitChildren(self)




    def library_declaration(self):

        localctx = VerilogParser.Library_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 130, self.RULE_library_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1118
            self.match(VerilogParser.LIBRARY)
            self.state = 1119
            self.library_identifier()
            self.state = 1120
            self.match(VerilogParser.FILE_PATH_SPEC)
            self.state = 1125
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1121
                self.match(VerilogParser.COMMA)
                self.state = 1122
                self.match(VerilogParser.FILE_PATH_SPEC)
                self.state = 1127
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1137
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.MINUS_INCDIR:
                self.state = 1128
                self.match(VerilogParser.MINUS_INCDIR)
                self.state = 1129
                self.match(VerilogParser.FILE_PATH_SPEC)
                self.state = 1134
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 1130
                    self.match(VerilogParser.COMMA)
                    self.state = 1131
                    self.match(VerilogParser.FILE_PATH_SPEC)
                    self.state = 1136
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



            self.state = 1139
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Include_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INCLUDE(self):
            return self.getToken(VerilogParser.INCLUDE, 0)

        def FILE_PATH_SPEC(self):
            return self.getToken(VerilogParser.FILE_PATH_SPEC, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_include_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInclude_statement" ):
                listener.enterInclude_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInclude_statement" ):
                listener.exitInclude_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInclude_statement" ):
                return visitor.visitInclude_statement(self)
            else:
                return visitor.visitChildren(self)




    def include_statement(self):

        localctx = VerilogParser.Include_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 132, self.RULE_include_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1141
            self.match(VerilogParser.INCLUDE)
            self.state = 1142
            self.match(VerilogParser.FILE_PATH_SPEC)
            self.state = 1143
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Source_textContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EOF(self):
            return self.getToken(VerilogParser.EOF, 0)

        def description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DescriptionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DescriptionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_source_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSource_text" ):
                listener.enterSource_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSource_text" ):
                listener.exitSource_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSource_text" ):
                return visitor.visitSource_text(self)
            else:
                return visitor.visitChildren(self)




    def source_text(self):

        localctx = VerilogParser.Source_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 134, self.RULE_source_text)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1148
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.CONFIG) | (1 << VerilogParser.MACROMODULE) | (1 << VerilogParser.MODULE))) != 0) or _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 1145
                self.description()
                self.state = 1150
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1151
            self.match(VerilogParser.EOF)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class DescriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Module_declarationContext,0)


        def config_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Config_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDescription" ):
                listener.enterDescription(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDescription" ):
                listener.exitDescription(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDescription" ):
                return visitor.visitDescription(self)
            else:
                return visitor.visitChildren(self)




    def description(self):

        localctx = VerilogParser.DescriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 136, self.RULE_description)
        try:
            self.state = 1155
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.MACROMODULE, VerilogParser.MODULE, VerilogParser.LEFT_PARENTHESIS]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1153
                self.module_declaration()
                pass
            elif token in [VerilogParser.CONFIG]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1154
                self.config_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_keyword(self):
            return self.getTypedRuleContext(VerilogParser.Module_keywordContext,0)


        def module_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Module_identifierContext,0)


        def list_of_ports(self):
            return self.getTypedRuleContext(VerilogParser.List_of_portsContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def ENDMODULE(self):
            return self.getToken(VerilogParser.ENDMODULE, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def module_parameter_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Module_parameter_port_listContext,0)


        def module_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_itemContext,i)


        def list_of_port_declarations(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_declarationsContext,0)


        def non_port_module_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Non_port_module_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Non_port_module_itemContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_declaration" ):
                listener.enterModule_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_declaration" ):
                listener.exitModule_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_declaration" ):
                return visitor.visitModule_declaration(self)
            else:
                return visitor.visitChildren(self)




    def module_declaration(self):

        localctx = VerilogParser.Module_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 138, self.RULE_module_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1201
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,45,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1160
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1157
                    self.attribute_instance()
                    self.state = 1162
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1163
                self.module_keyword()
                self.state = 1164
                self.module_identifier()
                self.state = 1166
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1165
                    self.module_parameter_port_list()


                self.state = 1168
                self.list_of_ports()
                self.state = 1169
                self.match(VerilogParser.SEMICOLON)
                self.state = 1173
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ALWAYS) | (1 << VerilogParser.AND) | (1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BUF) | (1 << VerilogParser.BUFIF0) | (1 << VerilogParser.BUFIF1) | (1 << VerilogParser.CMOS) | (1 << VerilogParser.DEFAULT) | (1 << VerilogParser.DEFPARAM) | (1 << VerilogParser.EVENT) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FUNCTION) | (1 << VerilogParser.GENERATE) | (1 << VerilogParser.GENVAR) | (1 << VerilogParser.IF) | (1 << VerilogParser.INITIAL) | (1 << VerilogParser.INOUT) | (1 << VerilogParser.INPUT) | (1 << VerilogParser.INTEGER) | (1 << VerilogParser.LOCALPARAM) | (1 << VerilogParser.NAND) | (1 << VerilogParser.NMOS) | (1 << VerilogParser.NOR))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (VerilogParser.NOT - 64)) | (1 << (VerilogParser.NOTIF0 - 64)) | (1 << (VerilogParser.NOTIF1 - 64)) | (1 << (VerilogParser.OR - 64)) | (1 << (VerilogParser.OUTPUT - 64)) | (1 << (VerilogParser.PARAMETER - 64)) | (1 << (VerilogParser.PMOS - 64)) | (1 << (VerilogParser.PULLDOWN - 64)) | (1 << (VerilogParser.PULLUP - 64)) | (1 << (VerilogParser.RCMOS - 64)) | (1 << (VerilogParser.REAL - 64)) | (1 << (VerilogParser.REALTIME - 64)) | (1 << (VerilogParser.REG - 64)) | (1 << (VerilogParser.RNMOS - 64)) | (1 << (VerilogParser.RPMOS - 64)) | (1 << (VerilogParser.RTRAN - 64)) | (1 << (VerilogParser.RTRANIF0 - 64)) | (1 << (VerilogParser.RTRANIF1 - 64)) | (1 << (VerilogParser.SPECIFY - 64)) | (1 << (VerilogParser.SPECPARAM - 64)) | (1 << (VerilogParser.SUPPLY0 - 64)) | (1 << (VerilogParser.SUPPLY1 - 64)) | (1 << (VerilogParser.TASK - 64)) | (1 << (VerilogParser.TIME - 64)) | (1 << (VerilogParser.TRAN - 64)) | (1 << (VerilogParser.TRANIF0 - 64)) | (1 << (VerilogParser.TRANIF1 - 64)) | (1 << (VerilogParser.TRI - 64)) | (1 << (VerilogParser.TRI0 - 64)) | (1 << (VerilogParser.TRI1 - 64)) | (1 << (VerilogParser.TRIAND - 64)) | (1 << (VerilogParser.TRIOR - 64)) | (1 << (VerilogParser.TRIREG - 64)) | (1 << (VerilogParser.WAND - 64)) | (1 << (VerilogParser.WIRE - 64)) | (1 << (VerilogParser.WOR - 64)) | (1 << (VerilogParser.XNOR - 64)) | (1 << (VerilogParser.XOR - 64)))) != 0) or ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                    self.state = 1170
                    self.module_item()
                    self.state = 1175
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1176
                self.match(VerilogParser.ENDMODULE)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1181
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1178
                    self.attribute_instance()
                    self.state = 1183
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1184
                self.module_keyword()
                self.state = 1185
                self.module_identifier()
                self.state = 1187
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1186
                    self.module_parameter_port_list()


                self.state = 1190
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1189
                    self.list_of_port_declarations()


                self.state = 1192
                self.match(VerilogParser.SEMICOLON)
                self.state = 1196
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ALWAYS) | (1 << VerilogParser.AND) | (1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BUF) | (1 << VerilogParser.BUFIF0) | (1 << VerilogParser.BUFIF1) | (1 << VerilogParser.CMOS) | (1 << VerilogParser.DEFAULT) | (1 << VerilogParser.DEFPARAM) | (1 << VerilogParser.EVENT) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FUNCTION) | (1 << VerilogParser.GENERATE) | (1 << VerilogParser.GENVAR) | (1 << VerilogParser.IF) | (1 << VerilogParser.INITIAL) | (1 << VerilogParser.INTEGER) | (1 << VerilogParser.LOCALPARAM) | (1 << VerilogParser.NAND) | (1 << VerilogParser.NMOS) | (1 << VerilogParser.NOR))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (VerilogParser.NOT - 64)) | (1 << (VerilogParser.NOTIF0 - 64)) | (1 << (VerilogParser.NOTIF1 - 64)) | (1 << (VerilogParser.OR - 64)) | (1 << (VerilogParser.PARAMETER - 64)) | (1 << (VerilogParser.PMOS - 64)) | (1 << (VerilogParser.PULLDOWN - 64)) | (1 << (VerilogParser.PULLUP - 64)) | (1 << (VerilogParser.RCMOS - 64)) | (1 << (VerilogParser.REAL - 64)) | (1 << (VerilogParser.REALTIME - 64)) | (1 << (VerilogParser.REG - 64)) | (1 << (VerilogParser.RNMOS - 64)) | (1 << (VerilogParser.RPMOS - 64)) | (1 << (VerilogParser.RTRAN - 64)) | (1 << (VerilogParser.RTRANIF0 - 64)) | (1 << (VerilogParser.RTRANIF1 - 64)) | (1 << (VerilogParser.SPECIFY - 64)) | (1 << (VerilogParser.SPECPARAM - 64)) | (1 << (VerilogParser.SUPPLY0 - 64)) | (1 << (VerilogParser.SUPPLY1 - 64)) | (1 << (VerilogParser.TASK - 64)) | (1 << (VerilogParser.TIME - 64)) | (1 << (VerilogParser.TRAN - 64)) | (1 << (VerilogParser.TRANIF0 - 64)) | (1 << (VerilogParser.TRANIF1 - 64)) | (1 << (VerilogParser.TRI - 64)) | (1 << (VerilogParser.TRI0 - 64)) | (1 << (VerilogParser.TRI1 - 64)) | (1 << (VerilogParser.TRIAND - 64)) | (1 << (VerilogParser.TRIOR - 64)) | (1 << (VerilogParser.TRIREG - 64)) | (1 << (VerilogParser.WAND - 64)) | (1 << (VerilogParser.WIRE - 64)) | (1 << (VerilogParser.WOR - 64)) | (1 << (VerilogParser.XNOR - 64)) | (1 << (VerilogParser.XOR - 64)))) != 0) or ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                    self.state = 1193
                    self.non_port_module_item()
                    self.state = 1198
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1199
                self.match(VerilogParser.ENDMODULE)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_keywordContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MODULE(self):
            return self.getToken(VerilogParser.MODULE, 0)

        def MACROMODULE(self):
            return self.getToken(VerilogParser.MACROMODULE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_keyword" ):
                listener.enterModule_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_keyword" ):
                listener.exitModule_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_keyword" ):
                return visitor.visitModule_keyword(self)
            else:
                return visitor.visitChildren(self)




    def module_keyword(self):

        localctx = VerilogParser.Module_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 140, self.RULE_module_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1203
            _la = self._input.LA(1)
            if not(_la==VerilogParser.MACROMODULE or _la==VerilogParser.MODULE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_parameter_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HASH(self):
            return self.getToken(VerilogParser.HASH, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def parameter_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Parameter_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Parameter_declarationContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_parameter_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_parameter_port_list" ):
                listener.enterModule_parameter_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_parameter_port_list" ):
                listener.exitModule_parameter_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_parameter_port_list" ):
                return visitor.visitModule_parameter_port_list(self)
            else:
                return visitor.visitChildren(self)




    def module_parameter_port_list(self):

        localctx = VerilogParser.Module_parameter_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 142, self.RULE_module_parameter_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1205
            self.match(VerilogParser.HASH)
            self.state = 1206
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1207
            self.parameter_declaration()
            self.state = 1212
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1208
                self.match(VerilogParser.COMMA)
                self.state = 1209
                self.parameter_declaration()
                self.state = 1214
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1215
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_portsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def port(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.PortContext)
            else:
                return self.getTypedRuleContext(VerilogParser.PortContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_ports

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_ports" ):
                listener.enterList_of_ports(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_ports" ):
                listener.exitList_of_ports(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_ports" ):
                return visitor.visitList_of_ports(self)
            else:
                return visitor.visitChildren(self)




    def list_of_ports(self):

        localctx = VerilogParser.List_of_portsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 144, self.RULE_list_of_ports)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1217
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 1218
            self.port()
            self.state = 1223
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1219
                self.match(VerilogParser.COMMA)
                self.state = 1220
                self.port()
                self.state = 1225
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1226
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_declarationsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def port_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Port_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Port_declarationContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_port_declarations

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_declarations" ):
                listener.enterList_of_port_declarations(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_declarations" ):
                listener.exitList_of_port_declarations(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_declarations" ):
                return visitor.visitList_of_port_declarations(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_declarations(self):

        localctx = VerilogParser.List_of_port_declarationsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 146, self.RULE_list_of_port_declarations)
        self._la = 0 # Token type
        try:
            self.state = 1241
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,49,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1228
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1229
                self.port_declaration()
                self.state = 1234
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 1230
                    self.match(VerilogParser.COMMA)
                    self.state = 1231
                    self.port_declaration()
                    self.state = 1236
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1237
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1239
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1240
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class PortContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_expression(self):
            return self.getTypedRuleContext(VerilogParser.Port_expressionContext,0)


        def DOT(self):
            return self.getToken(VerilogParser.DOT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_port

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort" ):
                listener.enterPort(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort" ):
                listener.exitPort(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort" ):
                return visitor.visitPort(self)
            else:
                return visitor.visitChildren(self)




    def port(self):

        localctx = VerilogParser.PortContext(self, self._ctx, self.state)
        self.enterRule(localctx, 148, self.RULE_port)
        self._la = 0 # Token type
        try:
            self.state = 1254
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.RIGHT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.COMMA]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1244
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 290)) & ~0x3f) == 0 and ((1 << (_la - 290)) & ((1 << (VerilogParser.ESCAPED_IDENTIFIER - 290)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 290)) | (1 << (VerilogParser.LEFT_BRACE - 290)))) != 0):
                    self.state = 1243
                    self.port_expression()


                pass
            elif token in [VerilogParser.DOT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1246
                self.match(VerilogParser.DOT)
                self.state = 1247
                self.port_identifier()
                self.state = 1248
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1250
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 290)) & ~0x3f) == 0 and ((1 << (_la - 290)) & ((1 << (VerilogParser.ESCAPED_IDENTIFIER - 290)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 290)) | (1 << (VerilogParser.LEFT_BRACE - 290)))) != 0):
                    self.state = 1249
                    self.port_expression()


                self.state = 1252
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_reference(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Port_referenceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Port_referenceContext,i)


        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_port_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_expression" ):
                listener.enterPort_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_expression" ):
                listener.exitPort_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_expression" ):
                return visitor.visitPort_expression(self)
            else:
                return visitor.visitChildren(self)




    def port_expression(self):

        localctx = VerilogParser.Port_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 150, self.RULE_port_expression)
        self._la = 0 # Token type
        try:
            self.state = 1268
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1256
                self.port_reference()
                pass
            elif token in [VerilogParser.LEFT_BRACE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1257
                self.match(VerilogParser.LEFT_BRACE)
                self.state = 1258
                self.port_reference()
                self.state = 1263
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 1259
                    self.match(VerilogParser.COMMA)
                    self.state = 1260
                    self.port_reference()
                    self.state = 1265
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1266
                self.match(VerilogParser.RIGHT_BRACE)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_referenceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def LEFT_BRACKET(self):
            return self.getToken(VerilogParser.LEFT_BRACKET, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RIGHT_BRACKET(self):
            return self.getToken(VerilogParser.RIGHT_BRACKET, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_port_reference

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_reference" ):
                listener.enterPort_reference(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_reference" ):
                listener.exitPort_reference(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_reference" ):
                return visitor.visitPort_reference(self)
            else:
                return visitor.visitChildren(self)




    def port_reference(self):

        localctx = VerilogParser.Port_referenceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 152, self.RULE_port_reference)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1270
            self.port_identifier()
            self.state = 1275
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 1271
                self.match(VerilogParser.LEFT_BRACKET)
                self.state = 1272
                self.constant_range_expression()
                self.state = 1273
                self.match(VerilogParser.RIGHT_BRACKET)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def inout_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Inout_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Input_declarationContext,0)


        def output_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Output_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_declaration" ):
                listener.enterPort_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_declaration" ):
                listener.exitPort_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_declaration" ):
                return visitor.visitPort_declaration(self)
            else:
                return visitor.visitChildren(self)




    def port_declaration(self):

        localctx = VerilogParser.Port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 154, self.RULE_port_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1298
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,59,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1280
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1277
                    self.attribute_instance()
                    self.state = 1282
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1283
                self.inout_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1287
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1284
                    self.attribute_instance()
                    self.state = 1289
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1290
                self.input_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1294
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1291
                    self.attribute_instance()
                    self.state = 1296
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1297
                self.output_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Port_declarationContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def non_port_module_item(self):
            return self.getTypedRuleContext(VerilogParser.Non_port_module_itemContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_item" ):
                listener.enterModule_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_item" ):
                listener.exitModule_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_item" ):
                return visitor.visitModule_item(self)
            else:
                return visitor.visitChildren(self)




    def module_item(self):

        localctx = VerilogParser.Module_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 156, self.RULE_module_item)
        try:
            self.state = 1304
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,60,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1300
                self.port_declaration()
                self.state = 1301
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1303
                self.non_port_module_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_or_generate_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_or_generate_item_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Module_or_generate_item_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def local_parameter_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Local_parameter_declarationContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def parameter_override(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_overrideContext,0)


        def continuous_assign(self):
            return self.getTypedRuleContext(VerilogParser.Continuous_assignContext,0)


        def gate_instantiation(self):
            return self.getTypedRuleContext(VerilogParser.Gate_instantiationContext,0)


        def module_instantiation(self):
            return self.getTypedRuleContext(VerilogParser.Module_instantiationContext,0)


        def initial_construct(self):
            return self.getTypedRuleContext(VerilogParser.Initial_constructContext,0)


        def always_construct(self):
            return self.getTypedRuleContext(VerilogParser.Always_constructContext,0)


        def loop_generate_construct(self):
            return self.getTypedRuleContext(VerilogParser.Loop_generate_constructContext,0)


        def conditional_generate_construct(self):
            return self.getTypedRuleContext(VerilogParser.Conditional_generate_constructContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_or_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_or_generate_item" ):
                listener.enterModule_or_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_or_generate_item" ):
                listener.exitModule_or_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_or_generate_item" ):
                return visitor.visitModule_or_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def module_or_generate_item(self):

        localctx = VerilogParser.Module_or_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 158, self.RULE_module_or_generate_item)
        self._la = 0 # Token type
        try:
            self.state = 1378
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,71,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1309
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1306
                    self.attribute_instance()
                    self.state = 1311
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1312
                self.module_or_generate_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1316
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1313
                    self.attribute_instance()
                    self.state = 1318
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1319
                self.local_parameter_declaration()
                self.state = 1320
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1325
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1322
                    self.attribute_instance()
                    self.state = 1327
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1328
                self.parameter_override()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1332
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1329
                    self.attribute_instance()
                    self.state = 1334
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1335
                self.continuous_assign()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1339
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1336
                    self.attribute_instance()
                    self.state = 1341
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1342
                self.gate_instantiation()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1346
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1343
                    self.attribute_instance()
                    self.state = 1348
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1349
                self.module_instantiation()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1353
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1350
                    self.attribute_instance()
                    self.state = 1355
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1356
                self.initial_construct()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1360
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1357
                    self.attribute_instance()
                    self.state = 1362
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1363
                self.always_construct()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 1367
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1364
                    self.attribute_instance()
                    self.state = 1369
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1370
                self.loop_generate_construct()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 1374
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,70,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 1371
                        self.attribute_instance() 
                    self.state = 1376
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,70,self._ctx)

                self.state = 1377
                self.conditional_generate_construct()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_or_generate_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Net_declarationContext,0)


        def reg_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Reg_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Integer_declarationContext,0)


        def real_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Real_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Time_declarationContext,0)


        def realtime_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Realtime_declarationContext,0)


        def event_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Event_declarationContext,0)


        def genvar_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_declarationContext,0)


        def task_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Task_declarationContext,0)


        def function_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Function_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_or_generate_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_or_generate_item_declaration" ):
                listener.enterModule_or_generate_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_or_generate_item_declaration" ):
                listener.exitModule_or_generate_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_or_generate_item_declaration" ):
                return visitor.visitModule_or_generate_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def module_or_generate_item_declaration(self):

        localctx = VerilogParser.Module_or_generate_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 160, self.RULE_module_or_generate_item_declaration)
        try:
            self.state = 1390
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.SUPPLY0, VerilogParser.SUPPLY1, VerilogParser.TRI, VerilogParser.TRI0, VerilogParser.TRI1, VerilogParser.TRIAND, VerilogParser.TRIOR, VerilogParser.TRIREG, VerilogParser.WAND, VerilogParser.WIRE, VerilogParser.WOR]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1380
                self.net_declaration()
                pass
            elif token in [VerilogParser.REG]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1381
                self.reg_declaration()
                pass
            elif token in [VerilogParser.INTEGER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1382
                self.integer_declaration()
                pass
            elif token in [VerilogParser.REAL]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1383
                self.real_declaration()
                pass
            elif token in [VerilogParser.TIME]:
                self.enterOuterAlt(localctx, 5)
                self.state = 1384
                self.time_declaration()
                pass
            elif token in [VerilogParser.REALTIME]:
                self.enterOuterAlt(localctx, 6)
                self.state = 1385
                self.realtime_declaration()
                pass
            elif token in [VerilogParser.EVENT]:
                self.enterOuterAlt(localctx, 7)
                self.state = 1386
                self.event_declaration()
                pass
            elif token in [VerilogParser.GENVAR]:
                self.enterOuterAlt(localctx, 8)
                self.state = 1387
                self.genvar_declaration()
                pass
            elif token in [VerilogParser.TASK]:
                self.enterOuterAlt(localctx, 9)
                self.state = 1388
                self.task_declaration()
                pass
            elif token in [VerilogParser.FUNCTION]:
                self.enterOuterAlt(localctx, 10)
                self.state = 1389
                self.function_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Non_port_module_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_or_generate_item(self):
            return self.getTypedRuleContext(VerilogParser.Module_or_generate_itemContext,0)


        def generate_region(self):
            return self.getTypedRuleContext(VerilogParser.Generate_regionContext,0)


        def specify_block(self):
            return self.getTypedRuleContext(VerilogParser.Specify_blockContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_declarationContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def specparam_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Specparam_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_non_port_module_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNon_port_module_item" ):
                listener.enterNon_port_module_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNon_port_module_item" ):
                listener.exitNon_port_module_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNon_port_module_item" ):
                return visitor.visitNon_port_module_item(self)
            else:
                return visitor.visitChildren(self)




    def non_port_module_item(self):

        localctx = VerilogParser.Non_port_module_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 162, self.RULE_non_port_module_item)
        self._la = 0 # Token type
        try:
            self.state = 1411
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,75,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1392
                self.module_or_generate_item()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1393
                self.generate_region()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1394
                self.specify_block()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1398
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1395
                    self.attribute_instance()
                    self.state = 1400
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1401
                self.parameter_declaration()
                self.state = 1402
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1407
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1404
                    self.attribute_instance()
                    self.state = 1409
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1410
                self.specparam_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_overrideContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DEFPARAM(self):
            return self.getToken(VerilogParser.DEFPARAM, 0)

        def list_of_param_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_param_assignmentsContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_override

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_override" ):
                listener.enterParameter_override(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_override" ):
                listener.exitParameter_override(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_override" ):
                return visitor.visitParameter_override(self)
            else:
                return visitor.visitChildren(self)




    def parameter_override(self):

        localctx = VerilogParser.Parameter_overrideContext(self, self._ctx, self.state)
        self.enterRule(localctx, 164, self.RULE_parameter_override)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1413
            self.match(VerilogParser.DEFPARAM)
            self.state = 1414
            self.list_of_param_assignments()
            self.state = 1415
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Config_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CONFIG(self):
            return self.getToken(VerilogParser.CONFIG, 0)

        def config_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Config_identifierContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def design_statement(self):
            return self.getTypedRuleContext(VerilogParser.Design_statementContext,0)


        def ENDCONFIG(self):
            return self.getToken(VerilogParser.ENDCONFIG, 0)

        def config_rule_statement(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Config_rule_statementContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Config_rule_statementContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_config_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_declaration" ):
                listener.enterConfig_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_declaration" ):
                listener.exitConfig_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_declaration" ):
                return visitor.visitConfig_declaration(self)
            else:
                return visitor.visitChildren(self)




    def config_declaration(self):

        localctx = VerilogParser.Config_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 166, self.RULE_config_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1417
            self.match(VerilogParser.CONFIG)
            self.state = 1418
            self.config_identifier()
            self.state = 1419
            self.match(VerilogParser.SEMICOLON)
            self.state = 1420
            self.design_statement()
            self.state = 1424
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.CELL) | (1 << VerilogParser.DEFAULT) | (1 << VerilogParser.INSTANCE))) != 0):
                self.state = 1421
                self.config_rule_statement()
                self.state = 1426
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1427
            self.match(VerilogParser.ENDCONFIG)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Design_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DESIGN(self):
            return self.getToken(VerilogParser.DESIGN, 0)

        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def cell_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Cell_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Cell_identifierContext,i)


        def library_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Library_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Library_identifierContext,i)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.DOT)
            else:
                return self.getToken(VerilogParser.DOT, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_design_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDesign_statement" ):
                listener.enterDesign_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDesign_statement" ):
                listener.exitDesign_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDesign_statement" ):
                return visitor.visitDesign_statement(self)
            else:
                return visitor.visitChildren(self)




    def design_statement(self):

        localctx = VerilogParser.Design_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 168, self.RULE_design_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1429
            self.match(VerilogParser.DESIGN)
            self.state = 1438
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 1433
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,77,self._ctx)
                if la_ == 1:
                    self.state = 1430
                    self.library_identifier()
                    self.state = 1431
                    self.match(VerilogParser.DOT)


                self.state = 1435
                self.cell_identifier()
                self.state = 1440
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1441
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Config_rule_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def default_clause(self):
            return self.getTypedRuleContext(VerilogParser.Default_clauseContext,0)


        def liblist_clause(self):
            return self.getTypedRuleContext(VerilogParser.Liblist_clauseContext,0)


        def inst_clause(self):
            return self.getTypedRuleContext(VerilogParser.Inst_clauseContext,0)


        def use_clause(self):
            return self.getTypedRuleContext(VerilogParser.Use_clauseContext,0)


        def cell_clause(self):
            return self.getTypedRuleContext(VerilogParser.Cell_clauseContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_config_rule_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_rule_statement" ):
                listener.enterConfig_rule_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_rule_statement" ):
                listener.exitConfig_rule_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_rule_statement" ):
                return visitor.visitConfig_rule_statement(self)
            else:
                return visitor.visitChildren(self)




    def config_rule_statement(self):

        localctx = VerilogParser.Config_rule_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 170, self.RULE_config_rule_statement)
        try:
            self.state = 1458
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,79,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1443
                self.default_clause()
                self.state = 1444
                self.liblist_clause()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1446
                self.inst_clause()
                self.state = 1447
                self.liblist_clause()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1449
                self.inst_clause()
                self.state = 1450
                self.use_clause()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1452
                self.cell_clause()
                self.state = 1453
                self.liblist_clause()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1455
                self.cell_clause()
                self.state = 1456
                self.use_clause()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Default_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DEFAULT(self):
            return self.getToken(VerilogParser.DEFAULT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_default_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefault_clause" ):
                listener.enterDefault_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefault_clause" ):
                listener.exitDefault_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefault_clause" ):
                return visitor.visitDefault_clause(self)
            else:
                return visitor.visitChildren(self)




    def default_clause(self):

        localctx = VerilogParser.Default_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 172, self.RULE_default_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1460
            self.match(VerilogParser.DEFAULT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inst_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INSTANCE(self):
            return self.getToken(VerilogParser.INSTANCE, 0)

        def inst_name(self):
            return self.getTypedRuleContext(VerilogParser.Inst_nameContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_inst_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInst_clause" ):
                listener.enterInst_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInst_clause" ):
                listener.exitInst_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInst_clause" ):
                return visitor.visitInst_clause(self)
            else:
                return visitor.visitChildren(self)




    def inst_clause(self):

        localctx = VerilogParser.Inst_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 174, self.RULE_inst_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1462
            self.match(VerilogParser.INSTANCE)
            self.state = 1463
            self.inst_name()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inst_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def topmodule_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Topmodule_identifierContext,0)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.DOT)
            else:
                return self.getToken(VerilogParser.DOT, i)

        def instance_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Instance_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Instance_identifierContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_inst_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInst_name" ):
                listener.enterInst_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInst_name" ):
                listener.exitInst_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInst_name" ):
                return visitor.visitInst_name(self)
            else:
                return visitor.visitChildren(self)




    def inst_name(self):

        localctx = VerilogParser.Inst_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 176, self.RULE_inst_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1465
            self.topmodule_identifier()
            self.state = 1470
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.DOT:
                self.state = 1466
                self.match(VerilogParser.DOT)
                self.state = 1467
                self.instance_identifier()
                self.state = 1472
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cell_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CELL(self):
            return self.getToken(VerilogParser.CELL, 0)

        def cell_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Cell_identifierContext,0)


        def library_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Library_identifierContext,0)


        def DOT(self):
            return self.getToken(VerilogParser.DOT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_cell_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCell_clause" ):
                listener.enterCell_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCell_clause" ):
                listener.exitCell_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCell_clause" ):
                return visitor.visitCell_clause(self)
            else:
                return visitor.visitChildren(self)




    def cell_clause(self):

        localctx = VerilogParser.Cell_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 178, self.RULE_cell_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1473
            self.match(VerilogParser.CELL)
            self.state = 1477
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,81,self._ctx)
            if la_ == 1:
                self.state = 1474
                self.library_identifier()
                self.state = 1475
                self.match(VerilogParser.DOT)


            self.state = 1479
            self.cell_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Liblist_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LIBLIST(self):
            return self.getToken(VerilogParser.LIBLIST, 0)

        def library_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Library_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Library_identifierContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_liblist_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLiblist_clause" ):
                listener.enterLiblist_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLiblist_clause" ):
                listener.exitLiblist_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLiblist_clause" ):
                return visitor.visitLiblist_clause(self)
            else:
                return visitor.visitChildren(self)




    def liblist_clause(self):

        localctx = VerilogParser.Liblist_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 180, self.RULE_liblist_clause)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1481
            self.match(VerilogParser.LIBLIST)
            self.state = 1485
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 1482
                self.library_identifier()
                self.state = 1487
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Use_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def USE(self):
            return self.getToken(VerilogParser.USE, 0)

        def cell_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Cell_identifierContext,0)


        def library_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Library_identifierContext,0)


        def DOT(self):
            return self.getToken(VerilogParser.DOT, 0)

        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def CONFIG(self):
            return self.getToken(VerilogParser.CONFIG, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_use_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUse_clause" ):
                listener.enterUse_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUse_clause" ):
                listener.exitUse_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUse_clause" ):
                return visitor.visitUse_clause(self)
            else:
                return visitor.visitChildren(self)




    def use_clause(self):

        localctx = VerilogParser.Use_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 182, self.RULE_use_clause)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1488
            self.match(VerilogParser.USE)
            self.state = 1492
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,83,self._ctx)
            if la_ == 1:
                self.state = 1489
                self.library_identifier()
                self.state = 1490
                self.match(VerilogParser.DOT)


            self.state = 1494
            self.cell_identifier()
            self.state = 1497
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.COLON:
                self.state = 1495
                self.match(VerilogParser.COLON)
                self.state = 1496
                self.match(VerilogParser.CONFIG)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Local_parameter_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LOCALPARAM(self):
            return self.getToken(VerilogParser.LOCALPARAM, 0)

        def list_of_param_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_param_assignmentsContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def parameter_type(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_local_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLocal_parameter_declaration" ):
                listener.enterLocal_parameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLocal_parameter_declaration" ):
                listener.exitLocal_parameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLocal_parameter_declaration" ):
                return visitor.visitLocal_parameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def local_parameter_declaration(self):

        localctx = VerilogParser.Local_parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 184, self.RULE_local_parameter_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1511
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,87,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1499
                self.match(VerilogParser.LOCALPARAM)
                self.state = 1501
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1500
                    self.match(VerilogParser.SIGNED)


                self.state = 1504
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 1503
                    self.range_()


                self.state = 1506
                self.list_of_param_assignments()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1507
                self.match(VerilogParser.LOCALPARAM)
                self.state = 1508
                self.parameter_type()
                self.state = 1509
                self.list_of_param_assignments()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PARAMETER(self):
            return self.getToken(VerilogParser.PARAMETER, 0)

        def list_of_param_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_param_assignmentsContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def parameter_type(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_declaration" ):
                listener.enterParameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_declaration" ):
                listener.exitParameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_declaration" ):
                return visitor.visitParameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def parameter_declaration(self):

        localctx = VerilogParser.Parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 186, self.RULE_parameter_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1525
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,90,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1513
                self.match(VerilogParser.PARAMETER)
                self.state = 1515
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1514
                    self.match(VerilogParser.SIGNED)


                self.state = 1518
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 1517
                    self.range_()


                self.state = 1520
                self.list_of_param_assignments()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1521
                self.match(VerilogParser.PARAMETER)
                self.state = 1522
                self.parameter_type()
                self.state = 1523
                self.list_of_param_assignments()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specparam_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SPECPARAM(self):
            return self.getToken(VerilogParser.SPECPARAM, 0)

        def list_of_specparam_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_specparam_assignmentsContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specparam_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_declaration" ):
                listener.enterSpecparam_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_declaration" ):
                listener.exitSpecparam_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_declaration" ):
                return visitor.visitSpecparam_declaration(self)
            else:
                return visitor.visitChildren(self)




    def specparam_declaration(self):

        localctx = VerilogParser.Specparam_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 188, self.RULE_specparam_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1527
            self.match(VerilogParser.SPECPARAM)
            self.state = 1529
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 1528
                self.range_()


            self.state = 1531
            self.list_of_specparam_assignments()
            self.state = 1532
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_type" ):
                listener.enterParameter_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_type" ):
                listener.exitParameter_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_type" ):
                return visitor.visitParameter_type(self)
            else:
                return visitor.visitChildren(self)




    def parameter_type(self):

        localctx = VerilogParser.Parameter_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 190, self.RULE_parameter_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1534
            _la = self._input.LA(1)
            if not(((((_la - 50)) & ~0x3f) == 0 and ((1 << (_la - 50)) & ((1 << (VerilogParser.INTEGER - 50)) | (1 << (VerilogParser.REAL - 50)) | (1 << (VerilogParser.REALTIME - 50)) | (1 << (VerilogParser.TIME - 50)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INOUT(self):
            return self.getToken(VerilogParser.INOUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def net_type(self):
            return self.getTypedRuleContext(VerilogParser.Net_typeContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_inout_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_declaration" ):
                listener.enterInout_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_declaration" ):
                listener.exitInout_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_declaration" ):
                return visitor.visitInout_declaration(self)
            else:
                return visitor.visitChildren(self)




    def inout_declaration(self):

        localctx = VerilogParser.Inout_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 192, self.RULE_inout_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1536
            self.match(VerilogParser.INOUT)
            self.state = 1538
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 98)) & ~0x3f) == 0 and ((1 << (_la - 98)) & ((1 << (VerilogParser.SUPPLY0 - 98)) | (1 << (VerilogParser.SUPPLY1 - 98)) | (1 << (VerilogParser.TRI - 98)) | (1 << (VerilogParser.TRI0 - 98)) | (1 << (VerilogParser.TRI1 - 98)) | (1 << (VerilogParser.TRIAND - 98)) | (1 << (VerilogParser.TRIOR - 98)) | (1 << (VerilogParser.WAND - 98)) | (1 << (VerilogParser.WIRE - 98)) | (1 << (VerilogParser.WOR - 98)))) != 0):
                self.state = 1537
                self.net_type()


            self.state = 1541
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.SIGNED:
                self.state = 1540
                self.match(VerilogParser.SIGNED)


            self.state = 1544
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 1543
                self.range_()


            self.state = 1546
            self.list_of_port_identifiers()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INPUT(self):
            return self.getToken(VerilogParser.INPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def net_type(self):
            return self.getTypedRuleContext(VerilogParser.Net_typeContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_input_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_declaration" ):
                listener.enterInput_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_declaration" ):
                listener.exitInput_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_declaration" ):
                return visitor.visitInput_declaration(self)
            else:
                return visitor.visitChildren(self)




    def input_declaration(self):

        localctx = VerilogParser.Input_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 194, self.RULE_input_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1548
            self.match(VerilogParser.INPUT)
            self.state = 1550
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 98)) & ~0x3f) == 0 and ((1 << (_la - 98)) & ((1 << (VerilogParser.SUPPLY0 - 98)) | (1 << (VerilogParser.SUPPLY1 - 98)) | (1 << (VerilogParser.TRI - 98)) | (1 << (VerilogParser.TRI0 - 98)) | (1 << (VerilogParser.TRI1 - 98)) | (1 << (VerilogParser.TRIAND - 98)) | (1 << (VerilogParser.TRIOR - 98)) | (1 << (VerilogParser.WAND - 98)) | (1 << (VerilogParser.WIRE - 98)) | (1 << (VerilogParser.WOR - 98)))) != 0):
                self.state = 1549
                self.net_type()


            self.state = 1553
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.SIGNED:
                self.state = 1552
                self.match(VerilogParser.SIGNED)


            self.state = 1556
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 1555
                self.range_()


            self.state = 1558
            self.list_of_port_identifiers()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def OUTPUT(self):
            return self.getToken(VerilogParser.OUTPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def net_type(self):
            return self.getTypedRuleContext(VerilogParser.Net_typeContext,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def list_of_variable_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_variable_port_identifiersContext,0)


        def output_variable_type(self):
            return self.getTypedRuleContext(VerilogParser.Output_variable_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_output_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_declaration" ):
                listener.enterOutput_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_declaration" ):
                listener.exitOutput_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_declaration" ):
                return visitor.visitOutput_declaration(self)
            else:
                return visitor.visitChildren(self)




    def output_declaration(self):

        localctx = VerilogParser.Output_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 196, self.RULE_output_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1584
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,103,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1560
                self.match(VerilogParser.OUTPUT)
                self.state = 1562
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 98)) & ~0x3f) == 0 and ((1 << (_la - 98)) & ((1 << (VerilogParser.SUPPLY0 - 98)) | (1 << (VerilogParser.SUPPLY1 - 98)) | (1 << (VerilogParser.TRI - 98)) | (1 << (VerilogParser.TRI0 - 98)) | (1 << (VerilogParser.TRI1 - 98)) | (1 << (VerilogParser.TRIAND - 98)) | (1 << (VerilogParser.TRIOR - 98)) | (1 << (VerilogParser.WAND - 98)) | (1 << (VerilogParser.WIRE - 98)) | (1 << (VerilogParser.WOR - 98)))) != 0):
                    self.state = 1561
                    self.net_type()


                self.state = 1565
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1564
                    self.match(VerilogParser.SIGNED)


                self.state = 1568
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 1567
                    self.range_()


                self.state = 1570
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1571
                self.match(VerilogParser.OUTPUT)
                self.state = 1572
                self.match(VerilogParser.REG)
                self.state = 1574
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1573
                    self.match(VerilogParser.SIGNED)


                self.state = 1577
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 1576
                    self.range_()


                self.state = 1579
                self.list_of_variable_port_identifiers()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1580
                self.match(VerilogParser.OUTPUT)
                self.state = 1581
                self.output_variable_type()
                self.state = 1582
                self.list_of_variable_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EVENT(self):
            return self.getToken(VerilogParser.EVENT, 0)

        def list_of_event_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_event_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_event_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_declaration" ):
                listener.enterEvent_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_declaration" ):
                listener.exitEvent_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_declaration" ):
                return visitor.visitEvent_declaration(self)
            else:
                return visitor.visitChildren(self)




    def event_declaration(self):

        localctx = VerilogParser.Event_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 198, self.RULE_event_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1586
            self.match(VerilogParser.EVENT)
            self.state = 1587
            self.list_of_event_identifiers()
            self.state = 1588
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Integer_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def list_of_variable_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_variable_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_integer_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInteger_declaration" ):
                listener.enterInteger_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInteger_declaration" ):
                listener.exitInteger_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInteger_declaration" ):
                return visitor.visitInteger_declaration(self)
            else:
                return visitor.visitChildren(self)




    def integer_declaration(self):

        localctx = VerilogParser.Integer_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 200, self.RULE_integer_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1590
            self.match(VerilogParser.INTEGER)
            self.state = 1591
            self.list_of_variable_identifiers()
            self.state = 1592
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_type(self):
            return self.getTypedRuleContext(VerilogParser.Net_typeContext,0)


        def list_of_net_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_net_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def delay3(self):
            return self.getTypedRuleContext(VerilogParser.Delay3Context,0)


        def list_of_net_decl_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_net_decl_assignmentsContext,0)


        def drive_strength(self):
            return self.getTypedRuleContext(VerilogParser.Drive_strengthContext,0)


        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def VECTORED(self):
            return self.getToken(VerilogParser.VECTORED, 0)

        def SCALARED(self):
            return self.getToken(VerilogParser.SCALARED, 0)

        def TRIREG(self):
            return self.getToken(VerilogParser.TRIREG, 0)

        def charge_strength(self):
            return self.getTypedRuleContext(VerilogParser.Charge_strengthContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_declaration" ):
                listener.enterNet_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_declaration" ):
                listener.exitNet_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_declaration" ):
                return visitor.visitNet_declaration(self)
            else:
                return visitor.visitChildren(self)




    def net_declaration(self):

        localctx = VerilogParser.Net_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 202, self.RULE_net_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1708
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,130,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1594
                self.net_type()
                self.state = 1596
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1595
                    self.match(VerilogParser.SIGNED)


                self.state = 1599
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1598
                    self.delay3()


                self.state = 1601
                self.list_of_net_identifiers()
                self.state = 1602
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1604
                self.net_type()
                self.state = 1606
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1605
                    self.drive_strength()


                self.state = 1609
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1608
                    self.match(VerilogParser.SIGNED)


                self.state = 1612
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1611
                    self.delay3()


                self.state = 1614
                self.list_of_net_decl_assignments()
                self.state = 1615
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1617
                self.net_type()
                self.state = 1619
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED:
                    self.state = 1618
                    _la = self._input.LA(1)
                    if not(_la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 1622
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1621
                    self.match(VerilogParser.SIGNED)


                self.state = 1624
                self.range_()
                self.state = 1626
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1625
                    self.delay3()


                self.state = 1628
                self.list_of_net_identifiers()
                self.state = 1629
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1631
                self.net_type()
                self.state = 1633
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1632
                    self.drive_strength()


                self.state = 1636
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED:
                    self.state = 1635
                    _la = self._input.LA(1)
                    if not(_la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 1639
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1638
                    self.match(VerilogParser.SIGNED)


                self.state = 1641
                self.range_()
                self.state = 1643
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1642
                    self.delay3()


                self.state = 1645
                self.list_of_net_decl_assignments()
                self.state = 1646
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1648
                self.match(VerilogParser.TRIREG)
                self.state = 1650
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1649
                    self.charge_strength()


                self.state = 1653
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1652
                    self.match(VerilogParser.SIGNED)


                self.state = 1656
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1655
                    self.delay3()


                self.state = 1658
                self.list_of_net_identifiers()
                self.state = 1659
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1661
                self.match(VerilogParser.TRIREG)
                self.state = 1663
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1662
                    self.drive_strength()


                self.state = 1666
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1665
                    self.match(VerilogParser.SIGNED)


                self.state = 1669
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1668
                    self.delay3()


                self.state = 1671
                self.list_of_net_decl_assignments()
                self.state = 1672
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1674
                self.match(VerilogParser.TRIREG)
                self.state = 1676
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1675
                    self.charge_strength()


                self.state = 1679
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED:
                    self.state = 1678
                    _la = self._input.LA(1)
                    if not(_la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 1682
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1681
                    self.match(VerilogParser.SIGNED)


                self.state = 1684
                self.range_()
                self.state = 1686
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1685
                    self.delay3()


                self.state = 1688
                self.list_of_net_identifiers()
                self.state = 1689
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1691
                self.match(VerilogParser.TRIREG)
                self.state = 1693
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 1692
                    self.drive_strength()


                self.state = 1696
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED:
                    self.state = 1695
                    _la = self._input.LA(1)
                    if not(_la==VerilogParser.SCALARED or _la==VerilogParser.VECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 1699
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 1698
                    self.match(VerilogParser.SIGNED)


                self.state = 1701
                self.range_()
                self.state = 1703
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 1702
                    self.delay3()


                self.state = 1705
                self.list_of_net_decl_assignments()
                self.state = 1706
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Real_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def list_of_real_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_real_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_real_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_declaration" ):
                listener.enterReal_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_declaration" ):
                listener.exitReal_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_declaration" ):
                return visitor.visitReal_declaration(self)
            else:
                return visitor.visitChildren(self)




    def real_declaration(self):

        localctx = VerilogParser.Real_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 204, self.RULE_real_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1710
            self.match(VerilogParser.REAL)
            self.state = 1711
            self.list_of_real_identifiers()
            self.state = 1712
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Realtime_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def list_of_real_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_real_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_realtime_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRealtime_declaration" ):
                listener.enterRealtime_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRealtime_declaration" ):
                listener.exitRealtime_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRealtime_declaration" ):
                return visitor.visitRealtime_declaration(self)
            else:
                return visitor.visitChildren(self)




    def realtime_declaration(self):

        localctx = VerilogParser.Realtime_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 206, self.RULE_realtime_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1714
            self.match(VerilogParser.REALTIME)
            self.state = 1715
            self.list_of_real_identifiers()
            self.state = 1716
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Reg_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def list_of_variable_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_variable_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_reg_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReg_declaration" ):
                listener.enterReg_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReg_declaration" ):
                listener.exitReg_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReg_declaration" ):
                return visitor.visitReg_declaration(self)
            else:
                return visitor.visitChildren(self)




    def reg_declaration(self):

        localctx = VerilogParser.Reg_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 208, self.RULE_reg_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1718
            self.match(VerilogParser.REG)
            self.state = 1720
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.SIGNED:
                self.state = 1719
                self.match(VerilogParser.SIGNED)


            self.state = 1723
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 1722
                self.range_()


            self.state = 1725
            self.list_of_variable_identifiers()
            self.state = 1726
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Time_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def list_of_variable_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_variable_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_time_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTime_declaration" ):
                listener.enterTime_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTime_declaration" ):
                listener.exitTime_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTime_declaration" ):
                return visitor.visitTime_declaration(self)
            else:
                return visitor.visitChildren(self)




    def time_declaration(self):

        localctx = VerilogParser.Time_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 210, self.RULE_time_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1728
            self.match(VerilogParser.TIME)
            self.state = 1729
            self.list_of_variable_identifiers()
            self.state = 1730
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SUPPLY0(self):
            return self.getToken(VerilogParser.SUPPLY0, 0)

        def SUPPLY1(self):
            return self.getToken(VerilogParser.SUPPLY1, 0)

        def TRI(self):
            return self.getToken(VerilogParser.TRI, 0)

        def TRIAND(self):
            return self.getToken(VerilogParser.TRIAND, 0)

        def TRIOR(self):
            return self.getToken(VerilogParser.TRIOR, 0)

        def TRI0(self):
            return self.getToken(VerilogParser.TRI0, 0)

        def TRI1(self):
            return self.getToken(VerilogParser.TRI1, 0)

        def WIRE(self):
            return self.getToken(VerilogParser.WIRE, 0)

        def WAND(self):
            return self.getToken(VerilogParser.WAND, 0)

        def WOR(self):
            return self.getToken(VerilogParser.WOR, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_net_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_type" ):
                listener.enterNet_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_type" ):
                listener.exitNet_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_type" ):
                return visitor.visitNet_type(self)
            else:
                return visitor.visitChildren(self)




    def net_type(self):

        localctx = VerilogParser.Net_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 212, self.RULE_net_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1732
            _la = self._input.LA(1)
            if not(((((_la - 98)) & ~0x3f) == 0 and ((1 << (_la - 98)) & ((1 << (VerilogParser.SUPPLY0 - 98)) | (1 << (VerilogParser.SUPPLY1 - 98)) | (1 << (VerilogParser.TRI - 98)) | (1 << (VerilogParser.TRI0 - 98)) | (1 << (VerilogParser.TRI1 - 98)) | (1 << (VerilogParser.TRIAND - 98)) | (1 << (VerilogParser.TRIOR - 98)) | (1 << (VerilogParser.WAND - 98)) | (1 << (VerilogParser.WIRE - 98)) | (1 << (VerilogParser.WOR - 98)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_variable_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_output_variable_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_variable_type" ):
                listener.enterOutput_variable_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_variable_type" ):
                listener.exitOutput_variable_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_variable_type" ):
                return visitor.visitOutput_variable_type(self)
            else:
                return visitor.visitChildren(self)




    def output_variable_type(self):

        localctx = VerilogParser.Output_variable_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 214, self.RULE_output_variable_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1734
            _la = self._input.LA(1)
            if not(_la==VerilogParser.INTEGER or _la==VerilogParser.TIME):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Real_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def real_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Real_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_real_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_type" ):
                listener.enterReal_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_type" ):
                listener.exitReal_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_type" ):
                return visitor.visitReal_type(self)
            else:
                return visitor.visitChildren(self)




    def real_type(self):

        localctx = VerilogParser.Real_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 216, self.RULE_real_type)
        self._la = 0 # Token type
        try:
            self.state = 1747
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,134,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1736
                self.real_identifier()
                self.state = 1740
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_BRACKET:
                    self.state = 1737
                    self.dimension()
                    self.state = 1742
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1743
                self.real_identifier()
                self.state = 1744
                self.match(VerilogParser.EQUAL)
                self.state = 1745
                self.constant_expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_variable_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_type" ):
                listener.enterVariable_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_type" ):
                listener.exitVariable_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_type" ):
                return visitor.visitVariable_type(self)
            else:
                return visitor.visitChildren(self)




    def variable_type(self):

        localctx = VerilogParser.Variable_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 218, self.RULE_variable_type)
        self._la = 0 # Token type
        try:
            self.state = 1760
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,136,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1749
                self.variable_identifier()
                self.state = 1753
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_BRACKET:
                    self.state = 1750
                    self.dimension()
                    self.state = 1755
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1756
                self.variable_identifier()
                self.state = 1757
                self.match(VerilogParser.EQUAL)
                self.state = 1758
                self.constant_expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Drive_strengthContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def strength0(self):
            return self.getTypedRuleContext(VerilogParser.Strength0Context,0)


        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def strength1(self):
            return self.getTypedRuleContext(VerilogParser.Strength1Context,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def HIGHZ1(self):
            return self.getToken(VerilogParser.HIGHZ1, 0)

        def HIGHZ0(self):
            return self.getToken(VerilogParser.HIGHZ0, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_drive_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDrive_strength" ):
                listener.enterDrive_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDrive_strength" ):
                listener.exitDrive_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDrive_strength" ):
                return visitor.visitDrive_strength(self)
            else:
                return visitor.visitChildren(self)




    def drive_strength(self):

        localctx = VerilogParser.Drive_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 220, self.RULE_drive_strength)
        try:
            self.state = 1798
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,137,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1762
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1763
                self.strength0()
                self.state = 1764
                self.match(VerilogParser.COMMA)
                self.state = 1765
                self.strength1()
                self.state = 1766
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1768
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1769
                self.strength1()
                self.state = 1770
                self.match(VerilogParser.COMMA)
                self.state = 1771
                self.strength0()
                self.state = 1772
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1774
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1775
                self.strength0()
                self.state = 1776
                self.match(VerilogParser.COMMA)
                self.state = 1777
                self.match(VerilogParser.HIGHZ1)
                self.state = 1778
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1780
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1781
                self.strength1()
                self.state = 1782
                self.match(VerilogParser.COMMA)
                self.state = 1783
                self.match(VerilogParser.HIGHZ0)
                self.state = 1784
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1786
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1787
                self.match(VerilogParser.HIGHZ0)
                self.state = 1788
                self.match(VerilogParser.COMMA)
                self.state = 1789
                self.strength1()
                self.state = 1790
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1792
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1793
                self.match(VerilogParser.HIGHZ1)
                self.state = 1794
                self.match(VerilogParser.COMMA)
                self.state = 1795
                self.strength0()
                self.state = 1796
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Strength0Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SUPPLY0(self):
            return self.getToken(VerilogParser.SUPPLY0, 0)

        def STRONG0(self):
            return self.getToken(VerilogParser.STRONG0, 0)

        def PULL0(self):
            return self.getToken(VerilogParser.PULL0, 0)

        def WEAK0(self):
            return self.getToken(VerilogParser.WEAK0, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_strength0

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrength0" ):
                listener.enterStrength0(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrength0" ):
                listener.exitStrength0(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrength0" ):
                return visitor.visitStrength0(self)
            else:
                return visitor.visitChildren(self)




    def strength0(self):

        localctx = VerilogParser.Strength0Context(self, self._ctx, self.state)
        self.enterRule(localctx, 222, self.RULE_strength0)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1800
            _la = self._input.LA(1)
            if not(((((_la - 73)) & ~0x3f) == 0 and ((1 << (_la - 73)) & ((1 << (VerilogParser.PULL0 - 73)) | (1 << (VerilogParser.STRONG0 - 73)) | (1 << (VerilogParser.SUPPLY0 - 73)) | (1 << (VerilogParser.WEAK0 - 73)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Strength1Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SUPPLY1(self):
            return self.getToken(VerilogParser.SUPPLY1, 0)

        def STRONG1(self):
            return self.getToken(VerilogParser.STRONG1, 0)

        def PULL1(self):
            return self.getToken(VerilogParser.PULL1, 0)

        def WEAK1(self):
            return self.getToken(VerilogParser.WEAK1, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_strength1

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrength1" ):
                listener.enterStrength1(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrength1" ):
                listener.exitStrength1(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrength1" ):
                return visitor.visitStrength1(self)
            else:
                return visitor.visitChildren(self)




    def strength1(self):

        localctx = VerilogParser.Strength1Context(self, self._ctx, self.state)
        self.enterRule(localctx, 224, self.RULE_strength1)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1802
            _la = self._input.LA(1)
            if not(((((_la - 74)) & ~0x3f) == 0 and ((1 << (_la - 74)) & ((1 << (VerilogParser.PULL1 - 74)) | (1 << (VerilogParser.STRONG1 - 74)) | (1 << (VerilogParser.SUPPLY1 - 74)) | (1 << (VerilogParser.WEAK1 - 74)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Charge_strengthContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def SMALL(self):
            return self.getToken(VerilogParser.SMALL, 0)

        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def MEDIUM(self):
            return self.getToken(VerilogParser.MEDIUM, 0)

        def LARGE(self):
            return self.getToken(VerilogParser.LARGE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_charge_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCharge_strength" ):
                listener.enterCharge_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCharge_strength" ):
                listener.exitCharge_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCharge_strength" ):
                return visitor.visitCharge_strength(self)
            else:
                return visitor.visitChildren(self)




    def charge_strength(self):

        localctx = VerilogParser.Charge_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 226, self.RULE_charge_strength)
        try:
            self.state = 1813
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,138,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1804
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1805
                self.match(VerilogParser.SMALL)
                self.state = 1806
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1807
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1808
                self.match(VerilogParser.MEDIUM)
                self.state = 1809
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1810
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1811
                self.match(VerilogParser.LARGE)
                self.state = 1812
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay3Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HASH(self):
            return self.getToken(VerilogParser.HASH, 0)

        def delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Delay_valueContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def mintypmax_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Mintypmax_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_delay3

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay3" ):
                listener.enterDelay3(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay3" ):
                listener.exitDelay3(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay3" ):
                return visitor.visitDelay3(self)
            else:
                return visitor.visitChildren(self)




    def delay3(self):

        localctx = VerilogParser.Delay3Context(self, self._ctx, self.state)
        self.enterRule(localctx, 228, self.RULE_delay3)
        self._la = 0 # Token type
        try:
            self.state = 1830
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,141,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1815
                self.match(VerilogParser.HASH)
                self.state = 1816
                self.delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1817
                self.match(VerilogParser.HASH)
                self.state = 1818
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1819
                self.mintypmax_expression()
                self.state = 1826
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 1820
                    self.match(VerilogParser.COMMA)
                    self.state = 1821
                    self.mintypmax_expression()
                    self.state = 1824
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==VerilogParser.COMMA:
                        self.state = 1822
                        self.match(VerilogParser.COMMA)
                        self.state = 1823
                        self.mintypmax_expression()




                self.state = 1828
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay2Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HASH(self):
            return self.getToken(VerilogParser.HASH, 0)

        def delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Delay_valueContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def mintypmax_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Mintypmax_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_delay2

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay2" ):
                listener.enterDelay2(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay2" ):
                listener.exitDelay2(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay2" ):
                return visitor.visitDelay2(self)
            else:
                return visitor.visitChildren(self)




    def delay2(self):

        localctx = VerilogParser.Delay2Context(self, self._ctx, self.state)
        self.enterRule(localctx, 230, self.RULE_delay2)
        self._la = 0 # Token type
        try:
            self.state = 1843
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,143,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1832
                self.match(VerilogParser.HASH)
                self.state = 1833
                self.delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1834
                self.match(VerilogParser.HASH)
                self.state = 1835
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1836
                self.mintypmax_expression()
                self.state = 1839
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 1837
                    self.match(VerilogParser.COMMA)
                    self.state = 1838
                    self.mintypmax_expression()


                self.state = 1841
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def REAL_NUMBER(self):
            return self.getToken(VerilogParser.REAL_NUMBER, 0)

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_delay_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_value" ):
                listener.enterDelay_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_value" ):
                listener.exitDelay_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_value" ):
                return visitor.visitDelay_value(self)
            else:
                return visitor.visitChildren(self)




    def delay_value(self):

        localctx = VerilogParser.Delay_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 232, self.RULE_delay_value)
        try:
            self.state = 1848
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DECIMAL_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1845
                self.match(VerilogParser.DECIMAL_NUMBER)
                pass
            elif token in [VerilogParser.REAL_NUMBER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1846
                self.match(VerilogParser.REAL_NUMBER)
                pass
            elif token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1847
                self.identifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_defparam_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def defparam_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Defparam_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Defparam_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_defparam_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_defparam_assignments" ):
                listener.enterList_of_defparam_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_defparam_assignments" ):
                listener.exitList_of_defparam_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_defparam_assignments" ):
                return visitor.visitList_of_defparam_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_defparam_assignments(self):

        localctx = VerilogParser.List_of_defparam_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 234, self.RULE_list_of_defparam_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1850
            self.defparam_assignment()
            self.state = 1855
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1851
                self.match(VerilogParser.COMMA)
                self.state = 1852
                self.defparam_assignment()
                self.state = 1857
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_event_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def event_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Event_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Event_identifierContext,i)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_event_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_event_identifiers" ):
                listener.enterList_of_event_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_event_identifiers" ):
                listener.exitList_of_event_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_event_identifiers" ):
                return visitor.visitList_of_event_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_event_identifiers(self):

        localctx = VerilogParser.List_of_event_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 236, self.RULE_list_of_event_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1858
            self.event_identifier()
            self.state = 1862
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,146,self._ctx)
            while _alt!=1 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1+1:
                    self.state = 1859
                    self.dimension() 
                self.state = 1864
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,146,self._ctx)

            self.state = 1875
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1865
                self.match(VerilogParser.COMMA)
                self.state = 1866
                self.event_identifier()
                self.state = 1870
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,147,self._ctx)
                while _alt!=1 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1+1:
                        self.state = 1867
                        self.dimension() 
                    self.state = 1872
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,147,self._ctx)

                self.state = 1877
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_net_decl_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_decl_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Net_decl_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Net_decl_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_net_decl_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_net_decl_assignments" ):
                listener.enterList_of_net_decl_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_net_decl_assignments" ):
                listener.exitList_of_net_decl_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_net_decl_assignments" ):
                return visitor.visitList_of_net_decl_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_net_decl_assignments(self):

        localctx = VerilogParser.List_of_net_decl_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 238, self.RULE_list_of_net_decl_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1878
            self.net_decl_assignment()
            self.state = 1883
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1879
                self.match(VerilogParser.COMMA)
                self.state = 1880
                self.net_decl_assignment()
                self.state = 1885
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_net_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Net_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Net_identifierContext,i)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_net_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_net_identifiers" ):
                listener.enterList_of_net_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_net_identifiers" ):
                listener.exitList_of_net_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_net_identifiers" ):
                return visitor.visitList_of_net_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_net_identifiers(self):

        localctx = VerilogParser.List_of_net_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 240, self.RULE_list_of_net_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1886
            self.net_identifier()
            self.state = 1890
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,150,self._ctx)
            while _alt!=1 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1+1:
                    self.state = 1887
                    self.dimension() 
                self.state = 1892
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,150,self._ctx)

            self.state = 1903
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1893
                self.match(VerilogParser.COMMA)
                self.state = 1894
                self.net_identifier()
                self.state = 1898
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,151,self._ctx)
                while _alt!=1 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1+1:
                        self.state = 1895
                        self.dimension() 
                    self.state = 1900
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,151,self._ctx)

                self.state = 1905
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_param_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def param_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Param_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Param_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_param_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_param_assignments" ):
                listener.enterList_of_param_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_param_assignments" ):
                listener.exitList_of_param_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_param_assignments" ):
                return visitor.visitList_of_param_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_param_assignments(self):

        localctx = VerilogParser.List_of_param_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 242, self.RULE_list_of_param_assignments)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1906
            self.param_assignment()
            self.state = 1911
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,153,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1907
                    self.match(VerilogParser.COMMA)
                    self.state = 1908
                    self.param_assignment() 
                self.state = 1913
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,153,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Port_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Port_identifierContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_port_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_identifiers" ):
                listener.enterList_of_port_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_identifiers" ):
                listener.exitList_of_port_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_identifiers" ):
                return visitor.visitList_of_port_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_identifiers(self):

        localctx = VerilogParser.List_of_port_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 244, self.RULE_list_of_port_identifiers)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1914
            self.port_identifier()
            self.state = 1919
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,154,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1915
                    self.match(VerilogParser.COMMA)
                    self.state = 1916
                    self.port_identifier() 
                self.state = 1921
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,154,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_real_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def real_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Real_typeContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Real_typeContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_real_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_real_identifiers" ):
                listener.enterList_of_real_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_real_identifiers" ):
                listener.exitList_of_real_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_real_identifiers" ):
                return visitor.visitList_of_real_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_real_identifiers(self):

        localctx = VerilogParser.List_of_real_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 246, self.RULE_list_of_real_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1922
            self.real_type()
            self.state = 1927
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1923
                self.match(VerilogParser.COMMA)
                self.state = 1924
                self.real_type()
                self.state = 1929
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_specparam_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Specparam_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Specparam_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_specparam_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_specparam_assignments" ):
                listener.enterList_of_specparam_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_specparam_assignments" ):
                listener.exitList_of_specparam_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_specparam_assignments" ):
                return visitor.visitList_of_specparam_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_specparam_assignments(self):

        localctx = VerilogParser.List_of_specparam_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 248, self.RULE_list_of_specparam_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1930
            self.specparam_assignment()
            self.state = 1935
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1931
                self.match(VerilogParser.COMMA)
                self.state = 1932
                self.specparam_assignment()
                self.state = 1937
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_variable_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Variable_typeContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Variable_typeContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_variable_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_identifiers" ):
                listener.enterList_of_variable_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_identifiers" ):
                listener.exitList_of_variable_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_identifiers" ):
                return visitor.visitList_of_variable_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_identifiers(self):

        localctx = VerilogParser.List_of_variable_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 250, self.RULE_list_of_variable_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1938
            self.variable_type()
            self.state = 1943
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 1939
                self.match(VerilogParser.COMMA)
                self.state = 1940
                self.variable_type()
                self.state = 1945
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_variable_port_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Port_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Port_identifierContext,i)


        def EQUAL(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.EQUAL)
            else:
                return self.getToken(VerilogParser.EQUAL, i)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_variable_port_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_port_identifiers" ):
                listener.enterList_of_variable_port_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_port_identifiers" ):
                listener.exitList_of_variable_port_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_port_identifiers" ):
                return visitor.visitList_of_variable_port_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_port_identifiers(self):

        localctx = VerilogParser.List_of_variable_port_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 252, self.RULE_list_of_variable_port_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1946
            self.port_identifier()
            self.state = 1949
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.EQUAL:
                self.state = 1947
                self.match(VerilogParser.EQUAL)
                self.state = 1948
                self.constant_expression(0)


            self.state = 1959
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,160,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1951
                    self.match(VerilogParser.COMMA)
                    self.state = 1952
                    self.port_identifier()
                    self.state = 1955
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==VerilogParser.EQUAL:
                        self.state = 1953
                        self.match(VerilogParser.EQUAL)
                        self.state = 1954
                        self.constant_expression(0)

             
                self.state = 1961
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,160,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Defparam_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_parameter_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_parameter_identifierContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_defparam_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefparam_assignment" ):
                listener.enterDefparam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefparam_assignment" ):
                listener.exitDefparam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefparam_assignment" ):
                return visitor.visitDefparam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def defparam_assignment(self):

        localctx = VerilogParser.Defparam_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 254, self.RULE_defparam_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1962
            self.hierarchical_parameter_identifier()
            self.state = 1963
            self.match(VerilogParser.EQUAL)
            self.state = 1964
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_decl_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Net_identifierContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_decl_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_decl_assignment" ):
                listener.enterNet_decl_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_decl_assignment" ):
                listener.exitNet_decl_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_decl_assignment" ):
                return visitor.visitNet_decl_assignment(self)
            else:
                return visitor.visitChildren(self)




    def net_decl_assignment(self):

        localctx = VerilogParser.Net_decl_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 256, self.RULE_net_decl_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1966
            self.net_identifier()
            self.state = 1967
            self.match(VerilogParser.EQUAL)
            self.state = 1968
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Param_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_identifierContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_param_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParam_assignment" ):
                listener.enterParam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParam_assignment" ):
                listener.exitParam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParam_assignment" ):
                return visitor.visitParam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def param_assignment(self):

        localctx = VerilogParser.Param_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 258, self.RULE_param_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1970
            self.parameter_identifier()
            self.state = 1971
            self.match(VerilogParser.EQUAL)
            self.state = 1972
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specparam_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Specparam_identifierContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def pulse_control_specparam(self):
            return self.getTypedRuleContext(VerilogParser.Pulse_control_specparamContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specparam_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_assignment" ):
                listener.enterSpecparam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_assignment" ):
                listener.exitSpecparam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_assignment" ):
                return visitor.visitSpecparam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def specparam_assignment(self):

        localctx = VerilogParser.Specparam_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 260, self.RULE_specparam_assignment)
        try:
            self.state = 1979
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1974
                self.specparam_identifier()
                self.state = 1975
                self.match(VerilogParser.EQUAL)
                self.state = 1976
                self.constant_mintypmax_expression()
                pass
            elif token in [VerilogParser.PATHPULSE_DOLLAR]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1978
                self.pulse_control_specparam()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pulse_control_specparamContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PATHPULSE_DOLLAR(self):
            return self.getToken(VerilogParser.PATHPULSE_DOLLAR, 0)

        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def reject_limit_value(self):
            return self.getTypedRuleContext(VerilogParser.Reject_limit_valueContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def error_limit_value(self):
            return self.getTypedRuleContext(VerilogParser.Error_limit_valueContext,0)


        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,0)


        def DOT(self):
            return self.getToken(VerilogParser.DOT, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pulse_control_specparam

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulse_control_specparam" ):
                listener.enterPulse_control_specparam(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulse_control_specparam" ):
                listener.exitPulse_control_specparam(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulse_control_specparam" ):
                return visitor.visitPulse_control_specparam(self)
            else:
                return visitor.visitChildren(self)




    def pulse_control_specparam(self):

        localctx = VerilogParser.Pulse_control_specparamContext(self, self._ctx, self.state)
        self.enterRule(localctx, 262, self.RULE_pulse_control_specparam)
        self._la = 0 # Token type
        try:
            self.state = 2004
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,164,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1981
                self.match(VerilogParser.PATHPULSE_DOLLAR)
                self.state = 1982
                self.match(VerilogParser.EQUAL)
                self.state = 1983
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1984
                self.reject_limit_value()
                self.state = 1987
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 1985
                    self.match(VerilogParser.COMMA)
                    self.state = 1986
                    self.error_limit_value()


                self.state = 1989
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1991
                self.match(VerilogParser.PATHPULSE_DOLLAR)
                self.state = 1992
                self.specify_input_terminal_descriptor()
                self.state = 1993
                self.match(VerilogParser.DOT)
                self.state = 1994
                self.specify_output_terminal_descriptor()
                self.state = 1995
                self.match(VerilogParser.EQUAL)
                self.state = 1996
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 1997
                self.reject_limit_value()
                self.state = 2000
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COMMA:
                    self.state = 1998
                    self.match(VerilogParser.COMMA)
                    self.state = 1999
                    self.error_limit_value()


                self.state = 2002
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Error_limit_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def limit_value(self):
            return self.getTypedRuleContext(VerilogParser.Limit_valueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_error_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterError_limit_value" ):
                listener.enterError_limit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitError_limit_value" ):
                listener.exitError_limit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitError_limit_value" ):
                return visitor.visitError_limit_value(self)
            else:
                return visitor.visitChildren(self)




    def error_limit_value(self):

        localctx = VerilogParser.Error_limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 264, self.RULE_error_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2006
            self.limit_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Reject_limit_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def limit_value(self):
            return self.getTypedRuleContext(VerilogParser.Limit_valueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_reject_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReject_limit_value" ):
                listener.enterReject_limit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReject_limit_value" ):
                listener.exitReject_limit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReject_limit_value" ):
                return visitor.visitReject_limit_value(self)
            else:
                return visitor.visitChildren(self)




    def reject_limit_value(self):

        localctx = VerilogParser.Reject_limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 266, self.RULE_reject_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2008
            self.limit_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Limit_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLimit_value" ):
                listener.enterLimit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLimit_value" ):
                listener.exitLimit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLimit_value" ):
                return visitor.visitLimit_value(self)
            else:
                return visitor.visitChildren(self)




    def limit_value(self):

        localctx = VerilogParser.Limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 268, self.RULE_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2010
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class DimensionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_BRACKET(self):
            return self.getToken(VerilogParser.LEFT_BRACKET, 0)

        def dimension_constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Dimension_constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Dimension_constant_expressionContext,i)


        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def RIGHT_BRACKET(self):
            return self.getToken(VerilogParser.RIGHT_BRACKET, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDimension" ):
                listener.enterDimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDimension" ):
                listener.exitDimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDimension" ):
                return visitor.visitDimension(self)
            else:
                return visitor.visitChildren(self)




    def dimension(self):

        localctx = VerilogParser.DimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 270, self.RULE_dimension)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2012
            self.match(VerilogParser.LEFT_BRACKET)
            self.state = 2013
            self.dimension_constant_expression()
            self.state = 2014
            self.match(VerilogParser.COLON)
            self.state = 2015
            self.dimension_constant_expression()
            self.state = 2016
            self.match(VerilogParser.RIGHT_BRACKET)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Range_Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_BRACKET(self):
            return self.getToken(VerilogParser.LEFT_BRACKET, 0)

        def msb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Msb_constant_expressionContext,0)


        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def lsb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Lsb_constant_expressionContext,0)


        def RIGHT_BRACKET(self):
            return self.getToken(VerilogParser.RIGHT_BRACKET, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_range_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRange_" ):
                listener.enterRange_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRange_" ):
                listener.exitRange_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRange_" ):
                return visitor.visitRange_(self)
            else:
                return visitor.visitChildren(self)




    def range_(self):

        localctx = VerilogParser.Range_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 272, self.RULE_range_)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2018
            self.match(VerilogParser.LEFT_BRACKET)
            self.state = 2019
            self.msb_constant_expression()
            self.state = 2020
            self.match(VerilogParser.COLON)
            self.state = 2021
            self.lsb_constant_expression()
            self.state = 2022
            self.match(VerilogParser.RIGHT_BRACKET)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FUNCTION(self):
            return self.getToken(VerilogParser.FUNCTION, 0)

        def function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Function_identifierContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def function_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Function_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Function_item_declarationContext,i)


        def function_statement(self):
            return self.getTypedRuleContext(VerilogParser.Function_statementContext,0)


        def ENDFUNCTION(self):
            return self.getToken(VerilogParser.ENDFUNCTION, 0)

        def AUTOMATIC(self):
            return self.getToken(VerilogParser.AUTOMATIC, 0)

        def function_range_or_type(self):
            return self.getTypedRuleContext(VerilogParser.Function_range_or_typeContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def function_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Function_port_listContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_function_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_declaration" ):
                listener.enterFunction_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_declaration" ):
                listener.exitFunction_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_declaration" ):
                return visitor.visitFunction_declaration(self)
            else:
                return visitor.visitChildren(self)




    def function_declaration(self):

        localctx = VerilogParser.Function_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 274, self.RULE_function_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2064
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,171,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2024
                self.match(VerilogParser.FUNCTION)
                self.state = 2026
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.AUTOMATIC:
                    self.state = 2025
                    self.match(VerilogParser.AUTOMATIC)


                self.state = 2029
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 50)) & ~0x3f) == 0 and ((1 << (_la - 50)) & ((1 << (VerilogParser.INTEGER - 50)) | (1 << (VerilogParser.REAL - 50)) | (1 << (VerilogParser.REALTIME - 50)) | (1 << (VerilogParser.SIGNED - 50)) | (1 << (VerilogParser.TIME - 50)))) != 0) or _la==VerilogParser.LEFT_BRACKET:
                    self.state = 2028
                    self.function_range_or_type()


                self.state = 2031
                self.function_identifier()
                self.state = 2032
                self.match(VerilogParser.SEMICOLON)
                self.state = 2033
                self.function_item_declaration()
                self.state = 2037
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,167,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2034
                        self.function_item_declaration() 
                    self.state = 2039
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,167,self._ctx)

                self.state = 2040
                self.function_statement()
                self.state = 2041
                self.match(VerilogParser.ENDFUNCTION)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2043
                self.match(VerilogParser.FUNCTION)
                self.state = 2045
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.AUTOMATIC:
                    self.state = 2044
                    self.match(VerilogParser.AUTOMATIC)


                self.state = 2048
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 50)) & ~0x3f) == 0 and ((1 << (_la - 50)) & ((1 << (VerilogParser.INTEGER - 50)) | (1 << (VerilogParser.REAL - 50)) | (1 << (VerilogParser.REALTIME - 50)) | (1 << (VerilogParser.SIGNED - 50)) | (1 << (VerilogParser.TIME - 50)))) != 0) or _la==VerilogParser.LEFT_BRACKET:
                    self.state = 2047
                    self.function_range_or_type()


                self.state = 2050
                self.function_identifier()
                self.state = 2051
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 2052
                self.function_port_list()
                self.state = 2053
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 2054
                self.match(VerilogParser.SEMICOLON)
                self.state = 2058
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,170,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2055
                        self.block_item_declaration() 
                    self.state = 2060
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,170,self._ctx)

                self.state = 2061
                self.function_statement()
                self.state = 2062
                self.match(VerilogParser.ENDFUNCTION)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,0)


        def tf_input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_input_declarationContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_function_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_item_declaration" ):
                listener.enterFunction_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_item_declaration" ):
                listener.exitFunction_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_item_declaration" ):
                return visitor.visitFunction_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def function_item_declaration(self):

        localctx = VerilogParser.Function_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 276, self.RULE_function_item_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2076
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,173,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2066
                self.block_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2070
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2067
                    self.attribute_instance()
                    self.state = 2072
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2073
                self.tf_input_declaration()
                self.state = 2074
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def tf_input_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Tf_input_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Tf_input_declarationContext,i)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_function_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_port_list" ):
                listener.enterFunction_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_port_list" ):
                listener.exitFunction_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_port_list" ):
                return visitor.visitFunction_port_list(self)
            else:
                return visitor.visitChildren(self)




    def function_port_list(self):

        localctx = VerilogParser.Function_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 278, self.RULE_function_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2081
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 2078
                self.attribute_instance()
                self.state = 2083
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2084
            self.tf_input_declaration()
            self.state = 2095
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 2085
                self.match(VerilogParser.COMMA)
                self.state = 2089
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2086
                    self.attribute_instance()
                    self.state = 2091
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2092
                self.tf_input_declaration()
                self.state = 2097
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_range_or_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_function_range_or_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_range_or_type" ):
                listener.enterFunction_range_or_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_range_or_type" ):
                listener.exitFunction_range_or_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_range_or_type" ):
                return visitor.visitFunction_range_or_type(self)
            else:
                return visitor.visitChildren(self)




    def function_range_or_type(self):

        localctx = VerilogParser.Function_range_or_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 280, self.RULE_function_range_or_type)
        self._la = 0 # Token type
        try:
            self.state = 2106
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.SIGNED, VerilogParser.LEFT_BRACKET]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2099
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 2098
                    self.match(VerilogParser.SIGNED)


                self.state = 2101
                self.range_()
                pass
            elif token in [VerilogParser.INTEGER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2102
                self.match(VerilogParser.INTEGER)
                pass
            elif token in [VerilogParser.REAL]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2103
                self.match(VerilogParser.REAL)
                pass
            elif token in [VerilogParser.REALTIME]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2104
                self.match(VerilogParser.REALTIME)
                pass
            elif token in [VerilogParser.TIME]:
                self.enterOuterAlt(localctx, 5)
                self.state = 2105
                self.match(VerilogParser.TIME)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TASK(self):
            return self.getToken(VerilogParser.TASK, 0)

        def task_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Task_identifierContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,0)


        def ENDTASK(self):
            return self.getToken(VerilogParser.ENDTASK, 0)

        def AUTOMATIC(self):
            return self.getToken(VerilogParser.AUTOMATIC, 0)

        def task_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Task_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Task_item_declarationContext,i)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def task_port_list(self):
            return self.getTypedRuleContext(VerilogParser.Task_port_listContext,0)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_declaration" ):
                listener.enterTask_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_declaration" ):
                listener.exitTask_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_declaration" ):
                return visitor.visitTask_declaration(self)
            else:
                return visitor.visitChildren(self)




    def task_declaration(self):

        localctx = VerilogParser.Task_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 282, self.RULE_task_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2143
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,184,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2108
                self.match(VerilogParser.TASK)
                self.state = 2110
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.AUTOMATIC:
                    self.state = 2109
                    self.match(VerilogParser.AUTOMATIC)


                self.state = 2112
                self.task_identifier()
                self.state = 2113
                self.match(VerilogParser.SEMICOLON)
                self.state = 2117
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,180,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2114
                        self.task_item_declaration() 
                    self.state = 2119
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,180,self._ctx)

                self.state = 2120
                self.statement_or_null()
                self.state = 2121
                self.match(VerilogParser.ENDTASK)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2123
                self.match(VerilogParser.TASK)
                self.state = 2125
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.AUTOMATIC:
                    self.state = 2124
                    self.match(VerilogParser.AUTOMATIC)


                self.state = 2127
                self.task_identifier()
                self.state = 2128
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 2130
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 47)) & ~0x3f) == 0 and ((1 << (_la - 47)) & ((1 << (VerilogParser.INOUT - 47)) | (1 << (VerilogParser.INPUT - 47)) | (1 << (VerilogParser.OUTPUT - 47)))) != 0) or _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2129
                    self.task_port_list()


                self.state = 2132
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 2133
                self.match(VerilogParser.SEMICOLON)
                self.state = 2137
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,183,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2134
                        self.block_item_declaration() 
                    self.state = 2139
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,183,self._ctx)

                self.state = 2140
                self.statement_or_null()
                self.state = 2141
                self.match(VerilogParser.ENDTASK)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,0)


        def tf_input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_input_declarationContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def tf_output_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_output_declarationContext,0)


        def tf_inout_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_inout_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_item_declaration" ):
                listener.enterTask_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_item_declaration" ):
                listener.exitTask_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_item_declaration" ):
                return visitor.visitTask_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def task_item_declaration(self):

        localctx = VerilogParser.Task_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 284, self.RULE_task_item_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2173
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,188,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2145
                self.block_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2149
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2146
                    self.attribute_instance()
                    self.state = 2151
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2152
                self.tf_input_declaration()
                self.state = 2153
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2158
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2155
                    self.attribute_instance()
                    self.state = 2160
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2161
                self.tf_output_declaration()
                self.state = 2162
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2167
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2164
                    self.attribute_instance()
                    self.state = 2169
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2170
                self.tf_inout_declaration()
                self.state = 2171
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Task_port_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Task_port_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_task_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_port_list" ):
                listener.enterTask_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_port_list" ):
                listener.exitTask_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_port_list" ):
                return visitor.visitTask_port_list(self)
            else:
                return visitor.visitChildren(self)




    def task_port_list(self):

        localctx = VerilogParser.Task_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 286, self.RULE_task_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2175
            self.task_port_item()
            self.state = 2180
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 2176
                self.match(VerilogParser.COMMA)
                self.state = 2177
                self.task_port_item()
                self.state = 2182
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_port_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def tf_input_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_input_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def tf_output_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_output_declarationContext,0)


        def tf_inout_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Tf_inout_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_port_item" ):
                listener.enterTask_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_port_item" ):
                listener.exitTask_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_port_item" ):
                return visitor.visitTask_port_item(self)
            else:
                return visitor.visitChildren(self)




    def task_port_item(self):

        localctx = VerilogParser.Task_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 288, self.RULE_task_port_item)
        self._la = 0 # Token type
        try:
            self.state = 2204
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,193,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2186
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2183
                    self.attribute_instance()
                    self.state = 2188
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2189
                self.tf_input_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2193
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2190
                    self.attribute_instance()
                    self.state = 2195
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2196
                self.tf_output_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2200
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2197
                    self.attribute_instance()
                    self.state = 2202
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2203
                self.tf_inout_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_input_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INPUT(self):
            return self.getToken(VerilogParser.INPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def task_port_type(self):
            return self.getTypedRuleContext(VerilogParser.Task_port_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tf_input_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_input_declaration" ):
                listener.enterTf_input_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_input_declaration" ):
                listener.exitTf_input_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_input_declaration" ):
                return visitor.visitTf_input_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_input_declaration(self):

        localctx = VerilogParser.Tf_input_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 290, self.RULE_tf_input_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2221
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,197,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2206
                self.match(VerilogParser.INPUT)
                self.state = 2208
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.REG:
                    self.state = 2207
                    self.match(VerilogParser.REG)


                self.state = 2211
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 2210
                    self.match(VerilogParser.SIGNED)


                self.state = 2214
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 2213
                    self.range_()


                self.state = 2216
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2217
                self.match(VerilogParser.INPUT)
                self.state = 2218
                self.task_port_type()
                self.state = 2219
                self.list_of_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_output_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def OUTPUT(self):
            return self.getToken(VerilogParser.OUTPUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def task_port_type(self):
            return self.getTypedRuleContext(VerilogParser.Task_port_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tf_output_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_output_declaration" ):
                listener.enterTf_output_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_output_declaration" ):
                listener.exitTf_output_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_output_declaration" ):
                return visitor.visitTf_output_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_output_declaration(self):

        localctx = VerilogParser.Tf_output_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 292, self.RULE_tf_output_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2238
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,201,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2223
                self.match(VerilogParser.OUTPUT)
                self.state = 2225
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.REG:
                    self.state = 2224
                    self.match(VerilogParser.REG)


                self.state = 2228
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 2227
                    self.match(VerilogParser.SIGNED)


                self.state = 2231
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 2230
                    self.range_()


                self.state = 2233
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2234
                self.match(VerilogParser.OUTPUT)
                self.state = 2235
                self.task_port_type()
                self.state = 2236
                self.list_of_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_inout_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INOUT(self):
            return self.getToken(VerilogParser.INOUT, 0)

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_identifiersContext,0)


        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def task_port_type(self):
            return self.getTypedRuleContext(VerilogParser.Task_port_typeContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tf_inout_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_inout_declaration" ):
                listener.enterTf_inout_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_inout_declaration" ):
                listener.exitTf_inout_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_inout_declaration" ):
                return visitor.visitTf_inout_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_inout_declaration(self):

        localctx = VerilogParser.Tf_inout_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 294, self.RULE_tf_inout_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2255
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,205,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2240
                self.match(VerilogParser.INOUT)
                self.state = 2242
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.REG:
                    self.state = 2241
                    self.match(VerilogParser.REG)


                self.state = 2245
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 2244
                    self.match(VerilogParser.SIGNED)


                self.state = 2248
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 2247
                    self.range_()


                self.state = 2250
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2251
                self.match(VerilogParser.INOUT)
                self.state = 2252
                self.task_port_type()
                self.state = 2253
                self.list_of_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_port_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_task_port_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_port_type" ):
                listener.enterTask_port_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_port_type" ):
                listener.exitTask_port_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_port_type" ):
                return visitor.visitTask_port_type(self)
            else:
                return visitor.visitChildren(self)




    def task_port_type(self):

        localctx = VerilogParser.Task_port_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 296, self.RULE_task_port_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2257
            _la = self._input.LA(1)
            if not(((((_la - 50)) & ~0x3f) == 0 and ((1 << (_la - 50)) & ((1 << (VerilogParser.INTEGER - 50)) | (1 << (VerilogParser.REAL - 50)) | (1 << (VerilogParser.REALTIME - 50)) | (1 << (VerilogParser.TIME - 50)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def REG(self):
            return self.getToken(VerilogParser.REG, 0)

        def list_of_block_variable_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_block_variable_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def SIGNED(self):
            return self.getToken(VerilogParser.SIGNED, 0)

        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def INTEGER(self):
            return self.getToken(VerilogParser.INTEGER, 0)

        def TIME(self):
            return self.getToken(VerilogParser.TIME, 0)

        def REAL(self):
            return self.getToken(VerilogParser.REAL, 0)

        def list_of_block_real_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_block_real_identifiersContext,0)


        def REALTIME(self):
            return self.getToken(VerilogParser.REALTIME, 0)

        def event_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Event_declarationContext,0)


        def local_parameter_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Local_parameter_declarationContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_item_declaration" ):
                listener.enterBlock_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_item_declaration" ):
                listener.exitBlock_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_item_declaration" ):
                return visitor.visitBlock_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def block_item_declaration(self):

        localctx = VerilogParser.Block_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 298, self.RULE_block_item_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2340
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,216,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2262
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2259
                    self.attribute_instance()
                    self.state = 2264
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2265
                self.match(VerilogParser.REG)
                self.state = 2267
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.SIGNED:
                    self.state = 2266
                    self.match(VerilogParser.SIGNED)


                self.state = 2270
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 2269
                    self.range_()


                self.state = 2272
                self.list_of_block_variable_identifiers()
                self.state = 2273
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2278
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2275
                    self.attribute_instance()
                    self.state = 2280
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2281
                self.match(VerilogParser.INTEGER)
                self.state = 2282
                self.list_of_block_variable_identifiers()
                self.state = 2283
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2288
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2285
                    self.attribute_instance()
                    self.state = 2290
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2291
                self.match(VerilogParser.TIME)
                self.state = 2292
                self.list_of_block_variable_identifiers()
                self.state = 2293
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2298
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2295
                    self.attribute_instance()
                    self.state = 2300
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2301
                self.match(VerilogParser.REAL)
                self.state = 2302
                self.list_of_block_real_identifiers()
                self.state = 2303
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2308
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2305
                    self.attribute_instance()
                    self.state = 2310
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2311
                self.match(VerilogParser.REALTIME)
                self.state = 2312
                self.list_of_block_real_identifiers()
                self.state = 2313
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2318
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2315
                    self.attribute_instance()
                    self.state = 2320
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2321
                self.event_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2325
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2322
                    self.attribute_instance()
                    self.state = 2327
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2328
                self.local_parameter_declaration()
                self.state = 2329
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2334
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2331
                    self.attribute_instance()
                    self.state = 2336
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2337
                self.parameter_declaration()
                self.state = 2338
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_block_variable_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_variable_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_variable_typeContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_variable_typeContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_block_variable_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_block_variable_identifiers" ):
                listener.enterList_of_block_variable_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_block_variable_identifiers" ):
                listener.exitList_of_block_variable_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_block_variable_identifiers" ):
                return visitor.visitList_of_block_variable_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_block_variable_identifiers(self):

        localctx = VerilogParser.List_of_block_variable_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 300, self.RULE_list_of_block_variable_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2342
            self.block_variable_type()
            self.state = 2347
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 2343
                self.match(VerilogParser.COMMA)
                self.state = 2344
                self.block_variable_type()
                self.state = 2349
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_block_real_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_real_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_real_typeContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_real_typeContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_block_real_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_block_real_identifiers" ):
                listener.enterList_of_block_real_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_block_real_identifiers" ):
                listener.exitList_of_block_real_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_block_real_identifiers" ):
                return visitor.visitList_of_block_real_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_block_real_identifiers(self):

        localctx = VerilogParser.List_of_block_real_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 302, self.RULE_list_of_block_real_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2350
            self.block_real_type()
            self.state = 2355
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 2351
                self.match(VerilogParser.COMMA)
                self.state = 2352
                self.block_real_type()
                self.state = 2357
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_variable_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Variable_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_variable_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_variable_type" ):
                listener.enterBlock_variable_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_variable_type" ):
                listener.exitBlock_variable_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_variable_type" ):
                return visitor.visitBlock_variable_type(self)
            else:
                return visitor.visitChildren(self)




    def block_variable_type(self):

        localctx = VerilogParser.Block_variable_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 304, self.RULE_block_variable_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2358
            self.variable_identifier()
            self.state = 2362
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LEFT_BRACKET:
                self.state = 2359
                self.dimension()
                self.state = 2364
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_real_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def real_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Real_identifierContext,0)


        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.DimensionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.DimensionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_real_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_real_type" ):
                listener.enterBlock_real_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_real_type" ):
                listener.exitBlock_real_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_real_type" ):
                return visitor.visitBlock_real_type(self)
            else:
                return visitor.visitChildren(self)




    def block_real_type(self):

        localctx = VerilogParser.Block_real_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 306, self.RULE_block_real_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2365
            self.real_identifier()
            self.state = 2369
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LEFT_BRACKET:
                self.state = 2366
                self.dimension()
                self.state = 2371
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Gate_instantiationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cmos_switchtype(self):
            return self.getTypedRuleContext(VerilogParser.Cmos_switchtypeContext,0)


        def cmos_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Cmos_switch_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Cmos_switch_instanceContext,i)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def delay3(self):
            return self.getTypedRuleContext(VerilogParser.Delay3Context,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def enable_gatetype(self):
            return self.getTypedRuleContext(VerilogParser.Enable_gatetypeContext,0)


        def enable_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Enable_gate_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Enable_gate_instanceContext,i)


        def drive_strength(self):
            return self.getTypedRuleContext(VerilogParser.Drive_strengthContext,0)


        def mos_switchtype(self):
            return self.getTypedRuleContext(VerilogParser.Mos_switchtypeContext,0)


        def mos_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Mos_switch_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Mos_switch_instanceContext,i)


        def n_input_gatetype(self):
            return self.getTypedRuleContext(VerilogParser.N_input_gatetypeContext,0)


        def n_input_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.N_input_gate_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.N_input_gate_instanceContext,i)


        def delay2(self):
            return self.getTypedRuleContext(VerilogParser.Delay2Context,0)


        def n_output_gatetype(self):
            return self.getTypedRuleContext(VerilogParser.N_output_gatetypeContext,0)


        def n_output_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.N_output_gate_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.N_output_gate_instanceContext,i)


        def pass_en_switchtype(self):
            return self.getTypedRuleContext(VerilogParser.Pass_en_switchtypeContext,0)


        def pass_enable_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Pass_enable_switch_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Pass_enable_switch_instanceContext,i)


        def pass_switchtype(self):
            return self.getTypedRuleContext(VerilogParser.Pass_switchtypeContext,0)


        def pass_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Pass_switch_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Pass_switch_instanceContext,i)


        def PULLDOWN(self):
            return self.getToken(VerilogParser.PULLDOWN, 0)

        def pull_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Pull_gate_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Pull_gate_instanceContext,i)


        def pulldown_strength(self):
            return self.getTypedRuleContext(VerilogParser.Pulldown_strengthContext,0)


        def PULLUP(self):
            return self.getToken(VerilogParser.PULLUP, 0)

        def pullup_strength(self):
            return self.getTypedRuleContext(VerilogParser.Pullup_strengthContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_gate_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGate_instantiation" ):
                listener.enterGate_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGate_instantiation" ):
                listener.exitGate_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGate_instantiation" ):
                return visitor.visitGate_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def gate_instantiation(self):

        localctx = VerilogParser.Gate_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 308, self.RULE_gate_instantiation)
        self._la = 0 # Token type
        try:
            self.state = 2504
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.CMOS, VerilogParser.RCMOS]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2372
                self.cmos_switchtype()
                self.state = 2374
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 2373
                    self.delay3()


                self.state = 2376
                self.cmos_switch_instance()
                self.state = 2381
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2377
                    self.match(VerilogParser.COMMA)
                    self.state = 2378
                    self.cmos_switch_instance()
                    self.state = 2383
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2384
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.BUFIF0, VerilogParser.BUFIF1, VerilogParser.NOTIF0, VerilogParser.NOTIF1]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2386
                self.enable_gatetype()
                self.state = 2388
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,223,self._ctx)
                if la_ == 1:
                    self.state = 2387
                    self.drive_strength()


                self.state = 2391
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 2390
                    self.delay3()


                self.state = 2393
                self.enable_gate_instance()
                self.state = 2398
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2394
                    self.match(VerilogParser.COMMA)
                    self.state = 2395
                    self.enable_gate_instance()
                    self.state = 2400
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2401
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.NMOS, VerilogParser.PMOS, VerilogParser.RNMOS, VerilogParser.RPMOS]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2403
                self.mos_switchtype()
                self.state = 2405
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 2404
                    self.delay3()


                self.state = 2407
                self.mos_switch_instance()
                self.state = 2412
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2408
                    self.match(VerilogParser.COMMA)
                    self.state = 2409
                    self.mos_switch_instance()
                    self.state = 2414
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2415
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.AND, VerilogParser.NAND, VerilogParser.NOR, VerilogParser.OR, VerilogParser.XNOR, VerilogParser.XOR]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2417
                self.n_input_gatetype()
                self.state = 2419
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,228,self._ctx)
                if la_ == 1:
                    self.state = 2418
                    self.drive_strength()


                self.state = 2422
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 2421
                    self.delay2()


                self.state = 2424
                self.n_input_gate_instance()
                self.state = 2429
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2425
                    self.match(VerilogParser.COMMA)
                    self.state = 2426
                    self.n_input_gate_instance()
                    self.state = 2431
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2432
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.BUF, VerilogParser.NOT]:
                self.enterOuterAlt(localctx, 5)
                self.state = 2434
                self.n_output_gatetype()
                self.state = 2436
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,231,self._ctx)
                if la_ == 1:
                    self.state = 2435
                    self.drive_strength()


                self.state = 2439
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 2438
                    self.delay2()


                self.state = 2441
                self.n_output_gate_instance()
                self.state = 2446
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2442
                    self.match(VerilogParser.COMMA)
                    self.state = 2443
                    self.n_output_gate_instance()
                    self.state = 2448
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2449
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.RTRANIF0, VerilogParser.RTRANIF1, VerilogParser.TRANIF0, VerilogParser.TRANIF1]:
                self.enterOuterAlt(localctx, 6)
                self.state = 2451
                self.pass_en_switchtype()
                self.state = 2453
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.HASH:
                    self.state = 2452
                    self.delay2()


                self.state = 2455
                self.pass_enable_switch_instance()
                self.state = 2460
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2456
                    self.match(VerilogParser.COMMA)
                    self.state = 2457
                    self.pass_enable_switch_instance()
                    self.state = 2462
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2463
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.RTRAN, VerilogParser.TRAN]:
                self.enterOuterAlt(localctx, 7)
                self.state = 2465
                self.pass_switchtype()
                self.state = 2466
                self.pass_switch_instance()
                self.state = 2471
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2467
                    self.match(VerilogParser.COMMA)
                    self.state = 2468
                    self.pass_switch_instance()
                    self.state = 2473
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2474
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.PULLDOWN]:
                self.enterOuterAlt(localctx, 8)
                self.state = 2476
                self.match(VerilogParser.PULLDOWN)
                self.state = 2478
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,237,self._ctx)
                if la_ == 1:
                    self.state = 2477
                    self.pulldown_strength()


                self.state = 2480
                self.pull_gate_instance()
                self.state = 2485
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2481
                    self.match(VerilogParser.COMMA)
                    self.state = 2482
                    self.pull_gate_instance()
                    self.state = 2487
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2488
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.PULLUP]:
                self.enterOuterAlt(localctx, 9)
                self.state = 2490
                self.match(VerilogParser.PULLUP)
                self.state = 2492
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,239,self._ctx)
                if la_ == 1:
                    self.state = 2491
                    self.pullup_strength()


                self.state = 2494
                self.pull_gate_instance()
                self.state = 2499
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2495
                    self.match(VerilogParser.COMMA)
                    self.state = 2496
                    self.pull_gate_instance()
                    self.state = 2501
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2502
                self.match(VerilogParser.SEMICOLON)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cmos_switch_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def input_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Input_terminalContext,0)


        def ncontrol_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Ncontrol_terminalContext,0)


        def pcontrol_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Pcontrol_terminalContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_cmos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switch_instance" ):
                listener.enterCmos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switch_instance" ):
                listener.exitCmos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switch_instance" ):
                return visitor.visitCmos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switch_instance(self):

        localctx = VerilogParser.Cmos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 310, self.RULE_cmos_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2507
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2506
                self.name_of_gate_instance()


            self.state = 2509
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2510
            self.output_terminal()
            self.state = 2511
            self.match(VerilogParser.COMMA)
            self.state = 2512
            self.input_terminal()
            self.state = 2513
            self.match(VerilogParser.COMMA)
            self.state = 2514
            self.ncontrol_terminal()
            self.state = 2515
            self.match(VerilogParser.COMMA)
            self.state = 2516
            self.pcontrol_terminal()
            self.state = 2517
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def input_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Input_terminalContext,0)


        def enable_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Enable_terminalContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_enable_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gate_instance" ):
                listener.enterEnable_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gate_instance" ):
                listener.exitEnable_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gate_instance" ):
                return visitor.visitEnable_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def enable_gate_instance(self):

        localctx = VerilogParser.Enable_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 312, self.RULE_enable_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2520
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2519
                self.name_of_gate_instance()


            self.state = 2522
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2523
            self.output_terminal()
            self.state = 2524
            self.match(VerilogParser.COMMA)
            self.state = 2525
            self.input_terminal()
            self.state = 2526
            self.match(VerilogParser.COMMA)
            self.state = 2527
            self.enable_terminal()
            self.state = 2528
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mos_switch_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def input_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Input_terminalContext,0)


        def enable_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Enable_terminalContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_mos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switch_instance" ):
                listener.enterMos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switch_instance" ):
                listener.exitMos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switch_instance" ):
                return visitor.visitMos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def mos_switch_instance(self):

        localctx = VerilogParser.Mos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 314, self.RULE_mos_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2531
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2530
                self.name_of_gate_instance()


            self.state = 2533
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2534
            self.output_terminal()
            self.state = 2535
            self.match(VerilogParser.COMMA)
            self.state = 2536
            self.input_terminal()
            self.state = 2537
            self.match(VerilogParser.COMMA)
            self.state = 2538
            self.enable_terminal()
            self.state = 2539
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_input_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def input_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Input_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Input_terminalContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_n_input_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gate_instance" ):
                listener.enterN_input_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gate_instance" ):
                listener.exitN_input_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gate_instance" ):
                return visitor.visitN_input_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gate_instance(self):

        localctx = VerilogParser.N_input_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 316, self.RULE_n_input_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2542
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2541
                self.name_of_gate_instance()


            self.state = 2544
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2545
            self.output_terminal()
            self.state = 2546
            self.match(VerilogParser.COMMA)
            self.state = 2547
            self.input_terminal()
            self.state = 2552
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 2548
                self.match(VerilogParser.COMMA)
                self.state = 2549
                self.input_terminal()
                self.state = 2554
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2555
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_output_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def output_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Output_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Output_terminalContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def input_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Input_terminalContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_n_output_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gate_instance" ):
                listener.enterN_output_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gate_instance" ):
                listener.exitN_output_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gate_instance" ):
                return visitor.visitN_output_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gate_instance(self):

        localctx = VerilogParser.N_output_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 318, self.RULE_n_output_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2558
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2557
                self.name_of_gate_instance()


            self.state = 2560
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2561
            self.output_terminal()
            self.state = 2566
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,248,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 2562
                    self.match(VerilogParser.COMMA)
                    self.state = 2563
                    self.output_terminal() 
                self.state = 2568
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,248,self._ctx)

            self.state = 2569
            self.match(VerilogParser.COMMA)
            self.state = 2570
            self.input_terminal()
            self.state = 2571
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_switch_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def inout_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Inout_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Inout_terminalContext,i)


        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pass_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switch_instance" ):
                listener.enterPass_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switch_instance" ):
                listener.exitPass_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switch_instance" ):
                return visitor.visitPass_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def pass_switch_instance(self):

        localctx = VerilogParser.Pass_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 320, self.RULE_pass_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2574
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2573
                self.name_of_gate_instance()


            self.state = 2576
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2577
            self.inout_terminal()
            self.state = 2578
            self.match(VerilogParser.COMMA)
            self.state = 2579
            self.inout_terminal()
            self.state = 2580
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_enable_switch_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def inout_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Inout_terminalContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Inout_terminalContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def enable_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Enable_terminalContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pass_enable_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_enable_switch_instance" ):
                listener.enterPass_enable_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_enable_switch_instance" ):
                listener.exitPass_enable_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_enable_switch_instance" ):
                return visitor.visitPass_enable_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def pass_enable_switch_instance(self):

        localctx = VerilogParser.Pass_enable_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 322, self.RULE_pass_enable_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2583
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2582
                self.name_of_gate_instance()


            self.state = 2585
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2586
            self.inout_terminal()
            self.state = 2587
            self.match(VerilogParser.COMMA)
            self.state = 2588
            self.inout_terminal()
            self.state = 2589
            self.match(VerilogParser.COMMA)
            self.state = 2590
            self.enable_terminal()
            self.state = 2591
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pull_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(VerilogParser.Output_terminalContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def name_of_gate_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_gate_instanceContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pull_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPull_gate_instance" ):
                listener.enterPull_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPull_gate_instance" ):
                listener.exitPull_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPull_gate_instance" ):
                return visitor.visitPull_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def pull_gate_instance(self):

        localctx = VerilogParser.Pull_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 324, self.RULE_pull_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2594
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2593
                self.name_of_gate_instance()


            self.state = 2596
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2597
            self.output_terminal()
            self.state = 2598
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Name_of_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def gate_instance_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Gate_instance_identifierContext,0)


        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_name_of_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterName_of_gate_instance" ):
                listener.enterName_of_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitName_of_gate_instance" ):
                listener.exitName_of_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitName_of_gate_instance" ):
                return visitor.visitName_of_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def name_of_gate_instance(self):

        localctx = VerilogParser.Name_of_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 326, self.RULE_name_of_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2600
            self.gate_instance_identifier()
            self.state = 2602
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 2601
                self.range_()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pulldown_strengthContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def strength0(self):
            return self.getTypedRuleContext(VerilogParser.Strength0Context,0)


        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def strength1(self):
            return self.getTypedRuleContext(VerilogParser.Strength1Context,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pulldown_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulldown_strength" ):
                listener.enterPulldown_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulldown_strength" ):
                listener.exitPulldown_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulldown_strength" ):
                return visitor.visitPulldown_strength(self)
            else:
                return visitor.visitChildren(self)




    def pulldown_strength(self):

        localctx = VerilogParser.Pulldown_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 328, self.RULE_pulldown_strength)
        try:
            self.state = 2620
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,253,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2604
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 2605
                self.strength0()
                self.state = 2606
                self.match(VerilogParser.COMMA)
                self.state = 2607
                self.strength1()
                self.state = 2608
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2610
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 2611
                self.strength1()
                self.state = 2612
                self.match(VerilogParser.COMMA)
                self.state = 2613
                self.strength0()
                self.state = 2614
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2616
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 2617
                self.strength0()
                self.state = 2618
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pullup_strengthContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def strength0(self):
            return self.getTypedRuleContext(VerilogParser.Strength0Context,0)


        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def strength1(self):
            return self.getTypedRuleContext(VerilogParser.Strength1Context,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pullup_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPullup_strength" ):
                listener.enterPullup_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPullup_strength" ):
                listener.exitPullup_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPullup_strength" ):
                return visitor.visitPullup_strength(self)
            else:
                return visitor.visitChildren(self)




    def pullup_strength(self):

        localctx = VerilogParser.Pullup_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 330, self.RULE_pullup_strength)
        try:
            self.state = 2638
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,254,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2622
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 2623
                self.strength0()
                self.state = 2624
                self.match(VerilogParser.COMMA)
                self.state = 2625
                self.strength1()
                self.state = 2626
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2628
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 2629
                self.strength1()
                self.state = 2630
                self.match(VerilogParser.COMMA)
                self.state = 2631
                self.strength0()
                self.state = 2632
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2634
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 2635
                self.strength1()
                self.state = 2636
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_enable_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_terminal" ):
                listener.enterEnable_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_terminal" ):
                listener.exitEnable_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_terminal" ):
                return visitor.visitEnable_terminal(self)
            else:
                return visitor.visitChildren(self)




    def enable_terminal(self):

        localctx = VerilogParser.Enable_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 332, self.RULE_enable_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2640
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_inout_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_terminal" ):
                listener.enterInout_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_terminal" ):
                listener.exitInout_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_terminal" ):
                return visitor.visitInout_terminal(self)
            else:
                return visitor.visitChildren(self)




    def inout_terminal(self):

        localctx = VerilogParser.Inout_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 334, self.RULE_inout_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2642
            self.net_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_input_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_terminal" ):
                listener.enterInput_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_terminal" ):
                listener.exitInput_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_terminal" ):
                return visitor.visitInput_terminal(self)
            else:
                return visitor.visitChildren(self)




    def input_terminal(self):

        localctx = VerilogParser.Input_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 336, self.RULE_input_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2644
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ncontrol_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_ncontrol_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNcontrol_terminal" ):
                listener.enterNcontrol_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNcontrol_terminal" ):
                listener.exitNcontrol_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNcontrol_terminal" ):
                return visitor.visitNcontrol_terminal(self)
            else:
                return visitor.visitChildren(self)




    def ncontrol_terminal(self):

        localctx = VerilogParser.Ncontrol_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 338, self.RULE_ncontrol_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2646
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_output_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_terminal" ):
                listener.enterOutput_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_terminal" ):
                listener.exitOutput_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_terminal" ):
                return visitor.visitOutput_terminal(self)
            else:
                return visitor.visitChildren(self)




    def output_terminal(self):

        localctx = VerilogParser.Output_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 340, self.RULE_output_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2648
            self.net_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pcontrol_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_pcontrol_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPcontrol_terminal" ):
                listener.enterPcontrol_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPcontrol_terminal" ):
                listener.exitPcontrol_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPcontrol_terminal" ):
                return visitor.visitPcontrol_terminal(self)
            else:
                return visitor.visitChildren(self)




    def pcontrol_terminal(self):

        localctx = VerilogParser.Pcontrol_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 342, self.RULE_pcontrol_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2650
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cmos_switchtypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CMOS(self):
            return self.getToken(VerilogParser.CMOS, 0)

        def RCMOS(self):
            return self.getToken(VerilogParser.RCMOS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_cmos_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switchtype" ):
                listener.enterCmos_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switchtype" ):
                listener.exitCmos_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switchtype" ):
                return visitor.visitCmos_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switchtype(self):

        localctx = VerilogParser.Cmos_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 344, self.RULE_cmos_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2652
            _la = self._input.LA(1)
            if not(_la==VerilogParser.CMOS or _la==VerilogParser.RCMOS):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_gatetypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def BUFIF0(self):
            return self.getToken(VerilogParser.BUFIF0, 0)

        def BUFIF1(self):
            return self.getToken(VerilogParser.BUFIF1, 0)

        def NOTIF0(self):
            return self.getToken(VerilogParser.NOTIF0, 0)

        def NOTIF1(self):
            return self.getToken(VerilogParser.NOTIF1, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_enable_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gatetype" ):
                listener.enterEnable_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gatetype" ):
                listener.exitEnable_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gatetype" ):
                return visitor.visitEnable_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def enable_gatetype(self):

        localctx = VerilogParser.Enable_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 346, self.RULE_enable_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2654
            _la = self._input.LA(1)
            if not(((((_la - 7)) & ~0x3f) == 0 and ((1 << (_la - 7)) & ((1 << (VerilogParser.BUFIF0 - 7)) | (1 << (VerilogParser.BUFIF1 - 7)) | (1 << (VerilogParser.NOTIF0 - 7)) | (1 << (VerilogParser.NOTIF1 - 7)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mos_switchtypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def NMOS(self):
            return self.getToken(VerilogParser.NMOS, 0)

        def PMOS(self):
            return self.getToken(VerilogParser.PMOS, 0)

        def RNMOS(self):
            return self.getToken(VerilogParser.RNMOS, 0)

        def RPMOS(self):
            return self.getToken(VerilogParser.RPMOS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_mos_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switchtype" ):
                listener.enterMos_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switchtype" ):
                listener.exitMos_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switchtype" ):
                return visitor.visitMos_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def mos_switchtype(self):

        localctx = VerilogParser.Mos_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 348, self.RULE_mos_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2656
            _la = self._input.LA(1)
            if not(((((_la - 61)) & ~0x3f) == 0 and ((1 << (_la - 61)) & ((1 << (VerilogParser.NMOS - 61)) | (1 << (VerilogParser.PMOS - 61)) | (1 << (VerilogParser.RNMOS - 61)) | (1 << (VerilogParser.RPMOS - 61)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_input_gatetypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def AND(self):
            return self.getToken(VerilogParser.AND, 0)

        def NAND(self):
            return self.getToken(VerilogParser.NAND, 0)

        def OR(self):
            return self.getToken(VerilogParser.OR, 0)

        def NOR(self):
            return self.getToken(VerilogParser.NOR, 0)

        def XOR(self):
            return self.getToken(VerilogParser.XOR, 0)

        def XNOR(self):
            return self.getToken(VerilogParser.XNOR, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_n_input_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gatetype" ):
                listener.enterN_input_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gatetype" ):
                listener.exitN_input_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gatetype" ):
                return visitor.visitN_input_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gatetype(self):

        localctx = VerilogParser.N_input_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 350, self.RULE_n_input_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2658
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.AND) | (1 << VerilogParser.NAND) | (1 << VerilogParser.NOR))) != 0) or ((((_la - 67)) & ~0x3f) == 0 and ((1 << (_la - 67)) & ((1 << (VerilogParser.OR - 67)) | (1 << (VerilogParser.XNOR - 67)) | (1 << (VerilogParser.XOR - 67)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_output_gatetypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def BUF(self):
            return self.getToken(VerilogParser.BUF, 0)

        def NOT(self):
            return self.getToken(VerilogParser.NOT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_n_output_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gatetype" ):
                listener.enterN_output_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gatetype" ):
                listener.exitN_output_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gatetype" ):
                return visitor.visitN_output_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gatetype(self):

        localctx = VerilogParser.N_output_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 352, self.RULE_n_output_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2660
            _la = self._input.LA(1)
            if not(_la==VerilogParser.BUF or _la==VerilogParser.NOT):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_en_switchtypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TRANIF0(self):
            return self.getToken(VerilogParser.TRANIF0, 0)

        def TRANIF1(self):
            return self.getToken(VerilogParser.TRANIF1, 0)

        def RTRANIF1(self):
            return self.getToken(VerilogParser.RTRANIF1, 0)

        def RTRANIF0(self):
            return self.getToken(VerilogParser.RTRANIF0, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pass_en_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_en_switchtype" ):
                listener.enterPass_en_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_en_switchtype" ):
                listener.exitPass_en_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_en_switchtype" ):
                return visitor.visitPass_en_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def pass_en_switchtype(self):

        localctx = VerilogParser.Pass_en_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 354, self.RULE_pass_en_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2662
            _la = self._input.LA(1)
            if not(((((_la - 88)) & ~0x3f) == 0 and ((1 << (_la - 88)) & ((1 << (VerilogParser.RTRANIF0 - 88)) | (1 << (VerilogParser.RTRANIF1 - 88)) | (1 << (VerilogParser.TRANIF0 - 88)) | (1 << (VerilogParser.TRANIF1 - 88)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_switchtypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def TRAN(self):
            return self.getToken(VerilogParser.TRAN, 0)

        def RTRAN(self):
            return self.getToken(VerilogParser.RTRAN, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pass_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switchtype" ):
                listener.enterPass_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switchtype" ):
                listener.exitPass_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switchtype" ):
                return visitor.visitPass_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def pass_switchtype(self):

        localctx = VerilogParser.Pass_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 356, self.RULE_pass_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2664
            _la = self._input.LA(1)
            if not(_la==VerilogParser.RTRAN or _la==VerilogParser.TRAN):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_instantiationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Module_identifierContext,0)


        def module_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_instanceContext,i)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def parameter_value_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_value_assignmentContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instantiation" ):
                listener.enterModule_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instantiation" ):
                listener.exitModule_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instantiation" ):
                return visitor.visitModule_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def module_instantiation(self):

        localctx = VerilogParser.Module_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 358, self.RULE_module_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2666
            self.module_identifier()
            self.state = 2668
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.HASH:
                self.state = 2667
                self.parameter_value_assignment()


            self.state = 2670
            self.module_instance()
            self.state = 2675
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 2671
                self.match(VerilogParser.COMMA)
                self.state = 2672
                self.module_instance()
                self.state = 2677
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2678
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_value_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HASH(self):
            return self.getToken(VerilogParser.HASH, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def list_of_parameter_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_parameter_assignmentsContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_value_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_value_assignment" ):
                listener.enterParameter_value_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_value_assignment" ):
                listener.exitParameter_value_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_value_assignment" ):
                return visitor.visitParameter_value_assignment(self)
            else:
                return visitor.visitChildren(self)




    def parameter_value_assignment(self):

        localctx = VerilogParser.Parameter_value_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 360, self.RULE_parameter_value_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2680
            self.match(VerilogParser.HASH)
            self.state = 2681
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2682
            self.list_of_parameter_assignments()
            self.state = 2683
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_parameter_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ordered_parameter_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Ordered_parameter_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Ordered_parameter_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def named_parameter_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Named_parameter_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Named_parameter_assignmentContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_parameter_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_parameter_assignments" ):
                listener.enterList_of_parameter_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_parameter_assignments" ):
                listener.exitList_of_parameter_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_parameter_assignments" ):
                return visitor.visitList_of_parameter_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_parameter_assignments(self):

        localctx = VerilogParser.List_of_parameter_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 362, self.RULE_list_of_parameter_assignments)
        self._la = 0 # Token type
        try:
            self.state = 2701
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2685
                self.ordered_parameter_assignment()
                self.state = 2690
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2686
                    self.match(VerilogParser.COMMA)
                    self.state = 2687
                    self.ordered_parameter_assignment()
                    self.state = 2692
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            elif token in [VerilogParser.DOT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2693
                self.named_parameter_assignment()
                self.state = 2698
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2694
                    self.match(VerilogParser.COMMA)
                    self.state = 2695
                    self.named_parameter_assignment()
                    self.state = 2700
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ordered_parameter_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_ordered_parameter_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOrdered_parameter_assignment" ):
                listener.enterOrdered_parameter_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOrdered_parameter_assignment" ):
                listener.exitOrdered_parameter_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOrdered_parameter_assignment" ):
                return visitor.visitOrdered_parameter_assignment(self)
            else:
                return visitor.visitChildren(self)




    def ordered_parameter_assignment(self):

        localctx = VerilogParser.Ordered_parameter_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 364, self.RULE_ordered_parameter_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2703
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Named_parameter_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self):
            return self.getToken(VerilogParser.DOT, 0)

        def parameter_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_identifierContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_named_parameter_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNamed_parameter_assignment" ):
                listener.enterNamed_parameter_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNamed_parameter_assignment" ):
                listener.exitNamed_parameter_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNamed_parameter_assignment" ):
                return visitor.visitNamed_parameter_assignment(self)
            else:
                return visitor.visitChildren(self)




    def named_parameter_assignment(self):

        localctx = VerilogParser.Named_parameter_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 366, self.RULE_named_parameter_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2705
            self.match(VerilogParser.DOT)
            self.state = 2706
            self.parameter_identifier()
            self.state = 2707
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2709
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                self.state = 2708
                self.mintypmax_expression()


            self.state = 2711
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def name_of_module_instance(self):
            return self.getTypedRuleContext(VerilogParser.Name_of_module_instanceContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def list_of_port_connections(self):
            return self.getTypedRuleContext(VerilogParser.List_of_port_connectionsContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instance" ):
                listener.enterModule_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instance" ):
                listener.exitModule_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instance" ):
                return visitor.visitModule_instance(self)
            else:
                return visitor.visitChildren(self)




    def module_instance(self):

        localctx = VerilogParser.Module_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 368, self.RULE_module_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2713
            self.name_of_module_instance()
            self.state = 2714
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2715
            self.list_of_port_connections()
            self.state = 2716
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Name_of_module_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_instance_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Module_instance_identifierContext,0)


        def range_(self):
            return self.getTypedRuleContext(VerilogParser.Range_Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_name_of_module_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterName_of_module_instance" ):
                listener.enterName_of_module_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitName_of_module_instance" ):
                listener.exitName_of_module_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitName_of_module_instance" ):
                return visitor.visitName_of_module_instance(self)
            else:
                return visitor.visitChildren(self)




    def name_of_module_instance(self):

        localctx = VerilogParser.Name_of_module_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 370, self.RULE_name_of_module_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2718
            self.module_instance_identifier()
            self.state = 2720
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 2719
                self.range_()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_connectionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ordered_port_connection(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Ordered_port_connectionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Ordered_port_connectionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def named_port_connection(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Named_port_connectionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Named_port_connectionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_port_connections

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_connections" ):
                listener.enterList_of_port_connections(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_connections" ):
                listener.exitList_of_port_connections(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_connections" ):
                return visitor.visitList_of_port_connections(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_connections(self):

        localctx = VerilogParser.List_of_port_connectionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 372, self.RULE_list_of_port_connections)
        self._la = 0 # Token type
        try:
            self.state = 2738
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,264,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2722
                self.ordered_port_connection()
                self.state = 2727
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2723
                    self.match(VerilogParser.COMMA)
                    self.state = 2724
                    self.ordered_port_connection()
                    self.state = 2729
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2730
                self.named_port_connection()
                self.state = 2735
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2731
                    self.match(VerilogParser.COMMA)
                    self.state = 2732
                    self.named_port_connection()
                    self.state = 2737
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ordered_port_connectionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_ordered_port_connection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOrdered_port_connection" ):
                listener.enterOrdered_port_connection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOrdered_port_connection" ):
                listener.exitOrdered_port_connection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOrdered_port_connection" ):
                return visitor.visitOrdered_port_connection(self)
            else:
                return visitor.visitChildren(self)




    def ordered_port_connection(self):

        localctx = VerilogParser.Ordered_port_connectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 374, self.RULE_ordered_port_connection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2743
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,265,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 2740
                    self.attribute_instance() 
                self.state = 2745
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,265,self._ctx)

            self.state = 2747
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                self.state = 2746
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Named_port_connectionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self):
            return self.getToken(VerilogParser.DOT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Port_identifierContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_named_port_connection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNamed_port_connection" ):
                listener.enterNamed_port_connection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNamed_port_connection" ):
                listener.exitNamed_port_connection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNamed_port_connection" ):
                return visitor.visitNamed_port_connection(self)
            else:
                return visitor.visitChildren(self)




    def named_port_connection(self):

        localctx = VerilogParser.Named_port_connectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 376, self.RULE_named_port_connection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2752
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 2749
                self.attribute_instance()
                self.state = 2754
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2755
            self.match(VerilogParser.DOT)
            self.state = 2756
            self.port_identifier()
            self.state = 2757
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2759
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                self.state = 2758
                self.expression(0)


            self.state = 2761
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_regionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GENERATE(self):
            return self.getToken(VerilogParser.GENERATE, 0)

        def ENDGENERATE(self):
            return self.getToken(VerilogParser.ENDGENERATE, 0)

        def module_or_generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_or_generate_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_or_generate_itemContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_generate_region

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_region" ):
                listener.enterGenerate_region(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_region" ):
                listener.exitGenerate_region(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_region" ):
                return visitor.visitGenerate_region(self)
            else:
                return visitor.visitChildren(self)




    def generate_region(self):

        localctx = VerilogParser.Generate_regionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 378, self.RULE_generate_region)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2763
            self.match(VerilogParser.GENERATE)
            self.state = 2767
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ALWAYS) | (1 << VerilogParser.AND) | (1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BUF) | (1 << VerilogParser.BUFIF0) | (1 << VerilogParser.BUFIF1) | (1 << VerilogParser.CMOS) | (1 << VerilogParser.DEFAULT) | (1 << VerilogParser.DEFPARAM) | (1 << VerilogParser.EVENT) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FUNCTION) | (1 << VerilogParser.GENVAR) | (1 << VerilogParser.IF) | (1 << VerilogParser.INITIAL) | (1 << VerilogParser.INTEGER) | (1 << VerilogParser.LOCALPARAM) | (1 << VerilogParser.NAND) | (1 << VerilogParser.NMOS) | (1 << VerilogParser.NOR))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (VerilogParser.NOT - 64)) | (1 << (VerilogParser.NOTIF0 - 64)) | (1 << (VerilogParser.NOTIF1 - 64)) | (1 << (VerilogParser.OR - 64)) | (1 << (VerilogParser.PMOS - 64)) | (1 << (VerilogParser.PULLDOWN - 64)) | (1 << (VerilogParser.PULLUP - 64)) | (1 << (VerilogParser.RCMOS - 64)) | (1 << (VerilogParser.REAL - 64)) | (1 << (VerilogParser.REALTIME - 64)) | (1 << (VerilogParser.REG - 64)) | (1 << (VerilogParser.RNMOS - 64)) | (1 << (VerilogParser.RPMOS - 64)) | (1 << (VerilogParser.RTRAN - 64)) | (1 << (VerilogParser.RTRANIF0 - 64)) | (1 << (VerilogParser.RTRANIF1 - 64)) | (1 << (VerilogParser.SUPPLY0 - 64)) | (1 << (VerilogParser.SUPPLY1 - 64)) | (1 << (VerilogParser.TASK - 64)) | (1 << (VerilogParser.TIME - 64)) | (1 << (VerilogParser.TRAN - 64)) | (1 << (VerilogParser.TRANIF0 - 64)) | (1 << (VerilogParser.TRANIF1 - 64)) | (1 << (VerilogParser.TRI - 64)) | (1 << (VerilogParser.TRI0 - 64)) | (1 << (VerilogParser.TRI1 - 64)) | (1 << (VerilogParser.TRIAND - 64)) | (1 << (VerilogParser.TRIOR - 64)) | (1 << (VerilogParser.TRIREG - 64)) | (1 << (VerilogParser.WAND - 64)) | (1 << (VerilogParser.WIRE - 64)) | (1 << (VerilogParser.WOR - 64)) | (1 << (VerilogParser.XNOR - 64)) | (1 << (VerilogParser.XOR - 64)))) != 0) or ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                self.state = 2764
                self.module_or_generate_item()
                self.state = 2769
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2770
            self.match(VerilogParser.ENDGENERATE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GENVAR(self):
            return self.getToken(VerilogParser.GENVAR, 0)

        def list_of_genvar_identifiers(self):
            return self.getTypedRuleContext(VerilogParser.List_of_genvar_identifiersContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_declaration" ):
                listener.enterGenvar_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_declaration" ):
                listener.exitGenvar_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_declaration" ):
                return visitor.visitGenvar_declaration(self)
            else:
                return visitor.visitChildren(self)




    def genvar_declaration(self):

        localctx = VerilogParser.Genvar_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 380, self.RULE_genvar_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2772
            self.match(VerilogParser.GENVAR)
            self.state = 2773
            self.list_of_genvar_identifiers()
            self.state = 2774
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_genvar_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Genvar_identifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Genvar_identifierContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_genvar_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_genvar_identifiers" ):
                listener.enterList_of_genvar_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_genvar_identifiers" ):
                listener.exitList_of_genvar_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_genvar_identifiers" ):
                return visitor.visitList_of_genvar_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_genvar_identifiers(self):

        localctx = VerilogParser.List_of_genvar_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 382, self.RULE_list_of_genvar_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2776
            self.genvar_identifier()
            self.state = 2781
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 2777
                self.match(VerilogParser.COMMA)
                self.state = 2778
                self.genvar_identifier()
                self.state = 2783
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_generate_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FOR(self):
            return self.getToken(VerilogParser.FOR, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def genvar_initialization(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_initializationContext,0)


        def SEMICOLON(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.SEMICOLON)
            else:
                return self.getToken(VerilogParser.SEMICOLON, i)

        def genvar_expression(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_expressionContext,0)


        def genvar_iteration(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_iterationContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def generate_block(self):
            return self.getTypedRuleContext(VerilogParser.Generate_blockContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_loop_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_generate_construct" ):
                listener.enterLoop_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_generate_construct" ):
                listener.exitLoop_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_generate_construct" ):
                return visitor.visitLoop_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def loop_generate_construct(self):

        localctx = VerilogParser.Loop_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 384, self.RULE_loop_generate_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2784
            self.match(VerilogParser.FOR)
            self.state = 2785
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2786
            self.genvar_initialization()
            self.state = 2787
            self.match(VerilogParser.SEMICOLON)
            self.state = 2788
            self.genvar_expression(0)
            self.state = 2789
            self.match(VerilogParser.SEMICOLON)
            self.state = 2790
            self.genvar_iteration()
            self.state = 2791
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 2792
            self.generate_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_initializationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_identifierContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_initialization

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_initialization" ):
                listener.enterGenvar_initialization(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_initialization" ):
                listener.exitGenvar_initialization(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_initialization" ):
                return visitor.visitGenvar_initialization(self)
            else:
                return visitor.visitChildren(self)




    def genvar_initialization(self):

        localctx = VerilogParser.Genvar_initializationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 386, self.RULE_genvar_initialization)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2794
            self.genvar_identifier()
            self.state = 2795
            self.match(VerilogParser.EQUAL)
            self.state = 2796
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_primary(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_primaryContext,0)


        def unary_operator(self):
            return self.getTypedRuleContext(VerilogParser.Unary_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def genvar_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Genvar_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Genvar_expressionContext,i)


        def binary_operator(self):
            return self.getTypedRuleContext(VerilogParser.Binary_operatorContext,0)


        def QUESTION_MARK(self):
            return self.getToken(VerilogParser.QUESTION_MARK, 0)

        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_expression" ):
                listener.enterGenvar_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_expression" ):
                listener.exitGenvar_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_expression" ):
                return visitor.visitGenvar_expression(self)
            else:
                return visitor.visitChildren(self)



    def genvar_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.Genvar_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 388
        self.enterRecursionRule(localctx, 388, self.RULE_genvar_expression, _p)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2809
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE]:
                self.state = 2799
                self.genvar_primary()
                pass
            elif token in [VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.state = 2800
                self.unary_operator()
                self.state = 2804
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,271,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2801
                        self.attribute_instance() 
                    self.state = 2806
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,271,self._ctx)

                self.state = 2807
                self.genvar_primary()
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 2835
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,276,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 2833
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,275,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.Genvar_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_genvar_expression)
                        self.state = 2811
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 2812
                        self.binary_operator()
                        self.state = 2816
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,273,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 2813
                                self.attribute_instance() 
                            self.state = 2818
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,273,self._ctx)

                        self.state = 2819
                        self.genvar_expression(3)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.Genvar_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_genvar_expression)
                        self.state = 2821
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 2822
                        self.match(VerilogParser.QUESTION_MARK)
                        self.state = 2826
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,274,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 2823
                                self.attribute_instance() 
                            self.state = 2828
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,274,self._ctx)

                        self.state = 2829
                        self.genvar_expression(0)
                        self.state = 2830
                        self.match(VerilogParser.COLON)
                        self.state = 2831
                        self.genvar_expression(2)
                        pass

             
                self.state = 2837
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,276,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Genvar_iterationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_identifierContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def genvar_expression(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_iteration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_iteration" ):
                listener.enterGenvar_iteration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_iteration" ):
                listener.exitGenvar_iteration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_iteration" ):
                return visitor.visitGenvar_iteration(self)
            else:
                return visitor.visitChildren(self)




    def genvar_iteration(self):

        localctx = VerilogParser.Genvar_iterationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 390, self.RULE_genvar_iteration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2838
            self.genvar_identifier()
            self.state = 2839
            self.match(VerilogParser.EQUAL)
            self.state = 2840
            self.genvar_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_primaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_primary(self):
            return self.getTypedRuleContext(VerilogParser.Constant_primaryContext,0)


        def genvar_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Genvar_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_primary" ):
                listener.enterGenvar_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_primary" ):
                listener.exitGenvar_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_primary" ):
                return visitor.visitGenvar_primary(self)
            else:
                return visitor.visitChildren(self)




    def genvar_primary(self):

        localctx = VerilogParser.Genvar_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 392, self.RULE_genvar_primary)
        try:
            self.state = 2844
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,277,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2842
                self.constant_primary()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2843
                self.genvar_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Conditional_generate_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def if_generate_construct(self):
            return self.getTypedRuleContext(VerilogParser.If_generate_constructContext,0)


        def case_generate_construct(self):
            return self.getTypedRuleContext(VerilogParser.Case_generate_constructContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_conditional_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConditional_generate_construct" ):
                listener.enterConditional_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConditional_generate_construct" ):
                listener.exitConditional_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConditional_generate_construct" ):
                return visitor.visitConditional_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def conditional_generate_construct(self):

        localctx = VerilogParser.Conditional_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 394, self.RULE_conditional_generate_construct)
        try:
            self.state = 2848
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.IF]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2846
                self.if_generate_construct()
                pass
            elif token in [VerilogParser.DEFAULT, VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2847
                self.case_generate_construct()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class If_generate_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def IF(self):
            return self.getToken(VerilogParser.IF, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def generate_block_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Generate_block_or_nullContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Generate_block_or_nullContext,i)


        def ELSE(self):
            return self.getToken(VerilogParser.ELSE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_if_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIf_generate_construct" ):
                listener.enterIf_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIf_generate_construct" ):
                listener.exitIf_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIf_generate_construct" ):
                return visitor.visitIf_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def if_generate_construct(self):

        localctx = VerilogParser.If_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 396, self.RULE_if_generate_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2850
            self.match(VerilogParser.IF)
            self.state = 2851
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 2852
            self.constant_expression(0)
            self.state = 2853
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 2854
            self.generate_block_or_null()
            self.state = 2857
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,279,self._ctx)
            if la_ == 1:
                self.state = 2855
                self.match(VerilogParser.ELSE)
                self.state = 2856
                self.generate_block_or_null()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_generate_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def generate_block_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Generate_block_or_nullContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def DEFAULT(self):
            return self.getToken(VerilogParser.DEFAULT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_case_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_generate_construct" ):
                listener.enterCase_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_generate_construct" ):
                listener.exitCase_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_generate_construct" ):
                return visitor.visitCase_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def case_generate_construct(self):

        localctx = VerilogParser.Case_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 398, self.RULE_case_generate_construct)
        self._la = 0 # Token type
        try:
            self.state = 2875
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2859
                self.constant_expression(0)
                self.state = 2864
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 2860
                    self.match(VerilogParser.COMMA)
                    self.state = 2861
                    self.constant_expression(0)
                    self.state = 2866
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2867
                self.match(VerilogParser.COLON)
                self.state = 2868
                self.generate_block_or_null()
                pass
            elif token in [VerilogParser.DEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2870
                self.match(VerilogParser.DEFAULT)
                self.state = 2872
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COLON:
                    self.state = 2871
                    self.match(VerilogParser.COLON)


                self.state = 2874
                self.generate_block_or_null()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_or_generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_or_generate_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_or_generate_itemContext,i)


        def BEGIN(self):
            return self.getToken(VerilogParser.BEGIN, 0)

        def END(self):
            return self.getToken(VerilogParser.END, 0)

        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def generate_block_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Generate_block_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_generate_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block" ):
                listener.enterGenerate_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block" ):
                listener.exitGenerate_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block" ):
                return visitor.visitGenerate_block(self)
            else:
                return visitor.visitChildren(self)




    def generate_block(self):

        localctx = VerilogParser.Generate_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 400, self.RULE_generate_block)
        self._la = 0 # Token type
        try:
            self.state = 2890
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ALWAYS, VerilogParser.AND, VerilogParser.ASSIGN, VerilogParser.BUF, VerilogParser.BUFIF0, VerilogParser.BUFIF1, VerilogParser.CMOS, VerilogParser.DEFAULT, VerilogParser.DEFPARAM, VerilogParser.EVENT, VerilogParser.FOR, VerilogParser.FUNCTION, VerilogParser.GENVAR, VerilogParser.IF, VerilogParser.INITIAL, VerilogParser.INTEGER, VerilogParser.LOCALPARAM, VerilogParser.NAND, VerilogParser.NMOS, VerilogParser.NOR, VerilogParser.NOT, VerilogParser.NOTIF0, VerilogParser.NOTIF1, VerilogParser.OR, VerilogParser.PMOS, VerilogParser.PULLDOWN, VerilogParser.PULLUP, VerilogParser.RCMOS, VerilogParser.REAL, VerilogParser.REALTIME, VerilogParser.REG, VerilogParser.RNMOS, VerilogParser.RPMOS, VerilogParser.RTRAN, VerilogParser.RTRANIF0, VerilogParser.RTRANIF1, VerilogParser.SUPPLY0, VerilogParser.SUPPLY1, VerilogParser.TASK, VerilogParser.TIME, VerilogParser.TRAN, VerilogParser.TRANIF0, VerilogParser.TRANIF1, VerilogParser.TRI, VerilogParser.TRI0, VerilogParser.TRI1, VerilogParser.TRIAND, VerilogParser.TRIOR, VerilogParser.TRIREG, VerilogParser.WAND, VerilogParser.WIRE, VerilogParser.WOR, VerilogParser.XNOR, VerilogParser.XOR, VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2877
                self.module_or_generate_item()
                pass
            elif token in [VerilogParser.BEGIN]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2878
                self.match(VerilogParser.BEGIN)
                self.state = 2881
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COLON:
                    self.state = 2879
                    self.match(VerilogParser.COLON)
                    self.state = 2880
                    self.generate_block_identifier()


                self.state = 2886
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ALWAYS) | (1 << VerilogParser.AND) | (1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BUF) | (1 << VerilogParser.BUFIF0) | (1 << VerilogParser.BUFIF1) | (1 << VerilogParser.CMOS) | (1 << VerilogParser.DEFAULT) | (1 << VerilogParser.DEFPARAM) | (1 << VerilogParser.EVENT) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FUNCTION) | (1 << VerilogParser.GENVAR) | (1 << VerilogParser.IF) | (1 << VerilogParser.INITIAL) | (1 << VerilogParser.INTEGER) | (1 << VerilogParser.LOCALPARAM) | (1 << VerilogParser.NAND) | (1 << VerilogParser.NMOS) | (1 << VerilogParser.NOR))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (VerilogParser.NOT - 64)) | (1 << (VerilogParser.NOTIF0 - 64)) | (1 << (VerilogParser.NOTIF1 - 64)) | (1 << (VerilogParser.OR - 64)) | (1 << (VerilogParser.PMOS - 64)) | (1 << (VerilogParser.PULLDOWN - 64)) | (1 << (VerilogParser.PULLUP - 64)) | (1 << (VerilogParser.RCMOS - 64)) | (1 << (VerilogParser.REAL - 64)) | (1 << (VerilogParser.REALTIME - 64)) | (1 << (VerilogParser.REG - 64)) | (1 << (VerilogParser.RNMOS - 64)) | (1 << (VerilogParser.RPMOS - 64)) | (1 << (VerilogParser.RTRAN - 64)) | (1 << (VerilogParser.RTRANIF0 - 64)) | (1 << (VerilogParser.RTRANIF1 - 64)) | (1 << (VerilogParser.SUPPLY0 - 64)) | (1 << (VerilogParser.SUPPLY1 - 64)) | (1 << (VerilogParser.TASK - 64)) | (1 << (VerilogParser.TIME - 64)) | (1 << (VerilogParser.TRAN - 64)) | (1 << (VerilogParser.TRANIF0 - 64)) | (1 << (VerilogParser.TRANIF1 - 64)) | (1 << (VerilogParser.TRI - 64)) | (1 << (VerilogParser.TRI0 - 64)) | (1 << (VerilogParser.TRI1 - 64)) | (1 << (VerilogParser.TRIAND - 64)) | (1 << (VerilogParser.TRIOR - 64)) | (1 << (VerilogParser.TRIREG - 64)) | (1 << (VerilogParser.WAND - 64)) | (1 << (VerilogParser.WIRE - 64)) | (1 << (VerilogParser.WOR - 64)) | (1 << (VerilogParser.XNOR - 64)) | (1 << (VerilogParser.XOR - 64)))) != 0) or ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                    self.state = 2883
                    self.module_or_generate_item()
                    self.state = 2888
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2889
                self.match(VerilogParser.END)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_block_or_nullContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_block(self):
            return self.getTypedRuleContext(VerilogParser.Generate_blockContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_generate_block_or_null

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block_or_null" ):
                listener.enterGenerate_block_or_null(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block_or_null" ):
                listener.exitGenerate_block_or_null(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block_or_null" ):
                return visitor.visitGenerate_block_or_null(self)
            else:
                return visitor.visitChildren(self)




    def generate_block_or_null(self):

        localctx = VerilogParser.Generate_block_or_nullContext(self, self._ctx, self.state)
        self.enterRule(localctx, 402, self.RULE_generate_block_or_null)
        try:
            self.state = 2894
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ALWAYS, VerilogParser.AND, VerilogParser.ASSIGN, VerilogParser.BEGIN, VerilogParser.BUF, VerilogParser.BUFIF0, VerilogParser.BUFIF1, VerilogParser.CMOS, VerilogParser.DEFAULT, VerilogParser.DEFPARAM, VerilogParser.EVENT, VerilogParser.FOR, VerilogParser.FUNCTION, VerilogParser.GENVAR, VerilogParser.IF, VerilogParser.INITIAL, VerilogParser.INTEGER, VerilogParser.LOCALPARAM, VerilogParser.NAND, VerilogParser.NMOS, VerilogParser.NOR, VerilogParser.NOT, VerilogParser.NOTIF0, VerilogParser.NOTIF1, VerilogParser.OR, VerilogParser.PMOS, VerilogParser.PULLDOWN, VerilogParser.PULLUP, VerilogParser.RCMOS, VerilogParser.REAL, VerilogParser.REALTIME, VerilogParser.REG, VerilogParser.RNMOS, VerilogParser.RPMOS, VerilogParser.RTRAN, VerilogParser.RTRANIF0, VerilogParser.RTRANIF1, VerilogParser.SUPPLY0, VerilogParser.SUPPLY1, VerilogParser.TASK, VerilogParser.TIME, VerilogParser.TRAN, VerilogParser.TRANIF0, VerilogParser.TRANIF1, VerilogParser.TRI, VerilogParser.TRI0, VerilogParser.TRI1, VerilogParser.TRIAND, VerilogParser.TRIOR, VerilogParser.TRIREG, VerilogParser.WAND, VerilogParser.WIRE, VerilogParser.WOR, VerilogParser.XNOR, VerilogParser.XOR, VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2892
                self.generate_block()
                pass
            elif token in [VerilogParser.SEMICOLON]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2893
                self.match(VerilogParser.SEMICOLON)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Continuous_assignContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ASSIGN(self):
            return self.getToken(VerilogParser.ASSIGN, 0)

        def list_of_net_assignments(self):
            return self.getTypedRuleContext(VerilogParser.List_of_net_assignmentsContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def drive_strength(self):
            return self.getTypedRuleContext(VerilogParser.Drive_strengthContext,0)


        def delay3(self):
            return self.getTypedRuleContext(VerilogParser.Delay3Context,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_continuous_assign

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterContinuous_assign" ):
                listener.enterContinuous_assign(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitContinuous_assign" ):
                listener.exitContinuous_assign(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitContinuous_assign" ):
                return visitor.visitContinuous_assign(self)
            else:
                return visitor.visitChildren(self)




    def continuous_assign(self):

        localctx = VerilogParser.Continuous_assignContext(self, self._ctx, self.state)
        self.enterRule(localctx, 404, self.RULE_continuous_assign)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2896
            self.match(VerilogParser.ASSIGN)
            self.state = 2898
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 2897
                self.drive_strength()


            self.state = 2901
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.HASH:
                self.state = 2900
                self.delay3()


            self.state = 2903
            self.list_of_net_assignments()
            self.state = 2904
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_net_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Net_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Net_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_net_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_net_assignments" ):
                listener.enterList_of_net_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_net_assignments" ):
                listener.exitList_of_net_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_net_assignments" ):
                return visitor.visitList_of_net_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_net_assignments(self):

        localctx = VerilogParser.List_of_net_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 406, self.RULE_list_of_net_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2906
            self.net_assignment()
            self.state = 2911
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 2907
                self.match(VerilogParser.COMMA)
                self.state = 2908
                self.net_assignment()
                self.state = 2913
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_assignment" ):
                listener.enterNet_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_assignment" ):
                listener.exitNet_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_assignment" ):
                return visitor.visitNet_assignment(self)
            else:
                return visitor.visitChildren(self)




    def net_assignment(self):

        localctx = VerilogParser.Net_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 408, self.RULE_net_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2914
            self.net_lvalue()
            self.state = 2915
            self.match(VerilogParser.EQUAL)
            self.state = 2916
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Initial_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def INITIAL(self):
            return self.getToken(VerilogParser.INITIAL, 0)

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_initial_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInitial_construct" ):
                listener.enterInitial_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInitial_construct" ):
                listener.exitInitial_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInitial_construct" ):
                return visitor.visitInitial_construct(self)
            else:
                return visitor.visitChildren(self)




    def initial_construct(self):

        localctx = VerilogParser.Initial_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 410, self.RULE_initial_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2918
            self.match(VerilogParser.INITIAL)
            self.state = 2919
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Always_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ALWAYS(self):
            return self.getToken(VerilogParser.ALWAYS, 0)

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_always_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAlways_construct" ):
                listener.enterAlways_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAlways_construct" ):
                listener.exitAlways_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAlways_construct" ):
                return visitor.visitAlways_construct(self)
            else:
                return visitor.visitChildren(self)




    def always_construct(self):

        localctx = VerilogParser.Always_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 412, self.RULE_always_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2921
            self.match(VerilogParser.ALWAYS)
            self.state = 2922
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Blocking_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def delay_or_event_control(self):
            return self.getTypedRuleContext(VerilogParser.Delay_or_event_controlContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_blocking_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlocking_assignment" ):
                listener.enterBlocking_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlocking_assignment" ):
                listener.exitBlocking_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlocking_assignment" ):
                return visitor.visitBlocking_assignment(self)
            else:
                return visitor.visitChildren(self)




    def blocking_assignment(self):

        localctx = VerilogParser.Blocking_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 414, self.RULE_blocking_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2924
            self.variable_lvalue()
            self.state = 2925
            self.match(VerilogParser.EQUAL)
            self.state = 2927
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.REPEAT or _la==VerilogParser.AT or _la==VerilogParser.HASH:
                self.state = 2926
                self.delay_or_event_control()


            self.state = 2929
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Nonblocking_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,0)


        def LESS_THAN_EQUAL(self):
            return self.getToken(VerilogParser.LESS_THAN_EQUAL, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def delay_or_event_control(self):
            return self.getTypedRuleContext(VerilogParser.Delay_or_event_controlContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_nonblocking_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNonblocking_assignment" ):
                listener.enterNonblocking_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNonblocking_assignment" ):
                listener.exitNonblocking_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNonblocking_assignment" ):
                return visitor.visitNonblocking_assignment(self)
            else:
                return visitor.visitChildren(self)




    def nonblocking_assignment(self):

        localctx = VerilogParser.Nonblocking_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 416, self.RULE_nonblocking_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2931
            self.variable_lvalue()
            self.state = 2932
            self.match(VerilogParser.LESS_THAN_EQUAL)
            self.state = 2934
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.REPEAT or _la==VerilogParser.AT or _la==VerilogParser.HASH:
                self.state = 2933
                self.delay_or_event_control()


            self.state = 2936
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_continuous_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ASSIGN(self):
            return self.getToken(VerilogParser.ASSIGN, 0)

        def variable_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Variable_assignmentContext,0)


        def DEASSIGN(self):
            return self.getToken(VerilogParser.DEASSIGN, 0)

        def variable_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,0)


        def FORCE(self):
            return self.getToken(VerilogParser.FORCE, 0)

        def net_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Net_assignmentContext,0)


        def RELEASE(self):
            return self.getToken(VerilogParser.RELEASE, 0)

        def net_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_procedural_continuous_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_continuous_assignments" ):
                listener.enterProcedural_continuous_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_continuous_assignments" ):
                listener.exitProcedural_continuous_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_continuous_assignments" ):
                return visitor.visitProcedural_continuous_assignments(self)
            else:
                return visitor.visitChildren(self)




    def procedural_continuous_assignments(self):

        localctx = VerilogParser.Procedural_continuous_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 418, self.RULE_procedural_continuous_assignments)
        try:
            self.state = 2950
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,292,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2938
                self.match(VerilogParser.ASSIGN)
                self.state = 2939
                self.variable_assignment()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2940
                self.match(VerilogParser.DEASSIGN)
                self.state = 2941
                self.variable_lvalue()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2942
                self.match(VerilogParser.FORCE)
                self.state = 2943
                self.variable_assignment()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2944
                self.match(VerilogParser.FORCE)
                self.state = 2945
                self.net_assignment()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2946
                self.match(VerilogParser.RELEASE)
                self.state = 2947
                self.variable_lvalue()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2948
                self.match(VerilogParser.RELEASE)
                self.state = 2949
                self.net_lvalue()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_variable_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_assignment" ):
                listener.enterVariable_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_assignment" ):
                listener.exitVariable_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_assignment" ):
                return visitor.visitVariable_assignment(self)
            else:
                return visitor.visitChildren(self)




    def variable_assignment(self):

        localctx = VerilogParser.Variable_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 420, self.RULE_variable_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2952
            self.variable_lvalue()
            self.state = 2953
            self.match(VerilogParser.EQUAL)
            self.state = 2954
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Par_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FORK(self):
            return self.getToken(VerilogParser.FORK, 0)

        def JOIN(self):
            return self.getToken(VerilogParser.JOIN, 0)

        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def block_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Block_identifierContext,0)


        def statement(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.StatementContext)
            else:
                return self.getTypedRuleContext(VerilogParser.StatementContext,i)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_par_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPar_block" ):
                listener.enterPar_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPar_block" ):
                listener.exitPar_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPar_block" ):
                return visitor.visitPar_block(self)
            else:
                return visitor.visitChildren(self)




    def par_block(self):

        localctx = VerilogParser.Par_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 422, self.RULE_par_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2956
            self.match(VerilogParser.FORK)
            self.state = 2965
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.COLON:
                self.state = 2957
                self.match(VerilogParser.COLON)
                self.state = 2958
                self.block_identifier()
                self.state = 2962
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,293,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2959
                        self.block_item_declaration() 
                    self.state = 2964
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,293,self._ctx)



            self.state = 2970
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BEGIN) | (1 << VerilogParser.CASE) | (1 << VerilogParser.CASEX) | (1 << VerilogParser.CASEZ) | (1 << VerilogParser.DEASSIGN) | (1 << VerilogParser.DISABLE) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FORCE) | (1 << VerilogParser.FOREVER) | (1 << VerilogParser.FORK) | (1 << VerilogParser.IF))) != 0) or ((((_la - 83)) & ~0x3f) == 0 and ((1 << (_la - 83)) & ((1 << (VerilogParser.RELEASE - 83)) | (1 << (VerilogParser.REPEAT - 83)) | (1 << (VerilogParser.WAIT - 83)) | (1 << (VerilogParser.WHILE - 83)) | (1 << (VerilogParser.DOLLAR_DISPLAY - 83)) | (1 << (VerilogParser.DOLLAR_DISPLAYB - 83)) | (1 << (VerilogParser.DOLLAR_DISPLAYH - 83)) | (1 << (VerilogParser.DOLLAR_DISPLAYO - 83)) | (1 << (VerilogParser.DOLLAR_WRITE - 83)) | (1 << (VerilogParser.DOLLAR_WRITEB - 83)) | (1 << (VerilogParser.DOLLAR_WRITEH - 83)) | (1 << (VerilogParser.DOLLAR_WRITEO - 83)) | (1 << (VerilogParser.DOLLAR_STROBE - 83)) | (1 << (VerilogParser.DOLLAR_STROBEB - 83)) | (1 << (VerilogParser.DOLLAR_STROBEH - 83)) | (1 << (VerilogParser.DOLLAR_STROBEO - 83)) | (1 << (VerilogParser.DOLLAR_MONITOR - 83)) | (1 << (VerilogParser.DOLLAR_MONITORB - 83)) | (1 << (VerilogParser.DOLLAR_MONITORH - 83)) | (1 << (VerilogParser.DOLLAR_MONITORO - 83)) | (1 << (VerilogParser.DOLLAR_MONITOROFF - 83)) | (1 << (VerilogParser.DOLLAR_MONITORON - 83)) | (1 << (VerilogParser.DOLLAR_FCLOSE - 83)) | (1 << (VerilogParser.DOLLAR_FDISPLAY - 83)) | (1 << (VerilogParser.DOLLAR_FDISPLAYB - 83)) | (1 << (VerilogParser.DOLLAR_FDISPLAYH - 83)))) != 0) or ((((_la - 147)) & ~0x3f) == 0 and ((1 << (_la - 147)) & ((1 << (VerilogParser.DOLLAR_FDISPLAYO - 147)) | (1 << (VerilogParser.DOLLAR_FSTROBE - 147)) | (1 << (VerilogParser.DOLLAR_FSTROBEB - 147)) | (1 << (VerilogParser.DOLLAR_FSTROBEH - 147)) | (1 << (VerilogParser.DOLLAR_FSTROBEO - 147)) | (1 << (VerilogParser.DOLLAR_FWRITE - 147)) | (1 << (VerilogParser.DOLLAR_FWRITEB - 147)) | (1 << (VerilogParser.DOLLAR_FWRITEH - 147)) | (1 << (VerilogParser.DOLLAR_FWRITEO - 147)) | (1 << (VerilogParser.DOLLAR_FMONITOR - 147)) | (1 << (VerilogParser.DOLLAR_FMONITORB - 147)) | (1 << (VerilogParser.DOLLAR_FMONITORH - 147)) | (1 << (VerilogParser.DOLLAR_FMONITORO - 147)) | (1 << (VerilogParser.DOLLAR_READMEMB - 147)) | (1 << (VerilogParser.DOLLAR_READMEMH - 147)) | (1 << (VerilogParser.DOLLAR_FINISH - 147)) | (1 << (VerilogParser.DOLLAR_STOP - 147)))) != 0) or ((((_la - 247)) & ~0x3f) == 0 and ((1 << (_la - 247)) & ((1 << (VerilogParser.DOLLAR_DUMPFILE - 247)) | (1 << (VerilogParser.DOLLAR_DUMPVARS - 247)) | (1 << (VerilogParser.DOLLAR_DUMPOFF - 247)) | (1 << (VerilogParser.DOLLAR_DUMPON - 247)) | (1 << (VerilogParser.DOLLAR_DUMPALL - 247)) | (1 << (VerilogParser.DOLLAR_DUMPLIMIT - 247)) | (1 << (VerilogParser.DOLLAR_DUMPFLUSH - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTS - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSOFF - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSON - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSALL - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSLIMIT - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSFLUSH - 247)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 247)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 247)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 247)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 247)) | (1 << (VerilogParser.LEFT_BRACE - 247)))) != 0) or ((((_la - 335)) & ~0x3f) == 0 and ((1 << (_la - 335)) & ((1 << (VerilogParser.AT - 335)) | (1 << (VerilogParser.HASH - 335)) | (1 << (VerilogParser.MINUS_GREATER_THAN - 335)))) != 0):
                self.state = 2967
                self.statement()
                self.state = 2972
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2973
            self.match(VerilogParser.JOIN)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Seq_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def BEGIN(self):
            return self.getToken(VerilogParser.BEGIN, 0)

        def END(self):
            return self.getToken(VerilogParser.END, 0)

        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def block_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Block_identifierContext,0)


        def statement(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.StatementContext)
            else:
                return self.getTypedRuleContext(VerilogParser.StatementContext,i)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_seq_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSeq_block" ):
                listener.enterSeq_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSeq_block" ):
                listener.exitSeq_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSeq_block" ):
                return visitor.visitSeq_block(self)
            else:
                return visitor.visitChildren(self)




    def seq_block(self):

        localctx = VerilogParser.Seq_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 424, self.RULE_seq_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2975
            self.match(VerilogParser.BEGIN)
            self.state = 2984
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.COLON:
                self.state = 2976
                self.match(VerilogParser.COLON)
                self.state = 2977
                self.block_identifier()
                self.state = 2981
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,296,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2978
                        self.block_item_declaration() 
                    self.state = 2983
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,296,self._ctx)



            self.state = 2989
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << VerilogParser.ASSIGN) | (1 << VerilogParser.BEGIN) | (1 << VerilogParser.CASE) | (1 << VerilogParser.CASEX) | (1 << VerilogParser.CASEZ) | (1 << VerilogParser.DEASSIGN) | (1 << VerilogParser.DISABLE) | (1 << VerilogParser.FOR) | (1 << VerilogParser.FORCE) | (1 << VerilogParser.FOREVER) | (1 << VerilogParser.FORK) | (1 << VerilogParser.IF))) != 0) or ((((_la - 83)) & ~0x3f) == 0 and ((1 << (_la - 83)) & ((1 << (VerilogParser.RELEASE - 83)) | (1 << (VerilogParser.REPEAT - 83)) | (1 << (VerilogParser.WAIT - 83)) | (1 << (VerilogParser.WHILE - 83)) | (1 << (VerilogParser.DOLLAR_DISPLAY - 83)) | (1 << (VerilogParser.DOLLAR_DISPLAYB - 83)) | (1 << (VerilogParser.DOLLAR_DISPLAYH - 83)) | (1 << (VerilogParser.DOLLAR_DISPLAYO - 83)) | (1 << (VerilogParser.DOLLAR_WRITE - 83)) | (1 << (VerilogParser.DOLLAR_WRITEB - 83)) | (1 << (VerilogParser.DOLLAR_WRITEH - 83)) | (1 << (VerilogParser.DOLLAR_WRITEO - 83)) | (1 << (VerilogParser.DOLLAR_STROBE - 83)) | (1 << (VerilogParser.DOLLAR_STROBEB - 83)) | (1 << (VerilogParser.DOLLAR_STROBEH - 83)) | (1 << (VerilogParser.DOLLAR_STROBEO - 83)) | (1 << (VerilogParser.DOLLAR_MONITOR - 83)) | (1 << (VerilogParser.DOLLAR_MONITORB - 83)) | (1 << (VerilogParser.DOLLAR_MONITORH - 83)) | (1 << (VerilogParser.DOLLAR_MONITORO - 83)) | (1 << (VerilogParser.DOLLAR_MONITOROFF - 83)) | (1 << (VerilogParser.DOLLAR_MONITORON - 83)) | (1 << (VerilogParser.DOLLAR_FCLOSE - 83)) | (1 << (VerilogParser.DOLLAR_FDISPLAY - 83)) | (1 << (VerilogParser.DOLLAR_FDISPLAYB - 83)) | (1 << (VerilogParser.DOLLAR_FDISPLAYH - 83)))) != 0) or ((((_la - 147)) & ~0x3f) == 0 and ((1 << (_la - 147)) & ((1 << (VerilogParser.DOLLAR_FDISPLAYO - 147)) | (1 << (VerilogParser.DOLLAR_FSTROBE - 147)) | (1 << (VerilogParser.DOLLAR_FSTROBEB - 147)) | (1 << (VerilogParser.DOLLAR_FSTROBEH - 147)) | (1 << (VerilogParser.DOLLAR_FSTROBEO - 147)) | (1 << (VerilogParser.DOLLAR_FWRITE - 147)) | (1 << (VerilogParser.DOLLAR_FWRITEB - 147)) | (1 << (VerilogParser.DOLLAR_FWRITEH - 147)) | (1 << (VerilogParser.DOLLAR_FWRITEO - 147)) | (1 << (VerilogParser.DOLLAR_FMONITOR - 147)) | (1 << (VerilogParser.DOLLAR_FMONITORB - 147)) | (1 << (VerilogParser.DOLLAR_FMONITORH - 147)) | (1 << (VerilogParser.DOLLAR_FMONITORO - 147)) | (1 << (VerilogParser.DOLLAR_READMEMB - 147)) | (1 << (VerilogParser.DOLLAR_READMEMH - 147)) | (1 << (VerilogParser.DOLLAR_FINISH - 147)) | (1 << (VerilogParser.DOLLAR_STOP - 147)))) != 0) or ((((_la - 247)) & ~0x3f) == 0 and ((1 << (_la - 247)) & ((1 << (VerilogParser.DOLLAR_DUMPFILE - 247)) | (1 << (VerilogParser.DOLLAR_DUMPVARS - 247)) | (1 << (VerilogParser.DOLLAR_DUMPOFF - 247)) | (1 << (VerilogParser.DOLLAR_DUMPON - 247)) | (1 << (VerilogParser.DOLLAR_DUMPALL - 247)) | (1 << (VerilogParser.DOLLAR_DUMPLIMIT - 247)) | (1 << (VerilogParser.DOLLAR_DUMPFLUSH - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTS - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSOFF - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSON - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSALL - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSLIMIT - 247)) | (1 << (VerilogParser.DOLLAR_DUMPPORTSFLUSH - 247)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 247)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 247)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 247)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 247)) | (1 << (VerilogParser.LEFT_BRACE - 247)))) != 0) or ((((_la - 335)) & ~0x3f) == 0 and ((1 << (_la - 335)) & ((1 << (VerilogParser.AT - 335)) | (1 << (VerilogParser.HASH - 335)) | (1 << (VerilogParser.MINUS_GREATER_THAN - 335)))) != 0):
                self.state = 2986
                self.statement()
                self.state = 2991
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2992
            self.match(VerilogParser.END)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class StatementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def blocking_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Blocking_assignmentContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def case_statement(self):
            return self.getTypedRuleContext(VerilogParser.Case_statementContext,0)


        def conditional_statement(self):
            return self.getTypedRuleContext(VerilogParser.Conditional_statementContext,0)


        def disable_statement(self):
            return self.getTypedRuleContext(VerilogParser.Disable_statementContext,0)


        def event_trigger(self):
            return self.getTypedRuleContext(VerilogParser.Event_triggerContext,0)


        def loop_statement(self):
            return self.getTypedRuleContext(VerilogParser.Loop_statementContext,0)


        def nonblocking_assignment(self):
            return self.getTypedRuleContext(VerilogParser.Nonblocking_assignmentContext,0)


        def par_block(self):
            return self.getTypedRuleContext(VerilogParser.Par_blockContext,0)


        def procedural_continuous_assignments(self):
            return self.getTypedRuleContext(VerilogParser.Procedural_continuous_assignmentsContext,0)


        def procedural_timing_control_statement(self):
            return self.getTypedRuleContext(VerilogParser.Procedural_timing_control_statementContext,0)


        def seq_block(self):
            return self.getTypedRuleContext(VerilogParser.Seq_blockContext,0)


        def system_task_enable(self):
            return self.getTypedRuleContext(VerilogParser.System_task_enableContext,0)


        def task_enable(self):
            return self.getTypedRuleContext(VerilogParser.Task_enableContext,0)


        def wait_statement(self):
            return self.getTypedRuleContext(VerilogParser.Wait_statementContext,0)


        def display_tasks(self):
            return self.getTypedRuleContext(VerilogParser.Display_tasksContext,0)


        def strobe_tasks(self):
            return self.getTypedRuleContext(VerilogParser.Strobe_tasksContext,0)


        def monitor_tasks(self):
            return self.getTypedRuleContext(VerilogParser.Monitor_tasksContext,0)


        def file_open_function(self):
            return self.getTypedRuleContext(VerilogParser.File_open_functionContext,0)


        def file_close_task(self):
            return self.getTypedRuleContext(VerilogParser.File_close_taskContext,0)


        def file_output_tasks(self):
            return self.getTypedRuleContext(VerilogParser.File_output_tasksContext,0)


        def load_memory_tasks(self):
            return self.getTypedRuleContext(VerilogParser.Load_memory_tasksContext,0)


        def finish_task(self):
            return self.getTypedRuleContext(VerilogParser.Finish_taskContext,0)


        def stop_task(self):
            return self.getTypedRuleContext(VerilogParser.Stop_taskContext,0)


        def dumpall_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpall_taskContext,0)


        def dumpfile_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpfile_taskContext,0)


        def dumpflush_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpflush_taskContext,0)


        def dumplimit_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumplimit_taskContext,0)


        def dumpoff_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpoff_taskContext,0)


        def dumpon_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpon_taskContext,0)


        def dumpports_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpports_taskContext,0)


        def dumpportsall_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpportsall_taskContext,0)


        def dumpportsflush_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpportsflush_taskContext,0)


        def dumpportslimit_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpportslimit_taskContext,0)


        def dumpportsoff_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpportsoff_taskContext,0)


        def dumpportson_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpportson_taskContext,0)


        def dumpvars_task(self):
            return self.getTypedRuleContext(VerilogParser.Dumpvars_taskContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement" ):
                listener.enterStatement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement" ):
                listener.exitStatement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement" ):
                return visitor.visitStatement(self)
            else:
                return visitor.visitChildren(self)




    def statement(self):

        localctx = VerilogParser.StatementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 426, self.RULE_statement)
        self._la = 0 # Token type
        try:
            self.state = 3120
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,313,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2997
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 2994
                    self.attribute_instance()
                    self.state = 2999
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3000
                self.blocking_assignment()
                self.state = 3001
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3006
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3003
                    self.attribute_instance()
                    self.state = 3008
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3009
                self.case_statement()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3013
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3010
                    self.attribute_instance()
                    self.state = 3015
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3016
                self.conditional_statement()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3020
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3017
                    self.attribute_instance()
                    self.state = 3022
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3023
                self.disable_statement()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 3027
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3024
                    self.attribute_instance()
                    self.state = 3029
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3030
                self.event_trigger()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 3034
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3031
                    self.attribute_instance()
                    self.state = 3036
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3037
                self.loop_statement()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 3041
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3038
                    self.attribute_instance()
                    self.state = 3043
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3044
                self.nonblocking_assignment()
                self.state = 3045
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 3050
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3047
                    self.attribute_instance()
                    self.state = 3052
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3053
                self.par_block()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 3057
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3054
                    self.attribute_instance()
                    self.state = 3059
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3060
                self.procedural_continuous_assignments()
                self.state = 3061
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 3066
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3063
                    self.attribute_instance()
                    self.state = 3068
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3069
                self.procedural_timing_control_statement()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 3073
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3070
                    self.attribute_instance()
                    self.state = 3075
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3076
                self.seq_block()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 3080
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3077
                    self.attribute_instance()
                    self.state = 3082
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3083
                self.system_task_enable()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 3087
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3084
                    self.attribute_instance()
                    self.state = 3089
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3090
                self.task_enable()
                pass

            elif la_ == 14:
                self.enterOuterAlt(localctx, 14)
                self.state = 3094
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3091
                    self.attribute_instance()
                    self.state = 3096
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3097
                self.wait_statement()
                pass

            elif la_ == 15:
                self.enterOuterAlt(localctx, 15)
                self.state = 3098
                self.display_tasks()
                pass

            elif la_ == 16:
                self.enterOuterAlt(localctx, 16)
                self.state = 3099
                self.strobe_tasks()
                pass

            elif la_ == 17:
                self.enterOuterAlt(localctx, 17)
                self.state = 3100
                self.monitor_tasks()
                pass

            elif la_ == 18:
                self.enterOuterAlt(localctx, 18)
                self.state = 3101
                self.file_open_function()
                pass

            elif la_ == 19:
                self.enterOuterAlt(localctx, 19)
                self.state = 3102
                self.file_close_task()
                pass

            elif la_ == 20:
                self.enterOuterAlt(localctx, 20)
                self.state = 3103
                self.file_output_tasks()
                pass

            elif la_ == 21:
                self.enterOuterAlt(localctx, 21)
                self.state = 3104
                self.load_memory_tasks()
                pass

            elif la_ == 22:
                self.enterOuterAlt(localctx, 22)
                self.state = 3105
                self.finish_task()
                pass

            elif la_ == 23:
                self.enterOuterAlt(localctx, 23)
                self.state = 3106
                self.stop_task()
                pass

            elif la_ == 24:
                self.enterOuterAlt(localctx, 24)
                self.state = 3107
                self.dumpall_task()
                pass

            elif la_ == 25:
                self.enterOuterAlt(localctx, 25)
                self.state = 3108
                self.dumpfile_task()
                pass

            elif la_ == 26:
                self.enterOuterAlt(localctx, 26)
                self.state = 3109
                self.dumpflush_task()
                pass

            elif la_ == 27:
                self.enterOuterAlt(localctx, 27)
                self.state = 3110
                self.dumplimit_task()
                pass

            elif la_ == 28:
                self.enterOuterAlt(localctx, 28)
                self.state = 3111
                self.dumpoff_task()
                pass

            elif la_ == 29:
                self.enterOuterAlt(localctx, 29)
                self.state = 3112
                self.dumpon_task()
                pass

            elif la_ == 30:
                self.enterOuterAlt(localctx, 30)
                self.state = 3113
                self.dumpports_task()
                pass

            elif la_ == 31:
                self.enterOuterAlt(localctx, 31)
                self.state = 3114
                self.dumpportsall_task()
                pass

            elif la_ == 32:
                self.enterOuterAlt(localctx, 32)
                self.state = 3115
                self.dumpportsflush_task()
                pass

            elif la_ == 33:
                self.enterOuterAlt(localctx, 33)
                self.state = 3116
                self.dumpportslimit_task()
                pass

            elif la_ == 34:
                self.enterOuterAlt(localctx, 34)
                self.state = 3117
                self.dumpportsoff_task()
                pass

            elif la_ == 35:
                self.enterOuterAlt(localctx, 35)
                self.state = 3118
                self.dumpportson_task()
                pass

            elif la_ == 36:
                self.enterOuterAlt(localctx, 36)
                self.state = 3119
                self.dumpvars_task()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Statement_or_nullContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_statement_or_null

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement_or_null" ):
                listener.enterStatement_or_null(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement_or_null" ):
                listener.exitStatement_or_null(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement_or_null" ):
                return visitor.visitStatement_or_null(self)
            else:
                return visitor.visitChildren(self)




    def statement_or_null(self):

        localctx = VerilogParser.Statement_or_nullContext(self, self._ctx, self.state)
        self.enterRule(localctx, 428, self.RULE_statement_or_null)
        self._la = 0 # Token type
        try:
            self.state = 3130
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,315,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3122
                self.statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3126
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.LEFT_PARENTHESIS:
                    self.state = 3123
                    self.attribute_instance()
                    self.state = 3128
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3129
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_function_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_statement" ):
                listener.enterFunction_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_statement" ):
                listener.exitFunction_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_statement" ):
                return visitor.visitFunction_statement(self)
            else:
                return visitor.visitChildren(self)




    def function_statement(self):

        localctx = VerilogParser.Function_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 430, self.RULE_function_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3132
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_controlContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def HASH(self):
            return self.getToken(VerilogParser.HASH, 0)

        def delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Delay_valueContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_delay_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_control" ):
                listener.enterDelay_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_control" ):
                listener.exitDelay_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_control" ):
                return visitor.visitDelay_control(self)
            else:
                return visitor.visitChildren(self)




    def delay_control(self):

        localctx = VerilogParser.Delay_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 432, self.RULE_delay_control)
        try:
            self.state = 3141
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,316,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3134
                self.match(VerilogParser.HASH)
                self.state = 3135
                self.delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3136
                self.match(VerilogParser.HASH)
                self.state = 3137
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3138
                self.mintypmax_expression()
                self.state = 3139
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_or_event_controlContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_control(self):
            return self.getTypedRuleContext(VerilogParser.Delay_controlContext,0)


        def event_control(self):
            return self.getTypedRuleContext(VerilogParser.Event_controlContext,0)


        def REPEAT(self):
            return self.getToken(VerilogParser.REPEAT, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_delay_or_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_or_event_control" ):
                listener.enterDelay_or_event_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_or_event_control" ):
                listener.exitDelay_or_event_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_or_event_control" ):
                return visitor.visitDelay_or_event_control(self)
            else:
                return visitor.visitChildren(self)




    def delay_or_event_control(self):

        localctx = VerilogParser.Delay_or_event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 434, self.RULE_delay_or_event_control)
        try:
            self.state = 3151
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.HASH]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3143
                self.delay_control()
                pass
            elif token in [VerilogParser.AT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3144
                self.event_control()
                pass
            elif token in [VerilogParser.REPEAT]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3145
                self.match(VerilogParser.REPEAT)
                self.state = 3146
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3147
                self.expression(0)
                self.state = 3148
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3149
                self.event_control()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Disable_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DISABLE(self):
            return self.getToken(VerilogParser.DISABLE, 0)

        def hierarchical_task_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_task_identifierContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def hierarchical_block_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_block_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_disable_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDisable_statement" ):
                listener.enterDisable_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDisable_statement" ):
                listener.exitDisable_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDisable_statement" ):
                return visitor.visitDisable_statement(self)
            else:
                return visitor.visitChildren(self)




    def disable_statement(self):

        localctx = VerilogParser.Disable_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 436, self.RULE_disable_statement)
        try:
            self.state = 3161
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,318,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3153
                self.match(VerilogParser.DISABLE)
                self.state = 3154
                self.hierarchical_task_identifier()
                self.state = 3155
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3157
                self.match(VerilogParser.DISABLE)
                self.state = 3158
                self.hierarchical_block_identifier()
                self.state = 3159
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_controlContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def AT(self):
            return self.getToken(VerilogParser.AT, 0)

        def hierarchical_event_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_event_identifierContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def event_expression(self):
            return self.getTypedRuleContext(VerilogParser.Event_expressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def ASTERISK(self):
            return self.getToken(VerilogParser.ASTERISK, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_control" ):
                listener.enterEvent_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_control" ):
                listener.exitEvent_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_control" ):
                return visitor.visitEvent_control(self)
            else:
                return visitor.visitChildren(self)




    def event_control(self):

        localctx = VerilogParser.Event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 438, self.RULE_event_control)
        try:
            self.state = 3176
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,319,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3163
                self.match(VerilogParser.AT)
                self.state = 3164
                self.hierarchical_event_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3165
                self.match(VerilogParser.AT)
                self.state = 3166
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3167
                self.event_expression(0)
                self.state = 3168
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3170
                self.match(VerilogParser.AT)
                self.state = 3171
                self.match(VerilogParser.ASTERISK)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3172
                self.match(VerilogParser.AT)
                self.state = 3173
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3174
                self.match(VerilogParser.ASTERISK)
                self.state = 3175
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_triggerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def MINUS_GREATER_THAN(self):
            return self.getToken(VerilogParser.MINUS_GREATER_THAN, 0)

        def hierarchical_event_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_event_identifierContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_event_trigger

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_trigger" ):
                listener.enterEvent_trigger(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_trigger" ):
                listener.exitEvent_trigger(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_trigger" ):
                return visitor.visitEvent_trigger(self)
            else:
                return visitor.visitChildren(self)




    def event_trigger(self):

        localctx = VerilogParser.Event_triggerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 440, self.RULE_event_trigger)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3178
            self.match(VerilogParser.MINUS_GREATER_THAN)
            self.state = 3179
            self.hierarchical_event_identifier()
            self.state = 3183
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                self.state = 3180
                self.expression(0)
                self.state = 3185
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3186
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def POSEDGE(self):
            return self.getToken(VerilogParser.POSEDGE, 0)

        def NEGEDGE(self):
            return self.getToken(VerilogParser.NEGEDGE, 0)

        def event_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Event_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Event_expressionContext,i)


        def OR(self):
            return self.getToken(VerilogParser.OR, 0)

        def COMMA(self):
            return self.getToken(VerilogParser.COMMA, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_event_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_expression" ):
                listener.enterEvent_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_expression" ):
                listener.exitEvent_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_expression" ):
                return visitor.visitEvent_expression(self)
            else:
                return visitor.visitChildren(self)



    def event_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.Event_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 442
        self.enterRecursionRule(localctx, 442, self.RULE_event_expression, _p)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3194
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.state = 3189
                self.expression(0)
                pass
            elif token in [VerilogParser.POSEDGE]:
                self.state = 3190
                self.match(VerilogParser.POSEDGE)
                self.state = 3191
                self.expression(0)
                pass
            elif token in [VerilogParser.NEGEDGE]:
                self.state = 3192
                self.match(VerilogParser.NEGEDGE)
                self.state = 3193
                self.expression(0)
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 3204
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,323,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 3202
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,322,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.Event_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_event_expression)
                        self.state = 3196
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 3197
                        self.match(VerilogParser.OR)
                        self.state = 3198
                        self.event_expression(3)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.Event_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_event_expression)
                        self.state = 3199
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 3200
                        self.match(VerilogParser.COMMA)
                        self.state = 3201
                        self.event_expression(2)
                        pass

             
                self.state = 3206
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,323,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Event_primaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def POSEDGE(self):
            return self.getToken(VerilogParser.POSEDGE, 0)

        def NEGEDGE(self):
            return self.getToken(VerilogParser.NEGEDGE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_event_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_primary" ):
                listener.enterEvent_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_primary" ):
                listener.exitEvent_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_primary" ):
                return visitor.visitEvent_primary(self)
            else:
                return visitor.visitChildren(self)




    def event_primary(self):

        localctx = VerilogParser.Event_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 444, self.RULE_event_primary)
        try:
            self.state = 3212
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3207
                self.expression(0)
                pass
            elif token in [VerilogParser.POSEDGE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3208
                self.match(VerilogParser.POSEDGE)
                self.state = 3209
                self.expression(0)
                pass
            elif token in [VerilogParser.NEGEDGE]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3210
                self.match(VerilogParser.NEGEDGE)
                self.state = 3211
                self.expression(0)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_timing_controlContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_control(self):
            return self.getTypedRuleContext(VerilogParser.Delay_controlContext,0)


        def event_control(self):
            return self.getTypedRuleContext(VerilogParser.Event_controlContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_procedural_timing_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_timing_control" ):
                listener.enterProcedural_timing_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_timing_control" ):
                listener.exitProcedural_timing_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_timing_control" ):
                return visitor.visitProcedural_timing_control(self)
            else:
                return visitor.visitChildren(self)




    def procedural_timing_control(self):

        localctx = VerilogParser.Procedural_timing_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 446, self.RULE_procedural_timing_control)
        try:
            self.state = 3216
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.HASH]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3214
                self.delay_control()
                pass
            elif token in [VerilogParser.AT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3215
                self.event_control()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_timing_control_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def procedural_timing_control(self):
            return self.getTypedRuleContext(VerilogParser.Procedural_timing_controlContext,0)


        def statement_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_procedural_timing_control_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_timing_control_statement" ):
                listener.enterProcedural_timing_control_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_timing_control_statement" ):
                listener.exitProcedural_timing_control_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_timing_control_statement" ):
                return visitor.visitProcedural_timing_control_statement(self)
            else:
                return visitor.visitChildren(self)




    def procedural_timing_control_statement(self):

        localctx = VerilogParser.Procedural_timing_control_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 448, self.RULE_procedural_timing_control_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3218
            self.procedural_timing_control()
            self.state = 3219
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Wait_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def WAIT(self):
            return self.getToken(VerilogParser.WAIT, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_wait_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWait_statement" ):
                listener.enterWait_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWait_statement" ):
                listener.exitWait_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWait_statement" ):
                return visitor.visitWait_statement(self)
            else:
                return visitor.visitChildren(self)




    def wait_statement(self):

        localctx = VerilogParser.Wait_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 450, self.RULE_wait_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3221
            self.match(VerilogParser.WAIT)
            self.state = 3222
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3223
            self.expression(0)
            self.state = 3224
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 3225
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Conditional_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def IF(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.IF)
            else:
                return self.getToken(VerilogParser.IF, i)

        def LEFT_PARENTHESIS(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LEFT_PARENTHESIS)
            else:
                return self.getToken(VerilogParser.LEFT_PARENTHESIS, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RIGHT_PARENTHESIS(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RIGHT_PARENTHESIS)
            else:
                return self.getToken(VerilogParser.RIGHT_PARENTHESIS, i)

        def statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Statement_or_nullContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,i)


        def ELSE(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.ELSE)
            else:
                return self.getToken(VerilogParser.ELSE, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_conditional_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConditional_statement" ):
                listener.enterConditional_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConditional_statement" ):
                listener.exitConditional_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConditional_statement" ):
                return visitor.visitConditional_statement(self)
            else:
                return visitor.visitChildren(self)




    def conditional_statement(self):

        localctx = VerilogParser.Conditional_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 452, self.RULE_conditional_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3227
            self.match(VerilogParser.IF)
            self.state = 3228
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3229
            self.expression(0)
            self.state = 3230
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 3231
            self.statement_or_null()
            self.state = 3241
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,326,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3232
                    self.match(VerilogParser.ELSE)
                    self.state = 3233
                    self.match(VerilogParser.IF)
                    self.state = 3234
                    self.match(VerilogParser.LEFT_PARENTHESIS)
                    self.state = 3235
                    self.expression(0)
                    self.state = 3236
                    self.match(VerilogParser.RIGHT_PARENTHESIS)
                    self.state = 3237
                    self.statement_or_null() 
                self.state = 3243
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,326,self._ctx)

            self.state = 3246
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,327,self._ctx)
            if la_ == 1:
                self.state = 3244
                self.match(VerilogParser.ELSE)
                self.state = 3245
                self.statement_or_null()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def CASE(self):
            return self.getToken(VerilogParser.CASE, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def case_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Case_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Case_itemContext,i)


        def ENDCASE(self):
            return self.getToken(VerilogParser.ENDCASE, 0)

        def CASEZ(self):
            return self.getToken(VerilogParser.CASEZ, 0)

        def CASEX(self):
            return self.getToken(VerilogParser.CASEX, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_case_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_statement" ):
                listener.enterCase_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_statement" ):
                listener.exitCase_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_statement" ):
                return visitor.visitCase_statement(self)
            else:
                return visitor.visitChildren(self)




    def case_statement(self):

        localctx = VerilogParser.Case_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 454, self.RULE_case_statement)
        self._la = 0 # Token type
        try:
            self.state = 3287
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.CASE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3248
                self.match(VerilogParser.CASE)
                self.state = 3249
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3250
                self.expression(0)
                self.state = 3251
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3252
                self.case_item()
                self.state = 3256
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.DEFAULT or ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                    self.state = 3253
                    self.case_item()
                    self.state = 3258
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3259
                self.match(VerilogParser.ENDCASE)
                pass
            elif token in [VerilogParser.CASEZ]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3261
                self.match(VerilogParser.CASEZ)
                self.state = 3262
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3263
                self.expression(0)
                self.state = 3264
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3265
                self.case_item()
                self.state = 3269
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.DEFAULT or ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                    self.state = 3266
                    self.case_item()
                    self.state = 3271
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3272
                self.match(VerilogParser.ENDCASE)
                pass
            elif token in [VerilogParser.CASEX]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3274
                self.match(VerilogParser.CASEX)
                self.state = 3275
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3276
                self.expression(0)
                self.state = 3277
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3278
                self.case_item()
                self.state = 3282
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.DEFAULT or ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                    self.state = 3279
                    self.case_item()
                    self.state = 3284
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3285
                self.match(VerilogParser.ENDCASE)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(VerilogParser.Statement_or_nullContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def DEFAULT(self):
            return self.getToken(VerilogParser.DEFAULT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_case_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_item" ):
                listener.enterCase_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_item" ):
                listener.exitCase_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_item" ):
                return visitor.visitCase_item(self)
            else:
                return visitor.visitChildren(self)




    def case_item(self):

        localctx = VerilogParser.Case_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 456, self.RULE_case_item)
        self._la = 0 # Token type
        try:
            self.state = 3305
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE, VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3289
                self.expression(0)
                self.state = 3294
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 3290
                    self.match(VerilogParser.COMMA)
                    self.state = 3291
                    self.expression(0)
                    self.state = 3296
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3297
                self.match(VerilogParser.COLON)
                self.state = 3298
                self.statement_or_null()
                pass
            elif token in [VerilogParser.DEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3300
                self.match(VerilogParser.DEFAULT)
                self.state = 3302
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.COLON:
                    self.state = 3301
                    self.match(VerilogParser.COLON)


                self.state = 3304
                self.statement_or_null()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def FOREVER(self):
            return self.getToken(VerilogParser.FOREVER, 0)

        def statement(self):
            return self.getTypedRuleContext(VerilogParser.StatementContext,0)


        def REPEAT(self):
            return self.getToken(VerilogParser.REPEAT, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def WHILE(self):
            return self.getToken(VerilogParser.WHILE, 0)

        def FOR(self):
            return self.getToken(VerilogParser.FOR, 0)

        def variable_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Variable_assignmentContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Variable_assignmentContext,i)


        def SEMICOLON(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.SEMICOLON)
            else:
                return self.getToken(VerilogParser.SEMICOLON, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_statement" ):
                listener.enterLoop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_statement" ):
                listener.exitLoop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_statement" ):
                return visitor.visitLoop_statement(self)
            else:
                return visitor.visitChildren(self)




    def loop_statement(self):

        localctx = VerilogParser.Loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 458, self.RULE_loop_statement)
        try:
            self.state = 3331
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.FOREVER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3307
                self.match(VerilogParser.FOREVER)
                self.state = 3308
                self.statement()
                pass
            elif token in [VerilogParser.REPEAT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3309
                self.match(VerilogParser.REPEAT)
                self.state = 3310
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3311
                self.expression(0)
                self.state = 3312
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3313
                self.statement()
                pass
            elif token in [VerilogParser.WHILE]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3315
                self.match(VerilogParser.WHILE)
                self.state = 3316
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3317
                self.expression(0)
                self.state = 3318
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3319
                self.statement()
                pass
            elif token in [VerilogParser.FOR]:
                self.enterOuterAlt(localctx, 4)
                self.state = 3321
                self.match(VerilogParser.FOR)
                self.state = 3322
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3323
                self.variable_assignment()
                self.state = 3324
                self.match(VerilogParser.SEMICOLON)
                self.state = 3325
                self.expression(0)
                self.state = 3326
                self.match(VerilogParser.SEMICOLON)
                self.state = 3327
                self.variable_assignment()
                self.state = 3328
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3329
                self.statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_task_enableContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def system_task_identifier(self):
            return self.getTypedRuleContext(VerilogParser.System_task_identifierContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_system_task_enable

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_task_enable" ):
                listener.enterSystem_task_enable(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_task_enable" ):
                listener.exitSystem_task_enable(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_task_enable" ):
                return visitor.visitSystem_task_enable(self)
            else:
                return visitor.visitChildren(self)




    def system_task_enable(self):

        localctx = VerilogParser.System_task_enableContext(self, self._ctx, self.state)
        self.enterRule(localctx, 460, self.RULE_system_task_enable)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3333
            self.system_task_identifier()
            self.state = 3348
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 3334
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3336
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                    self.state = 3335
                    self.expression(0)


                self.state = 3344
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 3338
                    self.match(VerilogParser.COMMA)
                    self.state = 3340
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if ((((_la - 209)) & ~0x3f) == 0 and ((1 << (_la - 209)) & ((1 << (VerilogParser.DOLLAR_BITSTOREAL - 209)) | (1 << (VerilogParser.DOLLAR_ITOR - 209)) | (1 << (VerilogParser.DOLLAR_SIGNED - 209)) | (1 << (VerilogParser.DOLLAR_REALTOBITS - 209)) | (1 << (VerilogParser.DOLLAR_RTOI - 209)) | (1 << (VerilogParser.DOLLAR_UNSIGNED - 209)) | (1 << (VerilogParser.DOLLAR_RANDOM - 209)) | (1 << (VerilogParser.DOLLAR_DIST_ERLANG - 209)) | (1 << (VerilogParser.DOLLAR_DIST_NORMAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_T - 209)) | (1 << (VerilogParser.DOLLAR_DIST_CHI_SQUARE - 209)) | (1 << (VerilogParser.DOLLAR_DIST_EXPONENTIAL - 209)) | (1 << (VerilogParser.DOLLAR_DIST_POISSON - 209)) | (1 << (VerilogParser.DOLLAR_DIST_UNIFORM - 209)) | (1 << (VerilogParser.DOLLAR_CLOG2 - 209)) | (1 << (VerilogParser.DOLLAR_LN - 209)) | (1 << (VerilogParser.DOLLAR_LOG10 - 209)) | (1 << (VerilogParser.DOLLAR_EXP - 209)) | (1 << (VerilogParser.DOLLAR_SQRT - 209)) | (1 << (VerilogParser.DOLLAR_POW - 209)) | (1 << (VerilogParser.DOLLAR_FLOOR - 209)) | (1 << (VerilogParser.DOLLAR_CEIL - 209)) | (1 << (VerilogParser.DOLLAR_SIN - 209)) | (1 << (VerilogParser.DOLLAR_COS - 209)) | (1 << (VerilogParser.DOLLAR_TAN - 209)) | (1 << (VerilogParser.DOLLAR_ASIN - 209)) | (1 << (VerilogParser.DOLLAR_ACOS - 209)) | (1 << (VerilogParser.DOLLAR_ATAN - 209)) | (1 << (VerilogParser.DOLLAR_ATAN2 - 209)) | (1 << (VerilogParser.DOLLAR_HYPOT - 209)) | (1 << (VerilogParser.DOLLAR_SINH - 209)) | (1 << (VerilogParser.DOLLAR_COSH - 209)) | (1 << (VerilogParser.DOLLAR_TANH - 209)) | (1 << (VerilogParser.DOLLAR_ASINH - 209)) | (1 << (VerilogParser.DOLLAR_ACOSH - 209)) | (1 << (VerilogParser.DOLLAR_ATANH - 209)))) != 0) or ((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)) | (1 << (VerilogParser.STRING - 282)) | (1 << (VerilogParser.ESCAPED_IDENTIFIER - 282)) | (1 << (VerilogParser.SIMPLE_IDENTIFIER - 282)) | (1 << (VerilogParser.SYSTEM_TF_IDENTIFIER - 282)) | (1 << (VerilogParser.LEFT_PARENTHESIS - 282)) | (1 << (VerilogParser.LEFT_BRACE - 282)) | (1 << (VerilogParser.PLUS - 282)) | (1 << (VerilogParser.MINUS - 282)) | (1 << (VerilogParser.EXCLAMATION_MARK - 282)) | (1 << (VerilogParser.TILDE - 282)) | (1 << (VerilogParser.AMPERSAND - 282)) | (1 << (VerilogParser.TILDE_AMPERSAND - 282)) | (1 << (VerilogParser.VERTICAL_BAR - 282)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 282)) | (1 << (VerilogParser.CARET - 282)) | (1 << (VerilogParser.TILDE_CARET - 282)) | (1 << (VerilogParser.CARET_TILDE - 282)))) != 0):
                        self.state = 3339
                        self.expression(0)


                    self.state = 3346
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3347
                self.match(VerilogParser.RIGHT_PARENTHESIS)


            self.state = 3350
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_enableContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_task_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_task_identifierContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_task_enable

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_enable" ):
                listener.enterTask_enable(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_enable" ):
                listener.exitTask_enable(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_enable" ):
                return visitor.visitTask_enable(self)
            else:
                return visitor.visitChildren(self)




    def task_enable(self):

        localctx = VerilogParser.Task_enableContext(self, self._ctx, self.state)
        self.enterRule(localctx, 462, self.RULE_task_enable)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3352
            self.hierarchical_task_identifier()
            self.state = 3364
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 3353
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3354
                self.expression(0)
                self.state = 3359
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 3355
                    self.match(VerilogParser.COMMA)
                    self.state = 3356
                    self.expression(0)
                    self.state = 3361
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3362
                self.match(VerilogParser.RIGHT_PARENTHESIS)


            self.state = 3366
            self.match(VerilogParser.SEMICOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specify_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SPECIFY(self):
            return self.getToken(VerilogParser.SPECIFY, 0)

        def ENDSPECIFY(self):
            return self.getToken(VerilogParser.ENDSPECIFY, 0)

        def specify_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Specify_itemContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Specify_itemContext,i)


        def getRuleIndex(self):
            return VerilogParser.RULE_specify_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_block" ):
                listener.enterSpecify_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_block" ):
                listener.exitSpecify_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_block" ):
                return visitor.visitSpecify_block(self)
            else:
                return visitor.visitChildren(self)




    def specify_block(self):

        localctx = VerilogParser.Specify_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 464, self.RULE_specify_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3368
            self.match(VerilogParser.SPECIFY)
            self.state = 3372
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 42)) & ~0x3f) == 0 and ((1 << (_la - 42)) & ((1 << (VerilogParser.IF - 42)) | (1 << (VerilogParser.IFNONE - 42)) | (1 << (VerilogParser.NOSHOWCANCELLED - 42)) | (1 << (VerilogParser.PULSESTYLE_ONEVENT - 42)) | (1 << (VerilogParser.PULSESTYLE_ONDETECT - 42)) | (1 << (VerilogParser.SHOWCANCELLED - 42)) | (1 << (VerilogParser.SPECPARAM - 42)))) != 0) or _la==VerilogParser.LEFT_PARENTHESIS:
                self.state = 3369
                self.specify_item()
                self.state = 3374
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3375
            self.match(VerilogParser.ENDSPECIFY)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specify_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Specparam_declarationContext,0)


        def pulsestyle_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Pulsestyle_declarationContext,0)


        def showcancelled_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Showcancelled_declarationContext,0)


        def path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Path_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specify_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_item" ):
                listener.enterSpecify_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_item" ):
                listener.exitSpecify_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_item" ):
                return visitor.visitSpecify_item(self)
            else:
                return visitor.visitChildren(self)




    def specify_item(self):

        localctx = VerilogParser.Specify_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 466, self.RULE_specify_item)
        try:
            self.state = 3381
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.SPECPARAM]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3377
                self.specparam_declaration()
                pass
            elif token in [VerilogParser.PULSESTYLE_ONEVENT, VerilogParser.PULSESTYLE_ONDETECT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3378
                self.pulsestyle_declaration()
                pass
            elif token in [VerilogParser.NOSHOWCANCELLED, VerilogParser.SHOWCANCELLED]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3379
                self.showcancelled_declaration()
                pass
            elif token in [VerilogParser.IF, VerilogParser.IFNONE, VerilogParser.LEFT_PARENTHESIS]:
                self.enterOuterAlt(localctx, 4)
                self.state = 3380
                self.path_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pulsestyle_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PULSESTYLE_ONEVENT(self):
            return self.getToken(VerilogParser.PULSESTYLE_ONEVENT, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_outputsContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def PULSESTYLE_ONDETECT(self):
            return self.getToken(VerilogParser.PULSESTYLE_ONDETECT, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_pulsestyle_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulsestyle_declaration" ):
                listener.enterPulsestyle_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulsestyle_declaration" ):
                listener.exitPulsestyle_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulsestyle_declaration" ):
                return visitor.visitPulsestyle_declaration(self)
            else:
                return visitor.visitChildren(self)




    def pulsestyle_declaration(self):

        localctx = VerilogParser.Pulsestyle_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 468, self.RULE_pulsestyle_declaration)
        try:
            self.state = 3391
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.PULSESTYLE_ONEVENT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3383
                self.match(VerilogParser.PULSESTYLE_ONEVENT)
                self.state = 3384
                self.list_of_path_outputs()
                self.state = 3385
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.PULSESTYLE_ONDETECT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3387
                self.match(VerilogParser.PULSESTYLE_ONDETECT)
                self.state = 3388
                self.list_of_path_outputs()
                self.state = 3389
                self.match(VerilogParser.SEMICOLON)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Showcancelled_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SHOWCANCELLED(self):
            return self.getToken(VerilogParser.SHOWCANCELLED, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_outputsContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def NOSHOWCANCELLED(self):
            return self.getToken(VerilogParser.NOSHOWCANCELLED, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_showcancelled_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterShowcancelled_declaration" ):
                listener.enterShowcancelled_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitShowcancelled_declaration" ):
                listener.exitShowcancelled_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitShowcancelled_declaration" ):
                return visitor.visitShowcancelled_declaration(self)
            else:
                return visitor.visitChildren(self)




    def showcancelled_declaration(self):

        localctx = VerilogParser.Showcancelled_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 470, self.RULE_showcancelled_declaration)
        try:
            self.state = 3401
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.SHOWCANCELLED]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3393
                self.match(VerilogParser.SHOWCANCELLED)
                self.state = 3394
                self.list_of_path_outputs()
                self.state = 3395
                self.match(VerilogParser.SEMICOLON)
                pass
            elif token in [VerilogParser.NOSHOWCANCELLED]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3397
                self.match(VerilogParser.NOSHOWCANCELLED)
                self.state = 3398
                self.list_of_path_outputs()
                self.state = 3399
                self.match(VerilogParser.SEMICOLON)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Path_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def simple_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Simple_path_declarationContext,0)


        def SEMICOLON(self):
            return self.getToken(VerilogParser.SEMICOLON, 0)

        def edge_sensitive_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Edge_sensitive_path_declarationContext,0)


        def state_dependent_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.State_dependent_path_declarationContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_declaration" ):
                listener.enterPath_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_declaration" ):
                listener.exitPath_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_declaration" ):
                return visitor.visitPath_declaration(self)
            else:
                return visitor.visitChildren(self)




    def path_declaration(self):

        localctx = VerilogParser.Path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 472, self.RULE_path_declaration)
        try:
            self.state = 3412
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,346,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3403
                self.simple_path_declaration()
                self.state = 3404
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3406
                self.edge_sensitive_path_declaration()
                self.state = 3407
                self.match(VerilogParser.SEMICOLON)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3409
                self.state_dependent_path_declaration()
                self.state = 3410
                self.match(VerilogParser.SEMICOLON)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Simple_path_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parallel_path_description(self):
            return self.getTypedRuleContext(VerilogParser.Parallel_path_descriptionContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def path_delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_valueContext,0)


        def full_path_description(self):
            return self.getTypedRuleContext(VerilogParser.Full_path_descriptionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_simple_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_path_declaration" ):
                listener.enterSimple_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_path_declaration" ):
                listener.exitSimple_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_path_declaration" ):
                return visitor.visitSimple_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def simple_path_declaration(self):

        localctx = VerilogParser.Simple_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 474, self.RULE_simple_path_declaration)
        try:
            self.state = 3422
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,347,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3414
                self.parallel_path_description()
                self.state = 3415
                self.match(VerilogParser.EQUAL)
                self.state = 3416
                self.path_delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3418
                self.full_path_description()
                self.state = 3419
                self.match(VerilogParser.EQUAL)
                self.state = 3420
                self.path_delay_value()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parallel_path_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,0)


        def EQUAL_GREATER_THAN(self):
            return self.getToken(VerilogParser.EQUAL_GREATER_THAN, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def polarity_operator(self):
            return self.getTypedRuleContext(VerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_parallel_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParallel_path_description" ):
                listener.enterParallel_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParallel_path_description" ):
                listener.exitParallel_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParallel_path_description" ):
                return visitor.visitParallel_path_description(self)
            else:
                return visitor.visitChildren(self)




    def parallel_path_description(self):

        localctx = VerilogParser.Parallel_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 476, self.RULE_parallel_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3424
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3425
            self.specify_input_terminal_descriptor()
            self.state = 3427
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.PLUS or _la==VerilogParser.MINUS:
                self.state = 3426
                self.polarity_operator()


            self.state = 3429
            self.match(VerilogParser.EQUAL_GREATER_THAN)
            self.state = 3430
            self.specify_output_terminal_descriptor()
            self.state = 3431
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Full_path_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def list_of_path_inputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_inputsContext,0)


        def ASTERISK_GREATER_THAN(self):
            return self.getToken(VerilogParser.ASTERISK_GREATER_THAN, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_outputsContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def polarity_operator(self):
            return self.getTypedRuleContext(VerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_full_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFull_path_description" ):
                listener.enterFull_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFull_path_description" ):
                listener.exitFull_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFull_path_description" ):
                return visitor.visitFull_path_description(self)
            else:
                return visitor.visitChildren(self)




    def full_path_description(self):

        localctx = VerilogParser.Full_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 478, self.RULE_full_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3433
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3434
            self.list_of_path_inputs()
            self.state = 3436
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.PLUS or _la==VerilogParser.MINUS:
                self.state = 3435
                self.polarity_operator()


            self.state = 3438
            self.match(VerilogParser.ASTERISK_GREATER_THAN)
            self.state = 3439
            self.list_of_path_outputs()
            self.state = 3440
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_path_inputsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specify_input_terminal_descriptor(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Specify_input_terminal_descriptorContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_path_inputs

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_inputs" ):
                listener.enterList_of_path_inputs(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_inputs" ):
                listener.exitList_of_path_inputs(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_inputs" ):
                return visitor.visitList_of_path_inputs(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_inputs(self):

        localctx = VerilogParser.List_of_path_inputsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 480, self.RULE_list_of_path_inputs)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3442
            self.specify_input_terminal_descriptor()
            self.state = 3447
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 3443
                self.match(VerilogParser.COMMA)
                self.state = 3444
                self.specify_input_terminal_descriptor()
                self.state = 3449
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_path_outputsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specify_output_terminal_descriptor(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Specify_output_terminal_descriptorContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_path_outputs

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_outputs" ):
                listener.enterList_of_path_outputs(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_outputs" ):
                listener.exitList_of_path_outputs(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_outputs" ):
                return visitor.visitList_of_path_outputs(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_outputs(self):

        localctx = VerilogParser.List_of_path_outputsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 482, self.RULE_list_of_path_outputs)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3450
            self.specify_output_terminal_descriptor()
            self.state = 3455
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 3451
                self.match(VerilogParser.COMMA)
                self.state = 3452
                self.specify_output_terminal_descriptor()
                self.state = 3457
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specify_input_terminal_descriptorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def input_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Input_identifierContext,0)


        def LEFT_BRACKET(self):
            return self.getToken(VerilogParser.LEFT_BRACKET, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RIGHT_BRACKET(self):
            return self.getToken(VerilogParser.RIGHT_BRACKET, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_specify_input_terminal_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_input_terminal_descriptor" ):
                listener.enterSpecify_input_terminal_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_input_terminal_descriptor" ):
                listener.exitSpecify_input_terminal_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_input_terminal_descriptor" ):
                return visitor.visitSpecify_input_terminal_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def specify_input_terminal_descriptor(self):

        localctx = VerilogParser.Specify_input_terminal_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 484, self.RULE_specify_input_terminal_descriptor)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3458
            self.input_identifier()
            self.state = 3463
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 3459
                self.match(VerilogParser.LEFT_BRACKET)
                self.state = 3460
                self.constant_range_expression()
                self.state = 3461
                self.match(VerilogParser.RIGHT_BRACKET)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specify_output_terminal_descriptorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def output_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Output_identifierContext,0)


        def LEFT_BRACKET(self):
            return self.getToken(VerilogParser.LEFT_BRACKET, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RIGHT_BRACKET(self):
            return self.getToken(VerilogParser.RIGHT_BRACKET, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_specify_output_terminal_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_output_terminal_descriptor" ):
                listener.enterSpecify_output_terminal_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_output_terminal_descriptor" ):
                listener.exitSpecify_output_terminal_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_output_terminal_descriptor" ):
                return visitor.visitSpecify_output_terminal_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def specify_output_terminal_descriptor(self):

        localctx = VerilogParser.Specify_output_terminal_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 486, self.RULE_specify_output_terminal_descriptor)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3465
            self.output_identifier()
            self.state = 3470
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.LEFT_BRACKET:
                self.state = 3466
                self.match(VerilogParser.LEFT_BRACKET)
                self.state = 3467
                self.constant_range_expression()
                self.state = 3468
                self.match(VerilogParser.RIGHT_BRACKET)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def input_port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Input_port_identifierContext,0)


        def inout_port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Inout_port_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_input_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_identifier" ):
                listener.enterInput_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_identifier" ):
                listener.exitInput_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_identifier" ):
                return visitor.visitInput_identifier(self)
            else:
                return visitor.visitChildren(self)




    def input_identifier(self):

        localctx = VerilogParser.Input_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 488, self.RULE_input_identifier)
        try:
            self.state = 3474
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,354,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3472
                self.input_port_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3473
                self.inout_port_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def output_port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Output_port_identifierContext,0)


        def inout_port_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Inout_port_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_output_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_identifier" ):
                listener.enterOutput_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_identifier" ):
                listener.exitOutput_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_identifier" ):
                return visitor.visitOutput_identifier(self)
            else:
                return visitor.visitChildren(self)




    def output_identifier(self):

        localctx = VerilogParser.Output_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 490, self.RULE_output_identifier)
        try:
            self.state = 3478
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,355,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3476
                self.output_port_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3477
                self.inout_port_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Path_delay_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_path_delay_expressions(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_delay_expressionsContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_path_delay_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_delay_value" ):
                listener.enterPath_delay_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_delay_value" ):
                listener.exitPath_delay_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_delay_value" ):
                return visitor.visitPath_delay_value(self)
            else:
                return visitor.visitChildren(self)




    def path_delay_value(self):

        localctx = VerilogParser.Path_delay_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 492, self.RULE_path_delay_value)
        try:
            self.state = 3485
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,356,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3480
                self.list_of_path_delay_expressions()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3481
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3482
                self.list_of_path_delay_expressions()
                self.state = 3483
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_path_delay_expressionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def t_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T_path_delay_expressionContext,0)


        def trise_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Trise_path_delay_expressionContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def tfall_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tfall_path_delay_expressionContext,0)


        def tz_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tz_path_delay_expressionContext,0)


        def t01_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T01_path_delay_expressionContext,0)


        def t10_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T10_path_delay_expressionContext,0)


        def t0z_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T0z_path_delay_expressionContext,0)


        def tz1_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tz1_path_delay_expressionContext,0)


        def t1z_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T1z_path_delay_expressionContext,0)


        def tz0_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tz0_path_delay_expressionContext,0)


        def t0x_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T0x_path_delay_expressionContext,0)


        def tx1_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tx1_path_delay_expressionContext,0)


        def t1x_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.T1x_path_delay_expressionContext,0)


        def tx0_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tx0_path_delay_expressionContext,0)


        def txz_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Txz_path_delay_expressionContext,0)


        def tzx_path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Tzx_path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_list_of_path_delay_expressions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_delay_expressions" ):
                listener.enterList_of_path_delay_expressions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_delay_expressions" ):
                listener.exitList_of_path_delay_expressions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_delay_expressions" ):
                return visitor.visitList_of_path_delay_expressions(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_delay_expressions(self):

        localctx = VerilogParser.List_of_path_delay_expressionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 494, self.RULE_list_of_path_delay_expressions)
        try:
            self.state = 3534
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,357,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3487
                self.t_path_delay_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3488
                self.trise_path_delay_expression()
                self.state = 3489
                self.match(VerilogParser.COMMA)
                self.state = 3490
                self.tfall_path_delay_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3492
                self.trise_path_delay_expression()
                self.state = 3493
                self.match(VerilogParser.COMMA)
                self.state = 3494
                self.tfall_path_delay_expression()
                self.state = 3495
                self.match(VerilogParser.COMMA)
                self.state = 3496
                self.tz_path_delay_expression()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3498
                self.t01_path_delay_expression()
                self.state = 3499
                self.match(VerilogParser.COMMA)
                self.state = 3500
                self.t10_path_delay_expression()
                self.state = 3501
                self.match(VerilogParser.COMMA)
                self.state = 3502
                self.t0z_path_delay_expression()
                self.state = 3503
                self.match(VerilogParser.COMMA)
                self.state = 3504
                self.tz1_path_delay_expression()
                self.state = 3505
                self.match(VerilogParser.COMMA)
                self.state = 3506
                self.t1z_path_delay_expression()
                self.state = 3507
                self.match(VerilogParser.COMMA)
                self.state = 3508
                self.tz0_path_delay_expression()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 3510
                self.t01_path_delay_expression()
                self.state = 3511
                self.match(VerilogParser.COMMA)
                self.state = 3512
                self.t10_path_delay_expression()
                self.state = 3513
                self.match(VerilogParser.COMMA)
                self.state = 3514
                self.t0z_path_delay_expression()
                self.state = 3515
                self.match(VerilogParser.COMMA)
                self.state = 3516
                self.tz1_path_delay_expression()
                self.state = 3517
                self.match(VerilogParser.COMMA)
                self.state = 3518
                self.t1z_path_delay_expression()
                self.state = 3519
                self.match(VerilogParser.COMMA)
                self.state = 3520
                self.tz0_path_delay_expression()
                self.state = 3521
                self.match(VerilogParser.COMMA)
                self.state = 3522
                self.t0x_path_delay_expression()
                self.state = 3523
                self.match(VerilogParser.COMMA)
                self.state = 3524
                self.tx1_path_delay_expression()
                self.state = 3525
                self.match(VerilogParser.COMMA)
                self.state = 3526
                self.t1x_path_delay_expression()
                self.state = 3527
                self.match(VerilogParser.COMMA)
                self.state = 3528
                self.tx0_path_delay_expression()
                self.state = 3529
                self.match(VerilogParser.COMMA)
                self.state = 3530
                self.txz_path_delay_expression()
                self.state = 3531
                self.match(VerilogParser.COMMA)
                self.state = 3532
                self.tzx_path_delay_expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT_path_delay_expression" ):
                listener.enterT_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT_path_delay_expression" ):
                listener.exitT_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT_path_delay_expression" ):
                return visitor.visitT_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t_path_delay_expression(self):

        localctx = VerilogParser.T_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 496, self.RULE_t_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3536
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Trise_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_trise_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTrise_path_delay_expression" ):
                listener.enterTrise_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTrise_path_delay_expression" ):
                listener.exitTrise_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTrise_path_delay_expression" ):
                return visitor.visitTrise_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def trise_path_delay_expression(self):

        localctx = VerilogParser.Trise_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 498, self.RULE_trise_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3538
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tfall_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tfall_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTfall_path_delay_expression" ):
                listener.enterTfall_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTfall_path_delay_expression" ):
                listener.exitTfall_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTfall_path_delay_expression" ):
                return visitor.visitTfall_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tfall_path_delay_expression(self):

        localctx = VerilogParser.Tfall_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 500, self.RULE_tfall_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3540
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tz_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tz_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz_path_delay_expression" ):
                listener.enterTz_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz_path_delay_expression" ):
                listener.exitTz_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz_path_delay_expression" ):
                return visitor.visitTz_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz_path_delay_expression(self):

        localctx = VerilogParser.Tz_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 502, self.RULE_tz_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3542
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T01_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t01_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT01_path_delay_expression" ):
                listener.enterT01_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT01_path_delay_expression" ):
                listener.exitT01_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT01_path_delay_expression" ):
                return visitor.visitT01_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t01_path_delay_expression(self):

        localctx = VerilogParser.T01_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 504, self.RULE_t01_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3544
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T10_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t10_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT10_path_delay_expression" ):
                listener.enterT10_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT10_path_delay_expression" ):
                listener.exitT10_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT10_path_delay_expression" ):
                return visitor.visitT10_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t10_path_delay_expression(self):

        localctx = VerilogParser.T10_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 506, self.RULE_t10_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3546
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T0z_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t0z_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT0z_path_delay_expression" ):
                listener.enterT0z_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT0z_path_delay_expression" ):
                listener.exitT0z_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT0z_path_delay_expression" ):
                return visitor.visitT0z_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t0z_path_delay_expression(self):

        localctx = VerilogParser.T0z_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 508, self.RULE_t0z_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3548
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tz1_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tz1_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz1_path_delay_expression" ):
                listener.enterTz1_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz1_path_delay_expression" ):
                listener.exitTz1_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz1_path_delay_expression" ):
                return visitor.visitTz1_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz1_path_delay_expression(self):

        localctx = VerilogParser.Tz1_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 510, self.RULE_tz1_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3550
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T1z_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t1z_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT1z_path_delay_expression" ):
                listener.enterT1z_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT1z_path_delay_expression" ):
                listener.exitT1z_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT1z_path_delay_expression" ):
                return visitor.visitT1z_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t1z_path_delay_expression(self):

        localctx = VerilogParser.T1z_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 512, self.RULE_t1z_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3552
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tz0_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tz0_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz0_path_delay_expression" ):
                listener.enterTz0_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz0_path_delay_expression" ):
                listener.exitTz0_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz0_path_delay_expression" ):
                return visitor.visitTz0_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz0_path_delay_expression(self):

        localctx = VerilogParser.Tz0_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 514, self.RULE_tz0_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3554
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T0x_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t0x_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT0x_path_delay_expression" ):
                listener.enterT0x_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT0x_path_delay_expression" ):
                listener.exitT0x_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT0x_path_delay_expression" ):
                return visitor.visitT0x_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t0x_path_delay_expression(self):

        localctx = VerilogParser.T0x_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 516, self.RULE_t0x_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3556
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tx1_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tx1_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTx1_path_delay_expression" ):
                listener.enterTx1_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTx1_path_delay_expression" ):
                listener.exitTx1_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTx1_path_delay_expression" ):
                return visitor.visitTx1_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tx1_path_delay_expression(self):

        localctx = VerilogParser.Tx1_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 518, self.RULE_tx1_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3558
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T1x_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_t1x_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT1x_path_delay_expression" ):
                listener.enterT1x_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT1x_path_delay_expression" ):
                listener.exitT1x_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT1x_path_delay_expression" ):
                return visitor.visitT1x_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t1x_path_delay_expression(self):

        localctx = VerilogParser.T1x_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 520, self.RULE_t1x_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3560
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tx0_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tx0_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTx0_path_delay_expression" ):
                listener.enterTx0_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTx0_path_delay_expression" ):
                listener.exitTx0_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTx0_path_delay_expression" ):
                return visitor.visitTx0_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tx0_path_delay_expression(self):

        localctx = VerilogParser.Tx0_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 522, self.RULE_tx0_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3562
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Txz_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_txz_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTxz_path_delay_expression" ):
                listener.enterTxz_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTxz_path_delay_expression" ):
                listener.exitTxz_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTxz_path_delay_expression" ):
                return visitor.visitTxz_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def txz_path_delay_expression(self):

        localctx = VerilogParser.Txz_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 524, self.RULE_txz_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3564
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tzx_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_tzx_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTzx_path_delay_expression" ):
                listener.enterTzx_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTzx_path_delay_expression" ):
                listener.exitTzx_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTzx_path_delay_expression" ):
                return visitor.visitTzx_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tzx_path_delay_expression(self):

        localctx = VerilogParser.Tzx_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 526, self.RULE_tzx_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3566
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_delay_expression" ):
                listener.enterPath_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_delay_expression" ):
                listener.exitPath_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_delay_expression" ):
                return visitor.visitPath_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def path_delay_expression(self):

        localctx = VerilogParser.Path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 528, self.RULE_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3568
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Edge_sensitive_path_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parallel_edge_sensitive_path_description(self):
            return self.getTypedRuleContext(VerilogParser.Parallel_edge_sensitive_path_descriptionContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def path_delay_value(self):
            return self.getTypedRuleContext(VerilogParser.Path_delay_valueContext,0)


        def full_edge_sensitive_path_description(self):
            return self.getTypedRuleContext(VerilogParser.Full_edge_sensitive_path_descriptionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_edge_sensitive_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_sensitive_path_declaration" ):
                listener.enterEdge_sensitive_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_sensitive_path_declaration" ):
                listener.exitEdge_sensitive_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_sensitive_path_declaration" ):
                return visitor.visitEdge_sensitive_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def edge_sensitive_path_declaration(self):

        localctx = VerilogParser.Edge_sensitive_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 530, self.RULE_edge_sensitive_path_declaration)
        try:
            self.state = 3578
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,358,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3570
                self.parallel_edge_sensitive_path_description()
                self.state = 3571
                self.match(VerilogParser.EQUAL)
                self.state = 3572
                self.path_delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3574
                self.full_edge_sensitive_path_description()
                self.state = 3575
                self.match(VerilogParser.EQUAL)
                self.state = 3576
                self.path_delay_value()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parallel_edge_sensitive_path_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LEFT_PARENTHESIS)
            else:
                return self.getToken(VerilogParser.LEFT_PARENTHESIS, i)

        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_input_terminal_descriptorContext,0)


        def EQUAL_GREATER_THAN(self):
            return self.getToken(VerilogParser.EQUAL_GREATER_THAN, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(VerilogParser.Specify_output_terminal_descriptorContext,0)


        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def data_source_expression(self):
            return self.getTypedRuleContext(VerilogParser.Data_source_expressionContext,0)


        def RIGHT_PARENTHESIS(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RIGHT_PARENTHESIS)
            else:
                return self.getToken(VerilogParser.RIGHT_PARENTHESIS, i)

        def edge_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Edge_identifierContext,0)


        def polarity_operator(self):
            return self.getTypedRuleContext(VerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_parallel_edge_sensitive_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParallel_edge_sensitive_path_description" ):
                listener.enterParallel_edge_sensitive_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParallel_edge_sensitive_path_description" ):
                listener.exitParallel_edge_sensitive_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParallel_edge_sensitive_path_description" ):
                return visitor.visitParallel_edge_sensitive_path_description(self)
            else:
                return visitor.visitChildren(self)




    def parallel_edge_sensitive_path_description(self):

        localctx = VerilogParser.Parallel_edge_sensitive_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 532, self.RULE_parallel_edge_sensitive_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3580
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3582
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.NEGEDGE or _la==VerilogParser.POSEDGE:
                self.state = 3581
                self.edge_identifier()


            self.state = 3584
            self.specify_input_terminal_descriptor()
            self.state = 3585
            self.match(VerilogParser.EQUAL_GREATER_THAN)
            self.state = 3586
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3587
            self.specify_output_terminal_descriptor()
            self.state = 3589
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.PLUS or _la==VerilogParser.MINUS:
                self.state = 3588
                self.polarity_operator()


            self.state = 3591
            self.match(VerilogParser.COLON)
            self.state = 3592
            self.data_source_expression()
            self.state = 3593
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 3594
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Full_edge_sensitive_path_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LEFT_PARENTHESIS)
            else:
                return self.getToken(VerilogParser.LEFT_PARENTHESIS, i)

        def list_of_path_inputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_inputsContext,0)


        def ASTERISK_GREATER_THAN(self):
            return self.getToken(VerilogParser.ASTERISK_GREATER_THAN, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(VerilogParser.List_of_path_outputsContext,0)


        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def data_source_expression(self):
            return self.getTypedRuleContext(VerilogParser.Data_source_expressionContext,0)


        def RIGHT_PARENTHESIS(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RIGHT_PARENTHESIS)
            else:
                return self.getToken(VerilogParser.RIGHT_PARENTHESIS, i)

        def edge_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Edge_identifierContext,0)


        def polarity_operator(self):
            return self.getTypedRuleContext(VerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_full_edge_sensitive_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFull_edge_sensitive_path_description" ):
                listener.enterFull_edge_sensitive_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFull_edge_sensitive_path_description" ):
                listener.exitFull_edge_sensitive_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFull_edge_sensitive_path_description" ):
                return visitor.visitFull_edge_sensitive_path_description(self)
            else:
                return visitor.visitChildren(self)




    def full_edge_sensitive_path_description(self):

        localctx = VerilogParser.Full_edge_sensitive_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 534, self.RULE_full_edge_sensitive_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3596
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3598
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.NEGEDGE or _la==VerilogParser.POSEDGE:
                self.state = 3597
                self.edge_identifier()


            self.state = 3600
            self.list_of_path_inputs()
            self.state = 3601
            self.match(VerilogParser.ASTERISK_GREATER_THAN)
            self.state = 3602
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3603
            self.list_of_path_outputs()
            self.state = 3605
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.PLUS or _la==VerilogParser.MINUS:
                self.state = 3604
                self.polarity_operator()


            self.state = 3607
            self.match(VerilogParser.COLON)
            self.state = 3608
            self.data_source_expression()
            self.state = 3609
            self.match(VerilogParser.RIGHT_PARENTHESIS)
            self.state = 3610
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Data_source_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_data_source_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterData_source_expression" ):
                listener.enterData_source_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitData_source_expression" ):
                listener.exitData_source_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitData_source_expression" ):
                return visitor.visitData_source_expression(self)
            else:
                return visitor.visitChildren(self)




    def data_source_expression(self):

        localctx = VerilogParser.Data_source_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 536, self.RULE_data_source_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3612
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Edge_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def POSEDGE(self):
            return self.getToken(VerilogParser.POSEDGE, 0)

        def NEGEDGE(self):
            return self.getToken(VerilogParser.NEGEDGE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_edge_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_identifier" ):
                listener.enterEdge_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_identifier" ):
                listener.exitEdge_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_identifier" ):
                return visitor.visitEdge_identifier(self)
            else:
                return visitor.visitChildren(self)




    def edge_identifier(self):

        localctx = VerilogParser.Edge_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 538, self.RULE_edge_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3614
            _la = self._input.LA(1)
            if not(_la==VerilogParser.NEGEDGE or _la==VerilogParser.POSEDGE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class State_dependent_path_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def IF(self):
            return self.getToken(VerilogParser.IF, 0)

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def module_path_expression(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_expressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def simple_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Simple_path_declarationContext,0)


        def edge_sensitive_path_declaration(self):
            return self.getTypedRuleContext(VerilogParser.Edge_sensitive_path_declarationContext,0)


        def IFNONE(self):
            return self.getToken(VerilogParser.IFNONE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_state_dependent_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterState_dependent_path_declaration" ):
                listener.enterState_dependent_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitState_dependent_path_declaration" ):
                listener.exitState_dependent_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitState_dependent_path_declaration" ):
                return visitor.visitState_dependent_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def state_dependent_path_declaration(self):

        localctx = VerilogParser.State_dependent_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 540, self.RULE_state_dependent_path_declaration)
        try:
            self.state = 3630
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,363,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3616
                self.match(VerilogParser.IF)
                self.state = 3617
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3618
                self.module_path_expression(0)
                self.state = 3619
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3620
                self.simple_path_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3622
                self.match(VerilogParser.IF)
                self.state = 3623
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3624
                self.module_path_expression(0)
                self.state = 3625
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                self.state = 3626
                self.edge_sensitive_path_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3628
                self.match(VerilogParser.IFNONE)
                self.state = 3629
                self.simple_path_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Polarity_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PLUS(self):
            return self.getToken(VerilogParser.PLUS, 0)

        def MINUS(self):
            return self.getToken(VerilogParser.MINUS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_polarity_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPolarity_operator" ):
                listener.enterPolarity_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPolarity_operator" ):
                listener.exitPolarity_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPolarity_operator" ):
                return visitor.visitPolarity_operator(self)
            else:
                return visitor.visitChildren(self)




    def polarity_operator(self):

        localctx = VerilogParser.Polarity_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 542, self.RULE_polarity_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3632
            _la = self._input.LA(1)
            if not(_la==VerilogParser.PLUS or _la==VerilogParser.MINUS):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ConcatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConcatenation" ):
                listener.enterConcatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConcatenation" ):
                listener.exitConcatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConcatenation" ):
                return visitor.visitConcatenation(self)
            else:
                return visitor.visitChildren(self)




    def concatenation(self):

        localctx = VerilogParser.ConcatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 544, self.RULE_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3634
            self.match(VerilogParser.LEFT_BRACE)
            self.state = 3635
            self.expression(0)
            self.state = 3640
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 3636
                self.match(VerilogParser.COMMA)
                self.state = 3637
                self.expression(0)
                self.state = 3642
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3643
            self.match(VerilogParser.RIGHT_BRACE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_concatenation" ):
                listener.enterConstant_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_concatenation" ):
                listener.exitConstant_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_concatenation" ):
                return visitor.visitConstant_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def constant_concatenation(self):

        localctx = VerilogParser.Constant_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 546, self.RULE_constant_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3645
            self.match(VerilogParser.LEFT_BRACE)
            self.state = 3646
            self.constant_expression(0)
            self.state = 3651
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 3647
                self.match(VerilogParser.COMMA)
                self.state = 3648
                self.constant_expression(0)
                self.state = 3653
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3654
            self.match(VerilogParser.RIGHT_BRACE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_multiple_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def constant_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Constant_concatenationContext,0)


        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_multiple_concatenation" ):
                listener.enterConstant_multiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_multiple_concatenation" ):
                listener.exitConstant_multiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_multiple_concatenation" ):
                return visitor.visitConstant_multiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def constant_multiple_concatenation(self):

        localctx = VerilogParser.Constant_multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 548, self.RULE_constant_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3656
            self.match(VerilogParser.LEFT_BRACE)
            self.state = 3657
            self.constant_expression(0)
            self.state = 3658
            self.constant_concatenation()
            self.state = 3659
            self.match(VerilogParser.RIGHT_BRACE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_path_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_path_expressionContext,i)


        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_concatenation" ):
                listener.enterModule_path_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_concatenation" ):
                listener.exitModule_path_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_concatenation" ):
                return visitor.visitModule_path_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def module_path_concatenation(self):

        localctx = VerilogParser.Module_path_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 550, self.RULE_module_path_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3661
            self.match(VerilogParser.LEFT_BRACE)
            self.state = 3662
            self.module_path_expression(0)
            self.state = 3667
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 3663
                self.match(VerilogParser.COMMA)
                self.state = 3664
                self.module_path_expression(0)
                self.state = 3669
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3670
            self.match(VerilogParser.RIGHT_BRACE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_path_multiple_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def module_path_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_concatenationContext,0)


        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_multiple_concatenation" ):
                listener.enterModule_path_multiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_multiple_concatenation" ):
                listener.exitModule_path_multiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_multiple_concatenation" ):
                return visitor.visitModule_path_multiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def module_path_multiple_concatenation(self):

        localctx = VerilogParser.Module_path_multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 552, self.RULE_module_path_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3672
            self.match(VerilogParser.LEFT_BRACE)
            self.state = 3673
            self.constant_expression(0)
            self.state = 3674
            self.module_path_concatenation()
            self.state = 3675
            self.match(VerilogParser.RIGHT_BRACE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Multiple_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def concatenation(self):
            return self.getTypedRuleContext(VerilogParser.ConcatenationContext,0)


        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMultiple_concatenation" ):
                listener.enterMultiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMultiple_concatenation" ):
                listener.exitMultiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMultiple_concatenation" ):
                return visitor.visitMultiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def multiple_concatenation(self):

        localctx = VerilogParser.Multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 554, self.RULE_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3677
            self.match(VerilogParser.LEFT_BRACE)
            self.state = 3678
            self.constant_expression(0)
            self.state = 3679
            self.concatenation()
            self.state = 3680
            self.match(VerilogParser.RIGHT_BRACE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_function_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Function_identifierContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_function_call" ):
                listener.enterConstant_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_function_call" ):
                listener.exitConstant_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_function_call" ):
                return visitor.visitConstant_function_call(self)
            else:
                return visitor.visitChildren(self)




    def constant_function_call(self):

        localctx = VerilogParser.Constant_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 556, self.RULE_constant_function_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3682
            self.function_identifier()
            self.state = 3686
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,367,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3683
                    self.attribute_instance() 
                self.state = 3688
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,367,self._ctx)

            self.state = 3689
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3690
            self.constant_expression(0)
            self.state = 3695
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 3691
                self.match(VerilogParser.COMMA)
                self.state = 3692
                self.constant_expression(0)
                self.state = 3697
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3698
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_system_function_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def system_function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.System_function_identifierContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_system_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_system_function_call" ):
                listener.enterConstant_system_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_system_function_call" ):
                listener.exitConstant_system_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_system_function_call" ):
                return visitor.visitConstant_system_function_call(self)
            else:
                return visitor.visitChildren(self)




    def constant_system_function_call(self):

        localctx = VerilogParser.Constant_system_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 558, self.RULE_constant_system_function_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3700
            self.system_function_identifier()
            self.state = 3701
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3702
            self.constant_expression(0)
            self.state = 3707
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 3703
                self.match(VerilogParser.COMMA)
                self.state = 3704
                self.constant_expression(0)
                self.state = 3709
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3710
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_function_identifierContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_call" ):
                listener.enterFunction_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_call" ):
                listener.exitFunction_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_call" ):
                return visitor.visitFunction_call(self)
            else:
                return visitor.visitChildren(self)




    def function_call(self):

        localctx = VerilogParser.Function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 560, self.RULE_function_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3712
            self.hierarchical_function_identifier()
            self.state = 3716
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,370,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3713
                    self.attribute_instance() 
                self.state = 3718
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,370,self._ctx)

            self.state = 3719
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 3720
            self.expression(0)
            self.state = 3725
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 3721
                self.match(VerilogParser.COMMA)
                self.state = 3722
                self.expression(0)
                self.state = 3727
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3728
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_function_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def system_function_identifier(self):
            return self.getTypedRuleContext(VerilogParser.System_function_identifierContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_system_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_function_call" ):
                listener.enterSystem_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_function_call" ):
                listener.exitSystem_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_function_call" ):
                return visitor.visitSystem_function_call(self)
            else:
                return visitor.visitChildren(self)




    def system_function_call(self):

        localctx = VerilogParser.System_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 562, self.RULE_system_function_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3730
            self.system_function_identifier()
            self.state = 3742
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,373,self._ctx)
            if la_ == 1:
                self.state = 3731
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3732
                self.expression(0)
                self.state = 3737
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 3733
                    self.match(VerilogParser.COMMA)
                    self.state = 3734
                    self.expression(0)
                    self.state = 3739
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3740
                self.match(VerilogParser.RIGHT_PARENTHESIS)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Base_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_base_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBase_expression" ):
                listener.enterBase_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBase_expression" ):
                listener.exitBase_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBase_expression" ):
                return visitor.visitBase_expression(self)
            else:
                return visitor.visitChildren(self)




    def base_expression(self):

        localctx = VerilogParser.Base_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 564, self.RULE_base_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3744
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_base_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_constant_base_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_base_expression" ):
                listener.enterConstant_base_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_base_expression" ):
                listener.exitConstant_base_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_base_expression" ):
                return visitor.visitConstant_base_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_base_expression(self):

        localctx = VerilogParser.Constant_base_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 566, self.RULE_constant_base_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3746
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_primary(self):
            return self.getTypedRuleContext(VerilogParser.Constant_primaryContext,0)


        def unary_operator(self):
            return self.getTypedRuleContext(VerilogParser.Unary_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def binary_operator(self):
            return self.getTypedRuleContext(VerilogParser.Binary_operatorContext,0)


        def QUESTION_MARK(self):
            return self.getToken(VerilogParser.QUESTION_MARK, 0)

        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_expression" ):
                listener.enterConstant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_expression" ):
                listener.exitConstant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_expression" ):
                return visitor.visitConstant_expression(self)
            else:
                return visitor.visitChildren(self)



    def constant_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.Constant_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 568
        self.enterRecursionRule(localctx, 568, self.RULE_constant_expression, _p)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3759
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE]:
                self.state = 3749
                self.constant_primary()
                pass
            elif token in [VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.state = 3750
                self.unary_operator()
                self.state = 3754
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,374,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3751
                        self.attribute_instance() 
                    self.state = 3756
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,374,self._ctx)

                self.state = 3757
                self.constant_primary()
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 3785
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,379,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 3783
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,378,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3761
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 3762
                        self.binary_operator()
                        self.state = 3766
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,376,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3763
                                self.attribute_instance() 
                            self.state = 3768
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,376,self._ctx)

                        self.state = 3769
                        self.constant_expression(3)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                        self.state = 3771
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 3772
                        self.match(VerilogParser.QUESTION_MARK)
                        self.state = 3776
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,377,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3773
                                self.attribute_instance() 
                            self.state = 3778
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,377,self._ctx)

                        self.state = 3779
                        self.constant_expression(0)
                        self.state = 3780
                        self.match(VerilogParser.COLON)
                        self.state = 3781
                        self.constant_expression(2)
                        pass

             
                self.state = 3787
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,379,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Constant_mintypmax_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COLON)
            else:
                return self.getToken(VerilogParser.COLON, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_mintypmax_expression" ):
                listener.enterConstant_mintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_mintypmax_expression" ):
                listener.exitConstant_mintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_mintypmax_expression" ):
                return visitor.visitConstant_mintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_mintypmax_expression(self):

        localctx = VerilogParser.Constant_mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 570, self.RULE_constant_mintypmax_expression)
        try:
            self.state = 3795
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,380,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3788
                self.constant_expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3789
                self.constant_expression(0)
                self.state = 3790
                self.match(VerilogParser.COLON)
                self.state = 3791
                self.constant_expression(0)
                self.state = 3792
                self.match(VerilogParser.COLON)
                self.state = 3793
                self.constant_expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_range_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def msb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Msb_constant_expressionContext,0)


        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def lsb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Lsb_constant_expressionContext,0)


        def constant_base_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_base_expressionContext,0)


        def PLUS_COLON(self):
            return self.getToken(VerilogParser.PLUS_COLON, 0)

        def width_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Width_constant_expressionContext,0)


        def MINUS_COLON(self):
            return self.getToken(VerilogParser.MINUS_COLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_constant_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_range_expression" ):
                listener.enterConstant_range_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_range_expression" ):
                listener.exitConstant_range_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_range_expression" ):
                return visitor.visitConstant_range_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_range_expression(self):

        localctx = VerilogParser.Constant_range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 572, self.RULE_constant_range_expression)
        try:
            self.state = 3810
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,381,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3797
                self.constant_expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3798
                self.msb_constant_expression()
                self.state = 3799
                self.match(VerilogParser.COLON)
                self.state = 3800
                self.lsb_constant_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3802
                self.constant_base_expression()
                self.state = 3803
                self.match(VerilogParser.PLUS_COLON)
                self.state = 3804
                self.width_constant_expression()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3806
                self.constant_base_expression()
                self.state = 3807
                self.match(VerilogParser.MINUS_COLON)
                self.state = 3808
                self.width_constant_expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dimension_constant_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_dimension_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDimension_constant_expression" ):
                listener.enterDimension_constant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDimension_constant_expression" ):
                listener.exitDimension_constant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDimension_constant_expression" ):
                return visitor.visitDimension_constant_expression(self)
            else:
                return visitor.visitChildren(self)




    def dimension_constant_expression(self):

        localctx = VerilogParser.Dimension_constant_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 574, self.RULE_dimension_constant_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3812
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ExpressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def primary(self):
            return self.getTypedRuleContext(VerilogParser.PrimaryContext,0)


        def unary_operator(self):
            return self.getTypedRuleContext(VerilogParser.Unary_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def binary_operator(self):
            return self.getTypedRuleContext(VerilogParser.Binary_operatorContext,0)


        def QUESTION_MARK(self):
            return self.getToken(VerilogParser.QUESTION_MARK, 0)

        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExpression" ):
                listener.enterExpression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExpression" ):
                listener.exitExpression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExpression" ):
                return visitor.visitExpression(self)
            else:
                return visitor.visitChildren(self)



    def expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.ExpressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 576
        self.enterRecursionRule(localctx, 576, self.RULE_expression, _p)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3825
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.DOLLAR_BITSTOREAL, VerilogParser.DOLLAR_ITOR, VerilogParser.DOLLAR_SIGNED, VerilogParser.DOLLAR_REALTOBITS, VerilogParser.DOLLAR_RTOI, VerilogParser.DOLLAR_UNSIGNED, VerilogParser.DOLLAR_RANDOM, VerilogParser.DOLLAR_DIST_ERLANG, VerilogParser.DOLLAR_DIST_NORMAL, VerilogParser.DOLLAR_DIST_T, VerilogParser.DOLLAR_DIST_CHI_SQUARE, VerilogParser.DOLLAR_DIST_EXPONENTIAL, VerilogParser.DOLLAR_DIST_POISSON, VerilogParser.DOLLAR_DIST_UNIFORM, VerilogParser.DOLLAR_CLOG2, VerilogParser.DOLLAR_LN, VerilogParser.DOLLAR_LOG10, VerilogParser.DOLLAR_EXP, VerilogParser.DOLLAR_SQRT, VerilogParser.DOLLAR_POW, VerilogParser.DOLLAR_FLOOR, VerilogParser.DOLLAR_CEIL, VerilogParser.DOLLAR_SIN, VerilogParser.DOLLAR_COS, VerilogParser.DOLLAR_TAN, VerilogParser.DOLLAR_ASIN, VerilogParser.DOLLAR_ACOS, VerilogParser.DOLLAR_ATAN, VerilogParser.DOLLAR_ATAN2, VerilogParser.DOLLAR_HYPOT, VerilogParser.DOLLAR_SINH, VerilogParser.DOLLAR_COSH, VerilogParser.DOLLAR_TANH, VerilogParser.DOLLAR_ASINH, VerilogParser.DOLLAR_ACOSH, VerilogParser.DOLLAR_ATANH, VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.STRING, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE]:
                self.state = 3815
                self.primary()
                pass
            elif token in [VerilogParser.PLUS, VerilogParser.MINUS, VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.state = 3816
                self.unary_operator()
                self.state = 3820
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,382,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3817
                        self.attribute_instance() 
                    self.state = 3822
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,382,self._ctx)

                self.state = 3823
                self.primary()
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 3851
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,387,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 3849
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,386,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 3827
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 3828
                        self.binary_operator()
                        self.state = 3832
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,384,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3829
                                self.attribute_instance() 
                            self.state = 3834
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,384,self._ctx)

                        self.state = 3835
                        self.expression(3)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 3837
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 3838
                        self.match(VerilogParser.QUESTION_MARK)
                        self.state = 3842
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,385,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3839
                                self.attribute_instance() 
                            self.state = 3844
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,385,self._ctx)

                        self.state = 3845
                        self.expression(0)
                        self.state = 3846
                        self.match(VerilogParser.COLON)
                        self.state = 3847
                        self.expression(2)
                        pass

             
                self.state = 3853
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,387,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Lsb_constant_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_lsb_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLsb_constant_expression" ):
                listener.enterLsb_constant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLsb_constant_expression" ):
                listener.exitLsb_constant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLsb_constant_expression" ):
                return visitor.visitLsb_constant_expression(self)
            else:
                return visitor.visitChildren(self)




    def lsb_constant_expression(self):

        localctx = VerilogParser.Lsb_constant_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 578, self.RULE_lsb_constant_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3854
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mintypmax_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COLON)
            else:
                return self.getToken(VerilogParser.COLON, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMintypmax_expression" ):
                listener.enterMintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMintypmax_expression" ):
                listener.exitMintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMintypmax_expression" ):
                return visitor.visitMintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def mintypmax_expression(self):

        localctx = VerilogParser.Mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 580, self.RULE_mintypmax_expression)
        try:
            self.state = 3863
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,388,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3856
                self.expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3857
                self.expression(0)
                self.state = 3858
                self.match(VerilogParser.COLON)
                self.state = 3859
                self.expression(0)
                self.state = 3860
                self.match(VerilogParser.COLON)
                self.state = 3861
                self.expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_path_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_path_primary(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_primaryContext,0)


        def unary_module_path_operator(self):
            return self.getTypedRuleContext(VerilogParser.Unary_module_path_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attribute_instanceContext,i)


        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_path_expressionContext,i)


        def binary_module_path_operator(self):
            return self.getTypedRuleContext(VerilogParser.Binary_module_path_operatorContext,0)


        def QUESTION_MARK(self):
            return self.getToken(VerilogParser.QUESTION_MARK, 0)

        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_expression" ):
                listener.enterModule_path_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_expression" ):
                listener.exitModule_path_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_expression" ):
                return visitor.visitModule_path_expression(self)
            else:
                return visitor.visitChildren(self)



    def module_path_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = VerilogParser.Module_path_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 582
        self.enterRecursionRule(localctx, 582, self.RULE_module_path_expression, _p)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3876
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.REAL_NUMBER, VerilogParser.DECIMAL_NUMBER, VerilogParser.BINARY_NUMBER, VerilogParser.OCTAL_NUMBER, VerilogParser.HEX_NUMBER, VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER, VerilogParser.SYSTEM_TF_IDENTIFIER, VerilogParser.LEFT_PARENTHESIS, VerilogParser.LEFT_BRACE]:
                self.state = 3866
                self.module_path_primary()
                pass
            elif token in [VerilogParser.EXCLAMATION_MARK, VerilogParser.TILDE, VerilogParser.AMPERSAND, VerilogParser.TILDE_AMPERSAND, VerilogParser.VERTICAL_BAR, VerilogParser.TILDE_VERTICAL_BAR, VerilogParser.CARET, VerilogParser.TILDE_CARET, VerilogParser.CARET_TILDE]:
                self.state = 3867
                self.unary_module_path_operator()
                self.state = 3871
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,389,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3868
                        self.attribute_instance() 
                    self.state = 3873
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,389,self._ctx)

                self.state = 3874
                self.module_path_primary()
                pass
            else:
                raise NoViableAltException(self)

            self._ctx.stop = self._input.LT(-1)
            self.state = 3902
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,394,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 3900
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,393,self._ctx)
                    if la_ == 1:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 3878
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 3879
                        self.binary_module_path_operator()
                        self.state = 3883
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,391,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3880
                                self.attribute_instance() 
                            self.state = 3885
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,391,self._ctx)

                        self.state = 3886
                        self.module_path_expression(3)
                        pass

                    elif la_ == 2:
                        localctx = VerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 3888
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 3889
                        self.match(VerilogParser.QUESTION_MARK)
                        self.state = 3893
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,392,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 3890
                                self.attribute_instance() 
                            self.state = 3895
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,392,self._ctx)

                        self.state = 3896
                        self.module_path_expression(0)
                        self.state = 3897
                        self.match(VerilogParser.COLON)
                        self.state = 3898
                        self.module_path_expression(2)
                        pass

             
                self.state = 3904
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,394,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Module_path_mintypmax_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Module_path_expressionContext,i)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COLON)
            else:
                return self.getToken(VerilogParser.COLON, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_mintypmax_expression" ):
                listener.enterModule_path_mintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_mintypmax_expression" ):
                listener.exitModule_path_mintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_mintypmax_expression" ):
                return visitor.visitModule_path_mintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def module_path_mintypmax_expression(self):

        localctx = VerilogParser.Module_path_mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 584, self.RULE_module_path_mintypmax_expression)
        try:
            self.state = 3912
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,395,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3905
                self.module_path_expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3906
                self.module_path_expression(0)
                self.state = 3907
                self.match(VerilogParser.COLON)
                self.state = 3908
                self.module_path_expression(0)
                self.state = 3909
                self.match(VerilogParser.COLON)
                self.state = 3910
                self.module_path_expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Msb_constant_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_msb_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMsb_constant_expression" ):
                listener.enterMsb_constant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMsb_constant_expression" ):
                listener.exitMsb_constant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMsb_constant_expression" ):
                return visitor.visitMsb_constant_expression(self)
            else:
                return visitor.visitChildren(self)




    def msb_constant_expression(self):

        localctx = VerilogParser.Msb_constant_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 586, self.RULE_msb_constant_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3914
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Range_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(VerilogParser.ExpressionContext,0)


        def msb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Msb_constant_expressionContext,0)


        def COLON(self):
            return self.getToken(VerilogParser.COLON, 0)

        def lsb_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Lsb_constant_expressionContext,0)


        def base_expression(self):
            return self.getTypedRuleContext(VerilogParser.Base_expressionContext,0)


        def PLUS_COLON(self):
            return self.getToken(VerilogParser.PLUS_COLON, 0)

        def width_constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Width_constant_expressionContext,0)


        def MINUS_COLON(self):
            return self.getToken(VerilogParser.MINUS_COLON, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRange_expression" ):
                listener.enterRange_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRange_expression" ):
                listener.exitRange_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRange_expression" ):
                return visitor.visitRange_expression(self)
            else:
                return visitor.visitChildren(self)




    def range_expression(self):

        localctx = VerilogParser.Range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 588, self.RULE_range_expression)
        try:
            self.state = 3929
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,396,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3916
                self.expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3917
                self.msb_constant_expression()
                self.state = 3918
                self.match(VerilogParser.COLON)
                self.state = 3919
                self.lsb_constant_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3921
                self.base_expression()
                self.state = 3922
                self.match(VerilogParser.PLUS_COLON)
                self.state = 3923
                self.width_constant_expression()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3925
                self.base_expression()
                self.state = 3926
                self.match(VerilogParser.MINUS_COLON)
                self.state = 3927
                self.width_constant_expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Width_constant_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_width_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWidth_constant_expression" ):
                listener.enterWidth_constant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWidth_constant_expression" ):
                listener.exitWidth_constant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWidth_constant_expression" ):
                return visitor.visitWidth_constant_expression(self)
            else:
                return visitor.visitChildren(self)




    def width_constant_expression(self):

        localctx = VerilogParser.Width_constant_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 590, self.RULE_width_constant_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3931
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_primaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(VerilogParser.NumberContext,0)


        def parameter_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Parameter_identifierContext,0)


        def LEFT_BRACKET(self):
            return self.getToken(VerilogParser.LEFT_BRACKET, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RIGHT_BRACKET(self):
            return self.getToken(VerilogParser.RIGHT_BRACKET, 0)

        def specparam_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Specparam_identifierContext,0)


        def constant_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Constant_concatenationContext,0)


        def constant_multiple_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Constant_multiple_concatenationContext,0)


        def constant_function_call(self):
            return self.getTypedRuleContext(VerilogParser.Constant_function_callContext,0)


        def constant_system_function_call(self):
            return self.getTypedRuleContext(VerilogParser.Constant_system_function_callContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_mintypmax_expressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def STRING(self):
            return self.getToken(VerilogParser.STRING, 0)

        def conversion_functions(self):
            return self.getTypedRuleContext(VerilogParser.Conversion_functionsContext,0)


        def random_function(self):
            return self.getTypedRuleContext(VerilogParser.Random_functionContext,0)


        def dist_functions(self):
            return self.getTypedRuleContext(VerilogParser.Dist_functionsContext,0)


        def math_functions(self):
            return self.getTypedRuleContext(VerilogParser.Math_functionsContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_constant_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_primary" ):
                listener.enterConstant_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_primary" ):
                listener.exitConstant_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_primary" ):
                return visitor.visitConstant_primary(self)
            else:
                return visitor.visitChildren(self)




    def constant_primary(self):

        localctx = VerilogParser.Constant_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 592, self.RULE_constant_primary)
        try:
            self.state = 3961
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,399,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3933
                self.number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3934
                self.parameter_identifier()
                self.state = 3939
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,397,self._ctx)
                if la_ == 1:
                    self.state = 3935
                    self.match(VerilogParser.LEFT_BRACKET)
                    self.state = 3936
                    self.constant_range_expression()
                    self.state = 3937
                    self.match(VerilogParser.RIGHT_BRACKET)


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3941
                self.specparam_identifier()
                self.state = 3946
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,398,self._ctx)
                if la_ == 1:
                    self.state = 3942
                    self.match(VerilogParser.LEFT_BRACKET)
                    self.state = 3943
                    self.constant_range_expression()
                    self.state = 3944
                    self.match(VerilogParser.RIGHT_BRACKET)


                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3948
                self.constant_concatenation()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 3949
                self.constant_multiple_concatenation()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 3950
                self.constant_function_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 3951
                self.constant_system_function_call()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 3952
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3953
                self.constant_mintypmax_expression()
                self.state = 3954
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 3956
                self.match(VerilogParser.STRING)
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 3957
                self.conversion_functions()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 3958
                self.random_function()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 3959
                self.dist_functions()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 3960
                self.math_functions()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_path_primaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(VerilogParser.NumberContext,0)


        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def module_path_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_concatenationContext,0)


        def module_path_multiple_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_multiple_concatenationContext,0)


        def function_call(self):
            return self.getTypedRuleContext(VerilogParser.Function_callContext,0)


        def system_function_call(self):
            return self.getTypedRuleContext(VerilogParser.System_function_callContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def module_path_mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Module_path_mintypmax_expressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_module_path_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_primary" ):
                listener.enterModule_path_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_primary" ):
                listener.exitModule_path_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_primary" ):
                return visitor.visitModule_path_primary(self)
            else:
                return visitor.visitChildren(self)




    def module_path_primary(self):

        localctx = VerilogParser.Module_path_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 594, self.RULE_module_path_primary)
        try:
            self.state = 3973
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,400,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3963
                self.number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3964
                self.identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3965
                self.module_path_concatenation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3966
                self.module_path_multiple_concatenation()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 3967
                self.function_call()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 3968
                self.system_function_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 3969
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3970
                self.module_path_mintypmax_expression()
                self.state = 3971
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class PrimaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(VerilogParser.NumberContext,0)


        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def LEFT_BRACKET(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LEFT_BRACKET)
            else:
                return self.getToken(VerilogParser.LEFT_BRACKET, i)

        def range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Range_expressionContext,0)


        def RIGHT_BRACKET(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RIGHT_BRACKET)
            else:
                return self.getToken(VerilogParser.RIGHT_BRACKET, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def concatenation(self):
            return self.getTypedRuleContext(VerilogParser.ConcatenationContext,0)


        def multiple_concatenation(self):
            return self.getTypedRuleContext(VerilogParser.Multiple_concatenationContext,0)


        def function_call(self):
            return self.getTypedRuleContext(VerilogParser.Function_callContext,0)


        def system_function_call(self):
            return self.getTypedRuleContext(VerilogParser.System_function_callContext,0)


        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(VerilogParser.Mintypmax_expressionContext,0)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def STRING(self):
            return self.getToken(VerilogParser.STRING, 0)

        def conversion_functions(self):
            return self.getTypedRuleContext(VerilogParser.Conversion_functionsContext,0)


        def random_function(self):
            return self.getTypedRuleContext(VerilogParser.Random_functionContext,0)


        def dist_functions(self):
            return self.getTypedRuleContext(VerilogParser.Dist_functionsContext,0)


        def math_functions(self):
            return self.getTypedRuleContext(VerilogParser.Math_functionsContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrimary" ):
                listener.enterPrimary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrimary" ):
                listener.exitPrimary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrimary" ):
                return visitor.visitPrimary(self)
            else:
                return visitor.visitChildren(self)




    def primary(self):

        localctx = VerilogParser.PrimaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 596, self.RULE_primary)
        try:
            self.state = 4005
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,403,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3975
                self.number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3976
                self.hierarchical_identifier()
                self.state = 3990
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,402,self._ctx)
                if la_ == 1:
                    self.state = 3983
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,401,self._ctx)
                    while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                        if _alt==1:
                            self.state = 3977
                            self.match(VerilogParser.LEFT_BRACKET)
                            self.state = 3978
                            self.expression(0)
                            self.state = 3979
                            self.match(VerilogParser.RIGHT_BRACKET) 
                        self.state = 3985
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,401,self._ctx)

                    self.state = 3986
                    self.match(VerilogParser.LEFT_BRACKET)
                    self.state = 3987
                    self.range_expression()
                    self.state = 3988
                    self.match(VerilogParser.RIGHT_BRACKET)


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3992
                self.concatenation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3993
                self.multiple_concatenation()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 3994
                self.function_call()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 3995
                self.system_function_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 3996
                self.match(VerilogParser.LEFT_PARENTHESIS)
                self.state = 3997
                self.mintypmax_expression()
                self.state = 3998
                self.match(VerilogParser.RIGHT_PARENTHESIS)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 4000
                self.match(VerilogParser.STRING)
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 4001
                self.conversion_functions()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 4002
                self.random_function()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 4003
                self.dist_functions()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 4004
                self.math_functions()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_lvalueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_net_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_net_identifierContext,0)


        def LEFT_BRACKET(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LEFT_BRACKET)
            else:
                return self.getToken(VerilogParser.LEFT_BRACKET, i)

        def constant_range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_range_expressionContext,0)


        def RIGHT_BRACKET(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RIGHT_BRACKET)
            else:
                return self.getToken(VerilogParser.RIGHT_BRACKET, i)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def net_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Net_lvalueContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Net_lvalueContext,i)


        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_net_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_lvalue" ):
                listener.enterNet_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_lvalue" ):
                listener.exitNet_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_lvalue" ):
                return visitor.visitNet_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def net_lvalue(self):

        localctx = VerilogParser.Net_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 598, self.RULE_net_lvalue)
        self._la = 0 # Token type
        try:
            self.state = 4034
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4007
                self.hierarchical_net_identifier()
                self.state = 4021
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 4014
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,404,self._ctx)
                    while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                        if _alt==1:
                            self.state = 4008
                            self.match(VerilogParser.LEFT_BRACKET)
                            self.state = 4009
                            self.constant_expression(0)
                            self.state = 4010
                            self.match(VerilogParser.RIGHT_BRACKET) 
                        self.state = 4016
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,404,self._ctx)

                    self.state = 4017
                    self.match(VerilogParser.LEFT_BRACKET)
                    self.state = 4018
                    self.constant_range_expression()
                    self.state = 4019
                    self.match(VerilogParser.RIGHT_BRACKET)


                pass
            elif token in [VerilogParser.LEFT_BRACE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4023
                self.match(VerilogParser.LEFT_BRACE)
                self.state = 4024
                self.net_lvalue()
                self.state = 4029
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 4025
                    self.match(VerilogParser.COMMA)
                    self.state = 4026
                    self.net_lvalue()
                    self.state = 4031
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4032
                self.match(VerilogParser.RIGHT_BRACE)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_lvalueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_variable_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_variable_identifierContext,0)


        def LEFT_BRACKET(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LEFT_BRACKET)
            else:
                return self.getToken(VerilogParser.LEFT_BRACKET, i)

        def range_expression(self):
            return self.getTypedRuleContext(VerilogParser.Range_expressionContext,0)


        def RIGHT_BRACKET(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RIGHT_BRACKET)
            else:
                return self.getToken(VerilogParser.RIGHT_BRACKET, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.ExpressionContext,i)


        def LEFT_BRACE(self):
            return self.getToken(VerilogParser.LEFT_BRACE, 0)

        def variable_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Variable_lvalueContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Variable_lvalueContext,i)


        def RIGHT_BRACE(self):
            return self.getToken(VerilogParser.RIGHT_BRACE, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_variable_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_lvalue" ):
                listener.enterVariable_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_lvalue" ):
                listener.exitVariable_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_lvalue" ):
                return visitor.visitVariable_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def variable_lvalue(self):

        localctx = VerilogParser.Variable_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 600, self.RULE_variable_lvalue)
        self._la = 0 # Token type
        try:
            self.state = 4063
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [VerilogParser.ESCAPED_IDENTIFIER, VerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4036
                self.hierarchical_variable_identifier()
                self.state = 4050
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==VerilogParser.LEFT_BRACKET:
                    self.state = 4043
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,408,self._ctx)
                    while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                        if _alt==1:
                            self.state = 4037
                            self.match(VerilogParser.LEFT_BRACKET)
                            self.state = 4038
                            self.expression(0)
                            self.state = 4039
                            self.match(VerilogParser.RIGHT_BRACKET) 
                        self.state = 4045
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,408,self._ctx)

                    self.state = 4046
                    self.match(VerilogParser.LEFT_BRACKET)
                    self.state = 4047
                    self.range_expression()
                    self.state = 4048
                    self.match(VerilogParser.RIGHT_BRACKET)


                pass
            elif token in [VerilogParser.LEFT_BRACE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4052
                self.match(VerilogParser.LEFT_BRACE)
                self.state = 4053
                self.variable_lvalue()
                self.state = 4058
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==VerilogParser.COMMA:
                    self.state = 4054
                    self.match(VerilogParser.COMMA)
                    self.state = 4055
                    self.variable_lvalue()
                    self.state = 4060
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4061
                self.match(VerilogParser.RIGHT_BRACE)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PLUS(self):
            return self.getToken(VerilogParser.PLUS, 0)

        def MINUS(self):
            return self.getToken(VerilogParser.MINUS, 0)

        def EXCLAMATION_MARK(self):
            return self.getToken(VerilogParser.EXCLAMATION_MARK, 0)

        def TILDE(self):
            return self.getToken(VerilogParser.TILDE, 0)

        def AMPERSAND(self):
            return self.getToken(VerilogParser.AMPERSAND, 0)

        def TILDE_AMPERSAND(self):
            return self.getToken(VerilogParser.TILDE_AMPERSAND, 0)

        def VERTICAL_BAR(self):
            return self.getToken(VerilogParser.VERTICAL_BAR, 0)

        def TILDE_VERTICAL_BAR(self):
            return self.getToken(VerilogParser.TILDE_VERTICAL_BAR, 0)

        def CARET(self):
            return self.getToken(VerilogParser.CARET, 0)

        def TILDE_CARET(self):
            return self.getToken(VerilogParser.TILDE_CARET, 0)

        def CARET_TILDE(self):
            return self.getToken(VerilogParser.CARET_TILDE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_unary_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_operator" ):
                listener.enterUnary_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_operator" ):
                listener.exitUnary_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_operator" ):
                return visitor.visitUnary_operator(self)
            else:
                return visitor.visitChildren(self)




    def unary_operator(self):

        localctx = VerilogParser.Unary_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 602, self.RULE_unary_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4065
            _la = self._input.LA(1)
            if not(((((_la - 300)) & ~0x3f) == 0 and ((1 << (_la - 300)) & ((1 << (VerilogParser.PLUS - 300)) | (1 << (VerilogParser.MINUS - 300)) | (1 << (VerilogParser.EXCLAMATION_MARK - 300)) | (1 << (VerilogParser.TILDE - 300)) | (1 << (VerilogParser.AMPERSAND - 300)) | (1 << (VerilogParser.TILDE_AMPERSAND - 300)) | (1 << (VerilogParser.VERTICAL_BAR - 300)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 300)) | (1 << (VerilogParser.CARET - 300)) | (1 << (VerilogParser.TILDE_CARET - 300)) | (1 << (VerilogParser.CARET_TILDE - 300)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Binary_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PLUS(self):
            return self.getToken(VerilogParser.PLUS, 0)

        def MINUS(self):
            return self.getToken(VerilogParser.MINUS, 0)

        def ASTERISK(self):
            return self.getToken(VerilogParser.ASTERISK, 0)

        def SLASH(self):
            return self.getToken(VerilogParser.SLASH, 0)

        def PERCENT(self):
            return self.getToken(VerilogParser.PERCENT, 0)

        def DOUBLE_EQUAL(self):
            return self.getToken(VerilogParser.DOUBLE_EQUAL, 0)

        def EXCLAMATION_MARK_EQUAL(self):
            return self.getToken(VerilogParser.EXCLAMATION_MARK_EQUAL, 0)

        def TRIPLE_EQUAL(self):
            return self.getToken(VerilogParser.TRIPLE_EQUAL, 0)

        def EXCLAMATION_MARK_DOUBLE_EQUAL(self):
            return self.getToken(VerilogParser.EXCLAMATION_MARK_DOUBLE_EQUAL, 0)

        def DOUBLE_AMPERSAND(self):
            return self.getToken(VerilogParser.DOUBLE_AMPERSAND, 0)

        def DOUBLE_VERTICAL_BAR(self):
            return self.getToken(VerilogParser.DOUBLE_VERTICAL_BAR, 0)

        def DOUBLE_ASTERISK(self):
            return self.getToken(VerilogParser.DOUBLE_ASTERISK, 0)

        def LESS_THAN(self):
            return self.getToken(VerilogParser.LESS_THAN, 0)

        def LESS_THAN_EQUAL(self):
            return self.getToken(VerilogParser.LESS_THAN_EQUAL, 0)

        def GREATER_THAN(self):
            return self.getToken(VerilogParser.GREATER_THAN, 0)

        def GREATER_THAN_EQUAL(self):
            return self.getToken(VerilogParser.GREATER_THAN_EQUAL, 0)

        def AMPERSAND(self):
            return self.getToken(VerilogParser.AMPERSAND, 0)

        def VERTICAL_BAR(self):
            return self.getToken(VerilogParser.VERTICAL_BAR, 0)

        def CARET(self):
            return self.getToken(VerilogParser.CARET, 0)

        def CARET_TILDE(self):
            return self.getToken(VerilogParser.CARET_TILDE, 0)

        def TILDE_CARET(self):
            return self.getToken(VerilogParser.TILDE_CARET, 0)

        def DOUBLE_GREATER_THAN(self):
            return self.getToken(VerilogParser.DOUBLE_GREATER_THAN, 0)

        def DOUBLE_LESS_THAN(self):
            return self.getToken(VerilogParser.DOUBLE_LESS_THAN, 0)

        def TRIPLE_GREATER_THAN(self):
            return self.getToken(VerilogParser.TRIPLE_GREATER_THAN, 0)

        def TRIPLE_LESS_THAN(self):
            return self.getToken(VerilogParser.TRIPLE_LESS_THAN, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_binary_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_operator" ):
                listener.enterBinary_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_operator" ):
                listener.exitBinary_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_operator" ):
                return visitor.visitBinary_operator(self)
            else:
                return visitor.visitChildren(self)




    def binary_operator(self):

        localctx = VerilogParser.Binary_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 604, self.RULE_binary_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4067
            _la = self._input.LA(1)
            if not(((((_la - 300)) & ~0x3f) == 0 and ((1 << (_la - 300)) & ((1 << (VerilogParser.PLUS - 300)) | (1 << (VerilogParser.MINUS - 300)) | (1 << (VerilogParser.AMPERSAND - 300)) | (1 << (VerilogParser.VERTICAL_BAR - 300)) | (1 << (VerilogParser.CARET - 300)) | (1 << (VerilogParser.TILDE_CARET - 300)) | (1 << (VerilogParser.CARET_TILDE - 300)) | (1 << (VerilogParser.ASTERISK - 300)) | (1 << (VerilogParser.PERCENT - 300)) | (1 << (VerilogParser.DOUBLE_EQUAL - 300)) | (1 << (VerilogParser.EXCLAMATION_MARK_EQUAL - 300)) | (1 << (VerilogParser.TRIPLE_EQUAL - 300)) | (1 << (VerilogParser.EXCLAMATION_MARK_DOUBLE_EQUAL - 300)) | (1 << (VerilogParser.DOUBLE_AMPERSAND - 300)) | (1 << (VerilogParser.DOUBLE_VERTICAL_BAR - 300)) | (1 << (VerilogParser.DOUBLE_ASTERISK - 300)) | (1 << (VerilogParser.LESS_THAN - 300)) | (1 << (VerilogParser.LESS_THAN_EQUAL - 300)) | (1 << (VerilogParser.GREATER_THAN - 300)) | (1 << (VerilogParser.GREATER_THAN_EQUAL - 300)) | (1 << (VerilogParser.DOUBLE_GREATER_THAN - 300)) | (1 << (VerilogParser.DOUBLE_LESS_THAN - 300)) | (1 << (VerilogParser.TRIPLE_GREATER_THAN - 300)) | (1 << (VerilogParser.TRIPLE_LESS_THAN - 300)) | (1 << (VerilogParser.SLASH - 300)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_module_path_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EXCLAMATION_MARK(self):
            return self.getToken(VerilogParser.EXCLAMATION_MARK, 0)

        def TILDE(self):
            return self.getToken(VerilogParser.TILDE, 0)

        def AMPERSAND(self):
            return self.getToken(VerilogParser.AMPERSAND, 0)

        def TILDE_AMPERSAND(self):
            return self.getToken(VerilogParser.TILDE_AMPERSAND, 0)

        def VERTICAL_BAR(self):
            return self.getToken(VerilogParser.VERTICAL_BAR, 0)

        def TILDE_VERTICAL_BAR(self):
            return self.getToken(VerilogParser.TILDE_VERTICAL_BAR, 0)

        def CARET(self):
            return self.getToken(VerilogParser.CARET, 0)

        def TILDE_CARET(self):
            return self.getToken(VerilogParser.TILDE_CARET, 0)

        def CARET_TILDE(self):
            return self.getToken(VerilogParser.CARET_TILDE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_unary_module_path_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_module_path_operator" ):
                listener.enterUnary_module_path_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_module_path_operator" ):
                listener.exitUnary_module_path_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_module_path_operator" ):
                return visitor.visitUnary_module_path_operator(self)
            else:
                return visitor.visitChildren(self)




    def unary_module_path_operator(self):

        localctx = VerilogParser.Unary_module_path_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 606, self.RULE_unary_module_path_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4069
            _la = self._input.LA(1)
            if not(((((_la - 302)) & ~0x3f) == 0 and ((1 << (_la - 302)) & ((1 << (VerilogParser.EXCLAMATION_MARK - 302)) | (1 << (VerilogParser.TILDE - 302)) | (1 << (VerilogParser.AMPERSAND - 302)) | (1 << (VerilogParser.TILDE_AMPERSAND - 302)) | (1 << (VerilogParser.VERTICAL_BAR - 302)) | (1 << (VerilogParser.TILDE_VERTICAL_BAR - 302)) | (1 << (VerilogParser.CARET - 302)) | (1 << (VerilogParser.TILDE_CARET - 302)) | (1 << (VerilogParser.CARET_TILDE - 302)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Binary_module_path_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOUBLE_EQUAL(self):
            return self.getToken(VerilogParser.DOUBLE_EQUAL, 0)

        def EXCLAMATION_MARK_EQUAL(self):
            return self.getToken(VerilogParser.EXCLAMATION_MARK_EQUAL, 0)

        def DOUBLE_AMPERSAND(self):
            return self.getToken(VerilogParser.DOUBLE_AMPERSAND, 0)

        def DOUBLE_VERTICAL_BAR(self):
            return self.getToken(VerilogParser.DOUBLE_VERTICAL_BAR, 0)

        def AMPERSAND(self):
            return self.getToken(VerilogParser.AMPERSAND, 0)

        def VERTICAL_BAR(self):
            return self.getToken(VerilogParser.VERTICAL_BAR, 0)

        def CARET(self):
            return self.getToken(VerilogParser.CARET, 0)

        def TILDE_CARET(self):
            return self.getToken(VerilogParser.TILDE_CARET, 0)

        def CARET_TILDE(self):
            return self.getToken(VerilogParser.CARET_TILDE, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_binary_module_path_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_module_path_operator" ):
                listener.enterBinary_module_path_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_module_path_operator" ):
                listener.exitBinary_module_path_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_module_path_operator" ):
                return visitor.visitBinary_module_path_operator(self)
            else:
                return visitor.visitChildren(self)




    def binary_module_path_operator(self):

        localctx = VerilogParser.Binary_module_path_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 608, self.RULE_binary_module_path_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4071
            _la = self._input.LA(1)
            if not(((((_la - 304)) & ~0x3f) == 0 and ((1 << (_la - 304)) & ((1 << (VerilogParser.AMPERSAND - 304)) | (1 << (VerilogParser.VERTICAL_BAR - 304)) | (1 << (VerilogParser.CARET - 304)) | (1 << (VerilogParser.TILDE_CARET - 304)) | (1 << (VerilogParser.CARET_TILDE - 304)) | (1 << (VerilogParser.DOUBLE_EQUAL - 304)) | (1 << (VerilogParser.EXCLAMATION_MARK_EQUAL - 304)) | (1 << (VerilogParser.DOUBLE_AMPERSAND - 304)) | (1 << (VerilogParser.DOUBLE_VERTICAL_BAR - 304)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class NumberContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(VerilogParser.DECIMAL_NUMBER, 0)

        def OCTAL_NUMBER(self):
            return self.getToken(VerilogParser.OCTAL_NUMBER, 0)

        def BINARY_NUMBER(self):
            return self.getToken(VerilogParser.BINARY_NUMBER, 0)

        def HEX_NUMBER(self):
            return self.getToken(VerilogParser.HEX_NUMBER, 0)

        def REAL_NUMBER(self):
            return self.getToken(VerilogParser.REAL_NUMBER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNumber" ):
                listener.enterNumber(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNumber" ):
                listener.exitNumber(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNumber" ):
                return visitor.visitNumber(self)
            else:
                return visitor.visitChildren(self)




    def number(self):

        localctx = VerilogParser.NumberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 610, self.RULE_number)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4073
            _la = self._input.LA(1)
            if not(((((_la - 282)) & ~0x3f) == 0 and ((1 << (_la - 282)) & ((1 << (VerilogParser.REAL_NUMBER - 282)) | (1 << (VerilogParser.DECIMAL_NUMBER - 282)) | (1 << (VerilogParser.BINARY_NUMBER - 282)) | (1 << (VerilogParser.OCTAL_NUMBER - 282)) | (1 << (VerilogParser.HEX_NUMBER - 282)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attribute_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LEFT_PARENTHESIS(self):
            return self.getToken(VerilogParser.LEFT_PARENTHESIS, 0)

        def ASTERISK(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.ASTERISK)
            else:
                return self.getToken(VerilogParser.ASTERISK, i)

        def attr_spec(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Attr_specContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Attr_specContext,i)


        def RIGHT_PARENTHESIS(self):
            return self.getToken(VerilogParser.RIGHT_PARENTHESIS, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.COMMA)
            else:
                return self.getToken(VerilogParser.COMMA, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_attribute_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttribute_instance" ):
                listener.enterAttribute_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttribute_instance" ):
                listener.exitAttribute_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttribute_instance" ):
                return visitor.visitAttribute_instance(self)
            else:
                return visitor.visitChildren(self)




    def attribute_instance(self):

        localctx = VerilogParser.Attribute_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 612, self.RULE_attribute_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4075
            self.match(VerilogParser.LEFT_PARENTHESIS)
            self.state = 4076
            self.match(VerilogParser.ASTERISK)
            self.state = 4077
            self.attr_spec()
            self.state = 4082
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==VerilogParser.COMMA:
                self.state = 4078
                self.match(VerilogParser.COMMA)
                self.state = 4079
                self.attr_spec()
                self.state = 4084
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4085
            self.match(VerilogParser.ASTERISK)
            self.state = 4086
            self.match(VerilogParser.RIGHT_PARENTHESIS)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_specContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_name(self):
            return self.getTypedRuleContext(VerilogParser.Attr_nameContext,0)


        def EQUAL(self):
            return self.getToken(VerilogParser.EQUAL, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_attr_spec

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_spec" ):
                listener.enterAttr_spec(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_spec" ):
                listener.exitAttr_spec(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_spec" ):
                return visitor.visitAttr_spec(self)
            else:
                return visitor.visitChildren(self)




    def attr_spec(self):

        localctx = VerilogParser.Attr_specContext(self, self._ctx, self.state)
        self.enterRule(localctx, 614, self.RULE_attr_spec)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4088
            self.attr_name()
            self.state = 4091
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==VerilogParser.EQUAL:
                self.state = 4089
                self.match(VerilogParser.EQUAL)
                self.state = 4090
                self.constant_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_attr_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_name" ):
                listener.enterAttr_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_name" ):
                listener.exitAttr_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_name" ):
                return visitor.visitAttr_name(self)
            else:
                return visitor.visitChildren(self)




    def attr_name(self):

        localctx = VerilogParser.Attr_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 616, self.RULE_attr_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4093
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_identifier" ):
                listener.enterBlock_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_identifier" ):
                listener.exitBlock_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_identifier" ):
                return visitor.visitBlock_identifier(self)
            else:
                return visitor.visitChildren(self)




    def block_identifier(self):

        localctx = VerilogParser.Block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 618, self.RULE_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4095
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cell_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_cell_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCell_identifier" ):
                listener.enterCell_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCell_identifier" ):
                listener.exitCell_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCell_identifier" ):
                return visitor.visitCell_identifier(self)
            else:
                return visitor.visitChildren(self)




    def cell_identifier(self):

        localctx = VerilogParser.Cell_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 620, self.RULE_cell_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4097
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Config_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_config_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_identifier" ):
                listener.enterConfig_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_identifier" ):
                listener.exitConfig_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_identifier" ):
                return visitor.visitConfig_identifier(self)
            else:
                return visitor.visitChildren(self)




    def config_identifier(self):

        localctx = VerilogParser.Config_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 622, self.RULE_config_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4099
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_event_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_identifier" ):
                listener.enterEvent_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_identifier" ):
                listener.exitEvent_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_identifier" ):
                return visitor.visitEvent_identifier(self)
            else:
                return visitor.visitChildren(self)




    def event_identifier(self):

        localctx = VerilogParser.Event_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 624, self.RULE_event_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4101
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_identifier" ):
                listener.enterFunction_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_identifier" ):
                listener.exitFunction_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_identifier" ):
                return visitor.visitFunction_identifier(self)
            else:
                return visitor.visitChildren(self)




    def function_identifier(self):

        localctx = VerilogParser.Function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 626, self.RULE_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4103
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Gate_instance_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_gate_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGate_instance_identifier" ):
                listener.enterGate_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGate_instance_identifier" ):
                listener.exitGate_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGate_instance_identifier" ):
                return visitor.visitGate_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def gate_instance_identifier(self):

        localctx = VerilogParser.Gate_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 628, self.RULE_gate_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4105
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_block_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_generate_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block_identifier" ):
                listener.enterGenerate_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block_identifier" ):
                listener.exitGenerate_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block_identifier" ):
                return visitor.visitGenerate_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def generate_block_identifier(self):

        localctx = VerilogParser.Generate_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 630, self.RULE_generate_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4107
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_genvar_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_identifier" ):
                listener.enterGenvar_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_identifier" ):
                listener.exitGenvar_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_identifier" ):
                return visitor.visitGenvar_identifier(self)
            else:
                return visitor.visitChildren(self)




    def genvar_identifier(self):

        localctx = VerilogParser.Genvar_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 632, self.RULE_genvar_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4109
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_block_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_block_identifier" ):
                listener.enterHierarchical_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_block_identifier" ):
                listener.exitHierarchical_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_block_identifier" ):
                return visitor.visitHierarchical_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_block_identifier(self):

        localctx = VerilogParser.Hierarchical_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 634, self.RULE_hierarchical_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4111
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_event_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_event_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_event_identifier" ):
                listener.enterHierarchical_event_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_event_identifier" ):
                listener.exitHierarchical_event_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_event_identifier" ):
                return visitor.visitHierarchical_event_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_event_identifier(self):

        localctx = VerilogParser.Hierarchical_event_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 636, self.RULE_hierarchical_event_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4113
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_function_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_function_identifier" ):
                listener.enterHierarchical_function_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_function_identifier" ):
                listener.exitHierarchical_function_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_function_identifier" ):
                return visitor.visitHierarchical_function_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_function_identifier(self):

        localctx = VerilogParser.Hierarchical_function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 638, self.RULE_hierarchical_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4115
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.IdentifierContext)
            else:
                return self.getTypedRuleContext(VerilogParser.IdentifierContext,i)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.DOT)
            else:
                return self.getToken(VerilogParser.DOT, i)

        def LEFT_BRACKET(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.LEFT_BRACKET)
            else:
                return self.getToken(VerilogParser.LEFT_BRACKET, i)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(VerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(VerilogParser.Constant_expressionContext,i)


        def RIGHT_BRACKET(self, i:int=None):
            if i is None:
                return self.getTokens(VerilogParser.RIGHT_BRACKET)
            else:
                return self.getToken(VerilogParser.RIGHT_BRACKET, i)

        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_identifier" ):
                listener.enterHierarchical_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_identifier" ):
                listener.exitHierarchical_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_identifier" ):
                return visitor.visitHierarchical_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_identifier(self):

        localctx = VerilogParser.Hierarchical_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 640, self.RULE_hierarchical_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4128
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,415,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 4117
                    self.identifier()
                    self.state = 4122
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==VerilogParser.LEFT_BRACKET:
                        self.state = 4118
                        self.match(VerilogParser.LEFT_BRACKET)
                        self.state = 4119
                        self.constant_expression(0)
                        self.state = 4120
                        self.match(VerilogParser.RIGHT_BRACKET)


                    self.state = 4124
                    self.match(VerilogParser.DOT) 
                self.state = 4130
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,415,self._ctx)

            self.state = 4131
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_net_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_net_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_net_identifier" ):
                listener.enterHierarchical_net_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_net_identifier" ):
                listener.exitHierarchical_net_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_net_identifier" ):
                return visitor.visitHierarchical_net_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_net_identifier(self):

        localctx = VerilogParser.Hierarchical_net_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 642, self.RULE_hierarchical_net_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4133
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_parameter_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_parameter_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_parameter_identifier" ):
                listener.enterHierarchical_parameter_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_parameter_identifier" ):
                listener.exitHierarchical_parameter_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_parameter_identifier" ):
                return visitor.visitHierarchical_parameter_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_parameter_identifier(self):

        localctx = VerilogParser.Hierarchical_parameter_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 644, self.RULE_hierarchical_parameter_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4135
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_variable_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_variable_identifier" ):
                listener.enterHierarchical_variable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_variable_identifier" ):
                listener.exitHierarchical_variable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_variable_identifier" ):
                return visitor.visitHierarchical_variable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_variable_identifier(self):

        localctx = VerilogParser.Hierarchical_variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 646, self.RULE_hierarchical_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4137
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_task_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(VerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_hierarchical_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_task_identifier" ):
                listener.enterHierarchical_task_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_task_identifier" ):
                listener.exitHierarchical_task_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_task_identifier" ):
                return visitor.visitHierarchical_task_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_task_identifier(self):

        localctx = VerilogParser.Hierarchical_task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 648, self.RULE_hierarchical_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4139
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class IdentifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SIMPLE_IDENTIFIER(self):
            return self.getToken(VerilogParser.SIMPLE_IDENTIFIER, 0)

        def ESCAPED_IDENTIFIER(self):
            return self.getToken(VerilogParser.ESCAPED_IDENTIFIER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIdentifier" ):
                listener.enterIdentifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIdentifier" ):
                listener.exitIdentifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIdentifier" ):
                return visitor.visitIdentifier(self)
            else:
                return visitor.visitChildren(self)




    def identifier(self):

        localctx = VerilogParser.IdentifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 650, self.RULE_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4141
            _la = self._input.LA(1)
            if not(_la==VerilogParser.ESCAPED_IDENTIFIER or _la==VerilogParser.SIMPLE_IDENTIFIER):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_inout_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_port_identifier" ):
                listener.enterInout_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_port_identifier" ):
                listener.exitInout_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_port_identifier" ):
                return visitor.visitInout_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def inout_port_identifier(self):

        localctx = VerilogParser.Inout_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 652, self.RULE_inout_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4143
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_input_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_port_identifier" ):
                listener.enterInput_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_port_identifier" ):
                listener.exitInput_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_port_identifier" ):
                return visitor.visitInput_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def input_port_identifier(self):

        localctx = VerilogParser.Input_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 654, self.RULE_input_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4145
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Instance_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInstance_identifier" ):
                listener.enterInstance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInstance_identifier" ):
                listener.exitInstance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInstance_identifier" ):
                return visitor.visitInstance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def instance_identifier(self):

        localctx = VerilogParser.Instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 656, self.RULE_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4147
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Library_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_library_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_identifier" ):
                listener.enterLibrary_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_identifier" ):
                listener.exitLibrary_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_identifier" ):
                return visitor.visitLibrary_identifier(self)
            else:
                return visitor.visitChildren(self)




    def library_identifier(self):

        localctx = VerilogParser.Library_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 658, self.RULE_library_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4149
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_identifier" ):
                listener.enterModule_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_identifier" ):
                listener.exitModule_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_identifier" ):
                return visitor.visitModule_identifier(self)
            else:
                return visitor.visitChildren(self)




    def module_identifier(self):

        localctx = VerilogParser.Module_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 660, self.RULE_module_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4151
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_instance_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_module_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instance_identifier" ):
                listener.enterModule_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instance_identifier" ):
                listener.exitModule_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instance_identifier" ):
                return visitor.visitModule_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def module_instance_identifier(self):

        localctx = VerilogParser.Module_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 662, self.RULE_module_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4153
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_net_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_identifier" ):
                listener.enterNet_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_identifier" ):
                listener.exitNet_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_identifier" ):
                return visitor.visitNet_identifier(self)
            else:
                return visitor.visitChildren(self)




    def net_identifier(self):

        localctx = VerilogParser.Net_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 664, self.RULE_net_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4155
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_output_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_port_identifier" ):
                listener.enterOutput_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_port_identifier" ):
                listener.exitOutput_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_port_identifier" ):
                return visitor.visitOutput_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def output_port_identifier(self):

        localctx = VerilogParser.Output_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 666, self.RULE_output_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4157
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_parameter_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_identifier" ):
                listener.enterParameter_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_identifier" ):
                listener.exitParameter_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_identifier" ):
                return visitor.visitParameter_identifier(self)
            else:
                return visitor.visitChildren(self)




    def parameter_identifier(self):

        localctx = VerilogParser.Parameter_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 668, self.RULE_parameter_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4159
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_identifier" ):
                listener.enterPort_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_identifier" ):
                listener.exitPort_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_identifier" ):
                return visitor.visitPort_identifier(self)
            else:
                return visitor.visitChildren(self)




    def port_identifier(self):

        localctx = VerilogParser.Port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 670, self.RULE_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4161
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Real_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_real_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_identifier" ):
                listener.enterReal_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_identifier" ):
                listener.exitReal_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_identifier" ):
                return visitor.visitReal_identifier(self)
            else:
                return visitor.visitChildren(self)




    def real_identifier(self):

        localctx = VerilogParser.Real_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 672, self.RULE_real_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4163
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specparam_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_specparam_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_identifier" ):
                listener.enterSpecparam_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_identifier" ):
                listener.exitSpecparam_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_identifier" ):
                return visitor.visitSpecparam_identifier(self)
            else:
                return visitor.visitChildren(self)




    def specparam_identifier(self):

        localctx = VerilogParser.Specparam_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 674, self.RULE_specparam_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4165
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_function_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SYSTEM_TF_IDENTIFIER(self):
            return self.getToken(VerilogParser.SYSTEM_TF_IDENTIFIER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_system_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_function_identifier" ):
                listener.enterSystem_function_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_function_identifier" ):
                listener.exitSystem_function_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_function_identifier" ):
                return visitor.visitSystem_function_identifier(self)
            else:
                return visitor.visitChildren(self)




    def system_function_identifier(self):

        localctx = VerilogParser.System_function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 676, self.RULE_system_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4167
            self.match(VerilogParser.SYSTEM_TF_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_task_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SYSTEM_TF_IDENTIFIER(self):
            return self.getToken(VerilogParser.SYSTEM_TF_IDENTIFIER, 0)

        def getRuleIndex(self):
            return VerilogParser.RULE_system_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_task_identifier" ):
                listener.enterSystem_task_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_task_identifier" ):
                listener.exitSystem_task_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_task_identifier" ):
                return visitor.visitSystem_task_identifier(self)
            else:
                return visitor.visitChildren(self)




    def system_task_identifier(self):

        localctx = VerilogParser.System_task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 678, self.RULE_system_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4169
            self.match(VerilogParser.SYSTEM_TF_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_identifier" ):
                listener.enterTask_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_identifier" ):
                listener.exitTask_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_identifier" ):
                return visitor.visitTask_identifier(self)
            else:
                return visitor.visitChildren(self)




    def task_identifier(self):

        localctx = VerilogParser.Task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 680, self.RULE_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4171
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Terminal_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_terminal_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTerminal_identifier" ):
                listener.enterTerminal_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTerminal_identifier" ):
                listener.exitTerminal_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTerminal_identifier" ):
                return visitor.visitTerminal_identifier(self)
            else:
                return visitor.visitChildren(self)




    def terminal_identifier(self):

        localctx = VerilogParser.Terminal_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 682, self.RULE_terminal_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4173
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Topmodule_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_topmodule_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTopmodule_identifier" ):
                listener.enterTopmodule_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTopmodule_identifier" ):
                listener.exitTopmodule_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTopmodule_identifier" ):
                return visitor.visitTopmodule_identifier(self)
            else:
                return visitor.visitChildren(self)




    def topmodule_identifier(self):

        localctx = VerilogParser.Topmodule_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 684, self.RULE_topmodule_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4175
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Udp_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_identifier" ):
                listener.enterUdp_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_identifier" ):
                listener.exitUdp_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_identifier" ):
                return visitor.visitUdp_identifier(self)
            else:
                return visitor.visitChildren(self)




    def udp_identifier(self):

        localctx = VerilogParser.Udp_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 686, self.RULE_udp_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4177
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Udp_instance_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_udp_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUdp_instance_identifier" ):
                listener.enterUdp_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUdp_instance_identifier" ):
                listener.exitUdp_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUdp_instance_identifier" ):
                return visitor.visitUdp_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def udp_instance_identifier(self):

        localctx = VerilogParser.Udp_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 688, self.RULE_udp_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4179
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(VerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return VerilogParser.RULE_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_identifier" ):
                listener.enterVariable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_identifier" ):
                listener.exitVariable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_identifier" ):
                return visitor.visitVariable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def variable_identifier(self):

        localctx = VerilogParser.Variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 690, self.RULE_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4181
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx



    def sempred(self, localctx:RuleContext, ruleIndex:int, predIndex:int):
        if self._predicates == None:
            self._predicates = dict()
        self._predicates[194] = self.genvar_expression_sempred
        self._predicates[221] = self.event_expression_sempred
        self._predicates[284] = self.constant_expression_sempred
        self._predicates[288] = self.expression_sempred
        self._predicates[291] = self.module_path_expression_sempred
        pred = self._predicates.get(ruleIndex, None)
        if pred is None:
            raise Exception("No predicate with index:" + str(ruleIndex))
        else:
            return pred(localctx, predIndex)

    def genvar_expression_sempred(self, localctx:Genvar_expressionContext, predIndex:int):
            if predIndex == 0:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 1:
                return self.precpred(self._ctx, 1)
         

    def event_expression_sempred(self, localctx:Event_expressionContext, predIndex:int):
            if predIndex == 2:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 3:
                return self.precpred(self._ctx, 1)
         

    def constant_expression_sempred(self, localctx:Constant_expressionContext, predIndex:int):
            if predIndex == 4:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 5:
                return self.precpred(self._ctx, 1)
         

    def expression_sempred(self, localctx:ExpressionContext, predIndex:int):
            if predIndex == 6:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 7:
                return self.precpred(self._ctx, 1)
         

    def module_path_expression_sempred(self, localctx:Module_path_expressionContext, predIndex:int):
            if predIndex == 8:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 9:
                return self.precpred(self._ctx, 1)
         




