# Generated from SysVerilogHDL.g4 by ANTLR 4.8
from antlr4 import *
if __name__ is not None and "." in __name__:
    from .SysVerilogHDLParser import SysVerilogHDLParser
else:
    from SysVerilogHDLParser import SysVerilogHDLParser

# This class defines a complete listener for a parse tree produced by SysVerilogHDLParser.
class SysVerilogHDLListener(ParseTreeListener):

    # Enter a parse tree produced by SysVerilogHDLParser#module_keyword.
    def enterModule_keyword(self, ctx:SysVerilogHDLParser.Module_keywordContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_keyword.
    def exitModule_keyword(self, ctx:SysVerilogHDLParser.Module_keywordContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#struct_keyword.
    def enterStruct_keyword(self, ctx:SysVerilogHDLParser.Struct_keywordContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#struct_keyword.
    def exitStruct_keyword(self, ctx:SysVerilogHDLParser.Struct_keywordContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#any_case_keyword.
    def enterAny_case_keyword(self, ctx:SysVerilogHDLParser.Any_case_keywordContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#any_case_keyword.
    def exitAny_case_keyword(self, ctx:SysVerilogHDLParser.Any_case_keywordContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#semicolon.
    def enterSemicolon(self, ctx:SysVerilogHDLParser.SemicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#semicolon.
    def exitSemicolon(self, ctx:SysVerilogHDLParser.SemicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#unary_operator.
    def enterUnary_operator(self, ctx:SysVerilogHDLParser.Unary_operatorContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#unary_operator.
    def exitUnary_operator(self, ctx:SysVerilogHDLParser.Unary_operatorContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#binary_operator.
    def enterBinary_operator(self, ctx:SysVerilogHDLParser.Binary_operatorContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#binary_operator.
    def exitBinary_operator(self, ctx:SysVerilogHDLParser.Binary_operatorContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#unary_assign_operator.
    def enterUnary_assign_operator(self, ctx:SysVerilogHDLParser.Unary_assign_operatorContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#unary_assign_operator.
    def exitUnary_assign_operator(self, ctx:SysVerilogHDLParser.Unary_assign_operatorContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#binary_assign_operator.
    def enterBinary_assign_operator(self, ctx:SysVerilogHDLParser.Binary_assign_operatorContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#binary_assign_operator.
    def exitBinary_assign_operator(self, ctx:SysVerilogHDLParser.Binary_assign_operatorContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#source_text.
    def enterSource_text(self, ctx:SysVerilogHDLParser.Source_textContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#source_text.
    def exitSource_text(self, ctx:SysVerilogHDLParser.Source_textContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#description_star.
    def enterDescription_star(self, ctx:SysVerilogHDLParser.Description_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#description_star.
    def exitDescription_star(self, ctx:SysVerilogHDLParser.Description_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#header_text.
    def enterHeader_text(self, ctx:SysVerilogHDLParser.Header_textContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#header_text.
    def exitHeader_text(self, ctx:SysVerilogHDLParser.Header_textContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#design_attribute.
    def enterDesign_attribute(self, ctx:SysVerilogHDLParser.Design_attributeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#design_attribute.
    def exitDesign_attribute(self, ctx:SysVerilogHDLParser.Design_attributeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#compiler_directive.
    def enterCompiler_directive(self, ctx:SysVerilogHDLParser.Compiler_directiveContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#compiler_directive.
    def exitCompiler_directive(self, ctx:SysVerilogHDLParser.Compiler_directiveContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#description.
    def enterDescription(self, ctx:SysVerilogHDLParser.DescriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#description.
    def exitDescription(self, ctx:SysVerilogHDLParser.DescriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_declaration.
    def enterModule_declaration(self, ctx:SysVerilogHDLParser.Module_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_declaration.
    def exitModule_declaration(self, ctx:SysVerilogHDLParser.Module_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_identifier.
    def enterModule_identifier(self, ctx:SysVerilogHDLParser.Module_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_identifier.
    def exitModule_identifier(self, ctx:SysVerilogHDLParser.Module_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_interface.
    def enterModule_interface(self, ctx:SysVerilogHDLParser.Module_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_interface.
    def exitModule_interface(self, ctx:SysVerilogHDLParser.Module_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_parameter_interface.
    def enterModule_parameter_interface(self, ctx:SysVerilogHDLParser.Module_parameter_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_parameter_interface.
    def exitModule_parameter_interface(self, ctx:SysVerilogHDLParser.Module_parameter_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_port_interface.
    def enterModule_port_interface(self, ctx:SysVerilogHDLParser.Module_port_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_port_interface.
    def exitModule_port_interface(self, ctx:SysVerilogHDLParser.Module_port_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_item_star.
    def enterModule_item_star(self, ctx:SysVerilogHDLParser.Module_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_item_star.
    def exitModule_item_star(self, ctx:SysVerilogHDLParser.Module_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_item.
    def enterModule_item(self, ctx:SysVerilogHDLParser.Module_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_item.
    def exitModule_item(self, ctx:SysVerilogHDLParser.Module_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#colon_module_identifier.
    def enterColon_module_identifier(self, ctx:SysVerilogHDLParser.Colon_module_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#colon_module_identifier.
    def exitColon_module_identifier(self, ctx:SysVerilogHDLParser.Colon_module_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#package_declaration.
    def enterPackage_declaration(self, ctx:SysVerilogHDLParser.Package_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#package_declaration.
    def exitPackage_declaration(self, ctx:SysVerilogHDLParser.Package_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#package_identifier.
    def enterPackage_identifier(self, ctx:SysVerilogHDLParser.Package_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#package_identifier.
    def exitPackage_identifier(self, ctx:SysVerilogHDLParser.Package_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#colon_package_identifier.
    def enterColon_package_identifier(self, ctx:SysVerilogHDLParser.Colon_package_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#colon_package_identifier.
    def exitColon_package_identifier(self, ctx:SysVerilogHDLParser.Colon_package_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#package_item_star.
    def enterPackage_item_star(self, ctx:SysVerilogHDLParser.Package_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#package_item_star.
    def exitPackage_item_star(self, ctx:SysVerilogHDLParser.Package_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#package_item.
    def enterPackage_item(self, ctx:SysVerilogHDLParser.Package_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#package_item.
    def exitPackage_item(self, ctx:SysVerilogHDLParser.Package_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#import_package.
    def enterImport_package(self, ctx:SysVerilogHDLParser.Import_packageContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#import_package.
    def exitImport_package(self, ctx:SysVerilogHDLParser.Import_packageContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#package_item_identifier.
    def enterPackage_item_identifier(self, ctx:SysVerilogHDLParser.Package_item_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#package_item_identifier.
    def exitPackage_item_identifier(self, ctx:SysVerilogHDLParser.Package_item_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#parameter_item_semicolon.
    def enterParameter_item_semicolon(self, ctx:SysVerilogHDLParser.Parameter_item_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#parameter_item_semicolon.
    def exitParameter_item_semicolon(self, ctx:SysVerilogHDLParser.Parameter_item_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#parameter_item.
    def enterParameter_item(self, ctx:SysVerilogHDLParser.Parameter_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#parameter_item.
    def exitParameter_item(self, ctx:SysVerilogHDLParser.Parameter_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_port_item_semicolon.
    def enterAttr_port_item_semicolon(self, ctx:SysVerilogHDLParser.Attr_port_item_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_port_item_semicolon.
    def exitAttr_port_item_semicolon(self, ctx:SysVerilogHDLParser.Attr_port_item_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_variable_item_semicolon.
    def enterAttr_variable_item_semicolon(self, ctx:SysVerilogHDLParser.Attr_variable_item_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_variable_item_semicolon.
    def exitAttr_variable_item_semicolon(self, ctx:SysVerilogHDLParser.Attr_variable_item_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_item.
    def enterVariable_item(self, ctx:SysVerilogHDLParser.Variable_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_item.
    def exitVariable_item(self, ctx:SysVerilogHDLParser.Variable_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#subroutine_item_semicolon.
    def enterSubroutine_item_semicolon(self, ctx:SysVerilogHDLParser.Subroutine_item_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#subroutine_item_semicolon.
    def exitSubroutine_item_semicolon(self, ctx:SysVerilogHDLParser.Subroutine_item_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#subroutine_item.
    def enterSubroutine_item(self, ctx:SysVerilogHDLParser.Subroutine_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#subroutine_item.
    def exitSubroutine_item(self, ctx:SysVerilogHDLParser.Subroutine_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_construct_item.
    def enterAttr_construct_item(self, ctx:SysVerilogHDLParser.Attr_construct_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_construct_item.
    def exitAttr_construct_item(self, ctx:SysVerilogHDLParser.Attr_construct_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#construct_item.
    def enterConstruct_item(self, ctx:SysVerilogHDLParser.Construct_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#construct_item.
    def exitConstruct_item(self, ctx:SysVerilogHDLParser.Construct_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_component_item.
    def enterAttr_component_item(self, ctx:SysVerilogHDLParser.Attr_component_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_component_item.
    def exitAttr_component_item(self, ctx:SysVerilogHDLParser.Attr_component_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#component_item.
    def enterComponent_item(self, ctx:SysVerilogHDLParser.Component_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#component_item.
    def exitComponent_item(self, ctx:SysVerilogHDLParser.Component_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#compiler_item.
    def enterCompiler_item(self, ctx:SysVerilogHDLParser.Compiler_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#compiler_item.
    def exitCompiler_item(self, ctx:SysVerilogHDLParser.Compiler_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#type_item.
    def enterType_item(self, ctx:SysVerilogHDLParser.Type_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#type_item.
    def exitType_item(self, ctx:SysVerilogHDLParser.Type_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#null_item.
    def enterNull_item(self, ctx:SysVerilogHDLParser.Null_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#null_item.
    def exitNull_item(self, ctx:SysVerilogHDLParser.Null_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_interface_parameters.
    def enterList_of_interface_parameters(self, ctx:SysVerilogHDLParser.List_of_interface_parametersContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_interface_parameters.
    def exitList_of_interface_parameters(self, ctx:SysVerilogHDLParser.List_of_interface_parametersContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_parameter_declarations.
    def enterList_of_parameter_declarations(self, ctx:SysVerilogHDLParser.List_of_parameter_declarationsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_parameter_declarations.
    def exitList_of_parameter_declarations(self, ctx:SysVerilogHDLParser.List_of_parameter_declarationsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_parameter_declaration_star.
    def enterComma_parameter_declaration_star(self, ctx:SysVerilogHDLParser.Comma_parameter_declaration_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_parameter_declaration_star.
    def exitComma_parameter_declaration_star(self, ctx:SysVerilogHDLParser.Comma_parameter_declaration_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_parameter_declaration.
    def enterComma_parameter_declaration(self, ctx:SysVerilogHDLParser.Comma_parameter_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_parameter_declaration.
    def exitComma_parameter_declaration(self, ctx:SysVerilogHDLParser.Comma_parameter_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_parameter_descriptions.
    def enterList_of_parameter_descriptions(self, ctx:SysVerilogHDLParser.List_of_parameter_descriptionsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_parameter_descriptions.
    def exitList_of_parameter_descriptions(self, ctx:SysVerilogHDLParser.List_of_parameter_descriptionsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#param_declaration.
    def enterParam_declaration(self, ctx:SysVerilogHDLParser.Param_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#param_declaration.
    def exitParam_declaration(self, ctx:SysVerilogHDLParser.Param_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#param_description.
    def enterParam_description(self, ctx:SysVerilogHDLParser.Param_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#param_description.
    def exitParam_description(self, ctx:SysVerilogHDLParser.Param_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#parameter_declaration.
    def enterParameter_declaration(self, ctx:SysVerilogHDLParser.Parameter_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#parameter_declaration.
    def exitParameter_declaration(self, ctx:SysVerilogHDLParser.Parameter_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#local_parameter_declaration.
    def enterLocal_parameter_declaration(self, ctx:SysVerilogHDLParser.Local_parameter_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#local_parameter_declaration.
    def exitLocal_parameter_declaration(self, ctx:SysVerilogHDLParser.Local_parameter_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#parameter_override.
    def enterParameter_override(self, ctx:SysVerilogHDLParser.Parameter_overrideContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#parameter_override.
    def exitParameter_override(self, ctx:SysVerilogHDLParser.Parameter_overrideContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_tf_interface_ports.
    def enterList_of_tf_interface_ports(self, ctx:SysVerilogHDLParser.List_of_tf_interface_portsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_tf_interface_ports.
    def exitList_of_tf_interface_ports(self, ctx:SysVerilogHDLParser.List_of_tf_interface_portsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_tf_port_declarations.
    def enterList_of_tf_port_declarations(self, ctx:SysVerilogHDLParser.List_of_tf_port_declarationsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_tf_port_declarations.
    def exitList_of_tf_port_declarations(self, ctx:SysVerilogHDLParser.List_of_tf_port_declarationsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_tf_port_declarations_comma.
    def enterList_of_tf_port_declarations_comma(self, ctx:SysVerilogHDLParser.List_of_tf_port_declarations_commaContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_tf_port_declarations_comma.
    def exitList_of_tf_port_declarations_comma(self, ctx:SysVerilogHDLParser.List_of_tf_port_declarations_commaContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_attr_tf_port_declaration_star.
    def enterComma_attr_tf_port_declaration_star(self, ctx:SysVerilogHDLParser.Comma_attr_tf_port_declaration_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_attr_tf_port_declaration_star.
    def exitComma_attr_tf_port_declaration_star(self, ctx:SysVerilogHDLParser.Comma_attr_tf_port_declaration_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_attr_tf_port_declaration.
    def enterComma_attr_tf_port_declaration(self, ctx:SysVerilogHDLParser.Comma_attr_tf_port_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_attr_tf_port_declaration.
    def exitComma_attr_tf_port_declaration(self, ctx:SysVerilogHDLParser.Comma_attr_tf_port_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_tf_port_declarations_semicolon.
    def enterList_of_tf_port_declarations_semicolon(self, ctx:SysVerilogHDLParser.List_of_tf_port_declarations_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_tf_port_declarations_semicolon.
    def exitList_of_tf_port_declarations_semicolon(self, ctx:SysVerilogHDLParser.List_of_tf_port_declarations_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_tf_port_declaration_semicolon_plus.
    def enterAttr_tf_port_declaration_semicolon_plus(self, ctx:SysVerilogHDLParser.Attr_tf_port_declaration_semicolon_plusContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_tf_port_declaration_semicolon_plus.
    def exitAttr_tf_port_declaration_semicolon_plus(self, ctx:SysVerilogHDLParser.Attr_tf_port_declaration_semicolon_plusContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_tf_port_declaration_semicolon_star.
    def enterAttr_tf_port_declaration_semicolon_star(self, ctx:SysVerilogHDLParser.Attr_tf_port_declaration_semicolon_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_tf_port_declaration_semicolon_star.
    def exitAttr_tf_port_declaration_semicolon_star(self, ctx:SysVerilogHDLParser.Attr_tf_port_declaration_semicolon_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_tf_port_declaration_semicolon.
    def enterAttr_tf_port_declaration_semicolon(self, ctx:SysVerilogHDLParser.Attr_tf_port_declaration_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_tf_port_declaration_semicolon.
    def exitAttr_tf_port_declaration_semicolon(self, ctx:SysVerilogHDLParser.Attr_tf_port_declaration_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_tf_port_declaration.
    def enterAttr_tf_port_declaration(self, ctx:SysVerilogHDLParser.Attr_tf_port_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_tf_port_declaration.
    def exitAttr_tf_port_declaration(self, ctx:SysVerilogHDLParser.Attr_tf_port_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#tf_port_declaration.
    def enterTf_port_declaration(self, ctx:SysVerilogHDLParser.Tf_port_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#tf_port_declaration.
    def exitTf_port_declaration(self, ctx:SysVerilogHDLParser.Tf_port_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_interface_ports.
    def enterList_of_interface_ports(self, ctx:SysVerilogHDLParser.List_of_interface_portsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_interface_ports.
    def exitList_of_interface_ports(self, ctx:SysVerilogHDLParser.List_of_interface_portsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_port_identifiers.
    def enterList_of_port_identifiers(self, ctx:SysVerilogHDLParser.List_of_port_identifiersContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_port_identifiers.
    def exitList_of_port_identifiers(self, ctx:SysVerilogHDLParser.List_of_port_identifiersContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_port_identifier_star.
    def enterComma_port_identifier_star(self, ctx:SysVerilogHDLParser.Comma_port_identifier_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_port_identifier_star.
    def exitComma_port_identifier_star(self, ctx:SysVerilogHDLParser.Comma_port_identifier_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_port_identifier.
    def enterComma_port_identifier(self, ctx:SysVerilogHDLParser.Comma_port_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_port_identifier.
    def exitComma_port_identifier(self, ctx:SysVerilogHDLParser.Comma_port_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#port_identifier.
    def enterPort_identifier(self, ctx:SysVerilogHDLParser.Port_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#port_identifier.
    def exitPort_identifier(self, ctx:SysVerilogHDLParser.Port_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_port_declarations.
    def enterList_of_port_declarations(self, ctx:SysVerilogHDLParser.List_of_port_declarationsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_port_declarations.
    def exitList_of_port_declarations(self, ctx:SysVerilogHDLParser.List_of_port_declarationsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_port_declarations_comma.
    def enterList_of_port_declarations_comma(self, ctx:SysVerilogHDLParser.List_of_port_declarations_commaContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_port_declarations_comma.
    def exitList_of_port_declarations_comma(self, ctx:SysVerilogHDLParser.List_of_port_declarations_commaContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_attr_port_declaration_star.
    def enterComma_attr_port_declaration_star(self, ctx:SysVerilogHDLParser.Comma_attr_port_declaration_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_attr_port_declaration_star.
    def exitComma_attr_port_declaration_star(self, ctx:SysVerilogHDLParser.Comma_attr_port_declaration_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_attr_port_declaration.
    def enterComma_attr_port_declaration(self, ctx:SysVerilogHDLParser.Comma_attr_port_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_attr_port_declaration.
    def exitComma_attr_port_declaration(self, ctx:SysVerilogHDLParser.Comma_attr_port_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_port_declarations_semicolon.
    def enterList_of_port_declarations_semicolon(self, ctx:SysVerilogHDLParser.List_of_port_declarations_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_port_declarations_semicolon.
    def exitList_of_port_declarations_semicolon(self, ctx:SysVerilogHDLParser.List_of_port_declarations_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_port_declaration_semicolon_plus.
    def enterAttr_port_declaration_semicolon_plus(self, ctx:SysVerilogHDLParser.Attr_port_declaration_semicolon_plusContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_port_declaration_semicolon_plus.
    def exitAttr_port_declaration_semicolon_plus(self, ctx:SysVerilogHDLParser.Attr_port_declaration_semicolon_plusContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_port_declaration_semicolon_star.
    def enterAttr_port_declaration_semicolon_star(self, ctx:SysVerilogHDLParser.Attr_port_declaration_semicolon_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_port_declaration_semicolon_star.
    def exitAttr_port_declaration_semicolon_star(self, ctx:SysVerilogHDLParser.Attr_port_declaration_semicolon_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_port_declaration_semicolon.
    def enterAttr_port_declaration_semicolon(self, ctx:SysVerilogHDLParser.Attr_port_declaration_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_port_declaration_semicolon.
    def exitAttr_port_declaration_semicolon(self, ctx:SysVerilogHDLParser.Attr_port_declaration_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_port_declaration.
    def enterAttr_port_declaration(self, ctx:SysVerilogHDLParser.Attr_port_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_port_declaration.
    def exitAttr_port_declaration(self, ctx:SysVerilogHDLParser.Attr_port_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#port_declaration.
    def enterPort_declaration(self, ctx:SysVerilogHDLParser.Port_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#port_declaration.
    def exitPort_declaration(self, ctx:SysVerilogHDLParser.Port_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#port_description.
    def enterPort_description(self, ctx:SysVerilogHDLParser.Port_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#port_description.
    def exitPort_description(self, ctx:SysVerilogHDLParser.Port_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#inout_description.
    def enterInout_description(self, ctx:SysVerilogHDLParser.Inout_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#inout_description.
    def exitInout_description(self, ctx:SysVerilogHDLParser.Inout_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#input_description.
    def enterInput_description(self, ctx:SysVerilogHDLParser.Input_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#input_description.
    def exitInput_description(self, ctx:SysVerilogHDLParser.Input_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#output_description.
    def enterOutput_description(self, ctx:SysVerilogHDLParser.Output_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#output_description.
    def exitOutput_description(self, ctx:SysVerilogHDLParser.Output_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#ref_description.
    def enterRef_description(self, ctx:SysVerilogHDLParser.Ref_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#ref_description.
    def exitRef_description(self, ctx:SysVerilogHDLParser.Ref_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#tf_declaration.
    def enterTf_declaration(self, ctx:SysVerilogHDLParser.Tf_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#tf_declaration.
    def exitTf_declaration(self, ctx:SysVerilogHDLParser.Tf_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#inout_declaration.
    def enterInout_declaration(self, ctx:SysVerilogHDLParser.Inout_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#inout_declaration.
    def exitInout_declaration(self, ctx:SysVerilogHDLParser.Inout_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#input_declaration.
    def enterInput_declaration(self, ctx:SysVerilogHDLParser.Input_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#input_declaration.
    def exitInput_declaration(self, ctx:SysVerilogHDLParser.Input_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#output_declaration.
    def enterOutput_declaration(self, ctx:SysVerilogHDLParser.Output_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#output_declaration.
    def exitOutput_declaration(self, ctx:SysVerilogHDLParser.Output_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#ref_declaration.
    def enterRef_declaration(self, ctx:SysVerilogHDLParser.Ref_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#ref_declaration.
    def exitRef_declaration(self, ctx:SysVerilogHDLParser.Ref_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#user_type.
    def enterUser_type(self, ctx:SysVerilogHDLParser.User_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#user_type.
    def exitUser_type(self, ctx:SysVerilogHDLParser.User_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#user_type_identifer.
    def enterUser_type_identifer(self, ctx:SysVerilogHDLParser.User_type_identiferContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#user_type_identifer.
    def exitUser_type_identifer(self, ctx:SysVerilogHDLParser.User_type_identiferContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#dimension_plus.
    def enterDimension_plus(self, ctx:SysVerilogHDLParser.Dimension_plusContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#dimension_plus.
    def exitDimension_plus(self, ctx:SysVerilogHDLParser.Dimension_plusContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#dimension_star.
    def enterDimension_star(self, ctx:SysVerilogHDLParser.Dimension_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#dimension_star.
    def exitDimension_star(self, ctx:SysVerilogHDLParser.Dimension_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#dimension.
    def enterDimension(self, ctx:SysVerilogHDLParser.DimensionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#dimension.
    def exitDimension(self, ctx:SysVerilogHDLParser.DimensionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#range_expression.
    def enterRange_expression(self, ctx:SysVerilogHDLParser.Range_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#range_expression.
    def exitRange_expression(self, ctx:SysVerilogHDLParser.Range_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#index_expression.
    def enterIndex_expression(self, ctx:SysVerilogHDLParser.Index_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#index_expression.
    def exitIndex_expression(self, ctx:SysVerilogHDLParser.Index_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#sb_range.
    def enterSb_range(self, ctx:SysVerilogHDLParser.Sb_rangeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#sb_range.
    def exitSb_range(self, ctx:SysVerilogHDLParser.Sb_rangeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#base_increment_range.
    def enterBase_increment_range(self, ctx:SysVerilogHDLParser.Base_increment_rangeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#base_increment_range.
    def exitBase_increment_range(self, ctx:SysVerilogHDLParser.Base_increment_rangeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#base_decrement_range.
    def enterBase_decrement_range(self, ctx:SysVerilogHDLParser.Base_decrement_rangeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#base_decrement_range.
    def exitBase_decrement_range(self, ctx:SysVerilogHDLParser.Base_decrement_rangeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#base_expression.
    def enterBase_expression(self, ctx:SysVerilogHDLParser.Base_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#base_expression.
    def exitBase_expression(self, ctx:SysVerilogHDLParser.Base_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#net_type.
    def enterNet_type(self, ctx:SysVerilogHDLParser.Net_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#net_type.
    def exitNet_type(self, ctx:SysVerilogHDLParser.Net_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#drive_strength.
    def enterDrive_strength(self, ctx:SysVerilogHDLParser.Drive_strengthContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#drive_strength.
    def exitDrive_strength(self, ctx:SysVerilogHDLParser.Drive_strengthContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#drive_strength_value_0.
    def enterDrive_strength_value_0(self, ctx:SysVerilogHDLParser.Drive_strength_value_0Context):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#drive_strength_value_0.
    def exitDrive_strength_value_0(self, ctx:SysVerilogHDLParser.Drive_strength_value_0Context):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#drive_strength_value_1.
    def enterDrive_strength_value_1(self, ctx:SysVerilogHDLParser.Drive_strength_value_1Context):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#drive_strength_value_1.
    def exitDrive_strength_value_1(self, ctx:SysVerilogHDLParser.Drive_strength_value_1Context):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#strength0.
    def enterStrength0(self, ctx:SysVerilogHDLParser.Strength0Context):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#strength0.
    def exitStrength0(self, ctx:SysVerilogHDLParser.Strength0Context):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#strength1.
    def enterStrength1(self, ctx:SysVerilogHDLParser.Strength1Context):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#strength1.
    def exitStrength1(self, ctx:SysVerilogHDLParser.Strength1Context):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#highz0.
    def enterHighz0(self, ctx:SysVerilogHDLParser.Highz0Context):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#highz0.
    def exitHighz0(self, ctx:SysVerilogHDLParser.Highz0Context):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#highz1.
    def enterHighz1(self, ctx:SysVerilogHDLParser.Highz1Context):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#highz1.
    def exitHighz1(self, ctx:SysVerilogHDLParser.Highz1Context):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#charge_strength.
    def enterCharge_strength(self, ctx:SysVerilogHDLParser.Charge_strengthContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#charge_strength.
    def exitCharge_strength(self, ctx:SysVerilogHDLParser.Charge_strengthContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#charge_size.
    def enterCharge_size(self, ctx:SysVerilogHDLParser.Charge_sizeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#charge_size.
    def exitCharge_size(self, ctx:SysVerilogHDLParser.Charge_sizeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_variable_descriptions.
    def enterList_of_variable_descriptions(self, ctx:SysVerilogHDLParser.List_of_variable_descriptionsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_variable_descriptions.
    def exitList_of_variable_descriptions(self, ctx:SysVerilogHDLParser.List_of_variable_descriptionsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_variable_description_star.
    def enterComma_variable_description_star(self, ctx:SysVerilogHDLParser.Comma_variable_description_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_variable_description_star.
    def exitComma_variable_description_star(self, ctx:SysVerilogHDLParser.Comma_variable_description_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_variable_description.
    def enterComma_variable_description(self, ctx:SysVerilogHDLParser.Comma_variable_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_variable_description.
    def exitComma_variable_description(self, ctx:SysVerilogHDLParser.Comma_variable_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_description.
    def enterVariable_description(self, ctx:SysVerilogHDLParser.Variable_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_description.
    def exitVariable_description(self, ctx:SysVerilogHDLParser.Variable_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_identifier.
    def enterVariable_identifier(self, ctx:SysVerilogHDLParser.Variable_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_identifier.
    def exitVariable_identifier(self, ctx:SysVerilogHDLParser.Variable_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_hierarchical_variable_descriptions.
    def enterList_of_hierarchical_variable_descriptions(self, ctx:SysVerilogHDLParser.List_of_hierarchical_variable_descriptionsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_hierarchical_variable_descriptions.
    def exitList_of_hierarchical_variable_descriptions(self, ctx:SysVerilogHDLParser.List_of_hierarchical_variable_descriptionsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_hierarchical_variable_description_star.
    def enterComma_hierarchical_variable_description_star(self, ctx:SysVerilogHDLParser.Comma_hierarchical_variable_description_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_hierarchical_variable_description_star.
    def exitComma_hierarchical_variable_description_star(self, ctx:SysVerilogHDLParser.Comma_hierarchical_variable_description_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_hierarchical_variable_description.
    def enterComma_hierarchical_variable_description(self, ctx:SysVerilogHDLParser.Comma_hierarchical_variable_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_hierarchical_variable_description.
    def exitComma_hierarchical_variable_description(self, ctx:SysVerilogHDLParser.Comma_hierarchical_variable_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_variable_description.
    def enterHierarchical_variable_description(self, ctx:SysVerilogHDLParser.Hierarchical_variable_descriptionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_variable_description.
    def exitHierarchical_variable_description(self, ctx:SysVerilogHDLParser.Hierarchical_variable_descriptionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_variable_identifier.
    def enterHierarchical_variable_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_variable_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_variable_identifier.
    def exitHierarchical_variable_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_variable_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#net_declaration.
    def enterNet_declaration(self, ctx:SysVerilogHDLParser.Net_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#net_declaration.
    def exitNet_declaration(self, ctx:SysVerilogHDLParser.Net_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#reg_declaration.
    def enterReg_declaration(self, ctx:SysVerilogHDLParser.Reg_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#reg_declaration.
    def exitReg_declaration(self, ctx:SysVerilogHDLParser.Reg_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#logic_declaration.
    def enterLogic_declaration(self, ctx:SysVerilogHDLParser.Logic_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#logic_declaration.
    def exitLogic_declaration(self, ctx:SysVerilogHDLParser.Logic_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#bits_type.
    def enterBits_type(self, ctx:SysVerilogHDLParser.Bits_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#bits_type.
    def exitBits_type(self, ctx:SysVerilogHDLParser.Bits_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#bits_declaration.
    def enterBits_declaration(self, ctx:SysVerilogHDLParser.Bits_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#bits_declaration.
    def exitBits_declaration(self, ctx:SysVerilogHDLParser.Bits_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#integer_declaration.
    def enterInteger_declaration(self, ctx:SysVerilogHDLParser.Integer_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#integer_declaration.
    def exitInteger_declaration(self, ctx:SysVerilogHDLParser.Integer_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#int_declaration.
    def enterInt_declaration(self, ctx:SysVerilogHDLParser.Int_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#int_declaration.
    def exitInt_declaration(self, ctx:SysVerilogHDLParser.Int_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#real_declaration.
    def enterReal_declaration(self, ctx:SysVerilogHDLParser.Real_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#real_declaration.
    def exitReal_declaration(self, ctx:SysVerilogHDLParser.Real_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#time_declaration.
    def enterTime_declaration(self, ctx:SysVerilogHDLParser.Time_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#time_declaration.
    def exitTime_declaration(self, ctx:SysVerilogHDLParser.Time_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#realtime_declaration.
    def enterRealtime_declaration(self, ctx:SysVerilogHDLParser.Realtime_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#realtime_declaration.
    def exitRealtime_declaration(self, ctx:SysVerilogHDLParser.Realtime_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_declaration.
    def enterEvent_declaration(self, ctx:SysVerilogHDLParser.Event_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_declaration.
    def exitEvent_declaration(self, ctx:SysVerilogHDLParser.Event_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#genvar_declaration.
    def enterGenvar_declaration(self, ctx:SysVerilogHDLParser.Genvar_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#genvar_declaration.
    def exitGenvar_declaration(self, ctx:SysVerilogHDLParser.Genvar_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#usertype_variable_declaration.
    def enterUsertype_variable_declaration(self, ctx:SysVerilogHDLParser.Usertype_variable_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#usertype_variable_declaration.
    def exitUsertype_variable_declaration(self, ctx:SysVerilogHDLParser.Usertype_variable_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#string_declaration.
    def enterString_declaration(self, ctx:SysVerilogHDLParser.String_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#string_declaration.
    def exitString_declaration(self, ctx:SysVerilogHDLParser.String_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#struct_declaration.
    def enterStruct_declaration(self, ctx:SysVerilogHDLParser.Struct_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#struct_declaration.
    def exitStruct_declaration(self, ctx:SysVerilogHDLParser.Struct_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enum_declaration.
    def enterEnum_declaration(self, ctx:SysVerilogHDLParser.Enum_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enum_declaration.
    def exitEnum_declaration(self, ctx:SysVerilogHDLParser.Enum_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_declaration.
    def enterFunction_declaration(self, ctx:SysVerilogHDLParser.Function_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_declaration.
    def exitFunction_declaration(self, ctx:SysVerilogHDLParser.Function_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_type.
    def enterFunction_type(self, ctx:SysVerilogHDLParser.Function_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_type.
    def exitFunction_type(self, ctx:SysVerilogHDLParser.Function_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_identifier.
    def enterFunction_identifier(self, ctx:SysVerilogHDLParser.Function_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_identifier.
    def exitFunction_identifier(self, ctx:SysVerilogHDLParser.Function_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_interface.
    def enterFunction_interface(self, ctx:SysVerilogHDLParser.Function_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_interface.
    def exitFunction_interface(self, ctx:SysVerilogHDLParser.Function_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_item_declaration_star.
    def enterFunction_item_declaration_star(self, ctx:SysVerilogHDLParser.Function_item_declaration_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_item_declaration_star.
    def exitFunction_item_declaration_star(self, ctx:SysVerilogHDLParser.Function_item_declaration_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_item_declaration_semicolon.
    def enterFunction_item_declaration_semicolon(self, ctx:SysVerilogHDLParser.Function_item_declaration_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_item_declaration_semicolon.
    def exitFunction_item_declaration_semicolon(self, ctx:SysVerilogHDLParser.Function_item_declaration_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_item_declaration.
    def enterFunction_item_declaration(self, ctx:SysVerilogHDLParser.Function_item_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_item_declaration.
    def exitFunction_item_declaration(self, ctx:SysVerilogHDLParser.Function_item_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_statement.
    def enterFunction_statement(self, ctx:SysVerilogHDLParser.Function_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_statement.
    def exitFunction_statement(self, ctx:SysVerilogHDLParser.Function_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#colon_function_identifier.
    def enterColon_function_identifier(self, ctx:SysVerilogHDLParser.Colon_function_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#colon_function_identifier.
    def exitColon_function_identifier(self, ctx:SysVerilogHDLParser.Colon_function_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_declaration.
    def enterTask_declaration(self, ctx:SysVerilogHDLParser.Task_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_declaration.
    def exitTask_declaration(self, ctx:SysVerilogHDLParser.Task_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_identifier.
    def enterTask_identifier(self, ctx:SysVerilogHDLParser.Task_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_identifier.
    def exitTask_identifier(self, ctx:SysVerilogHDLParser.Task_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_interface.
    def enterTask_interface(self, ctx:SysVerilogHDLParser.Task_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_interface.
    def exitTask_interface(self, ctx:SysVerilogHDLParser.Task_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_item_declaration_semicolon.
    def enterTask_item_declaration_semicolon(self, ctx:SysVerilogHDLParser.Task_item_declaration_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_item_declaration_semicolon.
    def exitTask_item_declaration_semicolon(self, ctx:SysVerilogHDLParser.Task_item_declaration_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_item_declaration.
    def enterTask_item_declaration(self, ctx:SysVerilogHDLParser.Task_item_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_item_declaration.
    def exitTask_item_declaration(self, ctx:SysVerilogHDLParser.Task_item_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_item_declaration_star.
    def enterTask_item_declaration_star(self, ctx:SysVerilogHDLParser.Task_item_declaration_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_item_declaration_star.
    def exitTask_item_declaration_star(self, ctx:SysVerilogHDLParser.Task_item_declaration_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_statement.
    def enterTask_statement(self, ctx:SysVerilogHDLParser.Task_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_statement.
    def exitTask_statement(self, ctx:SysVerilogHDLParser.Task_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#struct_item_semicolon.
    def enterStruct_item_semicolon(self, ctx:SysVerilogHDLParser.Struct_item_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#struct_item_semicolon.
    def exitStruct_item_semicolon(self, ctx:SysVerilogHDLParser.Struct_item_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#struct_item_star.
    def enterStruct_item_star(self, ctx:SysVerilogHDLParser.Struct_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#struct_item_star.
    def exitStruct_item_star(self, ctx:SysVerilogHDLParser.Struct_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#struct_item.
    def enterStruct_item(self, ctx:SysVerilogHDLParser.Struct_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#struct_item.
    def exitStruct_item(self, ctx:SysVerilogHDLParser.Struct_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#struct_type.
    def enterStruct_type(self, ctx:SysVerilogHDLParser.Struct_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#struct_type.
    def exitStruct_type(self, ctx:SysVerilogHDLParser.Struct_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enum_type.
    def enterEnum_type(self, ctx:SysVerilogHDLParser.Enum_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enum_type.
    def exitEnum_type(self, ctx:SysVerilogHDLParser.Enum_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_enum_items.
    def enterList_of_enum_items(self, ctx:SysVerilogHDLParser.List_of_enum_itemsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_enum_items.
    def exitList_of_enum_items(self, ctx:SysVerilogHDLParser.List_of_enum_itemsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enum_item.
    def enterEnum_item(self, ctx:SysVerilogHDLParser.Enum_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enum_item.
    def exitEnum_item(self, ctx:SysVerilogHDLParser.Enum_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enum_identifier.
    def enterEnum_identifier(self, ctx:SysVerilogHDLParser.Enum_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enum_identifier.
    def exitEnum_identifier(self, ctx:SysVerilogHDLParser.Enum_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_enum_item_star.
    def enterComma_enum_item_star(self, ctx:SysVerilogHDLParser.Comma_enum_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_enum_item_star.
    def exitComma_enum_item_star(self, ctx:SysVerilogHDLParser.Comma_enum_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_enum_item.
    def enterComma_enum_item(self, ctx:SysVerilogHDLParser.Comma_enum_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_enum_item.
    def exitComma_enum_item(self, ctx:SysVerilogHDLParser.Comma_enum_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enumerated_type.
    def enterEnumerated_type(self, ctx:SysVerilogHDLParser.Enumerated_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enumerated_type.
    def exitEnumerated_type(self, ctx:SysVerilogHDLParser.Enumerated_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_instantiation.
    def enterModule_instantiation(self, ctx:SysVerilogHDLParser.Module_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_instantiation.
    def exitModule_instantiation(self, ctx:SysVerilogHDLParser.Module_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#parameter_interface_assignments.
    def enterParameter_interface_assignments(self, ctx:SysVerilogHDLParser.Parameter_interface_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#parameter_interface_assignments.
    def exitParameter_interface_assignments(self, ctx:SysVerilogHDLParser.Parameter_interface_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_interface_assignments.
    def enterList_of_interface_assignments(self, ctx:SysVerilogHDLParser.List_of_interface_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_interface_assignments.
    def exitList_of_interface_assignments(self, ctx:SysVerilogHDLParser.List_of_interface_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_ordered_interface_assignments.
    def enterList_of_ordered_interface_assignments(self, ctx:SysVerilogHDLParser.List_of_ordered_interface_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_ordered_interface_assignments.
    def exitList_of_ordered_interface_assignments(self, ctx:SysVerilogHDLParser.List_of_ordered_interface_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_ordered_interface_assignment_star.
    def enterComma_ordered_interface_assignment_star(self, ctx:SysVerilogHDLParser.Comma_ordered_interface_assignment_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_ordered_interface_assignment_star.
    def exitComma_ordered_interface_assignment_star(self, ctx:SysVerilogHDLParser.Comma_ordered_interface_assignment_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_ordered_interface_assignment.
    def enterComma_ordered_interface_assignment(self, ctx:SysVerilogHDLParser.Comma_ordered_interface_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_ordered_interface_assignment.
    def exitComma_ordered_interface_assignment(self, ctx:SysVerilogHDLParser.Comma_ordered_interface_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#ordered_interface_assignment.
    def enterOrdered_interface_assignment(self, ctx:SysVerilogHDLParser.Ordered_interface_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#ordered_interface_assignment.
    def exitOrdered_interface_assignment(self, ctx:SysVerilogHDLParser.Ordered_interface_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_named_interface_assignments.
    def enterList_of_named_interface_assignments(self, ctx:SysVerilogHDLParser.List_of_named_interface_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_named_interface_assignments.
    def exitList_of_named_interface_assignments(self, ctx:SysVerilogHDLParser.List_of_named_interface_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_named_interface_assignment_star.
    def enterComma_named_interface_assignment_star(self, ctx:SysVerilogHDLParser.Comma_named_interface_assignment_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_named_interface_assignment_star.
    def exitComma_named_interface_assignment_star(self, ctx:SysVerilogHDLParser.Comma_named_interface_assignment_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_named_interface_assignment.
    def enterComma_named_interface_assignment(self, ctx:SysVerilogHDLParser.Comma_named_interface_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_named_interface_assignment.
    def exitComma_named_interface_assignment(self, ctx:SysVerilogHDLParser.Comma_named_interface_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#named_interface_assignment.
    def enterNamed_interface_assignment(self, ctx:SysVerilogHDLParser.Named_interface_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#named_interface_assignment.
    def exitNamed_interface_assignment(self, ctx:SysVerilogHDLParser.Named_interface_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_module_instances.
    def enterList_of_module_instances(self, ctx:SysVerilogHDLParser.List_of_module_instancesContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_module_instances.
    def exitList_of_module_instances(self, ctx:SysVerilogHDLParser.List_of_module_instancesContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_module_instance_star.
    def enterComma_module_instance_star(self, ctx:SysVerilogHDLParser.Comma_module_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_module_instance_star.
    def exitComma_module_instance_star(self, ctx:SysVerilogHDLParser.Comma_module_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_module_instance.
    def enterComma_module_instance(self, ctx:SysVerilogHDLParser.Comma_module_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_module_instance.
    def exitComma_module_instance(self, ctx:SysVerilogHDLParser.Comma_module_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_instance.
    def enterModule_instance(self, ctx:SysVerilogHDLParser.Module_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_instance.
    def exitModule_instance(self, ctx:SysVerilogHDLParser.Module_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#module_instance_identifier.
    def enterModule_instance_identifier(self, ctx:SysVerilogHDLParser.Module_instance_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#module_instance_identifier.
    def exitModule_instance_identifier(self, ctx:SysVerilogHDLParser.Module_instance_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#arrayed_identifier.
    def enterArrayed_identifier(self, ctx:SysVerilogHDLParser.Arrayed_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#arrayed_identifier.
    def exitArrayed_identifier(self, ctx:SysVerilogHDLParser.Arrayed_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#simple_arrayed_identifier.
    def enterSimple_arrayed_identifier(self, ctx:SysVerilogHDLParser.Simple_arrayed_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#simple_arrayed_identifier.
    def exitSimple_arrayed_identifier(self, ctx:SysVerilogHDLParser.Simple_arrayed_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#escaped_arrayed_identifier.
    def enterEscaped_arrayed_identifier(self, ctx:SysVerilogHDLParser.Escaped_arrayed_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#escaped_arrayed_identifier.
    def exitEscaped_arrayed_identifier(self, ctx:SysVerilogHDLParser.Escaped_arrayed_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#port_interface_assignments.
    def enterPort_interface_assignments(self, ctx:SysVerilogHDLParser.Port_interface_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#port_interface_assignments.
    def exitPort_interface_assignments(self, ctx:SysVerilogHDLParser.Port_interface_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#delay.
    def enterDelay(self, ctx:SysVerilogHDLParser.DelayContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#delay.
    def exitDelay(self, ctx:SysVerilogHDLParser.DelayContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_delay_values.
    def enterList_of_delay_values(self, ctx:SysVerilogHDLParser.List_of_delay_valuesContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_delay_values.
    def exitList_of_delay_values(self, ctx:SysVerilogHDLParser.List_of_delay_valuesContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_delay_value_star.
    def enterComma_delay_value_star(self, ctx:SysVerilogHDLParser.Comma_delay_value_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_delay_value_star.
    def exitComma_delay_value_star(self, ctx:SysVerilogHDLParser.Comma_delay_value_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_delay_value.
    def enterComma_delay_value(self, ctx:SysVerilogHDLParser.Comma_delay_valueContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_delay_value.
    def exitComma_delay_value(self, ctx:SysVerilogHDLParser.Comma_delay_valueContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#delay_value.
    def enterDelay_value(self, ctx:SysVerilogHDLParser.Delay_valueContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#delay_value.
    def exitDelay_value(self, ctx:SysVerilogHDLParser.Delay_valueContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pulldown_strength.
    def enterPulldown_strength(self, ctx:SysVerilogHDLParser.Pulldown_strengthContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pulldown_strength.
    def exitPulldown_strength(self, ctx:SysVerilogHDLParser.Pulldown_strengthContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pullup_strength.
    def enterPullup_strength(self, ctx:SysVerilogHDLParser.Pullup_strengthContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pullup_strength.
    def exitPullup_strength(self, ctx:SysVerilogHDLParser.Pullup_strengthContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#gate_instance_identifier.
    def enterGate_instance_identifier(self, ctx:SysVerilogHDLParser.Gate_instance_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#gate_instance_identifier.
    def exitGate_instance_identifier(self, ctx:SysVerilogHDLParser.Gate_instance_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#gate_instantiation.
    def enterGate_instantiation(self, ctx:SysVerilogHDLParser.Gate_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#gate_instantiation.
    def exitGate_instantiation(self, ctx:SysVerilogHDLParser.Gate_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enable_gatetype.
    def enterEnable_gatetype(self, ctx:SysVerilogHDLParser.Enable_gatetypeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enable_gatetype.
    def exitEnable_gatetype(self, ctx:SysVerilogHDLParser.Enable_gatetypeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#mos_switchtype.
    def enterMos_switchtype(self, ctx:SysVerilogHDLParser.Mos_switchtypeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#mos_switchtype.
    def exitMos_switchtype(self, ctx:SysVerilogHDLParser.Mos_switchtypeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#cmos_switchtype.
    def enterCmos_switchtype(self, ctx:SysVerilogHDLParser.Cmos_switchtypeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#cmos_switchtype.
    def exitCmos_switchtype(self, ctx:SysVerilogHDLParser.Cmos_switchtypeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#n_output_gatetype.
    def enterN_output_gatetype(self, ctx:SysVerilogHDLParser.N_output_gatetypeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#n_output_gatetype.
    def exitN_output_gatetype(self, ctx:SysVerilogHDLParser.N_output_gatetypeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#n_input_gatetype.
    def enterN_input_gatetype(self, ctx:SysVerilogHDLParser.N_input_gatetypeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#n_input_gatetype.
    def exitN_input_gatetype(self, ctx:SysVerilogHDLParser.N_input_gatetypeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pass_switchtype.
    def enterPass_switchtype(self, ctx:SysVerilogHDLParser.Pass_switchtypeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pass_switchtype.
    def exitPass_switchtype(self, ctx:SysVerilogHDLParser.Pass_switchtypeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pass_enable_switchtype.
    def enterPass_enable_switchtype(self, ctx:SysVerilogHDLParser.Pass_enable_switchtypeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pass_enable_switchtype.
    def exitPass_enable_switchtype(self, ctx:SysVerilogHDLParser.Pass_enable_switchtypeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pulldown_instantiation.
    def enterPulldown_instantiation(self, ctx:SysVerilogHDLParser.Pulldown_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pulldown_instantiation.
    def exitPulldown_instantiation(self, ctx:SysVerilogHDLParser.Pulldown_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pullup_instantiation.
    def enterPullup_instantiation(self, ctx:SysVerilogHDLParser.Pullup_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pullup_instantiation.
    def exitPullup_instantiation(self, ctx:SysVerilogHDLParser.Pullup_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enable_instantiation.
    def enterEnable_instantiation(self, ctx:SysVerilogHDLParser.Enable_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enable_instantiation.
    def exitEnable_instantiation(self, ctx:SysVerilogHDLParser.Enable_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#mos_instantiation.
    def enterMos_instantiation(self, ctx:SysVerilogHDLParser.Mos_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#mos_instantiation.
    def exitMos_instantiation(self, ctx:SysVerilogHDLParser.Mos_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#cmos_instantiation.
    def enterCmos_instantiation(self, ctx:SysVerilogHDLParser.Cmos_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#cmos_instantiation.
    def exitCmos_instantiation(self, ctx:SysVerilogHDLParser.Cmos_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#n_output_instantiation.
    def enterN_output_instantiation(self, ctx:SysVerilogHDLParser.N_output_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#n_output_instantiation.
    def exitN_output_instantiation(self, ctx:SysVerilogHDLParser.N_output_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#n_input_instantiation.
    def enterN_input_instantiation(self, ctx:SysVerilogHDLParser.N_input_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#n_input_instantiation.
    def exitN_input_instantiation(self, ctx:SysVerilogHDLParser.N_input_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pass_instantiation.
    def enterPass_instantiation(self, ctx:SysVerilogHDLParser.Pass_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pass_instantiation.
    def exitPass_instantiation(self, ctx:SysVerilogHDLParser.Pass_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pass_enable_instantiation.
    def enterPass_enable_instantiation(self, ctx:SysVerilogHDLParser.Pass_enable_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pass_enable_instantiation.
    def exitPass_enable_instantiation(self, ctx:SysVerilogHDLParser.Pass_enable_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_pull_gate_instance.
    def enterList_of_pull_gate_instance(self, ctx:SysVerilogHDLParser.List_of_pull_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_pull_gate_instance.
    def exitList_of_pull_gate_instance(self, ctx:SysVerilogHDLParser.List_of_pull_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_enable_gate_instance.
    def enterList_of_enable_gate_instance(self, ctx:SysVerilogHDLParser.List_of_enable_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_enable_gate_instance.
    def exitList_of_enable_gate_instance(self, ctx:SysVerilogHDLParser.List_of_enable_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_mos_switch_instance.
    def enterList_of_mos_switch_instance(self, ctx:SysVerilogHDLParser.List_of_mos_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_mos_switch_instance.
    def exitList_of_mos_switch_instance(self, ctx:SysVerilogHDLParser.List_of_mos_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_cmos_switch_instance.
    def enterList_of_cmos_switch_instance(self, ctx:SysVerilogHDLParser.List_of_cmos_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_cmos_switch_instance.
    def exitList_of_cmos_switch_instance(self, ctx:SysVerilogHDLParser.List_of_cmos_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_n_input_gate_instance.
    def enterList_of_n_input_gate_instance(self, ctx:SysVerilogHDLParser.List_of_n_input_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_n_input_gate_instance.
    def exitList_of_n_input_gate_instance(self, ctx:SysVerilogHDLParser.List_of_n_input_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_n_output_gate_instance.
    def enterList_of_n_output_gate_instance(self, ctx:SysVerilogHDLParser.List_of_n_output_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_n_output_gate_instance.
    def exitList_of_n_output_gate_instance(self, ctx:SysVerilogHDLParser.List_of_n_output_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_pass_switch_instance.
    def enterList_of_pass_switch_instance(self, ctx:SysVerilogHDLParser.List_of_pass_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_pass_switch_instance.
    def exitList_of_pass_switch_instance(self, ctx:SysVerilogHDLParser.List_of_pass_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_pass_enable_switch_instance.
    def enterList_of_pass_enable_switch_instance(self, ctx:SysVerilogHDLParser.List_of_pass_enable_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_pass_enable_switch_instance.
    def exitList_of_pass_enable_switch_instance(self, ctx:SysVerilogHDLParser.List_of_pass_enable_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_pull_gate_instance_star.
    def enterComma_pull_gate_instance_star(self, ctx:SysVerilogHDLParser.Comma_pull_gate_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_pull_gate_instance_star.
    def exitComma_pull_gate_instance_star(self, ctx:SysVerilogHDLParser.Comma_pull_gate_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_enable_gate_instance_star.
    def enterComma_enable_gate_instance_star(self, ctx:SysVerilogHDLParser.Comma_enable_gate_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_enable_gate_instance_star.
    def exitComma_enable_gate_instance_star(self, ctx:SysVerilogHDLParser.Comma_enable_gate_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_mos_switch_instance_star.
    def enterComma_mos_switch_instance_star(self, ctx:SysVerilogHDLParser.Comma_mos_switch_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_mos_switch_instance_star.
    def exitComma_mos_switch_instance_star(self, ctx:SysVerilogHDLParser.Comma_mos_switch_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_cmos_switch_instance_star.
    def enterComma_cmos_switch_instance_star(self, ctx:SysVerilogHDLParser.Comma_cmos_switch_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_cmos_switch_instance_star.
    def exitComma_cmos_switch_instance_star(self, ctx:SysVerilogHDLParser.Comma_cmos_switch_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_n_input_gate_instance_star.
    def enterComma_n_input_gate_instance_star(self, ctx:SysVerilogHDLParser.Comma_n_input_gate_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_n_input_gate_instance_star.
    def exitComma_n_input_gate_instance_star(self, ctx:SysVerilogHDLParser.Comma_n_input_gate_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_n_output_gate_instance_star.
    def enterComma_n_output_gate_instance_star(self, ctx:SysVerilogHDLParser.Comma_n_output_gate_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_n_output_gate_instance_star.
    def exitComma_n_output_gate_instance_star(self, ctx:SysVerilogHDLParser.Comma_n_output_gate_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_pass_switch_instance_star.
    def enterComma_pass_switch_instance_star(self, ctx:SysVerilogHDLParser.Comma_pass_switch_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_pass_switch_instance_star.
    def exitComma_pass_switch_instance_star(self, ctx:SysVerilogHDLParser.Comma_pass_switch_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_pass_enable_switch_instance_star.
    def enterComma_pass_enable_switch_instance_star(self, ctx:SysVerilogHDLParser.Comma_pass_enable_switch_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_pass_enable_switch_instance_star.
    def exitComma_pass_enable_switch_instance_star(self, ctx:SysVerilogHDLParser.Comma_pass_enable_switch_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_pull_gate_instance.
    def enterComma_pull_gate_instance(self, ctx:SysVerilogHDLParser.Comma_pull_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_pull_gate_instance.
    def exitComma_pull_gate_instance(self, ctx:SysVerilogHDLParser.Comma_pull_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_enable_gate_instance.
    def enterComma_enable_gate_instance(self, ctx:SysVerilogHDLParser.Comma_enable_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_enable_gate_instance.
    def exitComma_enable_gate_instance(self, ctx:SysVerilogHDLParser.Comma_enable_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_mos_switch_instance.
    def enterComma_mos_switch_instance(self, ctx:SysVerilogHDLParser.Comma_mos_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_mos_switch_instance.
    def exitComma_mos_switch_instance(self, ctx:SysVerilogHDLParser.Comma_mos_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_cmos_switch_instance.
    def enterComma_cmos_switch_instance(self, ctx:SysVerilogHDLParser.Comma_cmos_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_cmos_switch_instance.
    def exitComma_cmos_switch_instance(self, ctx:SysVerilogHDLParser.Comma_cmos_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_n_input_gate_instance.
    def enterComma_n_input_gate_instance(self, ctx:SysVerilogHDLParser.Comma_n_input_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_n_input_gate_instance.
    def exitComma_n_input_gate_instance(self, ctx:SysVerilogHDLParser.Comma_n_input_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_n_output_gate_instance.
    def enterComma_n_output_gate_instance(self, ctx:SysVerilogHDLParser.Comma_n_output_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_n_output_gate_instance.
    def exitComma_n_output_gate_instance(self, ctx:SysVerilogHDLParser.Comma_n_output_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_pass_switch_instance.
    def enterComma_pass_switch_instance(self, ctx:SysVerilogHDLParser.Comma_pass_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_pass_switch_instance.
    def exitComma_pass_switch_instance(self, ctx:SysVerilogHDLParser.Comma_pass_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_pass_enable_switch_instance.
    def enterComma_pass_enable_switch_instance(self, ctx:SysVerilogHDLParser.Comma_pass_enable_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_pass_enable_switch_instance.
    def exitComma_pass_enable_switch_instance(self, ctx:SysVerilogHDLParser.Comma_pass_enable_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pull_gate_instance.
    def enterPull_gate_instance(self, ctx:SysVerilogHDLParser.Pull_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pull_gate_instance.
    def exitPull_gate_instance(self, ctx:SysVerilogHDLParser.Pull_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enable_gate_instance.
    def enterEnable_gate_instance(self, ctx:SysVerilogHDLParser.Enable_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enable_gate_instance.
    def exitEnable_gate_instance(self, ctx:SysVerilogHDLParser.Enable_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#mos_switch_instance.
    def enterMos_switch_instance(self, ctx:SysVerilogHDLParser.Mos_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#mos_switch_instance.
    def exitMos_switch_instance(self, ctx:SysVerilogHDLParser.Mos_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#cmos_switch_instance.
    def enterCmos_switch_instance(self, ctx:SysVerilogHDLParser.Cmos_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#cmos_switch_instance.
    def exitCmos_switch_instance(self, ctx:SysVerilogHDLParser.Cmos_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#n_input_gate_instance.
    def enterN_input_gate_instance(self, ctx:SysVerilogHDLParser.N_input_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#n_input_gate_instance.
    def exitN_input_gate_instance(self, ctx:SysVerilogHDLParser.N_input_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#n_output_gate_instance.
    def enterN_output_gate_instance(self, ctx:SysVerilogHDLParser.N_output_gate_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#n_output_gate_instance.
    def exitN_output_gate_instance(self, ctx:SysVerilogHDLParser.N_output_gate_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pass_switch_instance.
    def enterPass_switch_instance(self, ctx:SysVerilogHDLParser.Pass_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pass_switch_instance.
    def exitPass_switch_instance(self, ctx:SysVerilogHDLParser.Pass_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pass_enable_switch_instance.
    def enterPass_enable_switch_instance(self, ctx:SysVerilogHDLParser.Pass_enable_switch_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pass_enable_switch_instance.
    def exitPass_enable_switch_instance(self, ctx:SysVerilogHDLParser.Pass_enable_switch_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pull_gate_interface.
    def enterPull_gate_interface(self, ctx:SysVerilogHDLParser.Pull_gate_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pull_gate_interface.
    def exitPull_gate_interface(self, ctx:SysVerilogHDLParser.Pull_gate_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enable_gate_interface.
    def enterEnable_gate_interface(self, ctx:SysVerilogHDLParser.Enable_gate_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enable_gate_interface.
    def exitEnable_gate_interface(self, ctx:SysVerilogHDLParser.Enable_gate_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#mos_switch_interface.
    def enterMos_switch_interface(self, ctx:SysVerilogHDLParser.Mos_switch_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#mos_switch_interface.
    def exitMos_switch_interface(self, ctx:SysVerilogHDLParser.Mos_switch_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#cmos_switch_interface.
    def enterCmos_switch_interface(self, ctx:SysVerilogHDLParser.Cmos_switch_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#cmos_switch_interface.
    def exitCmos_switch_interface(self, ctx:SysVerilogHDLParser.Cmos_switch_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#n_input_gate_interface.
    def enterN_input_gate_interface(self, ctx:SysVerilogHDLParser.N_input_gate_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#n_input_gate_interface.
    def exitN_input_gate_interface(self, ctx:SysVerilogHDLParser.N_input_gate_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#n_output_gate_interface.
    def enterN_output_gate_interface(self, ctx:SysVerilogHDLParser.N_output_gate_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#n_output_gate_interface.
    def exitN_output_gate_interface(self, ctx:SysVerilogHDLParser.N_output_gate_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pass_switch_interface.
    def enterPass_switch_interface(self, ctx:SysVerilogHDLParser.Pass_switch_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pass_switch_interface.
    def exitPass_switch_interface(self, ctx:SysVerilogHDLParser.Pass_switch_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pass_enable_switch_interface.
    def enterPass_enable_switch_interface(self, ctx:SysVerilogHDLParser.Pass_enable_switch_interfaceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pass_enable_switch_interface.
    def exitPass_enable_switch_interface(self, ctx:SysVerilogHDLParser.Pass_enable_switch_interfaceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_input_terminals.
    def enterList_of_input_terminals(self, ctx:SysVerilogHDLParser.List_of_input_terminalsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_input_terminals.
    def exitList_of_input_terminals(self, ctx:SysVerilogHDLParser.List_of_input_terminalsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_output_terminals.
    def enterList_of_output_terminals(self, ctx:SysVerilogHDLParser.List_of_output_terminalsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_output_terminals.
    def exitList_of_output_terminals(self, ctx:SysVerilogHDLParser.List_of_output_terminalsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_input_terminal_star.
    def enterComma_input_terminal_star(self, ctx:SysVerilogHDLParser.Comma_input_terminal_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_input_terminal_star.
    def exitComma_input_terminal_star(self, ctx:SysVerilogHDLParser.Comma_input_terminal_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_output_terminal_star.
    def enterComma_output_terminal_star(self, ctx:SysVerilogHDLParser.Comma_output_terminal_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_output_terminal_star.
    def exitComma_output_terminal_star(self, ctx:SysVerilogHDLParser.Comma_output_terminal_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_input_terminal.
    def enterComma_input_terminal(self, ctx:SysVerilogHDLParser.Comma_input_terminalContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_input_terminal.
    def exitComma_input_terminal(self, ctx:SysVerilogHDLParser.Comma_input_terminalContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_output_terminal.
    def enterComma_output_terminal(self, ctx:SysVerilogHDLParser.Comma_output_terminalContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_output_terminal.
    def exitComma_output_terminal(self, ctx:SysVerilogHDLParser.Comma_output_terminalContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#enable_terminal.
    def enterEnable_terminal(self, ctx:SysVerilogHDLParser.Enable_terminalContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#enable_terminal.
    def exitEnable_terminal(self, ctx:SysVerilogHDLParser.Enable_terminalContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#input_terminal.
    def enterInput_terminal(self, ctx:SysVerilogHDLParser.Input_terminalContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#input_terminal.
    def exitInput_terminal(self, ctx:SysVerilogHDLParser.Input_terminalContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#inout_terminal.
    def enterInout_terminal(self, ctx:SysVerilogHDLParser.Inout_terminalContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#inout_terminal.
    def exitInout_terminal(self, ctx:SysVerilogHDLParser.Inout_terminalContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#ncontrol_terminal.
    def enterNcontrol_terminal(self, ctx:SysVerilogHDLParser.Ncontrol_terminalContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#ncontrol_terminal.
    def exitNcontrol_terminal(self, ctx:SysVerilogHDLParser.Ncontrol_terminalContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#output_terminal.
    def enterOutput_terminal(self, ctx:SysVerilogHDLParser.Output_terminalContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#output_terminal.
    def exitOutput_terminal(self, ctx:SysVerilogHDLParser.Output_terminalContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#pcontrol_terminal.
    def enterPcontrol_terminal(self, ctx:SysVerilogHDLParser.Pcontrol_terminalContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#pcontrol_terminal.
    def exitPcontrol_terminal(self, ctx:SysVerilogHDLParser.Pcontrol_terminalContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#statement_star.
    def enterStatement_star(self, ctx:SysVerilogHDLParser.Statement_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#statement_star.
    def exitStatement_star(self, ctx:SysVerilogHDLParser.Statement_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#statement_semicolon.
    def enterStatement_semicolon(self, ctx:SysVerilogHDLParser.Statement_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#statement_semicolon.
    def exitStatement_semicolon(self, ctx:SysVerilogHDLParser.Statement_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#statement.
    def enterStatement(self, ctx:SysVerilogHDLParser.StatementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#statement.
    def exitStatement(self, ctx:SysVerilogHDLParser.StatementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#assignment_statement.
    def enterAssignment_statement(self, ctx:SysVerilogHDLParser.Assignment_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#assignment_statement.
    def exitAssignment_statement(self, ctx:SysVerilogHDLParser.Assignment_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#flow_control_statement.
    def enterFlow_control_statement(self, ctx:SysVerilogHDLParser.Flow_control_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#flow_control_statement.
    def exitFlow_control_statement(self, ctx:SysVerilogHDLParser.Flow_control_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#block_statement.
    def enterBlock_statement(self, ctx:SysVerilogHDLParser.Block_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#block_statement.
    def exitBlock_statement(self, ctx:SysVerilogHDLParser.Block_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_call_statement.
    def enterTask_call_statement(self, ctx:SysVerilogHDLParser.Task_call_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_call_statement.
    def exitTask_call_statement(self, ctx:SysVerilogHDLParser.Task_call_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_statement.
    def enterEvent_statement(self, ctx:SysVerilogHDLParser.Event_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_statement.
    def exitEvent_statement(self, ctx:SysVerilogHDLParser.Event_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#procedural_statement.
    def enterProcedural_statement(self, ctx:SysVerilogHDLParser.Procedural_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#procedural_statement.
    def exitProcedural_statement(self, ctx:SysVerilogHDLParser.Procedural_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#expression_statement.
    def enterExpression_statement(self, ctx:SysVerilogHDLParser.Expression_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#expression_statement.
    def exitExpression_statement(self, ctx:SysVerilogHDLParser.Expression_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#subroutine_statement.
    def enterSubroutine_statement(self, ctx:SysVerilogHDLParser.Subroutine_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#subroutine_statement.
    def exitSubroutine_statement(self, ctx:SysVerilogHDLParser.Subroutine_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#return_statement.
    def enterReturn_statement(self, ctx:SysVerilogHDLParser.Return_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#return_statement.
    def exitReturn_statement(self, ctx:SysVerilogHDLParser.Return_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#null_statement.
    def enterNull_statement(self, ctx:SysVerilogHDLParser.Null_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#null_statement.
    def exitNull_statement(self, ctx:SysVerilogHDLParser.Null_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#procedural_continuous_assignments.
    def enterProcedural_continuous_assignments(self, ctx:SysVerilogHDLParser.Procedural_continuous_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#procedural_continuous_assignments.
    def exitProcedural_continuous_assignments(self, ctx:SysVerilogHDLParser.Procedural_continuous_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#assign_statement.
    def enterAssign_statement(self, ctx:SysVerilogHDLParser.Assign_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#assign_statement.
    def exitAssign_statement(self, ctx:SysVerilogHDLParser.Assign_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#deassign_statement.
    def enterDeassign_statement(self, ctx:SysVerilogHDLParser.Deassign_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#deassign_statement.
    def exitDeassign_statement(self, ctx:SysVerilogHDLParser.Deassign_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#force_statement.
    def enterForce_statement(self, ctx:SysVerilogHDLParser.Force_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#force_statement.
    def exitForce_statement(self, ctx:SysVerilogHDLParser.Force_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#release_statement.
    def enterRelease_statement(self, ctx:SysVerilogHDLParser.Release_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#release_statement.
    def exitRelease_statement(self, ctx:SysVerilogHDLParser.Release_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#procedural_timing_control_statement.
    def enterProcedural_timing_control_statement(self, ctx:SysVerilogHDLParser.Procedural_timing_control_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#procedural_timing_control_statement.
    def exitProcedural_timing_control_statement(self, ctx:SysVerilogHDLParser.Procedural_timing_control_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#property_statement.
    def enterProperty_statement(self, ctx:SysVerilogHDLParser.Property_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#property_statement.
    def exitProperty_statement(self, ctx:SysVerilogHDLParser.Property_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#disable_condition_statement.
    def enterDisable_condition_statement(self, ctx:SysVerilogHDLParser.Disable_condition_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#disable_condition_statement.
    def exitDisable_condition_statement(self, ctx:SysVerilogHDLParser.Disable_condition_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#property_expression.
    def enterProperty_expression(self, ctx:SysVerilogHDLParser.Property_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#property_expression.
    def exitProperty_expression(self, ctx:SysVerilogHDLParser.Property_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#procedural_assertion_statement.
    def enterProcedural_assertion_statement(self, ctx:SysVerilogHDLParser.Procedural_assertion_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#procedural_assertion_statement.
    def exitProcedural_assertion_statement(self, ctx:SysVerilogHDLParser.Procedural_assertion_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#assert_else_statement.
    def enterAssert_else_statement(self, ctx:SysVerilogHDLParser.Assert_else_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#assert_else_statement.
    def exitAssert_else_statement(self, ctx:SysVerilogHDLParser.Assert_else_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#assert_statement.
    def enterAssert_statement(self, ctx:SysVerilogHDLParser.Assert_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#assert_statement.
    def exitAssert_statement(self, ctx:SysVerilogHDLParser.Assert_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#system_task_enable.
    def enterSystem_task_enable(self, ctx:SysVerilogHDLParser.System_task_enableContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#system_task_enable.
    def exitSystem_task_enable(self, ctx:SysVerilogHDLParser.System_task_enableContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#system_task_identifier.
    def enterSystem_task_identifier(self, ctx:SysVerilogHDLParser.System_task_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#system_task_identifier.
    def exitSystem_task_identifier(self, ctx:SysVerilogHDLParser.System_task_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_interface_assignments.
    def enterTask_interface_assignments(self, ctx:SysVerilogHDLParser.Task_interface_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_interface_assignments.
    def exitTask_interface_assignments(self, ctx:SysVerilogHDLParser.Task_interface_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#task_enable.
    def enterTask_enable(self, ctx:SysVerilogHDLParser.Task_enableContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#task_enable.
    def exitTask_enable(self, ctx:SysVerilogHDLParser.Task_enableContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_task_identifier.
    def enterHierarchical_task_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_task_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_task_identifier.
    def exitHierarchical_task_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_task_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#disable_statement.
    def enterDisable_statement(self, ctx:SysVerilogHDLParser.Disable_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#disable_statement.
    def exitDisable_statement(self, ctx:SysVerilogHDLParser.Disable_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_block_identifier.
    def enterHierarchical_block_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_block_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_block_identifier.
    def exitHierarchical_block_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_block_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_lvalue.
    def enterVariable_lvalue(self, ctx:SysVerilogHDLParser.Variable_lvalueContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_lvalue.
    def exitVariable_lvalue(self, ctx:SysVerilogHDLParser.Variable_lvalueContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_variable_lvalue.
    def enterHierarchical_variable_lvalue(self, ctx:SysVerilogHDLParser.Hierarchical_variable_lvalueContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_variable_lvalue.
    def exitHierarchical_variable_lvalue(self, ctx:SysVerilogHDLParser.Hierarchical_variable_lvalueContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_concatenation.
    def enterVariable_concatenation(self, ctx:SysVerilogHDLParser.Variable_concatenationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_concatenation.
    def exitVariable_concatenation(self, ctx:SysVerilogHDLParser.Variable_concatenationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_concatenation_value.
    def enterVariable_concatenation_value(self, ctx:SysVerilogHDLParser.Variable_concatenation_valueContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_concatenation_value.
    def exitVariable_concatenation_value(self, ctx:SysVerilogHDLParser.Variable_concatenation_valueContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_vcv_star.
    def enterComma_vcv_star(self, ctx:SysVerilogHDLParser.Comma_vcv_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_vcv_star.
    def exitComma_vcv_star(self, ctx:SysVerilogHDLParser.Comma_vcv_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#blocking_assignment.
    def enterBlocking_assignment(self, ctx:SysVerilogHDLParser.Blocking_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#blocking_assignment.
    def exitBlocking_assignment(self, ctx:SysVerilogHDLParser.Blocking_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#nonblocking_assignment.
    def enterNonblocking_assignment(self, ctx:SysVerilogHDLParser.Nonblocking_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#nonblocking_assignment.
    def exitNonblocking_assignment(self, ctx:SysVerilogHDLParser.Nonblocking_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#prefix_assignment.
    def enterPrefix_assignment(self, ctx:SysVerilogHDLParser.Prefix_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#prefix_assignment.
    def exitPrefix_assignment(self, ctx:SysVerilogHDLParser.Prefix_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#postfix_assignment.
    def enterPostfix_assignment(self, ctx:SysVerilogHDLParser.Postfix_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#postfix_assignment.
    def exitPostfix_assignment(self, ctx:SysVerilogHDLParser.Postfix_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#operator_assignment.
    def enterOperator_assignment(self, ctx:SysVerilogHDLParser.Operator_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#operator_assignment.
    def exitOperator_assignment(self, ctx:SysVerilogHDLParser.Operator_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#declarative_assignment.
    def enterDeclarative_assignment(self, ctx:SysVerilogHDLParser.Declarative_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#declarative_assignment.
    def exitDeclarative_assignment(self, ctx:SysVerilogHDLParser.Declarative_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#delay_or_event_control.
    def enterDelay_or_event_control(self, ctx:SysVerilogHDLParser.Delay_or_event_controlContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#delay_or_event_control.
    def exitDelay_or_event_control(self, ctx:SysVerilogHDLParser.Delay_or_event_controlContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#delay_control.
    def enterDelay_control(self, ctx:SysVerilogHDLParser.Delay_controlContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#delay_control.
    def exitDelay_control(self, ctx:SysVerilogHDLParser.Delay_controlContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_control.
    def enterEvent_control(self, ctx:SysVerilogHDLParser.Event_controlContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_control.
    def exitEvent_control(self, ctx:SysVerilogHDLParser.Event_controlContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_control_identifier.
    def enterEvent_control_identifier(self, ctx:SysVerilogHDLParser.Event_control_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_control_identifier.
    def exitEvent_control_identifier(self, ctx:SysVerilogHDLParser.Event_control_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_control_expression.
    def enterEvent_control_expression(self, ctx:SysVerilogHDLParser.Event_control_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_control_expression.
    def exitEvent_control_expression(self, ctx:SysVerilogHDLParser.Event_control_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_expression.
    def enterEvent_expression(self, ctx:SysVerilogHDLParser.Event_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_expression.
    def exitEvent_expression(self, ctx:SysVerilogHDLParser.Event_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#single_event_expression.
    def enterSingle_event_expression(self, ctx:SysVerilogHDLParser.Single_event_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#single_event_expression.
    def exitSingle_event_expression(self, ctx:SysVerilogHDLParser.Single_event_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_expression_edgespec.
    def enterEvent_expression_edgespec(self, ctx:SysVerilogHDLParser.Event_expression_edgespecContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_expression_edgespec.
    def exitEvent_expression_edgespec(self, ctx:SysVerilogHDLParser.Event_expression_edgespecContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_expression_or.
    def enterEvent_expression_or(self, ctx:SysVerilogHDLParser.Event_expression_orContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_expression_or.
    def exitEvent_expression_or(self, ctx:SysVerilogHDLParser.Event_expression_orContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_event_expression_comma.
    def enterList_of_event_expression_comma(self, ctx:SysVerilogHDLParser.List_of_event_expression_commaContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_event_expression_comma.
    def exitList_of_event_expression_comma(self, ctx:SysVerilogHDLParser.List_of_event_expression_commaContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_event_expression_star.
    def enterComma_event_expression_star(self, ctx:SysVerilogHDLParser.Comma_event_expression_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_event_expression_star.
    def exitComma_event_expression_star(self, ctx:SysVerilogHDLParser.Comma_event_expression_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_event_expression.
    def enterComma_event_expression(self, ctx:SysVerilogHDLParser.Comma_event_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_event_expression.
    def exitComma_event_expression(self, ctx:SysVerilogHDLParser.Comma_event_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_event_expression_or.
    def enterList_of_event_expression_or(self, ctx:SysVerilogHDLParser.List_of_event_expression_orContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_event_expression_or.
    def exitList_of_event_expression_or(self, ctx:SysVerilogHDLParser.List_of_event_expression_orContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#or_event_expression_star.
    def enterOr_event_expression_star(self, ctx:SysVerilogHDLParser.Or_event_expression_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#or_event_expression_star.
    def exitOr_event_expression_star(self, ctx:SysVerilogHDLParser.Or_event_expression_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#or_event_expression.
    def enterOr_event_expression(self, ctx:SysVerilogHDLParser.Or_event_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#or_event_expression.
    def exitOr_event_expression(self, ctx:SysVerilogHDLParser.Or_event_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_control_wildcard.
    def enterEvent_control_wildcard(self, ctx:SysVerilogHDLParser.Event_control_wildcardContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_control_wildcard.
    def exitEvent_control_wildcard(self, ctx:SysVerilogHDLParser.Event_control_wildcardContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#repeat_event_control.
    def enterRepeat_event_control(self, ctx:SysVerilogHDLParser.Repeat_event_controlContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#repeat_event_control.
    def exitRepeat_event_control(self, ctx:SysVerilogHDLParser.Repeat_event_controlContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_trigger.
    def enterEvent_trigger(self, ctx:SysVerilogHDLParser.Event_triggerContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_trigger.
    def exitEvent_trigger(self, ctx:SysVerilogHDLParser.Event_triggerContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_event_identifier.
    def enterHierarchical_event_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_event_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_event_identifier.
    def exitHierarchical_event_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_event_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#event_identifier.
    def enterEvent_identifier(self, ctx:SysVerilogHDLParser.Event_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#event_identifier.
    def exitEvent_identifier(self, ctx:SysVerilogHDLParser.Event_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#wait_statement.
    def enterWait_statement(self, ctx:SysVerilogHDLParser.Wait_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#wait_statement.
    def exitWait_statement(self, ctx:SysVerilogHDLParser.Wait_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_generated_instantiation.
    def enterAttr_generated_instantiation(self, ctx:SysVerilogHDLParser.Attr_generated_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_generated_instantiation.
    def exitAttr_generated_instantiation(self, ctx:SysVerilogHDLParser.Attr_generated_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generated_instantiation.
    def enterGenerated_instantiation(self, ctx:SysVerilogHDLParser.Generated_instantiationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generated_instantiation.
    def exitGenerated_instantiation(self, ctx:SysVerilogHDLParser.Generated_instantiationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_item_star.
    def enterGenerate_item_star(self, ctx:SysVerilogHDLParser.Generate_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_item_star.
    def exitGenerate_item_star(self, ctx:SysVerilogHDLParser.Generate_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_item.
    def enterGenerate_item(self, ctx:SysVerilogHDLParser.Generate_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_item.
    def exitGenerate_item(self, ctx:SysVerilogHDLParser.Generate_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_block.
    def enterGenerate_block(self, ctx:SysVerilogHDLParser.Generate_blockContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_block.
    def exitGenerate_block(self, ctx:SysVerilogHDLParser.Generate_blockContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_colon_block_identifier0.
    def enterGenerate_colon_block_identifier0(self, ctx:SysVerilogHDLParser.Generate_colon_block_identifier0Context):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_colon_block_identifier0.
    def exitGenerate_colon_block_identifier0(self, ctx:SysVerilogHDLParser.Generate_colon_block_identifier0Context):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_colon_block_identifier1.
    def enterGenerate_colon_block_identifier1(self, ctx:SysVerilogHDLParser.Generate_colon_block_identifier1Context):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_colon_block_identifier1.
    def exitGenerate_colon_block_identifier1(self, ctx:SysVerilogHDLParser.Generate_colon_block_identifier1Context):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_colon_block_identifier.
    def enterGenerate_colon_block_identifier(self, ctx:SysVerilogHDLParser.Generate_colon_block_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_colon_block_identifier.
    def exitGenerate_colon_block_identifier(self, ctx:SysVerilogHDLParser.Generate_colon_block_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_block_identifier.
    def enterGenerate_block_identifier(self, ctx:SysVerilogHDLParser.Generate_block_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_block_identifier.
    def exitGenerate_block_identifier(self, ctx:SysVerilogHDLParser.Generate_block_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_conditional_statement.
    def enterGenerate_conditional_statement(self, ctx:SysVerilogHDLParser.Generate_conditional_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_conditional_statement.
    def exitGenerate_conditional_statement(self, ctx:SysVerilogHDLParser.Generate_conditional_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_if_statement.
    def enterGenerate_if_statement(self, ctx:SysVerilogHDLParser.Generate_if_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_if_statement.
    def exitGenerate_if_statement(self, ctx:SysVerilogHDLParser.Generate_if_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_else_statement.
    def enterGenerate_else_statement(self, ctx:SysVerilogHDLParser.Generate_else_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_else_statement.
    def exitGenerate_else_statement(self, ctx:SysVerilogHDLParser.Generate_else_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_loop_statement.
    def enterGenerate_loop_statement(self, ctx:SysVerilogHDLParser.Generate_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_loop_statement.
    def exitGenerate_loop_statement(self, ctx:SysVerilogHDLParser.Generate_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_forever_loop_statement.
    def enterGenerate_forever_loop_statement(self, ctx:SysVerilogHDLParser.Generate_forever_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_forever_loop_statement.
    def exitGenerate_forever_loop_statement(self, ctx:SysVerilogHDLParser.Generate_forever_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_repeat_loop_statement.
    def enterGenerate_repeat_loop_statement(self, ctx:SysVerilogHDLParser.Generate_repeat_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_repeat_loop_statement.
    def exitGenerate_repeat_loop_statement(self, ctx:SysVerilogHDLParser.Generate_repeat_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_while_loop_statement.
    def enterGenerate_while_loop_statement(self, ctx:SysVerilogHDLParser.Generate_while_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_while_loop_statement.
    def exitGenerate_while_loop_statement(self, ctx:SysVerilogHDLParser.Generate_while_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_do_loop_statement.
    def enterGenerate_do_loop_statement(self, ctx:SysVerilogHDLParser.Generate_do_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_do_loop_statement.
    def exitGenerate_do_loop_statement(self, ctx:SysVerilogHDLParser.Generate_do_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_for_loop_statement.
    def enterGenerate_for_loop_statement(self, ctx:SysVerilogHDLParser.Generate_for_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_for_loop_statement.
    def exitGenerate_for_loop_statement(self, ctx:SysVerilogHDLParser.Generate_for_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_case_statement.
    def enterGenerate_case_statement(self, ctx:SysVerilogHDLParser.Generate_case_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_case_statement.
    def exitGenerate_case_statement(self, ctx:SysVerilogHDLParser.Generate_case_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_case_item_star.
    def enterGenerate_case_item_star(self, ctx:SysVerilogHDLParser.Generate_case_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_case_item_star.
    def exitGenerate_case_item_star(self, ctx:SysVerilogHDLParser.Generate_case_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#generate_case_item.
    def enterGenerate_case_item(self, ctx:SysVerilogHDLParser.Generate_case_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#generate_case_item.
    def exitGenerate_case_item(self, ctx:SysVerilogHDLParser.Generate_case_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#conditional_statement.
    def enterConditional_statement(self, ctx:SysVerilogHDLParser.Conditional_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#conditional_statement.
    def exitConditional_statement(self, ctx:SysVerilogHDLParser.Conditional_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#if_statement.
    def enterIf_statement(self, ctx:SysVerilogHDLParser.If_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#if_statement.
    def exitIf_statement(self, ctx:SysVerilogHDLParser.If_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#else_statement.
    def enterElse_statement(self, ctx:SysVerilogHDLParser.Else_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#else_statement.
    def exitElse_statement(self, ctx:SysVerilogHDLParser.Else_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#conditional_expression.
    def enterConditional_expression(self, ctx:SysVerilogHDLParser.Conditional_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#conditional_expression.
    def exitConditional_expression(self, ctx:SysVerilogHDLParser.Conditional_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#loop_statement.
    def enterLoop_statement(self, ctx:SysVerilogHDLParser.Loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#loop_statement.
    def exitLoop_statement(self, ctx:SysVerilogHDLParser.Loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#forever_loop_statement.
    def enterForever_loop_statement(self, ctx:SysVerilogHDLParser.Forever_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#forever_loop_statement.
    def exitForever_loop_statement(self, ctx:SysVerilogHDLParser.Forever_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#repeat_loop_statement.
    def enterRepeat_loop_statement(self, ctx:SysVerilogHDLParser.Repeat_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#repeat_loop_statement.
    def exitRepeat_loop_statement(self, ctx:SysVerilogHDLParser.Repeat_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#while_loop_statement.
    def enterWhile_loop_statement(self, ctx:SysVerilogHDLParser.While_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#while_loop_statement.
    def exitWhile_loop_statement(self, ctx:SysVerilogHDLParser.While_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#do_loop_statement.
    def enterDo_loop_statement(self, ctx:SysVerilogHDLParser.Do_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#do_loop_statement.
    def exitDo_loop_statement(self, ctx:SysVerilogHDLParser.Do_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#for_loop_statement.
    def enterFor_loop_statement(self, ctx:SysVerilogHDLParser.For_loop_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#for_loop_statement.
    def exitFor_loop_statement(self, ctx:SysVerilogHDLParser.For_loop_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#loop_init_assignment.
    def enterLoop_init_assignment(self, ctx:SysVerilogHDLParser.Loop_init_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#loop_init_assignment.
    def exitLoop_init_assignment(self, ctx:SysVerilogHDLParser.Loop_init_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#loop_terminate_expression.
    def enterLoop_terminate_expression(self, ctx:SysVerilogHDLParser.Loop_terminate_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#loop_terminate_expression.
    def exitLoop_terminate_expression(self, ctx:SysVerilogHDLParser.Loop_terminate_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#loop_step_assignment.
    def enterLoop_step_assignment(self, ctx:SysVerilogHDLParser.Loop_step_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#loop_step_assignment.
    def exitLoop_step_assignment(self, ctx:SysVerilogHDLParser.Loop_step_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#case_statement.
    def enterCase_statement(self, ctx:SysVerilogHDLParser.Case_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#case_statement.
    def exitCase_statement(self, ctx:SysVerilogHDLParser.Case_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#case_item_star.
    def enterCase_item_star(self, ctx:SysVerilogHDLParser.Case_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#case_item_star.
    def exitCase_item_star(self, ctx:SysVerilogHDLParser.Case_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#case_item.
    def enterCase_item(self, ctx:SysVerilogHDLParser.Case_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#case_item.
    def exitCase_item(self, ctx:SysVerilogHDLParser.Case_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#case_switch.
    def enterCase_switch(self, ctx:SysVerilogHDLParser.Case_switchContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#case_switch.
    def exitCase_switch(self, ctx:SysVerilogHDLParser.Case_switchContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#case_item_key.
    def enterCase_item_key(self, ctx:SysVerilogHDLParser.Case_item_keyContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#case_item_key.
    def exitCase_item_key(self, ctx:SysVerilogHDLParser.Case_item_keyContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#case_item_key_expression.
    def enterCase_item_key_expression(self, ctx:SysVerilogHDLParser.Case_item_key_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#case_item_key_expression.
    def exitCase_item_key_expression(self, ctx:SysVerilogHDLParser.Case_item_key_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_case_item_key_expression.
    def enterComma_case_item_key_expression(self, ctx:SysVerilogHDLParser.Comma_case_item_key_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_case_item_key_expression.
    def exitComma_case_item_key_expression(self, ctx:SysVerilogHDLParser.Comma_case_item_key_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_case_item_key_expression_star.
    def enterComma_case_item_key_expression_star(self, ctx:SysVerilogHDLParser.Comma_case_item_key_expression_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_case_item_key_expression_star.
    def exitComma_case_item_key_expression_star(self, ctx:SysVerilogHDLParser.Comma_case_item_key_expression_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#expression.
    def enterExpression(self, ctx:SysVerilogHDLParser.ExpressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#expression.
    def exitExpression(self, ctx:SysVerilogHDLParser.ExpressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#single_expression.
    def enterSingle_expression(self, ctx:SysVerilogHDLParser.Single_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#single_expression.
    def exitSingle_expression(self, ctx:SysVerilogHDLParser.Single_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#primary_range.
    def enterPrimary_range(self, ctx:SysVerilogHDLParser.Primary_rangeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#primary_range.
    def exitPrimary_range(self, ctx:SysVerilogHDLParser.Primary_rangeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#primary.
    def enterPrimary(self, ctx:SysVerilogHDLParser.PrimaryContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#primary.
    def exitPrimary(self, ctx:SysVerilogHDLParser.PrimaryContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#unary_expression.
    def enterUnary_expression(self, ctx:SysVerilogHDLParser.Unary_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#unary_expression.
    def exitUnary_expression(self, ctx:SysVerilogHDLParser.Unary_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#unary_post_assign_expression.
    def enterUnary_post_assign_expression(self, ctx:SysVerilogHDLParser.Unary_post_assign_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#unary_post_assign_expression.
    def exitUnary_post_assign_expression(self, ctx:SysVerilogHDLParser.Unary_post_assign_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#unary_pre_assign_expression.
    def enterUnary_pre_assign_expression(self, ctx:SysVerilogHDLParser.Unary_pre_assign_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#unary_pre_assign_expression.
    def exitUnary_pre_assign_expression(self, ctx:SysVerilogHDLParser.Unary_pre_assign_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#binary_expression.
    def enterBinary_expression(self, ctx:SysVerilogHDLParser.Binary_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#binary_expression.
    def exitBinary_expression(self, ctx:SysVerilogHDLParser.Binary_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#ternary_expression.
    def enterTernary_expression(self, ctx:SysVerilogHDLParser.Ternary_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#ternary_expression.
    def exitTernary_expression(self, ctx:SysVerilogHDLParser.Ternary_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#mintypmax_expression.
    def enterMintypmax_expression(self, ctx:SysVerilogHDLParser.Mintypmax_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#mintypmax_expression.
    def exitMintypmax_expression(self, ctx:SysVerilogHDLParser.Mintypmax_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#structured_value.
    def enterStructured_value(self, ctx:SysVerilogHDLParser.Structured_valueContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#structured_value.
    def exitStructured_value(self, ctx:SysVerilogHDLParser.Structured_valueContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#arrayed_structured_value.
    def enterArrayed_structured_value(self, ctx:SysVerilogHDLParser.Arrayed_structured_valueContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#arrayed_structured_value.
    def exitArrayed_structured_value(self, ctx:SysVerilogHDLParser.Arrayed_structured_valueContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#arrayed_structure_item.
    def enterArrayed_structure_item(self, ctx:SysVerilogHDLParser.Arrayed_structure_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#arrayed_structure_item.
    def exitArrayed_structure_item(self, ctx:SysVerilogHDLParser.Arrayed_structure_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_arrayed_structure_item.
    def enterComma_arrayed_structure_item(self, ctx:SysVerilogHDLParser.Comma_arrayed_structure_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_arrayed_structure_item.
    def exitComma_arrayed_structure_item(self, ctx:SysVerilogHDLParser.Comma_arrayed_structure_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_arrayed_structure_item_star.
    def enterComma_arrayed_structure_item_star(self, ctx:SysVerilogHDLParser.Comma_arrayed_structure_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_arrayed_structure_item_star.
    def exitComma_arrayed_structure_item_star(self, ctx:SysVerilogHDLParser.Comma_arrayed_structure_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#arrayed_structure_item_plus.
    def enterArrayed_structure_item_plus(self, ctx:SysVerilogHDLParser.Arrayed_structure_item_plusContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#arrayed_structure_item_plus.
    def exitArrayed_structure_item_plus(self, ctx:SysVerilogHDLParser.Arrayed_structure_item_plusContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_type_cast.
    def enterVariable_type_cast(self, ctx:SysVerilogHDLParser.Variable_type_castContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_type_cast.
    def exitVariable_type_cast(self, ctx:SysVerilogHDLParser.Variable_type_castContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#width_type_cast.
    def enterWidth_type_cast(self, ctx:SysVerilogHDLParser.Width_type_castContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#width_type_cast.
    def exitWidth_type_cast(self, ctx:SysVerilogHDLParser.Width_type_castContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#sign_type_cast.
    def enterSign_type_cast(self, ctx:SysVerilogHDLParser.Sign_type_castContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#sign_type_cast.
    def exitSign_type_cast(self, ctx:SysVerilogHDLParser.Sign_type_castContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#null_type_cast.
    def enterNull_type_cast(self, ctx:SysVerilogHDLParser.Null_type_castContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#null_type_cast.
    def exitNull_type_cast(self, ctx:SysVerilogHDLParser.Null_type_castContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_type.
    def enterVariable_type(self, ctx:SysVerilogHDLParser.Variable_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_type.
    def exitVariable_type(self, ctx:SysVerilogHDLParser.Variable_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#type_cast_identifier.
    def enterType_cast_identifier(self, ctx:SysVerilogHDLParser.Type_cast_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#type_cast_identifier.
    def exitType_cast_identifier(self, ctx:SysVerilogHDLParser.Type_cast_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#type_cast_expression.
    def enterType_cast_expression(self, ctx:SysVerilogHDLParser.Type_cast_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#type_cast_expression.
    def exitType_cast_expression(self, ctx:SysVerilogHDLParser.Type_cast_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_call.
    def enterFunction_call(self, ctx:SysVerilogHDLParser.Function_callContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_call.
    def exitFunction_call(self, ctx:SysVerilogHDLParser.Function_callContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_function_identifier.
    def enterHierarchical_function_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_function_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_function_identifier.
    def exitHierarchical_function_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_function_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#function_interface_assignments.
    def enterFunction_interface_assignments(self, ctx:SysVerilogHDLParser.Function_interface_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#function_interface_assignments.
    def exitFunction_interface_assignments(self, ctx:SysVerilogHDLParser.Function_interface_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#system_function_call.
    def enterSystem_function_call(self, ctx:SysVerilogHDLParser.System_function_callContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#system_function_call.
    def exitSystem_function_call(self, ctx:SysVerilogHDLParser.System_function_callContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#system_function_identifier.
    def enterSystem_function_identifier(self, ctx:SysVerilogHDLParser.System_function_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#system_function_identifier.
    def exitSystem_function_identifier(self, ctx:SysVerilogHDLParser.System_function_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#constant_function_call.
    def enterConstant_function_call(self, ctx:SysVerilogHDLParser.Constant_function_callContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#constant_function_call.
    def exitConstant_function_call(self, ctx:SysVerilogHDLParser.Constant_function_callContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#imported_function_call.
    def enterImported_function_call(self, ctx:SysVerilogHDLParser.Imported_function_callContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#imported_function_call.
    def exitImported_function_call(self, ctx:SysVerilogHDLParser.Imported_function_callContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#imported_function_hierarchical_identifier.
    def enterImported_function_hierarchical_identifier(self, ctx:SysVerilogHDLParser.Imported_function_hierarchical_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#imported_function_hierarchical_identifier.
    def exitImported_function_hierarchical_identifier(self, ctx:SysVerilogHDLParser.Imported_function_hierarchical_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#primary_hierarchical_identifier.
    def enterPrimary_hierarchical_identifier(self, ctx:SysVerilogHDLParser.Primary_hierarchical_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#primary_hierarchical_identifier.
    def exitPrimary_hierarchical_identifier(self, ctx:SysVerilogHDLParser.Primary_hierarchical_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#primary_imported_hierarchical_identifier.
    def enterPrimary_imported_hierarchical_identifier(self, ctx:SysVerilogHDLParser.Primary_imported_hierarchical_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#primary_imported_hierarchical_identifier.
    def exitPrimary_imported_hierarchical_identifier(self, ctx:SysVerilogHDLParser.Primary_imported_hierarchical_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#imported_hierarchical_identifier.
    def enterImported_hierarchical_identifier(self, ctx:SysVerilogHDLParser.Imported_hierarchical_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#imported_hierarchical_identifier.
    def exitImported_hierarchical_identifier(self, ctx:SysVerilogHDLParser.Imported_hierarchical_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#parenthesis_expression.
    def enterParenthesis_expression(self, ctx:SysVerilogHDLParser.Parenthesis_expressionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#parenthesis_expression.
    def exitParenthesis_expression(self, ctx:SysVerilogHDLParser.Parenthesis_expressionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#concatenation.
    def enterConcatenation(self, ctx:SysVerilogHDLParser.ConcatenationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#concatenation.
    def exitConcatenation(self, ctx:SysVerilogHDLParser.ConcatenationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#multiple_concatenation.
    def enterMultiple_concatenation(self, ctx:SysVerilogHDLParser.Multiple_concatenationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#multiple_concatenation.
    def exitMultiple_concatenation(self, ctx:SysVerilogHDLParser.Multiple_concatenationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_expression_plus.
    def enterComma_expression_plus(self, ctx:SysVerilogHDLParser.Comma_expression_plusContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_expression_plus.
    def exitComma_expression_plus(self, ctx:SysVerilogHDLParser.Comma_expression_plusContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_expression_star.
    def enterComma_expression_star(self, ctx:SysVerilogHDLParser.Comma_expression_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_expression_star.
    def exitComma_expression_star(self, ctx:SysVerilogHDLParser.Comma_expression_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#typedef_declaration.
    def enterTypedef_declaration(self, ctx:SysVerilogHDLParser.Typedef_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#typedef_declaration.
    def exitTypedef_declaration(self, ctx:SysVerilogHDLParser.Typedef_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#typedef_identifier.
    def enterTypedef_identifier(self, ctx:SysVerilogHDLParser.Typedef_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#typedef_identifier.
    def exitTypedef_identifier(self, ctx:SysVerilogHDLParser.Typedef_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#typedef_definition.
    def enterTypedef_definition(self, ctx:SysVerilogHDLParser.Typedef_definitionContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#typedef_definition.
    def exitTypedef_definition(self, ctx:SysVerilogHDLParser.Typedef_definitionContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#typedef_definition_type.
    def enterTypedef_definition_type(self, ctx:SysVerilogHDLParser.Typedef_definition_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#typedef_definition_type.
    def exitTypedef_definition_type(self, ctx:SysVerilogHDLParser.Typedef_definition_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#complex_type.
    def enterComplex_type(self, ctx:SysVerilogHDLParser.Complex_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#complex_type.
    def exitComplex_type(self, ctx:SysVerilogHDLParser.Complex_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#typedef_type.
    def enterTypedef_type(self, ctx:SysVerilogHDLParser.Typedef_typeContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#typedef_type.
    def exitTypedef_type(self, ctx:SysVerilogHDLParser.Typedef_typeContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#par_block.
    def enterPar_block(self, ctx:SysVerilogHDLParser.Par_blockContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#par_block.
    def exitPar_block(self, ctx:SysVerilogHDLParser.Par_blockContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#seq_block.
    def enterSeq_block(self, ctx:SysVerilogHDLParser.Seq_blockContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#seq_block.
    def exitSeq_block(self, ctx:SysVerilogHDLParser.Seq_blockContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#block_identifier.
    def enterBlock_identifier(self, ctx:SysVerilogHDLParser.Block_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#block_identifier.
    def exitBlock_identifier(self, ctx:SysVerilogHDLParser.Block_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#colon_block_identifier.
    def enterColon_block_identifier(self, ctx:SysVerilogHDLParser.Colon_block_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#colon_block_identifier.
    def exitColon_block_identifier(self, ctx:SysVerilogHDLParser.Colon_block_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#block_item_declaration_star.
    def enterBlock_item_declaration_star(self, ctx:SysVerilogHDLParser.Block_item_declaration_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#block_item_declaration_star.
    def exitBlock_item_declaration_star(self, ctx:SysVerilogHDLParser.Block_item_declaration_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#block_item_declaration_semicolon.
    def enterBlock_item_declaration_semicolon(self, ctx:SysVerilogHDLParser.Block_item_declaration_semicolonContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#block_item_declaration_semicolon.
    def exitBlock_item_declaration_semicolon(self, ctx:SysVerilogHDLParser.Block_item_declaration_semicolonContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#block_item_declaration.
    def enterBlock_item_declaration(self, ctx:SysVerilogHDLParser.Block_item_declarationContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#block_item_declaration.
    def exitBlock_item_declaration(self, ctx:SysVerilogHDLParser.Block_item_declarationContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#join_keyword.
    def enterJoin_keyword(self, ctx:SysVerilogHDLParser.Join_keywordContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#join_keyword.
    def exitJoin_keyword(self, ctx:SysVerilogHDLParser.Join_keywordContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#continuous_assign.
    def enterContinuous_assign(self, ctx:SysVerilogHDLParser.Continuous_assignContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#continuous_assign.
    def exitContinuous_assign(self, ctx:SysVerilogHDLParser.Continuous_assignContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#list_of_variable_assignments.
    def enterList_of_variable_assignments(self, ctx:SysVerilogHDLParser.List_of_variable_assignmentsContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#list_of_variable_assignments.
    def exitList_of_variable_assignments(self, ctx:SysVerilogHDLParser.List_of_variable_assignmentsContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_variable_assignment_star.
    def enterComma_variable_assignment_star(self, ctx:SysVerilogHDLParser.Comma_variable_assignment_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_variable_assignment_star.
    def exitComma_variable_assignment_star(self, ctx:SysVerilogHDLParser.Comma_variable_assignment_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#comma_variable_assignment.
    def enterComma_variable_assignment(self, ctx:SysVerilogHDLParser.Comma_variable_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#comma_variable_assignment.
    def exitComma_variable_assignment(self, ctx:SysVerilogHDLParser.Comma_variable_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#variable_assignment.
    def enterVariable_assignment(self, ctx:SysVerilogHDLParser.Variable_assignmentContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#variable_assignment.
    def exitVariable_assignment(self, ctx:SysVerilogHDLParser.Variable_assignmentContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#initial_construct.
    def enterInitial_construct(self, ctx:SysVerilogHDLParser.Initial_constructContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#initial_construct.
    def exitInitial_construct(self, ctx:SysVerilogHDLParser.Initial_constructContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#final_construct.
    def enterFinal_construct(self, ctx:SysVerilogHDLParser.Final_constructContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#final_construct.
    def exitFinal_construct(self, ctx:SysVerilogHDLParser.Final_constructContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#always_keyword.
    def enterAlways_keyword(self, ctx:SysVerilogHDLParser.Always_keywordContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#always_keyword.
    def exitAlways_keyword(self, ctx:SysVerilogHDLParser.Always_keywordContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#always_construct.
    def enterAlways_construct(self, ctx:SysVerilogHDLParser.Always_constructContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#always_construct.
    def exitAlways_construct(self, ctx:SysVerilogHDLParser.Always_constructContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attribute_instance_star.
    def enterAttribute_instance_star(self, ctx:SysVerilogHDLParser.Attribute_instance_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attribute_instance_star.
    def exitAttribute_instance_star(self, ctx:SysVerilogHDLParser.Attribute_instance_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attribute_instance.
    def enterAttribute_instance(self, ctx:SysVerilogHDLParser.Attribute_instanceContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attribute_instance.
    def exitAttribute_instance(self, ctx:SysVerilogHDLParser.Attribute_instanceContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_spec_star.
    def enterAttr_spec_star(self, ctx:SysVerilogHDLParser.Attr_spec_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_spec_star.
    def exitAttr_spec_star(self, ctx:SysVerilogHDLParser.Attr_spec_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_spec.
    def enterAttr_spec(self, ctx:SysVerilogHDLParser.Attr_specContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_spec.
    def exitAttr_spec(self, ctx:SysVerilogHDLParser.Attr_specContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#attr_name.
    def enterAttr_name(self, ctx:SysVerilogHDLParser.Attr_nameContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#attr_name.
    def exitAttr_name(self, ctx:SysVerilogHDLParser.Attr_nameContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#identifier.
    def enterIdentifier(self, ctx:SysVerilogHDLParser.IdentifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#identifier.
    def exitIdentifier(self, ctx:SysVerilogHDLParser.IdentifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_identifier.
    def enterHierarchical_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_identifierContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_identifier.
    def exitHierarchical_identifier(self, ctx:SysVerilogHDLParser.Hierarchical_identifierContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#dot_hierarchical_identifier_branch_item_star.
    def enterDot_hierarchical_identifier_branch_item_star(self, ctx:SysVerilogHDLParser.Dot_hierarchical_identifier_branch_item_starContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#dot_hierarchical_identifier_branch_item_star.
    def exitDot_hierarchical_identifier_branch_item_star(self, ctx:SysVerilogHDLParser.Dot_hierarchical_identifier_branch_item_starContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#dot_hierarchical_identifier_branch_item.
    def enterDot_hierarchical_identifier_branch_item(self, ctx:SysVerilogHDLParser.Dot_hierarchical_identifier_branch_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#dot_hierarchical_identifier_branch_item.
    def exitDot_hierarchical_identifier_branch_item(self, ctx:SysVerilogHDLParser.Dot_hierarchical_identifier_branch_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#hierarchical_identifier_branch_item.
    def enterHierarchical_identifier_branch_item(self, ctx:SysVerilogHDLParser.Hierarchical_identifier_branch_itemContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#hierarchical_identifier_branch_item.
    def exitHierarchical_identifier_branch_item(self, ctx:SysVerilogHDLParser.Hierarchical_identifier_branch_itemContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#timescale_compiler_directive.
    def enterTimescale_compiler_directive(self, ctx:SysVerilogHDLParser.Timescale_compiler_directiveContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#timescale_compiler_directive.
    def exitTimescale_compiler_directive(self, ctx:SysVerilogHDLParser.Timescale_compiler_directiveContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#timeunit_directive.
    def enterTimeunit_directive(self, ctx:SysVerilogHDLParser.Timeunit_directiveContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#timeunit_directive.
    def exitTimeunit_directive(self, ctx:SysVerilogHDLParser.Timeunit_directiveContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#timeprecision_directive.
    def enterTimeprecision_directive(self, ctx:SysVerilogHDLParser.Timeprecision_directiveContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#timeprecision_directive.
    def exitTimeprecision_directive(self, ctx:SysVerilogHDLParser.Timeprecision_directiveContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#default_nettype_statement.
    def enterDefault_nettype_statement(self, ctx:SysVerilogHDLParser.Default_nettype_statementContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#default_nettype_statement.
    def exitDefault_nettype_statement(self, ctx:SysVerilogHDLParser.Default_nettype_statementContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#number.
    def enterNumber(self, ctx:SysVerilogHDLParser.NumberContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#number.
    def exitNumber(self, ctx:SysVerilogHDLParser.NumberContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#integral_number.
    def enterIntegral_number(self, ctx:SysVerilogHDLParser.Integral_numberContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#integral_number.
    def exitIntegral_number(self, ctx:SysVerilogHDLParser.Integral_numberContext):
        pass


    # Enter a parse tree produced by SysVerilogHDLParser#real_number.
    def enterReal_number(self, ctx:SysVerilogHDLParser.Real_numberContext):
        pass

    # Exit a parse tree produced by SysVerilogHDLParser#real_number.
    def exitReal_number(self, ctx:SysVerilogHDLParser.Real_numberContext):
        pass



del SysVerilogHDLParser