# Generated from SystemVerilogParser.g4 by ANTLR 4.9.3
# encoding: utf-8
from antlr4 import *
from io import StringIO
import sys
if sys.version_info[1] > 5:
	from typing import TextIO
else:
	from typing.io import TextIO


def serializedATN():
    with StringIO() as buf:
        buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\u0167")
        buf.write("\u1ed5\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7")
        buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16")
        buf.write("\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23\t\23")
        buf.write("\4\24\t\24\4\25\t\25\4\26\t\26\4\27\t\27\4\30\t\30\4\31")
        buf.write("\t\31\4\32\t\32\4\33\t\33\4\34\t\34\4\35\t\35\4\36\t\36")
        buf.write("\4\37\t\37\4 \t \4!\t!\4\"\t\"\4#\t#\4$\t$\4%\t%\4&\t")
        buf.write("&\4\'\t\'\4(\t(\4)\t)\4*\t*\4+\t+\4,\t,\4-\t-\4.\t.\4")
        buf.write("/\t/\4\60\t\60\4\61\t\61\4\62\t\62\4\63\t\63\4\64\t\64")
        buf.write("\4\65\t\65\4\66\t\66\4\67\t\67\48\t8\49\t9\4:\t:\4;\t")
        buf.write(";\4<\t<\4=\t=\4>\t>\4?\t?\4@\t@\4A\tA\4B\tB\4C\tC\4D\t")
        buf.write("D\4E\tE\4F\tF\4G\tG\4H\tH\4I\tI\4J\tJ\4K\tK\4L\tL\4M\t")
        buf.write("M\4N\tN\4O\tO\4P\tP\4Q\tQ\4R\tR\4S\tS\4T\tT\4U\tU\4V\t")
        buf.write("V\4W\tW\4X\tX\4Y\tY\4Z\tZ\4[\t[\4\\\t\\\4]\t]\4^\t^\4")
        buf.write("_\t_\4`\t`\4a\ta\4b\tb\4c\tc\4d\td\4e\te\4f\tf\4g\tg\4")
        buf.write("h\th\4i\ti\4j\tj\4k\tk\4l\tl\4m\tm\4n\tn\4o\to\4p\tp\4")
        buf.write("q\tq\4r\tr\4s\ts\4t\tt\4u\tu\4v\tv\4w\tw\4x\tx\4y\ty\4")
        buf.write("z\tz\4{\t{\4|\t|\4}\t}\4~\t~\4\177\t\177\4\u0080\t\u0080")
        buf.write("\4\u0081\t\u0081\4\u0082\t\u0082\4\u0083\t\u0083\4\u0084")
        buf.write("\t\u0084\4\u0085\t\u0085\4\u0086\t\u0086\4\u0087\t\u0087")
        buf.write("\4\u0088\t\u0088\4\u0089\t\u0089\4\u008a\t\u008a\4\u008b")
        buf.write("\t\u008b\4\u008c\t\u008c\4\u008d\t\u008d\4\u008e\t\u008e")
        buf.write("\4\u008f\t\u008f\4\u0090\t\u0090\4\u0091\t\u0091\4\u0092")
        buf.write("\t\u0092\4\u0093\t\u0093\4\u0094\t\u0094\4\u0095\t\u0095")
        buf.write("\4\u0096\t\u0096\4\u0097\t\u0097\4\u0098\t\u0098\4\u0099")
        buf.write("\t\u0099\4\u009a\t\u009a\4\u009b\t\u009b\4\u009c\t\u009c")
        buf.write("\4\u009d\t\u009d\4\u009e\t\u009e\4\u009f\t\u009f\4\u00a0")
        buf.write("\t\u00a0\4\u00a1\t\u00a1\4\u00a2\t\u00a2\4\u00a3\t\u00a3")
        buf.write("\4\u00a4\t\u00a4\4\u00a5\t\u00a5\4\u00a6\t\u00a6\4\u00a7")
        buf.write("\t\u00a7\4\u00a8\t\u00a8\4\u00a9\t\u00a9\4\u00aa\t\u00aa")
        buf.write("\4\u00ab\t\u00ab\4\u00ac\t\u00ac\4\u00ad\t\u00ad\4\u00ae")
        buf.write("\t\u00ae\4\u00af\t\u00af\4\u00b0\t\u00b0\4\u00b1\t\u00b1")
        buf.write("\4\u00b2\t\u00b2\4\u00b3\t\u00b3\4\u00b4\t\u00b4\4\u00b5")
        buf.write("\t\u00b5\4\u00b6\t\u00b6\4\u00b7\t\u00b7\4\u00b8\t\u00b8")
        buf.write("\4\u00b9\t\u00b9\4\u00ba\t\u00ba\4\u00bb\t\u00bb\4\u00bc")
        buf.write("\t\u00bc\4\u00bd\t\u00bd\4\u00be\t\u00be\4\u00bf\t\u00bf")
        buf.write("\4\u00c0\t\u00c0\4\u00c1\t\u00c1\4\u00c2\t\u00c2\4\u00c3")
        buf.write("\t\u00c3\4\u00c4\t\u00c4\4\u00c5\t\u00c5\4\u00c6\t\u00c6")
        buf.write("\4\u00c7\t\u00c7\4\u00c8\t\u00c8\4\u00c9\t\u00c9\4\u00ca")
        buf.write("\t\u00ca\4\u00cb\t\u00cb\4\u00cc\t\u00cc\4\u00cd\t\u00cd")
        buf.write("\4\u00ce\t\u00ce\4\u00cf\t\u00cf\4\u00d0\t\u00d0\4\u00d1")
        buf.write("\t\u00d1\4\u00d2\t\u00d2\4\u00d3\t\u00d3\4\u00d4\t\u00d4")
        buf.write("\4\u00d5\t\u00d5\4\u00d6\t\u00d6\4\u00d7\t\u00d7\4\u00d8")
        buf.write("\t\u00d8\4\u00d9\t\u00d9\4\u00da\t\u00da\4\u00db\t\u00db")
        buf.write("\4\u00dc\t\u00dc\4\u00dd\t\u00dd\4\u00de\t\u00de\4\u00df")
        buf.write("\t\u00df\4\u00e0\t\u00e0\4\u00e1\t\u00e1\4\u00e2\t\u00e2")
        buf.write("\4\u00e3\t\u00e3\4\u00e4\t\u00e4\4\u00e5\t\u00e5\4\u00e6")
        buf.write("\t\u00e6\4\u00e7\t\u00e7\4\u00e8\t\u00e8\4\u00e9\t\u00e9")
        buf.write("\4\u00ea\t\u00ea\4\u00eb\t\u00eb\4\u00ec\t\u00ec\4\u00ed")
        buf.write("\t\u00ed\4\u00ee\t\u00ee\4\u00ef\t\u00ef\4\u00f0\t\u00f0")
        buf.write("\4\u00f1\t\u00f1\4\u00f2\t\u00f2\4\u00f3\t\u00f3\4\u00f4")
        buf.write("\t\u00f4\4\u00f5\t\u00f5\4\u00f6\t\u00f6\4\u00f7\t\u00f7")
        buf.write("\4\u00f8\t\u00f8\4\u00f9\t\u00f9\4\u00fa\t\u00fa\4\u00fb")
        buf.write("\t\u00fb\4\u00fc\t\u00fc\4\u00fd\t\u00fd\4\u00fe\t\u00fe")
        buf.write("\4\u00ff\t\u00ff\4\u0100\t\u0100\4\u0101\t\u0101\4\u0102")
        buf.write("\t\u0102\4\u0103\t\u0103\4\u0104\t\u0104\4\u0105\t\u0105")
        buf.write("\4\u0106\t\u0106\4\u0107\t\u0107\4\u0108\t\u0108\4\u0109")
        buf.write("\t\u0109\4\u010a\t\u010a\4\u010b\t\u010b\4\u010c\t\u010c")
        buf.write("\4\u010d\t\u010d\4\u010e\t\u010e\4\u010f\t\u010f\4\u0110")
        buf.write("\t\u0110\4\u0111\t\u0111\4\u0112\t\u0112\4\u0113\t\u0113")
        buf.write("\4\u0114\t\u0114\4\u0115\t\u0115\4\u0116\t\u0116\4\u0117")
        buf.write("\t\u0117\4\u0118\t\u0118\4\u0119\t\u0119\4\u011a\t\u011a")
        buf.write("\4\u011b\t\u011b\4\u011c\t\u011c\4\u011d\t\u011d\4\u011e")
        buf.write("\t\u011e\4\u011f\t\u011f\4\u0120\t\u0120\4\u0121\t\u0121")
        buf.write("\4\u0122\t\u0122\4\u0123\t\u0123\4\u0124\t\u0124\4\u0125")
        buf.write("\t\u0125\4\u0126\t\u0126\4\u0127\t\u0127\4\u0128\t\u0128")
        buf.write("\4\u0129\t\u0129\4\u012a\t\u012a\4\u012b\t\u012b\4\u012c")
        buf.write("\t\u012c\4\u012d\t\u012d\4\u012e\t\u012e\4\u012f\t\u012f")
        buf.write("\4\u0130\t\u0130\4\u0131\t\u0131\4\u0132\t\u0132\4\u0133")
        buf.write("\t\u0133\4\u0134\t\u0134\4\u0135\t\u0135\4\u0136\t\u0136")
        buf.write("\4\u0137\t\u0137\4\u0138\t\u0138\4\u0139\t\u0139\4\u013a")
        buf.write("\t\u013a\4\u013b\t\u013b\4\u013c\t\u013c\4\u013d\t\u013d")
        buf.write("\4\u013e\t\u013e\4\u013f\t\u013f\4\u0140\t\u0140\4\u0141")
        buf.write("\t\u0141\4\u0142\t\u0142\4\u0143\t\u0143\4\u0144\t\u0144")
        buf.write("\4\u0145\t\u0145\4\u0146\t\u0146\4\u0147\t\u0147\4\u0148")
        buf.write("\t\u0148\4\u0149\t\u0149\4\u014a\t\u014a\4\u014b\t\u014b")
        buf.write("\4\u014c\t\u014c\4\u014d\t\u014d\4\u014e\t\u014e\4\u014f")
        buf.write("\t\u014f\4\u0150\t\u0150\4\u0151\t\u0151\4\u0152\t\u0152")
        buf.write("\4\u0153\t\u0153\4\u0154\t\u0154\4\u0155\t\u0155\4\u0156")
        buf.write("\t\u0156\4\u0157\t\u0157\4\u0158\t\u0158\4\u0159\t\u0159")
        buf.write("\4\u015a\t\u015a\4\u015b\t\u015b\4\u015c\t\u015c\4\u015d")
        buf.write("\t\u015d\4\u015e\t\u015e\4\u015f\t\u015f\4\u0160\t\u0160")
        buf.write("\4\u0161\t\u0161\4\u0162\t\u0162\4\u0163\t\u0163\4\u0164")
        buf.write("\t\u0164\4\u0165\t\u0165\4\u0166\t\u0166\4\u0167\t\u0167")
        buf.write("\4\u0168\t\u0168\4\u0169\t\u0169\4\u016a\t\u016a\4\u016b")
        buf.write("\t\u016b\4\u016c\t\u016c\4\u016d\t\u016d\4\u016e\t\u016e")
        buf.write("\4\u016f\t\u016f\4\u0170\t\u0170\4\u0171\t\u0171\4\u0172")
        buf.write("\t\u0172\4\u0173\t\u0173\4\u0174\t\u0174\4\u0175\t\u0175")
        buf.write("\4\u0176\t\u0176\4\u0177\t\u0177\4\u0178\t\u0178\4\u0179")
        buf.write("\t\u0179\4\u017a\t\u017a\4\u017b\t\u017b\4\u017c\t\u017c")
        buf.write("\4\u017d\t\u017d\4\u017e\t\u017e\4\u017f\t\u017f\4\u0180")
        buf.write("\t\u0180\4\u0181\t\u0181\4\u0182\t\u0182\4\u0183\t\u0183")
        buf.write("\4\u0184\t\u0184\4\u0185\t\u0185\4\u0186\t\u0186\4\u0187")
        buf.write("\t\u0187\4\u0188\t\u0188\4\u0189\t\u0189\4\u018a\t\u018a")
        buf.write("\4\u018b\t\u018b\4\u018c\t\u018c\4\u018d\t\u018d\4\u018e")
        buf.write("\t\u018e\4\u018f\t\u018f\4\u0190\t\u0190\4\u0191\t\u0191")
        buf.write("\4\u0192\t\u0192\4\u0193\t\u0193\4\u0194\t\u0194\4\u0195")
        buf.write("\t\u0195\4\u0196\t\u0196\4\u0197\t\u0197\4\u0198\t\u0198")
        buf.write("\4\u0199\t\u0199\4\u019a\t\u019a\4\u019b\t\u019b\4\u019c")
        buf.write("\t\u019c\4\u019d\t\u019d\4\u019e\t\u019e\4\u019f\t\u019f")
        buf.write("\4\u01a0\t\u01a0\4\u01a1\t\u01a1\4\u01a2\t\u01a2\4\u01a3")
        buf.write("\t\u01a3\4\u01a4\t\u01a4\4\u01a5\t\u01a5\4\u01a6\t\u01a6")
        buf.write("\4\u01a7\t\u01a7\4\u01a8\t\u01a8\4\u01a9\t\u01a9\4\u01aa")
        buf.write("\t\u01aa\4\u01ab\t\u01ab\4\u01ac\t\u01ac\4\u01ad\t\u01ad")
        buf.write("\4\u01ae\t\u01ae\4\u01af\t\u01af\4\u01b0\t\u01b0\4\u01b1")
        buf.write("\t\u01b1\4\u01b2\t\u01b2\4\u01b3\t\u01b3\4\u01b4\t\u01b4")
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        buf.write("\t\u01b8\4\u01b9\t\u01b9\4\u01ba\t\u01ba\4\u01bb\t\u01bb")
        buf.write("\4\u01bc\t\u01bc\4\u01bd\t\u01bd\4\u01be\t\u01be\4\u01bf")
        buf.write("\t\u01bf\4\u01c0\t\u01c0\4\u01c1\t\u01c1\4\u01c2\t\u01c2")
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        buf.write("\t\u01c6\4\u01c7\t\u01c7\4\u01c8\t\u01c8\4\u01c9\t\u01c9")
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        buf.write("\u14c2\u14c9\u14d2\u14dc\u14e4\u14e7\u14ec\u14f0\u14f5")
        buf.write("\u14fc\u14ff\u1502\u1508\u1518\u1528\u152c\u1535\u153f")
        buf.write("\u1549\u1551\u1554\u155a\u155f\u1564\u156a\u156c\u1571")
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        buf.write("\u16c2\u16c7\u16c9\u16d2\u16d7\u16e7\u16ec\u16f5\u16fa")
        buf.write("\u1701\u170b\u1713\u1716\u171b\u1726\u172b\u1736\u173e")
        buf.write("\u1741\u1746\u174d\u1750\u1758\u175b\u1764\u1772\u177e")
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        buf.write("\u1954\u195d\u195f\u1965\u196e\u1975\u1978\u1984\u198a")
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        buf.write("\u1a99\u1aa2\u1aa6\u1aac\u1abd\u1ac1\u1acb\u1ad6\u1ae6")
        buf.write("\u1af8\u1b01\u1b09\u1b14\u1b19\u1b24\u1b2b\u1b32\u1b38")
        buf.write("\u1b3d\u1b41\u1b46\u1b48\u1b4a\u1b4e\u1b55\u1b60\u1b67")
        buf.write("\u1b75\u1b7b\u1b7e\u1b83\u1b87\u1b8b\u1b92\u1b96\u1b9d")
        buf.write("\u1ba3\u1baa\u1bb1\u1bb4\u1bb8\u1bbe\u1bc5\u1bcc\u1bd2")
        buf.write("\u1bd8\u1bdb\u1be0\u1be3\u1be6\u1bed\u1bf3\u1bfc\u1c01")
        buf.write("\u1c08\u1c0b\u1c14\u1c1b\u1c21\u1c27\u1c30\u1c35\u1c3a")
        buf.write("\u1c3e\u1c42\u1c51\u1c54\u1c61\u1c63\u1c6a\u1c74\u1c7b")
        buf.write("\u1c87\u1c8a\u1c8c\u1c96\u1c9e\u1ca5\u1ca8\u1cb1\u1cbb")
        buf.write("\u1cc2\u1cc4\u1ccd\u1cd1\u1cdc\u1ce3\u1ce9\u1cee\u1cfa")
        buf.write("\u1d05\u1d0a\u1d15\u1d1c\u1d2b\u1d2f\u1d35\u1d39\u1d3e")
        buf.write("\u1d43\u1d46\u1d4e\u1d57\u1d5c\u1d63\u1d6b\u1d70\u1d7a")
        buf.write("\u1d83\u1d88\u1d8f\u1da2\u1da8\u1dab\u1db1\u1dbc\u1dc2")
        buf.write("\u1dc6\u1dcc\u1de3\u1deb\u1e22\u1e2a\u1e5f\u1e6e\u1e73")
        buf.write("\u1e78\u1e7d\u1e86\u1e8b\u1e8f\u1e92\u1e96\u1e99\u1e9d")
        buf.write("\u1ea0\u1ea4\u1ea8\u1eb0\u1eb6\u1eba\u1ec0")
        return buf.getvalue()


class SystemVerilogParser ( Parser ):

    grammarFileName = "SystemVerilogParser.g4"

    atn = ATNDeserializer().deserialize(serializedATN())

    decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ]

    sharedContextCache = PredictionContextCache()

    literalNames = [ "<INVALID>", "'-'", "'--'", "'!'", "'!='", "'!=?'", 
                     "'!=='", "'\"DPI\"'", "'\"DPI-C\"'", "'#'", "'##'", 
                     "'#-#'", "'#=#'", "'#0'", "'$'", "'$error'", "'$fatal'", 
                     "'$info'", "'$root.'", "'$unit'", "'$warning'", "'%'", 
                     "'%='", "'&'", "'&&'", "'&&&'", "'&='", "'('", "'(*'", 
                     "')'", "'*'", "'*)'", "'**'", "'*::*'", "'*='", "'*>'", 
                     "','", "'.'", "'.*'", "'/'", "'/='", "':'", "'-:'", 
                     "':/'", "'::'", "':='", "';'", "'?'", "'@'", "'@@'", 
                     "'['", "'''", "']'", "'^'", "'^~'", "'^='", "'{'", 
                     "'|'", "'||'", "'|='", "'|=>'", "'|->'", "'}'", "'~'", 
                     "'~&'", "'~^'", "'~|'", "'+'", "'+:'", "'++'", "'+='", 
                     "'<'", "'<<'", "'<<<'", "'<<<='", "'<<='", "'<='", 
                     "'<->'", "'='", "'-='", "'=='", "'==?'", "'==='", "'=>'", 
                     "'>'", "'->'", "'>='", "'>>'", "'->>'", "'>>='", "'>>>'", 
                     "'>>>='", "'1step'", "'accept_on'", "'alias'", "'always'", 
                     "'always_comb'", "'always_ff'", "'always_latch'", "'and'", 
                     "'assert'", "'assign'", "'assume'", "'automatic'", 
                     "'before'", "'begin'", "'bind'", "'bins'", "'binsof'", 
                     "'bit'", "'break'", "'buf'", "'bufif0'", "'bufif1'", 
                     "'byte'", "'case'", "'casex'", "'casez'", "'cell'", 
                     "'chandle'", "'checker'", "'class'", "'clocking'", 
                     "'cmos'", "'config'", "'const'", "'constraint'", "'context'", 
                     "'continue'", "'cover'", "'covergroup'", "'coverpoint'", 
                     "'cross'", "'deassign'", "'default'", "'defparam'", 
                     "'design'", "'disable'", "'dist'", "'do'", "'edge'", 
                     "'else'", "'end'", "'endcase'", "'endchecker'", "'endclass'", 
                     "'endclocking'", "'endconfig'", "'endfunction'", "'endgenerate'", 
                     "'endgroup'", "'endinterface'", "'endmodule'", "'endpackage'", 
                     "'endprogram'", "'endproperty'", "'endsequence'", "'endspecify'", 
                     "'endtask'", "'enum'", "'event'", "'eventually'", "'expect'", 
                     "'export'", "'extends'", "'extern'", "'final'", "'first_match'", 
                     "'for'", "'force'", "'foreach'", "'forever'", "'fork'", 
                     "'forkjoin'", "'function'", "'generate'", "'genvar'", 
                     "'global'", "'highz0'", "'highz1'", "'if'", "'iff'", 
                     "'ifnone'", "'ignore_bins'", "'illegal_bins'", "'implements'", 
                     "'implies'", "'import'", "'-incdir'", "'include'", 
                     "'initial'", "'inout'", "'input'", "'inside'", "'instance'", 
                     "'int'", "'integer'", "'interconnect'", "'interface'", 
                     "'intersect'", "'join'", "'join_any'", "'join_none'", 
                     "'large'", "'let'", "'liblist'", "'library'", "'local'", 
                     "'localparam'", "'logic'", "'longint'", "'macromodule'", 
                     "'matches'", "'medium'", "'member_identifier'", "'modport'", 
                     "'module'", "'nand'", "'negedge'", "'nettype'", "'new'", 
                     "'nexttime'", "'nmos'", "'nor'", "'noshowcancelled'", 
                     "'not'", "'notif0'", "'notif1'", "'null'", "'option'", 
                     "'or'", "'output'", "'package'", "'packed'", "'parameter'", 
                     "'PATHPULSE$'", "'pmos'", "'posedge'", "'priority'", 
                     "'program'", "'property'", "'protected'", "'pull0'", 
                     "'pull1'", "'pulldown'", "'pullup'", "'pulsestyle_ondetect'", 
                     "'pulsestyle_onevent'", "'pure'", "'rand'", "'randc'", 
                     "'randcase'", "'randomize'", "'randsequence'", "'rcmos'", 
                     "'real'", "'realtime'", "'ref'", "'reg'", "'reject_on'", 
                     "'release'", "'repeat'", "'restrict'", "'return'", 
                     "'rnmos'", "'rpmos'", "'rtran'", "'rtranif0'", "'rtranif1'", 
                     "'s_always'", "'s_eventually'", "'s_nexttime'", "'s_until'", 
                     "'s_until_with'", "'scalared'", "'sequence'", "'shortint'", 
                     "'shortreal'", "'showcancelled'", "'signed'", "'small'", 
                     "'soft'", "'solve'", "'specify'", "'specparam'", "'static'", 
                     "'std'", "'string'", "'strong'", "'strong0'", "'strong1'", 
                     "'struct'", "'super'", "'supply0'", "'supply1'", "'sync_accept_on'", 
                     "'sync_reject_on'", "'tagged'", "'task'", "'this'", 
                     "'throughout'", "'time'", "'timeprecision'", "'timeunit'", 
                     "'tran'", "'tranif0'", "'tranif1'", "'tri'", "'tri0'", 
                     "'tri1'", "'triand'", "'trior'", "'trireg'", "'type'", 
                     "'type_option'", "'typedef'", "'union'", "'unique'", 
                     "'unique0'", "'unsigned'", "'until'", "'until_with'", 
                     "'untyped'", "'use'", "'uwire'", "'var'", "'vectored'", 
                     "'virtual'", "'void'", "'wait'", "'wait_order'", "'wand'", 
                     "'weak'", "'weak0'", "'weak1'", "'while'", "'wildcard'", 
                     "'wire'", "'with'", "'within'", "'wor'", "'xnor'", 
                     "'xor'" ]

    symbolicNames = [ "<INVALID>", "MINUS", "MINUSMINS", "NOT", "NE", "NEQ", 
                      "NEE", "DPI", "DPIC", "P", "PP", "PMP", "PEP", "PZ", 
                      "DOLLAR", "DERROR", "DFATAL", "DINFO", "DROOT", "DUNIT", 
                      "DWARNING", "PER", "PE", "AND", "ANDAND", "ANDANDAND", 
                      "AE", "LP", "LPS", "RP", "STAR", "SRP", "SS", "SCCS", 
                      "SEQ", "SGT", "COMMA", "DOT", "DOTSTAR", "SLASH", 
                      "SLASHEQ", "COLON", "MCOLON", "COLONSLASH", "COLONCOLON", 
                      "COLONEQ", "SEMI", "QUES", "AT", "ATAT", "LB", "QUOTE", 
                      "RB", "CARET", "CARETSQUIG", "CARETEQ", "LC", "BAR", 
                      "BARBAR", "BAREQ", "BAREQGT", "BARARROW", "RC", "SQUIG", 
                      "SQUIGAND", "SQUIGCARET", "SQUIGBAR", "PLUS", "PLUSCOLON", 
                      "PLUSPLUS", "PLUSEQ", "LT", "LTLT", "LTLTLT", "LTLTLTEQ", 
                      "LTLTEQ", "LTEQ", "LTMINUSGT", "EQ", "MINUSEQ", "EQEQ", 
                      "EQEQQUEST", "EQEQEQ", "EQGT", "GT", "ARROW", "GE", 
                      "GTGT", "MINUSGTGT", "GTGTEQ", "GTGTGT", "GTGTGTEQ", 
                      "KONESTEP", "KACCEPT_ON", "KALIAS", "KALWAYS", "KALWAYS_COMB", 
                      "KALWAYS_FF", "KALWAYS_LATCH", "KAND", "KASSERT", 
                      "KASSIGN", "KASSUME", "KAUTOMATIC", "KBEFORE", "KBEGIN", 
                      "KBIND", "KBINS", "KBINSOF", "KBIT", "KBREAK", "KBUF", 
                      "KBUFIF0", "KBUFIF1", "KBYTE", "KCASE", "KCASEX", 
                      "KCASEZ", "KCELL", "KCHANDLE", "KCHECKER", "KCLASS", 
                      "KCLOCKING", "KCMOS", "KCONFIG", "KCONST", "KCONSTRAINT", 
                      "KCONTEXT", "KCONTINUE", "KCOVER", "KCOVERGROUP", 
                      "KCOVERPOINT", "KCROSS", "KDEASSIGN", "KDEFAULT", 
                      "KDEFPARAM", "KDESIGN", "KDISABLE", "KDIST", "KDO", 
                      "KEDGE", "KELSE", "KEND", "KENDCASE", "KENDCHECKER", 
                      "KENDCLASS", "KENDCLOCKING", "KENDCONFIG", "KENDFUNCTION", 
                      "KENDGENERATE", "KENDGROUP", "KENDINTERFACE", "KENDMODULE", 
                      "KENDPACKAGE", "KENDPROGRAM", "KENDPROPERTY", "KENDSEQUENCE", 
                      "KENDSPECIFY", "KENDTASK", "KENUM", "KEVENT", "KEVENTUALLY", 
                      "KEXPECT", "KEXPORT", "KEXTENDS", "KEXTERN", "KFINAL", 
                      "KFIRST_MATCH", "KFOR", "KFORCE", "KFOREACH", "KFOREVER", 
                      "KFORK", "KFORKJOIN", "KFUNCTION", "KGENERATE", "KGENVAR", 
                      "KGLOBAL", "KHIGHZ0", "KHIGHZ1", "KIF", "KIFF", "KIFNONE", 
                      "KIGNORE_BINS", "KILLEGAL_BINS", "KIMPLEMENTS", "KIMPLIES", 
                      "KIMPORT", "KINCDIR", "KINCLUDE", "KINITIAL", "KINOUT", 
                      "KINPUT", "KINSIDE", "KINSTANCE", "KINT", "KINTEGER", 
                      "KINTERCONNECT", "KINTERFACE", "KINTERSECT", "KJOIN", 
                      "KJOIN_ANY", "KJOIN_NONE", "KLARGE", "KLET", "KLIBLIST", 
                      "KLIBRARY", "KLOCAL", "KLOCALPARAM", "KLOGIC", "KLONGINT", 
                      "KMACROMODULE", "KMATCHES", "KMEDIUM", "KMEMBER_IDENTIFIER", 
                      "KMODPORT", "KMODULE", "KNAND", "KNEGEDGE", "KNETTYPE", 
                      "KNEW", "KNEXTTIME", "KNMOS", "KNOR", "KNOSHOWCANCELLED", 
                      "KNOT", "KNOTIF0", "KNOTIF1", "KNULL", "KOPTION", 
                      "KOR", "KOUTPUT", "KPACKAGE", "KPACKED", "KPARAMETER", 
                      "KPATHPULSE", "KPMOS", "KPOSEDGE", "KPRIORITY", "KPROGRAM", 
                      "KPROPERTY", "KPROTECTED", "KPULL0", "KPULL1", "KPULLDOWN", 
                      "KPULLUP", "KPULSESTYLE_ONDETECT", "KPULSESTYLE_ONEVENT", 
                      "KPURE", "KRAND", "KRANDC", "KRANDCASE", "KRANDOMIZE", 
                      "KRANDSEQUENCE", "KRCMOS", "KREAL", "KREALTIME", "KREF", 
                      "KREG", "KREJECT_ON", "KRELEASE", "KREPEAT", "KRESTRICT", 
                      "KRETURN", "KRNMOS", "KRPMOS", "KRTRAN", "KRTRANIF0", 
                      "KRTRANIF1", "KS_ALWAYS", "KS_EVENTUALLY", "KS_NEXTTIME", 
                      "KS_UNTIL", "KS_UNTIL_WITH", "KSCALARED", "KSEQUENCE", 
                      "KSHORTINT", "KSHORTREAL", "KSHOWCANCELLED", "KSIGNED", 
                      "KSMALL", "KSOFT", "KSOLVE", "KSPECIFY", "KSPECPARAM", 
                      "KSTATIC", "KSTD", "KSTRING", "KSTRONG", "KSTRONG0", 
                      "KSTRONG1", "KSTRUCT", "KSUPER", "KSUPPLY0", "KSUPPLY1", 
                      "KSYNC_ACCEPT_ON", "KSYNC_REJECT_ON", "KTAGGED", "KTASK", 
                      "KTHIS", "KTHROUGHOUT", "KTIME", "KTIMEPRECISION", 
                      "KTIMEUNIT", "KTRAN", "KTRANIF0", "KTRANIF1", "KTRI", 
                      "KTRI0", "KTRI1", "KTRIAND", "KTRIOR", "KTRIREG", 
                      "KTYPE", "KTYPE_OPTION", "KTYPEDEF", "KUNION", "KUNIQUE", 
                      "KUNIQUE0", "KUNSIGNED", "KUNTIL", "KUNTIL_WITH", 
                      "KUNTYPED", "KUSE", "KUWIRE", "KVAR", "KVECTORED", 
                      "KVIRTUAL", "KVOID", "KWAIT", "KWAIT_ORDER", "KWAND", 
                      "KWEAK", "KWEAK0", "KWEAK1", "KWHILE", "KWILDCARD", 
                      "KWIRE", "KWITH", "KWITHIN", "KWOR", "KXNOR", "KXOR", 
                      "COMPILER_DIRECTIVE", "FILE_PATH_SPEC", "TIME_LITERAL", 
                      "DECIMAL_NUMBER", "BINARY_NUMBER", "OCTAL_NUMBER", 
                      "HEX_NUMBER", "REAL_NUMBER", "UNSIGNED_NUMBER", "STRING_LITERAL", 
                      "ONE_LINE_COMMENT", "BLOCK_COMMENT", "SIMPLE_IDENTIFIER", 
                      "SYSTEM_TF_IDENTIFIER", "WHITE_SPACE" ]

    RULE_library_text = 0
    RULE_library_description = 1
    RULE_library_declaration = 2
    RULE_include_statement = 3
    RULE_source_text = 4
    RULE_description = 5
    RULE_module_nonansi_header = 6
    RULE_module_ansi_header = 7
    RULE_module_declaration = 8
    RULE_module_keyword = 9
    RULE_interface_declaration = 10
    RULE_interface_nonansi_header = 11
    RULE_interface_ansi_header = 12
    RULE_program_declaration = 13
    RULE_program_nonansi_header = 14
    RULE_program_ansi_header = 15
    RULE_checker_declaration = 16
    RULE_class_declaration = 17
    RULE_interface_class_type = 18
    RULE_interface_class_declaration = 19
    RULE_interface_class_item = 20
    RULE_interface_class_method = 21
    RULE_package_declaration = 22
    RULE_timeunits_declaration = 23
    RULE_parameter_port_list = 24
    RULE_parameter_port_declaration = 25
    RULE_list_of_ports = 26
    RULE_list_of_port_declarations = 27
    RULE_port_declaration = 28
    RULE_port = 29
    RULE_port_expression = 30
    RULE_port_reference = 31
    RULE_port_direction = 32
    RULE_net_port_header = 33
    RULE_variable_port_header = 34
    RULE_interface_port_header = 35
    RULE_ansi_port_declaration = 36
    RULE_elaboration_system_task = 37
    RULE_module_common_item = 38
    RULE_module_item = 39
    RULE_module_or_generate_item = 40
    RULE_module_or_generate_item_declaration = 41
    RULE_non_port_module_item = 42
    RULE_parameter_override = 43
    RULE_bind_directive = 44
    RULE_bind_target_scope = 45
    RULE_bind_target_instance = 46
    RULE_bind_target_instance_list = 47
    RULE_bind_instantiation = 48
    RULE_config_declaration = 49
    RULE_design_statement = 50
    RULE_config_rule_statement = 51
    RULE_default_clause = 52
    RULE_inst_clause = 53
    RULE_inst_name = 54
    RULE_cell_clause = 55
    RULE_liblist_clause = 56
    RULE_use_clause = 57
    RULE_interface_or_generate_item = 58
    RULE_extern_tf_declaration = 59
    RULE_interface_item = 60
    RULE_non_port_interface_item = 61
    RULE_program_item = 62
    RULE_non_port_program_item = 63
    RULE_program_generate_item = 64
    RULE_checker_port_list = 65
    RULE_checker_port_item = 66
    RULE_checker_port_direction = 67
    RULE_checker_or_generate_item = 68
    RULE_checker_or_generate_item_declaration = 69
    RULE_checker_generate_item = 70
    RULE_class_item = 71
    RULE_class_property = 72
    RULE_class_method = 73
    RULE_class_constructor_prototype = 74
    RULE_class_constraint = 75
    RULE_class_item_qualifier = 76
    RULE_property_qualifier = 77
    RULE_random_qualifier = 78
    RULE_method_qualifier = 79
    RULE_method_prototype = 80
    RULE_class_constructor_declaration = 81
    RULE_constraint_declaration = 82
    RULE_constraint_block = 83
    RULE_constraint_block_item = 84
    RULE_solve_before_list = 85
    RULE_constraint_primary = 86
    RULE_constraint_expression = 87
    RULE_uniqueness_constraint = 88
    RULE_constraint_set = 89
    RULE_dist_list = 90
    RULE_dist_item = 91
    RULE_dist_weight = 92
    RULE_constraint_prototype = 93
    RULE_constraint_prototype_qualifier = 94
    RULE_extern_constraint_declaration = 95
    RULE_identifier_list = 96
    RULE_package_item = 97
    RULE_package_or_generate_item_declaration = 98
    RULE_anonymous_program = 99
    RULE_anonymous_program_item = 100
    RULE_local_parameter_declaration = 101
    RULE_parameter_declaration = 102
    RULE_specparam_declaration = 103
    RULE_inout_declaration = 104
    RULE_input_declaration = 105
    RULE_output_declaration = 106
    RULE_interface_port_declaration = 107
    RULE_ref_declaration = 108
    RULE_data_declaration = 109
    RULE_package_import_declaration = 110
    RULE_package_import_item = 111
    RULE_package_export_declaration = 112
    RULE_genvar_declaration = 113
    RULE_net_declaration = 114
    RULE_type_declaration = 115
    RULE_net_type_declaration = 116
    RULE_lifetime = 117
    RULE_casting_type = 118
    RULE_data_type = 119
    RULE_data_type_or_implicit = 120
    RULE_implicit_data_type = 121
    RULE_enum_base_type = 122
    RULE_enum_name_declaration = 123
    RULE_class_scope = 124
    RULE_class_type = 125
    RULE_integer_type = 126
    RULE_integer_atom_type = 127
    RULE_integer_vector_type = 128
    RULE_non_integer_type = 129
    RULE_net_type = 130
    RULE_net_port_type = 131
    RULE_variable_port_type = 132
    RULE_var_data_type = 133
    RULE_signing = 134
    RULE_simple_type = 135
    RULE_struct_union_member = 136
    RULE_data_type_or_void = 137
    RULE_struct_union = 138
    RULE_type_reference = 139
    RULE_drive_strength = 140
    RULE_strength0 = 141
    RULE_strength1 = 142
    RULE_charge_strength = 143
    RULE_delay3 = 144
    RULE_delay2 = 145
    RULE_delay_value = 146
    RULE_list_of_defparam_assignments = 147
    RULE_list_of_genvar_identifiers = 148
    RULE_list_of_interface_identifiers = 149
    RULE_list_of_net_decl_assignments = 150
    RULE_list_of_param_assignments = 151
    RULE_list_of_port_identifiers = 152
    RULE_list_of_udp_port_identifiers = 153
    RULE_list_of_specparam_assignments = 154
    RULE_list_of_tf_variable_identifiers = 155
    RULE_list_of_type_assignments = 156
    RULE_list_of_variable_decl_assignments = 157
    RULE_list_of_variable_identifiers = 158
    RULE_list_of_variable_port_identifiers = 159
    RULE_defparam_assignment = 160
    RULE_net_decl_assignment = 161
    RULE_param_assignment = 162
    RULE_specparam_assignment = 163
    RULE_type_assignment = 164
    RULE_pulse_control_specparam = 165
    RULE_error_limit_value = 166
    RULE_reject_limit_value = 167
    RULE_limit_value = 168
    RULE_variable_decl_assignment = 169
    RULE_class_new = 170
    RULE_dynamic_array_new = 171
    RULE_unpacked_dimension = 172
    RULE_packed_dimension = 173
    RULE_associative_dimension = 174
    RULE_variable_dimension = 175
    RULE_queue_dimension = 176
    RULE_unsized_dimension = 177
    RULE_function_data_type_or_implicit = 178
    RULE_function_declaration = 179
    RULE_function_body_declaration = 180
    RULE_function_prototype = 181
    RULE_dpi_import_export = 182
    RULE_dpi_spec_string = 183
    RULE_dpi_function_import_property = 184
    RULE_dpi_task_import_property = 185
    RULE_dpi_function_proto = 186
    RULE_dpi_task_proto = 187
    RULE_task_declaration = 188
    RULE_task_body_declaration = 189
    RULE_tf_item_declaration = 190
    RULE_tf_port_list = 191
    RULE_tf_port_item = 192
    RULE_tf_port_direction = 193
    RULE_tf_port_declaration = 194
    RULE_task_prototype = 195
    RULE_block_item_declaration = 196
    RULE_modport_declaration = 197
    RULE_modport_item = 198
    RULE_modport_ports_declaration = 199
    RULE_modport_clocking_declaration = 200
    RULE_modport_simple_ports_declaration = 201
    RULE_modport_simple_port = 202
    RULE_modport_tf_ports_declaration = 203
    RULE_modport_tf_port = 204
    RULE_import_export = 205
    RULE_concurrent_assertion_item = 206
    RULE_concurrent_assertion_statement = 207
    RULE_assert_property_statement = 208
    RULE_assume_property_statement = 209
    RULE_cover_property_statement = 210
    RULE_expect_property_statement = 211
    RULE_cover_sequence_statement = 212
    RULE_restrict_property_statement = 213
    RULE_property_instance = 214
    RULE_property_list_of_arguments = 215
    RULE_property_actual_arg = 216
    RULE_assertion_item_declaration = 217
    RULE_property_declaration = 218
    RULE_property_port_list = 219
    RULE_property_port_item = 220
    RULE_property_lvar_port_direction = 221
    RULE_property_formal_type = 222
    RULE_property_spec = 223
    RULE_property_expr = 224
    RULE_property_case_item = 225
    RULE_sequence_declaration = 226
    RULE_sequence_port_list = 227
    RULE_sequence_port_item = 228
    RULE_sequence_lvar_port_direction = 229
    RULE_sequence_formal_type = 230
    RULE_sequence_expr = 231
    RULE_cycle_delay_range = 232
    RULE_sequence_method_call = 233
    RULE_sequence_match_item = 234
    RULE_sequence_instance = 235
    RULE_sequence_list_of_arguments = 236
    RULE_sequence_actual_arg = 237
    RULE_boolean_abbrev = 238
    RULE_sequence_abbrev = 239
    RULE_consecutive_repetition = 240
    RULE_non_consecutive_repetition = 241
    RULE_goto_repetition = 242
    RULE_const_or_range_expression = 243
    RULE_cycle_delay_const_range_expression = 244
    RULE_expression_or_dist = 245
    RULE_assertion_variable_declaration = 246
    RULE_covergroup_declaration = 247
    RULE_coverage_spec_or_option = 248
    RULE_coverage_option = 249
    RULE_coverage_spec = 250
    RULE_coverage_event = 251
    RULE_block_event_expression = 252
    RULE_hierarchical_btf_identifier = 253
    RULE_cover_point = 254
    RULE_bins_or_empty = 255
    RULE_bins_or_options = 256
    RULE_bins_keyword = 257
    RULE_trans_list = 258
    RULE_trans_set = 259
    RULE_trans_range_list = 260
    RULE_trans_item = 261
    RULE_repeat_range = 262
    RULE_cover_cross = 263
    RULE_list_of_cross_items = 264
    RULE_cross_item = 265
    RULE_cross_body = 266
    RULE_cross_body_item = 267
    RULE_bins_selection_or_option = 268
    RULE_bins_selection = 269
    RULE_select_expression = 270
    RULE_select_condition = 271
    RULE_bins_expression = 272
    RULE_covergroup_range_list = 273
    RULE_covergroup_value_range = 274
    RULE_with_covergroup_expression = 275
    RULE_set_covergroup_expression = 276
    RULE_integer_covergroup_expression = 277
    RULE_cross_set_expression = 278
    RULE_covergroup_expression = 279
    RULE_let_declaration = 280
    RULE_let_identifier = 281
    RULE_let_port_list = 282
    RULE_let_port_item = 283
    RULE_let_formal_type = 284
    RULE_let_expression = 285
    RULE_let_list_of_arguments = 286
    RULE_let_actual_arg = 287
    RULE_gate_instantiation = 288
    RULE_cmos_switch_instance = 289
    RULE_enable_gate_instance = 290
    RULE_mos_switch_instance = 291
    RULE_n_input_gate_instance = 292
    RULE_n_output_gate_instance = 293
    RULE_pass_switch_instance = 294
    RULE_pass_enable_switch_instance = 295
    RULE_pull_gate_instance = 296
    RULE_pulldown_strength = 297
    RULE_pullup_strength = 298
    RULE_enable_terminal = 299
    RULE_inout_terminal = 300
    RULE_input_terminal = 301
    RULE_ncontrol_terminal = 302
    RULE_output_terminal = 303
    RULE_pcontrol_terminal = 304
    RULE_cmos_switchtype = 305
    RULE_enable_gatetype = 306
    RULE_mos_switchtype = 307
    RULE_n_input_gatetype = 308
    RULE_n_output_gatetype = 309
    RULE_pass_en_switchtype = 310
    RULE_pass_switchtype = 311
    RULE_module_instantiation = 312
    RULE_parameter_value_assignment = 313
    RULE_list_of_parameter_assignments = 314
    RULE_ordered_parameter_assignment = 315
    RULE_named_parameter_assignment = 316
    RULE_hierarchical_instance = 317
    RULE_name_of_instance = 318
    RULE_list_of_port_connections = 319
    RULE_ordered_port_connection = 320
    RULE_named_port_connection = 321
    RULE_interface_instantiation = 322
    RULE_program_instantiation = 323
    RULE_checker_instantiation = 324
    RULE_list_of_checker_port_connections = 325
    RULE_ordered_checker_port_connection = 326
    RULE_named_checker_port_connection = 327
    RULE_generate_region = 328
    RULE_loop_generate_construct = 329
    RULE_genvar_initialization = 330
    RULE_genvar_iteration = 331
    RULE_conditional_generate_construct = 332
    RULE_if_generate_construct = 333
    RULE_case_generate_construct = 334
    RULE_case_generate_item = 335
    RULE_generate_block = 336
    RULE_generate_item = 337
    RULE_continuous_assign = 338
    RULE_list_of_net_assignments = 339
    RULE_list_of_variable_assignments = 340
    RULE_net_alias = 341
    RULE_net_assignment = 342
    RULE_initial_construct = 343
    RULE_always_construct = 344
    RULE_always_keyword = 345
    RULE_final_construct = 346
    RULE_blocking_assignment = 347
    RULE_operator_assignment = 348
    RULE_assignment_operator = 349
    RULE_nonblocking_assignment = 350
    RULE_procedural_continuous_assignment = 351
    RULE_variable_assignment = 352
    RULE_action_block = 353
    RULE_seq_block = 354
    RULE_par_block = 355
    RULE_join_keyword = 356
    RULE_statement_or_null = 357
    RULE_statement = 358
    RULE_statement_item = 359
    RULE_function_statement = 360
    RULE_function_statement_or_null = 361
    RULE_variable_identifier_list = 362
    RULE_procedural_timing_control_statement = 363
    RULE_delay_or_event_control = 364
    RULE_delay_control = 365
    RULE_event_control = 366
    RULE_event_expression = 367
    RULE_procedural_timing_control = 368
    RULE_jump_statement = 369
    RULE_wait_statement = 370
    RULE_event_trigger = 371
    RULE_disable_statement = 372
    RULE_conditional_statement = 373
    RULE_unique_priority = 374
    RULE_cond_predicate = 375
    RULE_expression_or_cond_pattern = 376
    RULE_cond_pattern = 377
    RULE_case_statement = 378
    RULE_case_keyword = 379
    RULE_case_expression = 380
    RULE_case_item = 381
    RULE_case_pattern_item = 382
    RULE_case_inside_item = 383
    RULE_case_item_expression = 384
    RULE_randcase_statement = 385
    RULE_randcase_item = 386
    RULE_open_range_list = 387
    RULE_open_value_range = 388
    RULE_pattern = 389
    RULE_assignment_pattern = 390
    RULE_structure_pattern_key = 391
    RULE_array_pattern_key = 392
    RULE_assignment_pattern_key = 393
    RULE_assignment_pattern_expression = 394
    RULE_assignment_pattern_expression_type = 395
    RULE_constant_assignment_pattern_expression = 396
    RULE_assignment_pattern_net_lvalue = 397
    RULE_assignment_pattern_variable_lvalue = 398
    RULE_loop_statement = 399
    RULE_for_initialization = 400
    RULE_for_variable_declaration = 401
    RULE_for_step = 402
    RULE_for_step_assignment = 403
    RULE_loop_variables = 404
    RULE_subroutine_call_statement = 405
    RULE_assertion_item = 406
    RULE_deferred_immediate_assertion_item = 407
    RULE_procedural_assertion_statement = 408
    RULE_immediate_assertion_statement = 409
    RULE_simple_immediate_assertion_statement = 410
    RULE_simple_immediate_assert_statement = 411
    RULE_simple_immediate_assume_statement = 412
    RULE_simple_immediate_cover_statement = 413
    RULE_deferred_immediate_assertion_statement = 414
    RULE_deferred_immediate_assert_statement = 415
    RULE_deferred_immediate_assume_statement = 416
    RULE_deferred_immediate_cover_statement = 417
    RULE_clocking_declaration = 418
    RULE_clocking_event = 419
    RULE_clocking_item = 420
    RULE_default_skew = 421
    RULE_clocking_direction = 422
    RULE_list_of_clocking_decl_assign = 423
    RULE_clocking_decl_assign = 424
    RULE_clocking_skew = 425
    RULE_clocking_drive = 426
    RULE_cycle_delay = 427
    RULE_clockvar = 428
    RULE_clockvar_expression = 429
    RULE_randsequence_statement = 430
    RULE_production = 431
    RULE_rs_rule = 432
    RULE_rs_production_list = 433
    RULE_weight_specification = 434
    RULE_rs_code_block = 435
    RULE_rs_prod = 436
    RULE_production_item = 437
    RULE_rs_if_else = 438
    RULE_rs_repeat = 439
    RULE_rs_case = 440
    RULE_rs_case_item = 441
    RULE_specify_block = 442
    RULE_specify_item = 443
    RULE_pulsestyle_declaration = 444
    RULE_showcancelled_declaration = 445
    RULE_path_declaration = 446
    RULE_simple_path_declaration = 447
    RULE_parallel_path_description = 448
    RULE_full_path_description = 449
    RULE_list_of_path_inputs = 450
    RULE_list_of_path_outputs = 451
    RULE_specify_input_terminal_descriptor = 452
    RULE_specify_output_terminal_descriptor = 453
    RULE_input_identifier = 454
    RULE_output_identifier = 455
    RULE_path_delay_value = 456
    RULE_list_of_path_delay_expressions = 457
    RULE_t_path_delay_expression = 458
    RULE_trise_path_delay_expression = 459
    RULE_tfall_path_delay_expression = 460
    RULE_tz_path_delay_expression = 461
    RULE_t01_path_delay_expression = 462
    RULE_t10_path_delay_expression = 463
    RULE_t0z_path_delay_expression = 464
    RULE_tz1_path_delay_expression = 465
    RULE_t1z_path_delay_expression = 466
    RULE_tz0_path_delay_expression = 467
    RULE_t0x_path_delay_expression = 468
    RULE_tx1_path_delay_expression = 469
    RULE_t1x_path_delay_expression = 470
    RULE_tx0_path_delay_expression = 471
    RULE_txz_path_delay_expression = 472
    RULE_tzx_path_delay_expression = 473
    RULE_path_delay_expression = 474
    RULE_edge_sensitive_path_declaration = 475
    RULE_parallel_edge_sensitive_path_description = 476
    RULE_full_edge_sensitive_path_description = 477
    RULE_data_source_expression = 478
    RULE_edge_identifier = 479
    RULE_state_dependent_path_declaration = 480
    RULE_polarity_operator = 481
    RULE_concatenation = 482
    RULE_constant_concatenation = 483
    RULE_constant_multiple_concatenation = 484
    RULE_module_path_concatenation = 485
    RULE_module_path_multiple_concatenation = 486
    RULE_multiple_concatenation = 487
    RULE_streaming_concatenation = 488
    RULE_stream_operator = 489
    RULE_slice_size = 490
    RULE_stream_concatenation = 491
    RULE_stream_expression = 492
    RULE_array_range_expression = 493
    RULE_empty_unpacked_array_concatenation = 494
    RULE_constant_function_call = 495
    RULE_tf_call = 496
    RULE_system_tf_call = 497
    RULE_subroutine_call = 498
    RULE_function_subroutine_call = 499
    RULE_list_of_arguments = 500
    RULE_method_call_body = 501
    RULE_built_in_method_call = 502
    RULE_array_manipulation_call = 503
    RULE_randomize_call = 504
    RULE_array_method_name = 505
    RULE_inc_or_dec_expression = 506
    RULE_constant_expression = 507
    RULE_constant_mintypmax_expression = 508
    RULE_constant_param_expression = 509
    RULE_param_expression = 510
    RULE_constant_range_expression = 511
    RULE_constant_part_select_range = 512
    RULE_constant_range = 513
    RULE_constant_indexed_range = 514
    RULE_expression = 515
    RULE_value_range = 516
    RULE_mintypmax_expression = 517
    RULE_module_path_expression = 518
    RULE_module_path_mintypmax_expression = 519
    RULE_part_select_range = 520
    RULE_indexed_range = 521
    RULE_genvar_expression = 522
    RULE_constant_primary = 523
    RULE_module_path_primary = 524
    RULE_primary = 525
    RULE_class_qualifier = 526
    RULE_range_expression = 527
    RULE_primary_literal = 528
    RULE_implicit_class_handle = 529
    RULE_bit_select = 530
    RULE_select_ = 531
    RULE_nonrange_select = 532
    RULE_constant_bit_select = 533
    RULE_constant_select = 534
    RULE_constant_let_expression = 535
    RULE_cast = 536
    RULE_net_lvalue = 537
    RULE_variable_lvalue = 538
    RULE_nonrange_variable_lvalue = 539
    RULE_unary_operator = 540
    RULE_binary_operator = 541
    RULE_inc_or_dec_operator = 542
    RULE_unary_module_path_operator = 543
    RULE_binary_module_path_operator = 544
    RULE_number = 545
    RULE_attribute_instance = 546
    RULE_attr_spec = 547
    RULE_attr_name = 548
    RULE_array_identifier = 549
    RULE_block_identifier = 550
    RULE_bin_identifier = 551
    RULE_c_identifier = 552
    RULE_cell_identifier = 553
    RULE_checker_identifier = 554
    RULE_class_identifier = 555
    RULE_class_variable_identifier = 556
    RULE_clocking_identifier = 557
    RULE_config_identifier = 558
    RULE_const_identifier = 559
    RULE_constraint_identifier = 560
    RULE_covergroup_identifier = 561
    RULE_covergroup_variable_identifier = 562
    RULE_cover_point_identifier = 563
    RULE_cross_identifier = 564
    RULE_dynamic_array_variable_identifier = 565
    RULE_enum_identifier = 566
    RULE_formal_port_identifier = 567
    RULE_function_identifier = 568
    RULE_generate_block_identifier = 569
    RULE_genvar_identifier = 570
    RULE_hierarchical_array_identifier = 571
    RULE_hierarchical_block_identifier = 572
    RULE_hierarchical_event_identifier = 573
    RULE_hierarchical_identifier = 574
    RULE_hierarchical_net_identifier = 575
    RULE_hierarchical_parameter_identifier = 576
    RULE_hierarchical_property_identifier = 577
    RULE_hierarchical_sequence_identifier = 578
    RULE_hierarchical_task_identifier = 579
    RULE_hierarchical_tf_identifier = 580
    RULE_hierarchical_variable_identifier = 581
    RULE_identifier = 582
    RULE_index_variable_identifier = 583
    RULE_interface_identifier = 584
    RULE_interface_instance_identifier = 585
    RULE_inout_port_identifier = 586
    RULE_input_port_identifier = 587
    RULE_instance_identifier = 588
    RULE_library_identifier = 589
    RULE_member_identifier = 590
    RULE_method_identifier = 591
    RULE_modport_identifier = 592
    RULE_module_identifier = 593
    RULE_net_identifier = 594
    RULE_net_type_identifier = 595
    RULE_output_port_identifier = 596
    RULE_package_identifier = 597
    RULE_package_scope = 598
    RULE_parameter_identifier = 599
    RULE_port_identifier = 600
    RULE_production_identifier = 601
    RULE_program_identifier = 602
    RULE_property_identifier = 603
    RULE_ps_class_identifier = 604
    RULE_ps_covergroup_identifier = 605
    RULE_ps_checker_identifier = 606
    RULE_ps_identifier = 607
    RULE_ps_or_hierarchical_array_identifier = 608
    RULE_ps_or_hierarchical_net_identifier = 609
    RULE_ps_or_hierarchical_property_identifier = 610
    RULE_ps_or_hierarchical_sequence_identifier = 611
    RULE_ps_or_hierarchical_tf_identifier = 612
    RULE_ps_parameter_identifier = 613
    RULE_ps_type_identifier = 614
    RULE_sequence_identifier = 615
    RULE_signal_identifier = 616
    RULE_specparam_identifier = 617
    RULE_task_identifier = 618
    RULE_tf_identifier = 619
    RULE_topmodule_identifier = 620
    RULE_type_identifier = 621
    RULE_variable_identifier = 622

    ruleNames =  [ "library_text", "library_description", "library_declaration", 
                   "include_statement", "source_text", "description", "module_nonansi_header", 
                   "module_ansi_header", "module_declaration", "module_keyword", 
                   "interface_declaration", "interface_nonansi_header", 
                   "interface_ansi_header", "program_declaration", "program_nonansi_header", 
                   "program_ansi_header", "checker_declaration", "class_declaration", 
                   "interface_class_type", "interface_class_declaration", 
                   "interface_class_item", "interface_class_method", "package_declaration", 
                   "timeunits_declaration", "parameter_port_list", "parameter_port_declaration", 
                   "list_of_ports", "list_of_port_declarations", "port_declaration", 
                   "port", "port_expression", "port_reference", "port_direction", 
                   "net_port_header", "variable_port_header", "interface_port_header", 
                   "ansi_port_declaration", "elaboration_system_task", "module_common_item", 
                   "module_item", "module_or_generate_item", "module_or_generate_item_declaration", 
                   "non_port_module_item", "parameter_override", "bind_directive", 
                   "bind_target_scope", "bind_target_instance", "bind_target_instance_list", 
                   "bind_instantiation", "config_declaration", "design_statement", 
                   "config_rule_statement", "default_clause", "inst_clause", 
                   "inst_name", "cell_clause", "liblist_clause", "use_clause", 
                   "interface_or_generate_item", "extern_tf_declaration", 
                   "interface_item", "non_port_interface_item", "program_item", 
                   "non_port_program_item", "program_generate_item", "checker_port_list", 
                   "checker_port_item", "checker_port_direction", "checker_or_generate_item", 
                   "checker_or_generate_item_declaration", "checker_generate_item", 
                   "class_item", "class_property", "class_method", "class_constructor_prototype", 
                   "class_constraint", "class_item_qualifier", "property_qualifier", 
                   "random_qualifier", "method_qualifier", "method_prototype", 
                   "class_constructor_declaration", "constraint_declaration", 
                   "constraint_block", "constraint_block_item", "solve_before_list", 
                   "constraint_primary", "constraint_expression", "uniqueness_constraint", 
                   "constraint_set", "dist_list", "dist_item", "dist_weight", 
                   "constraint_prototype", "constraint_prototype_qualifier", 
                   "extern_constraint_declaration", "identifier_list", "package_item", 
                   "package_or_generate_item_declaration", "anonymous_program", 
                   "anonymous_program_item", "local_parameter_declaration", 
                   "parameter_declaration", "specparam_declaration", "inout_declaration", 
                   "input_declaration", "output_declaration", "interface_port_declaration", 
                   "ref_declaration", "data_declaration", "package_import_declaration", 
                   "package_import_item", "package_export_declaration", 
                   "genvar_declaration", "net_declaration", "type_declaration", 
                   "net_type_declaration", "lifetime", "casting_type", "data_type", 
                   "data_type_or_implicit", "implicit_data_type", "enum_base_type", 
                   "enum_name_declaration", "class_scope", "class_type", 
                   "integer_type", "integer_atom_type", "integer_vector_type", 
                   "non_integer_type", "net_type", "net_port_type", "variable_port_type", 
                   "var_data_type", "signing", "simple_type", "struct_union_member", 
                   "data_type_or_void", "struct_union", "type_reference", 
                   "drive_strength", "strength0", "strength1", "charge_strength", 
                   "delay3", "delay2", "delay_value", "list_of_defparam_assignments", 
                   "list_of_genvar_identifiers", "list_of_interface_identifiers", 
                   "list_of_net_decl_assignments", "list_of_param_assignments", 
                   "list_of_port_identifiers", "list_of_udp_port_identifiers", 
                   "list_of_specparam_assignments", "list_of_tf_variable_identifiers", 
                   "list_of_type_assignments", "list_of_variable_decl_assignments", 
                   "list_of_variable_identifiers", "list_of_variable_port_identifiers", 
                   "defparam_assignment", "net_decl_assignment", "param_assignment", 
                   "specparam_assignment", "type_assignment", "pulse_control_specparam", 
                   "error_limit_value", "reject_limit_value", "limit_value", 
                   "variable_decl_assignment", "class_new", "dynamic_array_new", 
                   "unpacked_dimension", "packed_dimension", "associative_dimension", 
                   "variable_dimension", "queue_dimension", "unsized_dimension", 
                   "function_data_type_or_implicit", "function_declaration", 
                   "function_body_declaration", "function_prototype", "dpi_import_export", 
                   "dpi_spec_string", "dpi_function_import_property", "dpi_task_import_property", 
                   "dpi_function_proto", "dpi_task_proto", "task_declaration", 
                   "task_body_declaration", "tf_item_declaration", "tf_port_list", 
                   "tf_port_item", "tf_port_direction", "tf_port_declaration", 
                   "task_prototype", "block_item_declaration", "modport_declaration", 
                   "modport_item", "modport_ports_declaration", "modport_clocking_declaration", 
                   "modport_simple_ports_declaration", "modport_simple_port", 
                   "modport_tf_ports_declaration", "modport_tf_port", "import_export", 
                   "concurrent_assertion_item", "concurrent_assertion_statement", 
                   "assert_property_statement", "assume_property_statement", 
                   "cover_property_statement", "expect_property_statement", 
                   "cover_sequence_statement", "restrict_property_statement", 
                   "property_instance", "property_list_of_arguments", "property_actual_arg", 
                   "assertion_item_declaration", "property_declaration", 
                   "property_port_list", "property_port_item", "property_lvar_port_direction", 
                   "property_formal_type", "property_spec", "property_expr", 
                   "property_case_item", "sequence_declaration", "sequence_port_list", 
                   "sequence_port_item", "sequence_lvar_port_direction", 
                   "sequence_formal_type", "sequence_expr", "cycle_delay_range", 
                   "sequence_method_call", "sequence_match_item", "sequence_instance", 
                   "sequence_list_of_arguments", "sequence_actual_arg", 
                   "boolean_abbrev", "sequence_abbrev", "consecutive_repetition", 
                   "non_consecutive_repetition", "goto_repetition", "const_or_range_expression", 
                   "cycle_delay_const_range_expression", "expression_or_dist", 
                   "assertion_variable_declaration", "covergroup_declaration", 
                   "coverage_spec_or_option", "coverage_option", "coverage_spec", 
                   "coverage_event", "block_event_expression", "hierarchical_btf_identifier", 
                   "cover_point", "bins_or_empty", "bins_or_options", "bins_keyword", 
                   "trans_list", "trans_set", "trans_range_list", "trans_item", 
                   "repeat_range", "cover_cross", "list_of_cross_items", 
                   "cross_item", "cross_body", "cross_body_item", "bins_selection_or_option", 
                   "bins_selection", "select_expression", "select_condition", 
                   "bins_expression", "covergroup_range_list", "covergroup_value_range", 
                   "with_covergroup_expression", "set_covergroup_expression", 
                   "integer_covergroup_expression", "cross_set_expression", 
                   "covergroup_expression", "let_declaration", "let_identifier", 
                   "let_port_list", "let_port_item", "let_formal_type", 
                   "let_expression", "let_list_of_arguments", "let_actual_arg", 
                   "gate_instantiation", "cmos_switch_instance", "enable_gate_instance", 
                   "mos_switch_instance", "n_input_gate_instance", "n_output_gate_instance", 
                   "pass_switch_instance", "pass_enable_switch_instance", 
                   "pull_gate_instance", "pulldown_strength", "pullup_strength", 
                   "enable_terminal", "inout_terminal", "input_terminal", 
                   "ncontrol_terminal", "output_terminal", "pcontrol_terminal", 
                   "cmos_switchtype", "enable_gatetype", "mos_switchtype", 
                   "n_input_gatetype", "n_output_gatetype", "pass_en_switchtype", 
                   "pass_switchtype", "module_instantiation", "parameter_value_assignment", 
                   "list_of_parameter_assignments", "ordered_parameter_assignment", 
                   "named_parameter_assignment", "hierarchical_instance", 
                   "name_of_instance", "list_of_port_connections", "ordered_port_connection", 
                   "named_port_connection", "interface_instantiation", "program_instantiation", 
                   "checker_instantiation", "list_of_checker_port_connections", 
                   "ordered_checker_port_connection", "named_checker_port_connection", 
                   "generate_region", "loop_generate_construct", "genvar_initialization", 
                   "genvar_iteration", "conditional_generate_construct", 
                   "if_generate_construct", "case_generate_construct", "case_generate_item", 
                   "generate_block", "generate_item", "continuous_assign", 
                   "list_of_net_assignments", "list_of_variable_assignments", 
                   "net_alias", "net_assignment", "initial_construct", "always_construct", 
                   "always_keyword", "final_construct", "blocking_assignment", 
                   "operator_assignment", "assignment_operator", "nonblocking_assignment", 
                   "procedural_continuous_assignment", "variable_assignment", 
                   "action_block", "seq_block", "par_block", "join_keyword", 
                   "statement_or_null", "statement", "statement_item", "function_statement", 
                   "function_statement_or_null", "variable_identifier_list", 
                   "procedural_timing_control_statement", "delay_or_event_control", 
                   "delay_control", "event_control", "event_expression", 
                   "procedural_timing_control", "jump_statement", "wait_statement", 
                   "event_trigger", "disable_statement", "conditional_statement", 
                   "unique_priority", "cond_predicate", "expression_or_cond_pattern", 
                   "cond_pattern", "case_statement", "case_keyword", "case_expression", 
                   "case_item", "case_pattern_item", "case_inside_item", 
                   "case_item_expression", "randcase_statement", "randcase_item", 
                   "open_range_list", "open_value_range", "pattern", "assignment_pattern", 
                   "structure_pattern_key", "array_pattern_key", "assignment_pattern_key", 
                   "assignment_pattern_expression", "assignment_pattern_expression_type", 
                   "constant_assignment_pattern_expression", "assignment_pattern_net_lvalue", 
                   "assignment_pattern_variable_lvalue", "loop_statement", 
                   "for_initialization", "for_variable_declaration", "for_step", 
                   "for_step_assignment", "loop_variables", "subroutine_call_statement", 
                   "assertion_item", "deferred_immediate_assertion_item", 
                   "procedural_assertion_statement", "immediate_assertion_statement", 
                   "simple_immediate_assertion_statement", "simple_immediate_assert_statement", 
                   "simple_immediate_assume_statement", "simple_immediate_cover_statement", 
                   "deferred_immediate_assertion_statement", "deferred_immediate_assert_statement", 
                   "deferred_immediate_assume_statement", "deferred_immediate_cover_statement", 
                   "clocking_declaration", "clocking_event", "clocking_item", 
                   "default_skew", "clocking_direction", "list_of_clocking_decl_assign", 
                   "clocking_decl_assign", "clocking_skew", "clocking_drive", 
                   "cycle_delay", "clockvar", "clockvar_expression", "randsequence_statement", 
                   "production", "rs_rule", "rs_production_list", "weight_specification", 
                   "rs_code_block", "rs_prod", "production_item", "rs_if_else", 
                   "rs_repeat", "rs_case", "rs_case_item", "specify_block", 
                   "specify_item", "pulsestyle_declaration", "showcancelled_declaration", 
                   "path_declaration", "simple_path_declaration", "parallel_path_description", 
                   "full_path_description", "list_of_path_inputs", "list_of_path_outputs", 
                   "specify_input_terminal_descriptor", "specify_output_terminal_descriptor", 
                   "input_identifier", "output_identifier", "path_delay_value", 
                   "list_of_path_delay_expressions", "t_path_delay_expression", 
                   "trise_path_delay_expression", "tfall_path_delay_expression", 
                   "tz_path_delay_expression", "t01_path_delay_expression", 
                   "t10_path_delay_expression", "t0z_path_delay_expression", 
                   "tz1_path_delay_expression", "t1z_path_delay_expression", 
                   "tz0_path_delay_expression", "t0x_path_delay_expression", 
                   "tx1_path_delay_expression", "t1x_path_delay_expression", 
                   "tx0_path_delay_expression", "txz_path_delay_expression", 
                   "tzx_path_delay_expression", "path_delay_expression", 
                   "edge_sensitive_path_declaration", "parallel_edge_sensitive_path_description", 
                   "full_edge_sensitive_path_description", "data_source_expression", 
                   "edge_identifier", "state_dependent_path_declaration", 
                   "polarity_operator", "concatenation", "constant_concatenation", 
                   "constant_multiple_concatenation", "module_path_concatenation", 
                   "module_path_multiple_concatenation", "multiple_concatenation", 
                   "streaming_concatenation", "stream_operator", "slice_size", 
                   "stream_concatenation", "stream_expression", "array_range_expression", 
                   "empty_unpacked_array_concatenation", "constant_function_call", 
                   "tf_call", "system_tf_call", "subroutine_call", "function_subroutine_call", 
                   "list_of_arguments", "method_call_body", "built_in_method_call", 
                   "array_manipulation_call", "randomize_call", "array_method_name", 
                   "inc_or_dec_expression", "constant_expression", "constant_mintypmax_expression", 
                   "constant_param_expression", "param_expression", "constant_range_expression", 
                   "constant_part_select_range", "constant_range", "constant_indexed_range", 
                   "expression", "value_range", "mintypmax_expression", 
                   "module_path_expression", "module_path_mintypmax_expression", 
                   "part_select_range", "indexed_range", "genvar_expression", 
                   "constant_primary", "module_path_primary", "primary", 
                   "class_qualifier", "range_expression", "primary_literal", 
                   "implicit_class_handle", "bit_select", "select_", "nonrange_select", 
                   "constant_bit_select", "constant_select", "constant_let_expression", 
                   "cast", "net_lvalue", "variable_lvalue", "nonrange_variable_lvalue", 
                   "unary_operator", "binary_operator", "inc_or_dec_operator", 
                   "unary_module_path_operator", "binary_module_path_operator", 
                   "number", "attribute_instance", "attr_spec", "attr_name", 
                   "array_identifier", "block_identifier", "bin_identifier", 
                   "c_identifier", "cell_identifier", "checker_identifier", 
                   "class_identifier", "class_variable_identifier", "clocking_identifier", 
                   "config_identifier", "const_identifier", "constraint_identifier", 
                   "covergroup_identifier", "covergroup_variable_identifier", 
                   "cover_point_identifier", "cross_identifier", "dynamic_array_variable_identifier", 
                   "enum_identifier", "formal_port_identifier", "function_identifier", 
                   "generate_block_identifier", "genvar_identifier", "hierarchical_array_identifier", 
                   "hierarchical_block_identifier", "hierarchical_event_identifier", 
                   "hierarchical_identifier", "hierarchical_net_identifier", 
                   "hierarchical_parameter_identifier", "hierarchical_property_identifier", 
                   "hierarchical_sequence_identifier", "hierarchical_task_identifier", 
                   "hierarchical_tf_identifier", "hierarchical_variable_identifier", 
                   "identifier", "index_variable_identifier", "interface_identifier", 
                   "interface_instance_identifier", "inout_port_identifier", 
                   "input_port_identifier", "instance_identifier", "library_identifier", 
                   "member_identifier", "method_identifier", "modport_identifier", 
                   "module_identifier", "net_identifier", "net_type_identifier", 
                   "output_port_identifier", "package_identifier", "package_scope", 
                   "parameter_identifier", "port_identifier", "production_identifier", 
                   "program_identifier", "property_identifier", "ps_class_identifier", 
                   "ps_covergroup_identifier", "ps_checker_identifier", 
                   "ps_identifier", "ps_or_hierarchical_array_identifier", 
                   "ps_or_hierarchical_net_identifier", "ps_or_hierarchical_property_identifier", 
                   "ps_or_hierarchical_sequence_identifier", "ps_or_hierarchical_tf_identifier", 
                   "ps_parameter_identifier", "ps_type_identifier", "sequence_identifier", 
                   "signal_identifier", "specparam_identifier", "task_identifier", 
                   "tf_identifier", "topmodule_identifier", "type_identifier", 
                   "variable_identifier" ]

    EOF = Token.EOF
    MINUS=1
    MINUSMINS=2
    NOT=3
    NE=4
    NEQ=5
    NEE=6
    DPI=7
    DPIC=8
    P=9
    PP=10
    PMP=11
    PEP=12
    PZ=13
    DOLLAR=14
    DERROR=15
    DFATAL=16
    DINFO=17
    DROOT=18
    DUNIT=19
    DWARNING=20
    PER=21
    PE=22
    AND=23
    ANDAND=24
    ANDANDAND=25
    AE=26
    LP=27
    LPS=28
    RP=29
    STAR=30
    SRP=31
    SS=32
    SCCS=33
    SEQ=34
    SGT=35
    COMMA=36
    DOT=37
    DOTSTAR=38
    SLASH=39
    SLASHEQ=40
    COLON=41
    MCOLON=42
    COLONSLASH=43
    COLONCOLON=44
    COLONEQ=45
    SEMI=46
    QUES=47
    AT=48
    ATAT=49
    LB=50
    QUOTE=51
    RB=52
    CARET=53
    CARETSQUIG=54
    CARETEQ=55
    LC=56
    BAR=57
    BARBAR=58
    BAREQ=59
    BAREQGT=60
    BARARROW=61
    RC=62
    SQUIG=63
    SQUIGAND=64
    SQUIGCARET=65
    SQUIGBAR=66
    PLUS=67
    PLUSCOLON=68
    PLUSPLUS=69
    PLUSEQ=70
    LT=71
    LTLT=72
    LTLTLT=73
    LTLTLTEQ=74
    LTLTEQ=75
    LTEQ=76
    LTMINUSGT=77
    EQ=78
    MINUSEQ=79
    EQEQ=80
    EQEQQUEST=81
    EQEQEQ=82
    EQGT=83
    GT=84
    ARROW=85
    GE=86
    GTGT=87
    MINUSGTGT=88
    GTGTEQ=89
    GTGTGT=90
    GTGTGTEQ=91
    KONESTEP=92
    KACCEPT_ON=93
    KALIAS=94
    KALWAYS=95
    KALWAYS_COMB=96
    KALWAYS_FF=97
    KALWAYS_LATCH=98
    KAND=99
    KASSERT=100
    KASSIGN=101
    KASSUME=102
    KAUTOMATIC=103
    KBEFORE=104
    KBEGIN=105
    KBIND=106
    KBINS=107
    KBINSOF=108
    KBIT=109
    KBREAK=110
    KBUF=111
    KBUFIF0=112
    KBUFIF1=113
    KBYTE=114
    KCASE=115
    KCASEX=116
    KCASEZ=117
    KCELL=118
    KCHANDLE=119
    KCHECKER=120
    KCLASS=121
    KCLOCKING=122
    KCMOS=123
    KCONFIG=124
    KCONST=125
    KCONSTRAINT=126
    KCONTEXT=127
    KCONTINUE=128
    KCOVER=129
    KCOVERGROUP=130
    KCOVERPOINT=131
    KCROSS=132
    KDEASSIGN=133
    KDEFAULT=134
    KDEFPARAM=135
    KDESIGN=136
    KDISABLE=137
    KDIST=138
    KDO=139
    KEDGE=140
    KELSE=141
    KEND=142
    KENDCASE=143
    KENDCHECKER=144
    KENDCLASS=145
    KENDCLOCKING=146
    KENDCONFIG=147
    KENDFUNCTION=148
    KENDGENERATE=149
    KENDGROUP=150
    KENDINTERFACE=151
    KENDMODULE=152
    KENDPACKAGE=153
    KENDPROGRAM=154
    KENDPROPERTY=155
    KENDSEQUENCE=156
    KENDSPECIFY=157
    KENDTASK=158
    KENUM=159
    KEVENT=160
    KEVENTUALLY=161
    KEXPECT=162
    KEXPORT=163
    KEXTENDS=164
    KEXTERN=165
    KFINAL=166
    KFIRST_MATCH=167
    KFOR=168
    KFORCE=169
    KFOREACH=170
    KFOREVER=171
    KFORK=172
    KFORKJOIN=173
    KFUNCTION=174
    KGENERATE=175
    KGENVAR=176
    KGLOBAL=177
    KHIGHZ0=178
    KHIGHZ1=179
    KIF=180
    KIFF=181
    KIFNONE=182
    KIGNORE_BINS=183
    KILLEGAL_BINS=184
    KIMPLEMENTS=185
    KIMPLIES=186
    KIMPORT=187
    KINCDIR=188
    KINCLUDE=189
    KINITIAL=190
    KINOUT=191
    KINPUT=192
    KINSIDE=193
    KINSTANCE=194
    KINT=195
    KINTEGER=196
    KINTERCONNECT=197
    KINTERFACE=198
    KINTERSECT=199
    KJOIN=200
    KJOIN_ANY=201
    KJOIN_NONE=202
    KLARGE=203
    KLET=204
    KLIBLIST=205
    KLIBRARY=206
    KLOCAL=207
    KLOCALPARAM=208
    KLOGIC=209
    KLONGINT=210
    KMACROMODULE=211
    KMATCHES=212
    KMEDIUM=213
    KMEMBER_IDENTIFIER=214
    KMODPORT=215
    KMODULE=216
    KNAND=217
    KNEGEDGE=218
    KNETTYPE=219
    KNEW=220
    KNEXTTIME=221
    KNMOS=222
    KNOR=223
    KNOSHOWCANCELLED=224
    KNOT=225
    KNOTIF0=226
    KNOTIF1=227
    KNULL=228
    KOPTION=229
    KOR=230
    KOUTPUT=231
    KPACKAGE=232
    KPACKED=233
    KPARAMETER=234
    KPATHPULSE=235
    KPMOS=236
    KPOSEDGE=237
    KPRIORITY=238
    KPROGRAM=239
    KPROPERTY=240
    KPROTECTED=241
    KPULL0=242
    KPULL1=243
    KPULLDOWN=244
    KPULLUP=245
    KPULSESTYLE_ONDETECT=246
    KPULSESTYLE_ONEVENT=247
    KPURE=248
    KRAND=249
    KRANDC=250
    KRANDCASE=251
    KRANDOMIZE=252
    KRANDSEQUENCE=253
    KRCMOS=254
    KREAL=255
    KREALTIME=256
    KREF=257
    KREG=258
    KREJECT_ON=259
    KRELEASE=260
    KREPEAT=261
    KRESTRICT=262
    KRETURN=263
    KRNMOS=264
    KRPMOS=265
    KRTRAN=266
    KRTRANIF0=267
    KRTRANIF1=268
    KS_ALWAYS=269
    KS_EVENTUALLY=270
    KS_NEXTTIME=271
    KS_UNTIL=272
    KS_UNTIL_WITH=273
    KSCALARED=274
    KSEQUENCE=275
    KSHORTINT=276
    KSHORTREAL=277
    KSHOWCANCELLED=278
    KSIGNED=279
    KSMALL=280
    KSOFT=281
    KSOLVE=282
    KSPECIFY=283
    KSPECPARAM=284
    KSTATIC=285
    KSTD=286
    KSTRING=287
    KSTRONG=288
    KSTRONG0=289
    KSTRONG1=290
    KSTRUCT=291
    KSUPER=292
    KSUPPLY0=293
    KSUPPLY1=294
    KSYNC_ACCEPT_ON=295
    KSYNC_REJECT_ON=296
    KTAGGED=297
    KTASK=298
    KTHIS=299
    KTHROUGHOUT=300
    KTIME=301
    KTIMEPRECISION=302
    KTIMEUNIT=303
    KTRAN=304
    KTRANIF0=305
    KTRANIF1=306
    KTRI=307
    KTRI0=308
    KTRI1=309
    KTRIAND=310
    KTRIOR=311
    KTRIREG=312
    KTYPE=313
    KTYPE_OPTION=314
    KTYPEDEF=315
    KUNION=316
    KUNIQUE=317
    KUNIQUE0=318
    KUNSIGNED=319
    KUNTIL=320
    KUNTIL_WITH=321
    KUNTYPED=322
    KUSE=323
    KUWIRE=324
    KVAR=325
    KVECTORED=326
    KVIRTUAL=327
    KVOID=328
    KWAIT=329
    KWAIT_ORDER=330
    KWAND=331
    KWEAK=332
    KWEAK0=333
    KWEAK1=334
    KWHILE=335
    KWILDCARD=336
    KWIRE=337
    KWITH=338
    KWITHIN=339
    KWOR=340
    KXNOR=341
    KXOR=342
    COMPILER_DIRECTIVE=343
    FILE_PATH_SPEC=344
    TIME_LITERAL=345
    DECIMAL_NUMBER=346
    BINARY_NUMBER=347
    OCTAL_NUMBER=348
    HEX_NUMBER=349
    REAL_NUMBER=350
    UNSIGNED_NUMBER=351
    STRING_LITERAL=352
    ONE_LINE_COMMENT=353
    BLOCK_COMMENT=354
    SIMPLE_IDENTIFIER=355
    SYSTEM_TF_IDENTIFIER=356
    WHITE_SPACE=357

    def __init__(self, input:TokenStream, output:TextIO = sys.stdout):
        super().__init__(input, output)
        self.checkVersion("4.9.3")
        self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache)
        self._predicates = None




    class Library_textContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def library_description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Library_descriptionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Library_descriptionContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_library_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_text" ):
                listener.enterLibrary_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_text" ):
                listener.exitLibrary_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_text" ):
                return visitor.visitLibrary_text(self)
            else:
                return visitor.visitChildren(self)




    def library_text(self):

        localctx = SystemVerilogParser.Library_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 0, self.RULE_library_text)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1249
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.SEMI or _la==SystemVerilogParser.KCONFIG or _la==SystemVerilogParser.KINCLUDE or _la==SystemVerilogParser.KLIBRARY:
                self.state = 1246
                self.library_description()
                self.state = 1251
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Library_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def library_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Library_declarationContext,0)


        def include_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Include_statementContext,0)


        def config_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Config_declarationContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_library_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_description" ):
                listener.enterLibrary_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_description" ):
                listener.exitLibrary_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_description" ):
                return visitor.visitLibrary_description(self)
            else:
                return visitor.visitChildren(self)




    def library_description(self):

        localctx = SystemVerilogParser.Library_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 2, self.RULE_library_description)
        try:
            self.state = 1256
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KLIBRARY]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1252
                self.library_declaration()
                pass
            elif token in [SystemVerilogParser.KINCLUDE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1253
                self.include_statement()
                pass
            elif token in [SystemVerilogParser.KCONFIG]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1254
                self.config_declaration()
                pass
            elif token in [SystemVerilogParser.SEMI]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1255
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Library_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KLIBRARY(self):
            return self.getToken(SystemVerilogParser.KLIBRARY, 0)

        def library_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Library_identifierContext,0)


        def FILE_PATH_SPEC(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.FILE_PATH_SPEC)
            else:
                return self.getToken(SystemVerilogParser.FILE_PATH_SPEC, i)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def KINCDIR(self):
            return self.getToken(SystemVerilogParser.KINCDIR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_library_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_declaration" ):
                listener.enterLibrary_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_declaration" ):
                listener.exitLibrary_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_declaration" ):
                return visitor.visitLibrary_declaration(self)
            else:
                return visitor.visitChildren(self)




    def library_declaration(self):

        localctx = SystemVerilogParser.Library_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 4, self.RULE_library_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1258
            self.match(SystemVerilogParser.KLIBRARY)
            self.state = 1259
            self.library_identifier()
            self.state = 1260
            self.match(SystemVerilogParser.FILE_PATH_SPEC)
            self.state = 1265
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 1261
                self.match(SystemVerilogParser.COMMA)
                self.state = 1262
                self.match(SystemVerilogParser.FILE_PATH_SPEC)
                self.state = 1267
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1277
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KINCDIR:
                self.state = 1268
                self.match(SystemVerilogParser.KINCDIR)
                self.state = 1269
                self.match(SystemVerilogParser.FILE_PATH_SPEC)
                self.state = 1274
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 1270
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 1271
                    self.match(SystemVerilogParser.FILE_PATH_SPEC)
                    self.state = 1276
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



            self.state = 1279
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Include_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINCLUDE(self):
            return self.getToken(SystemVerilogParser.KINCLUDE, 0)

        def FILE_PATH_SPEC(self):
            return self.getToken(SystemVerilogParser.FILE_PATH_SPEC, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_include_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInclude_statement" ):
                listener.enterInclude_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInclude_statement" ):
                listener.exitInclude_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInclude_statement" ):
                return visitor.visitInclude_statement(self)
            else:
                return visitor.visitChildren(self)




    def include_statement(self):

        localctx = SystemVerilogParser.Include_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 6, self.RULE_include_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1281
            self.match(SystemVerilogParser.KINCLUDE)
            self.state = 1282
            self.match(SystemVerilogParser.FILE_PATH_SPEC)
            self.state = 1283
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Source_textContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EOF(self):
            return self.getToken(SystemVerilogParser.EOF, 0)

        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.DescriptionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.DescriptionContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_source_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSource_text" ):
                listener.enterSource_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSource_text" ):
                listener.exitSource_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSource_text" ):
                return visitor.visitSource_text(self)
            else:
                return visitor.visitChildren(self)




    def source_text(self):

        localctx = SystemVerilogParser.Source_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 8, self.RULE_source_text)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1286
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,5,self._ctx)
            if la_ == 1:
                self.state = 1285
                self.timeunits_declaration()


            self.state = 1291
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 103)) & ~0x3f) == 0 and ((1 << (_la - 103)) & ((1 << (SystemVerilogParser.KAUTOMATIC - 103)) | (1 << (SystemVerilogParser.KBIND - 103)) | (1 << (SystemVerilogParser.KBIT - 103)) | (1 << (SystemVerilogParser.KBYTE - 103)) | (1 << (SystemVerilogParser.KCHANDLE - 103)) | (1 << (SystemVerilogParser.KCHECKER - 103)) | (1 << (SystemVerilogParser.KCLASS - 103)) | (1 << (SystemVerilogParser.KCONFIG - 103)) | (1 << (SystemVerilogParser.KCONST - 103)) | (1 << (SystemVerilogParser.KCONSTRAINT - 103)) | (1 << (SystemVerilogParser.KCOVERGROUP - 103)) | (1 << (SystemVerilogParser.KENUM - 103)) | (1 << (SystemVerilogParser.KEVENT - 103)) | (1 << (SystemVerilogParser.KEXPORT - 103)) | (1 << (SystemVerilogParser.KEXTERN - 103)))) != 0) or ((((_la - 174)) & ~0x3f) == 0 and ((1 << (_la - 174)) & ((1 << (SystemVerilogParser.KFUNCTION - 174)) | (1 << (SystemVerilogParser.KIMPORT - 174)) | (1 << (SystemVerilogParser.KINT - 174)) | (1 << (SystemVerilogParser.KINTEGER - 174)) | (1 << (SystemVerilogParser.KINTERCONNECT - 174)) | (1 << (SystemVerilogParser.KINTERFACE - 174)) | (1 << (SystemVerilogParser.KLET - 174)) | (1 << (SystemVerilogParser.KLOCALPARAM - 174)) | (1 << (SystemVerilogParser.KLOGIC - 174)) | (1 << (SystemVerilogParser.KLONGINT - 174)) | (1 << (SystemVerilogParser.KMACROMODULE - 174)) | (1 << (SystemVerilogParser.KMODULE - 174)) | (1 << (SystemVerilogParser.KNETTYPE - 174)) | (1 << (SystemVerilogParser.KPACKAGE - 174)) | (1 << (SystemVerilogParser.KPARAMETER - 174)))) != 0) or ((((_la - 239)) & ~0x3f) == 0 and ((1 << (_la - 239)) & ((1 << (SystemVerilogParser.KPROGRAM - 239)) | (1 << (SystemVerilogParser.KPROPERTY - 239)) | (1 << (SystemVerilogParser.KREAL - 239)) | (1 << (SystemVerilogParser.KREALTIME - 239)) | (1 << (SystemVerilogParser.KREG - 239)) | (1 << (SystemVerilogParser.KSEQUENCE - 239)) | (1 << (SystemVerilogParser.KSHORTINT - 239)) | (1 << (SystemVerilogParser.KSHORTREAL - 239)) | (1 << (SystemVerilogParser.KSIGNED - 239)) | (1 << (SystemVerilogParser.KSTATIC - 239)) | (1 << (SystemVerilogParser.KSTRING - 239)) | (1 << (SystemVerilogParser.KSTRUCT - 239)) | (1 << (SystemVerilogParser.KSUPPLY0 - 239)) | (1 << (SystemVerilogParser.KSUPPLY1 - 239)) | (1 << (SystemVerilogParser.KTASK - 239)) | (1 << (SystemVerilogParser.KTIME - 239)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 239)))) != 0) or ((((_la - 303)) & ~0x3f) == 0 and ((1 << (_la - 303)) & ((1 << (SystemVerilogParser.KTIMEUNIT - 303)) | (1 << (SystemVerilogParser.KTRI - 303)) | (1 << (SystemVerilogParser.KTRI0 - 303)) | (1 << (SystemVerilogParser.KTRI1 - 303)) | (1 << (SystemVerilogParser.KTRIAND - 303)) | (1 << (SystemVerilogParser.KTRIOR - 303)) | (1 << (SystemVerilogParser.KTRIREG - 303)) | (1 << (SystemVerilogParser.KTYPE - 303)) | (1 << (SystemVerilogParser.KTYPEDEF - 303)) | (1 << (SystemVerilogParser.KUNION - 303)) | (1 << (SystemVerilogParser.KUNSIGNED - 303)) | (1 << (SystemVerilogParser.KUWIRE - 303)) | (1 << (SystemVerilogParser.KVAR - 303)) | (1 << (SystemVerilogParser.KVIRTUAL - 303)) | (1 << (SystemVerilogParser.KWAND - 303)) | (1 << (SystemVerilogParser.KWIRE - 303)) | (1 << (SystemVerilogParser.KWOR - 303)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 303)))) != 0):
                self.state = 1288
                self.description()
                self.state = 1293
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1294
            self.match(SystemVerilogParser.EOF)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class DescriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_declarationContext,0)


        def interface_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_declarationContext,0)


        def program_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_declarationContext,0)


        def package_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_declarationContext,0)


        def package_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_itemContext,0)


        def bind_directive(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bind_directiveContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def config_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Config_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDescription" ):
                listener.enterDescription(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDescription" ):
                listener.exitDescription(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDescription" ):
                return visitor.visitDescription(self)
            else:
                return visitor.visitChildren(self)




    def description(self):

        localctx = SystemVerilogParser.DescriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 10, self.RULE_description)
        self._la = 0 # Token type
        try:
            self.state = 1311
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,9,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1296
                self.module_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1297
                self.interface_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1298
                self.program_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1299
                self.package_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1303
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 1300
                    self.attribute_instance()
                    self.state = 1305
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1308
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.SEMI, SystemVerilogParser.LB, SystemVerilogParser.KAUTOMATIC, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KCHECKER, SystemVerilogParser.KCLASS, SystemVerilogParser.KCONST, SystemVerilogParser.KCONSTRAINT, SystemVerilogParser.KCOVERGROUP, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KEXPORT, SystemVerilogParser.KFUNCTION, SystemVerilogParser.KIMPORT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KINTERCONNECT, SystemVerilogParser.KLET, SystemVerilogParser.KLOCALPARAM, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNETTYPE, SystemVerilogParser.KPARAMETER, SystemVerilogParser.KPROGRAM, SystemVerilogParser.KPROPERTY, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSEQUENCE, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTATIC, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KSUPPLY0, SystemVerilogParser.KSUPPLY1, SystemVerilogParser.KTASK, SystemVerilogParser.KTIME, SystemVerilogParser.KTIMEPRECISION, SystemVerilogParser.KTIMEUNIT, SystemVerilogParser.KTRI, SystemVerilogParser.KTRI0, SystemVerilogParser.KTRI1, SystemVerilogParser.KTRIAND, SystemVerilogParser.KTRIOR, SystemVerilogParser.KTRIREG, SystemVerilogParser.KTYPE, SystemVerilogParser.KTYPEDEF, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KUWIRE, SystemVerilogParser.KVAR, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.KWAND, SystemVerilogParser.KWIRE, SystemVerilogParser.KWOR, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                    self.state = 1306
                    self.package_item()
                    pass
                elif token in [SystemVerilogParser.KBIND]:
                    self.state = 1307
                    self.bind_directive()
                    pass
                else:
                    raise NoViableAltException(self)

                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1310
                self.config_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_nonansi_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_keyword(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_keywordContext,0)


        def module_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_identifierContext,0)


        def list_of_ports(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_portsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def package_import_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_import_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_import_declarationContext,i)


        def parameter_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_nonansi_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_nonansi_header" ):
                listener.enterModule_nonansi_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_nonansi_header" ):
                listener.exitModule_nonansi_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_nonansi_header" ):
                return visitor.visitModule_nonansi_header(self)
            else:
                return visitor.visitChildren(self)




    def module_nonansi_header(self):

        localctx = SystemVerilogParser.Module_nonansi_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 12, self.RULE_module_nonansi_header)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1316
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 1313
                self.attribute_instance()
                self.state = 1318
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1319
            self.module_keyword()
            self.state = 1321
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 1320
                self.lifetime()


            self.state = 1323
            self.module_identifier()
            self.state = 1327
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.KIMPORT:
                self.state = 1324
                self.package_import_declaration()
                self.state = 1329
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1331
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1330
                self.parameter_port_list()


            self.state = 1333
            self.list_of_ports()
            self.state = 1334
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_ansi_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_keyword(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_keywordContext,0)


        def module_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_identifierContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def package_import_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_import_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_import_declarationContext,i)


        def parameter_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_listContext,0)


        def list_of_port_declarations(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_port_declarationsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_ansi_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_ansi_header" ):
                listener.enterModule_ansi_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_ansi_header" ):
                listener.exitModule_ansi_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_ansi_header" ):
                return visitor.visitModule_ansi_header(self)
            else:
                return visitor.visitChildren(self)




    def module_ansi_header(self):

        localctx = SystemVerilogParser.Module_ansi_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 14, self.RULE_module_ansi_header)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1339
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 1336
                self.attribute_instance()
                self.state = 1341
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1342
            self.module_keyword()
            self.state = 1344
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 1343
                self.lifetime()


            self.state = 1346
            self.module_identifier()
            self.state = 1350
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.KIMPORT:
                self.state = 1347
                self.package_import_declaration()
                self.state = 1352
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1354
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1353
                self.parameter_port_list()


            self.state = 1357
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 1356
                self.list_of_port_declarations()


            self.state = 1359
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_nonansi_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_nonansi_headerContext,0)


        def KENDMODULE(self):
            return self.getToken(SystemVerilogParser.KENDMODULE, 0)

        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def module_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Module_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Module_itemContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def module_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Module_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Module_identifierContext,i)


        def module_ansi_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_ansi_headerContext,0)


        def non_port_module_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Non_port_module_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Non_port_module_itemContext,i)


        def module_keyword(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_keywordContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def DOTSTAR(self):
            return self.getToken(SystemVerilogParser.DOTSTAR, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def KEXTERN(self):
            return self.getToken(SystemVerilogParser.KEXTERN, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_declaration" ):
                listener.enterModule_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_declaration" ):
                listener.exitModule_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_declaration" ):
                return visitor.visitModule_declaration(self)
            else:
                return visitor.visitChildren(self)




    def module_declaration(self):

        localctx = SystemVerilogParser.Module_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 16, self.RULE_module_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1425
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,31,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1361
                self.module_nonansi_header()
                self.state = 1363
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,19,self._ctx)
                if la_ == 1:
                    self.state = 1362
                    self.timeunits_declaration()


                self.state = 1368
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 94)) & ~0x3f) == 0 and ((1 << (_la - 94)) & ((1 << (SystemVerilogParser.KALIAS - 94)) | (1 << (SystemVerilogParser.KALWAYS - 94)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 94)) | (1 << (SystemVerilogParser.KALWAYS_FF - 94)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 94)) | (1 << (SystemVerilogParser.KAND - 94)) | (1 << (SystemVerilogParser.KASSERT - 94)) | (1 << (SystemVerilogParser.KASSIGN - 94)) | (1 << (SystemVerilogParser.KASSUME - 94)) | (1 << (SystemVerilogParser.KAUTOMATIC - 94)) | (1 << (SystemVerilogParser.KBIND - 94)) | (1 << (SystemVerilogParser.KBIT - 94)) | (1 << (SystemVerilogParser.KBUF - 94)) | (1 << (SystemVerilogParser.KBUFIF0 - 94)) | (1 << (SystemVerilogParser.KBUFIF1 - 94)) | (1 << (SystemVerilogParser.KBYTE - 94)) | (1 << (SystemVerilogParser.KCASE - 94)) | (1 << (SystemVerilogParser.KCHANDLE - 94)) | (1 << (SystemVerilogParser.KCHECKER - 94)) | (1 << (SystemVerilogParser.KCLASS - 94)) | (1 << (SystemVerilogParser.KCLOCKING - 94)) | (1 << (SystemVerilogParser.KCMOS - 94)) | (1 << (SystemVerilogParser.KCONST - 94)) | (1 << (SystemVerilogParser.KCONSTRAINT - 94)) | (1 << (SystemVerilogParser.KCOVER - 94)) | (1 << (SystemVerilogParser.KCOVERGROUP - 94)) | (1 << (SystemVerilogParser.KDEFAULT - 94)) | (1 << (SystemVerilogParser.KDEFPARAM - 94)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KEXPORT - 159)) | (1 << (SystemVerilogParser.KEXTERN - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINOUT - 159)) | (1 << (SystemVerilogParser.KINPUT - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KINTERCONNECT - 159)) | (1 << (SystemVerilogParser.KINTERFACE - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOCALPARAM - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KMACROMODULE - 159)) | (1 << (SystemVerilogParser.KMODULE - 159)) | (1 << (SystemVerilogParser.KNAND - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)) | (1 << (SystemVerilogParser.KNMOS - 159)))) != 0) or ((((_la - 223)) & ~0x3f) == 0 and ((1 << (_la - 223)) & ((1 << (SystemVerilogParser.KNOR - 223)) | (1 << (SystemVerilogParser.KNOT - 223)) | (1 << (SystemVerilogParser.KNOTIF0 - 223)) | (1 << (SystemVerilogParser.KNOTIF1 - 223)) | (1 << (SystemVerilogParser.KOR - 223)) | (1 << (SystemVerilogParser.KOUTPUT - 223)) | (1 << (SystemVerilogParser.KPARAMETER - 223)) | (1 << (SystemVerilogParser.KPMOS - 223)) | (1 << (SystemVerilogParser.KPROGRAM - 223)) | (1 << (SystemVerilogParser.KPROPERTY - 223)) | (1 << (SystemVerilogParser.KPULLDOWN - 223)) | (1 << (SystemVerilogParser.KPULLUP - 223)) | (1 << (SystemVerilogParser.KRCMOS - 223)) | (1 << (SystemVerilogParser.KREAL - 223)) | (1 << (SystemVerilogParser.KREALTIME - 223)) | (1 << (SystemVerilogParser.KREF - 223)) | (1 << (SystemVerilogParser.KREG - 223)) | (1 << (SystemVerilogParser.KRESTRICT - 223)) | (1 << (SystemVerilogParser.KRNMOS - 223)) | (1 << (SystemVerilogParser.KRPMOS - 223)) | (1 << (SystemVerilogParser.KRTRAN - 223)) | (1 << (SystemVerilogParser.KRTRANIF0 - 223)) | (1 << (SystemVerilogParser.KRTRANIF1 - 223)) | (1 << (SystemVerilogParser.KSEQUENCE - 223)) | (1 << (SystemVerilogParser.KSHORTINT - 223)) | (1 << (SystemVerilogParser.KSHORTREAL - 223)) | (1 << (SystemVerilogParser.KSIGNED - 223)) | (1 << (SystemVerilogParser.KSPECIFY - 223)) | (1 << (SystemVerilogParser.KSPECPARAM - 223)) | (1 << (SystemVerilogParser.KSTATIC - 223)))) != 0) or ((((_la - 287)) & ~0x3f) == 0 and ((1 << (_la - 287)) & ((1 << (SystemVerilogParser.KSTRING - 287)) | (1 << (SystemVerilogParser.KSTRUCT - 287)) | (1 << (SystemVerilogParser.KSUPPLY0 - 287)) | (1 << (SystemVerilogParser.KSUPPLY1 - 287)) | (1 << (SystemVerilogParser.KTASK - 287)) | (1 << (SystemVerilogParser.KTIME - 287)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 287)) | (1 << (SystemVerilogParser.KTIMEUNIT - 287)) | (1 << (SystemVerilogParser.KTRAN - 287)) | (1 << (SystemVerilogParser.KTRANIF0 - 287)) | (1 << (SystemVerilogParser.KTRANIF1 - 287)) | (1 << (SystemVerilogParser.KTRI - 287)) | (1 << (SystemVerilogParser.KTRI0 - 287)) | (1 << (SystemVerilogParser.KTRI1 - 287)) | (1 << (SystemVerilogParser.KTRIAND - 287)) | (1 << (SystemVerilogParser.KTRIOR - 287)) | (1 << (SystemVerilogParser.KTRIREG - 287)) | (1 << (SystemVerilogParser.KTYPE - 287)) | (1 << (SystemVerilogParser.KTYPEDEF - 287)) | (1 << (SystemVerilogParser.KUNION - 287)) | (1 << (SystemVerilogParser.KUNSIGNED - 287)) | (1 << (SystemVerilogParser.KUWIRE - 287)) | (1 << (SystemVerilogParser.KVAR - 287)) | (1 << (SystemVerilogParser.KVIRTUAL - 287)) | (1 << (SystemVerilogParser.KWAND - 287)) | (1 << (SystemVerilogParser.KWIRE - 287)) | (1 << (SystemVerilogParser.KWOR - 287)) | (1 << (SystemVerilogParser.KXNOR - 287)) | (1 << (SystemVerilogParser.KXOR - 287)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 1365
                    self.module_item()
                    self.state = 1370
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1371
                self.match(SystemVerilogParser.KENDMODULE)
                self.state = 1374
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1372
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1373
                    self.module_identifier()


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1376
                self.module_ansi_header()
                self.state = 1378
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,22,self._ctx)
                if la_ == 1:
                    self.state = 1377
                    self.timeunits_declaration()


                self.state = 1383
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 94)) & ~0x3f) == 0 and ((1 << (_la - 94)) & ((1 << (SystemVerilogParser.KALIAS - 94)) | (1 << (SystemVerilogParser.KALWAYS - 94)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 94)) | (1 << (SystemVerilogParser.KALWAYS_FF - 94)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 94)) | (1 << (SystemVerilogParser.KAND - 94)) | (1 << (SystemVerilogParser.KASSERT - 94)) | (1 << (SystemVerilogParser.KASSIGN - 94)) | (1 << (SystemVerilogParser.KASSUME - 94)) | (1 << (SystemVerilogParser.KAUTOMATIC - 94)) | (1 << (SystemVerilogParser.KBIND - 94)) | (1 << (SystemVerilogParser.KBIT - 94)) | (1 << (SystemVerilogParser.KBUF - 94)) | (1 << (SystemVerilogParser.KBUFIF0 - 94)) | (1 << (SystemVerilogParser.KBUFIF1 - 94)) | (1 << (SystemVerilogParser.KBYTE - 94)) | (1 << (SystemVerilogParser.KCASE - 94)) | (1 << (SystemVerilogParser.KCHANDLE - 94)) | (1 << (SystemVerilogParser.KCHECKER - 94)) | (1 << (SystemVerilogParser.KCLASS - 94)) | (1 << (SystemVerilogParser.KCLOCKING - 94)) | (1 << (SystemVerilogParser.KCMOS - 94)) | (1 << (SystemVerilogParser.KCONST - 94)) | (1 << (SystemVerilogParser.KCONSTRAINT - 94)) | (1 << (SystemVerilogParser.KCOVER - 94)) | (1 << (SystemVerilogParser.KCOVERGROUP - 94)) | (1 << (SystemVerilogParser.KDEFAULT - 94)) | (1 << (SystemVerilogParser.KDEFPARAM - 94)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KEXPORT - 159)) | (1 << (SystemVerilogParser.KEXTERN - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KINTERCONNECT - 159)) | (1 << (SystemVerilogParser.KINTERFACE - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOCALPARAM - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KMACROMODULE - 159)) | (1 << (SystemVerilogParser.KMODULE - 159)) | (1 << (SystemVerilogParser.KNAND - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)) | (1 << (SystemVerilogParser.KNMOS - 159)))) != 0) or ((((_la - 223)) & ~0x3f) == 0 and ((1 << (_la - 223)) & ((1 << (SystemVerilogParser.KNOR - 223)) | (1 << (SystemVerilogParser.KNOT - 223)) | (1 << (SystemVerilogParser.KNOTIF0 - 223)) | (1 << (SystemVerilogParser.KNOTIF1 - 223)) | (1 << (SystemVerilogParser.KOR - 223)) | (1 << (SystemVerilogParser.KPARAMETER - 223)) | (1 << (SystemVerilogParser.KPMOS - 223)) | (1 << (SystemVerilogParser.KPROGRAM - 223)) | (1 << (SystemVerilogParser.KPROPERTY - 223)) | (1 << (SystemVerilogParser.KPULLDOWN - 223)) | (1 << (SystemVerilogParser.KPULLUP - 223)) | (1 << (SystemVerilogParser.KRCMOS - 223)) | (1 << (SystemVerilogParser.KREAL - 223)) | (1 << (SystemVerilogParser.KREALTIME - 223)) | (1 << (SystemVerilogParser.KREG - 223)) | (1 << (SystemVerilogParser.KRESTRICT - 223)) | (1 << (SystemVerilogParser.KRNMOS - 223)) | (1 << (SystemVerilogParser.KRPMOS - 223)) | (1 << (SystemVerilogParser.KRTRAN - 223)) | (1 << (SystemVerilogParser.KRTRANIF0 - 223)) | (1 << (SystemVerilogParser.KRTRANIF1 - 223)) | (1 << (SystemVerilogParser.KSEQUENCE - 223)) | (1 << (SystemVerilogParser.KSHORTINT - 223)) | (1 << (SystemVerilogParser.KSHORTREAL - 223)) | (1 << (SystemVerilogParser.KSIGNED - 223)) | (1 << (SystemVerilogParser.KSPECIFY - 223)) | (1 << (SystemVerilogParser.KSPECPARAM - 223)) | (1 << (SystemVerilogParser.KSTATIC - 223)))) != 0) or ((((_la - 287)) & ~0x3f) == 0 and ((1 << (_la - 287)) & ((1 << (SystemVerilogParser.KSTRING - 287)) | (1 << (SystemVerilogParser.KSTRUCT - 287)) | (1 << (SystemVerilogParser.KSUPPLY0 - 287)) | (1 << (SystemVerilogParser.KSUPPLY1 - 287)) | (1 << (SystemVerilogParser.KTASK - 287)) | (1 << (SystemVerilogParser.KTIME - 287)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 287)) | (1 << (SystemVerilogParser.KTIMEUNIT - 287)) | (1 << (SystemVerilogParser.KTRAN - 287)) | (1 << (SystemVerilogParser.KTRANIF0 - 287)) | (1 << (SystemVerilogParser.KTRANIF1 - 287)) | (1 << (SystemVerilogParser.KTRI - 287)) | (1 << (SystemVerilogParser.KTRI0 - 287)) | (1 << (SystemVerilogParser.KTRI1 - 287)) | (1 << (SystemVerilogParser.KTRIAND - 287)) | (1 << (SystemVerilogParser.KTRIOR - 287)) | (1 << (SystemVerilogParser.KTRIREG - 287)) | (1 << (SystemVerilogParser.KTYPE - 287)) | (1 << (SystemVerilogParser.KTYPEDEF - 287)) | (1 << (SystemVerilogParser.KUNION - 287)) | (1 << (SystemVerilogParser.KUNSIGNED - 287)) | (1 << (SystemVerilogParser.KUWIRE - 287)) | (1 << (SystemVerilogParser.KVAR - 287)) | (1 << (SystemVerilogParser.KVIRTUAL - 287)) | (1 << (SystemVerilogParser.KWAND - 287)) | (1 << (SystemVerilogParser.KWIRE - 287)) | (1 << (SystemVerilogParser.KWOR - 287)) | (1 << (SystemVerilogParser.KXNOR - 287)) | (1 << (SystemVerilogParser.KXOR - 287)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 1380
                    self.non_port_module_item()
                    self.state = 1385
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1386
                self.match(SystemVerilogParser.KENDMODULE)
                self.state = 1389
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1387
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1388
                    self.module_identifier()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1394
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 1391
                    self.attribute_instance()
                    self.state = 1396
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1397
                self.module_keyword()
                self.state = 1399
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                    self.state = 1398
                    self.lifetime()


                self.state = 1401
                self.module_identifier()
                self.state = 1402
                self.match(SystemVerilogParser.LP)
                self.state = 1403
                self.match(SystemVerilogParser.DOTSTAR)
                self.state = 1404
                self.match(SystemVerilogParser.RP)
                self.state = 1405
                self.match(SystemVerilogParser.SEMI)
                self.state = 1407
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,27,self._ctx)
                if la_ == 1:
                    self.state = 1406
                    self.timeunits_declaration()


                self.state = 1412
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 94)) & ~0x3f) == 0 and ((1 << (_la - 94)) & ((1 << (SystemVerilogParser.KALIAS - 94)) | (1 << (SystemVerilogParser.KALWAYS - 94)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 94)) | (1 << (SystemVerilogParser.KALWAYS_FF - 94)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 94)) | (1 << (SystemVerilogParser.KAND - 94)) | (1 << (SystemVerilogParser.KASSERT - 94)) | (1 << (SystemVerilogParser.KASSIGN - 94)) | (1 << (SystemVerilogParser.KASSUME - 94)) | (1 << (SystemVerilogParser.KAUTOMATIC - 94)) | (1 << (SystemVerilogParser.KBIND - 94)) | (1 << (SystemVerilogParser.KBIT - 94)) | (1 << (SystemVerilogParser.KBUF - 94)) | (1 << (SystemVerilogParser.KBUFIF0 - 94)) | (1 << (SystemVerilogParser.KBUFIF1 - 94)) | (1 << (SystemVerilogParser.KBYTE - 94)) | (1 << (SystemVerilogParser.KCASE - 94)) | (1 << (SystemVerilogParser.KCHANDLE - 94)) | (1 << (SystemVerilogParser.KCHECKER - 94)) | (1 << (SystemVerilogParser.KCLASS - 94)) | (1 << (SystemVerilogParser.KCLOCKING - 94)) | (1 << (SystemVerilogParser.KCMOS - 94)) | (1 << (SystemVerilogParser.KCONST - 94)) | (1 << (SystemVerilogParser.KCONSTRAINT - 94)) | (1 << (SystemVerilogParser.KCOVER - 94)) | (1 << (SystemVerilogParser.KCOVERGROUP - 94)) | (1 << (SystemVerilogParser.KDEFAULT - 94)) | (1 << (SystemVerilogParser.KDEFPARAM - 94)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KEXPORT - 159)) | (1 << (SystemVerilogParser.KEXTERN - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINOUT - 159)) | (1 << (SystemVerilogParser.KINPUT - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KINTERCONNECT - 159)) | (1 << (SystemVerilogParser.KINTERFACE - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOCALPARAM - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KMACROMODULE - 159)) | (1 << (SystemVerilogParser.KMODULE - 159)) | (1 << (SystemVerilogParser.KNAND - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)) | (1 << (SystemVerilogParser.KNMOS - 159)))) != 0) or ((((_la - 223)) & ~0x3f) == 0 and ((1 << (_la - 223)) & ((1 << (SystemVerilogParser.KNOR - 223)) | (1 << (SystemVerilogParser.KNOT - 223)) | (1 << (SystemVerilogParser.KNOTIF0 - 223)) | (1 << (SystemVerilogParser.KNOTIF1 - 223)) | (1 << (SystemVerilogParser.KOR - 223)) | (1 << (SystemVerilogParser.KOUTPUT - 223)) | (1 << (SystemVerilogParser.KPARAMETER - 223)) | (1 << (SystemVerilogParser.KPMOS - 223)) | (1 << (SystemVerilogParser.KPROGRAM - 223)) | (1 << (SystemVerilogParser.KPROPERTY - 223)) | (1 << (SystemVerilogParser.KPULLDOWN - 223)) | (1 << (SystemVerilogParser.KPULLUP - 223)) | (1 << (SystemVerilogParser.KRCMOS - 223)) | (1 << (SystemVerilogParser.KREAL - 223)) | (1 << (SystemVerilogParser.KREALTIME - 223)) | (1 << (SystemVerilogParser.KREF - 223)) | (1 << (SystemVerilogParser.KREG - 223)) | (1 << (SystemVerilogParser.KRESTRICT - 223)) | (1 << (SystemVerilogParser.KRNMOS - 223)) | (1 << (SystemVerilogParser.KRPMOS - 223)) | (1 << (SystemVerilogParser.KRTRAN - 223)) | (1 << (SystemVerilogParser.KRTRANIF0 - 223)) | (1 << (SystemVerilogParser.KRTRANIF1 - 223)) | (1 << (SystemVerilogParser.KSEQUENCE - 223)) | (1 << (SystemVerilogParser.KSHORTINT - 223)) | (1 << (SystemVerilogParser.KSHORTREAL - 223)) | (1 << (SystemVerilogParser.KSIGNED - 223)) | (1 << (SystemVerilogParser.KSPECIFY - 223)) | (1 << (SystemVerilogParser.KSPECPARAM - 223)) | (1 << (SystemVerilogParser.KSTATIC - 223)))) != 0) or ((((_la - 287)) & ~0x3f) == 0 and ((1 << (_la - 287)) & ((1 << (SystemVerilogParser.KSTRING - 287)) | (1 << (SystemVerilogParser.KSTRUCT - 287)) | (1 << (SystemVerilogParser.KSUPPLY0 - 287)) | (1 << (SystemVerilogParser.KSUPPLY1 - 287)) | (1 << (SystemVerilogParser.KTASK - 287)) | (1 << (SystemVerilogParser.KTIME - 287)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 287)) | (1 << (SystemVerilogParser.KTIMEUNIT - 287)) | (1 << (SystemVerilogParser.KTRAN - 287)) | (1 << (SystemVerilogParser.KTRANIF0 - 287)) | (1 << (SystemVerilogParser.KTRANIF1 - 287)) | (1 << (SystemVerilogParser.KTRI - 287)) | (1 << (SystemVerilogParser.KTRI0 - 287)) | (1 << (SystemVerilogParser.KTRI1 - 287)) | (1 << (SystemVerilogParser.KTRIAND - 287)) | (1 << (SystemVerilogParser.KTRIOR - 287)) | (1 << (SystemVerilogParser.KTRIREG - 287)) | (1 << (SystemVerilogParser.KTYPE - 287)) | (1 << (SystemVerilogParser.KTYPEDEF - 287)) | (1 << (SystemVerilogParser.KUNION - 287)) | (1 << (SystemVerilogParser.KUNSIGNED - 287)) | (1 << (SystemVerilogParser.KUWIRE - 287)) | (1 << (SystemVerilogParser.KVAR - 287)) | (1 << (SystemVerilogParser.KVIRTUAL - 287)) | (1 << (SystemVerilogParser.KWAND - 287)) | (1 << (SystemVerilogParser.KWIRE - 287)) | (1 << (SystemVerilogParser.KWOR - 287)) | (1 << (SystemVerilogParser.KXNOR - 287)) | (1 << (SystemVerilogParser.KXOR - 287)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 1409
                    self.module_item()
                    self.state = 1414
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1415
                self.match(SystemVerilogParser.KENDMODULE)
                self.state = 1418
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1416
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1417
                    self.module_identifier()


                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1420
                self.match(SystemVerilogParser.KEXTERN)
                self.state = 1423
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,30,self._ctx)
                if la_ == 1:
                    self.state = 1421
                    self.module_nonansi_header()
                    pass

                elif la_ == 2:
                    self.state = 1422
                    self.module_ansi_header()
                    pass


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_keywordContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KMODULE(self):
            return self.getToken(SystemVerilogParser.KMODULE, 0)

        def KMACROMODULE(self):
            return self.getToken(SystemVerilogParser.KMACROMODULE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_keyword" ):
                listener.enterModule_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_keyword" ):
                listener.exitModule_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_keyword" ):
                return visitor.visitModule_keyword(self)
            else:
                return visitor.visitChildren(self)




    def module_keyword(self):

        localctx = SystemVerilogParser.Module_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 18, self.RULE_module_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1427
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KMACROMODULE or _la==SystemVerilogParser.KMODULE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def interface_nonansi_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_nonansi_headerContext,0)


        def KENDINTERFACE(self):
            return self.getToken(SystemVerilogParser.KENDINTERFACE, 0)

        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def interface_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Interface_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Interface_itemContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def interface_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Interface_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,i)


        def interface_ansi_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_ansi_headerContext,0)


        def non_port_interface_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Non_port_interface_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Non_port_interface_itemContext,i)


        def KINTERFACE(self):
            return self.getToken(SystemVerilogParser.KINTERFACE, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def DOTSTAR(self):
            return self.getToken(SystemVerilogParser.DOTSTAR, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def KEXTERN(self):
            return self.getToken(SystemVerilogParser.KEXTERN, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_declaration" ):
                listener.enterInterface_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_declaration" ):
                listener.exitInterface_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_declaration" ):
                return visitor.visitInterface_declaration(self)
            else:
                return visitor.visitChildren(self)




    def interface_declaration(self):

        localctx = SystemVerilogParser.Interface_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 20, self.RULE_interface_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1490
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,43,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1429
                self.interface_nonansi_header()
                self.state = 1431
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,32,self._ctx)
                if la_ == 1:
                    self.state = 1430
                    self.timeunits_declaration()


                self.state = 1436
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 94)) & ~0x3f) == 0 and ((1 << (_la - 94)) & ((1 << (SystemVerilogParser.KALIAS - 94)) | (1 << (SystemVerilogParser.KALWAYS - 94)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 94)) | (1 << (SystemVerilogParser.KALWAYS_FF - 94)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 94)) | (1 << (SystemVerilogParser.KASSERT - 94)) | (1 << (SystemVerilogParser.KASSIGN - 94)) | (1 << (SystemVerilogParser.KASSUME - 94)) | (1 << (SystemVerilogParser.KAUTOMATIC - 94)) | (1 << (SystemVerilogParser.KBIND - 94)) | (1 << (SystemVerilogParser.KBIT - 94)) | (1 << (SystemVerilogParser.KBYTE - 94)) | (1 << (SystemVerilogParser.KCASE - 94)) | (1 << (SystemVerilogParser.KCHANDLE - 94)) | (1 << (SystemVerilogParser.KCHECKER - 94)) | (1 << (SystemVerilogParser.KCLASS - 94)) | (1 << (SystemVerilogParser.KCLOCKING - 94)) | (1 << (SystemVerilogParser.KCONST - 94)) | (1 << (SystemVerilogParser.KCONSTRAINT - 94)) | (1 << (SystemVerilogParser.KCOVER - 94)) | (1 << (SystemVerilogParser.KCOVERGROUP - 94)) | (1 << (SystemVerilogParser.KDEFAULT - 94)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KEXPORT - 159)) | (1 << (SystemVerilogParser.KEXTERN - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINOUT - 159)) | (1 << (SystemVerilogParser.KINPUT - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KINTERCONNECT - 159)) | (1 << (SystemVerilogParser.KINTERFACE - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOCALPARAM - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KMODPORT - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)))) != 0) or ((((_la - 231)) & ~0x3f) == 0 and ((1 << (_la - 231)) & ((1 << (SystemVerilogParser.KOUTPUT - 231)) | (1 << (SystemVerilogParser.KPARAMETER - 231)) | (1 << (SystemVerilogParser.KPROGRAM - 231)) | (1 << (SystemVerilogParser.KPROPERTY - 231)) | (1 << (SystemVerilogParser.KREAL - 231)) | (1 << (SystemVerilogParser.KREALTIME - 231)) | (1 << (SystemVerilogParser.KREF - 231)) | (1 << (SystemVerilogParser.KREG - 231)) | (1 << (SystemVerilogParser.KRESTRICT - 231)) | (1 << (SystemVerilogParser.KSEQUENCE - 231)) | (1 << (SystemVerilogParser.KSHORTINT - 231)) | (1 << (SystemVerilogParser.KSHORTREAL - 231)) | (1 << (SystemVerilogParser.KSIGNED - 231)) | (1 << (SystemVerilogParser.KSTATIC - 231)) | (1 << (SystemVerilogParser.KSTRING - 231)) | (1 << (SystemVerilogParser.KSTRUCT - 231)) | (1 << (SystemVerilogParser.KSUPPLY0 - 231)) | (1 << (SystemVerilogParser.KSUPPLY1 - 231)))) != 0) or ((((_la - 298)) & ~0x3f) == 0 and ((1 << (_la - 298)) & ((1 << (SystemVerilogParser.KTASK - 298)) | (1 << (SystemVerilogParser.KTIME - 298)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 298)) | (1 << (SystemVerilogParser.KTIMEUNIT - 298)) | (1 << (SystemVerilogParser.KTRI - 298)) | (1 << (SystemVerilogParser.KTRI0 - 298)) | (1 << (SystemVerilogParser.KTRI1 - 298)) | (1 << (SystemVerilogParser.KTRIAND - 298)) | (1 << (SystemVerilogParser.KTRIOR - 298)) | (1 << (SystemVerilogParser.KTRIREG - 298)) | (1 << (SystemVerilogParser.KTYPE - 298)) | (1 << (SystemVerilogParser.KTYPEDEF - 298)) | (1 << (SystemVerilogParser.KUNION - 298)) | (1 << (SystemVerilogParser.KUNSIGNED - 298)) | (1 << (SystemVerilogParser.KUWIRE - 298)) | (1 << (SystemVerilogParser.KVAR - 298)) | (1 << (SystemVerilogParser.KVIRTUAL - 298)) | (1 << (SystemVerilogParser.KWAND - 298)) | (1 << (SystemVerilogParser.KWIRE - 298)) | (1 << (SystemVerilogParser.KWOR - 298)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 298)))) != 0):
                    self.state = 1433
                    self.interface_item()
                    self.state = 1438
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1439
                self.match(SystemVerilogParser.KENDINTERFACE)
                self.state = 1442
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1440
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1441
                    self.interface_identifier()


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1444
                self.interface_ansi_header()
                self.state = 1446
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,35,self._ctx)
                if la_ == 1:
                    self.state = 1445
                    self.timeunits_declaration()


                self.state = 1451
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 94)) & ~0x3f) == 0 and ((1 << (_la - 94)) & ((1 << (SystemVerilogParser.KALIAS - 94)) | (1 << (SystemVerilogParser.KALWAYS - 94)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 94)) | (1 << (SystemVerilogParser.KALWAYS_FF - 94)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 94)) | (1 << (SystemVerilogParser.KASSERT - 94)) | (1 << (SystemVerilogParser.KASSIGN - 94)) | (1 << (SystemVerilogParser.KASSUME - 94)) | (1 << (SystemVerilogParser.KAUTOMATIC - 94)) | (1 << (SystemVerilogParser.KBIND - 94)) | (1 << (SystemVerilogParser.KBIT - 94)) | (1 << (SystemVerilogParser.KBYTE - 94)) | (1 << (SystemVerilogParser.KCASE - 94)) | (1 << (SystemVerilogParser.KCHANDLE - 94)) | (1 << (SystemVerilogParser.KCHECKER - 94)) | (1 << (SystemVerilogParser.KCLASS - 94)) | (1 << (SystemVerilogParser.KCLOCKING - 94)) | (1 << (SystemVerilogParser.KCONST - 94)) | (1 << (SystemVerilogParser.KCONSTRAINT - 94)) | (1 << (SystemVerilogParser.KCOVER - 94)) | (1 << (SystemVerilogParser.KCOVERGROUP - 94)) | (1 << (SystemVerilogParser.KDEFAULT - 94)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KEXPORT - 159)) | (1 << (SystemVerilogParser.KEXTERN - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KINTERCONNECT - 159)) | (1 << (SystemVerilogParser.KINTERFACE - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOCALPARAM - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KMODPORT - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)))) != 0) or ((((_la - 234)) & ~0x3f) == 0 and ((1 << (_la - 234)) & ((1 << (SystemVerilogParser.KPARAMETER - 234)) | (1 << (SystemVerilogParser.KPROGRAM - 234)) | (1 << (SystemVerilogParser.KPROPERTY - 234)) | (1 << (SystemVerilogParser.KREAL - 234)) | (1 << (SystemVerilogParser.KREALTIME - 234)) | (1 << (SystemVerilogParser.KREG - 234)) | (1 << (SystemVerilogParser.KRESTRICT - 234)) | (1 << (SystemVerilogParser.KSEQUENCE - 234)) | (1 << (SystemVerilogParser.KSHORTINT - 234)) | (1 << (SystemVerilogParser.KSHORTREAL - 234)) | (1 << (SystemVerilogParser.KSIGNED - 234)) | (1 << (SystemVerilogParser.KSTATIC - 234)) | (1 << (SystemVerilogParser.KSTRING - 234)) | (1 << (SystemVerilogParser.KSTRUCT - 234)) | (1 << (SystemVerilogParser.KSUPPLY0 - 234)) | (1 << (SystemVerilogParser.KSUPPLY1 - 234)))) != 0) or ((((_la - 298)) & ~0x3f) == 0 and ((1 << (_la - 298)) & ((1 << (SystemVerilogParser.KTASK - 298)) | (1 << (SystemVerilogParser.KTIME - 298)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 298)) | (1 << (SystemVerilogParser.KTIMEUNIT - 298)) | (1 << (SystemVerilogParser.KTRI - 298)) | (1 << (SystemVerilogParser.KTRI0 - 298)) | (1 << (SystemVerilogParser.KTRI1 - 298)) | (1 << (SystemVerilogParser.KTRIAND - 298)) | (1 << (SystemVerilogParser.KTRIOR - 298)) | (1 << (SystemVerilogParser.KTRIREG - 298)) | (1 << (SystemVerilogParser.KTYPE - 298)) | (1 << (SystemVerilogParser.KTYPEDEF - 298)) | (1 << (SystemVerilogParser.KUNION - 298)) | (1 << (SystemVerilogParser.KUNSIGNED - 298)) | (1 << (SystemVerilogParser.KUWIRE - 298)) | (1 << (SystemVerilogParser.KVAR - 298)) | (1 << (SystemVerilogParser.KVIRTUAL - 298)) | (1 << (SystemVerilogParser.KWAND - 298)) | (1 << (SystemVerilogParser.KWIRE - 298)) | (1 << (SystemVerilogParser.KWOR - 298)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 298)))) != 0):
                    self.state = 1448
                    self.non_port_interface_item()
                    self.state = 1453
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1454
                self.match(SystemVerilogParser.KENDINTERFACE)
                self.state = 1457
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1455
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1456
                    self.interface_identifier()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1462
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 1459
                    self.attribute_instance()
                    self.state = 1464
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1465
                self.match(SystemVerilogParser.KINTERFACE)
                self.state = 1466
                self.interface_identifier()
                self.state = 1467
                self.match(SystemVerilogParser.LP)
                self.state = 1468
                self.match(SystemVerilogParser.DOTSTAR)
                self.state = 1469
                self.match(SystemVerilogParser.RP)
                self.state = 1470
                self.match(SystemVerilogParser.SEMI)
                self.state = 1472
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,39,self._ctx)
                if la_ == 1:
                    self.state = 1471
                    self.timeunits_declaration()


                self.state = 1477
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 94)) & ~0x3f) == 0 and ((1 << (_la - 94)) & ((1 << (SystemVerilogParser.KALIAS - 94)) | (1 << (SystemVerilogParser.KALWAYS - 94)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 94)) | (1 << (SystemVerilogParser.KALWAYS_FF - 94)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 94)) | (1 << (SystemVerilogParser.KASSERT - 94)) | (1 << (SystemVerilogParser.KASSIGN - 94)) | (1 << (SystemVerilogParser.KASSUME - 94)) | (1 << (SystemVerilogParser.KAUTOMATIC - 94)) | (1 << (SystemVerilogParser.KBIND - 94)) | (1 << (SystemVerilogParser.KBIT - 94)) | (1 << (SystemVerilogParser.KBYTE - 94)) | (1 << (SystemVerilogParser.KCASE - 94)) | (1 << (SystemVerilogParser.KCHANDLE - 94)) | (1 << (SystemVerilogParser.KCHECKER - 94)) | (1 << (SystemVerilogParser.KCLASS - 94)) | (1 << (SystemVerilogParser.KCLOCKING - 94)) | (1 << (SystemVerilogParser.KCONST - 94)) | (1 << (SystemVerilogParser.KCONSTRAINT - 94)) | (1 << (SystemVerilogParser.KCOVER - 94)) | (1 << (SystemVerilogParser.KCOVERGROUP - 94)) | (1 << (SystemVerilogParser.KDEFAULT - 94)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KEXPORT - 159)) | (1 << (SystemVerilogParser.KEXTERN - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINOUT - 159)) | (1 << (SystemVerilogParser.KINPUT - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KINTERCONNECT - 159)) | (1 << (SystemVerilogParser.KINTERFACE - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOCALPARAM - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KMODPORT - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)))) != 0) or ((((_la - 231)) & ~0x3f) == 0 and ((1 << (_la - 231)) & ((1 << (SystemVerilogParser.KOUTPUT - 231)) | (1 << (SystemVerilogParser.KPARAMETER - 231)) | (1 << (SystemVerilogParser.KPROGRAM - 231)) | (1 << (SystemVerilogParser.KPROPERTY - 231)) | (1 << (SystemVerilogParser.KREAL - 231)) | (1 << (SystemVerilogParser.KREALTIME - 231)) | (1 << (SystemVerilogParser.KREF - 231)) | (1 << (SystemVerilogParser.KREG - 231)) | (1 << (SystemVerilogParser.KRESTRICT - 231)) | (1 << (SystemVerilogParser.KSEQUENCE - 231)) | (1 << (SystemVerilogParser.KSHORTINT - 231)) | (1 << (SystemVerilogParser.KSHORTREAL - 231)) | (1 << (SystemVerilogParser.KSIGNED - 231)) | (1 << (SystemVerilogParser.KSTATIC - 231)) | (1 << (SystemVerilogParser.KSTRING - 231)) | (1 << (SystemVerilogParser.KSTRUCT - 231)) | (1 << (SystemVerilogParser.KSUPPLY0 - 231)) | (1 << (SystemVerilogParser.KSUPPLY1 - 231)))) != 0) or ((((_la - 298)) & ~0x3f) == 0 and ((1 << (_la - 298)) & ((1 << (SystemVerilogParser.KTASK - 298)) | (1 << (SystemVerilogParser.KTIME - 298)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 298)) | (1 << (SystemVerilogParser.KTIMEUNIT - 298)) | (1 << (SystemVerilogParser.KTRI - 298)) | (1 << (SystemVerilogParser.KTRI0 - 298)) | (1 << (SystemVerilogParser.KTRI1 - 298)) | (1 << (SystemVerilogParser.KTRIAND - 298)) | (1 << (SystemVerilogParser.KTRIOR - 298)) | (1 << (SystemVerilogParser.KTRIREG - 298)) | (1 << (SystemVerilogParser.KTYPE - 298)) | (1 << (SystemVerilogParser.KTYPEDEF - 298)) | (1 << (SystemVerilogParser.KUNION - 298)) | (1 << (SystemVerilogParser.KUNSIGNED - 298)) | (1 << (SystemVerilogParser.KUWIRE - 298)) | (1 << (SystemVerilogParser.KVAR - 298)) | (1 << (SystemVerilogParser.KVIRTUAL - 298)) | (1 << (SystemVerilogParser.KWAND - 298)) | (1 << (SystemVerilogParser.KWIRE - 298)) | (1 << (SystemVerilogParser.KWOR - 298)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 298)))) != 0):
                    self.state = 1474
                    self.interface_item()
                    self.state = 1479
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1480
                self.match(SystemVerilogParser.KENDINTERFACE)
                self.state = 1483
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1481
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1482
                    self.interface_identifier()


                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1485
                self.match(SystemVerilogParser.KEXTERN)
                self.state = 1488
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,42,self._ctx)
                if la_ == 1:
                    self.state = 1486
                    self.interface_nonansi_header()
                    pass

                elif la_ == 2:
                    self.state = 1487
                    self.interface_ansi_header()
                    pass


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_nonansi_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINTERFACE(self):
            return self.getToken(SystemVerilogParser.KINTERFACE, 0)

        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def list_of_ports(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_portsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def package_import_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_import_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_import_declarationContext,i)


        def parameter_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_nonansi_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_nonansi_header" ):
                listener.enterInterface_nonansi_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_nonansi_header" ):
                listener.exitInterface_nonansi_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_nonansi_header" ):
                return visitor.visitInterface_nonansi_header(self)
            else:
                return visitor.visitChildren(self)




    def interface_nonansi_header(self):

        localctx = SystemVerilogParser.Interface_nonansi_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 22, self.RULE_interface_nonansi_header)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1495
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 1492
                self.attribute_instance()
                self.state = 1497
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1498
            self.match(SystemVerilogParser.KINTERFACE)
            self.state = 1500
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 1499
                self.lifetime()


            self.state = 1502
            self.interface_identifier()
            self.state = 1506
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.KIMPORT:
                self.state = 1503
                self.package_import_declaration()
                self.state = 1508
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1510
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1509
                self.parameter_port_list()


            self.state = 1512
            self.list_of_ports()
            self.state = 1513
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_ansi_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINTERFACE(self):
            return self.getToken(SystemVerilogParser.KINTERFACE, 0)

        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def package_import_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_import_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_import_declarationContext,i)


        def parameter_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_listContext,0)


        def list_of_port_declarations(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_port_declarationsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_ansi_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_ansi_header" ):
                listener.enterInterface_ansi_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_ansi_header" ):
                listener.exitInterface_ansi_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_ansi_header" ):
                return visitor.visitInterface_ansi_header(self)
            else:
                return visitor.visitChildren(self)




    def interface_ansi_header(self):

        localctx = SystemVerilogParser.Interface_ansi_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 24, self.RULE_interface_ansi_header)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1518
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 1515
                self.attribute_instance()
                self.state = 1520
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1521
            self.match(SystemVerilogParser.KINTERFACE)
            self.state = 1523
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 1522
                self.lifetime()


            self.state = 1525
            self.interface_identifier()
            self.state = 1529
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.KIMPORT:
                self.state = 1526
                self.package_import_declaration()
                self.state = 1531
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1533
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1532
                self.parameter_port_list()


            self.state = 1536
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 1535
                self.list_of_port_declarations()


            self.state = 1538
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Program_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def program_nonansi_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_nonansi_headerContext,0)


        def KENDPROGRAM(self):
            return self.getToken(SystemVerilogParser.KENDPROGRAM, 0)

        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def program_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Program_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Program_itemContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def program_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Program_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Program_identifierContext,i)


        def program_ansi_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_ansi_headerContext,0)


        def non_port_program_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Non_port_program_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Non_port_program_itemContext,i)


        def KPROGRAM(self):
            return self.getToken(SystemVerilogParser.KPROGRAM, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def DOTSTAR(self):
            return self.getToken(SystemVerilogParser.DOTSTAR, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def KEXTERN(self):
            return self.getToken(SystemVerilogParser.KEXTERN, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_program_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProgram_declaration" ):
                listener.enterProgram_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProgram_declaration" ):
                listener.exitProgram_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProgram_declaration" ):
                return visitor.visitProgram_declaration(self)
            else:
                return visitor.visitChildren(self)




    def program_declaration(self):

        localctx = SystemVerilogParser.Program_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 26, self.RULE_program_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1601
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,64,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1540
                self.program_nonansi_header()
                self.state = 1542
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,53,self._ctx)
                if la_ == 1:
                    self.state = 1541
                    self.timeunits_declaration()


                self.state = 1547
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 100)) & ~0x3f) == 0 and ((1 << (_la - 100)) & ((1 << (SystemVerilogParser.KASSERT - 100)) | (1 << (SystemVerilogParser.KASSIGN - 100)) | (1 << (SystemVerilogParser.KASSUME - 100)) | (1 << (SystemVerilogParser.KAUTOMATIC - 100)) | (1 << (SystemVerilogParser.KBIT - 100)) | (1 << (SystemVerilogParser.KBYTE - 100)) | (1 << (SystemVerilogParser.KCASE - 100)) | (1 << (SystemVerilogParser.KCHANDLE - 100)) | (1 << (SystemVerilogParser.KCHECKER - 100)) | (1 << (SystemVerilogParser.KCLASS - 100)) | (1 << (SystemVerilogParser.KCLOCKING - 100)) | (1 << (SystemVerilogParser.KCONST - 100)) | (1 << (SystemVerilogParser.KCONSTRAINT - 100)) | (1 << (SystemVerilogParser.KCOVER - 100)) | (1 << (SystemVerilogParser.KCOVERGROUP - 100)) | (1 << (SystemVerilogParser.KDEFAULT - 100)) | (1 << (SystemVerilogParser.KENUM - 100)) | (1 << (SystemVerilogParser.KEVENT - 100)) | (1 << (SystemVerilogParser.KEXPORT - 100)))) != 0) or ((((_la - 166)) & ~0x3f) == 0 and ((1 << (_la - 166)) & ((1 << (SystemVerilogParser.KFINAL - 166)) | (1 << (SystemVerilogParser.KFOR - 166)) | (1 << (SystemVerilogParser.KFUNCTION - 166)) | (1 << (SystemVerilogParser.KGENERATE - 166)) | (1 << (SystemVerilogParser.KGENVAR - 166)) | (1 << (SystemVerilogParser.KGLOBAL - 166)) | (1 << (SystemVerilogParser.KIF - 166)) | (1 << (SystemVerilogParser.KIMPORT - 166)) | (1 << (SystemVerilogParser.KINITIAL - 166)) | (1 << (SystemVerilogParser.KINOUT - 166)) | (1 << (SystemVerilogParser.KINPUT - 166)) | (1 << (SystemVerilogParser.KINT - 166)) | (1 << (SystemVerilogParser.KINTEGER - 166)) | (1 << (SystemVerilogParser.KINTERCONNECT - 166)) | (1 << (SystemVerilogParser.KLET - 166)) | (1 << (SystemVerilogParser.KLOCALPARAM - 166)) | (1 << (SystemVerilogParser.KLOGIC - 166)) | (1 << (SystemVerilogParser.KLONGINT - 166)) | (1 << (SystemVerilogParser.KNETTYPE - 166)))) != 0) or ((((_la - 231)) & ~0x3f) == 0 and ((1 << (_la - 231)) & ((1 << (SystemVerilogParser.KOUTPUT - 231)) | (1 << (SystemVerilogParser.KPARAMETER - 231)) | (1 << (SystemVerilogParser.KPROPERTY - 231)) | (1 << (SystemVerilogParser.KREAL - 231)) | (1 << (SystemVerilogParser.KREALTIME - 231)) | (1 << (SystemVerilogParser.KREF - 231)) | (1 << (SystemVerilogParser.KREG - 231)) | (1 << (SystemVerilogParser.KRESTRICT - 231)) | (1 << (SystemVerilogParser.KSEQUENCE - 231)) | (1 << (SystemVerilogParser.KSHORTINT - 231)) | (1 << (SystemVerilogParser.KSHORTREAL - 231)) | (1 << (SystemVerilogParser.KSIGNED - 231)) | (1 << (SystemVerilogParser.KSTATIC - 231)) | (1 << (SystemVerilogParser.KSTRING - 231)) | (1 << (SystemVerilogParser.KSTRUCT - 231)) | (1 << (SystemVerilogParser.KSUPPLY0 - 231)) | (1 << (SystemVerilogParser.KSUPPLY1 - 231)))) != 0) or ((((_la - 298)) & ~0x3f) == 0 and ((1 << (_la - 298)) & ((1 << (SystemVerilogParser.KTASK - 298)) | (1 << (SystemVerilogParser.KTIME - 298)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 298)) | (1 << (SystemVerilogParser.KTIMEUNIT - 298)) | (1 << (SystemVerilogParser.KTRI - 298)) | (1 << (SystemVerilogParser.KTRI0 - 298)) | (1 << (SystemVerilogParser.KTRI1 - 298)) | (1 << (SystemVerilogParser.KTRIAND - 298)) | (1 << (SystemVerilogParser.KTRIOR - 298)) | (1 << (SystemVerilogParser.KTRIREG - 298)) | (1 << (SystemVerilogParser.KTYPE - 298)) | (1 << (SystemVerilogParser.KTYPEDEF - 298)) | (1 << (SystemVerilogParser.KUNION - 298)) | (1 << (SystemVerilogParser.KUNSIGNED - 298)) | (1 << (SystemVerilogParser.KUWIRE - 298)) | (1 << (SystemVerilogParser.KVAR - 298)) | (1 << (SystemVerilogParser.KVIRTUAL - 298)) | (1 << (SystemVerilogParser.KWAND - 298)) | (1 << (SystemVerilogParser.KWIRE - 298)) | (1 << (SystemVerilogParser.KWOR - 298)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 298)))) != 0):
                    self.state = 1544
                    self.program_item()
                    self.state = 1549
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1550
                self.match(SystemVerilogParser.KENDPROGRAM)
                self.state = 1553
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1551
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1552
                    self.program_identifier()


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1555
                self.program_ansi_header()
                self.state = 1557
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,56,self._ctx)
                if la_ == 1:
                    self.state = 1556
                    self.timeunits_declaration()


                self.state = 1562
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 100)) & ~0x3f) == 0 and ((1 << (_la - 100)) & ((1 << (SystemVerilogParser.KASSERT - 100)) | (1 << (SystemVerilogParser.KASSIGN - 100)) | (1 << (SystemVerilogParser.KASSUME - 100)) | (1 << (SystemVerilogParser.KAUTOMATIC - 100)) | (1 << (SystemVerilogParser.KBIT - 100)) | (1 << (SystemVerilogParser.KBYTE - 100)) | (1 << (SystemVerilogParser.KCASE - 100)) | (1 << (SystemVerilogParser.KCHANDLE - 100)) | (1 << (SystemVerilogParser.KCHECKER - 100)) | (1 << (SystemVerilogParser.KCLASS - 100)) | (1 << (SystemVerilogParser.KCLOCKING - 100)) | (1 << (SystemVerilogParser.KCONST - 100)) | (1 << (SystemVerilogParser.KCONSTRAINT - 100)) | (1 << (SystemVerilogParser.KCOVER - 100)) | (1 << (SystemVerilogParser.KCOVERGROUP - 100)) | (1 << (SystemVerilogParser.KDEFAULT - 100)) | (1 << (SystemVerilogParser.KENUM - 100)) | (1 << (SystemVerilogParser.KEVENT - 100)) | (1 << (SystemVerilogParser.KEXPORT - 100)))) != 0) or ((((_la - 166)) & ~0x3f) == 0 and ((1 << (_la - 166)) & ((1 << (SystemVerilogParser.KFINAL - 166)) | (1 << (SystemVerilogParser.KFOR - 166)) | (1 << (SystemVerilogParser.KFUNCTION - 166)) | (1 << (SystemVerilogParser.KGENERATE - 166)) | (1 << (SystemVerilogParser.KGENVAR - 166)) | (1 << (SystemVerilogParser.KGLOBAL - 166)) | (1 << (SystemVerilogParser.KIF - 166)) | (1 << (SystemVerilogParser.KIMPORT - 166)) | (1 << (SystemVerilogParser.KINITIAL - 166)) | (1 << (SystemVerilogParser.KINT - 166)) | (1 << (SystemVerilogParser.KINTEGER - 166)) | (1 << (SystemVerilogParser.KINTERCONNECT - 166)) | (1 << (SystemVerilogParser.KLET - 166)) | (1 << (SystemVerilogParser.KLOCALPARAM - 166)) | (1 << (SystemVerilogParser.KLOGIC - 166)) | (1 << (SystemVerilogParser.KLONGINT - 166)) | (1 << (SystemVerilogParser.KNETTYPE - 166)))) != 0) or ((((_la - 234)) & ~0x3f) == 0 and ((1 << (_la - 234)) & ((1 << (SystemVerilogParser.KPARAMETER - 234)) | (1 << (SystemVerilogParser.KPROPERTY - 234)) | (1 << (SystemVerilogParser.KREAL - 234)) | (1 << (SystemVerilogParser.KREALTIME - 234)) | (1 << (SystemVerilogParser.KREG - 234)) | (1 << (SystemVerilogParser.KRESTRICT - 234)) | (1 << (SystemVerilogParser.KSEQUENCE - 234)) | (1 << (SystemVerilogParser.KSHORTINT - 234)) | (1 << (SystemVerilogParser.KSHORTREAL - 234)) | (1 << (SystemVerilogParser.KSIGNED - 234)) | (1 << (SystemVerilogParser.KSTATIC - 234)) | (1 << (SystemVerilogParser.KSTRING - 234)) | (1 << (SystemVerilogParser.KSTRUCT - 234)) | (1 << (SystemVerilogParser.KSUPPLY0 - 234)) | (1 << (SystemVerilogParser.KSUPPLY1 - 234)))) != 0) or ((((_la - 298)) & ~0x3f) == 0 and ((1 << (_la - 298)) & ((1 << (SystemVerilogParser.KTASK - 298)) | (1 << (SystemVerilogParser.KTIME - 298)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 298)) | (1 << (SystemVerilogParser.KTIMEUNIT - 298)) | (1 << (SystemVerilogParser.KTRI - 298)) | (1 << (SystemVerilogParser.KTRI0 - 298)) | (1 << (SystemVerilogParser.KTRI1 - 298)) | (1 << (SystemVerilogParser.KTRIAND - 298)) | (1 << (SystemVerilogParser.KTRIOR - 298)) | (1 << (SystemVerilogParser.KTRIREG - 298)) | (1 << (SystemVerilogParser.KTYPE - 298)) | (1 << (SystemVerilogParser.KTYPEDEF - 298)) | (1 << (SystemVerilogParser.KUNION - 298)) | (1 << (SystemVerilogParser.KUNSIGNED - 298)) | (1 << (SystemVerilogParser.KUWIRE - 298)) | (1 << (SystemVerilogParser.KVAR - 298)) | (1 << (SystemVerilogParser.KVIRTUAL - 298)) | (1 << (SystemVerilogParser.KWAND - 298)) | (1 << (SystemVerilogParser.KWIRE - 298)) | (1 << (SystemVerilogParser.KWOR - 298)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 298)))) != 0):
                    self.state = 1559
                    self.non_port_program_item()
                    self.state = 1564
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1565
                self.match(SystemVerilogParser.KENDPROGRAM)
                self.state = 1568
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1566
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1567
                    self.program_identifier()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1573
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 1570
                    self.attribute_instance()
                    self.state = 1575
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1576
                self.match(SystemVerilogParser.KPROGRAM)
                self.state = 1577
                self.program_identifier()
                self.state = 1578
                self.match(SystemVerilogParser.LP)
                self.state = 1579
                self.match(SystemVerilogParser.DOTSTAR)
                self.state = 1580
                self.match(SystemVerilogParser.RP)
                self.state = 1581
                self.match(SystemVerilogParser.SEMI)
                self.state = 1583
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,60,self._ctx)
                if la_ == 1:
                    self.state = 1582
                    self.timeunits_declaration()


                self.state = 1588
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 100)) & ~0x3f) == 0 and ((1 << (_la - 100)) & ((1 << (SystemVerilogParser.KASSERT - 100)) | (1 << (SystemVerilogParser.KASSIGN - 100)) | (1 << (SystemVerilogParser.KASSUME - 100)) | (1 << (SystemVerilogParser.KAUTOMATIC - 100)) | (1 << (SystemVerilogParser.KBIT - 100)) | (1 << (SystemVerilogParser.KBYTE - 100)) | (1 << (SystemVerilogParser.KCASE - 100)) | (1 << (SystemVerilogParser.KCHANDLE - 100)) | (1 << (SystemVerilogParser.KCHECKER - 100)) | (1 << (SystemVerilogParser.KCLASS - 100)) | (1 << (SystemVerilogParser.KCLOCKING - 100)) | (1 << (SystemVerilogParser.KCONST - 100)) | (1 << (SystemVerilogParser.KCONSTRAINT - 100)) | (1 << (SystemVerilogParser.KCOVER - 100)) | (1 << (SystemVerilogParser.KCOVERGROUP - 100)) | (1 << (SystemVerilogParser.KDEFAULT - 100)) | (1 << (SystemVerilogParser.KENUM - 100)) | (1 << (SystemVerilogParser.KEVENT - 100)) | (1 << (SystemVerilogParser.KEXPORT - 100)))) != 0) or ((((_la - 166)) & ~0x3f) == 0 and ((1 << (_la - 166)) & ((1 << (SystemVerilogParser.KFINAL - 166)) | (1 << (SystemVerilogParser.KFOR - 166)) | (1 << (SystemVerilogParser.KFUNCTION - 166)) | (1 << (SystemVerilogParser.KGENERATE - 166)) | (1 << (SystemVerilogParser.KGENVAR - 166)) | (1 << (SystemVerilogParser.KGLOBAL - 166)) | (1 << (SystemVerilogParser.KIF - 166)) | (1 << (SystemVerilogParser.KIMPORT - 166)) | (1 << (SystemVerilogParser.KINITIAL - 166)) | (1 << (SystemVerilogParser.KINOUT - 166)) | (1 << (SystemVerilogParser.KINPUT - 166)) | (1 << (SystemVerilogParser.KINT - 166)) | (1 << (SystemVerilogParser.KINTEGER - 166)) | (1 << (SystemVerilogParser.KINTERCONNECT - 166)) | (1 << (SystemVerilogParser.KLET - 166)) | (1 << (SystemVerilogParser.KLOCALPARAM - 166)) | (1 << (SystemVerilogParser.KLOGIC - 166)) | (1 << (SystemVerilogParser.KLONGINT - 166)) | (1 << (SystemVerilogParser.KNETTYPE - 166)))) != 0) or ((((_la - 231)) & ~0x3f) == 0 and ((1 << (_la - 231)) & ((1 << (SystemVerilogParser.KOUTPUT - 231)) | (1 << (SystemVerilogParser.KPARAMETER - 231)) | (1 << (SystemVerilogParser.KPROPERTY - 231)) | (1 << (SystemVerilogParser.KREAL - 231)) | (1 << (SystemVerilogParser.KREALTIME - 231)) | (1 << (SystemVerilogParser.KREF - 231)) | (1 << (SystemVerilogParser.KREG - 231)) | (1 << (SystemVerilogParser.KRESTRICT - 231)) | (1 << (SystemVerilogParser.KSEQUENCE - 231)) | (1 << (SystemVerilogParser.KSHORTINT - 231)) | (1 << (SystemVerilogParser.KSHORTREAL - 231)) | (1 << (SystemVerilogParser.KSIGNED - 231)) | (1 << (SystemVerilogParser.KSTATIC - 231)) | (1 << (SystemVerilogParser.KSTRING - 231)) | (1 << (SystemVerilogParser.KSTRUCT - 231)) | (1 << (SystemVerilogParser.KSUPPLY0 - 231)) | (1 << (SystemVerilogParser.KSUPPLY1 - 231)))) != 0) or ((((_la - 298)) & ~0x3f) == 0 and ((1 << (_la - 298)) & ((1 << (SystemVerilogParser.KTASK - 298)) | (1 << (SystemVerilogParser.KTIME - 298)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 298)) | (1 << (SystemVerilogParser.KTIMEUNIT - 298)) | (1 << (SystemVerilogParser.KTRI - 298)) | (1 << (SystemVerilogParser.KTRI0 - 298)) | (1 << (SystemVerilogParser.KTRI1 - 298)) | (1 << (SystemVerilogParser.KTRIAND - 298)) | (1 << (SystemVerilogParser.KTRIOR - 298)) | (1 << (SystemVerilogParser.KTRIREG - 298)) | (1 << (SystemVerilogParser.KTYPE - 298)) | (1 << (SystemVerilogParser.KTYPEDEF - 298)) | (1 << (SystemVerilogParser.KUNION - 298)) | (1 << (SystemVerilogParser.KUNSIGNED - 298)) | (1 << (SystemVerilogParser.KUWIRE - 298)) | (1 << (SystemVerilogParser.KVAR - 298)) | (1 << (SystemVerilogParser.KVIRTUAL - 298)) | (1 << (SystemVerilogParser.KWAND - 298)) | (1 << (SystemVerilogParser.KWIRE - 298)) | (1 << (SystemVerilogParser.KWOR - 298)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 298)))) != 0):
                    self.state = 1585
                    self.program_item()
                    self.state = 1590
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1591
                self.match(SystemVerilogParser.KENDPROGRAM)
                self.state = 1594
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 1592
                    self.match(SystemVerilogParser.COLON)
                    self.state = 1593
                    self.program_identifier()


                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1596
                self.match(SystemVerilogParser.KEXTERN)
                self.state = 1599
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,63,self._ctx)
                if la_ == 1:
                    self.state = 1597
                    self.program_nonansi_header()
                    pass

                elif la_ == 2:
                    self.state = 1598
                    self.program_ansi_header()
                    pass


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Program_nonansi_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPROGRAM(self):
            return self.getToken(SystemVerilogParser.KPROGRAM, 0)

        def program_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_identifierContext,0)


        def list_of_ports(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_portsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def package_import_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_import_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_import_declarationContext,i)


        def parameter_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_program_nonansi_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProgram_nonansi_header" ):
                listener.enterProgram_nonansi_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProgram_nonansi_header" ):
                listener.exitProgram_nonansi_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProgram_nonansi_header" ):
                return visitor.visitProgram_nonansi_header(self)
            else:
                return visitor.visitChildren(self)




    def program_nonansi_header(self):

        localctx = SystemVerilogParser.Program_nonansi_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 28, self.RULE_program_nonansi_header)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1606
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 1603
                self.attribute_instance()
                self.state = 1608
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1609
            self.match(SystemVerilogParser.KPROGRAM)
            self.state = 1611
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 1610
                self.lifetime()


            self.state = 1613
            self.program_identifier()
            self.state = 1617
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.KIMPORT:
                self.state = 1614
                self.package_import_declaration()
                self.state = 1619
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1621
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1620
                self.parameter_port_list()


            self.state = 1623
            self.list_of_ports()
            self.state = 1624
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Program_ansi_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPROGRAM(self):
            return self.getToken(SystemVerilogParser.KPROGRAM, 0)

        def program_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_identifierContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def package_import_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_import_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_import_declarationContext,i)


        def parameter_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_listContext,0)


        def list_of_port_declarations(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_port_declarationsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_program_ansi_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProgram_ansi_header" ):
                listener.enterProgram_ansi_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProgram_ansi_header" ):
                listener.exitProgram_ansi_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProgram_ansi_header" ):
                return visitor.visitProgram_ansi_header(self)
            else:
                return visitor.visitChildren(self)




    def program_ansi_header(self):

        localctx = SystemVerilogParser.Program_ansi_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 30, self.RULE_program_ansi_header)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1629
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 1626
                self.attribute_instance()
                self.state = 1631
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1632
            self.match(SystemVerilogParser.KPROGRAM)
            self.state = 1634
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 1633
                self.lifetime()


            self.state = 1636
            self.program_identifier()
            self.state = 1640
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.KIMPORT:
                self.state = 1637
                self.package_import_declaration()
                self.state = 1642
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1644
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1643
                self.parameter_port_list()


            self.state = 1647
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 1646
                self.list_of_port_declarations()


            self.state = 1649
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCHECKER(self):
            return self.getToken(SystemVerilogParser.KCHECKER, 0)

        def checker_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Checker_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Checker_identifierContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KENDCHECKER(self):
            return self.getToken(SystemVerilogParser.KENDCHECKER, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def checker_or_generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Checker_or_generate_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Checker_or_generate_itemContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def checker_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_port_listContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_declaration" ):
                listener.enterChecker_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_declaration" ):
                listener.exitChecker_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_declaration" ):
                return visitor.visitChecker_declaration(self)
            else:
                return visitor.visitChildren(self)




    def checker_declaration(self):

        localctx = SystemVerilogParser.Checker_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 32, self.RULE_checker_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1651
            self.match(SystemVerilogParser.KCHECKER)
            self.state = 1652
            self.checker_identifier()
            self.state = 1658
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 1653
                self.match(SystemVerilogParser.LP)
                self.state = 1655
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 192)) & ~0x3f) == 0 and ((1 << (_la - 192)) & ((1 << (SystemVerilogParser.KINPUT - 192)) | (1 << (SystemVerilogParser.KINT - 192)) | (1 << (SystemVerilogParser.KINTEGER - 192)) | (1 << (SystemVerilogParser.KLOGIC - 192)) | (1 << (SystemVerilogParser.KLONGINT - 192)) | (1 << (SystemVerilogParser.KOUTPUT - 192)) | (1 << (SystemVerilogParser.KPROPERTY - 192)) | (1 << (SystemVerilogParser.KREAL - 192)))) != 0) or ((((_la - 256)) & ~0x3f) == 0 and ((1 << (_la - 256)) & ((1 << (SystemVerilogParser.KREALTIME - 256)) | (1 << (SystemVerilogParser.KREG - 256)) | (1 << (SystemVerilogParser.KSEQUENCE - 256)) | (1 << (SystemVerilogParser.KSHORTINT - 256)) | (1 << (SystemVerilogParser.KSHORTREAL - 256)) | (1 << (SystemVerilogParser.KSIGNED - 256)) | (1 << (SystemVerilogParser.KSTRING - 256)) | (1 << (SystemVerilogParser.KSTRUCT - 256)) | (1 << (SystemVerilogParser.KTIME - 256)) | (1 << (SystemVerilogParser.KTYPE - 256)) | (1 << (SystemVerilogParser.KUNION - 256)) | (1 << (SystemVerilogParser.KUNSIGNED - 256)))) != 0) or ((((_la - 322)) & ~0x3f) == 0 and ((1 << (_la - 322)) & ((1 << (SystemVerilogParser.KUNTYPED - 322)) | (1 << (SystemVerilogParser.KVIRTUAL - 322)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 322)))) != 0):
                    self.state = 1654
                    self.checker_port_list()


                self.state = 1657
                self.match(SystemVerilogParser.RP)


            self.state = 1660
            self.match(SystemVerilogParser.SEMI)
            self.state = 1670
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 95)) & ~0x3f) == 0 and ((1 << (_la - 95)) & ((1 << (SystemVerilogParser.KALWAYS - 95)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 95)) | (1 << (SystemVerilogParser.KALWAYS_FF - 95)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 95)) | (1 << (SystemVerilogParser.KASSERT - 95)) | (1 << (SystemVerilogParser.KASSIGN - 95)) | (1 << (SystemVerilogParser.KASSUME - 95)) | (1 << (SystemVerilogParser.KAUTOMATIC - 95)) | (1 << (SystemVerilogParser.KBIT - 95)) | (1 << (SystemVerilogParser.KBYTE - 95)) | (1 << (SystemVerilogParser.KCASE - 95)) | (1 << (SystemVerilogParser.KCHANDLE - 95)) | (1 << (SystemVerilogParser.KCHECKER - 95)) | (1 << (SystemVerilogParser.KCLOCKING - 95)) | (1 << (SystemVerilogParser.KCONST - 95)) | (1 << (SystemVerilogParser.KCOVER - 95)) | (1 << (SystemVerilogParser.KCOVERGROUP - 95)) | (1 << (SystemVerilogParser.KDEFAULT - 95)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)))) != 0) or ((((_la - 240)) & ~0x3f) == 0 and ((1 << (_la - 240)) & ((1 << (SystemVerilogParser.KPROPERTY - 240)) | (1 << (SystemVerilogParser.KRAND - 240)) | (1 << (SystemVerilogParser.KREAL - 240)) | (1 << (SystemVerilogParser.KREALTIME - 240)) | (1 << (SystemVerilogParser.KREG - 240)) | (1 << (SystemVerilogParser.KRESTRICT - 240)) | (1 << (SystemVerilogParser.KSEQUENCE - 240)) | (1 << (SystemVerilogParser.KSHORTINT - 240)) | (1 << (SystemVerilogParser.KSHORTREAL - 240)) | (1 << (SystemVerilogParser.KSIGNED - 240)) | (1 << (SystemVerilogParser.KSTATIC - 240)) | (1 << (SystemVerilogParser.KSTRING - 240)) | (1 << (SystemVerilogParser.KSTRUCT - 240)) | (1 << (SystemVerilogParser.KTIME - 240)))) != 0) or ((((_la - 313)) & ~0x3f) == 0 and ((1 << (_la - 313)) & ((1 << (SystemVerilogParser.KTYPE - 313)) | (1 << (SystemVerilogParser.KTYPEDEF - 313)) | (1 << (SystemVerilogParser.KUNION - 313)) | (1 << (SystemVerilogParser.KUNSIGNED - 313)) | (1 << (SystemVerilogParser.KVAR - 313)) | (1 << (SystemVerilogParser.KVIRTUAL - 313)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 313)))) != 0):
                self.state = 1664
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 1661
                    self.attribute_instance()
                    self.state = 1666
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1667
                self.checker_or_generate_item()
                self.state = 1672
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1673
            self.match(SystemVerilogParser.KENDCHECKER)
            self.state = 1676
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 1674
                self.match(SystemVerilogParser.COLON)
                self.state = 1675
                self.checker_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCLASS(self):
            return self.getToken(SystemVerilogParser.KCLASS, 0)

        def class_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Class_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Class_identifierContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KENDCLASS(self):
            return self.getToken(SystemVerilogParser.KENDCLASS, 0)

        def KVIRTUAL(self):
            return self.getToken(SystemVerilogParser.KVIRTUAL, 0)

        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def parameter_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_listContext,0)


        def KEXTENDS(self):
            return self.getToken(SystemVerilogParser.KEXTENDS, 0)

        def class_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_typeContext,0)


        def KIMPLEMENTS(self):
            return self.getToken(SystemVerilogParser.KIMPLEMENTS, 0)

        def interface_class_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Interface_class_typeContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Interface_class_typeContext,i)


        def class_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Class_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Class_itemContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_declaration" ):
                listener.enterClass_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_declaration" ):
                listener.exitClass_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_declaration" ):
                return visitor.visitClass_declaration(self)
            else:
                return visitor.visitChildren(self)




    def class_declaration(self):

        localctx = SystemVerilogParser.Class_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 34, self.RULE_class_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1679
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KVIRTUAL:
                self.state = 1678
                self.match(SystemVerilogParser.KVIRTUAL)


            self.state = 1681
            self.match(SystemVerilogParser.KCLASS)
            self.state = 1683
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 1682
                self.lifetime()


            self.state = 1685
            self.class_identifier()
            self.state = 1687
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1686
                self.parameter_port_list()


            self.state = 1697
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KEXTENDS:
                self.state = 1689
                self.match(SystemVerilogParser.KEXTENDS)
                self.state = 1690
                self.class_type()
                self.state = 1695
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 1691
                    self.match(SystemVerilogParser.LP)
                    self.state = 1692
                    self.list_of_arguments()
                    self.state = 1693
                    self.match(SystemVerilogParser.RP)




            self.state = 1708
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KIMPLEMENTS:
                self.state = 1699
                self.match(SystemVerilogParser.KIMPLEMENTS)
                self.state = 1700
                self.interface_class_type()
                self.state = 1705
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 1701
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 1702
                    self.interface_class_type()
                    self.state = 1707
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



            self.state = 1710
            self.match(SystemVerilogParser.SEMI)
            self.state = 1714
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 103)) & ~0x3f) == 0 and ((1 << (_la - 103)) & ((1 << (SystemVerilogParser.KAUTOMATIC - 103)) | (1 << (SystemVerilogParser.KBIT - 103)) | (1 << (SystemVerilogParser.KBYTE - 103)) | (1 << (SystemVerilogParser.KCHANDLE - 103)) | (1 << (SystemVerilogParser.KCLASS - 103)) | (1 << (SystemVerilogParser.KCONST - 103)) | (1 << (SystemVerilogParser.KCONSTRAINT - 103)) | (1 << (SystemVerilogParser.KCOVERGROUP - 103)) | (1 << (SystemVerilogParser.KENUM - 103)) | (1 << (SystemVerilogParser.KEVENT - 103)) | (1 << (SystemVerilogParser.KEXTERN - 103)))) != 0) or ((((_la - 174)) & ~0x3f) == 0 and ((1 << (_la - 174)) & ((1 << (SystemVerilogParser.KFUNCTION - 174)) | (1 << (SystemVerilogParser.KIMPORT - 174)) | (1 << (SystemVerilogParser.KINT - 174)) | (1 << (SystemVerilogParser.KINTEGER - 174)) | (1 << (SystemVerilogParser.KLOCAL - 174)) | (1 << (SystemVerilogParser.KLOCALPARAM - 174)) | (1 << (SystemVerilogParser.KLOGIC - 174)) | (1 << (SystemVerilogParser.KLONGINT - 174)) | (1 << (SystemVerilogParser.KNETTYPE - 174)) | (1 << (SystemVerilogParser.KPARAMETER - 174)))) != 0) or ((((_la - 241)) & ~0x3f) == 0 and ((1 << (_la - 241)) & ((1 << (SystemVerilogParser.KPROTECTED - 241)) | (1 << (SystemVerilogParser.KPURE - 241)) | (1 << (SystemVerilogParser.KRAND - 241)) | (1 << (SystemVerilogParser.KRANDC - 241)) | (1 << (SystemVerilogParser.KREAL - 241)) | (1 << (SystemVerilogParser.KREALTIME - 241)) | (1 << (SystemVerilogParser.KREG - 241)) | (1 << (SystemVerilogParser.KSHORTINT - 241)) | (1 << (SystemVerilogParser.KSHORTREAL - 241)) | (1 << (SystemVerilogParser.KSIGNED - 241)) | (1 << (SystemVerilogParser.KSTATIC - 241)) | (1 << (SystemVerilogParser.KSTRING - 241)) | (1 << (SystemVerilogParser.KSTRUCT - 241)) | (1 << (SystemVerilogParser.KTASK - 241)) | (1 << (SystemVerilogParser.KTIME - 241)))) != 0) or ((((_la - 313)) & ~0x3f) == 0 and ((1 << (_la - 313)) & ((1 << (SystemVerilogParser.KTYPE - 313)) | (1 << (SystemVerilogParser.KTYPEDEF - 313)) | (1 << (SystemVerilogParser.KUNION - 313)) | (1 << (SystemVerilogParser.KUNSIGNED - 313)) | (1 << (SystemVerilogParser.KVAR - 313)) | (1 << (SystemVerilogParser.KVIRTUAL - 313)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 313)))) != 0):
                self.state = 1711
                self.class_item()
                self.state = 1716
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1717
            self.match(SystemVerilogParser.KENDCLASS)
            self.state = 1720
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 1718
                self.match(SystemVerilogParser.COLON)
                self.state = 1719
                self.class_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_class_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ps_class_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_class_identifierContext,0)


        def parameter_value_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_value_assignmentContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_class_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_class_type" ):
                listener.enterInterface_class_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_class_type" ):
                listener.exitInterface_class_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_class_type" ):
                return visitor.visitInterface_class_type(self)
            else:
                return visitor.visitChildren(self)




    def interface_class_type(self):

        localctx = SystemVerilogParser.Interface_class_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 36, self.RULE_interface_class_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1722
            self.ps_class_identifier()
            self.state = 1724
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1723
                self.parameter_value_assignment()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_class_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINTERFACE(self):
            return self.getToken(SystemVerilogParser.KINTERFACE, 0)

        def KCLASS(self):
            return self.getToken(SystemVerilogParser.KCLASS, 0)

        def class_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Class_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Class_identifierContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KENDCLASS(self):
            return self.getToken(SystemVerilogParser.KENDCLASS, 0)

        def parameter_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_listContext,0)


        def KEXTENDS(self):
            return self.getToken(SystemVerilogParser.KEXTENDS, 0)

        def interface_class_type(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Interface_class_typeContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Interface_class_typeContext,i)


        def interface_class_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Interface_class_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Interface_class_itemContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_class_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_class_declaration" ):
                listener.enterInterface_class_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_class_declaration" ):
                listener.exitInterface_class_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_class_declaration" ):
                return visitor.visitInterface_class_declaration(self)
            else:
                return visitor.visitChildren(self)




    def interface_class_declaration(self):

        localctx = SystemVerilogParser.Interface_class_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 38, self.RULE_interface_class_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1726
            self.match(SystemVerilogParser.KINTERFACE)
            self.state = 1727
            self.match(SystemVerilogParser.KCLASS)
            self.state = 1728
            self.class_identifier()
            self.state = 1730
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 1729
                self.parameter_port_list()


            self.state = 1741
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KEXTENDS:
                self.state = 1732
                self.match(SystemVerilogParser.KEXTENDS)
                self.state = 1733
                self.interface_class_type()
                self.state = 1738
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 1734
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 1735
                    self.interface_class_type()
                    self.state = 1740
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



            self.state = 1743
            self.match(SystemVerilogParser.SEMI)
            self.state = 1747
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS or _la==SystemVerilogParser.SEMI or ((((_la - 208)) & ~0x3f) == 0 and ((1 << (_la - 208)) & ((1 << (SystemVerilogParser.KLOCALPARAM - 208)) | (1 << (SystemVerilogParser.KPARAMETER - 208)) | (1 << (SystemVerilogParser.KPURE - 208)))) != 0) or _la==SystemVerilogParser.KTYPEDEF:
                self.state = 1744
                self.interface_class_item()
                self.state = 1749
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1750
            self.match(SystemVerilogParser.KENDCLASS)
            self.state = 1753
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 1751
                self.match(SystemVerilogParser.COLON)
                self.state = 1752
                self.class_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_class_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def type_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_declarationContext,0)


        def interface_class_method(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_class_methodContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def local_parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Local_parameter_declarationContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_class_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_class_item" ):
                listener.enterInterface_class_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_class_item" ):
                listener.exitInterface_class_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_class_item" ):
                return visitor.visitInterface_class_item(self)
            else:
                return visitor.visitChildren(self)




    def interface_class_item(self):

        localctx = SystemVerilogParser.Interface_class_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 40, self.RULE_interface_class_item)
        self._la = 0 # Token type
        try:
            self.state = 1768
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KTYPEDEF]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1755
                self.type_declaration()
                pass
            elif token in [SystemVerilogParser.LPS, SystemVerilogParser.KPURE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1759
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 1756
                    self.attribute_instance()
                    self.state = 1761
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1762
                self.interface_class_method()
                pass
            elif token in [SystemVerilogParser.SEMI, SystemVerilogParser.KLOCALPARAM, SystemVerilogParser.KPARAMETER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1765
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KLOCALPARAM]:
                    self.state = 1763
                    self.local_parameter_declaration()
                    pass
                elif token in [SystemVerilogParser.KPARAMETER]:
                    self.state = 1764
                    self.parameter_declaration()
                    pass
                elif token in [SystemVerilogParser.SEMI]:
                    pass
                else:
                    pass
                self.state = 1767
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_class_methodContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPURE(self):
            return self.getToken(SystemVerilogParser.KPURE, 0)

        def KVIRTUAL(self):
            return self.getToken(SystemVerilogParser.KVIRTUAL, 0)

        def method_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_prototypeContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_class_method

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_class_method" ):
                listener.enterInterface_class_method(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_class_method" ):
                listener.exitInterface_class_method(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_class_method" ):
                return visitor.visitInterface_class_method(self)
            else:
                return visitor.visitChildren(self)




    def interface_class_method(self):

        localctx = SystemVerilogParser.Interface_class_methodContext(self, self._ctx, self.state)
        self.enterRule(localctx, 42, self.RULE_interface_class_method)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1770
            self.match(SystemVerilogParser.KPURE)
            self.state = 1771
            self.match(SystemVerilogParser.KVIRTUAL)
            self.state = 1772
            self.method_prototype()
            self.state = 1773
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPACKAGE(self):
            return self.getToken(SystemVerilogParser.KPACKAGE, 0)

        def package_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_identifierContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KENDPACKAGE(self):
            return self.getToken(SystemVerilogParser.KENDPACKAGE, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def package_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_itemContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_package_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_declaration" ):
                listener.enterPackage_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_declaration" ):
                listener.exitPackage_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_declaration" ):
                return visitor.visitPackage_declaration(self)
            else:
                return visitor.visitChildren(self)




    def package_declaration(self):

        localctx = SystemVerilogParser.Package_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 44, self.RULE_package_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1778
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 1775
                self.attribute_instance()
                self.state = 1780
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1781
            self.match(SystemVerilogParser.KPACKAGE)
            self.state = 1783
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 1782
                self.lifetime()


            self.state = 1785
            self.package_identifier()
            self.state = 1786
            self.match(SystemVerilogParser.SEMI)
            self.state = 1788
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,99,self._ctx)
            if la_ == 1:
                self.state = 1787
                self.timeunits_declaration()


            self.state = 1799
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 103)) & ~0x3f) == 0 and ((1 << (_la - 103)) & ((1 << (SystemVerilogParser.KAUTOMATIC - 103)) | (1 << (SystemVerilogParser.KBIT - 103)) | (1 << (SystemVerilogParser.KBYTE - 103)) | (1 << (SystemVerilogParser.KCHANDLE - 103)) | (1 << (SystemVerilogParser.KCHECKER - 103)) | (1 << (SystemVerilogParser.KCLASS - 103)) | (1 << (SystemVerilogParser.KCONST - 103)) | (1 << (SystemVerilogParser.KCONSTRAINT - 103)) | (1 << (SystemVerilogParser.KCOVERGROUP - 103)) | (1 << (SystemVerilogParser.KENUM - 103)) | (1 << (SystemVerilogParser.KEVENT - 103)) | (1 << (SystemVerilogParser.KEXPORT - 103)))) != 0) or ((((_la - 174)) & ~0x3f) == 0 and ((1 << (_la - 174)) & ((1 << (SystemVerilogParser.KFUNCTION - 174)) | (1 << (SystemVerilogParser.KIMPORT - 174)) | (1 << (SystemVerilogParser.KINT - 174)) | (1 << (SystemVerilogParser.KINTEGER - 174)) | (1 << (SystemVerilogParser.KINTERCONNECT - 174)) | (1 << (SystemVerilogParser.KLET - 174)) | (1 << (SystemVerilogParser.KLOCALPARAM - 174)) | (1 << (SystemVerilogParser.KLOGIC - 174)) | (1 << (SystemVerilogParser.KLONGINT - 174)) | (1 << (SystemVerilogParser.KNETTYPE - 174)) | (1 << (SystemVerilogParser.KPARAMETER - 174)))) != 0) or ((((_la - 239)) & ~0x3f) == 0 and ((1 << (_la - 239)) & ((1 << (SystemVerilogParser.KPROGRAM - 239)) | (1 << (SystemVerilogParser.KPROPERTY - 239)) | (1 << (SystemVerilogParser.KREAL - 239)) | (1 << (SystemVerilogParser.KREALTIME - 239)) | (1 << (SystemVerilogParser.KREG - 239)) | (1 << (SystemVerilogParser.KSEQUENCE - 239)) | (1 << (SystemVerilogParser.KSHORTINT - 239)) | (1 << (SystemVerilogParser.KSHORTREAL - 239)) | (1 << (SystemVerilogParser.KSIGNED - 239)) | (1 << (SystemVerilogParser.KSTATIC - 239)) | (1 << (SystemVerilogParser.KSTRING - 239)) | (1 << (SystemVerilogParser.KSTRUCT - 239)) | (1 << (SystemVerilogParser.KSUPPLY0 - 239)) | (1 << (SystemVerilogParser.KSUPPLY1 - 239)) | (1 << (SystemVerilogParser.KTASK - 239)) | (1 << (SystemVerilogParser.KTIME - 239)) | (1 << (SystemVerilogParser.KTIMEPRECISION - 239)))) != 0) or ((((_la - 303)) & ~0x3f) == 0 and ((1 << (_la - 303)) & ((1 << (SystemVerilogParser.KTIMEUNIT - 303)) | (1 << (SystemVerilogParser.KTRI - 303)) | (1 << (SystemVerilogParser.KTRI0 - 303)) | (1 << (SystemVerilogParser.KTRI1 - 303)) | (1 << (SystemVerilogParser.KTRIAND - 303)) | (1 << (SystemVerilogParser.KTRIOR - 303)) | (1 << (SystemVerilogParser.KTRIREG - 303)) | (1 << (SystemVerilogParser.KTYPE - 303)) | (1 << (SystemVerilogParser.KTYPEDEF - 303)) | (1 << (SystemVerilogParser.KUNION - 303)) | (1 << (SystemVerilogParser.KUNSIGNED - 303)) | (1 << (SystemVerilogParser.KUWIRE - 303)) | (1 << (SystemVerilogParser.KVAR - 303)) | (1 << (SystemVerilogParser.KVIRTUAL - 303)) | (1 << (SystemVerilogParser.KWAND - 303)) | (1 << (SystemVerilogParser.KWIRE - 303)) | (1 << (SystemVerilogParser.KWOR - 303)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 303)))) != 0):
                self.state = 1793
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 1790
                    self.attribute_instance()
                    self.state = 1795
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1796
                self.package_item()
                self.state = 1801
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1802
            self.match(SystemVerilogParser.KENDPACKAGE)
            self.state = 1805
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 1803
                self.match(SystemVerilogParser.COLON)
                self.state = 1804
                self.package_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Timeunits_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KTIMEUNIT(self):
            return self.getToken(SystemVerilogParser.KTIMEUNIT, 0)

        def TIME_LITERAL(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.TIME_LITERAL)
            else:
                return self.getToken(SystemVerilogParser.TIME_LITERAL, i)

        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def KTIMEPRECISION(self):
            return self.getToken(SystemVerilogParser.KTIMEPRECISION, 0)

        def SLASH(self):
            return self.getToken(SystemVerilogParser.SLASH, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_timeunits_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTimeunits_declaration" ):
                listener.enterTimeunits_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTimeunits_declaration" ):
                listener.exitTimeunits_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTimeunits_declaration" ):
                return visitor.visitTimeunits_declaration(self)
            else:
                return visitor.visitChildren(self)




    def timeunits_declaration(self):

        localctx = SystemVerilogParser.Timeunits_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 46, self.RULE_timeunits_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1827
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KTIMEUNIT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1807
                self.match(SystemVerilogParser.KTIMEUNIT)
                self.state = 1808
                self.match(SystemVerilogParser.TIME_LITERAL)
                self.state = 1816
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,104,self._ctx)
                if la_ == 1:
                    self.state = 1811
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.SLASH:
                        self.state = 1809
                        self.match(SystemVerilogParser.SLASH)
                        self.state = 1810
                        self.match(SystemVerilogParser.TIME_LITERAL)


                    pass

                elif la_ == 2:
                    self.state = 1813
                    self.match(SystemVerilogParser.SEMI)
                    self.state = 1814
                    self.match(SystemVerilogParser.KTIMEPRECISION)
                    self.state = 1815
                    self.match(SystemVerilogParser.TIME_LITERAL)
                    pass


                self.state = 1818
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KTIMEPRECISION]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1819
                self.match(SystemVerilogParser.KTIMEPRECISION)
                self.state = 1820
                self.match(SystemVerilogParser.TIME_LITERAL)
                self.state = 1821
                self.match(SystemVerilogParser.SEMI)
                self.state = 1825
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,105,self._ctx)
                if la_ == 1:
                    self.state = 1822
                    self.match(SystemVerilogParser.KTIMEUNIT)
                    self.state = 1823
                    self.match(SystemVerilogParser.TIME_LITERAL)
                    self.state = 1824
                    self.match(SystemVerilogParser.SEMI)


                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def P(self):
            return self.getToken(SystemVerilogParser.P, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def list_of_param_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_param_assignmentsContext,0)


        def parameter_port_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Parameter_port_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Parameter_port_declarationContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_parameter_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_port_list" ):
                listener.enterParameter_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_port_list" ):
                listener.exitParameter_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_port_list" ):
                return visitor.visitParameter_port_list(self)
            else:
                return visitor.visitChildren(self)




    def parameter_port_list(self):

        localctx = SystemVerilogParser.Parameter_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 48, self.RULE_parameter_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1829
            self.match(SystemVerilogParser.P)
            self.state = 1830
            self.match(SystemVerilogParser.LP)
            self.state = 1842
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.DUNIT or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCALPARAM - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KPARAMETER - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSTRUCT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNION - 276)) | (1 << (SystemVerilogParser.KVIRTUAL - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 1833
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,107,self._ctx)
                if la_ == 1:
                    self.state = 1831
                    self.list_of_param_assignments()
                    pass

                elif la_ == 2:
                    self.state = 1832
                    self.parameter_port_declaration()
                    pass


                self.state = 1839
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 1835
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 1836
                    self.parameter_port_declaration()
                    self.state = 1841
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



            self.state = 1844
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_port_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_declarationContext,0)


        def local_parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Local_parameter_declarationContext,0)


        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def list_of_param_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_param_assignmentsContext,0)


        def KTYPE(self):
            return self.getToken(SystemVerilogParser.KTYPE, 0)

        def list_of_type_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_type_assignmentsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_parameter_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_port_declaration" ):
                listener.enterParameter_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_port_declaration" ):
                listener.exitParameter_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_port_declaration" ):
                return visitor.visitParameter_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def parameter_port_declaration(self):

        localctx = SystemVerilogParser.Parameter_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 50, self.RULE_parameter_port_declaration)
        try:
            self.state = 1853
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,110,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1846
                self.parameter_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1847
                self.local_parameter_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1848
                self.data_type()
                self.state = 1849
                self.list_of_param_assignments()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1851
                self.match(SystemVerilogParser.KTYPE)
                self.state = 1852
                self.list_of_type_assignments()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_portsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def port(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.PortContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.PortContext,i)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_ports

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_ports" ):
                listener.enterList_of_ports(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_ports" ):
                listener.exitList_of_ports(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_ports" ):
                return visitor.visitList_of_ports(self)
            else:
                return visitor.visitChildren(self)




    def list_of_ports(self):

        localctx = SystemVerilogParser.List_of_portsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 52, self.RULE_list_of_ports)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1855
            self.match(SystemVerilogParser.LP)
            self.state = 1856
            self.port()
            self.state = 1861
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 1857
                self.match(SystemVerilogParser.COMMA)
                self.state = 1858
                self.port()
                self.state = 1863
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1864
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_declarationsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def ansi_port_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Ansi_port_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Ansi_port_declarationContext,i)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_port_declarations

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_declarations" ):
                listener.enterList_of_port_declarations(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_declarations" ):
                listener.exitList_of_port_declarations(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_declarations" ):
                return visitor.visitList_of_port_declarations(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_declarations(self):

        localctx = SystemVerilogParser.List_of_port_declarationsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 54, self.RULE_list_of_port_declarations)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1866
            self.match(SystemVerilogParser.LP)
            self.state = 1887
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.DOT) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 191)) & ~0x3f) == 0 and ((1 << (_la - 191)) & ((1 << (SystemVerilogParser.KINOUT - 191)) | (1 << (SystemVerilogParser.KINPUT - 191)) | (1 << (SystemVerilogParser.KINT - 191)) | (1 << (SystemVerilogParser.KINTEGER - 191)) | (1 << (SystemVerilogParser.KINTERCONNECT - 191)) | (1 << (SystemVerilogParser.KINTERFACE - 191)) | (1 << (SystemVerilogParser.KLOGIC - 191)) | (1 << (SystemVerilogParser.KLONGINT - 191)) | (1 << (SystemVerilogParser.KOUTPUT - 191)))) != 0) or ((((_la - 255)) & ~0x3f) == 0 and ((1 << (_la - 255)) & ((1 << (SystemVerilogParser.KREAL - 255)) | (1 << (SystemVerilogParser.KREALTIME - 255)) | (1 << (SystemVerilogParser.KREF - 255)) | (1 << (SystemVerilogParser.KREG - 255)) | (1 << (SystemVerilogParser.KSHORTINT - 255)) | (1 << (SystemVerilogParser.KSHORTREAL - 255)) | (1 << (SystemVerilogParser.KSIGNED - 255)) | (1 << (SystemVerilogParser.KSTRING - 255)) | (1 << (SystemVerilogParser.KSTRUCT - 255)) | (1 << (SystemVerilogParser.KSUPPLY0 - 255)) | (1 << (SystemVerilogParser.KSUPPLY1 - 255)) | (1 << (SystemVerilogParser.KTIME - 255)) | (1 << (SystemVerilogParser.KTRI - 255)) | (1 << (SystemVerilogParser.KTRI0 - 255)) | (1 << (SystemVerilogParser.KTRI1 - 255)) | (1 << (SystemVerilogParser.KTRIAND - 255)) | (1 << (SystemVerilogParser.KTRIOR - 255)) | (1 << (SystemVerilogParser.KTRIREG - 255)) | (1 << (SystemVerilogParser.KTYPE - 255)) | (1 << (SystemVerilogParser.KUNION - 255)))) != 0) or ((((_la - 319)) & ~0x3f) == 0 and ((1 << (_la - 319)) & ((1 << (SystemVerilogParser.KUNSIGNED - 319)) | (1 << (SystemVerilogParser.KUWIRE - 319)) | (1 << (SystemVerilogParser.KVAR - 319)) | (1 << (SystemVerilogParser.KVIRTUAL - 319)) | (1 << (SystemVerilogParser.KWAND - 319)) | (1 << (SystemVerilogParser.KWIRE - 319)) | (1 << (SystemVerilogParser.KWOR - 319)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 319)))) != 0):
                self.state = 1870
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 1867
                    self.attribute_instance()
                    self.state = 1872
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1873
                self.ansi_port_declaration()
                self.state = 1884
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 1874
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 1878
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    while _la==SystemVerilogParser.LPS:
                        self.state = 1875
                        self.attribute_instance()
                        self.state = 1880
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)

                    self.state = 1881
                    self.ansi_port_declaration()
                    self.state = 1886
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



            self.state = 1889
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def inout_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inout_declarationContext,0)


        def input_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Input_declarationContext,0)


        def output_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Output_declarationContext,0)


        def ref_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ref_declarationContext,0)


        def interface_port_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_port_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_declaration" ):
                listener.enterPort_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_declaration" ):
                listener.exitPort_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_declaration" ):
                return visitor.visitPort_declaration(self)
            else:
                return visitor.visitChildren(self)




    def port_declaration(self):

        localctx = SystemVerilogParser.Port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 56, self.RULE_port_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1894
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 1891
                self.attribute_instance()
                self.state = 1896
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 1902
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KINOUT]:
                self.state = 1897
                self.inout_declaration()
                pass
            elif token in [SystemVerilogParser.KINPUT]:
                self.state = 1898
                self.input_declaration()
                pass
            elif token in [SystemVerilogParser.KOUTPUT]:
                self.state = 1899
                self.output_declaration()
                pass
            elif token in [SystemVerilogParser.KREF]:
                self.state = 1900
                self.ref_declaration()
                pass
            elif token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 1901
                self.interface_port_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class PortContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_expressionContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_port

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort" ):
                listener.enterPort(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort" ):
                listener.exitPort(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort" ):
                return visitor.visitPort(self)
            else:
                return visitor.visitChildren(self)




    def port(self):

        localctx = SystemVerilogParser.PortContext(self, self._ctx, self.state)
        self.enterRule(localctx, 58, self.RULE_port)
        self._la = 0 # Token type
        try:
            self.state = 1915
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.RP, SystemVerilogParser.COMMA, SystemVerilogParser.LC, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1905
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LC or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 1904
                    self.port_expression()


                pass
            elif token in [SystemVerilogParser.DOT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1907
                self.match(SystemVerilogParser.DOT)
                self.state = 1908
                self.port_identifier()
                self.state = 1909
                self.match(SystemVerilogParser.LP)
                self.state = 1911
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LC or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 1910
                    self.port_expression()


                self.state = 1913
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_reference(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Port_referenceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Port_referenceContext,i)


        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_port_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_expression" ):
                listener.enterPort_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_expression" ):
                listener.exitPort_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_expression" ):
                return visitor.visitPort_expression(self)
            else:
                return visitor.visitChildren(self)




    def port_expression(self):

        localctx = SystemVerilogParser.Port_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 60, self.RULE_port_expression)
        self._la = 0 # Token type
        try:
            self.state = 1929
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1917
                self.port_reference()
                pass
            elif token in [SystemVerilogParser.LC]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1918
                self.match(SystemVerilogParser.LC)
                self.state = 1919
                self.port_reference()
                self.state = 1924
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 1920
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 1921
                    self.port_reference()
                    self.state = 1926
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1927
                self.match(SystemVerilogParser.RC)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_referenceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,0)


        def constant_select(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_selectContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_port_reference

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_reference" ):
                listener.enterPort_reference(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_reference" ):
                listener.exitPort_reference(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_reference" ):
                return visitor.visitPort_reference(self)
            else:
                return visitor.visitChildren(self)




    def port_reference(self):

        localctx = SystemVerilogParser.Port_referenceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 62, self.RULE_port_reference)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1931
            self.port_identifier()
            self.state = 1932
            self.constant_select()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_directionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINPUT(self):
            return self.getToken(SystemVerilogParser.KINPUT, 0)

        def KOUTPUT(self):
            return self.getToken(SystemVerilogParser.KOUTPUT, 0)

        def KINOUT(self):
            return self.getToken(SystemVerilogParser.KINOUT, 0)

        def KREF(self):
            return self.getToken(SystemVerilogParser.KREF, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_port_direction

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_direction" ):
                listener.enterPort_direction(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_direction" ):
                listener.exitPort_direction(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_direction" ):
                return visitor.visitPort_direction(self)
            else:
                return visitor.visitChildren(self)




    def port_direction(self):

        localctx = SystemVerilogParser.Port_directionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 64, self.RULE_port_direction)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1934
            _la = self._input.LA(1)
            if not(((((_la - 191)) & ~0x3f) == 0 and ((1 << (_la - 191)) & ((1 << (SystemVerilogParser.KINOUT - 191)) | (1 << (SystemVerilogParser.KINPUT - 191)) | (1 << (SystemVerilogParser.KOUTPUT - 191)))) != 0) or _la==SystemVerilogParser.KREF):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_port_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_port_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_port_typeContext,0)


        def port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_directionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_port_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_port_header" ):
                listener.enterNet_port_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_port_header" ):
                listener.exitNet_port_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_port_header" ):
                return visitor.visitNet_port_header(self)
            else:
                return visitor.visitChildren(self)




    def net_port_header(self):

        localctx = SystemVerilogParser.Net_port_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 66, self.RULE_net_port_header)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1937
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 191)) & ~0x3f) == 0 and ((1 << (_la - 191)) & ((1 << (SystemVerilogParser.KINOUT - 191)) | (1 << (SystemVerilogParser.KINPUT - 191)) | (1 << (SystemVerilogParser.KOUTPUT - 191)))) != 0) or _la==SystemVerilogParser.KREF:
                self.state = 1936
                self.port_direction()


            self.state = 1939
            self.net_port_type()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_port_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_port_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_port_typeContext,0)


        def port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_directionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_variable_port_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_port_header" ):
                listener.enterVariable_port_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_port_header" ):
                listener.exitVariable_port_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_port_header" ):
                return visitor.visitVariable_port_header(self)
            else:
                return visitor.visitChildren(self)




    def variable_port_header(self):

        localctx = SystemVerilogParser.Variable_port_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 68, self.RULE_variable_port_header)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1942
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 191)) & ~0x3f) == 0 and ((1 << (_la - 191)) & ((1 << (SystemVerilogParser.KINOUT - 191)) | (1 << (SystemVerilogParser.KINPUT - 191)) | (1 << (SystemVerilogParser.KOUTPUT - 191)))) != 0) or _la==SystemVerilogParser.KREF:
                self.state = 1941
                self.port_direction()


            self.state = 1944
            self.variable_port_type()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_port_headerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def modport_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Modport_identifierContext,0)


        def KINTERFACE(self):
            return self.getToken(SystemVerilogParser.KINTERFACE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_port_header

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_port_header" ):
                listener.enterInterface_port_header(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_port_header" ):
                listener.exitInterface_port_header(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_port_header" ):
                return visitor.visitInterface_port_header(self)
            else:
                return visitor.visitChildren(self)




    def interface_port_header(self):

        localctx = SystemVerilogParser.Interface_port_headerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 70, self.RULE_interface_port_header)
        self._la = 0 # Token type
        try:
            self.state = 1956
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1946
                self.interface_identifier()
                self.state = 1949
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.DOT:
                    self.state = 1947
                    self.match(SystemVerilogParser.DOT)
                    self.state = 1948
                    self.modport_identifier()


                pass
            elif token in [SystemVerilogParser.KINTERFACE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1951
                self.match(SystemVerilogParser.KINTERFACE)
                self.state = 1954
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.DOT:
                    self.state = 1952
                    self.match(SystemVerilogParser.DOT)
                    self.state = 1953
                    self.modport_identifier()


                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ansi_port_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,0)


        def net_port_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_port_headerContext,0)


        def interface_port_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_port_headerContext,0)


        def unpacked_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Unpacked_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Unpacked_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def variable_port_header(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_port_headerContext,0)


        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_directionContext,0)


        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ansi_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAnsi_port_declaration" ):
                listener.enterAnsi_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAnsi_port_declaration" ):
                listener.exitAnsi_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAnsi_port_declaration" ):
                return visitor.visitAnsi_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def ansi_port_declaration(self):

        localctx = SystemVerilogParser.Ansi_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 72, self.RULE_ansi_port_declaration)
        self._la = 0 # Token type
        try:
            self.state = 1998
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,136,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1960
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,128,self._ctx)
                if la_ == 1:
                    self.state = 1958
                    self.net_port_header()

                elif la_ == 2:
                    self.state = 1959
                    self.interface_port_header()


                self.state = 1962
                self.port_identifier()
                self.state = 1966
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 1963
                    self.unpacked_dimension()
                    self.state = 1968
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1971
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 1969
                    self.match(SystemVerilogParser.EQ)
                    self.state = 1970
                    self.constant_expression(0)


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1974
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,131,self._ctx)
                if la_ == 1:
                    self.state = 1973
                    self.variable_port_header()


                self.state = 1976
                self.port_identifier()
                self.state = 1980
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 1977
                    self.variable_dimension()
                    self.state = 1982
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 1985
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 1983
                    self.match(SystemVerilogParser.EQ)
                    self.state = 1984
                    self.constant_expression(0)


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1988
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 191)) & ~0x3f) == 0 and ((1 << (_la - 191)) & ((1 << (SystemVerilogParser.KINOUT - 191)) | (1 << (SystemVerilogParser.KINPUT - 191)) | (1 << (SystemVerilogParser.KOUTPUT - 191)))) != 0) or _la==SystemVerilogParser.KREF:
                    self.state = 1987
                    self.port_direction()


                self.state = 1990
                self.match(SystemVerilogParser.DOT)
                self.state = 1991
                self.port_identifier()
                self.state = 1992
                self.match(SystemVerilogParser.LP)
                self.state = 1994
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 1993
                    self.expression(0)


                self.state = 1996
                self.match(SystemVerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Elaboration_system_taskContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DFATAL(self):
            return self.getToken(SystemVerilogParser.DFATAL, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def DERROR(self):
            return self.getToken(SystemVerilogParser.DERROR, 0)

        def DWARNING(self):
            return self.getToken(SystemVerilogParser.DWARNING, 0)

        def DINFO(self):
            return self.getToken(SystemVerilogParser.DINFO, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_elaboration_system_task

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterElaboration_system_task" ):
                listener.enterElaboration_system_task(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitElaboration_system_task" ):
                listener.exitElaboration_system_task(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitElaboration_system_task" ):
                return visitor.visitElaboration_system_task(self)
            else:
                return visitor.visitChildren(self)




    def elaboration_system_task(self):

        localctx = SystemVerilogParser.Elaboration_system_taskContext(self, self._ctx, self.state)
        self.enterRule(localctx, 74, self.RULE_elaboration_system_task)
        self._la = 0 # Token type
        try:
            self.state = 2018
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DFATAL]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2000
                self.match(SystemVerilogParser.DFATAL)
                self.state = 2006
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 2001
                    self.match(SystemVerilogParser.LP)
                    self.state = 2003
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,137,self._ctx)
                    if la_ == 1:
                        self.state = 2002
                        self.list_of_arguments()


                    self.state = 2005
                    self.match(SystemVerilogParser.RP)


                self.state = 2008
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.DERROR, SystemVerilogParser.DINFO, SystemVerilogParser.DWARNING]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2009
                _la = self._input.LA(1)
                if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DWARNING))) != 0)):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 2015
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 2010
                    self.match(SystemVerilogParser.LP)
                    self.state = 2012
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,139,self._ctx)
                    if la_ == 1:
                        self.state = 2011
                        self.list_of_arguments()


                    self.state = 2014
                    self.match(SystemVerilogParser.RP)


                self.state = 2017
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_common_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_or_generate_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_or_generate_item_declarationContext,0)


        def interface_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_instantiationContext,0)


        def program_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_instantiationContext,0)


        def assertion_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assertion_itemContext,0)


        def bind_directive(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bind_directiveContext,0)


        def continuous_assign(self):
            return self.getTypedRuleContext(SystemVerilogParser.Continuous_assignContext,0)


        def net_alias(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_aliasContext,0)


        def initial_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Initial_constructContext,0)


        def final_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Final_constructContext,0)


        def always_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Always_constructContext,0)


        def loop_generate_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Loop_generate_constructContext,0)


        def conditional_generate_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Conditional_generate_constructContext,0)


        def elaboration_system_task(self):
            return self.getTypedRuleContext(SystemVerilogParser.Elaboration_system_taskContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_common_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_common_item" ):
                listener.enterModule_common_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_common_item" ):
                listener.exitModule_common_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_common_item" ):
                return visitor.visitModule_common_item(self)
            else:
                return visitor.visitChildren(self)




    def module_common_item(self):

        localctx = SystemVerilogParser.Module_common_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 76, self.RULE_module_common_item)
        try:
            self.state = 2033
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,142,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2020
                self.module_or_generate_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2021
                self.interface_instantiation()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2022
                self.program_instantiation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2023
                self.assertion_item()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2024
                self.bind_directive()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2025
                self.continuous_assign()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2026
                self.net_alias()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2027
                self.initial_construct()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 2028
                self.final_construct()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 2029
                self.always_construct()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 2030
                self.loop_generate_construct()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 2031
                self.conditional_generate_construct()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 2032
                self.elaboration_system_task()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_declarationContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def non_port_module_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Non_port_module_itemContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_item" ):
                listener.enterModule_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_item" ):
                listener.exitModule_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_item" ):
                return visitor.visitModule_item(self)
            else:
                return visitor.visitChildren(self)




    def module_item(self):

        localctx = SystemVerilogParser.Module_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 78, self.RULE_module_item)
        try:
            self.state = 2039
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,143,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2035
                self.port_declaration()
                self.state = 2036
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2038
                self.non_port_module_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_or_generate_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_override(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_overrideContext,0)


        def gate_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Gate_instantiationContext,0)


        def module_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_instantiationContext,0)


        def module_common_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_common_itemContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_or_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_or_generate_item" ):
                listener.enterModule_or_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_or_generate_item" ):
                listener.exitModule_or_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_or_generate_item" ):
                return visitor.visitModule_or_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def module_or_generate_item(self):

        localctx = SystemVerilogParser.Module_or_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 80, self.RULE_module_or_generate_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2044
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 2041
                self.attribute_instance()
                self.state = 2046
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2051
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,145,self._ctx)
            if la_ == 1:
                self.state = 2047
                self.parameter_override()
                pass

            elif la_ == 2:
                self.state = 2048
                self.gate_instantiation()
                pass

            elif la_ == 3:
                self.state = 2049
                self.module_instantiation()
                pass

            elif la_ == 4:
                self.state = 2050
                self.module_common_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_or_generate_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def package_or_generate_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_or_generate_item_declarationContext,0)


        def genvar_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_declarationContext,0)


        def clocking_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_declarationContext,0)


        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KCLOCKING(self):
            return self.getToken(SystemVerilogParser.KCLOCKING, 0)

        def clocking_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_identifierContext,0)


        def KDISABLE(self):
            return self.getToken(SystemVerilogParser.KDISABLE, 0)

        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def expression_or_dist(self):
            return self.getTypedRuleContext(SystemVerilogParser.Expression_or_distContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_or_generate_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_or_generate_item_declaration" ):
                listener.enterModule_or_generate_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_or_generate_item_declaration" ):
                listener.exitModule_or_generate_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_or_generate_item_declaration" ):
                return visitor.visitModule_or_generate_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def module_or_generate_item_declaration(self):

        localctx = SystemVerilogParser.Module_or_generate_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 82, self.RULE_module_or_generate_item_declaration)
        try:
            self.state = 2066
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,147,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2053
                self.package_or_generate_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2054
                self.genvar_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2055
                self.clocking_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2056
                self.match(SystemVerilogParser.KDEFAULT)
                self.state = 2062
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KCLOCKING]:
                    self.state = 2057
                    self.match(SystemVerilogParser.KCLOCKING)
                    self.state = 2058
                    self.clocking_identifier()
                    pass
                elif token in [SystemVerilogParser.KDISABLE]:
                    self.state = 2059
                    self.match(SystemVerilogParser.KDISABLE)
                    self.state = 2060
                    self.match(SystemVerilogParser.KIFF)
                    self.state = 2061
                    self.expression_or_dist()
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 2064
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Non_port_module_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_region(self):
            return self.getTypedRuleContext(SystemVerilogParser.Generate_regionContext,0)


        def module_or_generate_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_or_generate_itemContext,0)


        def specify_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specify_blockContext,0)


        def specparam_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specparam_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def program_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_declarationContext,0)


        def module_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_declarationContext,0)


        def interface_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_declarationContext,0)


        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_non_port_module_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNon_port_module_item" ):
                listener.enterNon_port_module_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNon_port_module_item" ):
                listener.exitNon_port_module_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNon_port_module_item" ):
                return visitor.visitNon_port_module_item(self)
            else:
                return visitor.visitChildren(self)




    def non_port_module_item(self):

        localctx = SystemVerilogParser.Non_port_module_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 84, self.RULE_non_port_module_item)
        self._la = 0 # Token type
        try:
            self.state = 2082
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,149,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2068
                self.generate_region()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2069
                self.module_or_generate_item()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2070
                self.specify_block()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2074
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 2071
                    self.attribute_instance()
                    self.state = 2076
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2077
                self.specparam_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2078
                self.program_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2079
                self.module_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2080
                self.interface_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2081
                self.timeunits_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_overrideContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KDEFPARAM(self):
            return self.getToken(SystemVerilogParser.KDEFPARAM, 0)

        def list_of_defparam_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_defparam_assignmentsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_parameter_override

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_override" ):
                listener.enterParameter_override(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_override" ):
                listener.exitParameter_override(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_override" ):
                return visitor.visitParameter_override(self)
            else:
                return visitor.visitChildren(self)




    def parameter_override(self):

        localctx = SystemVerilogParser.Parameter_overrideContext(self, self._ctx, self.state)
        self.enterRule(localctx, 86, self.RULE_parameter_override)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2084
            self.match(SystemVerilogParser.KDEFPARAM)
            self.state = 2085
            self.list_of_defparam_assignments()
            self.state = 2086
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bind_directiveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KBIND(self):
            return self.getToken(SystemVerilogParser.KBIND, 0)

        def bind_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bind_instantiationContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def bind_target_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bind_target_scopeContext,0)


        def bind_target_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bind_target_instanceContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def bind_target_instance_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bind_target_instance_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bind_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBind_directive" ):
                listener.enterBind_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBind_directive" ):
                listener.exitBind_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBind_directive" ):
                return visitor.visitBind_directive(self)
            else:
                return visitor.visitChildren(self)




    def bind_directive(self):

        localctx = SystemVerilogParser.Bind_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 88, self.RULE_bind_directive)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2088
            self.match(SystemVerilogParser.KBIND)
            self.state = 2095
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,151,self._ctx)
            if la_ == 1:
                self.state = 2089
                self.bind_target_scope()
                self.state = 2092
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 2090
                    self.match(SystemVerilogParser.COLON)
                    self.state = 2091
                    self.bind_target_instance_list()


                pass

            elif la_ == 2:
                self.state = 2094
                self.bind_target_instance()
                pass


            self.state = 2097
            self.bind_instantiation()
            self.state = 2098
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bind_target_scopeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_identifierContext,0)


        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bind_target_scope

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBind_target_scope" ):
                listener.enterBind_target_scope(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBind_target_scope" ):
                listener.exitBind_target_scope(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBind_target_scope" ):
                return visitor.visitBind_target_scope(self)
            else:
                return visitor.visitChildren(self)




    def bind_target_scope(self):

        localctx = SystemVerilogParser.Bind_target_scopeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 90, self.RULE_bind_target_scope)
        try:
            self.state = 2102
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,152,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2100
                self.module_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2101
                self.interface_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bind_target_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def constant_bit_select(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_bit_selectContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bind_target_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBind_target_instance" ):
                listener.enterBind_target_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBind_target_instance" ):
                listener.exitBind_target_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBind_target_instance" ):
                return visitor.visitBind_target_instance(self)
            else:
                return visitor.visitChildren(self)




    def bind_target_instance(self):

        localctx = SystemVerilogParser.Bind_target_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 92, self.RULE_bind_target_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2104
            self.hierarchical_identifier()
            self.state = 2105
            self.constant_bit_select()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bind_target_instance_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def bind_target_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Bind_target_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Bind_target_instanceContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bind_target_instance_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBind_target_instance_list" ):
                listener.enterBind_target_instance_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBind_target_instance_list" ):
                listener.exitBind_target_instance_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBind_target_instance_list" ):
                return visitor.visitBind_target_instance_list(self)
            else:
                return visitor.visitChildren(self)




    def bind_target_instance_list(self):

        localctx = SystemVerilogParser.Bind_target_instance_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 94, self.RULE_bind_target_instance_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2107
            self.bind_target_instance()
            self.state = 2112
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 2108
                self.match(SystemVerilogParser.COMMA)
                self.state = 2109
                self.bind_target_instance()
                self.state = 2114
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bind_instantiationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def program_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_instantiationContext,0)


        def module_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_instantiationContext,0)


        def interface_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_instantiationContext,0)


        def checker_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_instantiationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bind_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBind_instantiation" ):
                listener.enterBind_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBind_instantiation" ):
                listener.exitBind_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBind_instantiation" ):
                return visitor.visitBind_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def bind_instantiation(self):

        localctx = SystemVerilogParser.Bind_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 96, self.RULE_bind_instantiation)
        try:
            self.state = 2119
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,154,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2115
                self.program_instantiation()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2116
                self.module_instantiation()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2117
                self.interface_instantiation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2118
                self.checker_instantiation()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Config_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCONFIG(self):
            return self.getToken(SystemVerilogParser.KCONFIG, 0)

        def config_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Config_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Config_identifierContext,i)


        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def design_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Design_statementContext,0)


        def KENDCONFIG(self):
            return self.getToken(SystemVerilogParser.KENDCONFIG, 0)

        def local_parameter_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Local_parameter_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Local_parameter_declarationContext,i)


        def config_rule_statement(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Config_rule_statementContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Config_rule_statementContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_config_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_declaration" ):
                listener.enterConfig_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_declaration" ):
                listener.exitConfig_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_declaration" ):
                return visitor.visitConfig_declaration(self)
            else:
                return visitor.visitChildren(self)




    def config_declaration(self):

        localctx = SystemVerilogParser.Config_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 98, self.RULE_config_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2121
            self.match(SystemVerilogParser.KCONFIG)
            self.state = 2122
            self.config_identifier()
            self.state = 2123
            self.match(SystemVerilogParser.SEMI)
            self.state = 2129
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.KLOCALPARAM:
                self.state = 2124
                self.local_parameter_declaration()
                self.state = 2125
                self.match(SystemVerilogParser.SEMI)
                self.state = 2131
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2132
            self.design_statement()
            self.state = 2136
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.KCELL or _la==SystemVerilogParser.KDEFAULT or _la==SystemVerilogParser.KINSTANCE:
                self.state = 2133
                self.config_rule_statement()
                self.state = 2138
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2139
            self.match(SystemVerilogParser.KENDCONFIG)
            self.state = 2142
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 2140
                self.match(SystemVerilogParser.COLON)
                self.state = 2141
                self.config_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Design_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KDESIGN(self):
            return self.getToken(SystemVerilogParser.KDESIGN, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def cell_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Cell_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Cell_identifierContext,i)


        def library_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Library_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Library_identifierContext,i)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_design_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDesign_statement" ):
                listener.enterDesign_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDesign_statement" ):
                listener.exitDesign_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDesign_statement" ):
                return visitor.visitDesign_statement(self)
            else:
                return visitor.visitChildren(self)




    def design_statement(self):

        localctx = SystemVerilogParser.Design_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 100, self.RULE_design_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2144
            self.match(SystemVerilogParser.KDESIGN)
            self.state = 2153
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2148
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,158,self._ctx)
                if la_ == 1:
                    self.state = 2145
                    self.library_identifier()
                    self.state = 2146
                    self.match(SystemVerilogParser.DOT)


                self.state = 2150
                self.cell_identifier()
                self.state = 2155
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2156
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Config_rule_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def liblist_clause(self):
            return self.getTypedRuleContext(SystemVerilogParser.Liblist_clauseContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def default_clause(self):
            return self.getTypedRuleContext(SystemVerilogParser.Default_clauseContext,0)


        def inst_clause(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inst_clauseContext,0)


        def cell_clause(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cell_clauseContext,0)


        def use_clause(self):
            return self.getTypedRuleContext(SystemVerilogParser.Use_clauseContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_config_rule_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_rule_statement" ):
                listener.enterConfig_rule_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_rule_statement" ):
                listener.exitConfig_rule_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_rule_statement" ):
                return visitor.visitConfig_rule_statement(self)
            else:
                return visitor.visitChildren(self)




    def config_rule_statement(self):

        localctx = SystemVerilogParser.Config_rule_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 102, self.RULE_config_rule_statement)
        try:
            self.state = 2173
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,162,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2161
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KDEFAULT]:
                    self.state = 2158
                    self.default_clause()
                    pass
                elif token in [SystemVerilogParser.KINSTANCE]:
                    self.state = 2159
                    self.inst_clause()
                    pass
                elif token in [SystemVerilogParser.KCELL]:
                    self.state = 2160
                    self.cell_clause()
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 2163
                self.liblist_clause()
                self.state = 2164
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2168
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KINSTANCE]:
                    self.state = 2166
                    self.inst_clause()
                    pass
                elif token in [SystemVerilogParser.KCELL]:
                    self.state = 2167
                    self.cell_clause()
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 2170
                self.use_clause()
                self.state = 2171
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Default_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_default_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefault_clause" ):
                listener.enterDefault_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefault_clause" ):
                listener.exitDefault_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefault_clause" ):
                return visitor.visitDefault_clause(self)
            else:
                return visitor.visitChildren(self)




    def default_clause(self):

        localctx = SystemVerilogParser.Default_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 104, self.RULE_default_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2175
            self.match(SystemVerilogParser.KDEFAULT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inst_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINSTANCE(self):
            return self.getToken(SystemVerilogParser.KINSTANCE, 0)

        def inst_name(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inst_nameContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_inst_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInst_clause" ):
                listener.enterInst_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInst_clause" ):
                listener.exitInst_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInst_clause" ):
                return visitor.visitInst_clause(self)
            else:
                return visitor.visitChildren(self)




    def inst_clause(self):

        localctx = SystemVerilogParser.Inst_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 106, self.RULE_inst_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2177
            self.match(SystemVerilogParser.KINSTANCE)
            self.state = 2178
            self.inst_name()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inst_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def topmodule_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Topmodule_identifierContext,0)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def instance_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Instance_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Instance_identifierContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_inst_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInst_name" ):
                listener.enterInst_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInst_name" ):
                listener.exitInst_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInst_name" ):
                return visitor.visitInst_name(self)
            else:
                return visitor.visitChildren(self)




    def inst_name(self):

        localctx = SystemVerilogParser.Inst_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 108, self.RULE_inst_name)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2180
            self.topmodule_identifier()
            self.state = 2185
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.DOT:
                self.state = 2181
                self.match(SystemVerilogParser.DOT)
                self.state = 2182
                self.instance_identifier()
                self.state = 2187
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cell_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCELL(self):
            return self.getToken(SystemVerilogParser.KCELL, 0)

        def cell_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cell_identifierContext,0)


        def library_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Library_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cell_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCell_clause" ):
                listener.enterCell_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCell_clause" ):
                listener.exitCell_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCell_clause" ):
                return visitor.visitCell_clause(self)
            else:
                return visitor.visitChildren(self)




    def cell_clause(self):

        localctx = SystemVerilogParser.Cell_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 110, self.RULE_cell_clause)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2188
            self.match(SystemVerilogParser.KCELL)
            self.state = 2192
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,164,self._ctx)
            if la_ == 1:
                self.state = 2189
                self.library_identifier()
                self.state = 2190
                self.match(SystemVerilogParser.DOT)


            self.state = 2194
            self.cell_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Liblist_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KLIBLIST(self):
            return self.getToken(SystemVerilogParser.KLIBLIST, 0)

        def library_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Library_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Library_identifierContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_liblist_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLiblist_clause" ):
                listener.enterLiblist_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLiblist_clause" ):
                listener.exitLiblist_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLiblist_clause" ):
                return visitor.visitLiblist_clause(self)
            else:
                return visitor.visitChildren(self)




    def liblist_clause(self):

        localctx = SystemVerilogParser.Liblist_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 112, self.RULE_liblist_clause)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2196
            self.match(SystemVerilogParser.KLIBLIST)
            self.state = 2200
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2197
                self.library_identifier()
                self.state = 2202
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Use_clauseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KUSE(self):
            return self.getToken(SystemVerilogParser.KUSE, 0)

        def cell_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cell_identifierContext,0)


        def library_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Library_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def named_parameter_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Named_parameter_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Named_parameter_assignmentContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def KCONFIG(self):
            return self.getToken(SystemVerilogParser.KCONFIG, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_use_clause

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUse_clause" ):
                listener.enterUse_clause(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUse_clause" ):
                listener.exitUse_clause(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUse_clause" ):
                return visitor.visitUse_clause(self)
            else:
                return visitor.visitChildren(self)




    def use_clause(self):

        localctx = SystemVerilogParser.Use_clauseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 114, self.RULE_use_clause)
        self._la = 0 # Token type
        try:
            self.state = 2237
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,172,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2203
                self.match(SystemVerilogParser.KUSE)
                self.state = 2207
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,166,self._ctx)
                if la_ == 1:
                    self.state = 2204
                    self.library_identifier()
                    self.state = 2205
                    self.match(SystemVerilogParser.DOT)


                self.state = 2209
                self.cell_identifier()
                self.state = 2218
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.DOT:
                    self.state = 2210
                    self.named_parameter_assignment()
                    self.state = 2215
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    while _la==SystemVerilogParser.COMMA:
                        self.state = 2211
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 2212
                        self.named_parameter_assignment()
                        self.state = 2217
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)



                self.state = 2222
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 2220
                    self.match(SystemVerilogParser.COLON)
                    self.state = 2221
                    self.match(SystemVerilogParser.KCONFIG)


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2224
                self.match(SystemVerilogParser.KUSE)
                self.state = 2225
                self.named_parameter_assignment()
                self.state = 2230
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 2226
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 2227
                    self.named_parameter_assignment()
                    self.state = 2232
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2235
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 2233
                    self.match(SystemVerilogParser.COLON)
                    self.state = 2234
                    self.match(SystemVerilogParser.KCONFIG)


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_or_generate_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_common_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_common_itemContext,0)


        def extern_tf_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Extern_tf_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_or_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_or_generate_item" ):
                listener.enterInterface_or_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_or_generate_item" ):
                listener.exitInterface_or_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_or_generate_item" ):
                return visitor.visitInterface_or_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def interface_or_generate_item(self):

        localctx = SystemVerilogParser.Interface_or_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 116, self.RULE_interface_or_generate_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2242
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 2239
                self.attribute_instance()
                self.state = 2244
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2247
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DERROR, SystemVerilogParser.DFATAL, SystemVerilogParser.DINFO, SystemVerilogParser.DUNIT, SystemVerilogParser.DWARNING, SystemVerilogParser.SEMI, SystemVerilogParser.LB, SystemVerilogParser.KALIAS, SystemVerilogParser.KALWAYS, SystemVerilogParser.KALWAYS_COMB, SystemVerilogParser.KALWAYS_FF, SystemVerilogParser.KALWAYS_LATCH, SystemVerilogParser.KASSERT, SystemVerilogParser.KASSIGN, SystemVerilogParser.KASSUME, SystemVerilogParser.KAUTOMATIC, SystemVerilogParser.KBIND, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCASE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KCHECKER, SystemVerilogParser.KCLASS, SystemVerilogParser.KCLOCKING, SystemVerilogParser.KCONST, SystemVerilogParser.KCONSTRAINT, SystemVerilogParser.KCOVER, SystemVerilogParser.KCOVERGROUP, SystemVerilogParser.KDEFAULT, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KEXPORT, SystemVerilogParser.KFINAL, SystemVerilogParser.KFOR, SystemVerilogParser.KFUNCTION, SystemVerilogParser.KGENVAR, SystemVerilogParser.KGLOBAL, SystemVerilogParser.KIF, SystemVerilogParser.KIMPORT, SystemVerilogParser.KINITIAL, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KINTERCONNECT, SystemVerilogParser.KLET, SystemVerilogParser.KLOCALPARAM, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNETTYPE, SystemVerilogParser.KPARAMETER, SystemVerilogParser.KPROPERTY, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KRESTRICT, SystemVerilogParser.KSEQUENCE, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTATIC, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KSUPPLY0, SystemVerilogParser.KSUPPLY1, SystemVerilogParser.KTASK, SystemVerilogParser.KTIME, SystemVerilogParser.KTRI, SystemVerilogParser.KTRI0, SystemVerilogParser.KTRI1, SystemVerilogParser.KTRIAND, SystemVerilogParser.KTRIOR, SystemVerilogParser.KTRIREG, SystemVerilogParser.KTYPE, SystemVerilogParser.KTYPEDEF, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KUWIRE, SystemVerilogParser.KVAR, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.KWAND, SystemVerilogParser.KWIRE, SystemVerilogParser.KWOR, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 2245
                self.module_common_item()
                pass
            elif token in [SystemVerilogParser.KEXTERN]:
                self.state = 2246
                self.extern_tf_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Extern_tf_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KEXTERN(self):
            return self.getToken(SystemVerilogParser.KEXTERN, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def method_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_prototypeContext,0)


        def KFORKJOIN(self):
            return self.getToken(SystemVerilogParser.KFORKJOIN, 0)

        def task_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_prototypeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_extern_tf_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExtern_tf_declaration" ):
                listener.enterExtern_tf_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExtern_tf_declaration" ):
                listener.exitExtern_tf_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExtern_tf_declaration" ):
                return visitor.visitExtern_tf_declaration(self)
            else:
                return visitor.visitChildren(self)




    def extern_tf_declaration(self):

        localctx = SystemVerilogParser.Extern_tf_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 118, self.RULE_extern_tf_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2249
            self.match(SystemVerilogParser.KEXTERN)
            self.state = 2253
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KFUNCTION, SystemVerilogParser.KTASK]:
                self.state = 2250
                self.method_prototype()
                pass
            elif token in [SystemVerilogParser.KFORKJOIN]:
                self.state = 2251
                self.match(SystemVerilogParser.KFORKJOIN)
                self.state = 2252
                self.task_prototype()
                pass
            else:
                raise NoViableAltException(self)

            self.state = 2255
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_declarationContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def non_port_interface_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Non_port_interface_itemContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_item" ):
                listener.enterInterface_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_item" ):
                listener.exitInterface_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_item" ):
                return visitor.visitInterface_item(self)
            else:
                return visitor.visitChildren(self)




    def interface_item(self):

        localctx = SystemVerilogParser.Interface_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 120, self.RULE_interface_item)
        try:
            self.state = 2261
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,176,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2257
                self.port_declaration()
                self.state = 2258
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2260
                self.non_port_interface_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Non_port_interface_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_region(self):
            return self.getTypedRuleContext(SystemVerilogParser.Generate_regionContext,0)


        def interface_or_generate_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_or_generate_itemContext,0)


        def program_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_declarationContext,0)


        def modport_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Modport_declarationContext,0)


        def interface_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_declarationContext,0)


        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_non_port_interface_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNon_port_interface_item" ):
                listener.enterNon_port_interface_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNon_port_interface_item" ):
                listener.exitNon_port_interface_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNon_port_interface_item" ):
                return visitor.visitNon_port_interface_item(self)
            else:
                return visitor.visitChildren(self)




    def non_port_interface_item(self):

        localctx = SystemVerilogParser.Non_port_interface_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 122, self.RULE_non_port_interface_item)
        try:
            self.state = 2269
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,177,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2263
                self.generate_region()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2264
                self.interface_or_generate_item()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2265
                self.program_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2266
                self.modport_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2267
                self.interface_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2268
                self.timeunits_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Program_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_declarationContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def non_port_program_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Non_port_program_itemContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_program_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProgram_item" ):
                listener.enterProgram_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProgram_item" ):
                listener.exitProgram_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProgram_item" ):
                return visitor.visitProgram_item(self)
            else:
                return visitor.visitChildren(self)




    def program_item(self):

        localctx = SystemVerilogParser.Program_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 124, self.RULE_program_item)
        try:
            self.state = 2275
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,178,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2271
                self.port_declaration()
                self.state = 2272
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2274
                self.non_port_program_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Non_port_program_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def continuous_assign(self):
            return self.getTypedRuleContext(SystemVerilogParser.Continuous_assignContext,0)


        def module_or_generate_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_or_generate_item_declarationContext,0)


        def initial_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Initial_constructContext,0)


        def final_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Final_constructContext,0)


        def concurrent_assertion_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Concurrent_assertion_itemContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def program_generate_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_generate_itemContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_non_port_program_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNon_port_program_item" ):
                listener.enterNon_port_program_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNon_port_program_item" ):
                listener.exitNon_port_program_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNon_port_program_item" ):
                return visitor.visitNon_port_program_item(self)
            else:
                return visitor.visitChildren(self)




    def non_port_program_item(self):

        localctx = SystemVerilogParser.Non_port_program_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 126, self.RULE_non_port_program_item)
        self._la = 0 # Token type
        try:
            self.state = 2292
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.LPS, SystemVerilogParser.SEMI, SystemVerilogParser.LB, SystemVerilogParser.KASSERT, SystemVerilogParser.KASSIGN, SystemVerilogParser.KASSUME, SystemVerilogParser.KAUTOMATIC, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KCHECKER, SystemVerilogParser.KCLASS, SystemVerilogParser.KCLOCKING, SystemVerilogParser.KCONST, SystemVerilogParser.KCONSTRAINT, SystemVerilogParser.KCOVER, SystemVerilogParser.KCOVERGROUP, SystemVerilogParser.KDEFAULT, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KEXPORT, SystemVerilogParser.KFINAL, SystemVerilogParser.KFUNCTION, SystemVerilogParser.KGENVAR, SystemVerilogParser.KGLOBAL, SystemVerilogParser.KIMPORT, SystemVerilogParser.KINITIAL, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KINTERCONNECT, SystemVerilogParser.KLET, SystemVerilogParser.KLOCALPARAM, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNETTYPE, SystemVerilogParser.KPARAMETER, SystemVerilogParser.KPROPERTY, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KRESTRICT, SystemVerilogParser.KSEQUENCE, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTATIC, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KSUPPLY0, SystemVerilogParser.KSUPPLY1, SystemVerilogParser.KTASK, SystemVerilogParser.KTIME, SystemVerilogParser.KTRI, SystemVerilogParser.KTRI0, SystemVerilogParser.KTRI1, SystemVerilogParser.KTRIAND, SystemVerilogParser.KTRIOR, SystemVerilogParser.KTRIREG, SystemVerilogParser.KTYPE, SystemVerilogParser.KTYPEDEF, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KUWIRE, SystemVerilogParser.KVAR, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.KWAND, SystemVerilogParser.KWIRE, SystemVerilogParser.KWOR, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2280
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 2277
                    self.attribute_instance()
                    self.state = 2282
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2288
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,180,self._ctx)
                if la_ == 1:
                    self.state = 2283
                    self.continuous_assign()
                    pass

                elif la_ == 2:
                    self.state = 2284
                    self.module_or_generate_item_declaration()
                    pass

                elif la_ == 3:
                    self.state = 2285
                    self.initial_construct()
                    pass

                elif la_ == 4:
                    self.state = 2286
                    self.final_construct()
                    pass

                elif la_ == 5:
                    self.state = 2287
                    self.concurrent_assertion_item()
                    pass


                pass
            elif token in [SystemVerilogParser.KTIMEPRECISION, SystemVerilogParser.KTIMEUNIT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2290
                self.timeunits_declaration()
                pass
            elif token in [SystemVerilogParser.DERROR, SystemVerilogParser.DFATAL, SystemVerilogParser.DINFO, SystemVerilogParser.DWARNING, SystemVerilogParser.KCASE, SystemVerilogParser.KFOR, SystemVerilogParser.KGENERATE, SystemVerilogParser.KIF]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2291
                self.program_generate_item()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Program_generate_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def loop_generate_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Loop_generate_constructContext,0)


        def conditional_generate_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Conditional_generate_constructContext,0)


        def generate_region(self):
            return self.getTypedRuleContext(SystemVerilogParser.Generate_regionContext,0)


        def elaboration_system_task(self):
            return self.getTypedRuleContext(SystemVerilogParser.Elaboration_system_taskContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_program_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProgram_generate_item" ):
                listener.enterProgram_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProgram_generate_item" ):
                listener.exitProgram_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProgram_generate_item" ):
                return visitor.visitProgram_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def program_generate_item(self):

        localctx = SystemVerilogParser.Program_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 128, self.RULE_program_generate_item)
        try:
            self.state = 2298
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KFOR]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2294
                self.loop_generate_construct()
                pass
            elif token in [SystemVerilogParser.KCASE, SystemVerilogParser.KIF]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2295
                self.conditional_generate_construct()
                pass
            elif token in [SystemVerilogParser.KGENERATE]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2296
                self.generate_region()
                pass
            elif token in [SystemVerilogParser.DERROR, SystemVerilogParser.DFATAL, SystemVerilogParser.DINFO, SystemVerilogParser.DWARNING]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2297
                self.elaboration_system_task()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def checker_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Checker_port_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Checker_port_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_port_list" ):
                listener.enterChecker_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_port_list" ):
                listener.exitChecker_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_port_list" ):
                return visitor.visitChecker_port_list(self)
            else:
                return visitor.visitChildren(self)




    def checker_port_list(self):

        localctx = SystemVerilogParser.Checker_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 130, self.RULE_checker_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2300
            self.checker_port_item()
            self.state = 2305
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 2301
                self.match(SystemVerilogParser.COMMA)
                self.state = 2302
                self.checker_port_item()
                self.state = 2307
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_port_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def property_formal_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_formal_typeContext,0)


        def formal_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Formal_port_identifierContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def checker_port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_port_directionContext,0)


        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def property_actual_arg(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_actual_argContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_port_item" ):
                listener.enterChecker_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_port_item" ):
                listener.exitChecker_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_port_item" ):
                return visitor.visitChecker_port_item(self)
            else:
                return visitor.visitChildren(self)




    def checker_port_item(self):

        localctx = SystemVerilogParser.Checker_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 132, self.RULE_checker_port_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2311
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 2308
                self.attribute_instance()
                self.state = 2313
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2315
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KINPUT or _la==SystemVerilogParser.KOUTPUT:
                self.state = 2314
                self.checker_port_direction()


            self.state = 2317
            self.property_formal_type()
            self.state = 2318
            self.formal_port_identifier()
            self.state = 2322
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 2319
                self.variable_dimension()
                self.state = 2324
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2327
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 2325
                self.match(SystemVerilogParser.EQ)
                self.state = 2326
                self.property_actual_arg()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_port_directionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINPUT(self):
            return self.getToken(SystemVerilogParser.KINPUT, 0)

        def KOUTPUT(self):
            return self.getToken(SystemVerilogParser.KOUTPUT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_port_direction

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_port_direction" ):
                listener.enterChecker_port_direction(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_port_direction" ):
                listener.exitChecker_port_direction(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_port_direction" ):
                return visitor.visitChecker_port_direction(self)
            else:
                return visitor.visitChildren(self)




    def checker_port_direction(self):

        localctx = SystemVerilogParser.Checker_port_directionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 134, self.RULE_checker_port_direction)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2329
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KINPUT or _la==SystemVerilogParser.KOUTPUT):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_or_generate_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def checker_or_generate_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_or_generate_item_declarationContext,0)


        def initial_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Initial_constructContext,0)


        def always_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Always_constructContext,0)


        def final_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Final_constructContext,0)


        def assertion_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assertion_itemContext,0)


        def continuous_assign(self):
            return self.getTypedRuleContext(SystemVerilogParser.Continuous_assignContext,0)


        def checker_generate_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_generate_itemContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_or_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_or_generate_item" ):
                listener.enterChecker_or_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_or_generate_item" ):
                listener.exitChecker_or_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_or_generate_item" ):
                return visitor.visitChecker_or_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def checker_or_generate_item(self):

        localctx = SystemVerilogParser.Checker_or_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 136, self.RULE_checker_or_generate_item)
        try:
            self.state = 2338
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,188,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2331
                self.checker_or_generate_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2332
                self.initial_construct()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2333
                self.always_construct()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2334
                self.final_construct()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2335
                self.assertion_item()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2336
                self.continuous_assign()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2337
                self.checker_generate_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_or_generate_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_declarationContext,0)


        def KRAND(self):
            return self.getToken(SystemVerilogParser.KRAND, 0)

        def function_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_declarationContext,0)


        def checker_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_declarationContext,0)


        def assertion_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assertion_item_declarationContext,0)


        def covergroup_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_declarationContext,0)


        def genvar_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_declarationContext,0)


        def clocking_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_declarationContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def KCLOCKING(self):
            return self.getToken(SystemVerilogParser.KCLOCKING, 0)

        def clocking_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_identifierContext,0)


        def KDISABLE(self):
            return self.getToken(SystemVerilogParser.KDISABLE, 0)

        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def expression_or_dist(self):
            return self.getTypedRuleContext(SystemVerilogParser.Expression_or_distContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_or_generate_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_or_generate_item_declaration" ):
                listener.enterChecker_or_generate_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_or_generate_item_declaration" ):
                listener.exitChecker_or_generate_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_or_generate_item_declaration" ):
                return visitor.visitChecker_or_generate_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def checker_or_generate_item_declaration(self):

        localctx = SystemVerilogParser.Checker_or_generate_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 138, self.RULE_checker_or_generate_item_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2361
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,192,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2341
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KRAND:
                    self.state = 2340
                    self.match(SystemVerilogParser.KRAND)


                self.state = 2343
                self.data_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2344
                self.function_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2345
                self.checker_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2346
                self.assertion_item_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2347
                self.covergroup_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2348
                self.genvar_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2349
                self.clocking_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2358
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KDEFAULT:
                    self.state = 2350
                    self.match(SystemVerilogParser.KDEFAULT)
                    self.state = 2356
                    self._errHandler.sync(self)
                    token = self._input.LA(1)
                    if token in [SystemVerilogParser.KCLOCKING]:
                        self.state = 2351
                        self.match(SystemVerilogParser.KCLOCKING)
                        self.state = 2352
                        self.clocking_identifier()
                        pass
                    elif token in [SystemVerilogParser.KDISABLE]:
                        self.state = 2353
                        self.match(SystemVerilogParser.KDISABLE)
                        self.state = 2354
                        self.match(SystemVerilogParser.KIFF)
                        self.state = 2355
                        self.expression_or_dist()
                        pass
                    else:
                        raise NoViableAltException(self)



                self.state = 2360
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_generate_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def loop_generate_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Loop_generate_constructContext,0)


        def conditional_generate_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Conditional_generate_constructContext,0)


        def generate_region(self):
            return self.getTypedRuleContext(SystemVerilogParser.Generate_regionContext,0)


        def elaboration_system_task(self):
            return self.getTypedRuleContext(SystemVerilogParser.Elaboration_system_taskContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_generate_item" ):
                listener.enterChecker_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_generate_item" ):
                listener.exitChecker_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_generate_item" ):
                return visitor.visitChecker_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def checker_generate_item(self):

        localctx = SystemVerilogParser.Checker_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 140, self.RULE_checker_generate_item)
        try:
            self.state = 2367
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KFOR]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2363
                self.loop_generate_construct()
                pass
            elif token in [SystemVerilogParser.KCASE, SystemVerilogParser.KIF]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2364
                self.conditional_generate_construct()
                pass
            elif token in [SystemVerilogParser.KGENERATE]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2365
                self.generate_region()
                pass
            elif token in [SystemVerilogParser.DERROR, SystemVerilogParser.DFATAL, SystemVerilogParser.DINFO, SystemVerilogParser.DWARNING]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2366
                self.elaboration_system_task()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def class_property(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_propertyContext,0)


        def class_method(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_methodContext,0)


        def class_constraint(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_constraintContext,0)


        def class_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_declarationContext,0)


        def covergroup_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def local_parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Local_parameter_declarationContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_item" ):
                listener.enterClass_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_item" ):
                listener.exitClass_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_item" ):
                return visitor.visitClass_item(self)
            else:
                return visitor.visitChildren(self)




    def class_item(self):

        localctx = SystemVerilogParser.Class_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 142, self.RULE_class_item)
        self._la = 0 # Token type
        try:
            self.state = 2387
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.LPS, SystemVerilogParser.LB, SystemVerilogParser.KAUTOMATIC, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KCLASS, SystemVerilogParser.KCONST, SystemVerilogParser.KCONSTRAINT, SystemVerilogParser.KCOVERGROUP, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KEXTERN, SystemVerilogParser.KFUNCTION, SystemVerilogParser.KIMPORT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNETTYPE, SystemVerilogParser.KPROTECTED, SystemVerilogParser.KPURE, SystemVerilogParser.KRAND, SystemVerilogParser.KRANDC, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTATIC, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTASK, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KTYPEDEF, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KVAR, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2372
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 2369
                    self.attribute_instance()
                    self.state = 2374
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2380
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,195,self._ctx)
                if la_ == 1:
                    self.state = 2375
                    self.class_property()
                    pass

                elif la_ == 2:
                    self.state = 2376
                    self.class_method()
                    pass

                elif la_ == 3:
                    self.state = 2377
                    self.class_constraint()
                    pass

                elif la_ == 4:
                    self.state = 2378
                    self.class_declaration()
                    pass

                elif la_ == 5:
                    self.state = 2379
                    self.covergroup_declaration()
                    pass


                pass
            elif token in [SystemVerilogParser.SEMI, SystemVerilogParser.KLOCALPARAM, SystemVerilogParser.KPARAMETER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2384
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KLOCALPARAM]:
                    self.state = 2382
                    self.local_parameter_declaration()
                    pass
                elif token in [SystemVerilogParser.KPARAMETER]:
                    self.state = 2383
                    self.parameter_declaration()
                    pass
                elif token in [SystemVerilogParser.SEMI]:
                    pass
                else:
                    pass
                self.state = 2386
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_propertyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_declarationContext,0)


        def property_qualifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Property_qualifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Property_qualifierContext,i)


        def KCONST(self):
            return self.getToken(SystemVerilogParser.KCONST, 0)

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def const_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Const_identifierContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def class_item_qualifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Class_item_qualifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Class_item_qualifierContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_property

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_property" ):
                listener.enterClass_property(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_property" ):
                listener.exitClass_property(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_property" ):
                return visitor.visitClass_property(self)
            else:
                return visitor.visitChildren(self)




    def class_property(self):

        localctx = SystemVerilogParser.Class_propertyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 144, self.RULE_class_property)
        self._la = 0 # Token type
        try:
            self.state = 2411
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,201,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2392
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,198,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 2389
                        self.property_qualifier() 
                    self.state = 2394
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,198,self._ctx)

                self.state = 2395
                self.data_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2396
                self.match(SystemVerilogParser.KCONST)
                self.state = 2400
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.KLOCAL or _la==SystemVerilogParser.KPROTECTED or _la==SystemVerilogParser.KSTATIC:
                    self.state = 2397
                    self.class_item_qualifier()
                    self.state = 2402
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2403
                self.data_type()
                self.state = 2404
                self.const_identifier()
                self.state = 2407
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 2405
                    self.match(SystemVerilogParser.EQ)
                    self.state = 2406
                    self.constant_expression(0)


                self.state = 2409
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_methodContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_declarationContext,0)


        def function_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_declarationContext,0)


        def class_constructor_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_constructor_declarationContext,0)


        def method_qualifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Method_qualifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Method_qualifierContext,i)


        def KPURE(self):
            return self.getToken(SystemVerilogParser.KPURE, 0)

        def KVIRTUAL(self):
            return self.getToken(SystemVerilogParser.KVIRTUAL, 0)

        def method_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_prototypeContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def class_item_qualifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Class_item_qualifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Class_item_qualifierContext,i)


        def KEXTERN(self):
            return self.getToken(SystemVerilogParser.KEXTERN, 0)

        def class_constructor_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_constructor_prototypeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_method

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_method" ):
                listener.enterClass_method(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_method" ):
                listener.exitClass_method(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_method" ):
                return visitor.visitClass_method(self)
            else:
                return visitor.visitChildren(self)




    def class_method(self):

        localctx = SystemVerilogParser.Class_methodContext(self, self._ctx, self.state)
        self.enterRule(localctx, 146, self.RULE_class_method)
        self._la = 0 # Token type
        try:
            self.state = 2448
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,207,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2416
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KPROTECTED - 207)) | (1 << (SystemVerilogParser.KPURE - 207)))) != 0) or _la==SystemVerilogParser.KSTATIC or _la==SystemVerilogParser.KVIRTUAL:
                    self.state = 2413
                    self.method_qualifier()
                    self.state = 2418
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2422
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,203,self._ctx)
                if la_ == 1:
                    self.state = 2419
                    self.task_declaration()
                    pass

                elif la_ == 2:
                    self.state = 2420
                    self.function_declaration()
                    pass

                elif la_ == 3:
                    self.state = 2421
                    self.class_constructor_declaration()
                    pass


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2424
                self.match(SystemVerilogParser.KPURE)
                self.state = 2425
                self.match(SystemVerilogParser.KVIRTUAL)
                self.state = 2429
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.KLOCAL or _la==SystemVerilogParser.KPROTECTED or _la==SystemVerilogParser.KSTATIC:
                    self.state = 2426
                    self.class_item_qualifier()
                    self.state = 2431
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2432
                self.method_prototype()
                self.state = 2433
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2435
                self.match(SystemVerilogParser.KEXTERN)
                self.state = 2439
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KPROTECTED - 207)) | (1 << (SystemVerilogParser.KPURE - 207)))) != 0) or _la==SystemVerilogParser.KSTATIC or _la==SystemVerilogParser.KVIRTUAL:
                    self.state = 2436
                    self.method_qualifier()
                    self.state = 2441
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2446
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,206,self._ctx)
                if la_ == 1:
                    self.state = 2442
                    self.method_prototype()
                    self.state = 2443
                    self.match(SystemVerilogParser.SEMI)
                    pass

                elif la_ == 2:
                    self.state = 2445
                    self.class_constructor_prototype()
                    pass


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_constructor_prototypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KFUNCTION(self):
            return self.getToken(SystemVerilogParser.KFUNCTION, 0)

        def KNEW(self):
            return self.getToken(SystemVerilogParser.KNEW, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def tf_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_constructor_prototype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_constructor_prototype" ):
                listener.enterClass_constructor_prototype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_constructor_prototype" ):
                listener.exitClass_constructor_prototype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_constructor_prototype" ):
                return visitor.visitClass_constructor_prototype(self)
            else:
                return visitor.visitChildren(self)




    def class_constructor_prototype(self):

        localctx = SystemVerilogParser.Class_constructor_prototypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 148, self.RULE_class_constructor_prototype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2450
            self.match(SystemVerilogParser.KFUNCTION)
            self.state = 2451
            self.match(SystemVerilogParser.KNEW)
            self.state = 2457
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 2452
                self.match(SystemVerilogParser.LP)
                self.state = 2454
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,208,self._ctx)
                if la_ == 1:
                    self.state = 2453
                    self.tf_port_list()


                self.state = 2456
                self.match(SystemVerilogParser.RP)


            self.state = 2459
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_constraintContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constraint_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_prototypeContext,0)


        def constraint_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_constraint

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_constraint" ):
                listener.enterClass_constraint(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_constraint" ):
                listener.exitClass_constraint(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_constraint" ):
                return visitor.visitClass_constraint(self)
            else:
                return visitor.visitChildren(self)




    def class_constraint(self):

        localctx = SystemVerilogParser.Class_constraintContext(self, self._ctx, self.state)
        self.enterRule(localctx, 150, self.RULE_class_constraint)
        try:
            self.state = 2463
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,210,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2461
                self.constraint_prototype()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2462
                self.constraint_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_item_qualifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSTATIC(self):
            return self.getToken(SystemVerilogParser.KSTATIC, 0)

        def KPROTECTED(self):
            return self.getToken(SystemVerilogParser.KPROTECTED, 0)

        def KLOCAL(self):
            return self.getToken(SystemVerilogParser.KLOCAL, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_item_qualifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_item_qualifier" ):
                listener.enterClass_item_qualifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_item_qualifier" ):
                listener.exitClass_item_qualifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_item_qualifier" ):
                return visitor.visitClass_item_qualifier(self)
            else:
                return visitor.visitChildren(self)




    def class_item_qualifier(self):

        localctx = SystemVerilogParser.Class_item_qualifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 152, self.RULE_class_item_qualifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2465
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KLOCAL or _la==SystemVerilogParser.KPROTECTED or _la==SystemVerilogParser.KSTATIC):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_qualifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def random_qualifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Random_qualifierContext,0)


        def class_item_qualifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_item_qualifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_qualifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_qualifier" ):
                listener.enterProperty_qualifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_qualifier" ):
                listener.exitProperty_qualifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_qualifier" ):
                return visitor.visitProperty_qualifier(self)
            else:
                return visitor.visitChildren(self)




    def property_qualifier(self):

        localctx = SystemVerilogParser.Property_qualifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 154, self.RULE_property_qualifier)
        try:
            self.state = 2469
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KRAND, SystemVerilogParser.KRANDC]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2467
                self.random_qualifier()
                pass
            elif token in [SystemVerilogParser.KLOCAL, SystemVerilogParser.KPROTECTED, SystemVerilogParser.KSTATIC]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2468
                self.class_item_qualifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Random_qualifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KRAND(self):
            return self.getToken(SystemVerilogParser.KRAND, 0)

        def KRANDC(self):
            return self.getToken(SystemVerilogParser.KRANDC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_random_qualifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRandom_qualifier" ):
                listener.enterRandom_qualifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRandom_qualifier" ):
                listener.exitRandom_qualifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRandom_qualifier" ):
                return visitor.visitRandom_qualifier(self)
            else:
                return visitor.visitChildren(self)




    def random_qualifier(self):

        localctx = SystemVerilogParser.Random_qualifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 156, self.RULE_random_qualifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2471
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KRAND or _la==SystemVerilogParser.KRANDC):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Method_qualifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KVIRTUAL(self):
            return self.getToken(SystemVerilogParser.KVIRTUAL, 0)

        def KPURE(self):
            return self.getToken(SystemVerilogParser.KPURE, 0)

        def class_item_qualifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_item_qualifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_method_qualifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMethod_qualifier" ):
                listener.enterMethod_qualifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMethod_qualifier" ):
                listener.exitMethod_qualifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMethod_qualifier" ):
                return visitor.visitMethod_qualifier(self)
            else:
                return visitor.visitChildren(self)




    def method_qualifier(self):

        localctx = SystemVerilogParser.Method_qualifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 158, self.RULE_method_qualifier)
        self._la = 0 # Token type
        try:
            self.state = 2478
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KPURE, SystemVerilogParser.KVIRTUAL]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2474
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KPURE:
                    self.state = 2473
                    self.match(SystemVerilogParser.KPURE)


                self.state = 2476
                self.match(SystemVerilogParser.KVIRTUAL)
                pass
            elif token in [SystemVerilogParser.KLOCAL, SystemVerilogParser.KPROTECTED, SystemVerilogParser.KSTATIC]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2477
                self.class_item_qualifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Method_prototypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_prototypeContext,0)


        def function_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_prototypeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_method_prototype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMethod_prototype" ):
                listener.enterMethod_prototype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMethod_prototype" ):
                listener.exitMethod_prototype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMethod_prototype" ):
                return visitor.visitMethod_prototype(self)
            else:
                return visitor.visitChildren(self)




    def method_prototype(self):

        localctx = SystemVerilogParser.Method_prototypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 160, self.RULE_method_prototype)
        try:
            self.state = 2482
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KTASK]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2480
                self.task_prototype()
                pass
            elif token in [SystemVerilogParser.KFUNCTION]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2481
                self.function_prototype()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_constructor_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KFUNCTION(self):
            return self.getToken(SystemVerilogParser.KFUNCTION, 0)

        def KNEW(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.KNEW)
            else:
                return self.getToken(SystemVerilogParser.KNEW, i)

        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def KENDFUNCTION(self):
            return self.getToken(SystemVerilogParser.KENDFUNCTION, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Block_item_declarationContext,i)


        def KSUPER(self):
            return self.getToken(SystemVerilogParser.KSUPER, 0)

        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def function_statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Function_statement_or_nullContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Function_statement_or_nullContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def tf_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_listContext,0)


        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_constructor_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_constructor_declaration" ):
                listener.enterClass_constructor_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_constructor_declaration" ):
                listener.exitClass_constructor_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_constructor_declaration" ):
                return visitor.visitClass_constructor_declaration(self)
            else:
                return visitor.visitChildren(self)




    def class_constructor_declaration(self):

        localctx = SystemVerilogParser.Class_constructor_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 162, self.RULE_class_constructor_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2484
            self.match(SystemVerilogParser.KFUNCTION)
            self.state = 2486
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.DUNIT or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 2485
                self.class_scope()


            self.state = 2488
            self.match(SystemVerilogParser.KNEW)
            self.state = 2494
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 2489
                self.match(SystemVerilogParser.LP)
                self.state = 2491
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,216,self._ctx)
                if la_ == 1:
                    self.state = 2490
                    self.tf_port_list()


                self.state = 2493
                self.match(SystemVerilogParser.RP)


            self.state = 2496
            self.match(SystemVerilogParser.SEMI)
            self.state = 2500
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,218,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 2497
                    self.block_item_declaration() 
                self.state = 2502
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,218,self._ctx)

            self.state = 2513
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,220,self._ctx)
            if la_ == 1:
                self.state = 2503
                self.match(SystemVerilogParser.KSUPER)
                self.state = 2504
                self.match(SystemVerilogParser.DOT)
                self.state = 2505
                self.match(SystemVerilogParser.KNEW)
                self.state = 2510
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 2506
                    self.match(SystemVerilogParser.LP)
                    self.state = 2507
                    self.list_of_arguments()
                    self.state = 2508
                    self.match(SystemVerilogParser.RP)


                self.state = 2512
                self.match(SystemVerilogParser.SEMI)


            self.state = 2518
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.P) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or ((((_la - 69)) & ~0x3f) == 0 and ((1 << (_la - 69)) & ((1 << (SystemVerilogParser.PLUSPLUS - 69)) | (1 << (SystemVerilogParser.ARROW - 69)) | (1 << (SystemVerilogParser.MINUSGTGT - 69)) | (1 << (SystemVerilogParser.KASSERT - 69)) | (1 << (SystemVerilogParser.KASSIGN - 69)) | (1 << (SystemVerilogParser.KASSUME - 69)) | (1 << (SystemVerilogParser.KBEGIN - 69)) | (1 << (SystemVerilogParser.KBREAK - 69)) | (1 << (SystemVerilogParser.KBYTE - 69)) | (1 << (SystemVerilogParser.KCASE - 69)) | (1 << (SystemVerilogParser.KCASEX - 69)) | (1 << (SystemVerilogParser.KCASEZ - 69)) | (1 << (SystemVerilogParser.KCONTINUE - 69)) | (1 << (SystemVerilogParser.KCOVER - 69)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (SystemVerilogParser.KDEASSIGN - 133)) | (1 << (SystemVerilogParser.KDISABLE - 133)) | (1 << (SystemVerilogParser.KDO - 133)) | (1 << (SystemVerilogParser.KEXPECT - 133)) | (1 << (SystemVerilogParser.KFOR - 133)) | (1 << (SystemVerilogParser.KFORCE - 133)) | (1 << (SystemVerilogParser.KFOREACH - 133)) | (1 << (SystemVerilogParser.KFOREVER - 133)) | (1 << (SystemVerilogParser.KFORK - 133)) | (1 << (SystemVerilogParser.KIF - 133)) | (1 << (SystemVerilogParser.KINT - 133)) | (1 << (SystemVerilogParser.KINTEGER - 133)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPRIORITY - 207)) | (1 << (SystemVerilogParser.KRANDCASE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KRANDSEQUENCE - 207)) | (1 << (SystemVerilogParser.KRELEASE - 207)) | (1 << (SystemVerilogParser.KREPEAT - 207)) | (1 << (SystemVerilogParser.KRESTRICT - 207)) | (1 << (SystemVerilogParser.KRETURN - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNIQUE0 - 276)) | (1 << (SystemVerilogParser.KVOID - 276)) | (1 << (SystemVerilogParser.KWAIT - 276)) | (1 << (SystemVerilogParser.KWAIT_ORDER - 276)) | (1 << (SystemVerilogParser.KWHILE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 2515
                self.function_statement_or_null()
                self.state = 2520
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2521
            self.match(SystemVerilogParser.KENDFUNCTION)
            self.state = 2524
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 2522
                self.match(SystemVerilogParser.COLON)
                self.state = 2523
                self.match(SystemVerilogParser.KNEW)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCONSTRAINT(self):
            return self.getToken(SystemVerilogParser.KCONSTRAINT, 0)

        def constraint_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_identifierContext,0)


        def constraint_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_blockContext,0)


        def KSTATIC(self):
            return self.getToken(SystemVerilogParser.KSTATIC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_declaration" ):
                listener.enterConstraint_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_declaration" ):
                listener.exitConstraint_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_declaration" ):
                return visitor.visitConstraint_declaration(self)
            else:
                return visitor.visitChildren(self)




    def constraint_declaration(self):

        localctx = SystemVerilogParser.Constraint_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 164, self.RULE_constraint_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2527
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KSTATIC:
                self.state = 2526
                self.match(SystemVerilogParser.KSTATIC)


            self.state = 2529
            self.match(SystemVerilogParser.KCONSTRAINT)
            self.state = 2530
            self.constraint_identifier()
            self.state = 2531
            self.constraint_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def constraint_block_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constraint_block_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constraint_block_itemContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_block" ):
                listener.enterConstraint_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_block" ):
                listener.exitConstraint_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_block" ):
                return visitor.visitConstraint_block(self)
            else:
                return visitor.visitChildren(self)




    def constraint_block(self):

        localctx = SystemVerilogParser.Constraint_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 166, self.RULE_constraint_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2533
            self.match(SystemVerilogParser.LC)
            self.state = 2537
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (SystemVerilogParser.KDISABLE - 137)) | (1 << (SystemVerilogParser.KFOREACH - 137)) | (1 << (SystemVerilogParser.KIF - 137)) | (1 << (SystemVerilogParser.KINT - 137)) | (1 << (SystemVerilogParser.KINTEGER - 137)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSOFT - 276)) | (1 << (SystemVerilogParser.KSOLVE - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 2534
                self.constraint_block_item()
                self.state = 2539
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2540
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_block_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSOLVE(self):
            return self.getToken(SystemVerilogParser.KSOLVE, 0)

        def solve_before_list(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Solve_before_listContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Solve_before_listContext,i)


        def KBEFORE(self):
            return self.getToken(SystemVerilogParser.KBEFORE, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def constraint_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_block_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_block_item" ):
                listener.enterConstraint_block_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_block_item" ):
                listener.exitConstraint_block_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_block_item" ):
                return visitor.visitConstraint_block_item(self)
            else:
                return visitor.visitChildren(self)




    def constraint_block_item(self):

        localctx = SystemVerilogParser.Constraint_block_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 168, self.RULE_constraint_block_item)
        try:
            self.state = 2549
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KSOLVE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2542
                self.match(SystemVerilogParser.KSOLVE)
                self.state = 2543
                self.solve_before_list()
                self.state = 2544
                self.match(SystemVerilogParser.KBEFORE)
                self.state = 2545
                self.solve_before_list()
                self.state = 2546
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KDISABLE, SystemVerilogParser.KFOREACH, SystemVerilogParser.KIF, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSOFT, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNIQUE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2548
                self.constraint_expression()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Solve_before_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constraint_primary(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constraint_primaryContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constraint_primaryContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_solve_before_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSolve_before_list" ):
                listener.enterSolve_before_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSolve_before_list" ):
                listener.exitSolve_before_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSolve_before_list" ):
                return visitor.visitSolve_before_list(self)
            else:
                return visitor.visitChildren(self)




    def solve_before_list(self):

        localctx = SystemVerilogParser.Solve_before_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 170, self.RULE_solve_before_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2551
            self.constraint_primary()
            self.state = 2556
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 2552
                self.match(SystemVerilogParser.COMMA)
                self.state = 2553
                self.constraint_primary()
                self.state = 2558
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_primaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def select_(self):
            return self.getTypedRuleContext(SystemVerilogParser.Select_Context,0)


        def implicit_class_handle(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_class_handleContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_primary" ):
                listener.enterConstraint_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_primary" ):
                listener.exitConstraint_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_primary" ):
                return visitor.visitConstraint_primary(self)
            else:
                return visitor.visitChildren(self)




    def constraint_primary(self):

        localctx = SystemVerilogParser.Constraint_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 172, self.RULE_constraint_primary)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2563
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,227,self._ctx)
            if la_ == 1:
                self.state = 2559
                self.implicit_class_handle()
                self.state = 2560
                self.match(SystemVerilogParser.DOT)

            elif la_ == 2:
                self.state = 2562
                self.class_scope()


            self.state = 2565
            self.hierarchical_identifier()
            self.state = 2566
            self.select_()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression_or_dist(self):
            return self.getTypedRuleContext(SystemVerilogParser.Expression_or_distContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KSOFT(self):
            return self.getToken(SystemVerilogParser.KSOFT, 0)

        def uniqueness_constraint(self):
            return self.getTypedRuleContext(SystemVerilogParser.Uniqueness_constraintContext,0)


        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def ARROW(self):
            return self.getToken(SystemVerilogParser.ARROW, 0)

        def constraint_set(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constraint_setContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constraint_setContext,i)


        def KIF(self):
            return self.getToken(SystemVerilogParser.KIF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def KELSE(self):
            return self.getToken(SystemVerilogParser.KELSE, 0)

        def KFOREACH(self):
            return self.getToken(SystemVerilogParser.KFOREACH, 0)

        def ps_or_hierarchical_array_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_or_hierarchical_array_identifierContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def loop_variables(self):
            return self.getTypedRuleContext(SystemVerilogParser.Loop_variablesContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def KDISABLE(self):
            return self.getToken(SystemVerilogParser.KDISABLE, 0)

        def constraint_primary(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_primaryContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_expression" ):
                listener.enterConstraint_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_expression" ):
                listener.exitConstraint_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_expression" ):
                return visitor.visitConstraint_expression(self)
            else:
                return visitor.visitChildren(self)




    def constraint_expression(self):

        localctx = SystemVerilogParser.Constraint_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 174, self.RULE_constraint_expression)
        self._la = 0 # Token type
        try:
            self.state = 2604
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,230,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2569
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KSOFT:
                    self.state = 2568
                    self.match(SystemVerilogParser.KSOFT)


                self.state = 2571
                self.expression_or_dist()
                self.state = 2572
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2574
                self.uniqueness_constraint()
                self.state = 2575
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2577
                self.expression(0)
                self.state = 2578
                self.match(SystemVerilogParser.ARROW)
                self.state = 2579
                self.constraint_set()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2581
                self.match(SystemVerilogParser.KIF)
                self.state = 2582
                self.match(SystemVerilogParser.LP)
                self.state = 2583
                self.expression(0)
                self.state = 2584
                self.match(SystemVerilogParser.RP)
                self.state = 2585
                self.constraint_set()
                self.state = 2588
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,229,self._ctx)
                if la_ == 1:
                    self.state = 2586
                    self.match(SystemVerilogParser.KELSE)
                    self.state = 2587
                    self.constraint_set()


                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2590
                self.match(SystemVerilogParser.KFOREACH)
                self.state = 2591
                self.match(SystemVerilogParser.LP)
                self.state = 2592
                self.ps_or_hierarchical_array_identifier()
                self.state = 2593
                self.match(SystemVerilogParser.LB)
                self.state = 2594
                self.loop_variables()
                self.state = 2595
                self.match(SystemVerilogParser.RB)
                self.state = 2596
                self.match(SystemVerilogParser.RP)
                self.state = 2597
                self.constraint_set()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2599
                self.match(SystemVerilogParser.KDISABLE)
                self.state = 2600
                self.match(SystemVerilogParser.KSOFT)
                self.state = 2601
                self.constraint_primary()
                self.state = 2602
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Uniqueness_constraintContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KUNIQUE(self):
            return self.getToken(SystemVerilogParser.KUNIQUE, 0)

        def open_range_list(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Open_range_listContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Open_range_listContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_uniqueness_constraint

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUniqueness_constraint" ):
                listener.enterUniqueness_constraint(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUniqueness_constraint" ):
                listener.exitUniqueness_constraint(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUniqueness_constraint" ):
                return visitor.visitUniqueness_constraint(self)
            else:
                return visitor.visitChildren(self)




    def uniqueness_constraint(self):

        localctx = SystemVerilogParser.Uniqueness_constraintContext(self, self._ctx, self.state)
        self.enterRule(localctx, 176, self.RULE_uniqueness_constraint)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2606
            self.match(SystemVerilogParser.KUNIQUE)
            self.state = 2610
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LB) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 2607
                self.open_range_list()
                self.state = 2612
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_setContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constraint_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constraint_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constraint_expressionContext,i)


        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_set

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_set" ):
                listener.enterConstraint_set(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_set" ):
                listener.exitConstraint_set(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_set" ):
                return visitor.visitConstraint_set(self)
            else:
                return visitor.visitChildren(self)




    def constraint_set(self):

        localctx = SystemVerilogParser.Constraint_setContext(self, self._ctx, self.state)
        self.enterRule(localctx, 178, self.RULE_constraint_set)
        self._la = 0 # Token type
        try:
            self.state = 2622
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,233,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2613
                self.constraint_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2614
                self.match(SystemVerilogParser.LC)
                self.state = 2618
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 137)) & ~0x3f) == 0 and ((1 << (_la - 137)) & ((1 << (SystemVerilogParser.KDISABLE - 137)) | (1 << (SystemVerilogParser.KFOREACH - 137)) | (1 << (SystemVerilogParser.KIF - 137)) | (1 << (SystemVerilogParser.KINT - 137)) | (1 << (SystemVerilogParser.KINTEGER - 137)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSOFT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 2615
                    self.constraint_expression()
                    self.state = 2620
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2621
                self.match(SystemVerilogParser.RC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dist_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def dist_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Dist_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Dist_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dist_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDist_list" ):
                listener.enterDist_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDist_list" ):
                listener.exitDist_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDist_list" ):
                return visitor.visitDist_list(self)
            else:
                return visitor.visitChildren(self)




    def dist_list(self):

        localctx = SystemVerilogParser.Dist_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 180, self.RULE_dist_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2624
            self.dist_item()
            self.state = 2629
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 2625
                self.match(SystemVerilogParser.COMMA)
                self.state = 2626
                self.dist_item()
                self.state = 2631
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dist_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def value_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Value_rangeContext,0)


        def dist_weight(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dist_weightContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dist_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDist_item" ):
                listener.enterDist_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDist_item" ):
                listener.exitDist_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDist_item" ):
                return visitor.visitDist_item(self)
            else:
                return visitor.visitChildren(self)




    def dist_item(self):

        localctx = SystemVerilogParser.Dist_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 182, self.RULE_dist_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2632
            self.value_range()
            self.state = 2634
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLONSLASH or _la==SystemVerilogParser.COLONEQ:
                self.state = 2633
                self.dist_weight()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dist_weightContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def COLONEQ(self):
            return self.getToken(SystemVerilogParser.COLONEQ, 0)

        def COLONSLASH(self):
            return self.getToken(SystemVerilogParser.COLONSLASH, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dist_weight

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDist_weight" ):
                listener.enterDist_weight(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDist_weight" ):
                listener.exitDist_weight(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDist_weight" ):
                return visitor.visitDist_weight(self)
            else:
                return visitor.visitChildren(self)




    def dist_weight(self):

        localctx = SystemVerilogParser.Dist_weightContext(self, self._ctx, self.state)
        self.enterRule(localctx, 184, self.RULE_dist_weight)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2636
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.COLONSLASH or _la==SystemVerilogParser.COLONEQ):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 2637
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_prototypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCONSTRAINT(self):
            return self.getToken(SystemVerilogParser.KCONSTRAINT, 0)

        def constraint_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_identifierContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def constraint_prototype_qualifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_prototype_qualifierContext,0)


        def KSTATIC(self):
            return self.getToken(SystemVerilogParser.KSTATIC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_prototype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_prototype" ):
                listener.enterConstraint_prototype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_prototype" ):
                listener.exitConstraint_prototype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_prototype" ):
                return visitor.visitConstraint_prototype(self)
            else:
                return visitor.visitChildren(self)




    def constraint_prototype(self):

        localctx = SystemVerilogParser.Constraint_prototypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 186, self.RULE_constraint_prototype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2640
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KEXTERN or _la==SystemVerilogParser.KPURE:
                self.state = 2639
                self.constraint_prototype_qualifier()


            self.state = 2643
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KSTATIC:
                self.state = 2642
                self.match(SystemVerilogParser.KSTATIC)


            self.state = 2645
            self.match(SystemVerilogParser.KCONSTRAINT)
            self.state = 2646
            self.constraint_identifier()
            self.state = 2647
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_prototype_qualifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KEXTERN(self):
            return self.getToken(SystemVerilogParser.KEXTERN, 0)

        def KPURE(self):
            return self.getToken(SystemVerilogParser.KPURE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_prototype_qualifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_prototype_qualifier" ):
                listener.enterConstraint_prototype_qualifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_prototype_qualifier" ):
                listener.exitConstraint_prototype_qualifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_prototype_qualifier" ):
                return visitor.visitConstraint_prototype_qualifier(self)
            else:
                return visitor.visitChildren(self)




    def constraint_prototype_qualifier(self):

        localctx = SystemVerilogParser.Constraint_prototype_qualifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 188, self.RULE_constraint_prototype_qualifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2649
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KEXTERN or _la==SystemVerilogParser.KPURE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Extern_constraint_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCONSTRAINT(self):
            return self.getToken(SystemVerilogParser.KCONSTRAINT, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def constraint_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_identifierContext,0)


        def constraint_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_blockContext,0)


        def KSTATIC(self):
            return self.getToken(SystemVerilogParser.KSTATIC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_extern_constraint_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExtern_constraint_declaration" ):
                listener.enterExtern_constraint_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExtern_constraint_declaration" ):
                listener.exitExtern_constraint_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExtern_constraint_declaration" ):
                return visitor.visitExtern_constraint_declaration(self)
            else:
                return visitor.visitChildren(self)




    def extern_constraint_declaration(self):

        localctx = SystemVerilogParser.Extern_constraint_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 190, self.RULE_extern_constraint_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2652
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KSTATIC:
                self.state = 2651
                self.match(SystemVerilogParser.KSTATIC)


            self.state = 2654
            self.match(SystemVerilogParser.KCONSTRAINT)
            self.state = 2655
            self.class_scope()
            self.state = 2656
            self.constraint_identifier()
            self.state = 2657
            self.constraint_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Identifier_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.IdentifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_identifier_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIdentifier_list" ):
                listener.enterIdentifier_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIdentifier_list" ):
                listener.exitIdentifier_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIdentifier_list" ):
                return visitor.visitIdentifier_list(self)
            else:
                return visitor.visitChildren(self)




    def identifier_list(self):

        localctx = SystemVerilogParser.Identifier_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 192, self.RULE_identifier_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2659
            self.identifier()
            self.state = 2664
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 2660
                self.match(SystemVerilogParser.COMMA)
                self.state = 2661
                self.identifier()
                self.state = 2666
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def package_or_generate_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_or_generate_item_declarationContext,0)


        def anonymous_program(self):
            return self.getTypedRuleContext(SystemVerilogParser.Anonymous_programContext,0)


        def package_export_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_export_declarationContext,0)


        def timeunits_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Timeunits_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_package_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_item" ):
                listener.enterPackage_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_item" ):
                listener.exitPackage_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_item" ):
                return visitor.visitPackage_item(self)
            else:
                return visitor.visitChildren(self)




    def package_item(self):

        localctx = SystemVerilogParser.Package_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 194, self.RULE_package_item)
        try:
            self.state = 2671
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,240,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2667
                self.package_or_generate_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2668
                self.anonymous_program()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2669
                self.package_export_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2670
                self.timeunits_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_or_generate_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_declarationContext,0)


        def data_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_declarationContext,0)


        def task_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_declarationContext,0)


        def function_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_declarationContext,0)


        def checker_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_declarationContext,0)


        def dpi_import_export(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dpi_import_exportContext,0)


        def extern_constraint_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Extern_constraint_declarationContext,0)


        def class_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_declarationContext,0)


        def class_constructor_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_constructor_declarationContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def local_parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Local_parameter_declarationContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_declarationContext,0)


        def covergroup_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_declarationContext,0)


        def assertion_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assertion_item_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_package_or_generate_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_or_generate_item_declaration" ):
                listener.enterPackage_or_generate_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_or_generate_item_declaration" ):
                listener.exitPackage_or_generate_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_or_generate_item_declaration" ):
                return visitor.visitPackage_or_generate_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def package_or_generate_item_declaration(self):

        localctx = SystemVerilogParser.Package_or_generate_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 196, self.RULE_package_or_generate_item_declaration)
        try:
            self.state = 2689
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,242,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2673
                self.net_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2674
                self.data_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2675
                self.task_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2676
                self.function_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2677
                self.checker_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2678
                self.dpi_import_export()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2679
                self.extern_constraint_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2680
                self.class_declaration()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 2681
                self.class_constructor_declaration()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 2684
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KLOCALPARAM]:
                    self.state = 2682
                    self.local_parameter_declaration()
                    pass
                elif token in [SystemVerilogParser.KPARAMETER]:
                    self.state = 2683
                    self.parameter_declaration()
                    pass
                elif token in [SystemVerilogParser.SEMI]:
                    pass
                else:
                    pass
                self.state = 2686
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 2687
                self.covergroup_declaration()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 2688
                self.assertion_item_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Anonymous_programContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPROGRAM(self):
            return self.getToken(SystemVerilogParser.KPROGRAM, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KENDPROGRAM(self):
            return self.getToken(SystemVerilogParser.KENDPROGRAM, 0)

        def anonymous_program_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Anonymous_program_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Anonymous_program_itemContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_anonymous_program

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAnonymous_program" ):
                listener.enterAnonymous_program(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAnonymous_program" ):
                listener.exitAnonymous_program(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAnonymous_program" ):
                return visitor.visitAnonymous_program(self)
            else:
                return visitor.visitChildren(self)




    def anonymous_program(self):

        localctx = SystemVerilogParser.Anonymous_programContext(self, self._ctx, self.state)
        self.enterRule(localctx, 198, self.RULE_anonymous_program)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2691
            self.match(SystemVerilogParser.KPROGRAM)
            self.state = 2692
            self.match(SystemVerilogParser.SEMI)
            self.state = 2696
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.SEMI or ((((_la - 121)) & ~0x3f) == 0 and ((1 << (_la - 121)) & ((1 << (SystemVerilogParser.KCLASS - 121)) | (1 << (SystemVerilogParser.KCOVERGROUP - 121)) | (1 << (SystemVerilogParser.KFUNCTION - 121)))) != 0) or _la==SystemVerilogParser.KTASK or _la==SystemVerilogParser.KVIRTUAL:
                self.state = 2693
                self.anonymous_program_item()
                self.state = 2698
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2699
            self.match(SystemVerilogParser.KENDPROGRAM)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Anonymous_program_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_declarationContext,0)


        def function_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_declarationContext,0)


        def class_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_declarationContext,0)


        def covergroup_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_declarationContext,0)


        def class_constructor_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_constructor_declarationContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_anonymous_program_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAnonymous_program_item" ):
                listener.enterAnonymous_program_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAnonymous_program_item" ):
                listener.exitAnonymous_program_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAnonymous_program_item" ):
                return visitor.visitAnonymous_program_item(self)
            else:
                return visitor.visitChildren(self)




    def anonymous_program_item(self):

        localctx = SystemVerilogParser.Anonymous_program_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 200, self.RULE_anonymous_program_item)
        try:
            self.state = 2707
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,244,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2701
                self.task_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2702
                self.function_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2703
                self.class_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2704
                self.covergroup_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2705
                self.class_constructor_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2706
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Local_parameter_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KLOCALPARAM(self):
            return self.getToken(SystemVerilogParser.KLOCALPARAM, 0)

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def list_of_param_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_param_assignmentsContext,0)


        def KTYPE(self):
            return self.getToken(SystemVerilogParser.KTYPE, 0)

        def list_of_type_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_type_assignmentsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_local_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLocal_parameter_declaration" ):
                listener.enterLocal_parameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLocal_parameter_declaration" ):
                listener.exitLocal_parameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLocal_parameter_declaration" ):
                return visitor.visitLocal_parameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def local_parameter_declaration(self):

        localctx = SystemVerilogParser.Local_parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 202, self.RULE_local_parameter_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2709
            self.match(SystemVerilogParser.KLOCALPARAM)
            self.state = 2715
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,245,self._ctx)
            if la_ == 1:
                self.state = 2710
                self.data_type_or_implicit()
                self.state = 2711
                self.list_of_param_assignments()
                pass

            elif la_ == 2:
                self.state = 2713
                self.match(SystemVerilogParser.KTYPE)
                self.state = 2714
                self.list_of_type_assignments()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPARAMETER(self):
            return self.getToken(SystemVerilogParser.KPARAMETER, 0)

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def list_of_param_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_param_assignmentsContext,0)


        def KTYPE(self):
            return self.getToken(SystemVerilogParser.KTYPE, 0)

        def list_of_type_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_type_assignmentsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_declaration" ):
                listener.enterParameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_declaration" ):
                listener.exitParameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_declaration" ):
                return visitor.visitParameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def parameter_declaration(self):

        localctx = SystemVerilogParser.Parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 204, self.RULE_parameter_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2717
            self.match(SystemVerilogParser.KPARAMETER)
            self.state = 2723
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,246,self._ctx)
            if la_ == 1:
                self.state = 2718
                self.data_type_or_implicit()
                self.state = 2719
                self.list_of_param_assignments()
                pass

            elif la_ == 2:
                self.state = 2721
                self.match(SystemVerilogParser.KTYPE)
                self.state = 2722
                self.list_of_type_assignments()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specparam_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSPECPARAM(self):
            return self.getToken(SystemVerilogParser.KSPECPARAM, 0)

        def list_of_specparam_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_specparam_assignmentsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def packed_dimension(self):
            return self.getTypedRuleContext(SystemVerilogParser.Packed_dimensionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_specparam_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_declaration" ):
                listener.enterSpecparam_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_declaration" ):
                listener.exitSpecparam_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_declaration" ):
                return visitor.visitSpecparam_declaration(self)
            else:
                return visitor.visitChildren(self)




    def specparam_declaration(self):

        localctx = SystemVerilogParser.Specparam_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 206, self.RULE_specparam_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2725
            self.match(SystemVerilogParser.KSPECPARAM)
            self.state = 2727
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LB:
                self.state = 2726
                self.packed_dimension()


            self.state = 2729
            self.list_of_specparam_assignments()
            self.state = 2730
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINOUT(self):
            return self.getToken(SystemVerilogParser.KINOUT, 0)

        def net_port_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_port_typeContext,0)


        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_port_identifiersContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_inout_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_declaration" ):
                listener.enterInout_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_declaration" ):
                listener.exitInout_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_declaration" ):
                return visitor.visitInout_declaration(self)
            else:
                return visitor.visitChildren(self)




    def inout_declaration(self):

        localctx = SystemVerilogParser.Inout_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 208, self.RULE_inout_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2732
            self.match(SystemVerilogParser.KINOUT)
            self.state = 2733
            self.net_port_type()
            self.state = 2734
            self.list_of_port_identifiers()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINPUT(self):
            return self.getToken(SystemVerilogParser.KINPUT, 0)

        def net_port_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_port_typeContext,0)


        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_port_identifiersContext,0)


        def variable_port_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_port_typeContext,0)


        def list_of_variable_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_variable_identifiersContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_input_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_declaration" ):
                listener.enterInput_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_declaration" ):
                listener.exitInput_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_declaration" ):
                return visitor.visitInput_declaration(self)
            else:
                return visitor.visitChildren(self)




    def input_declaration(self):

        localctx = SystemVerilogParser.Input_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 210, self.RULE_input_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2736
            self.match(SystemVerilogParser.KINPUT)
            self.state = 2743
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,248,self._ctx)
            if la_ == 1:
                self.state = 2737
                self.net_port_type()
                self.state = 2738
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.state = 2740
                self.variable_port_type()
                self.state = 2741
                self.list_of_variable_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KOUTPUT(self):
            return self.getToken(SystemVerilogParser.KOUTPUT, 0)

        def net_port_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_port_typeContext,0)


        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_port_identifiersContext,0)


        def variable_port_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_port_typeContext,0)


        def list_of_variable_port_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_variable_port_identifiersContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_output_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_declaration" ):
                listener.enterOutput_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_declaration" ):
                listener.exitOutput_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_declaration" ):
                return visitor.visitOutput_declaration(self)
            else:
                return visitor.visitChildren(self)




    def output_declaration(self):

        localctx = SystemVerilogParser.Output_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 212, self.RULE_output_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2745
            self.match(SystemVerilogParser.KOUTPUT)
            self.state = 2752
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,249,self._ctx)
            if la_ == 1:
                self.state = 2746
                self.net_port_type()
                self.state = 2747
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.state = 2749
                self.variable_port_type()
                self.state = 2750
                self.list_of_variable_port_identifiers()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_port_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def list_of_interface_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_interface_identifiersContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def modport_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Modport_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_port_declaration" ):
                listener.enterInterface_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_port_declaration" ):
                listener.exitInterface_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_port_declaration" ):
                return visitor.visitInterface_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def interface_port_declaration(self):

        localctx = SystemVerilogParser.Interface_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 214, self.RULE_interface_port_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2754
            self.interface_identifier()
            self.state = 2757
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.DOT:
                self.state = 2755
                self.match(SystemVerilogParser.DOT)
                self.state = 2756
                self.modport_identifier()


            self.state = 2759
            self.list_of_interface_identifiers()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ref_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KREF(self):
            return self.getToken(SystemVerilogParser.KREF, 0)

        def variable_port_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_port_typeContext,0)


        def list_of_variable_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_variable_identifiersContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ref_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRef_declaration" ):
                listener.enterRef_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRef_declaration" ):
                listener.exitRef_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRef_declaration" ):
                return visitor.visitRef_declaration(self)
            else:
                return visitor.visitChildren(self)




    def ref_declaration(self):

        localctx = SystemVerilogParser.Ref_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 216, self.RULE_ref_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2761
            self.match(SystemVerilogParser.KREF)
            self.state = 2762
            self.variable_port_type()
            self.state = 2763
            self.list_of_variable_identifiers()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Data_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def list_of_variable_decl_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_variable_decl_assignmentsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KCONST(self):
            return self.getToken(SystemVerilogParser.KCONST, 0)

        def KVAR(self):
            return self.getToken(SystemVerilogParser.KVAR, 0)

        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def type_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_declarationContext,0)


        def package_import_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_import_declarationContext,0)


        def net_type_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_type_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_data_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterData_declaration" ):
                listener.enterData_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitData_declaration" ):
                listener.exitData_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitData_declaration" ):
                return visitor.visitData_declaration(self)
            else:
                return visitor.visitChildren(self)




    def data_declaration(self):

        localctx = SystemVerilogParser.Data_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 218, self.RULE_data_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2781
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.LB, SystemVerilogParser.KAUTOMATIC, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KCONST, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTATIC, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KVAR, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2766
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KCONST:
                    self.state = 2765
                    self.match(SystemVerilogParser.KCONST)


                self.state = 2769
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KVAR:
                    self.state = 2768
                    self.match(SystemVerilogParser.KVAR)


                self.state = 2772
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                    self.state = 2771
                    self.lifetime()


                self.state = 2774
                self.data_type_or_implicit()
                self.state = 2775
                self.list_of_variable_decl_assignments()
                self.state = 2776
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KTYPEDEF]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2778
                self.type_declaration()
                pass
            elif token in [SystemVerilogParser.KIMPORT]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2779
                self.package_import_declaration()
                pass
            elif token in [SystemVerilogParser.KNETTYPE]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2780
                self.net_type_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_import_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KIMPORT(self):
            return self.getToken(SystemVerilogParser.KIMPORT, 0)

        def package_import_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_import_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_import_itemContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_package_import_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_import_declaration" ):
                listener.enterPackage_import_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_import_declaration" ):
                listener.exitPackage_import_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_import_declaration" ):
                return visitor.visitPackage_import_declaration(self)
            else:
                return visitor.visitChildren(self)




    def package_import_declaration(self):

        localctx = SystemVerilogParser.Package_import_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 220, self.RULE_package_import_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2783
            self.match(SystemVerilogParser.KIMPORT)
            self.state = 2784
            self.package_import_item()
            self.state = 2789
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 2785
                self.match(SystemVerilogParser.COMMA)
                self.state = 2786
                self.package_import_item()
                self.state = 2791
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 2792
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_import_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def package_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_identifierContext,0)


        def COLONCOLON(self):
            return self.getToken(SystemVerilogParser.COLONCOLON, 0)

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def STAR(self):
            return self.getToken(SystemVerilogParser.STAR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_package_import_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_import_item" ):
                listener.enterPackage_import_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_import_item" ):
                listener.exitPackage_import_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_import_item" ):
                return visitor.visitPackage_import_item(self)
            else:
                return visitor.visitChildren(self)




    def package_import_item(self):

        localctx = SystemVerilogParser.Package_import_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 222, self.RULE_package_import_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2794
            self.package_identifier()
            self.state = 2795
            self.match(SystemVerilogParser.COLONCOLON)
            self.state = 2798
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 2796
                self.identifier()
                pass
            elif token in [SystemVerilogParser.STAR]:
                self.state = 2797
                self.match(SystemVerilogParser.STAR)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_export_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KEXPORT(self):
            return self.getToken(SystemVerilogParser.KEXPORT, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def SCCS(self):
            return self.getToken(SystemVerilogParser.SCCS, 0)

        def package_import_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Package_import_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Package_import_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_package_export_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_export_declaration" ):
                listener.enterPackage_export_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_export_declaration" ):
                listener.exitPackage_export_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_export_declaration" ):
                return visitor.visitPackage_export_declaration(self)
            else:
                return visitor.visitChildren(self)




    def package_export_declaration(self):

        localctx = SystemVerilogParser.Package_export_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 224, self.RULE_package_export_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2800
            self.match(SystemVerilogParser.KEXPORT)
            self.state = 2810
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SCCS]:
                self.state = 2801
                self.match(SystemVerilogParser.SCCS)
                pass
            elif token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 2802
                self.package_import_item()
                self.state = 2807
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 2803
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 2804
                    self.package_import_item()
                    self.state = 2809
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            else:
                raise NoViableAltException(self)

            self.state = 2812
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KGENVAR(self):
            return self.getToken(SystemVerilogParser.KGENVAR, 0)

        def list_of_genvar_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_genvar_identifiersContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_genvar_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_declaration" ):
                listener.enterGenvar_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_declaration" ):
                listener.exitGenvar_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_declaration" ):
                return visitor.visitGenvar_declaration(self)
            else:
                return visitor.visitChildren(self)




    def genvar_declaration(self):

        localctx = SystemVerilogParser.Genvar_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 226, self.RULE_genvar_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2814
            self.match(SystemVerilogParser.KGENVAR)
            self.state = 2815
            self.list_of_genvar_identifiers()
            self.state = 2816
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_typeContext,0)


        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def list_of_net_decl_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_net_decl_assignmentsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def drive_strength(self):
            return self.getTypedRuleContext(SystemVerilogParser.Drive_strengthContext,0)


        def charge_strength(self):
            return self.getTypedRuleContext(SystemVerilogParser.Charge_strengthContext,0)


        def delay3(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay3Context,0)


        def KVECTORED(self):
            return self.getToken(SystemVerilogParser.KVECTORED, 0)

        def KSCALARED(self):
            return self.getToken(SystemVerilogParser.KSCALARED, 0)

        def net_type_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_type_identifierContext,0)


        def delay_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_controlContext,0)


        def KINTERCONNECT(self):
            return self.getToken(SystemVerilogParser.KINTERCONNECT, 0)

        def implicit_data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_data_typeContext,0)


        def net_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Net_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Net_identifierContext,i)


        def P(self):
            return self.getToken(SystemVerilogParser.P, 0)

        def delay_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_valueContext,0)


        def unpacked_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Unpacked_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Unpacked_dimensionContext,i)


        def COMMA(self):
            return self.getToken(SystemVerilogParser.COMMA, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_declaration" ):
                listener.enterNet_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_declaration" ):
                listener.exitNet_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_declaration" ):
                return visitor.visitNet_declaration(self)
            else:
                return visitor.visitChildren(self)




    def net_declaration(self):

        localctx = SystemVerilogParser.Net_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 228, self.RULE_net_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2865
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KSUPPLY0, SystemVerilogParser.KSUPPLY1, SystemVerilogParser.KTRI, SystemVerilogParser.KTRI0, SystemVerilogParser.KTRI1, SystemVerilogParser.KTRIAND, SystemVerilogParser.KTRIOR, SystemVerilogParser.KTRIREG, SystemVerilogParser.KUWIRE, SystemVerilogParser.KWAND, SystemVerilogParser.KWIRE, SystemVerilogParser.KWOR]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2818
                self.net_type()
                self.state = 2821
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,259,self._ctx)
                if la_ == 1:
                    self.state = 2819
                    self.drive_strength()

                elif la_ == 2:
                    self.state = 2820
                    self.charge_strength()


                self.state = 2824
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KSCALARED or _la==SystemVerilogParser.KVECTORED:
                    self.state = 2823
                    _la = self._input.LA(1)
                    if not(_la==SystemVerilogParser.KSCALARED or _la==SystemVerilogParser.KVECTORED):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 2826
                self.data_type_or_implicit()
                self.state = 2828
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 2827
                    self.delay3()


                self.state = 2830
                self.list_of_net_decl_assignments()
                self.state = 2831
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2833
                self.net_type_identifier()
                self.state = 2835
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 2834
                    self.delay_control()


                self.state = 2837
                self.list_of_net_decl_assignments()
                self.state = 2838
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KINTERCONNECT]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2840
                self.match(SystemVerilogParser.KINTERCONNECT)
                self.state = 2841
                self.implicit_data_type()
                self.state = 2844
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 2842
                    self.match(SystemVerilogParser.P)
                    self.state = 2843
                    self.delay_value()


                self.state = 2846
                self.net_identifier()
                self.state = 2850
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 2847
                    self.unpacked_dimension()
                    self.state = 2852
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2861
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COMMA:
                    self.state = 2853
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 2854
                    self.net_identifier()
                    self.state = 2858
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    while _la==SystemVerilogParser.LB:
                        self.state = 2855
                        self.unpacked_dimension()
                        self.state = 2860
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)



                self.state = 2863
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Type_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KTYPEDEF(self):
            return self.getToken(SystemVerilogParser.KTYPEDEF, 0)

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def type_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Type_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Type_identifierContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def interface_instance_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_instance_identifierContext,0)


        def constant_bit_select(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_bit_selectContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def KENUM(self):
            return self.getToken(SystemVerilogParser.KENUM, 0)

        def KSTRUCT(self):
            return self.getToken(SystemVerilogParser.KSTRUCT, 0)

        def KUNION(self):
            return self.getToken(SystemVerilogParser.KUNION, 0)

        def KCLASS(self):
            return self.getToken(SystemVerilogParser.KCLASS, 0)

        def KINTERFACE(self):
            return self.getToken(SystemVerilogParser.KINTERFACE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_type_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterType_declaration" ):
                listener.enterType_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitType_declaration" ):
                listener.exitType_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitType_declaration" ):
                return visitor.visitType_declaration(self)
            else:
                return visitor.visitChildren(self)




    def type_declaration(self):

        localctx = SystemVerilogParser.Type_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 230, self.RULE_type_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2898
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,270,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2867
                self.match(SystemVerilogParser.KTYPEDEF)
                self.state = 2868
                self.data_type()
                self.state = 2869
                self.type_identifier()
                self.state = 2873
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 2870
                    self.variable_dimension()
                    self.state = 2875
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2876
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2878
                self.match(SystemVerilogParser.KTYPEDEF)
                self.state = 2879
                self.interface_instance_identifier()
                self.state = 2880
                self.constant_bit_select()
                self.state = 2881
                self.match(SystemVerilogParser.DOT)
                self.state = 2882
                self.type_identifier()
                self.state = 2883
                self.type_identifier()
                self.state = 2884
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2886
                self.match(SystemVerilogParser.KTYPEDEF)
                self.state = 2893
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KENUM]:
                    self.state = 2887
                    self.match(SystemVerilogParser.KENUM)
                    pass
                elif token in [SystemVerilogParser.KSTRUCT]:
                    self.state = 2888
                    self.match(SystemVerilogParser.KSTRUCT)
                    pass
                elif token in [SystemVerilogParser.KUNION]:
                    self.state = 2889
                    self.match(SystemVerilogParser.KUNION)
                    pass
                elif token in [SystemVerilogParser.KCLASS]:
                    self.state = 2890
                    self.match(SystemVerilogParser.KCLASS)
                    pass
                elif token in [SystemVerilogParser.KINTERFACE]:
                    self.state = 2891
                    self.match(SystemVerilogParser.KINTERFACE)
                    self.state = 2892
                    self.match(SystemVerilogParser.KCLASS)
                    pass
                elif token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                    pass
                else:
                    pass
                self.state = 2895
                self.type_identifier()
                self.state = 2896
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_type_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KNETTYPE(self):
            return self.getToken(SystemVerilogParser.KNETTYPE, 0)

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def net_type_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Net_type_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Net_type_identifierContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KWITH(self):
            return self.getToken(SystemVerilogParser.KWITH, 0)

        def tf_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_type_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_type_declaration" ):
                listener.enterNet_type_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_type_declaration" ):
                listener.exitNet_type_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_type_declaration" ):
                return visitor.visitNet_type_declaration(self)
            else:
                return visitor.visitChildren(self)




    def net_type_declaration(self):

        localctx = SystemVerilogParser.Net_type_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 232, self.RULE_net_type_declaration)
        self._la = 0 # Token type
        try:
            self.state = 2922
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,274,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2900
                self.match(SystemVerilogParser.KNETTYPE)
                self.state = 2901
                self.data_type()
                self.state = 2902
                self.net_type_identifier()
                self.state = 2909
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KWITH:
                    self.state = 2903
                    self.match(SystemVerilogParser.KWITH)
                    self.state = 2906
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,271,self._ctx)
                    if la_ == 1:
                        self.state = 2904
                        self.package_scope()

                    elif la_ == 2:
                        self.state = 2905
                        self.class_scope()


                    self.state = 2908
                    self.tf_identifier()


                self.state = 2911
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2913
                self.match(SystemVerilogParser.KNETTYPE)
                self.state = 2916
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,273,self._ctx)
                if la_ == 1:
                    self.state = 2914
                    self.package_scope()

                elif la_ == 2:
                    self.state = 2915
                    self.class_scope()


                self.state = 2918
                self.net_type_identifier()
                self.state = 2919
                self.net_type_identifier()
                self.state = 2920
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class LifetimeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSTATIC(self):
            return self.getToken(SystemVerilogParser.KSTATIC, 0)

        def KAUTOMATIC(self):
            return self.getToken(SystemVerilogParser.KAUTOMATIC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_lifetime

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLifetime" ):
                listener.enterLifetime(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLifetime" ):
                listener.exitLifetime(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLifetime" ):
                return visitor.visitLifetime(self)
            else:
                return visitor.visitChildren(self)




    def lifetime(self):

        localctx = SystemVerilogParser.LifetimeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 234, self.RULE_lifetime)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2924
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Casting_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def simple_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_typeContext,0)


        def constant_primary(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_primaryContext,0)


        def signing(self):
            return self.getTypedRuleContext(SystemVerilogParser.SigningContext,0)


        def KSTRING(self):
            return self.getToken(SystemVerilogParser.KSTRING, 0)

        def KCONST(self):
            return self.getToken(SystemVerilogParser.KCONST, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_casting_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCasting_type" ):
                listener.enterCasting_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCasting_type" ):
                listener.exitCasting_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCasting_type" ):
                return visitor.visitCasting_type(self)
            else:
                return visitor.visitChildren(self)




    def casting_type(self):

        localctx = SystemVerilogParser.Casting_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 236, self.RULE_casting_type)
        try:
            self.state = 2931
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,275,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2926
                self.simple_type()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2927
                self.constant_primary()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2928
                self.signing()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2929
                self.match(SystemVerilogParser.KSTRING)
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2930
                self.match(SystemVerilogParser.KCONST)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Data_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def integer_vector_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_vector_typeContext,0)


        def signing(self):
            return self.getTypedRuleContext(SystemVerilogParser.SigningContext,0)


        def packed_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Packed_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Packed_dimensionContext,i)


        def integer_atom_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_atom_typeContext,0)


        def non_integer_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Non_integer_typeContext,0)


        def struct_union(self):
            return self.getTypedRuleContext(SystemVerilogParser.Struct_unionContext,0)


        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def struct_union_member(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Struct_union_memberContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Struct_union_memberContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def KPACKED(self):
            return self.getToken(SystemVerilogParser.KPACKED, 0)

        def KENUM(self):
            return self.getToken(SystemVerilogParser.KENUM, 0)

        def enum_name_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Enum_name_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Enum_name_declarationContext,i)


        def enum_base_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Enum_base_typeContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def KSTRING(self):
            return self.getToken(SystemVerilogParser.KSTRING, 0)

        def KCHANDLE(self):
            return self.getToken(SystemVerilogParser.KCHANDLE, 0)

        def KVIRTUAL(self):
            return self.getToken(SystemVerilogParser.KVIRTUAL, 0)

        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def KINTERFACE(self):
            return self.getToken(SystemVerilogParser.KINTERFACE, 0)

        def parameter_value_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_value_assignmentContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def modport_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Modport_identifierContext,0)


        def type_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_identifierContext,0)


        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def class_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_typeContext,0)


        def KEVENT(self):
            return self.getToken(SystemVerilogParser.KEVENT, 0)

        def ps_covergroup_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_covergroup_identifierContext,0)


        def type_reference(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_referenceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_data_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterData_type" ):
                listener.enterData_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitData_type" ):
                listener.exitData_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitData_type" ):
                return visitor.visitData_type(self)
            else:
                return visitor.visitChildren(self)




    def data_type(self):

        localctx = SystemVerilogParser.Data_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 238, self.RULE_data_type)
        self._la = 0 # Token type
        try:
            self.state = 3019
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,291,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2933
                self.integer_vector_type()
                self.state = 2935
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KSIGNED or _la==SystemVerilogParser.KUNSIGNED:
                    self.state = 2934
                    self.signing()


                self.state = 2940
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 2937
                    self.packed_dimension()
                    self.state = 2942
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2943
                self.integer_atom_type()
                self.state = 2945
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KSIGNED or _la==SystemVerilogParser.KUNSIGNED:
                    self.state = 2944
                    self.signing()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2947
                self.non_integer_type()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2948
                self.struct_union()
                self.state = 2953
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KPACKED:
                    self.state = 2949
                    self.match(SystemVerilogParser.KPACKED)
                    self.state = 2951
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.KSIGNED or _la==SystemVerilogParser.KUNSIGNED:
                        self.state = 2950
                        self.signing()




                self.state = 2955
                self.match(SystemVerilogParser.LC)
                self.state = 2956
                self.struct_union_member()
                self.state = 2960
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.DUNIT or _la==SystemVerilogParser.LPS or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KRAND - 195)) | (1 << (SystemVerilogParser.KRANDC - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSTRUCT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNION - 276)) | (1 << (SystemVerilogParser.KVIRTUAL - 276)) | (1 << (SystemVerilogParser.KVOID - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 2957
                    self.struct_union_member()
                    self.state = 2962
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2963
                self.match(SystemVerilogParser.RC)
                self.state = 2967
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 2964
                    self.packed_dimension()
                    self.state = 2969
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2970
                self.match(SystemVerilogParser.KENUM)
                self.state = 2972
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KBIT or _la==SystemVerilogParser.KBYTE or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or _la==SystemVerilogParser.KSHORTINT or _la==SystemVerilogParser.KTIME or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 2971
                    self.enum_base_type()


                self.state = 2974
                self.match(SystemVerilogParser.LC)
                self.state = 2975
                self.enum_name_declaration()
                self.state = 2980
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 2976
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 2977
                    self.enum_name_declaration()
                    self.state = 2982
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2983
                self.match(SystemVerilogParser.RC)
                self.state = 2987
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 2984
                    self.packed_dimension()
                    self.state = 2989
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2990
                self.match(SystemVerilogParser.KSTRING)
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2991
                self.match(SystemVerilogParser.KCHANDLE)
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2992
                self.match(SystemVerilogParser.KVIRTUAL)
                self.state = 2994
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KINTERFACE:
                    self.state = 2993
                    self.match(SystemVerilogParser.KINTERFACE)


                self.state = 2996
                self.interface_identifier()
                self.state = 2998
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,287,self._ctx)
                if la_ == 1:
                    self.state = 2997
                    self.parameter_value_assignment()


                self.state = 3002
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.DOT:
                    self.state = 3000
                    self.match(SystemVerilogParser.DOT)
                    self.state = 3001
                    self.modport_identifier()


                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 3006
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,289,self._ctx)
                if la_ == 1:
                    self.state = 3004
                    self.class_scope()

                elif la_ == 2:
                    self.state = 3005
                    self.package_scope()


                self.state = 3008
                self.type_identifier()
                self.state = 3012
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3009
                    self.packed_dimension()
                    self.state = 3014
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 3015
                self.class_type()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 3016
                self.match(SystemVerilogParser.KEVENT)
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 3017
                self.ps_covergroup_identifier()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 3018
                self.type_reference()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Data_type_or_implicitContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def implicit_data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_data_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_data_type_or_implicit

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterData_type_or_implicit" ):
                listener.enterData_type_or_implicit(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitData_type_or_implicit" ):
                listener.exitData_type_or_implicit(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitData_type_or_implicit" ):
                return visitor.visitData_type_or_implicit(self)
            else:
                return visitor.visitChildren(self)




    def data_type_or_implicit(self):

        localctx = SystemVerilogParser.Data_type_or_implicitContext(self, self._ctx, self.state)
        self.enterRule(localctx, 240, self.RULE_data_type_or_implicit)
        try:
            self.state = 3023
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,292,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3021
                self.data_type()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3022
                self.implicit_data_type()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Implicit_data_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def signing(self):
            return self.getTypedRuleContext(SystemVerilogParser.SigningContext,0)


        def packed_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Packed_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Packed_dimensionContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_implicit_data_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterImplicit_data_type" ):
                listener.enterImplicit_data_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitImplicit_data_type" ):
                listener.exitImplicit_data_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitImplicit_data_type" ):
                return visitor.visitImplicit_data_type(self)
            else:
                return visitor.visitChildren(self)




    def implicit_data_type(self):

        localctx = SystemVerilogParser.Implicit_data_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 242, self.RULE_implicit_data_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3026
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KSIGNED or _la==SystemVerilogParser.KUNSIGNED:
                self.state = 3025
                self.signing()


            self.state = 3031
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 3028
                self.packed_dimension()
                self.state = 3033
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enum_base_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def integer_atom_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_atom_typeContext,0)


        def signing(self):
            return self.getTypedRuleContext(SystemVerilogParser.SigningContext,0)


        def integer_vector_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_vector_typeContext,0)


        def packed_dimension(self):
            return self.getTypedRuleContext(SystemVerilogParser.Packed_dimensionContext,0)


        def type_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_enum_base_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnum_base_type" ):
                listener.enterEnum_base_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnum_base_type" ):
                listener.exitEnum_base_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnum_base_type" ):
                return visitor.visitEnum_base_type(self)
            else:
                return visitor.visitChildren(self)




    def enum_base_type(self):

        localctx = SystemVerilogParser.Enum_base_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 244, self.RULE_enum_base_type)
        self._la = 0 # Token type
        try:
            self.state = 3049
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KBYTE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLONGINT, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KTIME]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3034
                self.integer_atom_type()
                self.state = 3036
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KSIGNED or _la==SystemVerilogParser.KUNSIGNED:
                    self.state = 3035
                    self.signing()


                pass
            elif token in [SystemVerilogParser.KBIT, SystemVerilogParser.KLOGIC, SystemVerilogParser.KREG]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3038
                self.integer_vector_type()
                self.state = 3040
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KSIGNED or _la==SystemVerilogParser.KUNSIGNED:
                    self.state = 3039
                    self.signing()


                self.state = 3043
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LB:
                    self.state = 3042
                    self.packed_dimension()


                pass
            elif token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3045
                self.type_identifier()
                self.state = 3047
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LB:
                    self.state = 3046
                    self.packed_dimension()


                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enum_name_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def enum_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Enum_identifierContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def DECIMAL_NUMBER(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DECIMAL_NUMBER)
            else:
                return self.getToken(SystemVerilogParser.DECIMAL_NUMBER, i)

        def UNSIGNED_NUMBER(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.UNSIGNED_NUMBER)
            else:
                return self.getToken(SystemVerilogParser.UNSIGNED_NUMBER, i)

        def OCTAL_NUMBER(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.OCTAL_NUMBER)
            else:
                return self.getToken(SystemVerilogParser.OCTAL_NUMBER, i)

        def BINARY_NUMBER(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.BINARY_NUMBER)
            else:
                return self.getToken(SystemVerilogParser.BINARY_NUMBER, i)

        def HEX_NUMBER(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.HEX_NUMBER)
            else:
                return self.getToken(SystemVerilogParser.HEX_NUMBER, i)

        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_enum_name_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnum_name_declaration" ):
                listener.enterEnum_name_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnum_name_declaration" ):
                listener.exitEnum_name_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnum_name_declaration" ):
                return visitor.visitEnum_name_declaration(self)
            else:
                return visitor.visitChildren(self)




    def enum_name_declaration(self):

        localctx = SystemVerilogParser.Enum_name_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 246, self.RULE_enum_name_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3051
            self.enum_identifier()
            self.state = 3059
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LB:
                self.state = 3052
                self.match(SystemVerilogParser.LB)
                self.state = 3053
                _la = self._input.LA(1)
                if not(((((_la - 346)) & ~0x3f) == 0 and ((1 << (_la - 346)) & ((1 << (SystemVerilogParser.DECIMAL_NUMBER - 346)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 346)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 346)) | (1 << (SystemVerilogParser.HEX_NUMBER - 346)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 346)))) != 0)):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 3056
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 3054
                    self.match(SystemVerilogParser.COLON)
                    self.state = 3055
                    _la = self._input.LA(1)
                    if not(((((_la - 346)) & ~0x3f) == 0 and ((1 << (_la - 346)) & ((1 << (SystemVerilogParser.DECIMAL_NUMBER - 346)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 346)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 346)) | (1 << (SystemVerilogParser.HEX_NUMBER - 346)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 346)))) != 0)):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()


                self.state = 3058
                self.match(SystemVerilogParser.RB)


            self.state = 3063
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 3061
                self.match(SystemVerilogParser.EQ)
                self.state = 3062
                self.constant_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_scopeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def class_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_typeContext,0)


        def COLONCOLON(self):
            return self.getToken(SystemVerilogParser.COLONCOLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_scope

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_scope" ):
                listener.enterClass_scope(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_scope" ):
                listener.exitClass_scope(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_scope" ):
                return visitor.visitClass_scope(self)
            else:
                return visitor.visitChildren(self)




    def class_scope(self):

        localctx = SystemVerilogParser.Class_scopeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 248, self.RULE_class_scope)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3065
            self.class_type()
            self.state = 3066
            self.match(SystemVerilogParser.COLONCOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ps_class_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_class_identifierContext,0)


        def parameter_value_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Parameter_value_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Parameter_value_assignmentContext,i)


        def COLONCOLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLONCOLON)
            else:
                return self.getToken(SystemVerilogParser.COLONCOLON, i)

        def class_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Class_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Class_identifierContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_type" ):
                listener.enterClass_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_type" ):
                listener.exitClass_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_type" ):
                return visitor.visitClass_type(self)
            else:
                return visitor.visitChildren(self)




    def class_type(self):

        localctx = SystemVerilogParser.Class_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 250, self.RULE_class_type)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3068
            self.ps_class_identifier()
            self.state = 3070
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,303,self._ctx)
            if la_ == 1:
                self.state = 3069
                self.parameter_value_assignment()


            self.state = 3079
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,305,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3072
                    self.match(SystemVerilogParser.COLONCOLON)
                    self.state = 3073
                    self.class_identifier()
                    self.state = 3075
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,304,self._ctx)
                    if la_ == 1:
                        self.state = 3074
                        self.parameter_value_assignment()

             
                self.state = 3081
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,305,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Integer_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def integer_vector_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_vector_typeContext,0)


        def integer_atom_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_atom_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_integer_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInteger_type" ):
                listener.enterInteger_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInteger_type" ):
                listener.exitInteger_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInteger_type" ):
                return visitor.visitInteger_type(self)
            else:
                return visitor.visitChildren(self)




    def integer_type(self):

        localctx = SystemVerilogParser.Integer_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 252, self.RULE_integer_type)
        try:
            self.state = 3084
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KBIT, SystemVerilogParser.KLOGIC, SystemVerilogParser.KREG]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3082
                self.integer_vector_type()
                pass
            elif token in [SystemVerilogParser.KBYTE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLONGINT, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KTIME]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3083
                self.integer_atom_type()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Integer_atom_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KBYTE(self):
            return self.getToken(SystemVerilogParser.KBYTE, 0)

        def KSHORTINT(self):
            return self.getToken(SystemVerilogParser.KSHORTINT, 0)

        def KINT(self):
            return self.getToken(SystemVerilogParser.KINT, 0)

        def KLONGINT(self):
            return self.getToken(SystemVerilogParser.KLONGINT, 0)

        def KINTEGER(self):
            return self.getToken(SystemVerilogParser.KINTEGER, 0)

        def KTIME(self):
            return self.getToken(SystemVerilogParser.KTIME, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_integer_atom_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInteger_atom_type" ):
                listener.enterInteger_atom_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInteger_atom_type" ):
                listener.exitInteger_atom_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInteger_atom_type" ):
                return visitor.visitInteger_atom_type(self)
            else:
                return visitor.visitChildren(self)




    def integer_atom_type(self):

        localctx = SystemVerilogParser.Integer_atom_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 254, self.RULE_integer_atom_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3086
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KBYTE or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)))) != 0) or _la==SystemVerilogParser.KSHORTINT or _la==SystemVerilogParser.KTIME):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Integer_vector_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KBIT(self):
            return self.getToken(SystemVerilogParser.KBIT, 0)

        def KLOGIC(self):
            return self.getToken(SystemVerilogParser.KLOGIC, 0)

        def KREG(self):
            return self.getToken(SystemVerilogParser.KREG, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_integer_vector_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInteger_vector_type" ):
                listener.enterInteger_vector_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInteger_vector_type" ):
                listener.exitInteger_vector_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInteger_vector_type" ):
                return visitor.visitInteger_vector_type(self)
            else:
                return visitor.visitChildren(self)




    def integer_vector_type(self):

        localctx = SystemVerilogParser.Integer_vector_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 256, self.RULE_integer_vector_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3088
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KBIT or _la==SystemVerilogParser.KLOGIC or _la==SystemVerilogParser.KREG):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Non_integer_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSHORTREAL(self):
            return self.getToken(SystemVerilogParser.KSHORTREAL, 0)

        def KREAL(self):
            return self.getToken(SystemVerilogParser.KREAL, 0)

        def KREALTIME(self):
            return self.getToken(SystemVerilogParser.KREALTIME, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_non_integer_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNon_integer_type" ):
                listener.enterNon_integer_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNon_integer_type" ):
                listener.exitNon_integer_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNon_integer_type" ):
                return visitor.visitNon_integer_type(self)
            else:
                return visitor.visitChildren(self)




    def non_integer_type(self):

        localctx = SystemVerilogParser.Non_integer_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 258, self.RULE_non_integer_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3090
            _la = self._input.LA(1)
            if not(((((_la - 255)) & ~0x3f) == 0 and ((1 << (_la - 255)) & ((1 << (SystemVerilogParser.KREAL - 255)) | (1 << (SystemVerilogParser.KREALTIME - 255)) | (1 << (SystemVerilogParser.KSHORTREAL - 255)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSUPPLY0(self):
            return self.getToken(SystemVerilogParser.KSUPPLY0, 0)

        def KSUPPLY1(self):
            return self.getToken(SystemVerilogParser.KSUPPLY1, 0)

        def KTRI(self):
            return self.getToken(SystemVerilogParser.KTRI, 0)

        def KTRIAND(self):
            return self.getToken(SystemVerilogParser.KTRIAND, 0)

        def KTRIOR(self):
            return self.getToken(SystemVerilogParser.KTRIOR, 0)

        def KTRIREG(self):
            return self.getToken(SystemVerilogParser.KTRIREG, 0)

        def KTRI0(self):
            return self.getToken(SystemVerilogParser.KTRI0, 0)

        def KTRI1(self):
            return self.getToken(SystemVerilogParser.KTRI1, 0)

        def KUWIRE(self):
            return self.getToken(SystemVerilogParser.KUWIRE, 0)

        def KWIRE(self):
            return self.getToken(SystemVerilogParser.KWIRE, 0)

        def KWAND(self):
            return self.getToken(SystemVerilogParser.KWAND, 0)

        def KWOR(self):
            return self.getToken(SystemVerilogParser.KWOR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_type" ):
                listener.enterNet_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_type" ):
                listener.exitNet_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_type" ):
                return visitor.visitNet_type(self)
            else:
                return visitor.visitChildren(self)




    def net_type(self):

        localctx = SystemVerilogParser.Net_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 260, self.RULE_net_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3092
            _la = self._input.LA(1)
            if not(((((_la - 293)) & ~0x3f) == 0 and ((1 << (_la - 293)) & ((1 << (SystemVerilogParser.KSUPPLY0 - 293)) | (1 << (SystemVerilogParser.KSUPPLY1 - 293)) | (1 << (SystemVerilogParser.KTRI - 293)) | (1 << (SystemVerilogParser.KTRI0 - 293)) | (1 << (SystemVerilogParser.KTRI1 - 293)) | (1 << (SystemVerilogParser.KTRIAND - 293)) | (1 << (SystemVerilogParser.KTRIOR - 293)) | (1 << (SystemVerilogParser.KTRIREG - 293)) | (1 << (SystemVerilogParser.KUWIRE - 293)) | (1 << (SystemVerilogParser.KWAND - 293)) | (1 << (SystemVerilogParser.KWIRE - 293)) | (1 << (SystemVerilogParser.KWOR - 293)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_port_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def net_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_typeContext,0)


        def net_type_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_type_identifierContext,0)


        def KINTERCONNECT(self):
            return self.getToken(SystemVerilogParser.KINTERCONNECT, 0)

        def implicit_data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_data_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_port_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_port_type" ):
                listener.enterNet_port_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_port_type" ):
                listener.exitNet_port_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_port_type" ):
                return visitor.visitNet_port_type(self)
            else:
                return visitor.visitChildren(self)




    def net_port_type(self):

        localctx = SystemVerilogParser.Net_port_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 262, self.RULE_net_port_type)
        self._la = 0 # Token type
        try:
            self.state = 3101
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,308,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3095
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 293)) & ~0x3f) == 0 and ((1 << (_la - 293)) & ((1 << (SystemVerilogParser.KSUPPLY0 - 293)) | (1 << (SystemVerilogParser.KSUPPLY1 - 293)) | (1 << (SystemVerilogParser.KTRI - 293)) | (1 << (SystemVerilogParser.KTRI0 - 293)) | (1 << (SystemVerilogParser.KTRI1 - 293)) | (1 << (SystemVerilogParser.KTRIAND - 293)) | (1 << (SystemVerilogParser.KTRIOR - 293)) | (1 << (SystemVerilogParser.KTRIREG - 293)) | (1 << (SystemVerilogParser.KUWIRE - 293)) | (1 << (SystemVerilogParser.KWAND - 293)) | (1 << (SystemVerilogParser.KWIRE - 293)) | (1 << (SystemVerilogParser.KWOR - 293)))) != 0):
                    self.state = 3094
                    self.net_type()


                self.state = 3097
                self.data_type_or_implicit()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3098
                self.net_type_identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3099
                self.match(SystemVerilogParser.KINTERCONNECT)
                self.state = 3100
                self.implicit_data_type()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_port_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def var_data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Var_data_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_variable_port_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_port_type" ):
                listener.enterVariable_port_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_port_type" ):
                listener.exitVariable_port_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_port_type" ):
                return visitor.visitVariable_port_type(self)
            else:
                return visitor.visitChildren(self)




    def variable_port_type(self):

        localctx = SystemVerilogParser.Variable_port_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 264, self.RULE_variable_port_type)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3103
            self.var_data_type()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Var_data_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def KVAR(self):
            return self.getToken(SystemVerilogParser.KVAR, 0)

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_var_data_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVar_data_type" ):
                listener.enterVar_data_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVar_data_type" ):
                listener.exitVar_data_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVar_data_type" ):
                return visitor.visitVar_data_type(self)
            else:
                return visitor.visitChildren(self)




    def var_data_type(self):

        localctx = SystemVerilogParser.Var_data_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 266, self.RULE_var_data_type)
        try:
            self.state = 3108
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3105
                self.data_type()
                pass
            elif token in [SystemVerilogParser.KVAR]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3106
                self.match(SystemVerilogParser.KVAR)
                self.state = 3107
                self.data_type_or_implicit()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class SigningContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSIGNED(self):
            return self.getToken(SystemVerilogParser.KSIGNED, 0)

        def KUNSIGNED(self):
            return self.getToken(SystemVerilogParser.KUNSIGNED, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_signing

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSigning" ):
                listener.enterSigning(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSigning" ):
                listener.exitSigning(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSigning" ):
                return visitor.visitSigning(self)
            else:
                return visitor.visitChildren(self)




    def signing(self):

        localctx = SystemVerilogParser.SigningContext(self, self._ctx, self.state)
        self.enterRule(localctx, 268, self.RULE_signing)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3110
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KSIGNED or _la==SystemVerilogParser.KUNSIGNED):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Simple_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def integer_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_typeContext,0)


        def non_integer_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Non_integer_typeContext,0)


        def ps_type_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_type_identifierContext,0)


        def ps_parameter_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_parameter_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_simple_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_type" ):
                listener.enterSimple_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_type" ):
                listener.exitSimple_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_type" ):
                return visitor.visitSimple_type(self)
            else:
                return visitor.visitChildren(self)




    def simple_type(self):

        localctx = SystemVerilogParser.Simple_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 270, self.RULE_simple_type)
        try:
            self.state = 3116
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,310,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3112
                self.integer_type()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3113
                self.non_integer_type()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3114
                self.ps_type_identifier()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3115
                self.ps_parameter_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Struct_union_memberContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type_or_void(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_voidContext,0)


        def list_of_variable_decl_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_variable_decl_assignmentsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def random_qualifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Random_qualifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_struct_union_member

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStruct_union_member" ):
                listener.enterStruct_union_member(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStruct_union_member" ):
                listener.exitStruct_union_member(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStruct_union_member" ):
                return visitor.visitStruct_union_member(self)
            else:
                return visitor.visitChildren(self)




    def struct_union_member(self):

        localctx = SystemVerilogParser.Struct_union_memberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 272, self.RULE_struct_union_member)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3121
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 3118
                self.attribute_instance()
                self.state = 3123
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3125
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KRAND or _la==SystemVerilogParser.KRANDC:
                self.state = 3124
                self.random_qualifier()


            self.state = 3127
            self.data_type_or_void()
            self.state = 3128
            self.list_of_variable_decl_assignments()
            self.state = 3129
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Data_type_or_voidContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def KVOID(self):
            return self.getToken(SystemVerilogParser.KVOID, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_data_type_or_void

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterData_type_or_void" ):
                listener.enterData_type_or_void(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitData_type_or_void" ):
                listener.exitData_type_or_void(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitData_type_or_void" ):
                return visitor.visitData_type_or_void(self)
            else:
                return visitor.visitChildren(self)




    def data_type_or_void(self):

        localctx = SystemVerilogParser.Data_type_or_voidContext(self, self._ctx, self.state)
        self.enterRule(localctx, 274, self.RULE_data_type_or_void)
        try:
            self.state = 3133
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3131
                self.data_type()
                pass
            elif token in [SystemVerilogParser.KVOID]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3132
                self.match(SystemVerilogParser.KVOID)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Struct_unionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSTRUCT(self):
            return self.getToken(SystemVerilogParser.KSTRUCT, 0)

        def KUNION(self):
            return self.getToken(SystemVerilogParser.KUNION, 0)

        def KTAGGED(self):
            return self.getToken(SystemVerilogParser.KTAGGED, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_struct_union

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStruct_union" ):
                listener.enterStruct_union(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStruct_union" ):
                listener.exitStruct_union(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStruct_union" ):
                return visitor.visitStruct_union(self)
            else:
                return visitor.visitChildren(self)




    def struct_union(self):

        localctx = SystemVerilogParser.Struct_unionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 276, self.RULE_struct_union)
        self._la = 0 # Token type
        try:
            self.state = 3140
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KSTRUCT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3135
                self.match(SystemVerilogParser.KSTRUCT)
                pass
            elif token in [SystemVerilogParser.KUNION]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3136
                self.match(SystemVerilogParser.KUNION)
                self.state = 3138
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KTAGGED:
                    self.state = 3137
                    self.match(SystemVerilogParser.KTAGGED)


                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Type_referenceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KTYPE(self):
            return self.getToken(SystemVerilogParser.KTYPE, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_type_reference

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterType_reference" ):
                listener.enterType_reference(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitType_reference" ):
                listener.exitType_reference(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitType_reference" ):
                return visitor.visitType_reference(self)
            else:
                return visitor.visitChildren(self)




    def type_reference(self):

        localctx = SystemVerilogParser.Type_referenceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 278, self.RULE_type_reference)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3142
            self.match(SystemVerilogParser.KTYPE)
            self.state = 3143
            self.match(SystemVerilogParser.LP)
            self.state = 3146
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,316,self._ctx)
            if la_ == 1:
                self.state = 3144
                self.expression(0)
                pass

            elif la_ == 2:
                self.state = 3145
                self.data_type()
                pass


            self.state = 3148
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Drive_strengthContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def strength0(self):
            return self.getTypedRuleContext(SystemVerilogParser.Strength0Context,0)


        def COMMA(self):
            return self.getToken(SystemVerilogParser.COMMA, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def strength1(self):
            return self.getTypedRuleContext(SystemVerilogParser.Strength1Context,0)


        def KHIGHZ1(self):
            return self.getToken(SystemVerilogParser.KHIGHZ1, 0)

        def KHIGHZ0(self):
            return self.getToken(SystemVerilogParser.KHIGHZ0, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_drive_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDrive_strength" ):
                listener.enterDrive_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDrive_strength" ):
                listener.exitDrive_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDrive_strength" ):
                return visitor.visitDrive_strength(self)
            else:
                return visitor.visitChildren(self)




    def drive_strength(self):

        localctx = SystemVerilogParser.Drive_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 280, self.RULE_drive_strength)
        try:
            self.state = 3180
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,319,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3150
                self.match(SystemVerilogParser.LP)
                self.state = 3151
                self.strength0()
                self.state = 3152
                self.match(SystemVerilogParser.COMMA)
                self.state = 3155
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KPULL1, SystemVerilogParser.KSTRONG1, SystemVerilogParser.KSUPPLY1, SystemVerilogParser.KWEAK1]:
                    self.state = 3153
                    self.strength1()
                    pass
                elif token in [SystemVerilogParser.KHIGHZ1]:
                    self.state = 3154
                    self.match(SystemVerilogParser.KHIGHZ1)
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 3157
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3159
                self.match(SystemVerilogParser.LP)
                self.state = 3160
                self.strength1()
                self.state = 3161
                self.match(SystemVerilogParser.COMMA)
                self.state = 3164
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KPULL0, SystemVerilogParser.KSTRONG0, SystemVerilogParser.KSUPPLY0, SystemVerilogParser.KWEAK0]:
                    self.state = 3162
                    self.strength0()
                    pass
                elif token in [SystemVerilogParser.KHIGHZ0]:
                    self.state = 3163
                    self.match(SystemVerilogParser.KHIGHZ0)
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 3166
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3168
                self.match(SystemVerilogParser.LP)
                self.state = 3169
                self.match(SystemVerilogParser.KHIGHZ0)
                self.state = 3170
                self.match(SystemVerilogParser.COMMA)
                self.state = 3171
                self.strength1()
                self.state = 3172
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3174
                self.match(SystemVerilogParser.LP)
                self.state = 3175
                self.match(SystemVerilogParser.KHIGHZ1)
                self.state = 3176
                self.match(SystemVerilogParser.COMMA)
                self.state = 3177
                self.strength0()
                self.state = 3178
                self.match(SystemVerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Strength0Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSUPPLY0(self):
            return self.getToken(SystemVerilogParser.KSUPPLY0, 0)

        def KSTRONG0(self):
            return self.getToken(SystemVerilogParser.KSTRONG0, 0)

        def KPULL0(self):
            return self.getToken(SystemVerilogParser.KPULL0, 0)

        def KWEAK0(self):
            return self.getToken(SystemVerilogParser.KWEAK0, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_strength0

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrength0" ):
                listener.enterStrength0(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrength0" ):
                listener.exitStrength0(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrength0" ):
                return visitor.visitStrength0(self)
            else:
                return visitor.visitChildren(self)




    def strength0(self):

        localctx = SystemVerilogParser.Strength0Context(self, self._ctx, self.state)
        self.enterRule(localctx, 282, self.RULE_strength0)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3182
            _la = self._input.LA(1)
            if not(((((_la - 242)) & ~0x3f) == 0 and ((1 << (_la - 242)) & ((1 << (SystemVerilogParser.KPULL0 - 242)) | (1 << (SystemVerilogParser.KSTRONG0 - 242)) | (1 << (SystemVerilogParser.KSUPPLY0 - 242)))) != 0) or _la==SystemVerilogParser.KWEAK0):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Strength1Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSUPPLY1(self):
            return self.getToken(SystemVerilogParser.KSUPPLY1, 0)

        def KSTRONG1(self):
            return self.getToken(SystemVerilogParser.KSTRONG1, 0)

        def KPULL1(self):
            return self.getToken(SystemVerilogParser.KPULL1, 0)

        def KWEAK1(self):
            return self.getToken(SystemVerilogParser.KWEAK1, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_strength1

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrength1" ):
                listener.enterStrength1(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrength1" ):
                listener.exitStrength1(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrength1" ):
                return visitor.visitStrength1(self)
            else:
                return visitor.visitChildren(self)




    def strength1(self):

        localctx = SystemVerilogParser.Strength1Context(self, self._ctx, self.state)
        self.enterRule(localctx, 284, self.RULE_strength1)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3184
            _la = self._input.LA(1)
            if not(((((_la - 243)) & ~0x3f) == 0 and ((1 << (_la - 243)) & ((1 << (SystemVerilogParser.KPULL1 - 243)) | (1 << (SystemVerilogParser.KSTRONG1 - 243)) | (1 << (SystemVerilogParser.KSUPPLY1 - 243)))) != 0) or _la==SystemVerilogParser.KWEAK1):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Charge_strengthContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def KSMALL(self):
            return self.getToken(SystemVerilogParser.KSMALL, 0)

        def KMEDIUM(self):
            return self.getToken(SystemVerilogParser.KMEDIUM, 0)

        def KLARGE(self):
            return self.getToken(SystemVerilogParser.KLARGE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_charge_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCharge_strength" ):
                listener.enterCharge_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCharge_strength" ):
                listener.exitCharge_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCharge_strength" ):
                return visitor.visitCharge_strength(self)
            else:
                return visitor.visitChildren(self)




    def charge_strength(self):

        localctx = SystemVerilogParser.Charge_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 286, self.RULE_charge_strength)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3186
            self.match(SystemVerilogParser.LP)
            self.state = 3187
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KLARGE or _la==SystemVerilogParser.KMEDIUM or _la==SystemVerilogParser.KSMALL):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 3188
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay3Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def P(self):
            return self.getToken(SystemVerilogParser.P, 0)

        def delay_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_valueContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def mintypmax_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Mintypmax_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Mintypmax_expressionContext,i)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_delay3

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay3" ):
                listener.enterDelay3(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay3" ):
                listener.exitDelay3(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay3" ):
                return visitor.visitDelay3(self)
            else:
                return visitor.visitChildren(self)




    def delay3(self):

        localctx = SystemVerilogParser.Delay3Context(self, self._ctx, self.state)
        self.enterRule(localctx, 288, self.RULE_delay3)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3190
            self.match(SystemVerilogParser.P)
            self.state = 3204
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.KONESTEP, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 3191
                self.delay_value()
                pass
            elif token in [SystemVerilogParser.LP]:
                self.state = 3192
                self.match(SystemVerilogParser.LP)
                self.state = 3193
                self.mintypmax_expression()
                self.state = 3200
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COMMA:
                    self.state = 3194
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 3195
                    self.mintypmax_expression()
                    self.state = 3198
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.COMMA:
                        self.state = 3196
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 3197
                        self.mintypmax_expression()




                self.state = 3202
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay2Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def P(self):
            return self.getToken(SystemVerilogParser.P, 0)

        def delay_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_valueContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def mintypmax_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Mintypmax_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Mintypmax_expressionContext,i)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def COMMA(self):
            return self.getToken(SystemVerilogParser.COMMA, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_delay2

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay2" ):
                listener.enterDelay2(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay2" ):
                listener.exitDelay2(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay2" ):
                return visitor.visitDelay2(self)
            else:
                return visitor.visitChildren(self)




    def delay2(self):

        localctx = SystemVerilogParser.Delay2Context(self, self._ctx, self.state)
        self.enterRule(localctx, 290, self.RULE_delay2)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3206
            self.match(SystemVerilogParser.P)
            self.state = 3216
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.KONESTEP, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 3207
                self.delay_value()
                pass
            elif token in [SystemVerilogParser.LP]:
                self.state = 3208
                self.match(SystemVerilogParser.LP)
                self.state = 3209
                self.mintypmax_expression()
                self.state = 3212
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COMMA:
                    self.state = 3210
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 3211
                    self.mintypmax_expression()


                self.state = 3214
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def UNSIGNED_NUMBER(self):
            return self.getToken(SystemVerilogParser.UNSIGNED_NUMBER, 0)

        def REAL_NUMBER(self):
            return self.getToken(SystemVerilogParser.REAL_NUMBER, 0)

        def ps_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_identifierContext,0)


        def TIME_LITERAL(self):
            return self.getToken(SystemVerilogParser.TIME_LITERAL, 0)

        def KONESTEP(self):
            return self.getToken(SystemVerilogParser.KONESTEP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_delay_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_value" ):
                listener.enterDelay_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_value" ):
                listener.exitDelay_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_value" ):
                return visitor.visitDelay_value(self)
            else:
                return visitor.visitChildren(self)




    def delay_value(self):

        localctx = SystemVerilogParser.Delay_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 292, self.RULE_delay_value)
        try:
            self.state = 3223
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.UNSIGNED_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3218
                self.match(SystemVerilogParser.UNSIGNED_NUMBER)
                pass
            elif token in [SystemVerilogParser.REAL_NUMBER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3219
                self.match(SystemVerilogParser.REAL_NUMBER)
                pass
            elif token in [SystemVerilogParser.DUNIT, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3220
                self.ps_identifier()
                pass
            elif token in [SystemVerilogParser.TIME_LITERAL]:
                self.enterOuterAlt(localctx, 4)
                self.state = 3221
                self.match(SystemVerilogParser.TIME_LITERAL)
                pass
            elif token in [SystemVerilogParser.KONESTEP]:
                self.enterOuterAlt(localctx, 5)
                self.state = 3222
                self.match(SystemVerilogParser.KONESTEP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_defparam_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def defparam_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Defparam_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Defparam_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_defparam_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_defparam_assignments" ):
                listener.enterList_of_defparam_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_defparam_assignments" ):
                listener.exitList_of_defparam_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_defparam_assignments" ):
                return visitor.visitList_of_defparam_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_defparam_assignments(self):

        localctx = SystemVerilogParser.List_of_defparam_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 294, self.RULE_list_of_defparam_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3225
            self.defparam_assignment()
            self.state = 3230
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3226
                self.match(SystemVerilogParser.COMMA)
                self.state = 3227
                self.defparam_assignment()
                self.state = 3232
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_genvar_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Genvar_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Genvar_identifierContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_genvar_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_genvar_identifiers" ):
                listener.enterList_of_genvar_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_genvar_identifiers" ):
                listener.exitList_of_genvar_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_genvar_identifiers" ):
                return visitor.visitList_of_genvar_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_genvar_identifiers(self):

        localctx = SystemVerilogParser.List_of_genvar_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 296, self.RULE_list_of_genvar_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3233
            self.genvar_identifier()
            self.state = 3238
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3234
                self.match(SystemVerilogParser.COMMA)
                self.state = 3235
                self.genvar_identifier()
                self.state = 3240
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_interface_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def interface_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Interface_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,i)


        def unpacked_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Unpacked_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Unpacked_dimensionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_interface_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_interface_identifiers" ):
                listener.enterList_of_interface_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_interface_identifiers" ):
                listener.exitList_of_interface_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_interface_identifiers" ):
                return visitor.visitList_of_interface_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_interface_identifiers(self):

        localctx = SystemVerilogParser.List_of_interface_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 298, self.RULE_list_of_interface_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3241
            self.interface_identifier()
            self.state = 3245
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 3242
                self.unpacked_dimension()
                self.state = 3247
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3258
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3248
                self.match(SystemVerilogParser.COMMA)
                self.state = 3249
                self.interface_identifier()
                self.state = 3253
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3250
                    self.unpacked_dimension()
                    self.state = 3255
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3260
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_net_decl_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_decl_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Net_decl_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Net_decl_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_net_decl_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_net_decl_assignments" ):
                listener.enterList_of_net_decl_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_net_decl_assignments" ):
                listener.exitList_of_net_decl_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_net_decl_assignments" ):
                return visitor.visitList_of_net_decl_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_net_decl_assignments(self):

        localctx = SystemVerilogParser.List_of_net_decl_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 300, self.RULE_list_of_net_decl_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3261
            self.net_decl_assignment()
            self.state = 3266
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3262
                self.match(SystemVerilogParser.COMMA)
                self.state = 3263
                self.net_decl_assignment()
                self.state = 3268
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_param_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def param_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Param_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Param_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_param_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_param_assignments" ):
                listener.enterList_of_param_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_param_assignments" ):
                listener.exitList_of_param_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_param_assignments" ):
                return visitor.visitList_of_param_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_param_assignments(self):

        localctx = SystemVerilogParser.List_of_param_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 302, self.RULE_list_of_param_assignments)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3269
            self.param_assignment()
            self.state = 3274
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,332,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3270
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 3271
                    self.param_assignment() 
                self.state = 3276
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,332,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Port_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,i)


        def unpacked_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Unpacked_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Unpacked_dimensionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_port_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_identifiers" ):
                listener.enterList_of_port_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_identifiers" ):
                listener.exitList_of_port_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_identifiers" ):
                return visitor.visitList_of_port_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_identifiers(self):

        localctx = SystemVerilogParser.List_of_port_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 304, self.RULE_list_of_port_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3277
            self.port_identifier()
            self.state = 3281
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 3278
                self.unpacked_dimension()
                self.state = 3283
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3294
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3284
                self.match(SystemVerilogParser.COMMA)
                self.state = 3285
                self.port_identifier()
                self.state = 3289
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3286
                    self.unpacked_dimension()
                    self.state = 3291
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3296
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_udp_port_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Port_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_udp_port_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_udp_port_identifiers" ):
                listener.enterList_of_udp_port_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_udp_port_identifiers" ):
                listener.exitList_of_udp_port_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_udp_port_identifiers" ):
                return visitor.visitList_of_udp_port_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_udp_port_identifiers(self):

        localctx = SystemVerilogParser.List_of_udp_port_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 306, self.RULE_list_of_udp_port_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3297
            self.port_identifier()
            self.state = 3302
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3298
                self.match(SystemVerilogParser.COMMA)
                self.state = 3299
                self.port_identifier()
                self.state = 3304
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_specparam_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Specparam_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Specparam_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_specparam_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_specparam_assignments" ):
                listener.enterList_of_specparam_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_specparam_assignments" ):
                listener.exitList_of_specparam_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_specparam_assignments" ):
                return visitor.visitList_of_specparam_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_specparam_assignments(self):

        localctx = SystemVerilogParser.List_of_specparam_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 308, self.RULE_list_of_specparam_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3305
            self.specparam_assignment()
            self.state = 3310
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3306
                self.match(SystemVerilogParser.COMMA)
                self.state = 3307
                self.specparam_assignment()
                self.state = 3312
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_tf_variable_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Port_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,i)


        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def EQ(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.EQ)
            else:
                return self.getToken(SystemVerilogParser.EQ, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_tf_variable_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_tf_variable_identifiers" ):
                listener.enterList_of_tf_variable_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_tf_variable_identifiers" ):
                listener.exitList_of_tf_variable_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_tf_variable_identifiers" ):
                return visitor.visitList_of_tf_variable_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_tf_variable_identifiers(self):

        localctx = SystemVerilogParser.List_of_tf_variable_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 310, self.RULE_list_of_tf_variable_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3313
            self.port_identifier()
            self.state = 3317
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 3314
                self.variable_dimension()
                self.state = 3319
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3322
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 3320
                self.match(SystemVerilogParser.EQ)
                self.state = 3321
                self.expression(0)


            self.state = 3338
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3324
                self.match(SystemVerilogParser.COMMA)
                self.state = 3325
                self.port_identifier()
                self.state = 3329
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3326
                    self.variable_dimension()
                    self.state = 3331
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3334
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 3332
                    self.match(SystemVerilogParser.EQ)
                    self.state = 3333
                    self.expression(0)


                self.state = 3340
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_type_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def type_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Type_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Type_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_type_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_type_assignments" ):
                listener.enterList_of_type_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_type_assignments" ):
                listener.exitList_of_type_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_type_assignments" ):
                return visitor.visitList_of_type_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_type_assignments(self):

        localctx = SystemVerilogParser.List_of_type_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 312, self.RULE_list_of_type_assignments)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3341
            self.type_assignment()
            self.state = 3346
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,343,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3342
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 3343
                    self.type_assignment() 
                self.state = 3348
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,343,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_variable_decl_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_decl_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_decl_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_decl_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_variable_decl_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_decl_assignments" ):
                listener.enterList_of_variable_decl_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_decl_assignments" ):
                listener.exitList_of_variable_decl_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_decl_assignments" ):
                return visitor.visitList_of_variable_decl_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_decl_assignments(self):

        localctx = SystemVerilogParser.List_of_variable_decl_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 314, self.RULE_list_of_variable_decl_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3349
            self.variable_decl_assignment()
            self.state = 3354
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3350
                self.match(SystemVerilogParser.COMMA)
                self.state = 3351
                self.variable_decl_assignment()
                self.state = 3356
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_variable_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,i)


        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_variable_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_identifiers" ):
                listener.enterList_of_variable_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_identifiers" ):
                listener.exitList_of_variable_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_identifiers" ):
                return visitor.visitList_of_variable_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_identifiers(self):

        localctx = SystemVerilogParser.List_of_variable_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 316, self.RULE_list_of_variable_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3357
            self.variable_identifier()
            self.state = 3361
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 3358
                self.variable_dimension()
                self.state = 3363
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3374
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3364
                self.match(SystemVerilogParser.COMMA)
                self.state = 3365
                self.variable_identifier()
                self.state = 3369
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3366
                    self.variable_dimension()
                    self.state = 3371
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3376
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_variable_port_identifiersContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Port_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,i)


        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def EQ(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.EQ)
            else:
                return self.getToken(SystemVerilogParser.EQ, i)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_variable_port_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_port_identifiers" ):
                listener.enterList_of_variable_port_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_port_identifiers" ):
                listener.exitList_of_variable_port_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_port_identifiers" ):
                return visitor.visitList_of_variable_port_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_port_identifiers(self):

        localctx = SystemVerilogParser.List_of_variable_port_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 318, self.RULE_list_of_variable_port_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3377
            self.port_identifier()
            self.state = 3381
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 3378
                self.variable_dimension()
                self.state = 3383
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3386
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 3384
                self.match(SystemVerilogParser.EQ)
                self.state = 3385
                self.constant_expression(0)


            self.state = 3402
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3388
                self.match(SystemVerilogParser.COMMA)
                self.state = 3389
                self.port_identifier()
                self.state = 3393
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3390
                    self.variable_dimension()
                    self.state = 3395
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3398
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 3396
                    self.match(SystemVerilogParser.EQ)
                    self.state = 3397
                    self.constant_expression(0)


                self.state = 3404
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Defparam_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_parameter_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_parameter_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_defparam_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefparam_assignment" ):
                listener.enterDefparam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefparam_assignment" ):
                listener.exitDefparam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefparam_assignment" ):
                return visitor.visitDefparam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def defparam_assignment(self):

        localctx = SystemVerilogParser.Defparam_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 320, self.RULE_defparam_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3405
            self.hierarchical_parameter_identifier()
            self.state = 3406
            self.match(SystemVerilogParser.EQ)
            self.state = 3407
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_decl_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_identifierContext,0)


        def unpacked_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Unpacked_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Unpacked_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_decl_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_decl_assignment" ):
                listener.enterNet_decl_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_decl_assignment" ):
                listener.exitNet_decl_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_decl_assignment" ):
                return visitor.visitNet_decl_assignment(self)
            else:
                return visitor.visitChildren(self)




    def net_decl_assignment(self):

        localctx = SystemVerilogParser.Net_decl_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 322, self.RULE_net_decl_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3409
            self.net_identifier()
            self.state = 3413
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 3410
                self.unpacked_dimension()
                self.state = 3415
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3418
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 3416
                self.match(SystemVerilogParser.EQ)
                self.state = 3417
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Param_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_identifierContext,0)


        def unpacked_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Unpacked_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Unpacked_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def constant_param_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_param_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_param_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParam_assignment" ):
                listener.enterParam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParam_assignment" ):
                listener.exitParam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParam_assignment" ):
                return visitor.visitParam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def param_assignment(self):

        localctx = SystemVerilogParser.Param_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 324, self.RULE_param_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3420
            self.parameter_identifier()
            self.state = 3424
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 3421
                self.unpacked_dimension()
                self.state = 3426
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3429
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 3427
                self.match(SystemVerilogParser.EQ)
                self.state = 3428
                self.constant_param_expression()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specparam_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specparam_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_mintypmax_expressionContext,0)


        def pulse_control_specparam(self):
            return self.getTypedRuleContext(SystemVerilogParser.Pulse_control_specparamContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_specparam_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_assignment" ):
                listener.enterSpecparam_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_assignment" ):
                listener.exitSpecparam_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_assignment" ):
                return visitor.visitSpecparam_assignment(self)
            else:
                return visitor.visitChildren(self)




    def specparam_assignment(self):

        localctx = SystemVerilogParser.Specparam_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 326, self.RULE_specparam_assignment)
        try:
            self.state = 3436
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3431
                self.specparam_identifier()
                self.state = 3432
                self.match(SystemVerilogParser.EQ)
                self.state = 3433
                self.constant_mintypmax_expression()
                pass
            elif token in [SystemVerilogParser.KPATHPULSE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3435
                self.pulse_control_specparam()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Type_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def type_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_type_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterType_assignment" ):
                listener.enterType_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitType_assignment" ):
                listener.exitType_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitType_assignment" ):
                return visitor.visitType_assignment(self)
            else:
                return visitor.visitChildren(self)




    def type_assignment(self):

        localctx = SystemVerilogParser.Type_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 328, self.RULE_type_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3438
            self.type_identifier()
            self.state = 3441
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 3439
                self.match(SystemVerilogParser.EQ)
                self.state = 3440
                self.data_type()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pulse_control_specparamContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPATHPULSE(self):
            return self.getToken(SystemVerilogParser.KPATHPULSE, 0)

        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def reject_limit_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Reject_limit_valueContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specify_input_terminal_descriptorContext,0)


        def DOLLAR(self):
            return self.getToken(SystemVerilogParser.DOLLAR, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specify_output_terminal_descriptorContext,0)


        def COMMA(self):
            return self.getToken(SystemVerilogParser.COMMA, 0)

        def error_limit_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Error_limit_valueContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pulse_control_specparam

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulse_control_specparam" ):
                listener.enterPulse_control_specparam(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulse_control_specparam" ):
                listener.exitPulse_control_specparam(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulse_control_specparam" ):
                return visitor.visitPulse_control_specparam(self)
            else:
                return visitor.visitChildren(self)




    def pulse_control_specparam(self):

        localctx = SystemVerilogParser.Pulse_control_specparamContext(self, self._ctx, self.state)
        self.enterRule(localctx, 330, self.RULE_pulse_control_specparam)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3443
            self.match(SystemVerilogParser.KPATHPULSE)
            self.state = 3448
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 3444
                self.specify_input_terminal_descriptor()
                self.state = 3445
                self.match(SystemVerilogParser.DOLLAR)
                self.state = 3446
                self.specify_output_terminal_descriptor()


            self.state = 3450
            self.match(SystemVerilogParser.EQ)
            self.state = 3451
            self.match(SystemVerilogParser.LP)
            self.state = 3452
            self.reject_limit_value()
            self.state = 3455
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COMMA:
                self.state = 3453
                self.match(SystemVerilogParser.COMMA)
                self.state = 3454
                self.error_limit_value()


            self.state = 3457
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Error_limit_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def limit_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Limit_valueContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_error_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterError_limit_value" ):
                listener.enterError_limit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitError_limit_value" ):
                listener.exitError_limit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitError_limit_value" ):
                return visitor.visitError_limit_value(self)
            else:
                return visitor.visitChildren(self)




    def error_limit_value(self):

        localctx = SystemVerilogParser.Error_limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 332, self.RULE_error_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3459
            self.limit_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Reject_limit_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def limit_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Limit_valueContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_reject_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReject_limit_value" ):
                listener.enterReject_limit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReject_limit_value" ):
                listener.exitReject_limit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReject_limit_value" ):
                return visitor.visitReject_limit_value(self)
            else:
                return visitor.visitChildren(self)




    def reject_limit_value(self):

        localctx = SystemVerilogParser.Reject_limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 334, self.RULE_reject_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3461
            self.limit_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Limit_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_limit_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLimit_value" ):
                listener.enterLimit_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLimit_value" ):
                listener.exitLimit_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLimit_value" ):
                return visitor.visitLimit_value(self)
            else:
                return visitor.visitChildren(self)




    def limit_value(self):

        localctx = SystemVerilogParser.Limit_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 336, self.RULE_limit_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3463
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_decl_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,0)


        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def dynamic_array_variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dynamic_array_variable_identifierContext,0)


        def unsized_dimension(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unsized_dimensionContext,0)


        def dynamic_array_new(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dynamic_array_newContext,0)


        def class_variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_variable_identifierContext,0)


        def class_new(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_newContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_variable_decl_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_decl_assignment" ):
                listener.enterVariable_decl_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_decl_assignment" ):
                listener.exitVariable_decl_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_decl_assignment" ):
                return visitor.visitVariable_decl_assignment(self)
            else:
                return visitor.visitChildren(self)




    def variable_decl_assignment(self):

        localctx = SystemVerilogParser.Variable_decl_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 338, self.RULE_variable_decl_assignment)
        self._la = 0 # Token type
        try:
            self.state = 3493
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,366,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3465
                self.variable_identifier()
                self.state = 3469
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3466
                    self.variable_dimension()
                    self.state = 3471
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3474
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 3472
                    self.match(SystemVerilogParser.EQ)
                    self.state = 3473
                    self.expression(0)


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3476
                self.dynamic_array_variable_identifier()
                self.state = 3477
                self.unsized_dimension()
                self.state = 3481
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3478
                    self.variable_dimension()
                    self.state = 3483
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3486
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 3484
                    self.match(SystemVerilogParser.EQ)
                    self.state = 3485
                    self.dynamic_array_new()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3488
                self.class_variable_identifier()
                self.state = 3491
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 3489
                    self.match(SystemVerilogParser.EQ)
                    self.state = 3490
                    self.class_new()


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_newContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KNEW(self):
            return self.getToken(SystemVerilogParser.KNEW, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_new

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_new" ):
                listener.enterClass_new(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_new" ):
                listener.exitClass_new(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_new" ):
                return visitor.visitClass_new(self)
            else:
                return visitor.visitChildren(self)




    def class_new(self):

        localctx = SystemVerilogParser.Class_newContext(self, self._ctx, self.state)
        self.enterRule(localctx, 340, self.RULE_class_new)
        self._la = 0 # Token type
        try:
            self.state = 3507
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,369,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3496
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.DUNIT or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 3495
                    self.class_scope()


                self.state = 3498
                self.match(SystemVerilogParser.KNEW)
                self.state = 3503
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 3499
                    self.match(SystemVerilogParser.LP)
                    self.state = 3500
                    self.list_of_arguments()
                    self.state = 3501
                    self.match(SystemVerilogParser.RP)


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3505
                self.match(SystemVerilogParser.KNEW)
                self.state = 3506
                self.expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dynamic_array_newContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KNEW(self):
            return self.getToken(SystemVerilogParser.KNEW, 0)

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dynamic_array_new

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDynamic_array_new" ):
                listener.enterDynamic_array_new(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDynamic_array_new" ):
                listener.exitDynamic_array_new(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDynamic_array_new" ):
                return visitor.visitDynamic_array_new(self)
            else:
                return visitor.visitChildren(self)




    def dynamic_array_new(self):

        localctx = SystemVerilogParser.Dynamic_array_newContext(self, self._ctx, self.state)
        self.enterRule(localctx, 342, self.RULE_dynamic_array_new)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3509
            self.match(SystemVerilogParser.KNEW)
            self.state = 3510
            self.match(SystemVerilogParser.LB)
            self.state = 3511
            self.expression(0)
            self.state = 3512
            self.match(SystemVerilogParser.RB)
            self.state = 3517
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 3513
                self.match(SystemVerilogParser.LP)
                self.state = 3514
                self.expression(0)
                self.state = 3515
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unpacked_dimensionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def constant_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_rangeContext,0)


        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_unpacked_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnpacked_dimension" ):
                listener.enterUnpacked_dimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnpacked_dimension" ):
                listener.exitUnpacked_dimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnpacked_dimension" ):
                return visitor.visitUnpacked_dimension(self)
            else:
                return visitor.visitChildren(self)




    def unpacked_dimension(self):

        localctx = SystemVerilogParser.Unpacked_dimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 344, self.RULE_unpacked_dimension)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3519
            self.match(SystemVerilogParser.LB)
            self.state = 3522
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,371,self._ctx)
            if la_ == 1:
                self.state = 3520
                self.constant_range()
                pass

            elif la_ == 2:
                self.state = 3521
                self.constant_expression(0)
                pass


            self.state = 3524
            self.match(SystemVerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Packed_dimensionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def constant_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_rangeContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def unsized_dimension(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unsized_dimensionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_packed_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPacked_dimension" ):
                listener.enterPacked_dimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPacked_dimension" ):
                listener.exitPacked_dimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPacked_dimension" ):
                return visitor.visitPacked_dimension(self)
            else:
                return visitor.visitChildren(self)




    def packed_dimension(self):

        localctx = SystemVerilogParser.Packed_dimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 346, self.RULE_packed_dimension)
        try:
            self.state = 3531
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,372,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3526
                self.match(SystemVerilogParser.LB)
                self.state = 3527
                self.constant_range()
                self.state = 3528
                self.match(SystemVerilogParser.RB)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3530
                self.unsized_dimension()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Associative_dimensionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def STAR(self):
            return self.getToken(SystemVerilogParser.STAR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_associative_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssociative_dimension" ):
                listener.enterAssociative_dimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssociative_dimension" ):
                listener.exitAssociative_dimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssociative_dimension" ):
                return visitor.visitAssociative_dimension(self)
            else:
                return visitor.visitChildren(self)




    def associative_dimension(self):

        localctx = SystemVerilogParser.Associative_dimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 348, self.RULE_associative_dimension)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3533
            self.match(SystemVerilogParser.LB)
            self.state = 3536
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 3534
                self.data_type()
                pass
            elif token in [SystemVerilogParser.STAR]:
                self.state = 3535
                self.match(SystemVerilogParser.STAR)
                pass
            else:
                raise NoViableAltException(self)

            self.state = 3538
            self.match(SystemVerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_dimensionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def unsized_dimension(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unsized_dimensionContext,0)


        def unpacked_dimension(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unpacked_dimensionContext,0)


        def associative_dimension(self):
            return self.getTypedRuleContext(SystemVerilogParser.Associative_dimensionContext,0)


        def queue_dimension(self):
            return self.getTypedRuleContext(SystemVerilogParser.Queue_dimensionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_variable_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_dimension" ):
                listener.enterVariable_dimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_dimension" ):
                listener.exitVariable_dimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_dimension" ):
                return visitor.visitVariable_dimension(self)
            else:
                return visitor.visitChildren(self)




    def variable_dimension(self):

        localctx = SystemVerilogParser.Variable_dimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 350, self.RULE_variable_dimension)
        try:
            self.state = 3544
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,374,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3540
                self.unsized_dimension()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3541
                self.unpacked_dimension()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3542
                self.associative_dimension()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3543
                self.queue_dimension()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Queue_dimensionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def DOLLAR(self):
            return self.getToken(SystemVerilogParser.DOLLAR, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_queue_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterQueue_dimension" ):
                listener.enterQueue_dimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitQueue_dimension" ):
                listener.exitQueue_dimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitQueue_dimension" ):
                return visitor.visitQueue_dimension(self)
            else:
                return visitor.visitChildren(self)




    def queue_dimension(self):

        localctx = SystemVerilogParser.Queue_dimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 352, self.RULE_queue_dimension)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3546
            self.match(SystemVerilogParser.LB)
            self.state = 3547
            self.match(SystemVerilogParser.DOLLAR)
            self.state = 3550
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 3548
                self.match(SystemVerilogParser.COLON)
                self.state = 3549
                self.constant_expression(0)


            self.state = 3552
            self.match(SystemVerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unsized_dimensionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_unsized_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnsized_dimension" ):
                listener.enterUnsized_dimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnsized_dimension" ):
                listener.exitUnsized_dimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnsized_dimension" ):
                return visitor.visitUnsized_dimension(self)
            else:
                return visitor.visitChildren(self)




    def unsized_dimension(self):

        localctx = SystemVerilogParser.Unsized_dimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 354, self.RULE_unsized_dimension)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3554
            self.match(SystemVerilogParser.LB)
            self.state = 3555
            self.match(SystemVerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_data_type_or_implicitContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type_or_void(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_voidContext,0)


        def implicit_data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_data_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_function_data_type_or_implicit

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_data_type_or_implicit" ):
                listener.enterFunction_data_type_or_implicit(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_data_type_or_implicit" ):
                listener.exitFunction_data_type_or_implicit(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_data_type_or_implicit" ):
                return visitor.visitFunction_data_type_or_implicit(self)
            else:
                return visitor.visitChildren(self)




    def function_data_type_or_implicit(self):

        localctx = SystemVerilogParser.Function_data_type_or_implicitContext(self, self._ctx, self.state)
        self.enterRule(localctx, 356, self.RULE_function_data_type_or_implicit)
        try:
            self.state = 3559
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,376,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3557
                self.data_type_or_void()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3558
                self.implicit_data_type()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KFUNCTION(self):
            return self.getToken(SystemVerilogParser.KFUNCTION, 0)

        def function_body_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_body_declarationContext,0)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_function_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_declaration" ):
                listener.enterFunction_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_declaration" ):
                listener.exitFunction_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_declaration" ):
                return visitor.visitFunction_declaration(self)
            else:
                return visitor.visitChildren(self)




    def function_declaration(self):

        localctx = SystemVerilogParser.Function_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 358, self.RULE_function_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3561
            self.match(SystemVerilogParser.KFUNCTION)
            self.state = 3563
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 3562
                self.lifetime()


            self.state = 3565
            self.function_body_declaration()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_body_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_data_type_or_implicitContext,0)


        def function_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Function_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Function_identifierContext,i)


        def KENDFUNCTION(self):
            return self.getToken(SystemVerilogParser.KENDFUNCTION, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def function_statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Function_statement_or_nullContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Function_statement_or_nullContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def tf_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Tf_item_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Tf_item_declarationContext,i)


        def tf_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_listContext,0)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_function_body_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_body_declaration" ):
                listener.enterFunction_body_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_body_declaration" ):
                listener.exitFunction_body_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_body_declaration" ):
                return visitor.visitFunction_body_declaration(self)
            else:
                return visitor.visitChildren(self)




    def function_body_declaration(self):

        localctx = SystemVerilogParser.Function_body_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 360, self.RULE_function_body_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3567
            self.function_data_type_or_implicit()
            self.state = 3572
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,378,self._ctx)
            if la_ == 1:
                self.state = 3568
                self.interface_identifier()
                self.state = 3569
                self.match(SystemVerilogParser.DOT)

            elif la_ == 2:
                self.state = 3571
                self.class_scope()


            self.state = 3574
            self.function_identifier()
            self.state = 3594
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SEMI]:
                self.state = 3575
                self.match(SystemVerilogParser.SEMI)
                self.state = 3579
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,379,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3576
                        self.tf_item_declaration() 
                    self.state = 3581
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,379,self._ctx)

                pass
            elif token in [SystemVerilogParser.LP]:
                self.state = 3582
                self.match(SystemVerilogParser.LP)
                self.state = 3584
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,380,self._ctx)
                if la_ == 1:
                    self.state = 3583
                    self.tf_port_list()


                self.state = 3586
                self.match(SystemVerilogParser.RP)
                self.state = 3587
                self.match(SystemVerilogParser.SEMI)
                self.state = 3591
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,381,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3588
                        self.block_item_declaration() 
                    self.state = 3593
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,381,self._ctx)

                pass
            else:
                raise NoViableAltException(self)

            self.state = 3599
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.P) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or ((((_la - 69)) & ~0x3f) == 0 and ((1 << (_la - 69)) & ((1 << (SystemVerilogParser.PLUSPLUS - 69)) | (1 << (SystemVerilogParser.ARROW - 69)) | (1 << (SystemVerilogParser.MINUSGTGT - 69)) | (1 << (SystemVerilogParser.KASSERT - 69)) | (1 << (SystemVerilogParser.KASSIGN - 69)) | (1 << (SystemVerilogParser.KASSUME - 69)) | (1 << (SystemVerilogParser.KBEGIN - 69)) | (1 << (SystemVerilogParser.KBREAK - 69)) | (1 << (SystemVerilogParser.KBYTE - 69)) | (1 << (SystemVerilogParser.KCASE - 69)) | (1 << (SystemVerilogParser.KCASEX - 69)) | (1 << (SystemVerilogParser.KCASEZ - 69)) | (1 << (SystemVerilogParser.KCONTINUE - 69)) | (1 << (SystemVerilogParser.KCOVER - 69)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (SystemVerilogParser.KDEASSIGN - 133)) | (1 << (SystemVerilogParser.KDISABLE - 133)) | (1 << (SystemVerilogParser.KDO - 133)) | (1 << (SystemVerilogParser.KEXPECT - 133)) | (1 << (SystemVerilogParser.KFOR - 133)) | (1 << (SystemVerilogParser.KFORCE - 133)) | (1 << (SystemVerilogParser.KFOREACH - 133)) | (1 << (SystemVerilogParser.KFOREVER - 133)) | (1 << (SystemVerilogParser.KFORK - 133)) | (1 << (SystemVerilogParser.KIF - 133)) | (1 << (SystemVerilogParser.KINT - 133)) | (1 << (SystemVerilogParser.KINTEGER - 133)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPRIORITY - 207)) | (1 << (SystemVerilogParser.KRANDCASE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KRANDSEQUENCE - 207)) | (1 << (SystemVerilogParser.KRELEASE - 207)) | (1 << (SystemVerilogParser.KREPEAT - 207)) | (1 << (SystemVerilogParser.KRESTRICT - 207)) | (1 << (SystemVerilogParser.KRETURN - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNIQUE0 - 276)) | (1 << (SystemVerilogParser.KVOID - 276)) | (1 << (SystemVerilogParser.KWAIT - 276)) | (1 << (SystemVerilogParser.KWAIT_ORDER - 276)) | (1 << (SystemVerilogParser.KWHILE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 3596
                self.function_statement_or_null()
                self.state = 3601
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3602
            self.match(SystemVerilogParser.KENDFUNCTION)
            self.state = 3605
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 3603
                self.match(SystemVerilogParser.COLON)
                self.state = 3604
                self.function_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_prototypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KFUNCTION(self):
            return self.getToken(SystemVerilogParser.KFUNCTION, 0)

        def data_type_or_void(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_voidContext,0)


        def function_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def tf_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_function_prototype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_prototype" ):
                listener.enterFunction_prototype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_prototype" ):
                listener.exitFunction_prototype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_prototype" ):
                return visitor.visitFunction_prototype(self)
            else:
                return visitor.visitChildren(self)




    def function_prototype(self):

        localctx = SystemVerilogParser.Function_prototypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 362, self.RULE_function_prototype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3607
            self.match(SystemVerilogParser.KFUNCTION)
            self.state = 3608
            self.data_type_or_void()
            self.state = 3609
            self.function_identifier()
            self.state = 3615
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 3610
                self.match(SystemVerilogParser.LP)
                self.state = 3612
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,385,self._ctx)
                if la_ == 1:
                    self.state = 3611
                    self.tf_port_list()


                self.state = 3614
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dpi_import_exportContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KIMPORT(self):
            return self.getToken(SystemVerilogParser.KIMPORT, 0)

        def dpi_spec_string(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dpi_spec_stringContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def dpi_function_proto(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dpi_function_protoContext,0)


        def dpi_task_proto(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dpi_task_protoContext,0)


        def dpi_function_import_property(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dpi_function_import_propertyContext,0)


        def c_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.C_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def dpi_task_import_property(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dpi_task_import_propertyContext,0)


        def KEXPORT(self):
            return self.getToken(SystemVerilogParser.KEXPORT, 0)

        def KFUNCTION(self):
            return self.getToken(SystemVerilogParser.KFUNCTION, 0)

        def function_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_identifierContext,0)


        def KTASK(self):
            return self.getToken(SystemVerilogParser.KTASK, 0)

        def task_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dpi_import_export

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDpi_import_export" ):
                listener.enterDpi_import_export(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDpi_import_export" ):
                listener.exitDpi_import_export(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDpi_import_export" ):
                return visitor.visitDpi_import_export(self)
            else:
                return visitor.visitChildren(self)




    def dpi_import_export(self):

        localctx = SystemVerilogParser.Dpi_import_exportContext(self, self._ctx, self.state)
        self.enterRule(localctx, 364, self.RULE_dpi_import_export)
        self._la = 0 # Token type
        try:
            self.state = 3656
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KIMPORT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3617
                self.match(SystemVerilogParser.KIMPORT)
                self.state = 3618
                self.dpi_spec_string()
                self.state = 3637
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,391,self._ctx)
                if la_ == 1:
                    self.state = 3620
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.KCONTEXT or _la==SystemVerilogParser.KPURE:
                        self.state = 3619
                        self.dpi_function_import_property()


                    self.state = 3625
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                        self.state = 3622
                        self.c_identifier()
                        self.state = 3623
                        self.match(SystemVerilogParser.EQ)


                    self.state = 3627
                    self.dpi_function_proto()
                    pass

                elif la_ == 2:
                    self.state = 3629
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.KCONTEXT:
                        self.state = 3628
                        self.dpi_task_import_property()


                    self.state = 3634
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                        self.state = 3631
                        self.c_identifier()
                        self.state = 3632
                        self.match(SystemVerilogParser.EQ)


                    self.state = 3636
                    self.dpi_task_proto()
                    pass


                self.state = 3639
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KEXPORT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3641
                self.match(SystemVerilogParser.KEXPORT)
                self.state = 3642
                self.dpi_spec_string()
                self.state = 3646
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 3643
                    self.c_identifier()
                    self.state = 3644
                    self.match(SystemVerilogParser.EQ)


                self.state = 3652
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KFUNCTION]:
                    self.state = 3648
                    self.match(SystemVerilogParser.KFUNCTION)
                    self.state = 3649
                    self.function_identifier()
                    pass
                elif token in [SystemVerilogParser.KTASK]:
                    self.state = 3650
                    self.match(SystemVerilogParser.KTASK)
                    self.state = 3651
                    self.task_identifier()
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 3654
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dpi_spec_stringContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DPIC(self):
            return self.getToken(SystemVerilogParser.DPIC, 0)

        def DPI(self):
            return self.getToken(SystemVerilogParser.DPI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dpi_spec_string

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDpi_spec_string" ):
                listener.enterDpi_spec_string(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDpi_spec_string" ):
                listener.exitDpi_spec_string(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDpi_spec_string" ):
                return visitor.visitDpi_spec_string(self)
            else:
                return visitor.visitChildren(self)




    def dpi_spec_string(self):

        localctx = SystemVerilogParser.Dpi_spec_stringContext(self, self._ctx, self.state)
        self.enterRule(localctx, 366, self.RULE_dpi_spec_string)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3658
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.DPI or _la==SystemVerilogParser.DPIC):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dpi_function_import_propertyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCONTEXT(self):
            return self.getToken(SystemVerilogParser.KCONTEXT, 0)

        def KPURE(self):
            return self.getToken(SystemVerilogParser.KPURE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dpi_function_import_property

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDpi_function_import_property" ):
                listener.enterDpi_function_import_property(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDpi_function_import_property" ):
                listener.exitDpi_function_import_property(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDpi_function_import_property" ):
                return visitor.visitDpi_function_import_property(self)
            else:
                return visitor.visitChildren(self)




    def dpi_function_import_property(self):

        localctx = SystemVerilogParser.Dpi_function_import_propertyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 368, self.RULE_dpi_function_import_property)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3660
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KCONTEXT or _la==SystemVerilogParser.KPURE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dpi_task_import_propertyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCONTEXT(self):
            return self.getToken(SystemVerilogParser.KCONTEXT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dpi_task_import_property

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDpi_task_import_property" ):
                listener.enterDpi_task_import_property(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDpi_task_import_property" ):
                listener.exitDpi_task_import_property(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDpi_task_import_property" ):
                return visitor.visitDpi_task_import_property(self)
            else:
                return visitor.visitChildren(self)




    def dpi_task_import_property(self):

        localctx = SystemVerilogParser.Dpi_task_import_propertyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 370, self.RULE_dpi_task_import_property)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3662
            self.match(SystemVerilogParser.KCONTEXT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dpi_function_protoContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_prototypeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dpi_function_proto

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDpi_function_proto" ):
                listener.enterDpi_function_proto(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDpi_function_proto" ):
                listener.exitDpi_function_proto(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDpi_function_proto" ):
                return visitor.visitDpi_function_proto(self)
            else:
                return visitor.visitChildren(self)




    def dpi_function_proto(self):

        localctx = SystemVerilogParser.Dpi_function_protoContext(self, self._ctx, self.state)
        self.enterRule(localctx, 372, self.RULE_dpi_function_proto)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3664
            self.function_prototype()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dpi_task_protoContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_prototypeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dpi_task_proto

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDpi_task_proto" ):
                listener.enterDpi_task_proto(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDpi_task_proto" ):
                listener.exitDpi_task_proto(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDpi_task_proto" ):
                return visitor.visitDpi_task_proto(self)
            else:
                return visitor.visitChildren(self)




    def dpi_task_proto(self):

        localctx = SystemVerilogParser.Dpi_task_protoContext(self, self._ctx, self.state)
        self.enterRule(localctx, 374, self.RULE_dpi_task_proto)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3666
            self.task_prototype()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KTASK(self):
            return self.getToken(SystemVerilogParser.KTASK, 0)

        def task_body_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_body_declarationContext,0)


        def lifetime(self):
            return self.getTypedRuleContext(SystemVerilogParser.LifetimeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_task_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_declaration" ):
                listener.enterTask_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_declaration" ):
                listener.exitTask_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_declaration" ):
                return visitor.visitTask_declaration(self)
            else:
                return visitor.visitChildren(self)




    def task_declaration(self):

        localctx = SystemVerilogParser.Task_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 376, self.RULE_task_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3668
            self.match(SystemVerilogParser.KTASK)
            self.state = 3670
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KAUTOMATIC or _la==SystemVerilogParser.KSTATIC:
                self.state = 3669
                self.lifetime()


            self.state = 3672
            self.task_body_declaration()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_body_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Task_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Task_identifierContext,i)


        def KENDTASK(self):
            return self.getToken(SystemVerilogParser.KENDTASK, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Statement_or_nullContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def tf_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Tf_item_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Tf_item_declarationContext,i)


        def tf_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_listContext,0)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Block_item_declarationContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_task_body_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_body_declaration" ):
                listener.enterTask_body_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_body_declaration" ):
                listener.exitTask_body_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_body_declaration" ):
                return visitor.visitTask_body_declaration(self)
            else:
                return visitor.visitChildren(self)




    def task_body_declaration(self):

        localctx = SystemVerilogParser.Task_body_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 378, self.RULE_task_body_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3678
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,396,self._ctx)
            if la_ == 1:
                self.state = 3674
                self.interface_identifier()
                self.state = 3675
                self.match(SystemVerilogParser.DOT)

            elif la_ == 2:
                self.state = 3677
                self.class_scope()


            self.state = 3680
            self.task_identifier()
            self.state = 3700
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SEMI]:
                self.state = 3681
                self.match(SystemVerilogParser.SEMI)
                self.state = 3685
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,397,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3682
                        self.tf_item_declaration() 
                    self.state = 3687
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,397,self._ctx)

                pass
            elif token in [SystemVerilogParser.LP]:
                self.state = 3688
                self.match(SystemVerilogParser.LP)
                self.state = 3690
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,398,self._ctx)
                if la_ == 1:
                    self.state = 3689
                    self.tf_port_list()


                self.state = 3692
                self.match(SystemVerilogParser.RP)
                self.state = 3693
                self.match(SystemVerilogParser.SEMI)
                self.state = 3697
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,399,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3694
                        self.block_item_declaration() 
                    self.state = 3699
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,399,self._ctx)

                pass
            else:
                raise NoViableAltException(self)

            self.state = 3705
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.P) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or ((((_la - 69)) & ~0x3f) == 0 and ((1 << (_la - 69)) & ((1 << (SystemVerilogParser.PLUSPLUS - 69)) | (1 << (SystemVerilogParser.ARROW - 69)) | (1 << (SystemVerilogParser.MINUSGTGT - 69)) | (1 << (SystemVerilogParser.KASSERT - 69)) | (1 << (SystemVerilogParser.KASSIGN - 69)) | (1 << (SystemVerilogParser.KASSUME - 69)) | (1 << (SystemVerilogParser.KBEGIN - 69)) | (1 << (SystemVerilogParser.KBREAK - 69)) | (1 << (SystemVerilogParser.KBYTE - 69)) | (1 << (SystemVerilogParser.KCASE - 69)) | (1 << (SystemVerilogParser.KCASEX - 69)) | (1 << (SystemVerilogParser.KCASEZ - 69)) | (1 << (SystemVerilogParser.KCONTINUE - 69)) | (1 << (SystemVerilogParser.KCOVER - 69)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (SystemVerilogParser.KDEASSIGN - 133)) | (1 << (SystemVerilogParser.KDISABLE - 133)) | (1 << (SystemVerilogParser.KDO - 133)) | (1 << (SystemVerilogParser.KEXPECT - 133)) | (1 << (SystemVerilogParser.KFOR - 133)) | (1 << (SystemVerilogParser.KFORCE - 133)) | (1 << (SystemVerilogParser.KFOREACH - 133)) | (1 << (SystemVerilogParser.KFOREVER - 133)) | (1 << (SystemVerilogParser.KFORK - 133)) | (1 << (SystemVerilogParser.KIF - 133)) | (1 << (SystemVerilogParser.KINT - 133)) | (1 << (SystemVerilogParser.KINTEGER - 133)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPRIORITY - 207)) | (1 << (SystemVerilogParser.KRANDCASE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KRANDSEQUENCE - 207)) | (1 << (SystemVerilogParser.KRELEASE - 207)) | (1 << (SystemVerilogParser.KREPEAT - 207)) | (1 << (SystemVerilogParser.KRESTRICT - 207)) | (1 << (SystemVerilogParser.KRETURN - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNIQUE0 - 276)) | (1 << (SystemVerilogParser.KVOID - 276)) | (1 << (SystemVerilogParser.KWAIT - 276)) | (1 << (SystemVerilogParser.KWAIT_ORDER - 276)) | (1 << (SystemVerilogParser.KWHILE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 3702
                self.statement_or_null()
                self.state = 3707
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3708
            self.match(SystemVerilogParser.KENDTASK)
            self.state = 3711
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 3709
                self.match(SystemVerilogParser.COLON)
                self.state = 3710
                self.task_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Block_item_declarationContext,0)


        def tf_port_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tf_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_item_declaration" ):
                listener.enterTf_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_item_declaration" ):
                listener.exitTf_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_item_declaration" ):
                return visitor.visitTf_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_item_declaration(self):

        localctx = SystemVerilogParser.Tf_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 380, self.RULE_tf_item_declaration)
        try:
            self.state = 3715
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,403,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3713
                self.block_item_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3714
                self.tf_port_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def tf_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Tf_port_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Tf_port_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tf_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_port_list" ):
                listener.enterTf_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_port_list" ):
                listener.exitTf_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_port_list" ):
                return visitor.visitTf_port_list(self)
            else:
                return visitor.visitChildren(self)




    def tf_port_list(self):

        localctx = SystemVerilogParser.Tf_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 382, self.RULE_tf_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3717
            self.tf_port_item()
            self.state = 3722
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3718
                self.match(SystemVerilogParser.COMMA)
                self.state = 3719
                self.tf_port_item()
                self.state = 3724
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_port_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def tf_port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_directionContext,0)


        def KVAR(self):
            return self.getToken(SystemVerilogParser.KVAR, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,0)


        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tf_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_port_item" ):
                listener.enterTf_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_port_item" ):
                listener.exitTf_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_port_item" ):
                return visitor.visitTf_port_item(self)
            else:
                return visitor.visitChildren(self)




    def tf_port_item(self):

        localctx = SystemVerilogParser.Tf_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 384, self.RULE_tf_port_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3728
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 3725
                self.attribute_instance()
                self.state = 3730
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3732
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KCONST or ((((_la - 191)) & ~0x3f) == 0 and ((1 << (_la - 191)) & ((1 << (SystemVerilogParser.KINOUT - 191)) | (1 << (SystemVerilogParser.KINPUT - 191)) | (1 << (SystemVerilogParser.KOUTPUT - 191)))) != 0) or _la==SystemVerilogParser.KREF:
                self.state = 3731
                self.tf_port_direction()


            self.state = 3735
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KVAR:
                self.state = 3734
                self.match(SystemVerilogParser.KVAR)


            self.state = 3737
            self.data_type_or_implicit()
            self.state = 3749
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 3738
                self.port_identifier()
                self.state = 3742
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LB:
                    self.state = 3739
                    self.variable_dimension()
                    self.state = 3744
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3747
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.EQ:
                    self.state = 3745
                    self.match(SystemVerilogParser.EQ)
                    self.state = 3746
                    self.expression(0)




        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_port_directionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_directionContext,0)


        def KCONST(self):
            return self.getToken(SystemVerilogParser.KCONST, 0)

        def KREF(self):
            return self.getToken(SystemVerilogParser.KREF, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tf_port_direction

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_port_direction" ):
                listener.enterTf_port_direction(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_port_direction" ):
                listener.exitTf_port_direction(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_port_direction" ):
                return visitor.visitTf_port_direction(self)
            else:
                return visitor.visitChildren(self)




    def tf_port_direction(self):

        localctx = SystemVerilogParser.Tf_port_directionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 386, self.RULE_tf_port_direction)
        try:
            self.state = 3754
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KINOUT, SystemVerilogParser.KINPUT, SystemVerilogParser.KOUTPUT, SystemVerilogParser.KREF]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3751
                self.port_direction()
                pass
            elif token in [SystemVerilogParser.KCONST]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3752
                self.match(SystemVerilogParser.KCONST)
                self.state = 3753
                self.match(SystemVerilogParser.KREF)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_port_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def tf_port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_directionContext,0)


        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def list_of_tf_variable_identifiers(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_tf_variable_identifiersContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def KVAR(self):
            return self.getToken(SystemVerilogParser.KVAR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tf_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_port_declaration" ):
                listener.enterTf_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_port_declaration" ):
                listener.exitTf_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_port_declaration" ):
                return visitor.visitTf_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_port_declaration(self):

        localctx = SystemVerilogParser.Tf_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 388, self.RULE_tf_port_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3759
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 3756
                self.attribute_instance()
                self.state = 3761
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3762
            self.tf_port_direction()
            self.state = 3764
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KVAR:
                self.state = 3763
                self.match(SystemVerilogParser.KVAR)


            self.state = 3766
            self.data_type_or_implicit()
            self.state = 3767
            self.list_of_tf_variable_identifiers()
            self.state = 3768
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_prototypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KTASK(self):
            return self.getToken(SystemVerilogParser.KTASK, 0)

        def task_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Task_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def tf_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_task_prototype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_prototype" ):
                listener.enterTask_prototype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_prototype" ):
                listener.exitTask_prototype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_prototype" ):
                return visitor.visitTask_prototype(self)
            else:
                return visitor.visitChildren(self)




    def task_prototype(self):

        localctx = SystemVerilogParser.Task_prototypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 390, self.RULE_task_prototype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3770
            self.match(SystemVerilogParser.KTASK)
            self.state = 3771
            self.task_identifier()
            self.state = 3777
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 3772
                self.match(SystemVerilogParser.LP)
                self.state = 3774
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,414,self._ctx)
                if la_ == 1:
                    self.state = 3773
                    self.tf_port_list()


                self.state = 3776
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_declarationContext,0)


        def let_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def local_parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Local_parameter_declarationContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_block_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_item_declaration" ):
                listener.enterBlock_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_item_declaration" ):
                listener.exitBlock_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_item_declaration" ):
                return visitor.visitBlock_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def block_item_declaration(self):

        localctx = SystemVerilogParser.Block_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 392, self.RULE_block_item_declaration)
        self._la = 0 # Token type
        try:
            self.state = 3801
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,420,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3782
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 3779
                    self.attribute_instance()
                    self.state = 3784
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3787
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.LB, SystemVerilogParser.KAUTOMATIC, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KCONST, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KIMPORT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNETTYPE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTATIC, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KTYPEDEF, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KVAR, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                    self.state = 3785
                    self.data_declaration()
                    pass
                elif token in [SystemVerilogParser.KLET]:
                    self.state = 3786
                    self.let_declaration()
                    pass
                else:
                    raise NoViableAltException(self)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3792
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 3789
                    self.attribute_instance()
                    self.state = 3794
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 3797
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.KLOCALPARAM]:
                    self.state = 3795
                    self.local_parameter_declaration()
                    pass
                elif token in [SystemVerilogParser.KPARAMETER]:
                    self.state = 3796
                    self.parameter_declaration()
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 3799
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KMODPORT(self):
            return self.getToken(SystemVerilogParser.KMODPORT, 0)

        def modport_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Modport_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Modport_itemContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_declaration" ):
                listener.enterModport_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_declaration" ):
                listener.exitModport_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_declaration" ):
                return visitor.visitModport_declaration(self)
            else:
                return visitor.visitChildren(self)




    def modport_declaration(self):

        localctx = SystemVerilogParser.Modport_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 394, self.RULE_modport_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3803
            self.match(SystemVerilogParser.KMODPORT)
            self.state = 3804
            self.modport_item()
            self.state = 3809
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3805
                self.match(SystemVerilogParser.COMMA)
                self.state = 3806
                self.modport_item()
                self.state = 3811
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3812
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def modport_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Modport_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def modport_ports_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Modport_ports_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Modport_ports_declarationContext,i)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_item" ):
                listener.enterModport_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_item" ):
                listener.exitModport_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_item" ):
                return visitor.visitModport_item(self)
            else:
                return visitor.visitChildren(self)




    def modport_item(self):

        localctx = SystemVerilogParser.Modport_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 396, self.RULE_modport_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3814
            self.modport_identifier()
            self.state = 3815
            self.match(SystemVerilogParser.LP)
            self.state = 3816
            self.modport_ports_declaration()
            self.state = 3821
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3817
                self.match(SystemVerilogParser.COMMA)
                self.state = 3818
                self.modport_ports_declaration()
                self.state = 3823
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3824
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_ports_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def modport_simple_ports_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Modport_simple_ports_declarationContext,0)


        def modport_tf_ports_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Modport_tf_ports_declarationContext,0)


        def modport_clocking_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Modport_clocking_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_ports_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_ports_declaration" ):
                listener.enterModport_ports_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_ports_declaration" ):
                listener.exitModport_ports_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_ports_declaration" ):
                return visitor.visitModport_ports_declaration(self)
            else:
                return visitor.visitChildren(self)




    def modport_ports_declaration(self):

        localctx = SystemVerilogParser.Modport_ports_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 398, self.RULE_modport_ports_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3829
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 3826
                self.attribute_instance()
                self.state = 3831
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 3835
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KINOUT, SystemVerilogParser.KINPUT, SystemVerilogParser.KOUTPUT, SystemVerilogParser.KREF]:
                self.state = 3832
                self.modport_simple_ports_declaration()
                pass
            elif token in [SystemVerilogParser.KEXPORT, SystemVerilogParser.KIMPORT]:
                self.state = 3833
                self.modport_tf_ports_declaration()
                pass
            elif token in [SystemVerilogParser.KCLOCKING]:
                self.state = 3834
                self.modport_clocking_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_clocking_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCLOCKING(self):
            return self.getToken(SystemVerilogParser.KCLOCKING, 0)

        def clocking_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_clocking_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_clocking_declaration" ):
                listener.enterModport_clocking_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_clocking_declaration" ):
                listener.exitModport_clocking_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_clocking_declaration" ):
                return visitor.visitModport_clocking_declaration(self)
            else:
                return visitor.visitChildren(self)




    def modport_clocking_declaration(self):

        localctx = SystemVerilogParser.Modport_clocking_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 400, self.RULE_modport_clocking_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3837
            self.match(SystemVerilogParser.KCLOCKING)
            self.state = 3838
            self.clocking_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_simple_ports_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_directionContext,0)


        def modport_simple_port(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Modport_simple_portContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Modport_simple_portContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_simple_ports_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_simple_ports_declaration" ):
                listener.enterModport_simple_ports_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_simple_ports_declaration" ):
                listener.exitModport_simple_ports_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_simple_ports_declaration" ):
                return visitor.visitModport_simple_ports_declaration(self)
            else:
                return visitor.visitChildren(self)




    def modport_simple_ports_declaration(self):

        localctx = SystemVerilogParser.Modport_simple_ports_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 402, self.RULE_modport_simple_ports_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3840
            self.port_direction()
            self.state = 3841
            self.modport_simple_port()
            self.state = 3846
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,425,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3842
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 3843
                    self.modport_simple_port() 
                self.state = 3848
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,425,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_simple_portContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_simple_port

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_simple_port" ):
                listener.enterModport_simple_port(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_simple_port" ):
                listener.exitModport_simple_port(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_simple_port" ):
                return visitor.visitModport_simple_port(self)
            else:
                return visitor.visitChildren(self)




    def modport_simple_port(self):

        localctx = SystemVerilogParser.Modport_simple_portContext(self, self._ctx, self.state)
        self.enterRule(localctx, 404, self.RULE_modport_simple_port)
        self._la = 0 # Token type
        try:
            self.state = 3858
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3849
                self.port_identifier()
                pass
            elif token in [SystemVerilogParser.DOT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3850
                self.match(SystemVerilogParser.DOT)
                self.state = 3851
                self.port_identifier()
                self.state = 3852
                self.match(SystemVerilogParser.LP)
                self.state = 3854
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 3853
                    self.expression(0)


                self.state = 3856
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_tf_ports_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def import_export(self):
            return self.getTypedRuleContext(SystemVerilogParser.Import_exportContext,0)


        def modport_tf_port(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Modport_tf_portContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Modport_tf_portContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_tf_ports_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_tf_ports_declaration" ):
                listener.enterModport_tf_ports_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_tf_ports_declaration" ):
                listener.exitModport_tf_ports_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_tf_ports_declaration" ):
                return visitor.visitModport_tf_ports_declaration(self)
            else:
                return visitor.visitChildren(self)




    def modport_tf_ports_declaration(self):

        localctx = SystemVerilogParser.Modport_tf_ports_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 406, self.RULE_modport_tf_ports_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3860
            self.import_export()
            self.state = 3861
            self.modport_tf_port()
            self.state = 3866
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,428,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3862
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 3863
                    self.modport_tf_port() 
                self.state = 3868
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,428,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_tf_portContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def method_prototype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_prototypeContext,0)


        def tf_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_tf_port

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_tf_port" ):
                listener.enterModport_tf_port(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_tf_port" ):
                listener.exitModport_tf_port(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_tf_port" ):
                return visitor.visitModport_tf_port(self)
            else:
                return visitor.visitChildren(self)




    def modport_tf_port(self):

        localctx = SystemVerilogParser.Modport_tf_portContext(self, self._ctx, self.state)
        self.enterRule(localctx, 408, self.RULE_modport_tf_port)
        try:
            self.state = 3871
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KFUNCTION, SystemVerilogParser.KTASK]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3869
                self.method_prototype()
                pass
            elif token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3870
                self.tf_identifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Import_exportContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KIMPORT(self):
            return self.getToken(SystemVerilogParser.KIMPORT, 0)

        def KEXPORT(self):
            return self.getToken(SystemVerilogParser.KEXPORT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_import_export

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterImport_export" ):
                listener.enterImport_export(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitImport_export" ):
                listener.exitImport_export(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitImport_export" ):
                return visitor.visitImport_export(self)
            else:
                return visitor.visitChildren(self)




    def import_export(self):

        localctx = SystemVerilogParser.Import_exportContext(self, self._ctx, self.state)
        self.enterRule(localctx, 410, self.RULE_import_export)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3873
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KEXPORT or _la==SystemVerilogParser.KIMPORT):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Concurrent_assertion_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def concurrent_assertion_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Concurrent_assertion_statementContext,0)


        def block_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Block_identifierContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def checker_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_instantiationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_concurrent_assertion_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConcurrent_assertion_item" ):
                listener.enterConcurrent_assertion_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConcurrent_assertion_item" ):
                listener.exitConcurrent_assertion_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConcurrent_assertion_item" ):
                return visitor.visitConcurrent_assertion_item(self)
            else:
                return visitor.visitChildren(self)




    def concurrent_assertion_item(self):

        localctx = SystemVerilogParser.Concurrent_assertion_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 412, self.RULE_concurrent_assertion_item)
        self._la = 0 # Token type
        try:
            self.state = 3882
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,431,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3878
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 3875
                    self.block_identifier()
                    self.state = 3876
                    self.match(SystemVerilogParser.COLON)


                self.state = 3880
                self.concurrent_assertion_statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3881
                self.checker_instantiation()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Concurrent_assertion_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def assert_property_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assert_property_statementContext,0)


        def assume_property_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assume_property_statementContext,0)


        def cover_property_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cover_property_statementContext,0)


        def cover_sequence_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cover_sequence_statementContext,0)


        def restrict_property_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Restrict_property_statementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_concurrent_assertion_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConcurrent_assertion_statement" ):
                listener.enterConcurrent_assertion_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConcurrent_assertion_statement" ):
                listener.exitConcurrent_assertion_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConcurrent_assertion_statement" ):
                return visitor.visitConcurrent_assertion_statement(self)
            else:
                return visitor.visitChildren(self)




    def concurrent_assertion_statement(self):

        localctx = SystemVerilogParser.Concurrent_assertion_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 414, self.RULE_concurrent_assertion_statement)
        try:
            self.state = 3889
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,432,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3884
                self.assert_property_statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3885
                self.assume_property_statement()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3886
                self.cover_property_statement()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3887
                self.cover_sequence_statement()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 3888
                self.restrict_property_statement()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assert_property_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KASSERT(self):
            return self.getToken(SystemVerilogParser.KASSERT, 0)

        def KPROPERTY(self):
            return self.getToken(SystemVerilogParser.KPROPERTY, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def property_spec(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_specContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def action_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Action_blockContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assert_property_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssert_property_statement" ):
                listener.enterAssert_property_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssert_property_statement" ):
                listener.exitAssert_property_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssert_property_statement" ):
                return visitor.visitAssert_property_statement(self)
            else:
                return visitor.visitChildren(self)




    def assert_property_statement(self):

        localctx = SystemVerilogParser.Assert_property_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 416, self.RULE_assert_property_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3891
            self.match(SystemVerilogParser.KASSERT)
            self.state = 3892
            self.match(SystemVerilogParser.KPROPERTY)
            self.state = 3893
            self.match(SystemVerilogParser.LP)
            self.state = 3894
            self.property_spec()
            self.state = 3895
            self.match(SystemVerilogParser.RP)
            self.state = 3896
            self.action_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assume_property_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KASSUME(self):
            return self.getToken(SystemVerilogParser.KASSUME, 0)

        def KPROPERTY(self):
            return self.getToken(SystemVerilogParser.KPROPERTY, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def property_spec(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_specContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def action_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Action_blockContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assume_property_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssume_property_statement" ):
                listener.enterAssume_property_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssume_property_statement" ):
                listener.exitAssume_property_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssume_property_statement" ):
                return visitor.visitAssume_property_statement(self)
            else:
                return visitor.visitChildren(self)




    def assume_property_statement(self):

        localctx = SystemVerilogParser.Assume_property_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 418, self.RULE_assume_property_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3898
            self.match(SystemVerilogParser.KASSUME)
            self.state = 3899
            self.match(SystemVerilogParser.KPROPERTY)
            self.state = 3900
            self.match(SystemVerilogParser.LP)
            self.state = 3901
            self.property_spec()
            self.state = 3902
            self.match(SystemVerilogParser.RP)
            self.state = 3903
            self.action_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cover_property_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCOVER(self):
            return self.getToken(SystemVerilogParser.KCOVER, 0)

        def KPROPERTY(self):
            return self.getToken(SystemVerilogParser.KPROPERTY, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def property_spec(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_specContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cover_property_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCover_property_statement" ):
                listener.enterCover_property_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCover_property_statement" ):
                listener.exitCover_property_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCover_property_statement" ):
                return visitor.visitCover_property_statement(self)
            else:
                return visitor.visitChildren(self)




    def cover_property_statement(self):

        localctx = SystemVerilogParser.Cover_property_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 420, self.RULE_cover_property_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3905
            self.match(SystemVerilogParser.KCOVER)
            self.state = 3906
            self.match(SystemVerilogParser.KPROPERTY)
            self.state = 3907
            self.match(SystemVerilogParser.LP)
            self.state = 3908
            self.property_spec()
            self.state = 3909
            self.match(SystemVerilogParser.RP)
            self.state = 3910
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Expect_property_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KEXPECT(self):
            return self.getToken(SystemVerilogParser.KEXPECT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def property_spec(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_specContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def action_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Action_blockContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_expect_property_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExpect_property_statement" ):
                listener.enterExpect_property_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExpect_property_statement" ):
                listener.exitExpect_property_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExpect_property_statement" ):
                return visitor.visitExpect_property_statement(self)
            else:
                return visitor.visitChildren(self)




    def expect_property_statement(self):

        localctx = SystemVerilogParser.Expect_property_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 422, self.RULE_expect_property_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3912
            self.match(SystemVerilogParser.KEXPECT)
            self.state = 3913
            self.match(SystemVerilogParser.LP)
            self.state = 3914
            self.property_spec()
            self.state = 3915
            self.match(SystemVerilogParser.RP)
            self.state = 3916
            self.action_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cover_sequence_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCOVER(self):
            return self.getToken(SystemVerilogParser.KCOVER, 0)

        def KSEQUENCE(self):
            return self.getToken(SystemVerilogParser.KSEQUENCE, 0)

        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def sequence_expr(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_exprContext,0)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def clocking_event(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_eventContext,0)


        def KDISABLE(self):
            return self.getToken(SystemVerilogParser.KDISABLE, 0)

        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def expression_or_dist(self):
            return self.getTypedRuleContext(SystemVerilogParser.Expression_or_distContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cover_sequence_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCover_sequence_statement" ):
                listener.enterCover_sequence_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCover_sequence_statement" ):
                listener.exitCover_sequence_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCover_sequence_statement" ):
                return visitor.visitCover_sequence_statement(self)
            else:
                return visitor.visitChildren(self)




    def cover_sequence_statement(self):

        localctx = SystemVerilogParser.Cover_sequence_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 424, self.RULE_cover_sequence_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3918
            self.match(SystemVerilogParser.KCOVER)
            self.state = 3919
            self.match(SystemVerilogParser.KSEQUENCE)
            self.state = 3920
            self.match(SystemVerilogParser.LP)
            self.state = 3922
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,433,self._ctx)
            if la_ == 1:
                self.state = 3921
                self.clocking_event()


            self.state = 3930
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KDISABLE:
                self.state = 3924
                self.match(SystemVerilogParser.KDISABLE)
                self.state = 3925
                self.match(SystemVerilogParser.KIFF)
                self.state = 3926
                self.match(SystemVerilogParser.LP)
                self.state = 3927
                self.expression_or_dist()
                self.state = 3928
                self.match(SystemVerilogParser.RP)


            self.state = 3932
            self.sequence_expr(0)
            self.state = 3933
            self.match(SystemVerilogParser.RP)
            self.state = 3934
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Restrict_property_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KRESTRICT(self):
            return self.getToken(SystemVerilogParser.KRESTRICT, 0)

        def KPROPERTY(self):
            return self.getToken(SystemVerilogParser.KPROPERTY, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def property_spec(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_specContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_restrict_property_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRestrict_property_statement" ):
                listener.enterRestrict_property_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRestrict_property_statement" ):
                listener.exitRestrict_property_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRestrict_property_statement" ):
                return visitor.visitRestrict_property_statement(self)
            else:
                return visitor.visitChildren(self)




    def restrict_property_statement(self):

        localctx = SystemVerilogParser.Restrict_property_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 426, self.RULE_restrict_property_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3936
            self.match(SystemVerilogParser.KRESTRICT)
            self.state = 3937
            self.match(SystemVerilogParser.KPROPERTY)
            self.state = 3938
            self.match(SystemVerilogParser.LP)
            self.state = 3939
            self.property_spec()
            self.state = 3940
            self.match(SystemVerilogParser.RP)
            self.state = 3941
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ps_or_hierarchical_property_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_or_hierarchical_property_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def property_list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_list_of_argumentsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_instance" ):
                listener.enterProperty_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_instance" ):
                listener.exitProperty_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_instance" ):
                return visitor.visitProperty_instance(self)
            else:
                return visitor.visitChildren(self)




    def property_instance(self):

        localctx = SystemVerilogParser.Property_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 428, self.RULE_property_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3943
            self.ps_or_hierarchical_property_identifier()
            self.state = 3949
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,436,self._ctx)
            if la_ == 1:
                self.state = 3944
                self.match(SystemVerilogParser.LP)
                self.state = 3946
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,435,self._ctx)
                if la_ == 1:
                    self.state = 3945
                    self.property_list_of_arguments()


                self.state = 3948
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_list_of_argumentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.IdentifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,i)


        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def property_actual_arg(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Property_actual_argContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Property_actual_argContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_list_of_arguments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_list_of_arguments" ):
                listener.enterProperty_list_of_arguments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_list_of_arguments" ):
                listener.exitProperty_list_of_arguments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_list_of_arguments" ):
                return visitor.visitProperty_list_of_arguments(self)
            else:
                return visitor.visitChildren(self)




    def property_list_of_arguments(self):

        localctx = SystemVerilogParser.Property_list_of_argumentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 430, self.RULE_property_list_of_arguments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3971
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.PP, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.RP, SystemVerilogParser.COMMA, SystemVerilogParser.AT, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KACCEPT_ON, SystemVerilogParser.KALWAYS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCASE, SystemVerilogParser.KCONST, SystemVerilogParser.KEDGE, SystemVerilogParser.KEVENTUALLY, SystemVerilogParser.KFIRST_MATCH, SystemVerilogParser.KIF, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNEGEDGE, SystemVerilogParser.KNEXTTIME, SystemVerilogParser.KNOT, SystemVerilogParser.KNULL, SystemVerilogParser.KPOSEDGE, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KREJECT_ON, SystemVerilogParser.KS_ALWAYS, SystemVerilogParser.KS_EVENTUALLY, SystemVerilogParser.KS_NEXTTIME, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRONG, SystemVerilogParser.KSUPER, SystemVerilogParser.KSYNC_ACCEPT_ON, SystemVerilogParser.KSYNC_REJECT_ON, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KWEAK, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.state = 3952
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KACCEPT_ON - 64)) | (1 << (SystemVerilogParser.KALWAYS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCASE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KEVENTUALLY - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KIF - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNEXTTIME - 207)) | (1 << (SystemVerilogParser.KNOT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)) | (1 << (SystemVerilogParser.KREJECT_ON - 207)) | (1 << (SystemVerilogParser.KS_ALWAYS - 207)) | (1 << (SystemVerilogParser.KS_EVENTUALLY - 207)))) != 0) or ((((_la - 271)) & ~0x3f) == 0 and ((1 << (_la - 271)) & ((1 << (SystemVerilogParser.KS_NEXTTIME - 271)) | (1 << (SystemVerilogParser.KSHORTINT - 271)) | (1 << (SystemVerilogParser.KSHORTREAL - 271)) | (1 << (SystemVerilogParser.KSIGNED - 271)) | (1 << (SystemVerilogParser.KSTD - 271)) | (1 << (SystemVerilogParser.KSTRING - 271)) | (1 << (SystemVerilogParser.KSTRONG - 271)) | (1 << (SystemVerilogParser.KSUPER - 271)) | (1 << (SystemVerilogParser.KSYNC_ACCEPT_ON - 271)) | (1 << (SystemVerilogParser.KSYNC_REJECT_ON - 271)) | (1 << (SystemVerilogParser.KTAGGED - 271)) | (1 << (SystemVerilogParser.KTHIS - 271)) | (1 << (SystemVerilogParser.KTIME - 271)) | (1 << (SystemVerilogParser.KTYPE - 271)) | (1 << (SystemVerilogParser.KUNSIGNED - 271)) | (1 << (SystemVerilogParser.KWEAK - 271)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 3951
                    self.property_actual_arg()


                self.state = 3960
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,439,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 3954
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 3956
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KACCEPT_ON - 64)) | (1 << (SystemVerilogParser.KALWAYS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCASE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KEVENTUALLY - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KIF - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNEXTTIME - 207)) | (1 << (SystemVerilogParser.KNOT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)) | (1 << (SystemVerilogParser.KREJECT_ON - 207)) | (1 << (SystemVerilogParser.KS_ALWAYS - 207)) | (1 << (SystemVerilogParser.KS_EVENTUALLY - 207)))) != 0) or ((((_la - 271)) & ~0x3f) == 0 and ((1 << (_la - 271)) & ((1 << (SystemVerilogParser.KS_NEXTTIME - 271)) | (1 << (SystemVerilogParser.KSHORTINT - 271)) | (1 << (SystemVerilogParser.KSHORTREAL - 271)) | (1 << (SystemVerilogParser.KSIGNED - 271)) | (1 << (SystemVerilogParser.KSTD - 271)) | (1 << (SystemVerilogParser.KSTRING - 271)) | (1 << (SystemVerilogParser.KSTRONG - 271)) | (1 << (SystemVerilogParser.KSUPER - 271)) | (1 << (SystemVerilogParser.KSYNC_ACCEPT_ON - 271)) | (1 << (SystemVerilogParser.KSYNC_REJECT_ON - 271)) | (1 << (SystemVerilogParser.KTAGGED - 271)) | (1 << (SystemVerilogParser.KTHIS - 271)) | (1 << (SystemVerilogParser.KTIME - 271)) | (1 << (SystemVerilogParser.KTYPE - 271)) | (1 << (SystemVerilogParser.KUNSIGNED - 271)) | (1 << (SystemVerilogParser.KWEAK - 271)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                            self.state = 3955
                            self.property_actual_arg()

                 
                    self.state = 3962
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,439,self._ctx)

                pass
            elif token in [SystemVerilogParser.DOT]:
                self.state = 3963
                self.match(SystemVerilogParser.DOT)
                self.state = 3964
                self.identifier()
                self.state = 3965
                self.match(SystemVerilogParser.LP)
                self.state = 3967
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KACCEPT_ON - 64)) | (1 << (SystemVerilogParser.KALWAYS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCASE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KEVENTUALLY - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KIF - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNEXTTIME - 207)) | (1 << (SystemVerilogParser.KNOT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)) | (1 << (SystemVerilogParser.KREJECT_ON - 207)) | (1 << (SystemVerilogParser.KS_ALWAYS - 207)) | (1 << (SystemVerilogParser.KS_EVENTUALLY - 207)))) != 0) or ((((_la - 271)) & ~0x3f) == 0 and ((1 << (_la - 271)) & ((1 << (SystemVerilogParser.KS_NEXTTIME - 271)) | (1 << (SystemVerilogParser.KSHORTINT - 271)) | (1 << (SystemVerilogParser.KSHORTREAL - 271)) | (1 << (SystemVerilogParser.KSIGNED - 271)) | (1 << (SystemVerilogParser.KSTD - 271)) | (1 << (SystemVerilogParser.KSTRING - 271)) | (1 << (SystemVerilogParser.KSTRONG - 271)) | (1 << (SystemVerilogParser.KSUPER - 271)) | (1 << (SystemVerilogParser.KSYNC_ACCEPT_ON - 271)) | (1 << (SystemVerilogParser.KSYNC_REJECT_ON - 271)) | (1 << (SystemVerilogParser.KTAGGED - 271)) | (1 << (SystemVerilogParser.KTHIS - 271)) | (1 << (SystemVerilogParser.KTIME - 271)) | (1 << (SystemVerilogParser.KTYPE - 271)) | (1 << (SystemVerilogParser.KUNSIGNED - 271)) | (1 << (SystemVerilogParser.KWEAK - 271)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 3966
                    self.property_actual_arg()


                self.state = 3969
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

            self.state = 3984
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 3973
                self.match(SystemVerilogParser.COMMA)
                self.state = 3974
                self.match(SystemVerilogParser.DOT)
                self.state = 3975
                self.identifier()
                self.state = 3976
                self.match(SystemVerilogParser.LP)
                self.state = 3978
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KACCEPT_ON - 64)) | (1 << (SystemVerilogParser.KALWAYS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCASE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KEVENTUALLY - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KIF - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNEXTTIME - 207)) | (1 << (SystemVerilogParser.KNOT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)) | (1 << (SystemVerilogParser.KREJECT_ON - 207)) | (1 << (SystemVerilogParser.KS_ALWAYS - 207)) | (1 << (SystemVerilogParser.KS_EVENTUALLY - 207)))) != 0) or ((((_la - 271)) & ~0x3f) == 0 and ((1 << (_la - 271)) & ((1 << (SystemVerilogParser.KS_NEXTTIME - 271)) | (1 << (SystemVerilogParser.KSHORTINT - 271)) | (1 << (SystemVerilogParser.KSHORTREAL - 271)) | (1 << (SystemVerilogParser.KSIGNED - 271)) | (1 << (SystemVerilogParser.KSTD - 271)) | (1 << (SystemVerilogParser.KSTRING - 271)) | (1 << (SystemVerilogParser.KSTRONG - 271)) | (1 << (SystemVerilogParser.KSUPER - 271)) | (1 << (SystemVerilogParser.KSYNC_ACCEPT_ON - 271)) | (1 << (SystemVerilogParser.KSYNC_REJECT_ON - 271)) | (1 << (SystemVerilogParser.KTAGGED - 271)) | (1 << (SystemVerilogParser.KTHIS - 271)) | (1 << (SystemVerilogParser.KTIME - 271)) | (1 << (SystemVerilogParser.KTYPE - 271)) | (1 << (SystemVerilogParser.KUNSIGNED - 271)) | (1 << (SystemVerilogParser.KWEAK - 271)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 3977
                    self.property_actual_arg()


                self.state = 3980
                self.match(SystemVerilogParser.RP)
                self.state = 3986
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_actual_argContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def property_expr(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_exprContext,0)


        def sequence_actual_arg(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_actual_argContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_actual_arg

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_actual_arg" ):
                listener.enterProperty_actual_arg(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_actual_arg" ):
                listener.exitProperty_actual_arg(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_actual_arg" ):
                return visitor.visitProperty_actual_arg(self)
            else:
                return visitor.visitChildren(self)




    def property_actual_arg(self):

        localctx = SystemVerilogParser.Property_actual_argContext(self, self._ctx, self.state)
        self.enterRule(localctx, 432, self.RULE_property_actual_arg)
        try:
            self.state = 3989
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,444,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3987
                self.property_expr(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3988
                self.sequence_actual_arg()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assertion_item_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def property_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_declarationContext,0)


        def sequence_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_declarationContext,0)


        def let_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assertion_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssertion_item_declaration" ):
                listener.enterAssertion_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssertion_item_declaration" ):
                listener.exitAssertion_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssertion_item_declaration" ):
                return visitor.visitAssertion_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def assertion_item_declaration(self):

        localctx = SystemVerilogParser.Assertion_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 434, self.RULE_assertion_item_declaration)
        try:
            self.state = 3994
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KPROPERTY]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3991
                self.property_declaration()
                pass
            elif token in [SystemVerilogParser.KSEQUENCE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3992
                self.sequence_declaration()
                pass
            elif token in [SystemVerilogParser.KLET]:
                self.enterOuterAlt(localctx, 3)
                self.state = 3993
                self.let_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPROPERTY(self):
            return self.getToken(SystemVerilogParser.KPROPERTY, 0)

        def property_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Property_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Property_identifierContext,i)


        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def property_spec(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_specContext,0)


        def KENDPROPERTY(self):
            return self.getToken(SystemVerilogParser.KENDPROPERTY, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def assertion_variable_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Assertion_variable_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Assertion_variable_declarationContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def property_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_declaration" ):
                listener.enterProperty_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_declaration" ):
                listener.exitProperty_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_declaration" ):
                return visitor.visitProperty_declaration(self)
            else:
                return visitor.visitChildren(self)




    def property_declaration(self):

        localctx = SystemVerilogParser.Property_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 436, self.RULE_property_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3996
            self.match(SystemVerilogParser.KPROPERTY)
            self.state = 3997
            self.property_identifier()
            self.state = 4003
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 3998
                self.match(SystemVerilogParser.LP)
                self.state = 4000
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KPROPERTY - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 275)) & ~0x3f) == 0 and ((1 << (_la - 275)) & ((1 << (SystemVerilogParser.KSEQUENCE - 275)) | (1 << (SystemVerilogParser.KSHORTINT - 275)) | (1 << (SystemVerilogParser.KSHORTREAL - 275)) | (1 << (SystemVerilogParser.KSIGNED - 275)) | (1 << (SystemVerilogParser.KSTRING - 275)) | (1 << (SystemVerilogParser.KSTRUCT - 275)) | (1 << (SystemVerilogParser.KTIME - 275)) | (1 << (SystemVerilogParser.KTYPE - 275)) | (1 << (SystemVerilogParser.KUNION - 275)) | (1 << (SystemVerilogParser.KUNSIGNED - 275)) | (1 << (SystemVerilogParser.KUNTYPED - 275)) | (1 << (SystemVerilogParser.KVIRTUAL - 275)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 3999
                    self.property_port_list()


                self.state = 4002
                self.match(SystemVerilogParser.RP)


            self.state = 4005
            self.match(SystemVerilogParser.SEMI)
            self.state = 4009
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,448,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 4006
                    self.assertion_variable_declaration() 
                self.state = 4011
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,448,self._ctx)

            self.state = 4012
            self.property_spec()
            self.state = 4014
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SEMI:
                self.state = 4013
                self.match(SystemVerilogParser.SEMI)


            self.state = 4016
            self.match(SystemVerilogParser.KENDPROPERTY)
            self.state = 4019
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 4017
                self.match(SystemVerilogParser.COLON)
                self.state = 4018
                self.property_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def property_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Property_port_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Property_port_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_port_list" ):
                listener.enterProperty_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_port_list" ):
                listener.exitProperty_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_port_list" ):
                return visitor.visitProperty_port_list(self)
            else:
                return visitor.visitChildren(self)




    def property_port_list(self):

        localctx = SystemVerilogParser.Property_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 438, self.RULE_property_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4021
            self.property_port_item()
            self.state = 4026
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 4022
                self.match(SystemVerilogParser.COMMA)
                self.state = 4023
                self.property_port_item()
                self.state = 4028
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_port_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def property_formal_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_formal_typeContext,0)


        def formal_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Formal_port_identifierContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def KLOCAL(self):
            return self.getToken(SystemVerilogParser.KLOCAL, 0)

        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def property_actual_arg(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_actual_argContext,0)


        def property_lvar_port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_lvar_port_directionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_port_item" ):
                listener.enterProperty_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_port_item" ):
                listener.exitProperty_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_port_item" ):
                return visitor.visitProperty_port_item(self)
            else:
                return visitor.visitChildren(self)




    def property_port_item(self):

        localctx = SystemVerilogParser.Property_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 440, self.RULE_property_port_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4032
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 4029
                self.attribute_instance()
                self.state = 4034
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4039
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KLOCAL:
                self.state = 4035
                self.match(SystemVerilogParser.KLOCAL)
                self.state = 4037
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KINPUT:
                    self.state = 4036
                    self.property_lvar_port_direction()




            self.state = 4041
            self.property_formal_type()
            self.state = 4042
            self.formal_port_identifier()
            self.state = 4046
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 4043
                self.variable_dimension()
                self.state = 4048
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4051
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 4049
                self.match(SystemVerilogParser.EQ)
                self.state = 4050
                self.property_actual_arg()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_lvar_port_directionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINPUT(self):
            return self.getToken(SystemVerilogParser.KINPUT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_lvar_port_direction

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_lvar_port_direction" ):
                listener.enterProperty_lvar_port_direction(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_lvar_port_direction" ):
                listener.exitProperty_lvar_port_direction(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_lvar_port_direction" ):
                return visitor.visitProperty_lvar_port_direction(self)
            else:
                return visitor.visitChildren(self)




    def property_lvar_port_direction(self):

        localctx = SystemVerilogParser.Property_lvar_port_directionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 442, self.RULE_property_lvar_port_direction)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4053
            self.match(SystemVerilogParser.KINPUT)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_formal_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def sequence_formal_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_formal_typeContext,0)


        def KPROPERTY(self):
            return self.getToken(SystemVerilogParser.KPROPERTY, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_formal_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_formal_type" ):
                listener.enterProperty_formal_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_formal_type" ):
                listener.exitProperty_formal_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_formal_type" ):
                return visitor.visitProperty_formal_type(self)
            else:
                return visitor.visitChildren(self)




    def property_formal_type(self):

        localctx = SystemVerilogParser.Property_formal_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 444, self.RULE_property_formal_type)
        try:
            self.state = 4057
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.LB, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSEQUENCE, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KUNTYPED, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4055
                self.sequence_formal_type()
                pass
            elif token in [SystemVerilogParser.KPROPERTY]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4056
                self.match(SystemVerilogParser.KPROPERTY)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_specContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def property_expr(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_exprContext,0)


        def clocking_event(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_eventContext,0)


        def KDISABLE(self):
            return self.getToken(SystemVerilogParser.KDISABLE, 0)

        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression_or_dist(self):
            return self.getTypedRuleContext(SystemVerilogParser.Expression_or_distContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_spec

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_spec" ):
                listener.enterProperty_spec(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_spec" ):
                listener.exitProperty_spec(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_spec" ):
                return visitor.visitProperty_spec(self)
            else:
                return visitor.visitChildren(self)




    def property_spec(self):

        localctx = SystemVerilogParser.Property_specContext(self, self._ctx, self.state)
        self.enterRule(localctx, 446, self.RULE_property_spec)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4060
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,458,self._ctx)
            if la_ == 1:
                self.state = 4059
                self.clocking_event()


            self.state = 4068
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KDISABLE:
                self.state = 4062
                self.match(SystemVerilogParser.KDISABLE)
                self.state = 4063
                self.match(SystemVerilogParser.KIFF)
                self.state = 4064
                self.match(SystemVerilogParser.LP)
                self.state = 4065
                self.expression_or_dist()
                self.state = 4066
                self.match(SystemVerilogParser.RP)


            self.state = 4070
            self.property_expr(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_exprContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def sequence_expr(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_exprContext,0)


        def property_expr(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Property_exprContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Property_exprContext,i)


        def BARARROW(self):
            return self.getToken(SystemVerilogParser.BARARROW, 0)

        def BAREQGT(self):
            return self.getToken(SystemVerilogParser.BAREQGT, 0)

        def PMP(self):
            return self.getToken(SystemVerilogParser.PMP, 0)

        def PEP(self):
            return self.getToken(SystemVerilogParser.PEP, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def KSTRONG(self):
            return self.getToken(SystemVerilogParser.KSTRONG, 0)

        def KWEAK(self):
            return self.getToken(SystemVerilogParser.KWEAK, 0)

        def KNOT(self):
            return self.getToken(SystemVerilogParser.KNOT, 0)

        def KIF(self):
            return self.getToken(SystemVerilogParser.KIF, 0)

        def expression_or_dist(self):
            return self.getTypedRuleContext(SystemVerilogParser.Expression_or_distContext,0)


        def KELSE(self):
            return self.getToken(SystemVerilogParser.KELSE, 0)

        def KCASE(self):
            return self.getToken(SystemVerilogParser.KCASE, 0)

        def property_case_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Property_case_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Property_case_itemContext,i)


        def KENDCASE(self):
            return self.getToken(SystemVerilogParser.KENDCASE, 0)

        def KNEXTTIME(self):
            return self.getToken(SystemVerilogParser.KNEXTTIME, 0)

        def KS_NEXTTIME(self):
            return self.getToken(SystemVerilogParser.KS_NEXTTIME, 0)

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def KALWAYS(self):
            return self.getToken(SystemVerilogParser.KALWAYS, 0)

        def KS_EVENTUALLY(self):
            return self.getToken(SystemVerilogParser.KS_EVENTUALLY, 0)

        def cycle_delay_const_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cycle_delay_const_range_expressionContext,0)


        def constant_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_rangeContext,0)


        def KS_ALWAYS(self):
            return self.getToken(SystemVerilogParser.KS_ALWAYS, 0)

        def KEVENTUALLY(self):
            return self.getToken(SystemVerilogParser.KEVENTUALLY, 0)

        def KACCEPT_ON(self):
            return self.getToken(SystemVerilogParser.KACCEPT_ON, 0)

        def KREJECT_ON(self):
            return self.getToken(SystemVerilogParser.KREJECT_ON, 0)

        def KSYNC_ACCEPT_ON(self):
            return self.getToken(SystemVerilogParser.KSYNC_ACCEPT_ON, 0)

        def KSYNC_REJECT_ON(self):
            return self.getToken(SystemVerilogParser.KSYNC_REJECT_ON, 0)

        def property_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_instanceContext,0)


        def clocking_event(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_eventContext,0)


        def KOR(self):
            return self.getToken(SystemVerilogParser.KOR, 0)

        def KAND(self):
            return self.getToken(SystemVerilogParser.KAND, 0)

        def KUNTIL(self):
            return self.getToken(SystemVerilogParser.KUNTIL, 0)

        def KS_UNTIL(self):
            return self.getToken(SystemVerilogParser.KS_UNTIL, 0)

        def KUNTIL_WITH(self):
            return self.getToken(SystemVerilogParser.KUNTIL_WITH, 0)

        def KS_UNTIL_WITH(self):
            return self.getToken(SystemVerilogParser.KS_UNTIL_WITH, 0)

        def KIMPLIES(self):
            return self.getToken(SystemVerilogParser.KIMPLIES, 0)

        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_expr

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_expr" ):
                listener.enterProperty_expr(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_expr" ):
                listener.exitProperty_expr(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_expr" ):
                return visitor.visitProperty_expr(self)
            else:
                return visitor.visitChildren(self)



    def property_expr(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = SystemVerilogParser.Property_exprContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 448
        self.enterRecursionRule(localctx, 448, self.RULE_property_expr, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4143
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,465,self._ctx)
            if la_ == 1:
                self.state = 4073
                self.sequence_expr(0)
                self.state = 4076
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,460,self._ctx)
                if la_ == 1:
                    self.state = 4074
                    _la = self._input.LA(1)
                    if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.PMP) | (1 << SystemVerilogParser.PEP) | (1 << SystemVerilogParser.BAREQGT) | (1 << SystemVerilogParser.BARARROW))) != 0)):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()
                    self.state = 4075
                    self.property_expr(0)


                pass

            elif la_ == 2:
                self.state = 4078
                _la = self._input.LA(1)
                if not(_la==SystemVerilogParser.KSTRONG or _la==SystemVerilogParser.KWEAK):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 4079
                self.match(SystemVerilogParser.LP)
                self.state = 4080
                self.sequence_expr(0)
                self.state = 4081
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 3:
                self.state = 4083
                self.match(SystemVerilogParser.LP)
                self.state = 4084
                self.property_expr(0)
                self.state = 4085
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 4:
                self.state = 4087
                self.match(SystemVerilogParser.KNOT)
                self.state = 4088
                self.property_expr(10)
                pass

            elif la_ == 5:
                self.state = 4089
                self.match(SystemVerilogParser.KIF)
                self.state = 4090
                self.match(SystemVerilogParser.LP)
                self.state = 4091
                self.expression_or_dist()
                self.state = 4092
                self.match(SystemVerilogParser.RP)
                self.state = 4093
                self.property_expr(0)
                self.state = 4096
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,461,self._ctx)
                if la_ == 1:
                    self.state = 4094
                    self.match(SystemVerilogParser.KELSE)
                    self.state = 4095
                    self.property_expr(0)


                pass

            elif la_ == 6:
                self.state = 4098
                self.match(SystemVerilogParser.KCASE)
                self.state = 4099
                self.match(SystemVerilogParser.LP)
                self.state = 4100
                self.expression_or_dist()
                self.state = 4101
                self.match(SystemVerilogParser.RP)
                self.state = 4102
                self.property_case_item()
                self.state = 4106
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 134)) & ~0x3f) == 0 and ((1 << (_la - 134)) & ((1 << (SystemVerilogParser.KDEFAULT - 134)) | (1 << (SystemVerilogParser.KINT - 134)) | (1 << (SystemVerilogParser.KINTEGER - 134)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 4103
                    self.property_case_item()
                    self.state = 4108
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4109
                self.match(SystemVerilogParser.KENDCASE)
                pass

            elif la_ == 7:
                self.state = 4111
                _la = self._input.LA(1)
                if not(_la==SystemVerilogParser.KNEXTTIME or _la==SystemVerilogParser.KS_NEXTTIME):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 4116
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LB:
                    self.state = 4112
                    self.match(SystemVerilogParser.LB)
                    self.state = 4113
                    self.constant_expression(0)
                    self.state = 4114
                    self.match(SystemVerilogParser.RB)


                self.state = 4118
                self.property_expr(6)
                pass

            elif la_ == 8:
                self.state = 4119
                _la = self._input.LA(1)
                if not(_la==SystemVerilogParser.KALWAYS or _la==SystemVerilogParser.KS_EVENTUALLY):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 4124
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LB:
                    self.state = 4120
                    self.match(SystemVerilogParser.LB)
                    self.state = 4121
                    self.cycle_delay_const_range_expression()
                    self.state = 4122
                    self.match(SystemVerilogParser.RB)


                self.state = 4126
                self.property_expr(5)
                pass

            elif la_ == 9:
                self.state = 4127
                _la = self._input.LA(1)
                if not(_la==SystemVerilogParser.KEVENTUALLY or _la==SystemVerilogParser.KS_ALWAYS):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 4128
                self.match(SystemVerilogParser.LB)
                self.state = 4129
                self.constant_range()
                self.state = 4130
                self.match(SystemVerilogParser.RB)
                self.state = 4131
                self.property_expr(4)
                pass

            elif la_ == 10:
                self.state = 4133
                _la = self._input.LA(1)
                if not(_la==SystemVerilogParser.KACCEPT_ON or ((((_la - 259)) & ~0x3f) == 0 and ((1 << (_la - 259)) & ((1 << (SystemVerilogParser.KREJECT_ON - 259)) | (1 << (SystemVerilogParser.KSYNC_ACCEPT_ON - 259)) | (1 << (SystemVerilogParser.KSYNC_REJECT_ON - 259)))) != 0)):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 4134
                self.match(SystemVerilogParser.LP)
                self.state = 4135
                self.expression_or_dist()
                self.state = 4136
                self.match(SystemVerilogParser.RP)
                self.state = 4137
                self.property_expr(3)
                pass

            elif la_ == 11:
                self.state = 4139
                self.property_instance()
                pass

            elif la_ == 12:
                self.state = 4140
                self.clocking_event()
                self.state = 4141
                self.property_expr(1)
                pass


            self._ctx.stop = self._input.LT(-1)
            self.state = 4150
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,466,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    localctx = SystemVerilogParser.Property_exprContext(self, _parentctx, _parentState)
                    self.pushNewRecursionContext(localctx, _startState, self.RULE_property_expr)
                    self.state = 4145
                    if not self.precpred(self._ctx, 9):
                        from antlr4.error.Errors import FailedPredicateException
                        raise FailedPredicateException(self, "self.precpred(self._ctx, 9)")
                    self.state = 4146
                    _la = self._input.LA(1)
                    if not(((((_la - 60)) & ~0x3f) == 0 and ((1 << (_la - 60)) & ((1 << (SystemVerilogParser.BAREQGT - 60)) | (1 << (SystemVerilogParser.BARARROW - 60)) | (1 << (SystemVerilogParser.KAND - 60)))) != 0) or ((((_la - 181)) & ~0x3f) == 0 and ((1 << (_la - 181)) & ((1 << (SystemVerilogParser.KIFF - 181)) | (1 << (SystemVerilogParser.KIMPLIES - 181)) | (1 << (SystemVerilogParser.KOR - 181)))) != 0) or ((((_la - 272)) & ~0x3f) == 0 and ((1 << (_la - 272)) & ((1 << (SystemVerilogParser.KS_UNTIL - 272)) | (1 << (SystemVerilogParser.KS_UNTIL_WITH - 272)) | (1 << (SystemVerilogParser.KUNTIL - 272)) | (1 << (SystemVerilogParser.KUNTIL_WITH - 272)))) != 0)):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()
                    self.state = 4147
                    self.property_expr(10) 
                self.state = 4152
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,466,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Property_case_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression_or_dist(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Expression_or_distContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Expression_or_distContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def property_expr(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_exprContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_case_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_case_item" ):
                listener.enterProperty_case_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_case_item" ):
                listener.exitProperty_case_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_case_item" ):
                return visitor.visitProperty_case_item(self)
            else:
                return visitor.visitChildren(self)




    def property_case_item(self):

        localctx = SystemVerilogParser.Property_case_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 450, self.RULE_property_case_item)
        self._la = 0 # Token type
        try:
            self.state = 4172
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4153
                self.expression_or_dist()
                self.state = 4158
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4154
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4155
                    self.expression_or_dist()
                    self.state = 4160
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4161
                self.match(SystemVerilogParser.COLON)
                self.state = 4162
                self.property_expr(0)
                self.state = 4163
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4165
                self.match(SystemVerilogParser.KDEFAULT)
                self.state = 4167
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 4166
                    self.match(SystemVerilogParser.COLON)


                self.state = 4169
                self.property_expr(0)
                self.state = 4170
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSEQUENCE(self):
            return self.getToken(SystemVerilogParser.KSEQUENCE, 0)

        def sequence_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Sequence_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Sequence_identifierContext,i)


        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def sequence_expr(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_exprContext,0)


        def KENDSEQUENCE(self):
            return self.getToken(SystemVerilogParser.KENDSEQUENCE, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def assertion_variable_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Assertion_variable_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Assertion_variable_declarationContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def sequence_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_declaration" ):
                listener.enterSequence_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_declaration" ):
                listener.exitSequence_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_declaration" ):
                return visitor.visitSequence_declaration(self)
            else:
                return visitor.visitChildren(self)




    def sequence_declaration(self):

        localctx = SystemVerilogParser.Sequence_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 452, self.RULE_sequence_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4174
            self.match(SystemVerilogParser.KSEQUENCE)
            self.state = 4175
            self.sequence_identifier()
            self.state = 4181
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 4176
                self.match(SystemVerilogParser.LP)
                self.state = 4178
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 275)) & ~0x3f) == 0 and ((1 << (_la - 275)) & ((1 << (SystemVerilogParser.KSEQUENCE - 275)) | (1 << (SystemVerilogParser.KSHORTINT - 275)) | (1 << (SystemVerilogParser.KSHORTREAL - 275)) | (1 << (SystemVerilogParser.KSIGNED - 275)) | (1 << (SystemVerilogParser.KSTRING - 275)) | (1 << (SystemVerilogParser.KSTRUCT - 275)) | (1 << (SystemVerilogParser.KTIME - 275)) | (1 << (SystemVerilogParser.KTYPE - 275)) | (1 << (SystemVerilogParser.KUNION - 275)) | (1 << (SystemVerilogParser.KUNSIGNED - 275)) | (1 << (SystemVerilogParser.KUNTYPED - 275)) | (1 << (SystemVerilogParser.KVIRTUAL - 275)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 4177
                    self.sequence_port_list()


                self.state = 4180
                self.match(SystemVerilogParser.RP)


            self.state = 4183
            self.match(SystemVerilogParser.SEMI)
            self.state = 4187
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,472,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 4184
                    self.assertion_variable_declaration() 
                self.state = 4189
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,472,self._ctx)

            self.state = 4190
            self.sequence_expr(0)
            self.state = 4192
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SEMI:
                self.state = 4191
                self.match(SystemVerilogParser.SEMI)


            self.state = 4194
            self.match(SystemVerilogParser.KENDSEQUENCE)
            self.state = 4197
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 4195
                self.match(SystemVerilogParser.COLON)
                self.state = 4196
                self.sequence_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def sequence_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Sequence_port_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Sequence_port_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_port_list" ):
                listener.enterSequence_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_port_list" ):
                listener.exitSequence_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_port_list" ):
                return visitor.visitSequence_port_list(self)
            else:
                return visitor.visitChildren(self)




    def sequence_port_list(self):

        localctx = SystemVerilogParser.Sequence_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 454, self.RULE_sequence_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4199
            self.sequence_port_item()
            self.state = 4204
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 4200
                self.match(SystemVerilogParser.COMMA)
                self.state = 4201
                self.sequence_port_item()
                self.state = 4206
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_port_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def sequence_formal_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_formal_typeContext,0)


        def formal_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Formal_port_identifierContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def KLOCAL(self):
            return self.getToken(SystemVerilogParser.KLOCAL, 0)

        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def sequence_actual_arg(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_actual_argContext,0)


        def sequence_lvar_port_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_lvar_port_directionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_port_item" ):
                listener.enterSequence_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_port_item" ):
                listener.exitSequence_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_port_item" ):
                return visitor.visitSequence_port_item(self)
            else:
                return visitor.visitChildren(self)




    def sequence_port_item(self):

        localctx = SystemVerilogParser.Sequence_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 456, self.RULE_sequence_port_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4210
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 4207
                self.attribute_instance()
                self.state = 4212
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4217
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KLOCAL:
                self.state = 4213
                self.match(SystemVerilogParser.KLOCAL)
                self.state = 4215
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if ((((_la - 191)) & ~0x3f) == 0 and ((1 << (_la - 191)) & ((1 << (SystemVerilogParser.KINOUT - 191)) | (1 << (SystemVerilogParser.KINPUT - 191)) | (1 << (SystemVerilogParser.KOUTPUT - 191)))) != 0):
                    self.state = 4214
                    self.sequence_lvar_port_direction()




            self.state = 4219
            self.sequence_formal_type()
            self.state = 4220
            self.formal_port_identifier()
            self.state = 4224
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 4221
                self.variable_dimension()
                self.state = 4226
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4229
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 4227
                self.match(SystemVerilogParser.EQ)
                self.state = 4228
                self.sequence_actual_arg()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_lvar_port_directionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINPUT(self):
            return self.getToken(SystemVerilogParser.KINPUT, 0)

        def KINOUT(self):
            return self.getToken(SystemVerilogParser.KINOUT, 0)

        def KOUTPUT(self):
            return self.getToken(SystemVerilogParser.KOUTPUT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_lvar_port_direction

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_lvar_port_direction" ):
                listener.enterSequence_lvar_port_direction(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_lvar_port_direction" ):
                listener.exitSequence_lvar_port_direction(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_lvar_port_direction" ):
                return visitor.visitSequence_lvar_port_direction(self)
            else:
                return visitor.visitChildren(self)




    def sequence_lvar_port_direction(self):

        localctx = SystemVerilogParser.Sequence_lvar_port_directionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 458, self.RULE_sequence_lvar_port_direction)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4231
            _la = self._input.LA(1)
            if not(((((_la - 191)) & ~0x3f) == 0 and ((1 << (_la - 191)) & ((1 << (SystemVerilogParser.KINOUT - 191)) | (1 << (SystemVerilogParser.KINPUT - 191)) | (1 << (SystemVerilogParser.KOUTPUT - 191)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_formal_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def KSEQUENCE(self):
            return self.getToken(SystemVerilogParser.KSEQUENCE, 0)

        def KUNTYPED(self):
            return self.getToken(SystemVerilogParser.KUNTYPED, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_formal_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_formal_type" ):
                listener.enterSequence_formal_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_formal_type" ):
                listener.exitSequence_formal_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_formal_type" ):
                return visitor.visitSequence_formal_type(self)
            else:
                return visitor.visitChildren(self)




    def sequence_formal_type(self):

        localctx = SystemVerilogParser.Sequence_formal_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 460, self.RULE_sequence_formal_type)
        try:
            self.state = 4236
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.LB, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4233
                self.data_type_or_implicit()
                pass
            elif token in [SystemVerilogParser.KSEQUENCE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4234
                self.match(SystemVerilogParser.KSEQUENCE)
                pass
            elif token in [SystemVerilogParser.KUNTYPED]:
                self.enterOuterAlt(localctx, 3)
                self.state = 4235
                self.match(SystemVerilogParser.KUNTYPED)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_exprContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cycle_delay_range(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Cycle_delay_rangeContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Cycle_delay_rangeContext,i)


        def sequence_expr(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Sequence_exprContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Sequence_exprContext,i)


        def expression_or_dist(self):
            return self.getTypedRuleContext(SystemVerilogParser.Expression_or_distContext,0)


        def KTHROUGHOUT(self):
            return self.getToken(SystemVerilogParser.KTHROUGHOUT, 0)

        def boolean_abbrev(self):
            return self.getTypedRuleContext(SystemVerilogParser.Boolean_abbrevContext,0)


        def sequence_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_instanceContext,0)


        def sequence_abbrev(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_abbrevContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def sequence_match_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Sequence_match_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Sequence_match_itemContext,i)


        def KFIRST_MATCH(self):
            return self.getToken(SystemVerilogParser.KFIRST_MATCH, 0)

        def clocking_event(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_eventContext,0)


        def KAND(self):
            return self.getToken(SystemVerilogParser.KAND, 0)

        def KINTERSECT(self):
            return self.getToken(SystemVerilogParser.KINTERSECT, 0)

        def KOR(self):
            return self.getToken(SystemVerilogParser.KOR, 0)

        def KWITHIN(self):
            return self.getToken(SystemVerilogParser.KWITHIN, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_expr

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_expr" ):
                listener.enterSequence_expr(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_expr" ):
                listener.exitSequence_expr(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_expr" ):
                return visitor.visitSequence_expr(self)
            else:
                return visitor.visitChildren(self)



    def sequence_expr(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = SystemVerilogParser.Sequence_exprContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 462
        self.enterRecursionRule(localctx, 462, self.RULE_sequence_expr, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4289
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,489,self._ctx)
            if la_ == 1:
                self.state = 4239
                self.cycle_delay_range()
                self.state = 4240
                self.sequence_expr(0)
                self.state = 4246
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,482,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 4241
                        self.cycle_delay_range()
                        self.state = 4242
                        self.sequence_expr(0) 
                    self.state = 4248
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,482,self._ctx)

                pass

            elif la_ == 2:
                self.state = 4249
                self.expression_or_dist()
                self.state = 4255
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,484,self._ctx)
                if la_ == 1:
                    self.state = 4251
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,483,self._ctx)
                    if la_ == 1:
                        self.state = 4250
                        self.boolean_abbrev()


                    pass

                elif la_ == 2:
                    self.state = 4253
                    self.match(SystemVerilogParser.KTHROUGHOUT)
                    self.state = 4254
                    self.sequence_expr(0)
                    pass


                pass

            elif la_ == 3:
                self.state = 4257
                self.sequence_instance()
                self.state = 4259
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,485,self._ctx)
                if la_ == 1:
                    self.state = 4258
                    self.sequence_abbrev()


                pass

            elif la_ == 4:
                self.state = 4261
                self.match(SystemVerilogParser.LP)
                self.state = 4262
                self.sequence_expr(0)
                self.state = 4267
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4263
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4264
                    self.sequence_match_item()
                    self.state = 4269
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4270
                self.match(SystemVerilogParser.RP)
                self.state = 4272
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,487,self._ctx)
                if la_ == 1:
                    self.state = 4271
                    self.sequence_abbrev()


                pass

            elif la_ == 5:
                self.state = 4274
                self.match(SystemVerilogParser.KFIRST_MATCH)
                self.state = 4275
                self.match(SystemVerilogParser.LP)
                self.state = 4276
                self.sequence_expr(0)
                self.state = 4281
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4277
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4278
                    self.sequence_match_item()
                    self.state = 4283
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4284
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 6:
                self.state = 4286
                self.clocking_event()
                self.state = 4287
                self.sequence_expr(1)
                pass


            self._ctx.stop = self._input.LT(-1)
            self.state = 4307
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,492,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 4305
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,491,self._ctx)
                    if la_ == 1:
                        localctx = SystemVerilogParser.Sequence_exprContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_sequence_expr)
                        self.state = 4291
                        if not self.precpred(self._ctx, 3):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 3)")
                        self.state = 4292
                        _la = self._input.LA(1)
                        if not(_la==SystemVerilogParser.KAND or _la==SystemVerilogParser.KINTERSECT or _la==SystemVerilogParser.KOR or _la==SystemVerilogParser.KWITHIN):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4293
                        self.sequence_expr(4)
                        pass

                    elif la_ == 2:
                        localctx = SystemVerilogParser.Sequence_exprContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_sequence_expr)
                        self.state = 4294
                        if not self.precpred(self._ctx, 7):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 7)")
                        self.state = 4295
                        self.cycle_delay_range()
                        self.state = 4296
                        self.sequence_expr(0)
                        self.state = 4302
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,490,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 4297
                                self.cycle_delay_range()
                                self.state = 4298
                                self.sequence_expr(0) 
                            self.state = 4304
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,490,self._ctx)

                        pass

             
                self.state = 4309
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,492,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Cycle_delay_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PP(self):
            return self.getToken(SystemVerilogParser.PP, 0)

        def constant_primary(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_primaryContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def cycle_delay_const_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cycle_delay_const_range_expressionContext,0)


        def STAR(self):
            return self.getToken(SystemVerilogParser.STAR, 0)

        def PLUS(self):
            return self.getToken(SystemVerilogParser.PLUS, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cycle_delay_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCycle_delay_range" ):
                listener.enterCycle_delay_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCycle_delay_range" ):
                listener.exitCycle_delay_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCycle_delay_range" ):
                return visitor.visitCycle_delay_range(self)
            else:
                return visitor.visitChildren(self)




    def cycle_delay_range(self):

        localctx = SystemVerilogParser.Cycle_delay_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 464, self.RULE_cycle_delay_range)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4310
            self.match(SystemVerilogParser.PP)
            self.state = 4319
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.LC, SystemVerilogParser.KBYTE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSTD, SystemVerilogParser.KSUPER, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.state = 4311
                self.constant_primary()
                pass
            elif token in [SystemVerilogParser.LB]:
                self.state = 4312
                self.match(SystemVerilogParser.LB)
                self.state = 4316
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,493,self._ctx)
                if la_ == 1:
                    self.state = 4313
                    self.cycle_delay_const_range_expression()
                    pass

                elif la_ == 2:
                    self.state = 4314
                    self.match(SystemVerilogParser.STAR)
                    pass

                elif la_ == 3:
                    self.state = 4315
                    self.match(SystemVerilogParser.PLUS)
                    pass


                self.state = 4318
                self.match(SystemVerilogParser.RB)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_method_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def sequence_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_instanceContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def method_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_method_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_method_call" ):
                listener.enterSequence_method_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_method_call" ):
                listener.exitSequence_method_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_method_call" ):
                return visitor.visitSequence_method_call(self)
            else:
                return visitor.visitChildren(self)




    def sequence_method_call(self):

        localctx = SystemVerilogParser.Sequence_method_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 466, self.RULE_sequence_method_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4321
            self.sequence_instance()
            self.state = 4322
            self.match(SystemVerilogParser.DOT)
            self.state = 4323
            self.method_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_match_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def operator_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Operator_assignmentContext,0)


        def inc_or_dec_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inc_or_dec_expressionContext,0)


        def subroutine_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Subroutine_callContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_match_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_match_item" ):
                listener.enterSequence_match_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_match_item" ):
                listener.exitSequence_match_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_match_item" ):
                return visitor.visitSequence_match_item(self)
            else:
                return visitor.visitChildren(self)




    def sequence_match_item(self):

        localctx = SystemVerilogParser.Sequence_match_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 468, self.RULE_sequence_match_item)
        try:
            self.state = 4328
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,495,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4325
                self.operator_assignment()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4326
                self.inc_or_dec_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4327
                self.subroutine_call()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ps_or_hierarchical_sequence_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_or_hierarchical_sequence_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def sequence_list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_list_of_argumentsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_instance" ):
                listener.enterSequence_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_instance" ):
                listener.exitSequence_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_instance" ):
                return visitor.visitSequence_instance(self)
            else:
                return visitor.visitChildren(self)




    def sequence_instance(self):

        localctx = SystemVerilogParser.Sequence_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 470, self.RULE_sequence_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4330
            self.ps_or_hierarchical_sequence_identifier()
            self.state = 4336
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,497,self._ctx)
            if la_ == 1:
                self.state = 4331
                self.match(SystemVerilogParser.LP)
                self.state = 4333
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,496,self._ctx)
                if la_ == 1:
                    self.state = 4332
                    self.sequence_list_of_arguments()


                self.state = 4335
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_list_of_argumentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.IdentifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,i)


        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def sequence_actual_arg(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Sequence_actual_argContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Sequence_actual_argContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_list_of_arguments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_list_of_arguments" ):
                listener.enterSequence_list_of_arguments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_list_of_arguments" ):
                listener.exitSequence_list_of_arguments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_list_of_arguments" ):
                return visitor.visitSequence_list_of_arguments(self)
            else:
                return visitor.visitChildren(self)




    def sequence_list_of_arguments(self):

        localctx = SystemVerilogParser.Sequence_list_of_argumentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 472, self.RULE_sequence_list_of_arguments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4358
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.PP, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.RP, SystemVerilogParser.COMMA, SystemVerilogParser.AT, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KEDGE, SystemVerilogParser.KFIRST_MATCH, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNEGEDGE, SystemVerilogParser.KNULL, SystemVerilogParser.KPOSEDGE, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.state = 4339
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 4338
                    self.sequence_actual_arg()


                self.state = 4347
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,500,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 4341
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 4343
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                            self.state = 4342
                            self.sequence_actual_arg()

                 
                    self.state = 4349
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,500,self._ctx)

                pass
            elif token in [SystemVerilogParser.DOT]:
                self.state = 4350
                self.match(SystemVerilogParser.DOT)
                self.state = 4351
                self.identifier()
                self.state = 4352
                self.match(SystemVerilogParser.LP)
                self.state = 4354
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 4353
                    self.sequence_actual_arg()


                self.state = 4356
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

            self.state = 4371
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 4360
                self.match(SystemVerilogParser.COMMA)
                self.state = 4361
                self.match(SystemVerilogParser.DOT)
                self.state = 4362
                self.identifier()
                self.state = 4363
                self.match(SystemVerilogParser.LP)
                self.state = 4365
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 4364
                    self.sequence_actual_arg()


                self.state = 4367
                self.match(SystemVerilogParser.RP)
                self.state = 4373
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_actual_argContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def event_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Event_expressionContext,0)


        def sequence_expr(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_exprContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_actual_arg

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_actual_arg" ):
                listener.enterSequence_actual_arg(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_actual_arg" ):
                listener.exitSequence_actual_arg(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_actual_arg" ):
                return visitor.visitSequence_actual_arg(self)
            else:
                return visitor.visitChildren(self)




    def sequence_actual_arg(self):

        localctx = SystemVerilogParser.Sequence_actual_argContext(self, self._ctx, self.state)
        self.enterRule(localctx, 474, self.RULE_sequence_actual_arg)
        try:
            self.state = 4376
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,505,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4374
                self.event_expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4375
                self.sequence_expr(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Boolean_abbrevContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def consecutive_repetition(self):
            return self.getTypedRuleContext(SystemVerilogParser.Consecutive_repetitionContext,0)


        def non_consecutive_repetition(self):
            return self.getTypedRuleContext(SystemVerilogParser.Non_consecutive_repetitionContext,0)


        def goto_repetition(self):
            return self.getTypedRuleContext(SystemVerilogParser.Goto_repetitionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_boolean_abbrev

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBoolean_abbrev" ):
                listener.enterBoolean_abbrev(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBoolean_abbrev" ):
                listener.exitBoolean_abbrev(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBoolean_abbrev" ):
                return visitor.visitBoolean_abbrev(self)
            else:
                return visitor.visitChildren(self)




    def boolean_abbrev(self):

        localctx = SystemVerilogParser.Boolean_abbrevContext(self, self._ctx, self.state)
        self.enterRule(localctx, 476, self.RULE_boolean_abbrev)
        try:
            self.state = 4381
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,506,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4378
                self.consecutive_repetition()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4379
                self.non_consecutive_repetition()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4380
                self.goto_repetition()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_abbrevContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def consecutive_repetition(self):
            return self.getTypedRuleContext(SystemVerilogParser.Consecutive_repetitionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_abbrev

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_abbrev" ):
                listener.enterSequence_abbrev(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_abbrev" ):
                listener.exitSequence_abbrev(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_abbrev" ):
                return visitor.visitSequence_abbrev(self)
            else:
                return visitor.visitChildren(self)




    def sequence_abbrev(self):

        localctx = SystemVerilogParser.Sequence_abbrevContext(self, self._ctx, self.state)
        self.enterRule(localctx, 478, self.RULE_sequence_abbrev)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4383
            self.consecutive_repetition()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Consecutive_repetitionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def STAR(self):
            return self.getToken(SystemVerilogParser.STAR, 0)

        def const_or_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Const_or_range_expressionContext,0)


        def PLUS(self):
            return self.getToken(SystemVerilogParser.PLUS, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_consecutive_repetition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConsecutive_repetition" ):
                listener.enterConsecutive_repetition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConsecutive_repetition" ):
                listener.exitConsecutive_repetition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConsecutive_repetition" ):
                return visitor.visitConsecutive_repetition(self)
            else:
                return visitor.visitChildren(self)




    def consecutive_repetition(self):

        localctx = SystemVerilogParser.Consecutive_repetitionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 480, self.RULE_consecutive_repetition)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4385
            self.match(SystemVerilogParser.LB)
            self.state = 4390
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,507,self._ctx)
            if la_ == 1:
                self.state = 4386
                self.match(SystemVerilogParser.STAR)
                self.state = 4387
                self.const_or_range_expression()
                pass

            elif la_ == 2:
                self.state = 4388
                self.match(SystemVerilogParser.STAR)
                pass

            elif la_ == 3:
                self.state = 4389
                self.match(SystemVerilogParser.PLUS)
                pass


            self.state = 4392
            self.match(SystemVerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Non_consecutive_repetitionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def const_or_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Const_or_range_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_non_consecutive_repetition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNon_consecutive_repetition" ):
                listener.enterNon_consecutive_repetition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNon_consecutive_repetition" ):
                listener.exitNon_consecutive_repetition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNon_consecutive_repetition" ):
                return visitor.visitNon_consecutive_repetition(self)
            else:
                return visitor.visitChildren(self)




    def non_consecutive_repetition(self):

        localctx = SystemVerilogParser.Non_consecutive_repetitionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 482, self.RULE_non_consecutive_repetition)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4394
            self.match(SystemVerilogParser.LB)
            self.state = 4395
            self.match(SystemVerilogParser.EQ)
            self.state = 4396
            self.const_or_range_expression()
            self.state = 4397
            self.match(SystemVerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Goto_repetitionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def ARROW(self):
            return self.getToken(SystemVerilogParser.ARROW, 0)

        def const_or_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Const_or_range_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_goto_repetition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGoto_repetition" ):
                listener.enterGoto_repetition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGoto_repetition" ):
                listener.exitGoto_repetition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGoto_repetition" ):
                return visitor.visitGoto_repetition(self)
            else:
                return visitor.visitChildren(self)




    def goto_repetition(self):

        localctx = SystemVerilogParser.Goto_repetitionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 484, self.RULE_goto_repetition)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4399
            self.match(SystemVerilogParser.LB)
            self.state = 4400
            self.match(SystemVerilogParser.ARROW)
            self.state = 4401
            self.const_or_range_expression()
            self.state = 4402
            self.match(SystemVerilogParser.RB)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Const_or_range_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def cycle_delay_const_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cycle_delay_const_range_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_const_or_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConst_or_range_expression" ):
                listener.enterConst_or_range_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConst_or_range_expression" ):
                listener.exitConst_or_range_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConst_or_range_expression" ):
                return visitor.visitConst_or_range_expression(self)
            else:
                return visitor.visitChildren(self)




    def const_or_range_expression(self):

        localctx = SystemVerilogParser.Const_or_range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 486, self.RULE_const_or_range_expression)
        try:
            self.state = 4406
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,508,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4404
                self.constant_expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4405
                self.cycle_delay_const_range_expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cycle_delay_const_range_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def DOLLAR(self):
            return self.getToken(SystemVerilogParser.DOLLAR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cycle_delay_const_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCycle_delay_const_range_expression" ):
                listener.enterCycle_delay_const_range_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCycle_delay_const_range_expression" ):
                listener.exitCycle_delay_const_range_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCycle_delay_const_range_expression" ):
                return visitor.visitCycle_delay_const_range_expression(self)
            else:
                return visitor.visitChildren(self)




    def cycle_delay_const_range_expression(self):

        localctx = SystemVerilogParser.Cycle_delay_const_range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 488, self.RULE_cycle_delay_const_range_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4408
            self.constant_expression(0)
            self.state = 4409
            self.match(SystemVerilogParser.COLON)
            self.state = 4412
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,509,self._ctx)
            if la_ == 1:
                self.state = 4410
                self.constant_expression(0)
                pass

            elif la_ == 2:
                self.state = 4411
                self.match(SystemVerilogParser.DOLLAR)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Expression_or_distContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def KDIST(self):
            return self.getToken(SystemVerilogParser.KDIST, 0)

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def dist_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dist_listContext,0)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_expression_or_dist

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExpression_or_dist" ):
                listener.enterExpression_or_dist(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExpression_or_dist" ):
                listener.exitExpression_or_dist(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExpression_or_dist" ):
                return visitor.visitExpression_or_dist(self)
            else:
                return visitor.visitChildren(self)




    def expression_or_dist(self):

        localctx = SystemVerilogParser.Expression_or_distContext(self, self._ctx, self.state)
        self.enterRule(localctx, 490, self.RULE_expression_or_dist)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4414
            self.expression(0)
            self.state = 4420
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,510,self._ctx)
            if la_ == 1:
                self.state = 4415
                self.match(SystemVerilogParser.KDIST)
                self.state = 4416
                self.match(SystemVerilogParser.LC)
                self.state = 4417
                self.dist_list()
                self.state = 4418
                self.match(SystemVerilogParser.RC)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assertion_variable_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def var_data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Var_data_typeContext,0)


        def list_of_variable_decl_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_variable_decl_assignmentsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assertion_variable_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssertion_variable_declaration" ):
                listener.enterAssertion_variable_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssertion_variable_declaration" ):
                listener.exitAssertion_variable_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssertion_variable_declaration" ):
                return visitor.visitAssertion_variable_declaration(self)
            else:
                return visitor.visitChildren(self)




    def assertion_variable_declaration(self):

        localctx = SystemVerilogParser.Assertion_variable_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 492, self.RULE_assertion_variable_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4422
            self.var_data_type()
            self.state = 4423
            self.list_of_variable_decl_assignments()
            self.state = 4424
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Covergroup_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCOVERGROUP(self):
            return self.getToken(SystemVerilogParser.KCOVERGROUP, 0)

        def covergroup_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Covergroup_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Covergroup_identifierContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KENDGROUP(self):
            return self.getToken(SystemVerilogParser.KENDGROUP, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def coverage_event(self):
            return self.getTypedRuleContext(SystemVerilogParser.Coverage_eventContext,0)


        def coverage_spec_or_option(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Coverage_spec_or_optionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Coverage_spec_or_optionContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def tf_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_covergroup_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCovergroup_declaration" ):
                listener.enterCovergroup_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCovergroup_declaration" ):
                listener.exitCovergroup_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCovergroup_declaration" ):
                return visitor.visitCovergroup_declaration(self)
            else:
                return visitor.visitChildren(self)




    def covergroup_declaration(self):

        localctx = SystemVerilogParser.Covergroup_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 494, self.RULE_covergroup_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4426
            self.match(SystemVerilogParser.KCOVERGROUP)
            self.state = 4427
            self.covergroup_identifier()
            self.state = 4433
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 4428
                self.match(SystemVerilogParser.LP)
                self.state = 4430
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,511,self._ctx)
                if la_ == 1:
                    self.state = 4429
                    self.tf_port_list()


                self.state = 4432
                self.match(SystemVerilogParser.RP)


            self.state = 4436
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.AT or _la==SystemVerilogParser.ATAT:
                self.state = 4435
                self.coverage_event()


            self.state = 4438
            self.match(SystemVerilogParser.SEMI)
            self.state = 4442
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KCOVERPOINT - 109)) | (1 << (SystemVerilogParser.KCROSS - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KOPTION - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSTRUCT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KTYPE_OPTION - 276)) | (1 << (SystemVerilogParser.KUNION - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)) | (1 << (SystemVerilogParser.KVIRTUAL - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 4439
                self.coverage_spec_or_option()
                self.state = 4444
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4445
            self.match(SystemVerilogParser.KENDGROUP)
            self.state = 4448
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 4446
                self.match(SystemVerilogParser.COLON)
                self.state = 4447
                self.covergroup_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Coverage_spec_or_optionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def coverage_spec(self):
            return self.getTypedRuleContext(SystemVerilogParser.Coverage_specContext,0)


        def coverage_option(self):
            return self.getTypedRuleContext(SystemVerilogParser.Coverage_optionContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_coverage_spec_or_option

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCoverage_spec_or_option" ):
                listener.enterCoverage_spec_or_option(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCoverage_spec_or_option" ):
                listener.exitCoverage_spec_or_option(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCoverage_spec_or_option" ):
                return visitor.visitCoverage_spec_or_option(self)
            else:
                return visitor.visitChildren(self)




    def coverage_spec_or_option(self):

        localctx = SystemVerilogParser.Coverage_spec_or_optionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 496, self.RULE_coverage_spec_or_option)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4453
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 4450
                self.attribute_instance()
                self.state = 4455
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4460
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.LB, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KCOVERPOINT, SystemVerilogParser.KCROSS, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 4456
                self.coverage_spec()
                pass
            elif token in [SystemVerilogParser.KOPTION, SystemVerilogParser.KTYPE_OPTION]:
                self.state = 4457
                self.coverage_option()
                self.state = 4458
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Coverage_optionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KOPTION(self):
            return self.getToken(SystemVerilogParser.KOPTION, 0)

        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def KMEMBER_IDENTIFIER(self):
            return self.getToken(SystemVerilogParser.KMEMBER_IDENTIFIER, 0)

        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def KTYPE_OPTION(self):
            return self.getToken(SystemVerilogParser.KTYPE_OPTION, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_coverage_option

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCoverage_option" ):
                listener.enterCoverage_option(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCoverage_option" ):
                listener.exitCoverage_option(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCoverage_option" ):
                return visitor.visitCoverage_option(self)
            else:
                return visitor.visitChildren(self)




    def coverage_option(self):

        localctx = SystemVerilogParser.Coverage_optionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 498, self.RULE_coverage_option)
        try:
            self.state = 4472
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KOPTION]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4462
                self.match(SystemVerilogParser.KOPTION)
                self.state = 4463
                self.match(SystemVerilogParser.DOT)
                self.state = 4464
                self.match(SystemVerilogParser.KMEMBER_IDENTIFIER)
                self.state = 4465
                self.match(SystemVerilogParser.EQ)
                self.state = 4466
                self.expression(0)
                pass
            elif token in [SystemVerilogParser.KTYPE_OPTION]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4467
                self.match(SystemVerilogParser.KTYPE_OPTION)
                self.state = 4468
                self.match(SystemVerilogParser.DOT)
                self.state = 4469
                self.match(SystemVerilogParser.KMEMBER_IDENTIFIER)
                self.state = 4470
                self.match(SystemVerilogParser.EQ)
                self.state = 4471
                self.constant_expression(0)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Coverage_specContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cover_point(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cover_pointContext,0)


        def cover_cross(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cover_crossContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_coverage_spec

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCoverage_spec" ):
                listener.enterCoverage_spec(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCoverage_spec" ):
                listener.exitCoverage_spec(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCoverage_spec" ):
                return visitor.visitCoverage_spec(self)
            else:
                return visitor.visitChildren(self)




    def coverage_spec(self):

        localctx = SystemVerilogParser.Coverage_specContext(self, self._ctx, self.state)
        self.enterRule(localctx, 500, self.RULE_coverage_spec)
        try:
            self.state = 4476
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,519,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4474
                self.cover_point()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4475
                self.cover_cross()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Coverage_eventContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def clocking_event(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_eventContext,0)


        def ATAT(self):
            return self.getToken(SystemVerilogParser.ATAT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def block_event_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Block_event_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_coverage_event

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCoverage_event" ):
                listener.enterCoverage_event(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCoverage_event" ):
                listener.exitCoverage_event(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCoverage_event" ):
                return visitor.visitCoverage_event(self)
            else:
                return visitor.visitChildren(self)




    def coverage_event(self):

        localctx = SystemVerilogParser.Coverage_eventContext(self, self._ctx, self.state)
        self.enterRule(localctx, 502, self.RULE_coverage_event)
        try:
            self.state = 4484
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.AT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4478
                self.clocking_event()
                pass
            elif token in [SystemVerilogParser.ATAT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4479
                self.match(SystemVerilogParser.ATAT)
                self.state = 4480
                self.match(SystemVerilogParser.LP)
                self.state = 4481
                self.block_event_expression(0)
                self.state = 4482
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_event_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_btf_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_btf_identifierContext,0)


        def KBEGIN(self):
            return self.getToken(SystemVerilogParser.KBEGIN, 0)

        def KEND(self):
            return self.getToken(SystemVerilogParser.KEND, 0)

        def block_event_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Block_event_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Block_event_expressionContext,i)


        def KOR(self):
            return self.getToken(SystemVerilogParser.KOR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_block_event_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_event_expression" ):
                listener.enterBlock_event_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_event_expression" ):
                listener.exitBlock_event_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_event_expression" ):
                return visitor.visitBlock_event_expression(self)
            else:
                return visitor.visitChildren(self)



    def block_event_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = SystemVerilogParser.Block_event_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 504
        self.enterRecursionRule(localctx, 504, self.RULE_block_event_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4487
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KBEGIN or _la==SystemVerilogParser.KEND):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 4488
            self.hierarchical_btf_identifier()
            self._ctx.stop = self._input.LT(-1)
            self.state = 4495
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,521,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    localctx = SystemVerilogParser.Block_event_expressionContext(self, _parentctx, _parentState)
                    self.pushNewRecursionContext(localctx, _startState, self.RULE_block_event_expression)
                    self.state = 4490
                    if not self.precpred(self._ctx, 2):
                        from antlr4.error.Errors import FailedPredicateException
                        raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                    self.state = 4491
                    self.match(SystemVerilogParser.KOR)
                    self.state = 4492
                    self.block_event_expression(3) 
                self.state = 4497
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,521,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Hierarchical_btf_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_tf_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_tf_identifierContext,0)


        def hierarchical_block_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_block_identifierContext,0)


        def method_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_identifierContext,0)


        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_btf_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_btf_identifier" ):
                listener.enterHierarchical_btf_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_btf_identifier" ):
                listener.exitHierarchical_btf_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_btf_identifier" ):
                return visitor.visitHierarchical_btf_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_btf_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_btf_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 506, self.RULE_hierarchical_btf_identifier)
        try:
            self.state = 4507
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,523,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4498
                self.hierarchical_tf_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4499
                self.hierarchical_block_identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4504
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,522,self._ctx)
                if la_ == 1:
                    self.state = 4500
                    self.hierarchical_identifier()
                    self.state = 4501
                    self.match(SystemVerilogParser.DOT)

                elif la_ == 2:
                    self.state = 4503
                    self.class_scope()


                self.state = 4506
                self.method_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cover_pointContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCOVERPOINT(self):
            return self.getToken(SystemVerilogParser.KCOVERPOINT, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def bins_or_empty(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bins_or_emptyContext,0)


        def cover_point_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cover_point_identifierContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cover_point

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCover_point" ):
                listener.enterCover_point(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCover_point" ):
                listener.exitCover_point(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCover_point" ):
                return visitor.visitCover_point(self)
            else:
                return visitor.visitChildren(self)




    def cover_point(self):

        localctx = SystemVerilogParser.Cover_pointContext(self, self._ctx, self.state)
        self.enterRule(localctx, 508, self.RULE_cover_point)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4515
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.DUNIT or _la==SystemVerilogParser.LB or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSTRUCT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNION - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)) | (1 << (SystemVerilogParser.KVIRTUAL - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 4510
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,524,self._ctx)
                if la_ == 1:
                    self.state = 4509
                    self.data_type_or_implicit()


                self.state = 4512
                self.cover_point_identifier()
                self.state = 4513
                self.match(SystemVerilogParser.COLON)


            self.state = 4517
            self.match(SystemVerilogParser.KCOVERPOINT)
            self.state = 4518
            self.expression(0)
            self.state = 4524
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KIFF:
                self.state = 4519
                self.match(SystemVerilogParser.KIFF)
                self.state = 4520
                self.match(SystemVerilogParser.LP)
                self.state = 4521
                self.expression(0)
                self.state = 4522
                self.match(SystemVerilogParser.RP)


            self.state = 4526
            self.bins_or_empty()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bins_or_emptyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def bins_or_options(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Bins_or_optionsContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Bins_or_optionsContext,i)


        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bins_or_empty

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBins_or_empty" ):
                listener.enterBins_or_empty(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBins_or_empty" ):
                listener.exitBins_or_empty(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBins_or_empty" ):
                return visitor.visitBins_or_empty(self)
            else:
                return visitor.visitChildren(self)




    def bins_or_empty(self):

        localctx = SystemVerilogParser.Bins_or_emptyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 510, self.RULE_bins_or_empty)
        self._la = 0 # Token type
        try:
            self.state = 4545
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.LC]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4528
                self.match(SystemVerilogParser.LC)
                self.state = 4532
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 4529
                    self.attribute_instance()
                    self.state = 4534
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4540
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.KBINS or ((((_la - 183)) & ~0x3f) == 0 and ((1 << (_la - 183)) & ((1 << (SystemVerilogParser.KIGNORE_BINS - 183)) | (1 << (SystemVerilogParser.KILLEGAL_BINS - 183)) | (1 << (SystemVerilogParser.KOPTION - 183)))) != 0) or _la==SystemVerilogParser.KTYPE_OPTION or _la==SystemVerilogParser.KWILDCARD:
                    self.state = 4535
                    self.bins_or_options()
                    self.state = 4536
                    self.match(SystemVerilogParser.SEMI)
                    self.state = 4542
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4543
                self.match(SystemVerilogParser.RC)
                pass
            elif token in [SystemVerilogParser.SEMI]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4544
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bins_or_optionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def coverage_option(self):
            return self.getTypedRuleContext(SystemVerilogParser.Coverage_optionContext,0)


        def bins_keyword(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bins_keywordContext,0)


        def bin_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bin_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def trans_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Trans_listContext,0)


        def KWILDCARD(self):
            return self.getToken(SystemVerilogParser.KWILDCARD, 0)

        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def covergroup_range_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_range_listContext,0)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def cover_point_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cover_point_identifierContext,0)


        def KWITH(self):
            return self.getToken(SystemVerilogParser.KWITH, 0)

        def with_covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.With_covergroup_expressionContext,0)


        def set_covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Set_covergroup_expressionContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_expressionContext,0)


        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def KSEQUENCE(self):
            return self.getToken(SystemVerilogParser.KSEQUENCE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bins_or_options

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBins_or_options" ):
                listener.enterBins_or_options(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBins_or_options" ):
                listener.exitBins_or_options(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBins_or_options" ):
                return visitor.visitBins_or_options(self)
            else:
                return visitor.visitChildren(self)




    def bins_or_options(self):

        localctx = SystemVerilogParser.Bins_or_optionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 512, self.RULE_bins_or_options)
        self._la = 0 # Token type
        try:
            self.state = 4618
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,542,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4547
                self.coverage_option()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4549
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KWILDCARD:
                    self.state = 4548
                    self.match(SystemVerilogParser.KWILDCARD)


                self.state = 4551
                self.bins_keyword()
                self.state = 4552
                self.bin_identifier()
                self.state = 4586
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,536,self._ctx)
                if la_ == 1:
                    self.state = 4558
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.LB:
                        self.state = 4553
                        self.match(SystemVerilogParser.LB)
                        self.state = 4555
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                            self.state = 4554
                            self.covergroup_expression()


                        self.state = 4557
                        self.match(SystemVerilogParser.RB)


                    self.state = 4560
                    self.match(SystemVerilogParser.EQ)
                    self.state = 4578
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,534,self._ctx)
                    if la_ == 1:
                        self.state = 4561
                        self.match(SystemVerilogParser.LC)
                        self.state = 4562
                        self.covergroup_range_list()
                        self.state = 4563
                        self.match(SystemVerilogParser.RC)
                        self.state = 4569
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if _la==SystemVerilogParser.KWITH:
                            self.state = 4564
                            self.match(SystemVerilogParser.KWITH)
                            self.state = 4565
                            self.match(SystemVerilogParser.LP)
                            self.state = 4566
                            self.with_covergroup_expression()
                            self.state = 4567
                            self.match(SystemVerilogParser.RP)


                        pass

                    elif la_ == 2:
                        self.state = 4571
                        self.cover_point_identifier()
                        self.state = 4572
                        self.match(SystemVerilogParser.KWITH)
                        self.state = 4573
                        self.match(SystemVerilogParser.LP)
                        self.state = 4574
                        self.with_covergroup_expression()
                        self.state = 4575
                        self.match(SystemVerilogParser.RP)
                        pass

                    elif la_ == 3:
                        self.state = 4577
                        self.set_covergroup_expression()
                        pass


                    pass

                elif la_ == 2:
                    self.state = 4582
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.LB:
                        self.state = 4580
                        self.match(SystemVerilogParser.LB)
                        self.state = 4581
                        self.match(SystemVerilogParser.RB)


                    self.state = 4584
                    self.match(SystemVerilogParser.EQ)
                    self.state = 4585
                    self.trans_list()
                    pass


                self.state = 4593
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KIFF:
                    self.state = 4588
                    self.match(SystemVerilogParser.KIFF)
                    self.state = 4589
                    self.match(SystemVerilogParser.LP)
                    self.state = 4590
                    self.expression(0)
                    self.state = 4591
                    self.match(SystemVerilogParser.RP)


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 4595
                self.bins_keyword()
                self.state = 4596
                self.bin_identifier()
                self.state = 4609
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,540,self._ctx)
                if la_ == 1:
                    self.state = 4602
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.LB:
                        self.state = 4597
                        self.match(SystemVerilogParser.LB)
                        self.state = 4599
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                            self.state = 4598
                            self.covergroup_expression()


                        self.state = 4601
                        self.match(SystemVerilogParser.RB)


                    self.state = 4604
                    self.match(SystemVerilogParser.EQ)
                    self.state = 4605
                    self.match(SystemVerilogParser.KDEFAULT)
                    pass

                elif la_ == 2:
                    self.state = 4606
                    self.match(SystemVerilogParser.EQ)
                    self.state = 4607
                    self.match(SystemVerilogParser.KDEFAULT)
                    self.state = 4608
                    self.match(SystemVerilogParser.KSEQUENCE)
                    pass


                self.state = 4616
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KIFF:
                    self.state = 4611
                    self.match(SystemVerilogParser.KIFF)
                    self.state = 4612
                    self.match(SystemVerilogParser.LP)
                    self.state = 4613
                    self.expression(0)
                    self.state = 4614
                    self.match(SystemVerilogParser.RP)


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bins_keywordContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KBINS(self):
            return self.getToken(SystemVerilogParser.KBINS, 0)

        def KILLEGAL_BINS(self):
            return self.getToken(SystemVerilogParser.KILLEGAL_BINS, 0)

        def KIGNORE_BINS(self):
            return self.getToken(SystemVerilogParser.KIGNORE_BINS, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bins_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBins_keyword" ):
                listener.enterBins_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBins_keyword" ):
                listener.exitBins_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBins_keyword" ):
                return visitor.visitBins_keyword(self)
            else:
                return visitor.visitChildren(self)




    def bins_keyword(self):

        localctx = SystemVerilogParser.Bins_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 514, self.RULE_bins_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4620
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KBINS or _la==SystemVerilogParser.KIGNORE_BINS or _la==SystemVerilogParser.KILLEGAL_BINS):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Trans_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def trans_set(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Trans_setContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Trans_setContext,i)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_trans_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTrans_list" ):
                listener.enterTrans_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTrans_list" ):
                listener.exitTrans_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTrans_list" ):
                return visitor.visitTrans_list(self)
            else:
                return visitor.visitChildren(self)




    def trans_list(self):

        localctx = SystemVerilogParser.Trans_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 516, self.RULE_trans_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4622
            self.match(SystemVerilogParser.LP)
            self.state = 4623
            self.trans_set()
            self.state = 4624
            self.match(SystemVerilogParser.RP)
            self.state = 4632
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 4625
                self.match(SystemVerilogParser.COMMA)
                self.state = 4626
                self.match(SystemVerilogParser.LP)
                self.state = 4627
                self.trans_set()
                self.state = 4628
                self.match(SystemVerilogParser.RP)
                self.state = 4634
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Trans_setContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def trans_range_list(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Trans_range_listContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Trans_range_listContext,i)


        def EQGT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.EQGT)
            else:
                return self.getToken(SystemVerilogParser.EQGT, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_trans_set

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTrans_set" ):
                listener.enterTrans_set(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTrans_set" ):
                listener.exitTrans_set(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTrans_set" ):
                return visitor.visitTrans_set(self)
            else:
                return visitor.visitChildren(self)




    def trans_set(self):

        localctx = SystemVerilogParser.Trans_setContext(self, self._ctx, self.state)
        self.enterRule(localctx, 518, self.RULE_trans_set)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4635
            self.trans_range_list()
            self.state = 4640
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.EQGT:
                self.state = 4636
                self.match(SystemVerilogParser.EQGT)
                self.state = 4637
                self.trans_range_list()
                self.state = 4642
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Trans_range_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def trans_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Trans_itemContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def repeat_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Repeat_rangeContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def STAR(self):
            return self.getToken(SystemVerilogParser.STAR, 0)

        def ARROW(self):
            return self.getToken(SystemVerilogParser.ARROW, 0)

        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_trans_range_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTrans_range_list" ):
                listener.enterTrans_range_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTrans_range_list" ):
                listener.exitTrans_range_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTrans_range_list" ):
                return visitor.visitTrans_range_list(self)
            else:
                return visitor.visitChildren(self)




    def trans_range_list(self):

        localctx = SystemVerilogParser.Trans_range_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 520, self.RULE_trans_range_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4643
            self.trans_item()
            self.state = 4649
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LB:
                self.state = 4644
                self.match(SystemVerilogParser.LB)
                self.state = 4645
                _la = self._input.LA(1)
                if not(((((_la - 30)) & ~0x3f) == 0 and ((1 << (_la - 30)) & ((1 << (SystemVerilogParser.STAR - 30)) | (1 << (SystemVerilogParser.EQ - 30)) | (1 << (SystemVerilogParser.ARROW - 30)))) != 0)):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 4646
                self.repeat_range()
                self.state = 4647
                self.match(SystemVerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Trans_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_range_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_range_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_trans_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTrans_item" ):
                listener.enterTrans_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTrans_item" ):
                listener.exitTrans_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTrans_item" ):
                return visitor.visitTrans_item(self)
            else:
                return visitor.visitChildren(self)




    def trans_item(self):

        localctx = SystemVerilogParser.Trans_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 522, self.RULE_trans_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4651
            self.covergroup_range_list()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Repeat_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Covergroup_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Covergroup_expressionContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_repeat_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRepeat_range" ):
                listener.enterRepeat_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRepeat_range" ):
                listener.exitRepeat_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRepeat_range" ):
                return visitor.visitRepeat_range(self)
            else:
                return visitor.visitChildren(self)




    def repeat_range(self):

        localctx = SystemVerilogParser.Repeat_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 524, self.RULE_repeat_range)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4653
            self.covergroup_expression()
            self.state = 4656
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 4654
                self.match(SystemVerilogParser.COLON)
                self.state = 4655
                self.covergroup_expression()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cover_crossContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCROSS(self):
            return self.getToken(SystemVerilogParser.KCROSS, 0)

        def list_of_cross_items(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_cross_itemsContext,0)


        def cross_body(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cross_bodyContext,0)


        def cross_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cross_identifierContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cover_cross

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCover_cross" ):
                listener.enterCover_cross(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCover_cross" ):
                listener.exitCover_cross(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCover_cross" ):
                return visitor.visitCover_cross(self)
            else:
                return visitor.visitChildren(self)




    def cover_cross(self):

        localctx = SystemVerilogParser.Cover_crossContext(self, self._ctx, self.state)
        self.enterRule(localctx, 526, self.RULE_cover_cross)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4661
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 4658
                self.cross_identifier()
                self.state = 4659
                self.match(SystemVerilogParser.COLON)


            self.state = 4663
            self.match(SystemVerilogParser.KCROSS)
            self.state = 4664
            self.list_of_cross_items()
            self.state = 4670
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KIFF:
                self.state = 4665
                self.match(SystemVerilogParser.KIFF)
                self.state = 4666
                self.match(SystemVerilogParser.LP)
                self.state = 4667
                self.expression(0)
                self.state = 4668
                self.match(SystemVerilogParser.RP)


            self.state = 4672
            self.cross_body()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_cross_itemsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cross_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Cross_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Cross_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_cross_items

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_cross_items" ):
                listener.enterList_of_cross_items(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_cross_items" ):
                listener.exitList_of_cross_items(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_cross_items" ):
                return visitor.visitList_of_cross_items(self)
            else:
                return visitor.visitChildren(self)




    def list_of_cross_items(self):

        localctx = SystemVerilogParser.List_of_cross_itemsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 528, self.RULE_list_of_cross_items)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4674
            self.cross_item()
            self.state = 4675
            self.match(SystemVerilogParser.COMMA)
            self.state = 4676
            self.cross_item()
            self.state = 4681
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 4677
                self.match(SystemVerilogParser.COMMA)
                self.state = 4678
                self.cross_item()
                self.state = 4683
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cross_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cover_point_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cover_point_identifierContext,0)


        def variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cross_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCross_item" ):
                listener.enterCross_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCross_item" ):
                listener.exitCross_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCross_item" ):
                return visitor.visitCross_item(self)
            else:
                return visitor.visitChildren(self)




    def cross_item(self):

        localctx = SystemVerilogParser.Cross_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 530, self.RULE_cross_item)
        try:
            self.state = 4686
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,550,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4684
                self.cover_point_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4685
                self.variable_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cross_bodyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def cross_body_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Cross_body_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Cross_body_itemContext,i)


        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cross_body

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCross_body" ):
                listener.enterCross_body(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCross_body" ):
                listener.exitCross_body(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCross_body" ):
                return visitor.visitCross_body(self)
            else:
                return visitor.visitChildren(self)




    def cross_body(self):

        localctx = SystemVerilogParser.Cross_bodyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 532, self.RULE_cross_body)
        self._la = 0 # Token type
        try:
            self.state = 4699
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.LC]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4688
                self.match(SystemVerilogParser.LC)
                self.state = 4694
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS or _la==SystemVerilogParser.KBINS or ((((_la - 174)) & ~0x3f) == 0 and ((1 << (_la - 174)) & ((1 << (SystemVerilogParser.KFUNCTION - 174)) | (1 << (SystemVerilogParser.KIGNORE_BINS - 174)) | (1 << (SystemVerilogParser.KILLEGAL_BINS - 174)) | (1 << (SystemVerilogParser.KOPTION - 174)))) != 0) or _la==SystemVerilogParser.KTYPE_OPTION:
                    self.state = 4689
                    self.cross_body_item()
                    self.state = 4690
                    self.match(SystemVerilogParser.SEMI)
                    self.state = 4696
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4697
                self.match(SystemVerilogParser.RC)
                pass
            elif token in [SystemVerilogParser.SEMI]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4698
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cross_body_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_declarationContext,0)


        def bins_selection_or_option(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bins_selection_or_optionContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cross_body_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCross_body_item" ):
                listener.enterCross_body_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCross_body_item" ):
                listener.exitCross_body_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCross_body_item" ):
                return visitor.visitCross_body_item(self)
            else:
                return visitor.visitChildren(self)




    def cross_body_item(self):

        localctx = SystemVerilogParser.Cross_body_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 534, self.RULE_cross_body_item)
        try:
            self.state = 4705
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KFUNCTION]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4701
                self.function_declaration()
                pass
            elif token in [SystemVerilogParser.LPS, SystemVerilogParser.KBINS, SystemVerilogParser.KIGNORE_BINS, SystemVerilogParser.KILLEGAL_BINS, SystemVerilogParser.KOPTION, SystemVerilogParser.KTYPE_OPTION]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4702
                self.bins_selection_or_option()
                self.state = 4703
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bins_selection_or_optionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def coverage_option(self):
            return self.getTypedRuleContext(SystemVerilogParser.Coverage_optionContext,0)


        def bins_selection(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bins_selectionContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bins_selection_or_option

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBins_selection_or_option" ):
                listener.enterBins_selection_or_option(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBins_selection_or_option" ):
                listener.exitBins_selection_or_option(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBins_selection_or_option" ):
                return visitor.visitBins_selection_or_option(self)
            else:
                return visitor.visitChildren(self)




    def bins_selection_or_option(self):

        localctx = SystemVerilogParser.Bins_selection_or_optionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 536, self.RULE_bins_selection_or_option)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4710
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 4707
                self.attribute_instance()
                self.state = 4712
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4715
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KOPTION, SystemVerilogParser.KTYPE_OPTION]:
                self.state = 4713
                self.coverage_option()
                pass
            elif token in [SystemVerilogParser.KBINS, SystemVerilogParser.KIGNORE_BINS, SystemVerilogParser.KILLEGAL_BINS]:
                self.state = 4714
                self.bins_selection()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bins_selectionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def bins_keyword(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bins_keywordContext,0)


        def bin_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bin_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def select_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Select_expressionContext,0)


        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bins_selection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBins_selection" ):
                listener.enterBins_selection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBins_selection" ):
                listener.exitBins_selection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBins_selection" ):
                return visitor.visitBins_selection(self)
            else:
                return visitor.visitChildren(self)




    def bins_selection(self):

        localctx = SystemVerilogParser.Bins_selectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 538, self.RULE_bins_selection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4717
            self.bins_keyword()
            self.state = 4718
            self.bin_identifier()
            self.state = 4719
            self.match(SystemVerilogParser.EQ)
            self.state = 4720
            self.select_expression(0)
            self.state = 4726
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KIFF:
                self.state = 4721
                self.match(SystemVerilogParser.KIFF)
                self.state = 4722
                self.match(SystemVerilogParser.LP)
                self.state = 4723
                self.expression(0)
                self.state = 4724
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Select_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def select_condition(self):
            return self.getTypedRuleContext(SystemVerilogParser.Select_conditionContext,0)


        def NOT(self):
            return self.getToken(SystemVerilogParser.NOT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def select_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Select_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Select_expressionContext,i)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def cross_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cross_identifierContext,0)


        def cross_set_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cross_set_expressionContext,0)


        def KMATCHES(self):
            return self.getToken(SystemVerilogParser.KMATCHES, 0)

        def integer_covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_covergroup_expressionContext,0)


        def ANDAND(self):
            return self.getToken(SystemVerilogParser.ANDAND, 0)

        def BARBAR(self):
            return self.getToken(SystemVerilogParser.BARBAR, 0)

        def KWITH(self):
            return self.getToken(SystemVerilogParser.KWITH, 0)

        def with_covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.With_covergroup_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_select_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSelect_expression" ):
                listener.enterSelect_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSelect_expression" ):
                listener.exitSelect_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSelect_expression" ):
                return visitor.visitSelect_expression(self)
            else:
                return visitor.visitChildren(self)



    def select_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = SystemVerilogParser.Select_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 540
        self.enterRecursionRule(localctx, 540, self.RULE_select_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4743
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,559,self._ctx)
            if la_ == 1:
                self.state = 4730
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.NOT:
                    self.state = 4729
                    self.match(SystemVerilogParser.NOT)


                self.state = 4732
                self.select_condition()
                pass

            elif la_ == 2:
                self.state = 4733
                self.match(SystemVerilogParser.LP)
                self.state = 4734
                self.select_expression(0)
                self.state = 4735
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 3:
                self.state = 4737
                self.cross_identifier()
                pass

            elif la_ == 4:
                self.state = 4738
                self.cross_set_expression()
                self.state = 4741
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,558,self._ctx)
                if la_ == 1:
                    self.state = 4739
                    self.match(SystemVerilogParser.KMATCHES)
                    self.state = 4740
                    self.integer_covergroup_expression()


                pass


            self._ctx.stop = self._input.LT(-1)
            self.state = 4759
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,562,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 4757
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,561,self._ctx)
                    if la_ == 1:
                        localctx = SystemVerilogParser.Select_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_select_expression)
                        self.state = 4745
                        if not self.precpred(self._ctx, 5):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 5)")
                        self.state = 4746
                        _la = self._input.LA(1)
                        if not(_la==SystemVerilogParser.ANDAND or _la==SystemVerilogParser.BARBAR):
                            self._errHandler.recoverInline(self)
                        else:
                            self._errHandler.reportMatch(self)
                            self.consume()
                        self.state = 4747
                        self.select_expression(6)
                        pass

                    elif la_ == 2:
                        localctx = SystemVerilogParser.Select_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_select_expression)
                        self.state = 4748
                        if not self.precpred(self._ctx, 3):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 3)")
                        self.state = 4749
                        self.match(SystemVerilogParser.KWITH)
                        self.state = 4750
                        self.match(SystemVerilogParser.LP)
                        self.state = 4751
                        self.with_covergroup_expression()
                        self.state = 4752
                        self.match(SystemVerilogParser.RP)
                        self.state = 4755
                        self._errHandler.sync(self)
                        la_ = self._interp.adaptivePredict(self._input,560,self._ctx)
                        if la_ == 1:
                            self.state = 4753
                            self.match(SystemVerilogParser.KMATCHES)
                            self.state = 4754
                            self.integer_covergroup_expression()


                        pass

             
                self.state = 4761
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,562,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Select_conditionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KBINSOF(self):
            return self.getToken(SystemVerilogParser.KBINSOF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def bins_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bins_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def KINTERSECT(self):
            return self.getToken(SystemVerilogParser.KINTERSECT, 0)

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def covergroup_range_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_range_listContext,0)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_select_condition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSelect_condition" ):
                listener.enterSelect_condition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSelect_condition" ):
                listener.exitSelect_condition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSelect_condition" ):
                return visitor.visitSelect_condition(self)
            else:
                return visitor.visitChildren(self)




    def select_condition(self):

        localctx = SystemVerilogParser.Select_conditionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 542, self.RULE_select_condition)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4762
            self.match(SystemVerilogParser.KBINSOF)
            self.state = 4763
            self.match(SystemVerilogParser.LP)
            self.state = 4764
            self.bins_expression()
            self.state = 4765
            self.match(SystemVerilogParser.RP)
            self.state = 4771
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,563,self._ctx)
            if la_ == 1:
                self.state = 4766
                self.match(SystemVerilogParser.KINTERSECT)
                self.state = 4767
                self.match(SystemVerilogParser.LC)
                self.state = 4768
                self.covergroup_range_list()
                self.state = 4769
                self.match(SystemVerilogParser.RC)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bins_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,0)


        def cover_point_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cover_point_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def bin_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Bin_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bins_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBins_expression" ):
                listener.enterBins_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBins_expression" ):
                listener.exitBins_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBins_expression" ):
                return visitor.visitBins_expression(self)
            else:
                return visitor.visitChildren(self)




    def bins_expression(self):

        localctx = SystemVerilogParser.Bins_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 544, self.RULE_bins_expression)
        self._la = 0 # Token type
        try:
            self.state = 4779
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,565,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 4773
                self.variable_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 4774
                self.cover_point_identifier()
                self.state = 4777
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.DOT:
                    self.state = 4775
                    self.match(SystemVerilogParser.DOT)
                    self.state = 4776
                    self.bin_identifier()


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Covergroup_range_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_value_range(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Covergroup_value_rangeContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Covergroup_value_rangeContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_covergroup_range_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCovergroup_range_list" ):
                listener.enterCovergroup_range_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCovergroup_range_list" ):
                listener.exitCovergroup_range_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCovergroup_range_list" ):
                return visitor.visitCovergroup_range_list(self)
            else:
                return visitor.visitChildren(self)




    def covergroup_range_list(self):

        localctx = SystemVerilogParser.Covergroup_range_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 546, self.RULE_covergroup_range_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4781
            self.covergroup_value_range()
            self.state = 4786
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 4782
                self.match(SystemVerilogParser.COMMA)
                self.state = 4783
                self.covergroup_value_range()
                self.state = 4788
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Covergroup_value_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Covergroup_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Covergroup_expressionContext,i)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_covergroup_value_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCovergroup_value_range" ):
                listener.enterCovergroup_value_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCovergroup_value_range" ):
                listener.exitCovergroup_value_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCovergroup_value_range" ):
                return visitor.visitCovergroup_value_range(self)
            else:
                return visitor.visitChildren(self)




    def covergroup_value_range(self):

        localctx = SystemVerilogParser.Covergroup_value_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 548, self.RULE_covergroup_value_range)
        try:
            self.state = 4796
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4789
                self.covergroup_expression()
                pass
            elif token in [SystemVerilogParser.LB]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4790
                self.match(SystemVerilogParser.LB)
                self.state = 4791
                self.covergroup_expression()
                self.state = 4792
                self.match(SystemVerilogParser.COLON)
                self.state = 4793
                self.covergroup_expression()
                self.state = 4794
                self.match(SystemVerilogParser.RB)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class With_covergroup_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_with_covergroup_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWith_covergroup_expression" ):
                listener.enterWith_covergroup_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWith_covergroup_expression" ):
                listener.exitWith_covergroup_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWith_covergroup_expression" ):
                return visitor.visitWith_covergroup_expression(self)
            else:
                return visitor.visitChildren(self)




    def with_covergroup_expression(self):

        localctx = SystemVerilogParser.With_covergroup_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 550, self.RULE_with_covergroup_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4798
            self.covergroup_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Set_covergroup_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_set_covergroup_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSet_covergroup_expression" ):
                listener.enterSet_covergroup_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSet_covergroup_expression" ):
                listener.exitSet_covergroup_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSet_covergroup_expression" ):
                return visitor.visitSet_covergroup_expression(self)
            else:
                return visitor.visitChildren(self)




    def set_covergroup_expression(self):

        localctx = SystemVerilogParser.Set_covergroup_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 552, self.RULE_set_covergroup_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4800
            self.covergroup_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Integer_covergroup_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_integer_covergroup_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInteger_covergroup_expression" ):
                listener.enterInteger_covergroup_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInteger_covergroup_expression" ):
                listener.exitInteger_covergroup_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInteger_covergroup_expression" ):
                return visitor.visitInteger_covergroup_expression(self)
            else:
                return visitor.visitChildren(self)




    def integer_covergroup_expression(self):

        localctx = SystemVerilogParser.Integer_covergroup_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 554, self.RULE_integer_covergroup_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4802
            self.covergroup_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cross_set_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cross_set_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCross_set_expression" ):
                listener.enterCross_set_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCross_set_expression" ):
                listener.exitCross_set_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCross_set_expression" ):
                return visitor.visitCross_set_expression(self)
            else:
                return visitor.visitChildren(self)




    def cross_set_expression(self):

        localctx = SystemVerilogParser.Cross_set_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 556, self.RULE_cross_set_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4804
            self.covergroup_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Covergroup_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_covergroup_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCovergroup_expression" ):
                listener.enterCovergroup_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCovergroup_expression" ):
                listener.exitCovergroup_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCovergroup_expression" ):
                return visitor.visitCovergroup_expression(self)
            else:
                return visitor.visitChildren(self)




    def covergroup_expression(self):

        localctx = SystemVerilogParser.Covergroup_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 558, self.RULE_covergroup_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4806
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Let_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KLET(self):
            return self.getToken(SystemVerilogParser.KLET, 0)

        def let_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def let_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_port_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_let_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLet_declaration" ):
                listener.enterLet_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLet_declaration" ):
                listener.exitLet_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLet_declaration" ):
                return visitor.visitLet_declaration(self)
            else:
                return visitor.visitChildren(self)




    def let_declaration(self):

        localctx = SystemVerilogParser.Let_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 560, self.RULE_let_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4808
            self.match(SystemVerilogParser.KLET)
            self.state = 4809
            self.let_identifier()
            self.state = 4815
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 4810
                self.match(SystemVerilogParser.LP)
                self.state = 4812
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSTRUCT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNION - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)) | (1 << (SystemVerilogParser.KUNTYPED - 276)) | (1 << (SystemVerilogParser.KVIRTUAL - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 4811
                    self.let_port_list()


                self.state = 4814
                self.match(SystemVerilogParser.RP)


            self.state = 4817
            self.match(SystemVerilogParser.EQ)
            self.state = 4818
            self.expression(0)
            self.state = 4819
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Let_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_let_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLet_identifier" ):
                listener.enterLet_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLet_identifier" ):
                listener.exitLet_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLet_identifier" ):
                return visitor.visitLet_identifier(self)
            else:
                return visitor.visitChildren(self)




    def let_identifier(self):

        localctx = SystemVerilogParser.Let_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 562, self.RULE_let_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4821
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Let_port_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def let_port_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Let_port_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Let_port_itemContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_let_port_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLet_port_list" ):
                listener.enterLet_port_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLet_port_list" ):
                listener.exitLet_port_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLet_port_list" ):
                return visitor.visitLet_port_list(self)
            else:
                return visitor.visitChildren(self)




    def let_port_list(self):

        localctx = SystemVerilogParser.Let_port_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 564, self.RULE_let_port_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4823
            self.let_port_item()
            self.state = 4828
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 4824
                self.match(SystemVerilogParser.COMMA)
                self.state = 4825
                self.let_port_item()
                self.state = 4830
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Let_port_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def let_formal_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_formal_typeContext,0)


        def formal_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Formal_port_identifierContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def variable_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_dimensionContext,i)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_let_port_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLet_port_item" ):
                listener.enterLet_port_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLet_port_item" ):
                listener.exitLet_port_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLet_port_item" ):
                return visitor.visitLet_port_item(self)
            else:
                return visitor.visitChildren(self)




    def let_port_item(self):

        localctx = SystemVerilogParser.Let_port_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 566, self.RULE_let_port_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4834
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 4831
                self.attribute_instance()
                self.state = 4836
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4837
            self.let_formal_type()
            self.state = 4838
            self.formal_port_identifier()
            self.state = 4842
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 4839
                self.variable_dimension()
                self.state = 4844
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 4847
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 4845
                self.match(SystemVerilogParser.EQ)
                self.state = 4846
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Let_formal_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type_or_implicit(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_implicitContext,0)


        def KUNTYPED(self):
            return self.getToken(SystemVerilogParser.KUNTYPED, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_let_formal_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLet_formal_type" ):
                listener.enterLet_formal_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLet_formal_type" ):
                listener.exitLet_formal_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLet_formal_type" ):
                return visitor.visitLet_formal_type(self)
            else:
                return visitor.visitChildren(self)




    def let_formal_type(self):

        localctx = SystemVerilogParser.Let_formal_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 568, self.RULE_let_formal_type)
        try:
            self.state = 4851
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.LB, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4849
                self.data_type_or_implicit()
                pass
            elif token in [SystemVerilogParser.KUNTYPED]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4850
                self.match(SystemVerilogParser.KUNTYPED)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Let_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def let_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def let_list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_list_of_argumentsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_let_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLet_expression" ):
                listener.enterLet_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLet_expression" ):
                listener.exitLet_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLet_expression" ):
                return visitor.visitLet_expression(self)
            else:
                return visitor.visitChildren(self)




    def let_expression(self):

        localctx = SystemVerilogParser.Let_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 570, self.RULE_let_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4854
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,575,self._ctx)
            if la_ == 1:
                self.state = 4853
                self.package_scope()


            self.state = 4856
            self.let_identifier()
            self.state = 4862
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,577,self._ctx)
            if la_ == 1:
                self.state = 4857
                self.match(SystemVerilogParser.LP)
                self.state = 4859
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,576,self._ctx)
                if la_ == 1:
                    self.state = 4858
                    self.let_list_of_arguments()


                self.state = 4861
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Let_list_of_argumentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.IdentifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,i)


        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def let_actual_arg(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Let_actual_argContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Let_actual_argContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_let_list_of_arguments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLet_list_of_arguments" ):
                listener.enterLet_list_of_arguments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLet_list_of_arguments" ):
                listener.exitLet_list_of_arguments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLet_list_of_arguments" ):
                return visitor.visitLet_list_of_arguments(self)
            else:
                return visitor.visitChildren(self)




    def let_list_of_arguments(self):

        localctx = SystemVerilogParser.Let_list_of_argumentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 572, self.RULE_let_list_of_arguments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4884
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.RP, SystemVerilogParser.COMMA, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.state = 4865
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 4864
                    self.let_actual_arg()


                self.state = 4873
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,580,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 4867
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 4869
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                            self.state = 4868
                            self.let_actual_arg()

                 
                    self.state = 4875
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,580,self._ctx)

                pass
            elif token in [SystemVerilogParser.DOT]:
                self.state = 4876
                self.match(SystemVerilogParser.DOT)
                self.state = 4877
                self.identifier()
                self.state = 4878
                self.match(SystemVerilogParser.LP)
                self.state = 4880
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 4879
                    self.let_actual_arg()


                self.state = 4882
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

            self.state = 4897
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 4886
                self.match(SystemVerilogParser.COMMA)
                self.state = 4887
                self.match(SystemVerilogParser.DOT)
                self.state = 4888
                self.identifier()
                self.state = 4889
                self.match(SystemVerilogParser.LP)
                self.state = 4891
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 4890
                    self.let_actual_arg()


                self.state = 4893
                self.match(SystemVerilogParser.RP)
                self.state = 4899
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Let_actual_argContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_let_actual_arg

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLet_actual_arg" ):
                listener.enterLet_actual_arg(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLet_actual_arg" ):
                listener.exitLet_actual_arg(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLet_actual_arg" ):
                return visitor.visitLet_actual_arg(self)
            else:
                return visitor.visitChildren(self)




    def let_actual_arg(self):

        localctx = SystemVerilogParser.Let_actual_argContext(self, self._ctx, self.state)
        self.enterRule(localctx, 574, self.RULE_let_actual_arg)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 4900
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Gate_instantiationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cmos_switchtype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cmos_switchtypeContext,0)


        def cmos_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Cmos_switch_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Cmos_switch_instanceContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def delay3(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay3Context,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def enable_gatetype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Enable_gatetypeContext,0)


        def enable_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Enable_gate_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Enable_gate_instanceContext,i)


        def drive_strength(self):
            return self.getTypedRuleContext(SystemVerilogParser.Drive_strengthContext,0)


        def mos_switchtype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Mos_switchtypeContext,0)


        def mos_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Mos_switch_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Mos_switch_instanceContext,i)


        def n_input_gatetype(self):
            return self.getTypedRuleContext(SystemVerilogParser.N_input_gatetypeContext,0)


        def n_input_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.N_input_gate_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.N_input_gate_instanceContext,i)


        def delay2(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay2Context,0)


        def n_output_gatetype(self):
            return self.getTypedRuleContext(SystemVerilogParser.N_output_gatetypeContext,0)


        def n_output_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.N_output_gate_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.N_output_gate_instanceContext,i)


        def pass_en_switchtype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Pass_en_switchtypeContext,0)


        def pass_enable_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Pass_enable_switch_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Pass_enable_switch_instanceContext,i)


        def pass_switchtype(self):
            return self.getTypedRuleContext(SystemVerilogParser.Pass_switchtypeContext,0)


        def pass_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Pass_switch_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Pass_switch_instanceContext,i)


        def KPULLDOWN(self):
            return self.getToken(SystemVerilogParser.KPULLDOWN, 0)

        def pull_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Pull_gate_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Pull_gate_instanceContext,i)


        def pulldown_strength(self):
            return self.getTypedRuleContext(SystemVerilogParser.Pulldown_strengthContext,0)


        def KPULLUP(self):
            return self.getToken(SystemVerilogParser.KPULLUP, 0)

        def pullup_strength(self):
            return self.getTypedRuleContext(SystemVerilogParser.Pullup_strengthContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_gate_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGate_instantiation" ):
                listener.enterGate_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGate_instantiation" ):
                listener.exitGate_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGate_instantiation" ):
                return visitor.visitGate_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def gate_instantiation(self):

        localctx = SystemVerilogParser.Gate_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 576, self.RULE_gate_instantiation)
        self._la = 0 # Token type
        try:
            self.state = 5034
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KCMOS, SystemVerilogParser.KRCMOS]:
                self.enterOuterAlt(localctx, 1)
                self.state = 4902
                self.cmos_switchtype()
                self.state = 4904
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 4903
                    self.delay3()


                self.state = 4906
                self.cmos_switch_instance()
                self.state = 4911
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4907
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4908
                    self.cmos_switch_instance()
                    self.state = 4913
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4914
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KBUFIF0, SystemVerilogParser.KBUFIF1, SystemVerilogParser.KNOTIF0, SystemVerilogParser.KNOTIF1]:
                self.enterOuterAlt(localctx, 2)
                self.state = 4916
                self.enable_gatetype()
                self.state = 4918
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,587,self._ctx)
                if la_ == 1:
                    self.state = 4917
                    self.drive_strength()


                self.state = 4921
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 4920
                    self.delay3()


                self.state = 4923
                self.enable_gate_instance()
                self.state = 4928
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4924
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4925
                    self.enable_gate_instance()
                    self.state = 4930
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4931
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KNMOS, SystemVerilogParser.KPMOS, SystemVerilogParser.KRNMOS, SystemVerilogParser.KRPMOS]:
                self.enterOuterAlt(localctx, 3)
                self.state = 4933
                self.mos_switchtype()
                self.state = 4935
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 4934
                    self.delay3()


                self.state = 4937
                self.mos_switch_instance()
                self.state = 4942
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4938
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4939
                    self.mos_switch_instance()
                    self.state = 4944
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4945
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KAND, SystemVerilogParser.KNAND, SystemVerilogParser.KNOR, SystemVerilogParser.KOR, SystemVerilogParser.KXNOR, SystemVerilogParser.KXOR]:
                self.enterOuterAlt(localctx, 4)
                self.state = 4947
                self.n_input_gatetype()
                self.state = 4949
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,592,self._ctx)
                if la_ == 1:
                    self.state = 4948
                    self.drive_strength()


                self.state = 4952
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 4951
                    self.delay2()


                self.state = 4954
                self.n_input_gate_instance()
                self.state = 4959
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4955
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4956
                    self.n_input_gate_instance()
                    self.state = 4961
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4962
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KBUF, SystemVerilogParser.KNOT]:
                self.enterOuterAlt(localctx, 5)
                self.state = 4964
                self.n_output_gatetype()
                self.state = 4966
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,595,self._ctx)
                if la_ == 1:
                    self.state = 4965
                    self.drive_strength()


                self.state = 4969
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 4968
                    self.delay2()


                self.state = 4971
                self.n_output_gate_instance()
                self.state = 4976
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4972
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4973
                    self.n_output_gate_instance()
                    self.state = 4978
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4979
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KRTRANIF0, SystemVerilogParser.KRTRANIF1, SystemVerilogParser.KTRANIF0, SystemVerilogParser.KTRANIF1]:
                self.enterOuterAlt(localctx, 6)
                self.state = 4981
                self.pass_en_switchtype()
                self.state = 4983
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 4982
                    self.delay2()


                self.state = 4985
                self.pass_enable_switch_instance()
                self.state = 4990
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4986
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4987
                    self.pass_enable_switch_instance()
                    self.state = 4992
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 4993
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KRTRAN, SystemVerilogParser.KTRAN]:
                self.enterOuterAlt(localctx, 7)
                self.state = 4995
                self.pass_switchtype()
                self.state = 4996
                self.pass_switch_instance()
                self.state = 5001
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 4997
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 4998
                    self.pass_switch_instance()
                    self.state = 5003
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5004
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KPULLDOWN]:
                self.enterOuterAlt(localctx, 8)
                self.state = 5006
                self.match(SystemVerilogParser.KPULLDOWN)
                self.state = 5008
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,601,self._ctx)
                if la_ == 1:
                    self.state = 5007
                    self.pulldown_strength()


                self.state = 5010
                self.pull_gate_instance()
                self.state = 5015
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5011
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5012
                    self.pull_gate_instance()
                    self.state = 5017
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5018
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KPULLUP]:
                self.enterOuterAlt(localctx, 9)
                self.state = 5020
                self.match(SystemVerilogParser.KPULLUP)
                self.state = 5022
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,603,self._ctx)
                if la_ == 1:
                    self.state = 5021
                    self.pullup_strength()


                self.state = 5024
                self.pull_gate_instance()
                self.state = 5029
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5025
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5026
                    self.pull_gate_instance()
                    self.state = 5031
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5032
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cmos_switch_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Output_terminalContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def input_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Input_terminalContext,0)


        def ncontrol_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ncontrol_terminalContext,0)


        def pcontrol_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Pcontrol_terminalContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cmos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switch_instance" ):
                listener.enterCmos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switch_instance" ):
                listener.exitCmos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switch_instance" ):
                return visitor.visitCmos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switch_instance(self):

        localctx = SystemVerilogParser.Cmos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 578, self.RULE_cmos_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5037
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5036
                self.name_of_instance()


            self.state = 5039
            self.match(SystemVerilogParser.LP)
            self.state = 5040
            self.output_terminal()
            self.state = 5041
            self.match(SystemVerilogParser.COMMA)
            self.state = 5042
            self.input_terminal()
            self.state = 5043
            self.match(SystemVerilogParser.COMMA)
            self.state = 5044
            self.ncontrol_terminal()
            self.state = 5045
            self.match(SystemVerilogParser.COMMA)
            self.state = 5046
            self.pcontrol_terminal()
            self.state = 5047
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Output_terminalContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def input_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Input_terminalContext,0)


        def enable_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Enable_terminalContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_enable_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gate_instance" ):
                listener.enterEnable_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gate_instance" ):
                listener.exitEnable_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gate_instance" ):
                return visitor.visitEnable_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def enable_gate_instance(self):

        localctx = SystemVerilogParser.Enable_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 580, self.RULE_enable_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5050
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5049
                self.name_of_instance()


            self.state = 5052
            self.match(SystemVerilogParser.LP)
            self.state = 5053
            self.output_terminal()
            self.state = 5054
            self.match(SystemVerilogParser.COMMA)
            self.state = 5055
            self.input_terminal()
            self.state = 5056
            self.match(SystemVerilogParser.COMMA)
            self.state = 5057
            self.enable_terminal()
            self.state = 5058
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mos_switch_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Output_terminalContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def input_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Input_terminalContext,0)


        def enable_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Enable_terminalContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_mos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switch_instance" ):
                listener.enterMos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switch_instance" ):
                listener.exitMos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switch_instance" ):
                return visitor.visitMos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def mos_switch_instance(self):

        localctx = SystemVerilogParser.Mos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 582, self.RULE_mos_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5061
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5060
                self.name_of_instance()


            self.state = 5063
            self.match(SystemVerilogParser.LP)
            self.state = 5064
            self.output_terminal()
            self.state = 5065
            self.match(SystemVerilogParser.COMMA)
            self.state = 5066
            self.input_terminal()
            self.state = 5067
            self.match(SystemVerilogParser.COMMA)
            self.state = 5068
            self.enable_terminal()
            self.state = 5069
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_input_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Output_terminalContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def input_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Input_terminalContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Input_terminalContext,i)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_n_input_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gate_instance" ):
                listener.enterN_input_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gate_instance" ):
                listener.exitN_input_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gate_instance" ):
                return visitor.visitN_input_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gate_instance(self):

        localctx = SystemVerilogParser.N_input_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 584, self.RULE_n_input_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5072
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5071
                self.name_of_instance()


            self.state = 5074
            self.match(SystemVerilogParser.LP)
            self.state = 5075
            self.output_terminal()
            self.state = 5076
            self.match(SystemVerilogParser.COMMA)
            self.state = 5077
            self.input_terminal()
            self.state = 5082
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 5078
                self.match(SystemVerilogParser.COMMA)
                self.state = 5079
                self.input_terminal()
                self.state = 5084
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5085
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_output_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def output_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Output_terminalContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Output_terminalContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def input_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Input_terminalContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_n_output_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gate_instance" ):
                listener.enterN_output_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gate_instance" ):
                listener.exitN_output_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gate_instance" ):
                return visitor.visitN_output_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gate_instance(self):

        localctx = SystemVerilogParser.N_output_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 586, self.RULE_n_output_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5088
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5087
                self.name_of_instance()


            self.state = 5090
            self.match(SystemVerilogParser.LP)
            self.state = 5091
            self.output_terminal()
            self.state = 5096
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,612,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 5092
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5093
                    self.output_terminal() 
                self.state = 5098
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,612,self._ctx)

            self.state = 5099
            self.match(SystemVerilogParser.COMMA)
            self.state = 5100
            self.input_terminal()
            self.state = 5101
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_switch_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def inout_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Inout_terminalContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Inout_terminalContext,i)


        def COMMA(self):
            return self.getToken(SystemVerilogParser.COMMA, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pass_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switch_instance" ):
                listener.enterPass_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switch_instance" ):
                listener.exitPass_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switch_instance" ):
                return visitor.visitPass_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def pass_switch_instance(self):

        localctx = SystemVerilogParser.Pass_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 588, self.RULE_pass_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5104
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5103
                self.name_of_instance()


            self.state = 5106
            self.match(SystemVerilogParser.LP)
            self.state = 5107
            self.inout_terminal()
            self.state = 5108
            self.match(SystemVerilogParser.COMMA)
            self.state = 5109
            self.inout_terminal()
            self.state = 5110
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_enable_switch_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def inout_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Inout_terminalContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Inout_terminalContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def enable_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Enable_terminalContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pass_enable_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_enable_switch_instance" ):
                listener.enterPass_enable_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_enable_switch_instance" ):
                listener.exitPass_enable_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_enable_switch_instance" ):
                return visitor.visitPass_enable_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def pass_enable_switch_instance(self):

        localctx = SystemVerilogParser.Pass_enable_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 590, self.RULE_pass_enable_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5113
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5112
                self.name_of_instance()


            self.state = 5115
            self.match(SystemVerilogParser.LP)
            self.state = 5116
            self.inout_terminal()
            self.state = 5117
            self.match(SystemVerilogParser.COMMA)
            self.state = 5118
            self.inout_terminal()
            self.state = 5119
            self.match(SystemVerilogParser.COMMA)
            self.state = 5120
            self.enable_terminal()
            self.state = 5121
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pull_gate_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Output_terminalContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pull_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPull_gate_instance" ):
                listener.enterPull_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPull_gate_instance" ):
                listener.exitPull_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPull_gate_instance" ):
                return visitor.visitPull_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def pull_gate_instance(self):

        localctx = SystemVerilogParser.Pull_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 592, self.RULE_pull_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5124
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5123
                self.name_of_instance()


            self.state = 5126
            self.match(SystemVerilogParser.LP)
            self.state = 5127
            self.output_terminal()
            self.state = 5128
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pulldown_strengthContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def strength0(self):
            return self.getTypedRuleContext(SystemVerilogParser.Strength0Context,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def COMMA(self):
            return self.getToken(SystemVerilogParser.COMMA, 0)

        def strength1(self):
            return self.getTypedRuleContext(SystemVerilogParser.Strength1Context,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pulldown_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulldown_strength" ):
                listener.enterPulldown_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulldown_strength" ):
                listener.exitPulldown_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulldown_strength" ):
                return visitor.visitPulldown_strength(self)
            else:
                return visitor.visitChildren(self)




    def pulldown_strength(self):

        localctx = SystemVerilogParser.Pulldown_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 594, self.RULE_pulldown_strength)
        self._la = 0 # Token type
        try:
            self.state = 5144
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,617,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5130
                self.match(SystemVerilogParser.LP)
                self.state = 5131
                self.strength0()
                self.state = 5134
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COMMA:
                    self.state = 5132
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5133
                    self.strength1()


                self.state = 5136
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5138
                self.match(SystemVerilogParser.LP)
                self.state = 5139
                self.strength1()
                self.state = 5140
                self.match(SystemVerilogParser.COMMA)
                self.state = 5141
                self.strength0()
                self.state = 5142
                self.match(SystemVerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pullup_strengthContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def strength0(self):
            return self.getTypedRuleContext(SystemVerilogParser.Strength0Context,0)


        def COMMA(self):
            return self.getToken(SystemVerilogParser.COMMA, 0)

        def strength1(self):
            return self.getTypedRuleContext(SystemVerilogParser.Strength1Context,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pullup_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPullup_strength" ):
                listener.enterPullup_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPullup_strength" ):
                listener.exitPullup_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPullup_strength" ):
                return visitor.visitPullup_strength(self)
            else:
                return visitor.visitChildren(self)




    def pullup_strength(self):

        localctx = SystemVerilogParser.Pullup_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 596, self.RULE_pullup_strength)
        self._la = 0 # Token type
        try:
            self.state = 5160
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,619,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5146
                self.match(SystemVerilogParser.LP)
                self.state = 5147
                self.strength0()
                self.state = 5148
                self.match(SystemVerilogParser.COMMA)
                self.state = 5149
                self.strength1()
                self.state = 5150
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5152
                self.match(SystemVerilogParser.LP)
                self.state = 5153
                self.strength1()
                self.state = 5156
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COMMA:
                    self.state = 5154
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5155
                    self.strength0()


                self.state = 5158
                self.match(SystemVerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_enable_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_terminal" ):
                listener.enterEnable_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_terminal" ):
                listener.exitEnable_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_terminal" ):
                return visitor.visitEnable_terminal(self)
            else:
                return visitor.visitChildren(self)




    def enable_terminal(self):

        localctx = SystemVerilogParser.Enable_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 598, self.RULE_enable_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5162
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_lvalueContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_inout_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_terminal" ):
                listener.enterInout_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_terminal" ):
                listener.exitInout_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_terminal" ):
                return visitor.visitInout_terminal(self)
            else:
                return visitor.visitChildren(self)




    def inout_terminal(self):

        localctx = SystemVerilogParser.Inout_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 600, self.RULE_inout_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5164
            self.net_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_input_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_terminal" ):
                listener.enterInput_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_terminal" ):
                listener.exitInput_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_terminal" ):
                return visitor.visitInput_terminal(self)
            else:
                return visitor.visitChildren(self)




    def input_terminal(self):

        localctx = SystemVerilogParser.Input_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 602, self.RULE_input_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5166
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ncontrol_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ncontrol_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNcontrol_terminal" ):
                listener.enterNcontrol_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNcontrol_terminal" ):
                listener.exitNcontrol_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNcontrol_terminal" ):
                return visitor.visitNcontrol_terminal(self)
            else:
                return visitor.visitChildren(self)




    def ncontrol_terminal(self):

        localctx = SystemVerilogParser.Ncontrol_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 604, self.RULE_ncontrol_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5168
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_lvalueContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_output_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_terminal" ):
                listener.enterOutput_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_terminal" ):
                listener.exitOutput_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_terminal" ):
                return visitor.visitOutput_terminal(self)
            else:
                return visitor.visitChildren(self)




    def output_terminal(self):

        localctx = SystemVerilogParser.Output_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 606, self.RULE_output_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5170
            self.net_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pcontrol_terminalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pcontrol_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPcontrol_terminal" ):
                listener.enterPcontrol_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPcontrol_terminal" ):
                listener.exitPcontrol_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPcontrol_terminal" ):
                return visitor.visitPcontrol_terminal(self)
            else:
                return visitor.visitChildren(self)




    def pcontrol_terminal(self):

        localctx = SystemVerilogParser.Pcontrol_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 608, self.RULE_pcontrol_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5172
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cmos_switchtypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCMOS(self):
            return self.getToken(SystemVerilogParser.KCMOS, 0)

        def KRCMOS(self):
            return self.getToken(SystemVerilogParser.KRCMOS, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cmos_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switchtype" ):
                listener.enterCmos_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switchtype" ):
                listener.exitCmos_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switchtype" ):
                return visitor.visitCmos_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switchtype(self):

        localctx = SystemVerilogParser.Cmos_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 610, self.RULE_cmos_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5174
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KCMOS or _la==SystemVerilogParser.KRCMOS):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_gatetypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KBUFIF0(self):
            return self.getToken(SystemVerilogParser.KBUFIF0, 0)

        def KBUFIF1(self):
            return self.getToken(SystemVerilogParser.KBUFIF1, 0)

        def KNOTIF0(self):
            return self.getToken(SystemVerilogParser.KNOTIF0, 0)

        def KNOTIF1(self):
            return self.getToken(SystemVerilogParser.KNOTIF1, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_enable_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gatetype" ):
                listener.enterEnable_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gatetype" ):
                listener.exitEnable_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gatetype" ):
                return visitor.visitEnable_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def enable_gatetype(self):

        localctx = SystemVerilogParser.Enable_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 612, self.RULE_enable_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5176
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KBUFIF0 or _la==SystemVerilogParser.KBUFIF1 or _la==SystemVerilogParser.KNOTIF0 or _la==SystemVerilogParser.KNOTIF1):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mos_switchtypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KNMOS(self):
            return self.getToken(SystemVerilogParser.KNMOS, 0)

        def KPMOS(self):
            return self.getToken(SystemVerilogParser.KPMOS, 0)

        def KRNMOS(self):
            return self.getToken(SystemVerilogParser.KRNMOS, 0)

        def KRPMOS(self):
            return self.getToken(SystemVerilogParser.KRPMOS, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_mos_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switchtype" ):
                listener.enterMos_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switchtype" ):
                listener.exitMos_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switchtype" ):
                return visitor.visitMos_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def mos_switchtype(self):

        localctx = SystemVerilogParser.Mos_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 614, self.RULE_mos_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5178
            _la = self._input.LA(1)
            if not(((((_la - 222)) & ~0x3f) == 0 and ((1 << (_la - 222)) & ((1 << (SystemVerilogParser.KNMOS - 222)) | (1 << (SystemVerilogParser.KPMOS - 222)) | (1 << (SystemVerilogParser.KRNMOS - 222)) | (1 << (SystemVerilogParser.KRPMOS - 222)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_input_gatetypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KAND(self):
            return self.getToken(SystemVerilogParser.KAND, 0)

        def KNAND(self):
            return self.getToken(SystemVerilogParser.KNAND, 0)

        def KOR(self):
            return self.getToken(SystemVerilogParser.KOR, 0)

        def KNOR(self):
            return self.getToken(SystemVerilogParser.KNOR, 0)

        def KXOR(self):
            return self.getToken(SystemVerilogParser.KXOR, 0)

        def KXNOR(self):
            return self.getToken(SystemVerilogParser.KXNOR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_n_input_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gatetype" ):
                listener.enterN_input_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gatetype" ):
                listener.exitN_input_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gatetype" ):
                return visitor.visitN_input_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gatetype(self):

        localctx = SystemVerilogParser.N_input_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 616, self.RULE_n_input_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5180
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KAND or ((((_la - 217)) & ~0x3f) == 0 and ((1 << (_la - 217)) & ((1 << (SystemVerilogParser.KNAND - 217)) | (1 << (SystemVerilogParser.KNOR - 217)) | (1 << (SystemVerilogParser.KOR - 217)))) != 0) or _la==SystemVerilogParser.KXNOR or _la==SystemVerilogParser.KXOR):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_output_gatetypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KBUF(self):
            return self.getToken(SystemVerilogParser.KBUF, 0)

        def KNOT(self):
            return self.getToken(SystemVerilogParser.KNOT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_n_output_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gatetype" ):
                listener.enterN_output_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gatetype" ):
                listener.exitN_output_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gatetype" ):
                return visitor.visitN_output_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gatetype(self):

        localctx = SystemVerilogParser.N_output_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 618, self.RULE_n_output_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5182
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KBUF or _la==SystemVerilogParser.KNOT):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_en_switchtypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KTRANIF0(self):
            return self.getToken(SystemVerilogParser.KTRANIF0, 0)

        def KTRANIF1(self):
            return self.getToken(SystemVerilogParser.KTRANIF1, 0)

        def KRTRANIF1(self):
            return self.getToken(SystemVerilogParser.KRTRANIF1, 0)

        def KRTRANIF0(self):
            return self.getToken(SystemVerilogParser.KRTRANIF0, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pass_en_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_en_switchtype" ):
                listener.enterPass_en_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_en_switchtype" ):
                listener.exitPass_en_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_en_switchtype" ):
                return visitor.visitPass_en_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def pass_en_switchtype(self):

        localctx = SystemVerilogParser.Pass_en_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 620, self.RULE_pass_en_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5184
            _la = self._input.LA(1)
            if not(((((_la - 267)) & ~0x3f) == 0 and ((1 << (_la - 267)) & ((1 << (SystemVerilogParser.KRTRANIF0 - 267)) | (1 << (SystemVerilogParser.KRTRANIF1 - 267)) | (1 << (SystemVerilogParser.KTRANIF0 - 267)) | (1 << (SystemVerilogParser.KTRANIF1 - 267)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_switchtypeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KTRAN(self):
            return self.getToken(SystemVerilogParser.KTRAN, 0)

        def KRTRAN(self):
            return self.getToken(SystemVerilogParser.KRTRAN, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pass_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switchtype" ):
                listener.enterPass_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switchtype" ):
                listener.exitPass_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switchtype" ):
                return visitor.visitPass_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def pass_switchtype(self):

        localctx = SystemVerilogParser.Pass_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 622, self.RULE_pass_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5186
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KRTRAN or _la==SystemVerilogParser.KTRAN):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_instantiationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_identifierContext,0)


        def hierarchical_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Hierarchical_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_instanceContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def parameter_value_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_value_assignmentContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instantiation" ):
                listener.enterModule_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instantiation" ):
                listener.exitModule_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instantiation" ):
                return visitor.visitModule_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def module_instantiation(self):

        localctx = SystemVerilogParser.Module_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 624, self.RULE_module_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5188
            self.module_identifier()
            self.state = 5190
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 5189
                self.parameter_value_assignment()


            self.state = 5192
            self.hierarchical_instance()
            self.state = 5197
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 5193
                self.match(SystemVerilogParser.COMMA)
                self.state = 5194
                self.hierarchical_instance()
                self.state = 5199
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5200
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_value_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def P(self):
            return self.getToken(SystemVerilogParser.P, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def list_of_parameter_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_parameter_assignmentsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_parameter_value_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_value_assignment" ):
                listener.enterParameter_value_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_value_assignment" ):
                listener.exitParameter_value_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_value_assignment" ):
                return visitor.visitParameter_value_assignment(self)
            else:
                return visitor.visitChildren(self)




    def parameter_value_assignment(self):

        localctx = SystemVerilogParser.Parameter_value_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 626, self.RULE_parameter_value_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5202
            self.match(SystemVerilogParser.P)
            self.state = 5203
            self.match(SystemVerilogParser.LP)
            self.state = 5205
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.DOT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCHANDLE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KLOCAL - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)))) != 0) or ((((_la - 228)) & ~0x3f) == 0 and ((1 << (_la - 228)) & ((1 << (SystemVerilogParser.KNULL - 228)) | (1 << (SystemVerilogParser.KRANDOMIZE - 228)) | (1 << (SystemVerilogParser.KREAL - 228)) | (1 << (SystemVerilogParser.KREALTIME - 228)) | (1 << (SystemVerilogParser.KREG - 228)) | (1 << (SystemVerilogParser.KSHORTINT - 228)) | (1 << (SystemVerilogParser.KSHORTREAL - 228)) | (1 << (SystemVerilogParser.KSIGNED - 228)) | (1 << (SystemVerilogParser.KSTD - 228)) | (1 << (SystemVerilogParser.KSTRING - 228)) | (1 << (SystemVerilogParser.KSTRUCT - 228)))) != 0) or ((((_la - 292)) & ~0x3f) == 0 and ((1 << (_la - 292)) & ((1 << (SystemVerilogParser.KSUPER - 292)) | (1 << (SystemVerilogParser.KTAGGED - 292)) | (1 << (SystemVerilogParser.KTHIS - 292)) | (1 << (SystemVerilogParser.KTIME - 292)) | (1 << (SystemVerilogParser.KTYPE - 292)) | (1 << (SystemVerilogParser.KUNION - 292)) | (1 << (SystemVerilogParser.KUNSIGNED - 292)) | (1 << (SystemVerilogParser.KVIRTUAL - 292)) | (1 << (SystemVerilogParser.TIME_LITERAL - 292)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 292)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 292)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 292)) | (1 << (SystemVerilogParser.HEX_NUMBER - 292)) | (1 << (SystemVerilogParser.REAL_NUMBER - 292)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 292)) | (1 << (SystemVerilogParser.STRING_LITERAL - 292)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 292)))) != 0) or _la==SystemVerilogParser.SYSTEM_TF_IDENTIFIER:
                self.state = 5204
                self.list_of_parameter_assignments()


            self.state = 5207
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_parameter_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ordered_parameter_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Ordered_parameter_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Ordered_parameter_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def named_parameter_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Named_parameter_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Named_parameter_assignmentContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_parameter_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_parameter_assignments" ):
                listener.enterList_of_parameter_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_parameter_assignments" ):
                listener.exitList_of_parameter_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_parameter_assignments" ):
                return visitor.visitList_of_parameter_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_parameter_assignments(self):

        localctx = SystemVerilogParser.List_of_parameter_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 628, self.RULE_list_of_parameter_assignments)
        self._la = 0 # Token type
        try:
            self.state = 5225
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCHANDLE, SystemVerilogParser.KCONST, SystemVerilogParser.KENUM, SystemVerilogParser.KEVENT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSTRUCT, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNION, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.KVIRTUAL, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5209
                self.ordered_parameter_assignment()
                self.state = 5214
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5210
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5211
                    self.ordered_parameter_assignment()
                    self.state = 5216
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            elif token in [SystemVerilogParser.DOT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5217
                self.named_parameter_assignment()
                self.state = 5222
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5218
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5219
                    self.named_parameter_assignment()
                    self.state = 5224
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ordered_parameter_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def param_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Param_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ordered_parameter_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOrdered_parameter_assignment" ):
                listener.enterOrdered_parameter_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOrdered_parameter_assignment" ):
                listener.exitOrdered_parameter_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOrdered_parameter_assignment" ):
                return visitor.visitOrdered_parameter_assignment(self)
            else:
                return visitor.visitChildren(self)




    def ordered_parameter_assignment(self):

        localctx = SystemVerilogParser.Ordered_parameter_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 630, self.RULE_ordered_parameter_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5227
            self.param_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Named_parameter_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def parameter_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def param_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Param_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_named_parameter_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNamed_parameter_assignment" ):
                listener.enterNamed_parameter_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNamed_parameter_assignment" ):
                listener.exitNamed_parameter_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNamed_parameter_assignment" ):
                return visitor.visitNamed_parameter_assignment(self)
            else:
                return visitor.visitChildren(self)




    def named_parameter_assignment(self):

        localctx = SystemVerilogParser.Named_parameter_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 632, self.RULE_named_parameter_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5229
            self.match(SystemVerilogParser.DOT)
            self.state = 5230
            self.parameter_identifier()
            self.state = 5231
            self.match(SystemVerilogParser.LP)
            self.state = 5233
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCHANDLE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KLOCAL - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)))) != 0) or ((((_la - 228)) & ~0x3f) == 0 and ((1 << (_la - 228)) & ((1 << (SystemVerilogParser.KNULL - 228)) | (1 << (SystemVerilogParser.KRANDOMIZE - 228)) | (1 << (SystemVerilogParser.KREAL - 228)) | (1 << (SystemVerilogParser.KREALTIME - 228)) | (1 << (SystemVerilogParser.KREG - 228)) | (1 << (SystemVerilogParser.KSHORTINT - 228)) | (1 << (SystemVerilogParser.KSHORTREAL - 228)) | (1 << (SystemVerilogParser.KSIGNED - 228)) | (1 << (SystemVerilogParser.KSTD - 228)) | (1 << (SystemVerilogParser.KSTRING - 228)) | (1 << (SystemVerilogParser.KSTRUCT - 228)))) != 0) or ((((_la - 292)) & ~0x3f) == 0 and ((1 << (_la - 292)) & ((1 << (SystemVerilogParser.KSUPER - 292)) | (1 << (SystemVerilogParser.KTAGGED - 292)) | (1 << (SystemVerilogParser.KTHIS - 292)) | (1 << (SystemVerilogParser.KTIME - 292)) | (1 << (SystemVerilogParser.KTYPE - 292)) | (1 << (SystemVerilogParser.KUNION - 292)) | (1 << (SystemVerilogParser.KUNSIGNED - 292)) | (1 << (SystemVerilogParser.KVIRTUAL - 292)) | (1 << (SystemVerilogParser.TIME_LITERAL - 292)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 292)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 292)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 292)) | (1 << (SystemVerilogParser.HEX_NUMBER - 292)) | (1 << (SystemVerilogParser.REAL_NUMBER - 292)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 292)) | (1 << (SystemVerilogParser.STRING_LITERAL - 292)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 292)))) != 0) or _la==SystemVerilogParser.SYSTEM_TF_IDENTIFIER:
                self.state = 5232
                self.param_expression()


            self.state = 5235
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def list_of_port_connections(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_port_connectionsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_instance" ):
                listener.enterHierarchical_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_instance" ):
                listener.exitHierarchical_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_instance" ):
                return visitor.visitHierarchical_instance(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_instance(self):

        localctx = SystemVerilogParser.Hierarchical_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 634, self.RULE_hierarchical_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5237
            self.name_of_instance()
            self.state = 5238
            self.match(SystemVerilogParser.LP)
            self.state = 5240
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,627,self._ctx)
            if la_ == 1:
                self.state = 5239
                self.list_of_port_connections()


            self.state = 5242
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Name_of_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def instance_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Instance_identifierContext,0)


        def unpacked_dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Unpacked_dimensionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Unpacked_dimensionContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_name_of_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterName_of_instance" ):
                listener.enterName_of_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitName_of_instance" ):
                listener.exitName_of_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitName_of_instance" ):
                return visitor.visitName_of_instance(self)
            else:
                return visitor.visitChildren(self)




    def name_of_instance(self):

        localctx = SystemVerilogParser.Name_of_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 636, self.RULE_name_of_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5244
            self.instance_identifier()
            self.state = 5248
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LB:
                self.state = 5245
                self.unpacked_dimension()
                self.state = 5250
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_connectionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ordered_port_connection(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Ordered_port_connectionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Ordered_port_connectionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def named_port_connection(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Named_port_connectionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Named_port_connectionContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_port_connections

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_connections" ):
                listener.enterList_of_port_connections(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_connections" ):
                listener.exitList_of_port_connections(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_connections" ):
                return visitor.visitList_of_port_connections(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_connections(self):

        localctx = SystemVerilogParser.List_of_port_connectionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 638, self.RULE_list_of_port_connections)
        self._la = 0 # Token type
        try:
            self.state = 5267
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,631,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5251
                self.ordered_port_connection()
                self.state = 5256
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5252
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5253
                    self.ordered_port_connection()
                    self.state = 5258
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5259
                self.named_port_connection()
                self.state = 5264
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5260
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5261
                    self.named_port_connection()
                    self.state = 5266
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ordered_port_connectionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ordered_port_connection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOrdered_port_connection" ):
                listener.enterOrdered_port_connection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOrdered_port_connection" ):
                listener.exitOrdered_port_connection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOrdered_port_connection" ):
                return visitor.visitOrdered_port_connection(self)
            else:
                return visitor.visitChildren(self)




    def ordered_port_connection(self):

        localctx = SystemVerilogParser.Ordered_port_connectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 640, self.RULE_ordered_port_connection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5272
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 5269
                self.attribute_instance()
                self.state = 5274
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5276
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 5275
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Named_port_connectionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,0)


        def DOTSTAR(self):
            return self.getToken(SystemVerilogParser.DOTSTAR, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_named_port_connection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNamed_port_connection" ):
                listener.enterNamed_port_connection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNamed_port_connection" ):
                listener.exitNamed_port_connection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNamed_port_connection" ):
                return visitor.visitNamed_port_connection(self)
            else:
                return visitor.visitChildren(self)




    def named_port_connection(self):

        localctx = SystemVerilogParser.Named_port_connectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 642, self.RULE_named_port_connection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5281
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 5278
                self.attribute_instance()
                self.state = 5283
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5294
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DOT]:
                self.state = 5284
                self.match(SystemVerilogParser.DOT)
                self.state = 5285
                self.port_identifier()
                self.state = 5291
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 5286
                    self.match(SystemVerilogParser.LP)
                    self.state = 5288
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                        self.state = 5287
                        self.expression(0)


                    self.state = 5290
                    self.match(SystemVerilogParser.RP)


                pass
            elif token in [SystemVerilogParser.DOTSTAR]:
                self.state = 5293
                self.match(SystemVerilogParser.DOTSTAR)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_instantiationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def hierarchical_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Hierarchical_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_instanceContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def parameter_value_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_value_assignmentContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_instantiation" ):
                listener.enterInterface_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_instantiation" ):
                listener.exitInterface_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_instantiation" ):
                return visitor.visitInterface_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def interface_instantiation(self):

        localctx = SystemVerilogParser.Interface_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 644, self.RULE_interface_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5296
            self.interface_identifier()
            self.state = 5298
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 5297
                self.parameter_value_assignment()


            self.state = 5300
            self.hierarchical_instance()
            self.state = 5305
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 5301
                self.match(SystemVerilogParser.COMMA)
                self.state = 5302
                self.hierarchical_instance()
                self.state = 5307
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5308
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Program_instantiationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def program_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Program_identifierContext,0)


        def hierarchical_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Hierarchical_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_instanceContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def parameter_value_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_value_assignmentContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_program_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProgram_instantiation" ):
                listener.enterProgram_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProgram_instantiation" ):
                listener.exitProgram_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProgram_instantiation" ):
                return visitor.visitProgram_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def program_instantiation(self):

        localctx = SystemVerilogParser.Program_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 646, self.RULE_program_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5310
            self.program_identifier()
            self.state = 5312
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P:
                self.state = 5311
                self.parameter_value_assignment()


            self.state = 5314
            self.hierarchical_instance()
            self.state = 5319
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 5315
                self.match(SystemVerilogParser.COMMA)
                self.state = 5316
                self.hierarchical_instance()
                self.state = 5321
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5322
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_instantiationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ps_checker_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_checker_identifierContext,0)


        def name_of_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Name_of_instanceContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def list_of_checker_port_connections(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_checker_port_connectionsContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_instantiation" ):
                listener.enterChecker_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_instantiation" ):
                listener.exitChecker_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_instantiation" ):
                return visitor.visitChecker_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def checker_instantiation(self):

        localctx = SystemVerilogParser.Checker_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 648, self.RULE_checker_instantiation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5324
            self.ps_checker_identifier()
            self.state = 5325
            self.name_of_instance()
            self.state = 5326
            self.match(SystemVerilogParser.LP)
            self.state = 5328
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,642,self._ctx)
            if la_ == 1:
                self.state = 5327
                self.list_of_checker_port_connections()


            self.state = 5330
            self.match(SystemVerilogParser.RP)
            self.state = 5331
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_checker_port_connectionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ordered_checker_port_connection(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Ordered_checker_port_connectionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Ordered_checker_port_connectionContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def named_checker_port_connection(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Named_checker_port_connectionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Named_checker_port_connectionContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_checker_port_connections

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_checker_port_connections" ):
                listener.enterList_of_checker_port_connections(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_checker_port_connections" ):
                listener.exitList_of_checker_port_connections(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_checker_port_connections" ):
                return visitor.visitList_of_checker_port_connections(self)
            else:
                return visitor.visitChildren(self)




    def list_of_checker_port_connections(self):

        localctx = SystemVerilogParser.List_of_checker_port_connectionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 650, self.RULE_list_of_checker_port_connections)
        self._la = 0 # Token type
        try:
            self.state = 5349
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,645,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5333
                self.ordered_checker_port_connection()
                self.state = 5338
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5334
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5335
                    self.ordered_checker_port_connection()
                    self.state = 5340
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5341
                self.named_checker_port_connection()
                self.state = 5346
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5342
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5343
                    self.named_checker_port_connection()
                    self.state = 5348
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ordered_checker_port_connectionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def property_actual_arg(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_actual_argContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ordered_checker_port_connection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOrdered_checker_port_connection" ):
                listener.enterOrdered_checker_port_connection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOrdered_checker_port_connection" ):
                listener.exitOrdered_checker_port_connection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOrdered_checker_port_connection" ):
                return visitor.visitOrdered_checker_port_connection(self)
            else:
                return visitor.visitChildren(self)




    def ordered_checker_port_connection(self):

        localctx = SystemVerilogParser.Ordered_checker_port_connectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 652, self.RULE_ordered_checker_port_connection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5354
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 5351
                self.attribute_instance()
                self.state = 5356
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5358
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KACCEPT_ON - 64)) | (1 << (SystemVerilogParser.KALWAYS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCASE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KEVENTUALLY - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KIF - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNEXTTIME - 207)) | (1 << (SystemVerilogParser.KNOT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)) | (1 << (SystemVerilogParser.KREJECT_ON - 207)) | (1 << (SystemVerilogParser.KS_ALWAYS - 207)) | (1 << (SystemVerilogParser.KS_EVENTUALLY - 207)))) != 0) or ((((_la - 271)) & ~0x3f) == 0 and ((1 << (_la - 271)) & ((1 << (SystemVerilogParser.KS_NEXTTIME - 271)) | (1 << (SystemVerilogParser.KSHORTINT - 271)) | (1 << (SystemVerilogParser.KSHORTREAL - 271)) | (1 << (SystemVerilogParser.KSIGNED - 271)) | (1 << (SystemVerilogParser.KSTD - 271)) | (1 << (SystemVerilogParser.KSTRING - 271)) | (1 << (SystemVerilogParser.KSTRONG - 271)) | (1 << (SystemVerilogParser.KSUPER - 271)) | (1 << (SystemVerilogParser.KSYNC_ACCEPT_ON - 271)) | (1 << (SystemVerilogParser.KSYNC_REJECT_ON - 271)) | (1 << (SystemVerilogParser.KTAGGED - 271)) | (1 << (SystemVerilogParser.KTHIS - 271)) | (1 << (SystemVerilogParser.KTIME - 271)) | (1 << (SystemVerilogParser.KTYPE - 271)) | (1 << (SystemVerilogParser.KUNSIGNED - 271)) | (1 << (SystemVerilogParser.KWEAK - 271)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 5357
                self.property_actual_arg()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Named_checker_port_connectionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def formal_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Formal_port_identifierContext,0)


        def DOTSTAR(self):
            return self.getToken(SystemVerilogParser.DOTSTAR, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def property_actual_arg(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_actual_argContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_named_checker_port_connection

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNamed_checker_port_connection" ):
                listener.enterNamed_checker_port_connection(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNamed_checker_port_connection" ):
                listener.exitNamed_checker_port_connection(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNamed_checker_port_connection" ):
                return visitor.visitNamed_checker_port_connection(self)
            else:
                return visitor.visitChildren(self)




    def named_checker_port_connection(self):

        localctx = SystemVerilogParser.Named_checker_port_connectionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 654, self.RULE_named_checker_port_connection)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5363
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 5360
                self.attribute_instance()
                self.state = 5365
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5376
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DOT]:
                self.state = 5366
                self.match(SystemVerilogParser.DOT)
                self.state = 5367
                self.formal_port_identifier()
                self.state = 5373
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 5368
                    self.match(SystemVerilogParser.LP)
                    self.state = 5370
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KACCEPT_ON - 64)) | (1 << (SystemVerilogParser.KALWAYS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCASE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SystemVerilogParser.KEDGE - 140)) | (1 << (SystemVerilogParser.KEVENTUALLY - 140)) | (1 << (SystemVerilogParser.KFIRST_MATCH - 140)) | (1 << (SystemVerilogParser.KIF - 140)) | (1 << (SystemVerilogParser.KINT - 140)) | (1 << (SystemVerilogParser.KINTEGER - 140)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNEGEDGE - 207)) | (1 << (SystemVerilogParser.KNEXTTIME - 207)) | (1 << (SystemVerilogParser.KNOT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPOSEDGE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)) | (1 << (SystemVerilogParser.KREJECT_ON - 207)) | (1 << (SystemVerilogParser.KS_ALWAYS - 207)) | (1 << (SystemVerilogParser.KS_EVENTUALLY - 207)))) != 0) or ((((_la - 271)) & ~0x3f) == 0 and ((1 << (_la - 271)) & ((1 << (SystemVerilogParser.KS_NEXTTIME - 271)) | (1 << (SystemVerilogParser.KSHORTINT - 271)) | (1 << (SystemVerilogParser.KSHORTREAL - 271)) | (1 << (SystemVerilogParser.KSIGNED - 271)) | (1 << (SystemVerilogParser.KSTD - 271)) | (1 << (SystemVerilogParser.KSTRING - 271)) | (1 << (SystemVerilogParser.KSTRONG - 271)) | (1 << (SystemVerilogParser.KSUPER - 271)) | (1 << (SystemVerilogParser.KSYNC_ACCEPT_ON - 271)) | (1 << (SystemVerilogParser.KSYNC_REJECT_ON - 271)) | (1 << (SystemVerilogParser.KTAGGED - 271)) | (1 << (SystemVerilogParser.KTHIS - 271)) | (1 << (SystemVerilogParser.KTIME - 271)) | (1 << (SystemVerilogParser.KTYPE - 271)) | (1 << (SystemVerilogParser.KUNSIGNED - 271)) | (1 << (SystemVerilogParser.KWEAK - 271)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                        self.state = 5369
                        self.property_actual_arg()


                    self.state = 5372
                    self.match(SystemVerilogParser.RP)


                pass
            elif token in [SystemVerilogParser.DOTSTAR]:
                self.state = 5375
                self.match(SystemVerilogParser.DOTSTAR)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_regionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KGENERATE(self):
            return self.getToken(SystemVerilogParser.KGENERATE, 0)

        def KENDGENERATE(self):
            return self.getToken(SystemVerilogParser.KENDGENERATE, 0)

        def generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Generate_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Generate_itemContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_generate_region

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_region" ):
                listener.enterGenerate_region(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_region" ):
                listener.exitGenerate_region(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_region" ):
                return visitor.visitGenerate_region(self)
            else:
                return visitor.visitChildren(self)




    def generate_region(self):

        localctx = SystemVerilogParser.Generate_regionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 656, self.RULE_generate_region)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5378
            self.match(SystemVerilogParser.KGENERATE)
            self.state = 5382
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 94)) & ~0x3f) == 0 and ((1 << (_la - 94)) & ((1 << (SystemVerilogParser.KALIAS - 94)) | (1 << (SystemVerilogParser.KALWAYS - 94)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 94)) | (1 << (SystemVerilogParser.KALWAYS_FF - 94)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 94)) | (1 << (SystemVerilogParser.KAND - 94)) | (1 << (SystemVerilogParser.KASSERT - 94)) | (1 << (SystemVerilogParser.KASSIGN - 94)) | (1 << (SystemVerilogParser.KASSUME - 94)) | (1 << (SystemVerilogParser.KAUTOMATIC - 94)) | (1 << (SystemVerilogParser.KBIND - 94)) | (1 << (SystemVerilogParser.KBIT - 94)) | (1 << (SystemVerilogParser.KBUF - 94)) | (1 << (SystemVerilogParser.KBUFIF0 - 94)) | (1 << (SystemVerilogParser.KBUFIF1 - 94)) | (1 << (SystemVerilogParser.KBYTE - 94)) | (1 << (SystemVerilogParser.KCASE - 94)) | (1 << (SystemVerilogParser.KCHANDLE - 94)) | (1 << (SystemVerilogParser.KCHECKER - 94)) | (1 << (SystemVerilogParser.KCLASS - 94)) | (1 << (SystemVerilogParser.KCLOCKING - 94)) | (1 << (SystemVerilogParser.KCMOS - 94)) | (1 << (SystemVerilogParser.KCONST - 94)) | (1 << (SystemVerilogParser.KCONSTRAINT - 94)) | (1 << (SystemVerilogParser.KCOVER - 94)) | (1 << (SystemVerilogParser.KCOVERGROUP - 94)) | (1 << (SystemVerilogParser.KDEFAULT - 94)) | (1 << (SystemVerilogParser.KDEFPARAM - 94)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KEXPORT - 159)) | (1 << (SystemVerilogParser.KEXTERN - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KINTERCONNECT - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOCALPARAM - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KNAND - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)) | (1 << (SystemVerilogParser.KNMOS - 159)))) != 0) or ((((_la - 223)) & ~0x3f) == 0 and ((1 << (_la - 223)) & ((1 << (SystemVerilogParser.KNOR - 223)) | (1 << (SystemVerilogParser.KNOT - 223)) | (1 << (SystemVerilogParser.KNOTIF0 - 223)) | (1 << (SystemVerilogParser.KNOTIF1 - 223)) | (1 << (SystemVerilogParser.KOR - 223)) | (1 << (SystemVerilogParser.KPARAMETER - 223)) | (1 << (SystemVerilogParser.KPMOS - 223)) | (1 << (SystemVerilogParser.KPROPERTY - 223)) | (1 << (SystemVerilogParser.KPULLDOWN - 223)) | (1 << (SystemVerilogParser.KPULLUP - 223)) | (1 << (SystemVerilogParser.KRAND - 223)) | (1 << (SystemVerilogParser.KRCMOS - 223)) | (1 << (SystemVerilogParser.KREAL - 223)) | (1 << (SystemVerilogParser.KREALTIME - 223)) | (1 << (SystemVerilogParser.KREG - 223)) | (1 << (SystemVerilogParser.KRESTRICT - 223)) | (1 << (SystemVerilogParser.KRNMOS - 223)) | (1 << (SystemVerilogParser.KRPMOS - 223)) | (1 << (SystemVerilogParser.KRTRAN - 223)) | (1 << (SystemVerilogParser.KRTRANIF0 - 223)) | (1 << (SystemVerilogParser.KRTRANIF1 - 223)) | (1 << (SystemVerilogParser.KSEQUENCE - 223)) | (1 << (SystemVerilogParser.KSHORTINT - 223)) | (1 << (SystemVerilogParser.KSHORTREAL - 223)) | (1 << (SystemVerilogParser.KSIGNED - 223)) | (1 << (SystemVerilogParser.KSTATIC - 223)))) != 0) or ((((_la - 287)) & ~0x3f) == 0 and ((1 << (_la - 287)) & ((1 << (SystemVerilogParser.KSTRING - 287)) | (1 << (SystemVerilogParser.KSTRUCT - 287)) | (1 << (SystemVerilogParser.KSUPPLY0 - 287)) | (1 << (SystemVerilogParser.KSUPPLY1 - 287)) | (1 << (SystemVerilogParser.KTASK - 287)) | (1 << (SystemVerilogParser.KTIME - 287)) | (1 << (SystemVerilogParser.KTRAN - 287)) | (1 << (SystemVerilogParser.KTRANIF0 - 287)) | (1 << (SystemVerilogParser.KTRANIF1 - 287)) | (1 << (SystemVerilogParser.KTRI - 287)) | (1 << (SystemVerilogParser.KTRI0 - 287)) | (1 << (SystemVerilogParser.KTRI1 - 287)) | (1 << (SystemVerilogParser.KTRIAND - 287)) | (1 << (SystemVerilogParser.KTRIOR - 287)) | (1 << (SystemVerilogParser.KTRIREG - 287)) | (1 << (SystemVerilogParser.KTYPE - 287)) | (1 << (SystemVerilogParser.KTYPEDEF - 287)) | (1 << (SystemVerilogParser.KUNION - 287)) | (1 << (SystemVerilogParser.KUNSIGNED - 287)) | (1 << (SystemVerilogParser.KUWIRE - 287)) | (1 << (SystemVerilogParser.KVAR - 287)) | (1 << (SystemVerilogParser.KVIRTUAL - 287)) | (1 << (SystemVerilogParser.KWAND - 287)) | (1 << (SystemVerilogParser.KWIRE - 287)) | (1 << (SystemVerilogParser.KWOR - 287)) | (1 << (SystemVerilogParser.KXNOR - 287)) | (1 << (SystemVerilogParser.KXOR - 287)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 5379
                self.generate_item()
                self.state = 5384
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5385
            self.match(SystemVerilogParser.KENDGENERATE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_generate_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KFOR(self):
            return self.getToken(SystemVerilogParser.KFOR, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def genvar_initialization(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_initializationContext,0)


        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def genvar_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_expressionContext,0)


        def genvar_iteration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_iterationContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def generate_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Generate_blockContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_loop_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_generate_construct" ):
                listener.enterLoop_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_generate_construct" ):
                listener.exitLoop_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_generate_construct" ):
                return visitor.visitLoop_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def loop_generate_construct(self):

        localctx = SystemVerilogParser.Loop_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 658, self.RULE_loop_generate_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5387
            self.match(SystemVerilogParser.KFOR)
            self.state = 5388
            self.match(SystemVerilogParser.LP)
            self.state = 5389
            self.genvar_initialization()
            self.state = 5390
            self.match(SystemVerilogParser.SEMI)
            self.state = 5391
            self.genvar_expression()
            self.state = 5392
            self.match(SystemVerilogParser.SEMI)
            self.state = 5393
            self.genvar_iteration()
            self.state = 5394
            self.match(SystemVerilogParser.RP)
            self.state = 5395
            self.generate_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_initializationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def KGENVAR(self):
            return self.getToken(SystemVerilogParser.KGENVAR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_genvar_initialization

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_initialization" ):
                listener.enterGenvar_initialization(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_initialization" ):
                listener.exitGenvar_initialization(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_initialization" ):
                return visitor.visitGenvar_initialization(self)
            else:
                return visitor.visitChildren(self)




    def genvar_initialization(self):

        localctx = SystemVerilogParser.Genvar_initializationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 660, self.RULE_genvar_initialization)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5398
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KGENVAR:
                self.state = 5397
                self.match(SystemVerilogParser.KGENVAR)


            self.state = 5400
            self.genvar_identifier()
            self.state = 5401
            self.match(SystemVerilogParser.EQ)
            self.state = 5402
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_iterationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def genvar_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_identifierContext,0)


        def assignment_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_operatorContext,0)


        def genvar_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_expressionContext,0)


        def inc_or_dec_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inc_or_dec_operatorContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_genvar_iteration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_iteration" ):
                listener.enterGenvar_iteration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_iteration" ):
                listener.exitGenvar_iteration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_iteration" ):
                return visitor.visitGenvar_iteration(self)
            else:
                return visitor.visitChildren(self)




    def genvar_iteration(self):

        localctx = SystemVerilogParser.Genvar_iterationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 662, self.RULE_genvar_iteration)
        try:
            self.state = 5414
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,654,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5404
                self.genvar_identifier()
                self.state = 5405
                self.assignment_operator()
                self.state = 5406
                self.genvar_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5408
                self.inc_or_dec_operator()
                self.state = 5409
                self.genvar_identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 5411
                self.genvar_identifier()
                self.state = 5412
                self.inc_or_dec_operator()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Conditional_generate_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def if_generate_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.If_generate_constructContext,0)


        def case_generate_construct(self):
            return self.getTypedRuleContext(SystemVerilogParser.Case_generate_constructContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_conditional_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConditional_generate_construct" ):
                listener.enterConditional_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConditional_generate_construct" ):
                listener.exitConditional_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConditional_generate_construct" ):
                return visitor.visitConditional_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def conditional_generate_construct(self):

        localctx = SystemVerilogParser.Conditional_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 664, self.RULE_conditional_generate_construct)
        try:
            self.state = 5418
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KIF]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5416
                self.if_generate_construct()
                pass
            elif token in [SystemVerilogParser.KCASE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5417
                self.case_generate_construct()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class If_generate_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KIF(self):
            return self.getToken(SystemVerilogParser.KIF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def generate_block(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Generate_blockContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Generate_blockContext,i)


        def KELSE(self):
            return self.getToken(SystemVerilogParser.KELSE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_if_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIf_generate_construct" ):
                listener.enterIf_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIf_generate_construct" ):
                listener.exitIf_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIf_generate_construct" ):
                return visitor.visitIf_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def if_generate_construct(self):

        localctx = SystemVerilogParser.If_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 666, self.RULE_if_generate_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5420
            self.match(SystemVerilogParser.KIF)
            self.state = 5421
            self.match(SystemVerilogParser.LP)
            self.state = 5422
            self.constant_expression(0)
            self.state = 5423
            self.match(SystemVerilogParser.RP)
            self.state = 5424
            self.generate_block()
            self.state = 5427
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,656,self._ctx)
            if la_ == 1:
                self.state = 5425
                self.match(SystemVerilogParser.KELSE)
                self.state = 5426
                self.generate_block()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_generate_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCASE(self):
            return self.getToken(SystemVerilogParser.KCASE, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def case_generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Case_generate_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Case_generate_itemContext,i)


        def KENDCASE(self):
            return self.getToken(SystemVerilogParser.KENDCASE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_generate_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_generate_construct" ):
                listener.enterCase_generate_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_generate_construct" ):
                listener.exitCase_generate_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_generate_construct" ):
                return visitor.visitCase_generate_construct(self)
            else:
                return visitor.visitChildren(self)




    def case_generate_construct(self):

        localctx = SystemVerilogParser.Case_generate_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 668, self.RULE_case_generate_construct)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5429
            self.match(SystemVerilogParser.KCASE)
            self.state = 5430
            self.match(SystemVerilogParser.LP)
            self.state = 5431
            self.constant_expression(0)
            self.state = 5432
            self.match(SystemVerilogParser.RP)
            self.state = 5433
            self.case_generate_item()
            self.state = 5437
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)))) != 0) or ((((_la - 134)) & ~0x3f) == 0 and ((1 << (_la - 134)) & ((1 << (SystemVerilogParser.KDEFAULT - 134)) | (1 << (SystemVerilogParser.KINT - 134)) | (1 << (SystemVerilogParser.KINTEGER - 134)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 5434
                self.case_generate_item()
                self.state = 5439
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5440
            self.match(SystemVerilogParser.KENDCASE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_generate_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def generate_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Generate_blockContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_generate_item" ):
                listener.enterCase_generate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_generate_item" ):
                listener.exitCase_generate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_generate_item" ):
                return visitor.visitCase_generate_item(self)
            else:
                return visitor.visitChildren(self)




    def case_generate_item(self):

        localctx = SystemVerilogParser.Case_generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 670, self.RULE_case_generate_item)
        self._la = 0 # Token type
        try:
            self.state = 5458
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.KBYTE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSTD, SystemVerilogParser.KSUPER, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5442
                self.constant_expression(0)
                self.state = 5447
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5443
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5444
                    self.constant_expression(0)
                    self.state = 5449
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5450
                self.match(SystemVerilogParser.COLON)
                self.state = 5451
                self.generate_block()
                pass
            elif token in [SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5453
                self.match(SystemVerilogParser.KDEFAULT)
                self.state = 5455
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 5454
                    self.match(SystemVerilogParser.COLON)


                self.state = 5457
                self.generate_block()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Generate_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Generate_itemContext,i)


        def KBEGIN(self):
            return self.getToken(SystemVerilogParser.KBEGIN, 0)

        def KEND(self):
            return self.getToken(SystemVerilogParser.KEND, 0)

        def generate_block_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Generate_block_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Generate_block_identifierContext,i)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLON)
            else:
                return self.getToken(SystemVerilogParser.COLON, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_generate_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block" ):
                listener.enterGenerate_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block" ):
                listener.exitGenerate_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block" ):
                return visitor.visitGenerate_block(self)
            else:
                return visitor.visitChildren(self)




    def generate_block(self):

        localctx = SystemVerilogParser.Generate_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 672, self.RULE_generate_block)
        self._la = 0 # Token type
        try:
            self.state = 5482
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,665,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5460
                self.generate_item()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5464
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 5461
                    self.generate_block_identifier()
                    self.state = 5462
                    self.match(SystemVerilogParser.COLON)


                self.state = 5466
                self.match(SystemVerilogParser.KBEGIN)
                self.state = 5469
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 5467
                    self.match(SystemVerilogParser.COLON)
                    self.state = 5468
                    self.generate_block_identifier()


                self.state = 5474
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.LB))) != 0) or ((((_la - 94)) & ~0x3f) == 0 and ((1 << (_la - 94)) & ((1 << (SystemVerilogParser.KALIAS - 94)) | (1 << (SystemVerilogParser.KALWAYS - 94)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 94)) | (1 << (SystemVerilogParser.KALWAYS_FF - 94)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 94)) | (1 << (SystemVerilogParser.KAND - 94)) | (1 << (SystemVerilogParser.KASSERT - 94)) | (1 << (SystemVerilogParser.KASSIGN - 94)) | (1 << (SystemVerilogParser.KASSUME - 94)) | (1 << (SystemVerilogParser.KAUTOMATIC - 94)) | (1 << (SystemVerilogParser.KBIND - 94)) | (1 << (SystemVerilogParser.KBIT - 94)) | (1 << (SystemVerilogParser.KBUF - 94)) | (1 << (SystemVerilogParser.KBUFIF0 - 94)) | (1 << (SystemVerilogParser.KBUFIF1 - 94)) | (1 << (SystemVerilogParser.KBYTE - 94)) | (1 << (SystemVerilogParser.KCASE - 94)) | (1 << (SystemVerilogParser.KCHANDLE - 94)) | (1 << (SystemVerilogParser.KCHECKER - 94)) | (1 << (SystemVerilogParser.KCLASS - 94)) | (1 << (SystemVerilogParser.KCLOCKING - 94)) | (1 << (SystemVerilogParser.KCMOS - 94)) | (1 << (SystemVerilogParser.KCONST - 94)) | (1 << (SystemVerilogParser.KCONSTRAINT - 94)) | (1 << (SystemVerilogParser.KCOVER - 94)) | (1 << (SystemVerilogParser.KCOVERGROUP - 94)) | (1 << (SystemVerilogParser.KDEFAULT - 94)) | (1 << (SystemVerilogParser.KDEFPARAM - 94)))) != 0) or ((((_la - 159)) & ~0x3f) == 0 and ((1 << (_la - 159)) & ((1 << (SystemVerilogParser.KENUM - 159)) | (1 << (SystemVerilogParser.KEVENT - 159)) | (1 << (SystemVerilogParser.KEXPORT - 159)) | (1 << (SystemVerilogParser.KEXTERN - 159)) | (1 << (SystemVerilogParser.KFINAL - 159)) | (1 << (SystemVerilogParser.KFOR - 159)) | (1 << (SystemVerilogParser.KFUNCTION - 159)) | (1 << (SystemVerilogParser.KGENERATE - 159)) | (1 << (SystemVerilogParser.KGENVAR - 159)) | (1 << (SystemVerilogParser.KGLOBAL - 159)) | (1 << (SystemVerilogParser.KIF - 159)) | (1 << (SystemVerilogParser.KIMPORT - 159)) | (1 << (SystemVerilogParser.KINITIAL - 159)) | (1 << (SystemVerilogParser.KINT - 159)) | (1 << (SystemVerilogParser.KINTEGER - 159)) | (1 << (SystemVerilogParser.KINTERCONNECT - 159)) | (1 << (SystemVerilogParser.KLET - 159)) | (1 << (SystemVerilogParser.KLOCALPARAM - 159)) | (1 << (SystemVerilogParser.KLOGIC - 159)) | (1 << (SystemVerilogParser.KLONGINT - 159)) | (1 << (SystemVerilogParser.KNAND - 159)) | (1 << (SystemVerilogParser.KNETTYPE - 159)) | (1 << (SystemVerilogParser.KNMOS - 159)))) != 0) or ((((_la - 223)) & ~0x3f) == 0 and ((1 << (_la - 223)) & ((1 << (SystemVerilogParser.KNOR - 223)) | (1 << (SystemVerilogParser.KNOT - 223)) | (1 << (SystemVerilogParser.KNOTIF0 - 223)) | (1 << (SystemVerilogParser.KNOTIF1 - 223)) | (1 << (SystemVerilogParser.KOR - 223)) | (1 << (SystemVerilogParser.KPARAMETER - 223)) | (1 << (SystemVerilogParser.KPMOS - 223)) | (1 << (SystemVerilogParser.KPROPERTY - 223)) | (1 << (SystemVerilogParser.KPULLDOWN - 223)) | (1 << (SystemVerilogParser.KPULLUP - 223)) | (1 << (SystemVerilogParser.KRAND - 223)) | (1 << (SystemVerilogParser.KRCMOS - 223)) | (1 << (SystemVerilogParser.KREAL - 223)) | (1 << (SystemVerilogParser.KREALTIME - 223)) | (1 << (SystemVerilogParser.KREG - 223)) | (1 << (SystemVerilogParser.KRESTRICT - 223)) | (1 << (SystemVerilogParser.KRNMOS - 223)) | (1 << (SystemVerilogParser.KRPMOS - 223)) | (1 << (SystemVerilogParser.KRTRAN - 223)) | (1 << (SystemVerilogParser.KRTRANIF0 - 223)) | (1 << (SystemVerilogParser.KRTRANIF1 - 223)) | (1 << (SystemVerilogParser.KSEQUENCE - 223)) | (1 << (SystemVerilogParser.KSHORTINT - 223)) | (1 << (SystemVerilogParser.KSHORTREAL - 223)) | (1 << (SystemVerilogParser.KSIGNED - 223)) | (1 << (SystemVerilogParser.KSTATIC - 223)))) != 0) or ((((_la - 287)) & ~0x3f) == 0 and ((1 << (_la - 287)) & ((1 << (SystemVerilogParser.KSTRING - 287)) | (1 << (SystemVerilogParser.KSTRUCT - 287)) | (1 << (SystemVerilogParser.KSUPPLY0 - 287)) | (1 << (SystemVerilogParser.KSUPPLY1 - 287)) | (1 << (SystemVerilogParser.KTASK - 287)) | (1 << (SystemVerilogParser.KTIME - 287)) | (1 << (SystemVerilogParser.KTRAN - 287)) | (1 << (SystemVerilogParser.KTRANIF0 - 287)) | (1 << (SystemVerilogParser.KTRANIF1 - 287)) | (1 << (SystemVerilogParser.KTRI - 287)) | (1 << (SystemVerilogParser.KTRI0 - 287)) | (1 << (SystemVerilogParser.KTRI1 - 287)) | (1 << (SystemVerilogParser.KTRIAND - 287)) | (1 << (SystemVerilogParser.KTRIOR - 287)) | (1 << (SystemVerilogParser.KTRIREG - 287)) | (1 << (SystemVerilogParser.KTYPE - 287)) | (1 << (SystemVerilogParser.KTYPEDEF - 287)) | (1 << (SystemVerilogParser.KUNION - 287)) | (1 << (SystemVerilogParser.KUNSIGNED - 287)) | (1 << (SystemVerilogParser.KUWIRE - 287)) | (1 << (SystemVerilogParser.KVAR - 287)) | (1 << (SystemVerilogParser.KVIRTUAL - 287)) | (1 << (SystemVerilogParser.KWAND - 287)) | (1 << (SystemVerilogParser.KWIRE - 287)) | (1 << (SystemVerilogParser.KWOR - 287)) | (1 << (SystemVerilogParser.KXNOR - 287)) | (1 << (SystemVerilogParser.KXOR - 287)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 5471
                    self.generate_item()
                    self.state = 5476
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5477
                self.match(SystemVerilogParser.KEND)
                self.state = 5480
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 5478
                    self.match(SystemVerilogParser.COLON)
                    self.state = 5479
                    self.generate_block_identifier()


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_or_generate_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_or_generate_itemContext,0)


        def interface_or_generate_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_or_generate_itemContext,0)


        def checker_or_generate_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_or_generate_itemContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_item" ):
                listener.enterGenerate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_item" ):
                listener.exitGenerate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_item" ):
                return visitor.visitGenerate_item(self)
            else:
                return visitor.visitChildren(self)




    def generate_item(self):

        localctx = SystemVerilogParser.Generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 674, self.RULE_generate_item)
        try:
            self.state = 5487
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,666,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5484
                self.module_or_generate_item()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5485
                self.interface_or_generate_item()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 5486
                self.checker_or_generate_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Continuous_assignContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KASSIGN(self):
            return self.getToken(SystemVerilogParser.KASSIGN, 0)

        def list_of_net_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_net_assignmentsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def list_of_variable_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_variable_assignmentsContext,0)


        def drive_strength(self):
            return self.getTypedRuleContext(SystemVerilogParser.Drive_strengthContext,0)


        def delay3(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay3Context,0)


        def delay_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_controlContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_continuous_assign

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterContinuous_assign" ):
                listener.enterContinuous_assign(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitContinuous_assign" ):
                listener.exitContinuous_assign(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitContinuous_assign" ):
                return visitor.visitContinuous_assign(self)
            else:
                return visitor.visitChildren(self)




    def continuous_assign(self):

        localctx = SystemVerilogParser.Continuous_assignContext(self, self._ctx, self.state)
        self.enterRule(localctx, 676, self.RULE_continuous_assign)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5489
            self.match(SystemVerilogParser.KASSIGN)
            self.state = 5505
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,670,self._ctx)
            if la_ == 1:
                self.state = 5491
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 5490
                    self.drive_strength()


                self.state = 5494
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 5493
                    self.delay3()


                self.state = 5496
                self.list_of_net_assignments()
                self.state = 5497
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.state = 5500
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 5499
                    self.delay_control()


                self.state = 5502
                self.list_of_variable_assignments()
                self.state = 5503
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_net_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Net_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Net_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_net_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_net_assignments" ):
                listener.enterList_of_net_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_net_assignments" ):
                listener.exitList_of_net_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_net_assignments" ):
                return visitor.visitList_of_net_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_net_assignments(self):

        localctx = SystemVerilogParser.List_of_net_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 678, self.RULE_list_of_net_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5507
            self.net_assignment()
            self.state = 5512
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 5508
                self.match(SystemVerilogParser.COMMA)
                self.state = 5509
                self.net_assignment()
                self.state = 5514
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_variable_assignmentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_variable_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_assignments" ):
                listener.enterList_of_variable_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_assignments" ):
                listener.exitList_of_variable_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_assignments" ):
                return visitor.visitList_of_variable_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_assignments(self):

        localctx = SystemVerilogParser.List_of_variable_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 680, self.RULE_list_of_variable_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5515
            self.variable_assignment()
            self.state = 5520
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 5516
                self.match(SystemVerilogParser.COMMA)
                self.state = 5517
                self.variable_assignment()
                self.state = 5522
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_aliasContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KALIAS(self):
            return self.getToken(SystemVerilogParser.KALIAS, 0)

        def net_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Net_lvalueContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Net_lvalueContext,i)


        def EQ(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.EQ)
            else:
                return self.getToken(SystemVerilogParser.EQ, i)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_alias

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_alias" ):
                listener.enterNet_alias(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_alias" ):
                listener.exitNet_alias(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_alias" ):
                return visitor.visitNet_alias(self)
            else:
                return visitor.visitChildren(self)




    def net_alias(self):

        localctx = SystemVerilogParser.Net_aliasContext(self, self._ctx, self.state)
        self.enterRule(localctx, 682, self.RULE_net_alias)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5523
            self.match(SystemVerilogParser.KALIAS)
            self.state = 5524
            self.net_lvalue()
            self.state = 5525
            self.match(SystemVerilogParser.EQ)
            self.state = 5526
            self.net_lvalue()
            self.state = 5531
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.EQ:
                self.state = 5527
                self.match(SystemVerilogParser.EQ)
                self.state = 5528
                self.net_lvalue()
                self.state = 5533
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5534
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_lvalueContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_assignment" ):
                listener.enterNet_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_assignment" ):
                listener.exitNet_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_assignment" ):
                return visitor.visitNet_assignment(self)
            else:
                return visitor.visitChildren(self)




    def net_assignment(self):

        localctx = SystemVerilogParser.Net_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 684, self.RULE_net_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5536
            self.net_lvalue()
            self.state = 5537
            self.match(SystemVerilogParser.EQ)
            self.state = 5538
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Initial_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINITIAL(self):
            return self.getToken(SystemVerilogParser.KINITIAL, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_initial_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInitial_construct" ):
                listener.enterInitial_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInitial_construct" ):
                listener.exitInitial_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInitial_construct" ):
                return visitor.visitInitial_construct(self)
            else:
                return visitor.visitChildren(self)




    def initial_construct(self):

        localctx = SystemVerilogParser.Initial_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 686, self.RULE_initial_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5540
            self.match(SystemVerilogParser.KINITIAL)
            self.state = 5541
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Always_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def always_keyword(self):
            return self.getTypedRuleContext(SystemVerilogParser.Always_keywordContext,0)


        def statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_always_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAlways_construct" ):
                listener.enterAlways_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAlways_construct" ):
                listener.exitAlways_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAlways_construct" ):
                return visitor.visitAlways_construct(self)
            else:
                return visitor.visitChildren(self)




    def always_construct(self):

        localctx = SystemVerilogParser.Always_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 688, self.RULE_always_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5543
            self.always_keyword()
            self.state = 5544
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Always_keywordContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KALWAYS(self):
            return self.getToken(SystemVerilogParser.KALWAYS, 0)

        def KALWAYS_COMB(self):
            return self.getToken(SystemVerilogParser.KALWAYS_COMB, 0)

        def KALWAYS_LATCH(self):
            return self.getToken(SystemVerilogParser.KALWAYS_LATCH, 0)

        def KALWAYS_FF(self):
            return self.getToken(SystemVerilogParser.KALWAYS_FF, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_always_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAlways_keyword" ):
                listener.enterAlways_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAlways_keyword" ):
                listener.exitAlways_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAlways_keyword" ):
                return visitor.visitAlways_keyword(self)
            else:
                return visitor.visitChildren(self)




    def always_keyword(self):

        localctx = SystemVerilogParser.Always_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 690, self.RULE_always_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5546
            _la = self._input.LA(1)
            if not(((((_la - 95)) & ~0x3f) == 0 and ((1 << (_la - 95)) & ((1 << (SystemVerilogParser.KALWAYS - 95)) | (1 << (SystemVerilogParser.KALWAYS_COMB - 95)) | (1 << (SystemVerilogParser.KALWAYS_FF - 95)) | (1 << (SystemVerilogParser.KALWAYS_LATCH - 95)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Final_constructContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KFINAL(self):
            return self.getToken(SystemVerilogParser.KFINAL, 0)

        def function_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_statementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_final_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFinal_construct" ):
                listener.enterFinal_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFinal_construct" ):
                listener.exitFinal_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFinal_construct" ):
                return visitor.visitFinal_construct(self)
            else:
                return visitor.visitChildren(self)




    def final_construct(self):

        localctx = SystemVerilogParser.Final_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 692, self.RULE_final_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5548
            self.match(SystemVerilogParser.KFINAL)
            self.state = 5549
            self.function_statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Blocking_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def delay_or_event_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_or_event_controlContext,0)


        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def nonrange_variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Nonrange_variable_lvalueContext,0)


        def dynamic_array_new(self):
            return self.getTypedRuleContext(SystemVerilogParser.Dynamic_array_newContext,0)


        def hierarchical_variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_variable_identifierContext,0)


        def select_(self):
            return self.getTypedRuleContext(SystemVerilogParser.Select_Context,0)


        def class_new(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_newContext,0)


        def implicit_class_handle(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_class_handleContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def operator_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Operator_assignmentContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_blocking_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlocking_assignment" ):
                listener.enterBlocking_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlocking_assignment" ):
                listener.exitBlocking_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlocking_assignment" ):
                return visitor.visitBlocking_assignment(self)
            else:
                return visitor.visitChildren(self)




    def blocking_assignment(self):

        localctx = SystemVerilogParser.Blocking_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 694, self.RULE_blocking_assignment)
        try:
            self.state = 5573
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,675,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5551
                self.variable_lvalue()
                self.state = 5552
                self.match(SystemVerilogParser.EQ)
                self.state = 5553
                self.delay_or_event_control()
                self.state = 5554
                self.expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5556
                self.nonrange_variable_lvalue()
                self.state = 5557
                self.match(SystemVerilogParser.EQ)
                self.state = 5558
                self.dynamic_array_new()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 5565
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,674,self._ctx)
                if la_ == 1:
                    self.state = 5560
                    self.implicit_class_handle()
                    self.state = 5561
                    self.match(SystemVerilogParser.DOT)

                elif la_ == 2:
                    self.state = 5563
                    self.class_scope()

                elif la_ == 3:
                    self.state = 5564
                    self.package_scope()


                self.state = 5567
                self.hierarchical_variable_identifier()
                self.state = 5568
                self.select_()
                self.state = 5569
                self.match(SystemVerilogParser.EQ)
                self.state = 5570
                self.class_new()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 5572
                self.operator_assignment()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Operator_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,0)


        def assignment_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_operatorContext,0)


        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_operator_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOperator_assignment" ):
                listener.enterOperator_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOperator_assignment" ):
                listener.exitOperator_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOperator_assignment" ):
                return visitor.visitOperator_assignment(self)
            else:
                return visitor.visitChildren(self)




    def operator_assignment(self):

        localctx = SystemVerilogParser.Operator_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 696, self.RULE_operator_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5575
            self.variable_lvalue()
            self.state = 5576
            self.assignment_operator()
            self.state = 5577
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assignment_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def PLUSEQ(self):
            return self.getToken(SystemVerilogParser.PLUSEQ, 0)

        def MINUSEQ(self):
            return self.getToken(SystemVerilogParser.MINUSEQ, 0)

        def SEQ(self):
            return self.getToken(SystemVerilogParser.SEQ, 0)

        def SLASHEQ(self):
            return self.getToken(SystemVerilogParser.SLASHEQ, 0)

        def PE(self):
            return self.getToken(SystemVerilogParser.PE, 0)

        def AE(self):
            return self.getToken(SystemVerilogParser.AE, 0)

        def BAREQ(self):
            return self.getToken(SystemVerilogParser.BAREQ, 0)

        def CARETEQ(self):
            return self.getToken(SystemVerilogParser.CARETEQ, 0)

        def LTLTEQ(self):
            return self.getToken(SystemVerilogParser.LTLTEQ, 0)

        def GTGTEQ(self):
            return self.getToken(SystemVerilogParser.GTGTEQ, 0)

        def LTLTLTEQ(self):
            return self.getToken(SystemVerilogParser.LTLTLTEQ, 0)

        def GTGTGTEQ(self):
            return self.getToken(SystemVerilogParser.GTGTGTEQ, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assignment_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssignment_operator" ):
                listener.enterAssignment_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssignment_operator" ):
                listener.exitAssignment_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssignment_operator" ):
                return visitor.visitAssignment_operator(self)
            else:
                return visitor.visitChildren(self)




    def assignment_operator(self):

        localctx = SystemVerilogParser.Assignment_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 698, self.RULE_assignment_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5579
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.PE) | (1 << SystemVerilogParser.AE) | (1 << SystemVerilogParser.SEQ) | (1 << SystemVerilogParser.SLASHEQ) | (1 << SystemVerilogParser.CARETEQ) | (1 << SystemVerilogParser.BAREQ))) != 0) or ((((_la - 70)) & ~0x3f) == 0 and ((1 << (_la - 70)) & ((1 << (SystemVerilogParser.PLUSEQ - 70)) | (1 << (SystemVerilogParser.LTLTLTEQ - 70)) | (1 << (SystemVerilogParser.LTLTEQ - 70)) | (1 << (SystemVerilogParser.EQ - 70)) | (1 << (SystemVerilogParser.MINUSEQ - 70)) | (1 << (SystemVerilogParser.GTGTEQ - 70)) | (1 << (SystemVerilogParser.GTGTGTEQ - 70)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Nonblocking_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,0)


        def LTEQ(self):
            return self.getToken(SystemVerilogParser.LTEQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def delay_or_event_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_or_event_controlContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_nonblocking_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNonblocking_assignment" ):
                listener.enterNonblocking_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNonblocking_assignment" ):
                listener.exitNonblocking_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNonblocking_assignment" ):
                return visitor.visitNonblocking_assignment(self)
            else:
                return visitor.visitChildren(self)




    def nonblocking_assignment(self):

        localctx = SystemVerilogParser.Nonblocking_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 700, self.RULE_nonblocking_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5581
            self.variable_lvalue()
            self.state = 5582
            self.match(SystemVerilogParser.LTEQ)
            self.state = 5584
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.P or _la==SystemVerilogParser.AT or _la==SystemVerilogParser.KREPEAT:
                self.state = 5583
                self.delay_or_event_control()


            self.state = 5586
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_continuous_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_assignmentContext,0)


        def KASSIGN(self):
            return self.getToken(SystemVerilogParser.KASSIGN, 0)

        def KFORCE(self):
            return self.getToken(SystemVerilogParser.KFORCE, 0)

        def variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,0)


        def KDEASSIGN(self):
            return self.getToken(SystemVerilogParser.KDEASSIGN, 0)

        def KRELEASE(self):
            return self.getToken(SystemVerilogParser.KRELEASE, 0)

        def net_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_assignmentContext,0)


        def net_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_lvalueContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_procedural_continuous_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_continuous_assignment" ):
                listener.enterProcedural_continuous_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_continuous_assignment" ):
                listener.exitProcedural_continuous_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_continuous_assignment" ):
                return visitor.visitProcedural_continuous_assignment(self)
            else:
                return visitor.visitChildren(self)




    def procedural_continuous_assignment(self):

        localctx = SystemVerilogParser.Procedural_continuous_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 702, self.RULE_procedural_continuous_assignment)
        self._la = 0 # Token type
        try:
            self.state = 5596
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,677,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5588
                _la = self._input.LA(1)
                if not(_la==SystemVerilogParser.KASSIGN or _la==SystemVerilogParser.KFORCE):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 5589
                self.variable_assignment()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5590
                _la = self._input.LA(1)
                if not(_la==SystemVerilogParser.KDEASSIGN or _la==SystemVerilogParser.KRELEASE):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 5591
                self.variable_lvalue()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 5592
                self.match(SystemVerilogParser.KFORCE)
                self.state = 5593
                self.net_assignment()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 5594
                self.match(SystemVerilogParser.KRELEASE)
                self.state = 5595
                self.net_lvalue()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_variable_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_assignment" ):
                listener.enterVariable_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_assignment" ):
                listener.exitVariable_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_assignment" ):
                return visitor.visitVariable_assignment(self)
            else:
                return visitor.visitChildren(self)




    def variable_assignment(self):

        localctx = SystemVerilogParser.Variable_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 704, self.RULE_variable_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5598
            self.variable_lvalue()
            self.state = 5599
            self.match(SystemVerilogParser.EQ)
            self.state = 5600
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Action_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def KELSE(self):
            return self.getToken(SystemVerilogParser.KELSE, 0)

        def statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_action_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAction_block" ):
                listener.enterAction_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAction_block" ):
                listener.exitAction_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAction_block" ):
                return visitor.visitAction_block(self)
            else:
                return visitor.visitChildren(self)




    def action_block(self):

        localctx = SystemVerilogParser.Action_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 706, self.RULE_action_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5606
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,679,self._ctx)
            if la_ == 1:
                self.state = 5603
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.P) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or ((((_la - 69)) & ~0x3f) == 0 and ((1 << (_la - 69)) & ((1 << (SystemVerilogParser.PLUSPLUS - 69)) | (1 << (SystemVerilogParser.ARROW - 69)) | (1 << (SystemVerilogParser.MINUSGTGT - 69)) | (1 << (SystemVerilogParser.KASSERT - 69)) | (1 << (SystemVerilogParser.KASSIGN - 69)) | (1 << (SystemVerilogParser.KASSUME - 69)) | (1 << (SystemVerilogParser.KBEGIN - 69)) | (1 << (SystemVerilogParser.KBREAK - 69)) | (1 << (SystemVerilogParser.KBYTE - 69)) | (1 << (SystemVerilogParser.KCASE - 69)) | (1 << (SystemVerilogParser.KCASEX - 69)) | (1 << (SystemVerilogParser.KCASEZ - 69)) | (1 << (SystemVerilogParser.KCONTINUE - 69)) | (1 << (SystemVerilogParser.KCOVER - 69)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (SystemVerilogParser.KDEASSIGN - 133)) | (1 << (SystemVerilogParser.KDISABLE - 133)) | (1 << (SystemVerilogParser.KDO - 133)) | (1 << (SystemVerilogParser.KEXPECT - 133)) | (1 << (SystemVerilogParser.KFOR - 133)) | (1 << (SystemVerilogParser.KFORCE - 133)) | (1 << (SystemVerilogParser.KFOREACH - 133)) | (1 << (SystemVerilogParser.KFOREVER - 133)) | (1 << (SystemVerilogParser.KFORK - 133)) | (1 << (SystemVerilogParser.KIF - 133)) | (1 << (SystemVerilogParser.KINT - 133)) | (1 << (SystemVerilogParser.KINTEGER - 133)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPRIORITY - 207)) | (1 << (SystemVerilogParser.KRANDCASE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KRANDSEQUENCE - 207)) | (1 << (SystemVerilogParser.KRELEASE - 207)) | (1 << (SystemVerilogParser.KREPEAT - 207)) | (1 << (SystemVerilogParser.KRESTRICT - 207)) | (1 << (SystemVerilogParser.KRETURN - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNIQUE0 - 276)) | (1 << (SystemVerilogParser.KVOID - 276)) | (1 << (SystemVerilogParser.KWAIT - 276)) | (1 << (SystemVerilogParser.KWAIT_ORDER - 276)) | (1 << (SystemVerilogParser.KWHILE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 5602
                    self.statement()


                self.state = 5605
                self.match(SystemVerilogParser.KELSE)


            self.state = 5608
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Seq_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KBEGIN(self):
            return self.getToken(SystemVerilogParser.KBEGIN, 0)

        def KEND(self):
            return self.getToken(SystemVerilogParser.KEND, 0)

        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLON)
            else:
                return self.getToken(SystemVerilogParser.COLON, i)

        def block_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Block_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Block_identifierContext,i)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Block_item_declarationContext,i)


        def statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Statement_or_nullContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_seq_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSeq_block" ):
                listener.enterSeq_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSeq_block" ):
                listener.exitSeq_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSeq_block" ):
                return visitor.visitSeq_block(self)
            else:
                return visitor.visitChildren(self)




    def seq_block(self):

        localctx = SystemVerilogParser.Seq_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 708, self.RULE_seq_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5610
            self.match(SystemVerilogParser.KBEGIN)
            self.state = 5613
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 5611
                self.match(SystemVerilogParser.COLON)
                self.state = 5612
                self.block_identifier()


            self.state = 5618
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,681,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 5615
                    self.block_item_declaration() 
                self.state = 5620
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,681,self._ctx)

            self.state = 5624
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.P) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or ((((_la - 69)) & ~0x3f) == 0 and ((1 << (_la - 69)) & ((1 << (SystemVerilogParser.PLUSPLUS - 69)) | (1 << (SystemVerilogParser.ARROW - 69)) | (1 << (SystemVerilogParser.MINUSGTGT - 69)) | (1 << (SystemVerilogParser.KASSERT - 69)) | (1 << (SystemVerilogParser.KASSIGN - 69)) | (1 << (SystemVerilogParser.KASSUME - 69)) | (1 << (SystemVerilogParser.KBEGIN - 69)) | (1 << (SystemVerilogParser.KBREAK - 69)) | (1 << (SystemVerilogParser.KBYTE - 69)) | (1 << (SystemVerilogParser.KCASE - 69)) | (1 << (SystemVerilogParser.KCASEX - 69)) | (1 << (SystemVerilogParser.KCASEZ - 69)) | (1 << (SystemVerilogParser.KCONTINUE - 69)) | (1 << (SystemVerilogParser.KCOVER - 69)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (SystemVerilogParser.KDEASSIGN - 133)) | (1 << (SystemVerilogParser.KDISABLE - 133)) | (1 << (SystemVerilogParser.KDO - 133)) | (1 << (SystemVerilogParser.KEXPECT - 133)) | (1 << (SystemVerilogParser.KFOR - 133)) | (1 << (SystemVerilogParser.KFORCE - 133)) | (1 << (SystemVerilogParser.KFOREACH - 133)) | (1 << (SystemVerilogParser.KFOREVER - 133)) | (1 << (SystemVerilogParser.KFORK - 133)) | (1 << (SystemVerilogParser.KIF - 133)) | (1 << (SystemVerilogParser.KINT - 133)) | (1 << (SystemVerilogParser.KINTEGER - 133)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPRIORITY - 207)) | (1 << (SystemVerilogParser.KRANDCASE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KRANDSEQUENCE - 207)) | (1 << (SystemVerilogParser.KRELEASE - 207)) | (1 << (SystemVerilogParser.KREPEAT - 207)) | (1 << (SystemVerilogParser.KRESTRICT - 207)) | (1 << (SystemVerilogParser.KRETURN - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNIQUE0 - 276)) | (1 << (SystemVerilogParser.KVOID - 276)) | (1 << (SystemVerilogParser.KWAIT - 276)) | (1 << (SystemVerilogParser.KWAIT_ORDER - 276)) | (1 << (SystemVerilogParser.KWHILE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 5621
                self.statement_or_null()
                self.state = 5626
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5627
            self.match(SystemVerilogParser.KEND)
            self.state = 5630
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 5628
                self.match(SystemVerilogParser.COLON)
                self.state = 5629
                self.block_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Par_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KFORK(self):
            return self.getToken(SystemVerilogParser.KFORK, 0)

        def join_keyword(self):
            return self.getTypedRuleContext(SystemVerilogParser.Join_keywordContext,0)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLON)
            else:
                return self.getToken(SystemVerilogParser.COLON, i)

        def block_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Block_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Block_identifierContext,i)


        def block_item_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Block_item_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Block_item_declarationContext,i)


        def statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Statement_or_nullContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_par_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPar_block" ):
                listener.enterPar_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPar_block" ):
                listener.exitPar_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPar_block" ):
                return visitor.visitPar_block(self)
            else:
                return visitor.visitChildren(self)




    def par_block(self):

        localctx = SystemVerilogParser.Par_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 710, self.RULE_par_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5632
            self.match(SystemVerilogParser.KFORK)
            self.state = 5635
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 5633
                self.match(SystemVerilogParser.COLON)
                self.state = 5634
                self.block_identifier()


            self.state = 5640
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,685,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 5637
                    self.block_item_declaration() 
                self.state = 5642
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,685,self._ctx)

            self.state = 5646
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.P) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or ((((_la - 69)) & ~0x3f) == 0 and ((1 << (_la - 69)) & ((1 << (SystemVerilogParser.PLUSPLUS - 69)) | (1 << (SystemVerilogParser.ARROW - 69)) | (1 << (SystemVerilogParser.MINUSGTGT - 69)) | (1 << (SystemVerilogParser.KASSERT - 69)) | (1 << (SystemVerilogParser.KASSIGN - 69)) | (1 << (SystemVerilogParser.KASSUME - 69)) | (1 << (SystemVerilogParser.KBEGIN - 69)) | (1 << (SystemVerilogParser.KBREAK - 69)) | (1 << (SystemVerilogParser.KBYTE - 69)) | (1 << (SystemVerilogParser.KCASE - 69)) | (1 << (SystemVerilogParser.KCASEX - 69)) | (1 << (SystemVerilogParser.KCASEZ - 69)) | (1 << (SystemVerilogParser.KCONTINUE - 69)) | (1 << (SystemVerilogParser.KCOVER - 69)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (SystemVerilogParser.KDEASSIGN - 133)) | (1 << (SystemVerilogParser.KDISABLE - 133)) | (1 << (SystemVerilogParser.KDO - 133)) | (1 << (SystemVerilogParser.KEXPECT - 133)) | (1 << (SystemVerilogParser.KFOR - 133)) | (1 << (SystemVerilogParser.KFORCE - 133)) | (1 << (SystemVerilogParser.KFOREACH - 133)) | (1 << (SystemVerilogParser.KFOREVER - 133)) | (1 << (SystemVerilogParser.KFORK - 133)) | (1 << (SystemVerilogParser.KIF - 133)) | (1 << (SystemVerilogParser.KINT - 133)) | (1 << (SystemVerilogParser.KINTEGER - 133)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPRIORITY - 207)) | (1 << (SystemVerilogParser.KRANDCASE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KRANDSEQUENCE - 207)) | (1 << (SystemVerilogParser.KRELEASE - 207)) | (1 << (SystemVerilogParser.KREPEAT - 207)) | (1 << (SystemVerilogParser.KRESTRICT - 207)) | (1 << (SystemVerilogParser.KRETURN - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNIQUE0 - 276)) | (1 << (SystemVerilogParser.KVOID - 276)) | (1 << (SystemVerilogParser.KWAIT - 276)) | (1 << (SystemVerilogParser.KWAIT_ORDER - 276)) | (1 << (SystemVerilogParser.KWHILE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 5643
                self.statement_or_null()
                self.state = 5648
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5649
            self.join_keyword()
            self.state = 5652
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 5650
                self.match(SystemVerilogParser.COLON)
                self.state = 5651
                self.block_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Join_keywordContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KJOIN(self):
            return self.getToken(SystemVerilogParser.KJOIN, 0)

        def KJOIN_ANY(self):
            return self.getToken(SystemVerilogParser.KJOIN_ANY, 0)

        def KJOIN_NONE(self):
            return self.getToken(SystemVerilogParser.KJOIN_NONE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_join_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterJoin_keyword" ):
                listener.enterJoin_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitJoin_keyword" ):
                listener.exitJoin_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitJoin_keyword" ):
                return visitor.visitJoin_keyword(self)
            else:
                return visitor.visitChildren(self)




    def join_keyword(self):

        localctx = SystemVerilogParser.Join_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 712, self.RULE_join_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5654
            _la = self._input.LA(1)
            if not(((((_la - 200)) & ~0x3f) == 0 and ((1 << (_la - 200)) & ((1 << (SystemVerilogParser.KJOIN - 200)) | (1 << (SystemVerilogParser.KJOIN_ANY - 200)) | (1 << (SystemVerilogParser.KJOIN_NONE - 200)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Statement_or_nullContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.StatementContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_statement_or_null

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement_or_null" ):
                listener.enterStatement_or_null(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement_or_null" ):
                listener.exitStatement_or_null(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement_or_null" ):
                return visitor.visitStatement_or_null(self)
            else:
                return visitor.visitChildren(self)




    def statement_or_null(self):

        localctx = SystemVerilogParser.Statement_or_nullContext(self, self._ctx, self.state)
        self.enterRule(localctx, 714, self.RULE_statement_or_null)
        self._la = 0 # Token type
        try:
            self.state = 5664
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,689,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5656
                self.statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5660
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 5657
                    self.attribute_instance()
                    self.state = 5662
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5663
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class StatementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_itemContext,0)


        def block_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Block_identifierContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement" ):
                listener.enterStatement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement" ):
                listener.exitStatement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement" ):
                return visitor.visitStatement(self)
            else:
                return visitor.visitChildren(self)




    def statement(self):

        localctx = SystemVerilogParser.StatementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 716, self.RULE_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5669
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,690,self._ctx)
            if la_ == 1:
                self.state = 5666
                self.block_identifier()
                self.state = 5667
                self.match(SystemVerilogParser.COLON)


            self.state = 5674
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LPS:
                self.state = 5671
                self.attribute_instance()
                self.state = 5676
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5677
            self.statement_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Statement_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def blocking_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Blocking_assignmentContext,0)


        def nonblocking_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Nonblocking_assignmentContext,0)


        def procedural_continuous_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Procedural_continuous_assignmentContext,0)


        def inc_or_dec_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inc_or_dec_expressionContext,0)


        def clocking_drive(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_driveContext,0)


        def case_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Case_statementContext,0)


        def conditional_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Conditional_statementContext,0)


        def subroutine_call_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Subroutine_call_statementContext,0)


        def disable_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Disable_statementContext,0)


        def event_trigger(self):
            return self.getTypedRuleContext(SystemVerilogParser.Event_triggerContext,0)


        def loop_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Loop_statementContext,0)


        def jump_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Jump_statementContext,0)


        def par_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Par_blockContext,0)


        def procedural_timing_control_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Procedural_timing_control_statementContext,0)


        def seq_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Seq_blockContext,0)


        def wait_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Wait_statementContext,0)


        def procedural_assertion_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Procedural_assertion_statementContext,0)


        def randsequence_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Randsequence_statementContext,0)


        def randcase_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Randcase_statementContext,0)


        def expect_property_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Expect_property_statementContext,0)


        def elaboration_system_task(self):
            return self.getTypedRuleContext(SystemVerilogParser.Elaboration_system_taskContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_statement_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement_item" ):
                listener.enterStatement_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement_item" ):
                listener.exitStatement_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement_item" ):
                return visitor.visitStatement_item(self)
            else:
                return visitor.visitChildren(self)




    def statement_item(self):

        localctx = SystemVerilogParser.Statement_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 718, self.RULE_statement_item)
        try:
            self.state = 5704
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,693,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5684
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,692,self._ctx)
                if la_ == 1:
                    self.state = 5679
                    self.blocking_assignment()
                    pass

                elif la_ == 2:
                    self.state = 5680
                    self.nonblocking_assignment()
                    pass

                elif la_ == 3:
                    self.state = 5681
                    self.procedural_continuous_assignment()
                    pass

                elif la_ == 4:
                    self.state = 5682
                    self.inc_or_dec_expression()
                    pass

                elif la_ == 5:
                    self.state = 5683
                    self.clocking_drive()
                    pass


                self.state = 5686
                self.match(SystemVerilogParser.SEMI)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5688
                self.case_statement()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 5689
                self.conditional_statement()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 5690
                self.subroutine_call_statement()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 5691
                self.disable_statement()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 5692
                self.event_trigger()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 5693
                self.loop_statement()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 5694
                self.jump_statement()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 5695
                self.par_block()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 5696
                self.procedural_timing_control_statement()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 5697
                self.seq_block()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 5698
                self.wait_statement()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 5699
                self.procedural_assertion_statement()
                pass

            elif la_ == 14:
                self.enterOuterAlt(localctx, 14)
                self.state = 5700
                self.randsequence_statement()
                pass

            elif la_ == 15:
                self.enterOuterAlt(localctx, 15)
                self.state = 5701
                self.randcase_statement()
                pass

            elif la_ == 16:
                self.enterOuterAlt(localctx, 16)
                self.state = 5702
                self.expect_property_statement()
                pass

            elif la_ == 17:
                self.enterOuterAlt(localctx, 17)
                self.state = 5703
                self.elaboration_system_task()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_function_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_statement" ):
                listener.enterFunction_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_statement" ):
                listener.exitFunction_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_statement" ):
                return visitor.visitFunction_statement(self)
            else:
                return visitor.visitChildren(self)




    def function_statement(self):

        localctx = SystemVerilogParser.Function_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 720, self.RULE_function_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5706
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_statement_or_nullContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_statementContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_function_statement_or_null

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_statement_or_null" ):
                listener.enterFunction_statement_or_null(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_statement_or_null" ):
                listener.exitFunction_statement_or_null(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_statement_or_null" ):
                return visitor.visitFunction_statement_or_null(self)
            else:
                return visitor.visitChildren(self)




    def function_statement_or_null(self):

        localctx = SystemVerilogParser.Function_statement_or_nullContext(self, self._ctx, self.state)
        self.enterRule(localctx, 722, self.RULE_function_statement_or_null)
        self._la = 0 # Token type
        try:
            self.state = 5716
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,695,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5708
                self.function_statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5712
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 5709
                    self.attribute_instance()
                    self.state = 5714
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5715
                self.match(SystemVerilogParser.SEMI)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_identifier_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_variable_identifier_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_identifier_list" ):
                listener.enterVariable_identifier_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_identifier_list" ):
                listener.exitVariable_identifier_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_identifier_list" ):
                return visitor.visitVariable_identifier_list(self)
            else:
                return visitor.visitChildren(self)




    def variable_identifier_list(self):

        localctx = SystemVerilogParser.Variable_identifier_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 724, self.RULE_variable_identifier_list)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5718
            self.variable_identifier()
            self.state = 5723
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 5719
                self.match(SystemVerilogParser.COMMA)
                self.state = 5720
                self.variable_identifier()
                self.state = 5725
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_timing_control_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def procedural_timing_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Procedural_timing_controlContext,0)


        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_procedural_timing_control_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_timing_control_statement" ):
                listener.enterProcedural_timing_control_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_timing_control_statement" ):
                listener.exitProcedural_timing_control_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_timing_control_statement" ):
                return visitor.visitProcedural_timing_control_statement(self)
            else:
                return visitor.visitChildren(self)




    def procedural_timing_control_statement(self):

        localctx = SystemVerilogParser.Procedural_timing_control_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 726, self.RULE_procedural_timing_control_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5726
            self.procedural_timing_control()
            self.state = 5727
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_or_event_controlContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_controlContext,0)


        def event_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Event_controlContext,0)


        def KREPEAT(self):
            return self.getToken(SystemVerilogParser.KREPEAT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_delay_or_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_or_event_control" ):
                listener.enterDelay_or_event_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_or_event_control" ):
                listener.exitDelay_or_event_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_or_event_control" ):
                return visitor.visitDelay_or_event_control(self)
            else:
                return visitor.visitChildren(self)




    def delay_or_event_control(self):

        localctx = SystemVerilogParser.Delay_or_event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 728, self.RULE_delay_or_event_control)
        self._la = 0 # Token type
        try:
            self.state = 5738
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.P]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5729
                self.delay_control()
                pass
            elif token in [SystemVerilogParser.AT, SystemVerilogParser.KREPEAT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5735
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KREPEAT:
                    self.state = 5730
                    self.match(SystemVerilogParser.KREPEAT)
                    self.state = 5731
                    self.match(SystemVerilogParser.LP)
                    self.state = 5732
                    self.expression(0)
                    self.state = 5733
                    self.match(SystemVerilogParser.RP)


                self.state = 5737
                self.event_control()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_controlContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def P(self):
            return self.getToken(SystemVerilogParser.P, 0)

        def delay_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_valueContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_delay_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_control" ):
                listener.enterDelay_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_control" ):
                listener.exitDelay_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_control" ):
                return visitor.visitDelay_control(self)
            else:
                return visitor.visitChildren(self)




    def delay_control(self):

        localctx = SystemVerilogParser.Delay_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 730, self.RULE_delay_control)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5740
            self.match(SystemVerilogParser.P)
            self.state = 5746
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.KONESTEP, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 5741
                self.delay_value()
                pass
            elif token in [SystemVerilogParser.LP]:
                self.state = 5742
                self.match(SystemVerilogParser.LP)
                self.state = 5743
                self.mintypmax_expression()
                self.state = 5744
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_controlContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def AT(self):
            return self.getToken(SystemVerilogParser.AT, 0)

        def hierarchical_event_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_event_identifierContext,0)


        def ps_or_hierarchical_sequence_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_or_hierarchical_sequence_identifierContext,0)


        def STAR(self):
            return self.getToken(SystemVerilogParser.STAR, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def event_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Event_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_control" ):
                listener.enterEvent_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_control" ):
                listener.exitEvent_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_control" ):
                return visitor.visitEvent_control(self)
            else:
                return visitor.visitChildren(self)




    def event_control(self):

        localctx = SystemVerilogParser.Event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 732, self.RULE_event_control)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5748
            self.match(SystemVerilogParser.AT)
            self.state = 5758
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,701,self._ctx)
            if la_ == 1:
                self.state = 5749
                self.hierarchical_event_identifier()
                pass

            elif la_ == 2:
                self.state = 5750
                self.ps_or_hierarchical_sequence_identifier()
                pass

            elif la_ == 3:
                self.state = 5751
                self.match(SystemVerilogParser.STAR)
                pass

            elif la_ == 4:
                self.state = 5752
                self.match(SystemVerilogParser.LP)
                self.state = 5755
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KEDGE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNEGEDGE, SystemVerilogParser.KNULL, SystemVerilogParser.KPOSEDGE, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                    self.state = 5753
                    self.event_expression(0)
                    pass
                elif token in [SystemVerilogParser.STAR]:
                    self.state = 5754
                    self.match(SystemVerilogParser.STAR)
                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 5757
                self.match(SystemVerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def sequence_instance(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_instanceContext,0)


        def KIFF(self):
            return self.getToken(SystemVerilogParser.KIFF, 0)

        def edge_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Edge_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def event_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Event_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Event_expressionContext,i)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def KOR(self):
            return self.getToken(SystemVerilogParser.KOR, 0)

        def COMMA(self):
            return self.getToken(SystemVerilogParser.COMMA, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_event_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_expression" ):
                listener.enterEvent_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_expression" ):
                listener.exitEvent_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_expression" ):
                return visitor.visitEvent_expression(self)
            else:
                return visitor.visitChildren(self)



    def event_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = SystemVerilogParser.Event_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 734
        self.enterRecursionRule(localctx, 734, self.RULE_event_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5776
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,705,self._ctx)
            if la_ == 1:
                self.state = 5766
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,703,self._ctx)
                if la_ == 1:
                    self.state = 5762
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.KEDGE or _la==SystemVerilogParser.KNEGEDGE or _la==SystemVerilogParser.KPOSEDGE:
                        self.state = 5761
                        self.edge_identifier()


                    self.state = 5764
                    self.expression(0)
                    pass

                elif la_ == 2:
                    self.state = 5765
                    self.sequence_instance()
                    pass


                self.state = 5770
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,704,self._ctx)
                if la_ == 1:
                    self.state = 5768
                    self.match(SystemVerilogParser.KIFF)
                    self.state = 5769
                    self.expression(0)


                pass

            elif la_ == 2:
                self.state = 5772
                self.match(SystemVerilogParser.LP)
                self.state = 5773
                self.event_expression(0)
                self.state = 5774
                self.match(SystemVerilogParser.RP)
                pass


            self._ctx.stop = self._input.LT(-1)
            self.state = 5783
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,706,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    localctx = SystemVerilogParser.Event_expressionContext(self, _parentctx, _parentState)
                    self.pushNewRecursionContext(localctx, _startState, self.RULE_event_expression)
                    self.state = 5778
                    if not self.precpred(self._ctx, 2):
                        from antlr4.error.Errors import FailedPredicateException
                        raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                    self.state = 5779
                    _la = self._input.LA(1)
                    if not(_la==SystemVerilogParser.COMMA or _la==SystemVerilogParser.KOR):
                        self._errHandler.recoverInline(self)
                    else:
                        self._errHandler.reportMatch(self)
                        self.consume()
                    self.state = 5780
                    self.event_expression(3) 
                self.state = 5785
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,706,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Procedural_timing_controlContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_controlContext,0)


        def event_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Event_controlContext,0)


        def cycle_delay(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cycle_delayContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_procedural_timing_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_timing_control" ):
                listener.enterProcedural_timing_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_timing_control" ):
                listener.exitProcedural_timing_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_timing_control" ):
                return visitor.visitProcedural_timing_control(self)
            else:
                return visitor.visitChildren(self)




    def procedural_timing_control(self):

        localctx = SystemVerilogParser.Procedural_timing_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 736, self.RULE_procedural_timing_control)
        try:
            self.state = 5789
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.P]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5786
                self.delay_control()
                pass
            elif token in [SystemVerilogParser.AT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5787
                self.event_control()
                pass
            elif token in [SystemVerilogParser.PP]:
                self.enterOuterAlt(localctx, 3)
                self.state = 5788
                self.cycle_delay()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Jump_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KRETURN(self):
            return self.getToken(SystemVerilogParser.KRETURN, 0)

        def KBREAK(self):
            return self.getToken(SystemVerilogParser.KBREAK, 0)

        def KCONTINUE(self):
            return self.getToken(SystemVerilogParser.KCONTINUE, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_jump_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterJump_statement" ):
                listener.enterJump_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitJump_statement" ):
                listener.exitJump_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitJump_statement" ):
                return visitor.visitJump_statement(self)
            else:
                return visitor.visitChildren(self)




    def jump_statement(self):

        localctx = SystemVerilogParser.Jump_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 738, self.RULE_jump_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5797
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KRETURN]:
                self.state = 5791
                self.match(SystemVerilogParser.KRETURN)
                self.state = 5793
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 5792
                    self.expression(0)


                pass
            elif token in [SystemVerilogParser.KBREAK]:
                self.state = 5795
                self.match(SystemVerilogParser.KBREAK)
                pass
            elif token in [SystemVerilogParser.KCONTINUE]:
                self.state = 5796
                self.match(SystemVerilogParser.KCONTINUE)
                pass
            else:
                raise NoViableAltException(self)

            self.state = 5799
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Wait_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KWAIT(self):
            return self.getToken(SystemVerilogParser.KWAIT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def KFORK(self):
            return self.getToken(SystemVerilogParser.KFORK, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KWAIT_ORDER(self):
            return self.getToken(SystemVerilogParser.KWAIT_ORDER, 0)

        def hierarchical_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Hierarchical_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,i)


        def action_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Action_blockContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_wait_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWait_statement" ):
                listener.enterWait_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWait_statement" ):
                listener.exitWait_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWait_statement" ):
                return visitor.visitWait_statement(self)
            else:
                return visitor.visitChildren(self)




    def wait_statement(self):

        localctx = SystemVerilogParser.Wait_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 740, self.RULE_wait_statement)
        self._la = 0 # Token type
        try:
            self.state = 5824
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KWAIT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5801
                self.match(SystemVerilogParser.KWAIT)
                self.state = 5809
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.LP]:
                    self.state = 5802
                    self.match(SystemVerilogParser.LP)
                    self.state = 5803
                    self.expression(0)
                    self.state = 5804
                    self.match(SystemVerilogParser.RP)
                    self.state = 5805
                    self.statement_or_null()
                    pass
                elif token in [SystemVerilogParser.KFORK]:
                    self.state = 5807
                    self.match(SystemVerilogParser.KFORK)
                    self.state = 5808
                    self.match(SystemVerilogParser.SEMI)
                    pass
                else:
                    raise NoViableAltException(self)

                pass
            elif token in [SystemVerilogParser.KWAIT_ORDER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5811
                self.match(SystemVerilogParser.KWAIT_ORDER)
                self.state = 5812
                self.match(SystemVerilogParser.LP)
                self.state = 5813
                self.hierarchical_identifier()
                self.state = 5818
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5814
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5815
                    self.hierarchical_identifier()
                    self.state = 5820
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5821
                self.match(SystemVerilogParser.RP)
                self.state = 5822
                self.action_block()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_triggerContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_event_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_event_identifierContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def ARROW(self):
            return self.getToken(SystemVerilogParser.ARROW, 0)

        def MINUSGTGT(self):
            return self.getToken(SystemVerilogParser.MINUSGTGT, 0)

        def delay_or_event_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_or_event_controlContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_event_trigger

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_trigger" ):
                listener.enterEvent_trigger(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_trigger" ):
                listener.exitEvent_trigger(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_trigger" ):
                return visitor.visitEvent_trigger(self)
            else:
                return visitor.visitChildren(self)




    def event_trigger(self):

        localctx = SystemVerilogParser.Event_triggerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 742, self.RULE_event_trigger)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5831
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.ARROW]:
                self.state = 5826
                self.match(SystemVerilogParser.ARROW)
                pass
            elif token in [SystemVerilogParser.MINUSGTGT]:
                self.state = 5827
                self.match(SystemVerilogParser.MINUSGTGT)
                self.state = 5829
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P or _la==SystemVerilogParser.AT or _la==SystemVerilogParser.KREPEAT:
                    self.state = 5828
                    self.delay_or_event_control()


                pass
            else:
                raise NoViableAltException(self)

            self.state = 5833
            self.hierarchical_event_identifier()
            self.state = 5834
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Disable_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KDISABLE(self):
            return self.getToken(SystemVerilogParser.KDISABLE, 0)

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def hierarchical_task_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_task_identifierContext,0)


        def hierarchical_block_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_block_identifierContext,0)


        def KFORK(self):
            return self.getToken(SystemVerilogParser.KFORK, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_disable_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDisable_statement" ):
                listener.enterDisable_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDisable_statement" ):
                listener.exitDisable_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDisable_statement" ):
                return visitor.visitDisable_statement(self)
            else:
                return visitor.visitChildren(self)




    def disable_statement(self):

        localctx = SystemVerilogParser.Disable_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 744, self.RULE_disable_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5836
            self.match(SystemVerilogParser.KDISABLE)
            self.state = 5840
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,715,self._ctx)
            if la_ == 1:
                self.state = 5837
                self.hierarchical_task_identifier()
                pass

            elif la_ == 2:
                self.state = 5838
                self.hierarchical_block_identifier()
                pass

            elif la_ == 3:
                self.state = 5839
                self.match(SystemVerilogParser.KFORK)
                pass


            self.state = 5842
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Conditional_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KIF(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.KIF)
            else:
                return self.getToken(SystemVerilogParser.KIF, i)

        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def cond_predicate(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Cond_predicateContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Cond_predicateContext,i)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Statement_or_nullContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,i)


        def unique_priority(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unique_priorityContext,0)


        def KELSE(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.KELSE)
            else:
                return self.getToken(SystemVerilogParser.KELSE, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_conditional_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConditional_statement" ):
                listener.enterConditional_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConditional_statement" ):
                listener.exitConditional_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConditional_statement" ):
                return visitor.visitConditional_statement(self)
            else:
                return visitor.visitChildren(self)




    def conditional_statement(self):

        localctx = SystemVerilogParser.Conditional_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 746, self.RULE_conditional_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5845
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KPRIORITY or _la==SystemVerilogParser.KUNIQUE or _la==SystemVerilogParser.KUNIQUE0:
                self.state = 5844
                self.unique_priority()


            self.state = 5847
            self.match(SystemVerilogParser.KIF)
            self.state = 5848
            self.match(SystemVerilogParser.LP)
            self.state = 5849
            self.cond_predicate()
            self.state = 5850
            self.match(SystemVerilogParser.RP)
            self.state = 5851
            self.statement_or_null()
            self.state = 5861
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,717,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 5852
                    self.match(SystemVerilogParser.KELSE)
                    self.state = 5853
                    self.match(SystemVerilogParser.KIF)
                    self.state = 5854
                    self.match(SystemVerilogParser.LP)
                    self.state = 5855
                    self.cond_predicate()
                    self.state = 5856
                    self.match(SystemVerilogParser.RP)
                    self.state = 5857
                    self.statement_or_null() 
                self.state = 5863
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,717,self._ctx)

            self.state = 5866
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,718,self._ctx)
            if la_ == 1:
                self.state = 5864
                self.match(SystemVerilogParser.KELSE)
                self.state = 5865
                self.statement_or_null()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unique_priorityContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KUNIQUE(self):
            return self.getToken(SystemVerilogParser.KUNIQUE, 0)

        def KUNIQUE0(self):
            return self.getToken(SystemVerilogParser.KUNIQUE0, 0)

        def KPRIORITY(self):
            return self.getToken(SystemVerilogParser.KPRIORITY, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_unique_priority

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnique_priority" ):
                listener.enterUnique_priority(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnique_priority" ):
                listener.exitUnique_priority(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnique_priority" ):
                return visitor.visitUnique_priority(self)
            else:
                return visitor.visitChildren(self)




    def unique_priority(self):

        localctx = SystemVerilogParser.Unique_priorityContext(self, self._ctx, self.state)
        self.enterRule(localctx, 748, self.RULE_unique_priority)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5868
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KPRIORITY or _la==SystemVerilogParser.KUNIQUE or _la==SystemVerilogParser.KUNIQUE0):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cond_predicateContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression_or_cond_pattern(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Expression_or_cond_patternContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Expression_or_cond_patternContext,i)


        def ANDANDAND(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.ANDANDAND)
            else:
                return self.getToken(SystemVerilogParser.ANDANDAND, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cond_predicate

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCond_predicate" ):
                listener.enterCond_predicate(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCond_predicate" ):
                listener.exitCond_predicate(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCond_predicate" ):
                return visitor.visitCond_predicate(self)
            else:
                return visitor.visitChildren(self)




    def cond_predicate(self):

        localctx = SystemVerilogParser.Cond_predicateContext(self, self._ctx, self.state)
        self.enterRule(localctx, 750, self.RULE_cond_predicate)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5870
            self.expression_or_cond_pattern()
            self.state = 5875
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.ANDANDAND:
                self.state = 5871
                self.match(SystemVerilogParser.ANDANDAND)
                self.state = 5872
                self.expression_or_cond_pattern()
                self.state = 5877
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Expression_or_cond_patternContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def cond_pattern(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cond_patternContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_expression_or_cond_pattern

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExpression_or_cond_pattern" ):
                listener.enterExpression_or_cond_pattern(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExpression_or_cond_pattern" ):
                listener.exitExpression_or_cond_pattern(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExpression_or_cond_pattern" ):
                return visitor.visitExpression_or_cond_pattern(self)
            else:
                return visitor.visitChildren(self)




    def expression_or_cond_pattern(self):

        localctx = SystemVerilogParser.Expression_or_cond_patternContext(self, self._ctx, self.state)
        self.enterRule(localctx, 752, self.RULE_expression_or_cond_pattern)
        try:
            self.state = 5880
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,720,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5878
                self.expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5879
                self.cond_pattern()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cond_patternContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def KMATCHES(self):
            return self.getToken(SystemVerilogParser.KMATCHES, 0)

        def pattern(self):
            return self.getTypedRuleContext(SystemVerilogParser.PatternContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cond_pattern

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCond_pattern" ):
                listener.enterCond_pattern(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCond_pattern" ):
                listener.exitCond_pattern(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCond_pattern" ):
                return visitor.visitCond_pattern(self)
            else:
                return visitor.visitChildren(self)




    def cond_pattern(self):

        localctx = SystemVerilogParser.Cond_patternContext(self, self._ctx, self.state)
        self.enterRule(localctx, 754, self.RULE_cond_pattern)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5882
            self.expression(0)
            self.state = 5883
            self.match(SystemVerilogParser.KMATCHES)
            self.state = 5884
            self.pattern()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def case_keyword(self):
            return self.getTypedRuleContext(SystemVerilogParser.Case_keywordContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def case_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Case_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def KENDCASE(self):
            return self.getToken(SystemVerilogParser.KENDCASE, 0)

        def case_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Case_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Case_itemContext,i)


        def KMATCHES(self):
            return self.getToken(SystemVerilogParser.KMATCHES, 0)

        def case_pattern_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Case_pattern_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Case_pattern_itemContext,i)


        def unique_priority(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unique_priorityContext,0)


        def KCASE(self):
            return self.getToken(SystemVerilogParser.KCASE, 0)

        def KINSIDE(self):
            return self.getToken(SystemVerilogParser.KINSIDE, 0)

        def case_inside_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Case_inside_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Case_inside_itemContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_statement" ):
                listener.enterCase_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_statement" ):
                listener.exitCase_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_statement" ):
                return visitor.visitCase_statement(self)
            else:
                return visitor.visitChildren(self)




    def case_statement(self):

        localctx = SystemVerilogParser.Case_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 756, self.RULE_case_statement)
        self._la = 0 # Token type
        try:
            self.state = 5929
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,727,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 5887
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KPRIORITY or _la==SystemVerilogParser.KUNIQUE or _la==SystemVerilogParser.KUNIQUE0:
                    self.state = 5886
                    self.unique_priority()


                self.state = 5889
                self.case_keyword()
                self.state = 5890
                self.match(SystemVerilogParser.LP)
                self.state = 5891
                self.case_expression()
                self.state = 5892
                self.match(SystemVerilogParser.RP)
                self.state = 5908
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KDEFAULT, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                    self.state = 5893
                    self.case_item()
                    self.state = 5897
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 134)) & ~0x3f) == 0 and ((1 << (_la - 134)) & ((1 << (SystemVerilogParser.KDEFAULT - 134)) | (1 << (SystemVerilogParser.KINT - 134)) | (1 << (SystemVerilogParser.KINTEGER - 134)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                        self.state = 5894
                        self.case_item()
                        self.state = 5899
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)

                    pass
                elif token in [SystemVerilogParser.KMATCHES]:
                    self.state = 5900
                    self.match(SystemVerilogParser.KMATCHES)
                    self.state = 5901
                    self.case_pattern_item()
                    self.state = 5905
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.DOT) | (1 << SystemVerilogParser.DOTSTAR) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)))) != 0) or ((((_la - 134)) & ~0x3f) == 0 and ((1 << (_la - 134)) & ((1 << (SystemVerilogParser.KDEFAULT - 134)) | (1 << (SystemVerilogParser.KINT - 134)) | (1 << (SystemVerilogParser.KINTEGER - 134)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                        self.state = 5902
                        self.case_pattern_item()
                        self.state = 5907
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)

                    pass
                else:
                    raise NoViableAltException(self)

                self.state = 5910
                self.match(SystemVerilogParser.KENDCASE)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 5913
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KPRIORITY or _la==SystemVerilogParser.KUNIQUE or _la==SystemVerilogParser.KUNIQUE0:
                    self.state = 5912
                    self.unique_priority()


                self.state = 5915
                self.match(SystemVerilogParser.KCASE)
                self.state = 5916
                self.match(SystemVerilogParser.LP)
                self.state = 5917
                self.case_expression()
                self.state = 5918
                self.match(SystemVerilogParser.RP)
                self.state = 5919
                self.match(SystemVerilogParser.KINSIDE)
                self.state = 5920
                self.case_inside_item()
                self.state = 5924
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LB) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 134)) & ~0x3f) == 0 and ((1 << (_la - 134)) & ((1 << (SystemVerilogParser.KDEFAULT - 134)) | (1 << (SystemVerilogParser.KINT - 134)) | (1 << (SystemVerilogParser.KINTEGER - 134)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 5921
                    self.case_inside_item()
                    self.state = 5926
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5927
                self.match(SystemVerilogParser.KENDCASE)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_keywordContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCASE(self):
            return self.getToken(SystemVerilogParser.KCASE, 0)

        def KCASEZ(self):
            return self.getToken(SystemVerilogParser.KCASEZ, 0)

        def KCASEX(self):
            return self.getToken(SystemVerilogParser.KCASEX, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_keyword" ):
                listener.enterCase_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_keyword" ):
                listener.exitCase_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_keyword" ):
                return visitor.visitCase_keyword(self)
            else:
                return visitor.visitChildren(self)




    def case_keyword(self):

        localctx = SystemVerilogParser.Case_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 758, self.RULE_case_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5931
            _la = self._input.LA(1)
            if not(((((_la - 115)) & ~0x3f) == 0 and ((1 << (_la - 115)) & ((1 << (SystemVerilogParser.KCASE - 115)) | (1 << (SystemVerilogParser.KCASEX - 115)) | (1 << (SystemVerilogParser.KCASEZ - 115)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_expression" ):
                listener.enterCase_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_expression" ):
                listener.exitCase_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_expression" ):
                return visitor.visitCase_expression(self)
            else:
                return visitor.visitChildren(self)




    def case_expression(self):

        localctx = SystemVerilogParser.Case_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 760, self.RULE_case_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5933
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def case_item_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Case_item_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Case_item_expressionContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_item" ):
                listener.enterCase_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_item" ):
                listener.exitCase_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_item" ):
                return visitor.visitCase_item(self)
            else:
                return visitor.visitChildren(self)




    def case_item(self):

        localctx = SystemVerilogParser.Case_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 762, self.RULE_case_item)
        self._la = 0 # Token type
        try:
            self.state = 5951
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5935
                self.case_item_expression()
                self.state = 5940
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 5936
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5937
                    self.case_item_expression()
                    self.state = 5942
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 5943
                self.match(SystemVerilogParser.COLON)
                self.state = 5944
                self.statement_or_null()
                pass
            elif token in [SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5946
                self.match(SystemVerilogParser.KDEFAULT)
                self.state = 5948
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 5947
                    self.match(SystemVerilogParser.COLON)


                self.state = 5950
                self.statement_or_null()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_pattern_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pattern(self):
            return self.getTypedRuleContext(SystemVerilogParser.PatternContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def ANDANDAND(self):
            return self.getToken(SystemVerilogParser.ANDANDAND, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_pattern_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_pattern_item" ):
                listener.enterCase_pattern_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_pattern_item" ):
                listener.exitCase_pattern_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_pattern_item" ):
                return visitor.visitCase_pattern_item(self)
            else:
                return visitor.visitChildren(self)




    def case_pattern_item(self):

        localctx = SystemVerilogParser.Case_pattern_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 764, self.RULE_case_pattern_item)
        self._la = 0 # Token type
        try:
            self.state = 5966
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.DOT, SystemVerilogParser.DOTSTAR, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.KBYTE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSTD, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5953
                self.pattern()
                self.state = 5956
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.ANDANDAND:
                    self.state = 5954
                    self.match(SystemVerilogParser.ANDANDAND)
                    self.state = 5955
                    self.expression(0)


                self.state = 5958
                self.match(SystemVerilogParser.COLON)
                self.state = 5959
                self.statement_or_null()
                pass
            elif token in [SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5961
                self.match(SystemVerilogParser.KDEFAULT)
                self.state = 5963
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 5962
                    self.match(SystemVerilogParser.COLON)


                self.state = 5965
                self.statement_or_null()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_inside_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def open_range_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Open_range_listContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_inside_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_inside_item" ):
                listener.enterCase_inside_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_inside_item" ):
                listener.exitCase_inside_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_inside_item" ):
                return visitor.visitCase_inside_item(self)
            else:
                return visitor.visitChildren(self)




    def case_inside_item(self):

        localctx = SystemVerilogParser.Case_inside_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 766, self.RULE_case_inside_item)
        self._la = 0 # Token type
        try:
            self.state = 5977
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.LB, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 5968
                self.open_range_list()
                self.state = 5969
                self.match(SystemVerilogParser.COLON)
                self.state = 5970
                self.statement_or_null()
                pass
            elif token in [SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 5972
                self.match(SystemVerilogParser.KDEFAULT)
                self.state = 5974
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 5973
                    self.match(SystemVerilogParser.COLON)


                self.state = 5976
                self.statement_or_null()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_item_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_case_item_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_item_expression" ):
                listener.enterCase_item_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_item_expression" ):
                listener.exitCase_item_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_item_expression" ):
                return visitor.visitCase_item_expression(self)
            else:
                return visitor.visitChildren(self)




    def case_item_expression(self):

        localctx = SystemVerilogParser.Case_item_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 768, self.RULE_case_item_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5979
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Randcase_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KRANDCASE(self):
            return self.getToken(SystemVerilogParser.KRANDCASE, 0)

        def randcase_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Randcase_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Randcase_itemContext,i)


        def KENDCASE(self):
            return self.getToken(SystemVerilogParser.KENDCASE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_randcase_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRandcase_statement" ):
                listener.enterRandcase_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRandcase_statement" ):
                listener.exitRandcase_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRandcase_statement" ):
                return visitor.visitRandcase_statement(self)
            else:
                return visitor.visitChildren(self)




    def randcase_statement(self):

        localctx = SystemVerilogParser.Randcase_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 770, self.RULE_randcase_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5981
            self.match(SystemVerilogParser.KRANDCASE)
            self.state = 5982
            self.randcase_item()
            self.state = 5986
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 5983
                self.randcase_item()
                self.state = 5988
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 5989
            self.match(SystemVerilogParser.KENDCASE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Randcase_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_randcase_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRandcase_item" ):
                listener.enterRandcase_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRandcase_item" ):
                listener.exitRandcase_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRandcase_item" ):
                return visitor.visitRandcase_item(self)
            else:
                return visitor.visitChildren(self)




    def randcase_item(self):

        localctx = SystemVerilogParser.Randcase_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 772, self.RULE_randcase_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5991
            self.expression(0)
            self.state = 5992
            self.match(SystemVerilogParser.COLON)
            self.state = 5993
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Open_range_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def open_value_range(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Open_value_rangeContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Open_value_rangeContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_open_range_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOpen_range_list" ):
                listener.enterOpen_range_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOpen_range_list" ):
                listener.exitOpen_range_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOpen_range_list" ):
                return visitor.visitOpen_range_list(self)
            else:
                return visitor.visitChildren(self)




    def open_range_list(self):

        localctx = SystemVerilogParser.Open_range_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 774, self.RULE_open_range_list)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 5995
            self.open_value_range()
            self.state = 6000
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,737,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 5996
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 5997
                    self.open_value_range() 
                self.state = 6002
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,737,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Open_value_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def value_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Value_rangeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_open_value_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOpen_value_range" ):
                listener.enterOpen_value_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOpen_value_range" ):
                listener.exitOpen_value_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOpen_value_range" ):
                return visitor.visitOpen_value_range(self)
            else:
                return visitor.visitChildren(self)




    def open_value_range(self):

        localctx = SystemVerilogParser.Open_value_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 776, self.RULE_open_value_range)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6003
            self.value_range()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class PatternContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,0)


        def DOTSTAR(self):
            return self.getToken(SystemVerilogParser.DOTSTAR, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def KTAGGED(self):
            return self.getToken(SystemVerilogParser.KTAGGED, 0)

        def member_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Member_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Member_identifierContext,i)


        def pattern(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.PatternContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.PatternContext,i)


        def QUOTE(self):
            return self.getToken(SystemVerilogParser.QUOTE, 0)

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLON)
            else:
                return self.getToken(SystemVerilogParser.COLON, i)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pattern

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPattern" ):
                listener.enterPattern(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPattern" ):
                listener.exitPattern(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPattern" ):
                return visitor.visitPattern(self)
            else:
                return visitor.visitChildren(self)




    def pattern(self):

        localctx = SystemVerilogParser.PatternContext(self, self._ctx, self.state)
        self.enterRule(localctx, 778, self.RULE_pattern)
        self._la = 0 # Token type
        try:
            self.state = 6041
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,742,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6005
                self.match(SystemVerilogParser.DOT)
                self.state = 6006
                self.variable_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6007
                self.match(SystemVerilogParser.DOTSTAR)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 6008
                self.constant_expression(0)
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 6009
                self.match(SystemVerilogParser.KTAGGED)
                self.state = 6010
                self.member_identifier()
                self.state = 6012
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.DOT) | (1 << SystemVerilogParser.DOTSTAR) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 6011
                    self.pattern()


                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 6014
                self.match(SystemVerilogParser.QUOTE)
                self.state = 6015
                self.match(SystemVerilogParser.LC)
                self.state = 6037
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,741,self._ctx)
                if la_ == 1:
                    self.state = 6016
                    self.pattern()
                    self.state = 6021
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    while _la==SystemVerilogParser.COMMA:
                        self.state = 6017
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 6018
                        self.pattern()
                        self.state = 6023
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)

                    pass

                elif la_ == 2:
                    self.state = 6024
                    self.member_identifier()
                    self.state = 6025
                    self.match(SystemVerilogParser.COLON)
                    self.state = 6026
                    self.pattern()
                    self.state = 6034
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    while _la==SystemVerilogParser.COMMA:
                        self.state = 6027
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 6028
                        self.member_identifier()
                        self.state = 6029
                        self.match(SystemVerilogParser.COLON)
                        self.state = 6030
                        self.pattern()
                        self.state = 6036
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)

                    pass


                self.state = 6039
                self.match(SystemVerilogParser.RC)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assignment_patternContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def QUOTE(self):
            return self.getToken(SystemVerilogParser.QUOTE, 0)

        def LC(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LC)
            else:
                return self.getToken(SystemVerilogParser.LC, i)

        def RC(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RC)
            else:
                return self.getToken(SystemVerilogParser.RC, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def structure_pattern_key(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Structure_pattern_keyContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Structure_pattern_keyContext,i)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLON)
            else:
                return self.getToken(SystemVerilogParser.COLON, i)

        def array_pattern_key(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Array_pattern_keyContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Array_pattern_keyContext,i)


        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assignment_pattern

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssignment_pattern" ):
                listener.enterAssignment_pattern(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssignment_pattern" ):
                listener.exitAssignment_pattern(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssignment_pattern" ):
                return visitor.visitAssignment_pattern(self)
            else:
                return visitor.visitChildren(self)




    def assignment_pattern(self):

        localctx = SystemVerilogParser.Assignment_patternContext(self, self._ctx, self.state)
        self.enterRule(localctx, 780, self.RULE_assignment_pattern)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6043
            self.match(SystemVerilogParser.QUOTE)
            self.state = 6044
            self.match(SystemVerilogParser.LC)
            self.state = 6091
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,747,self._ctx)
            if la_ == 1:
                self.state = 6045
                self.expression(0)
                self.state = 6050
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 6046
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6047
                    self.expression(0)
                    self.state = 6052
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 2:
                self.state = 6053
                self.structure_pattern_key()
                self.state = 6054
                self.match(SystemVerilogParser.COLON)
                self.state = 6055
                self.expression(0)
                self.state = 6063
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 6056
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6057
                    self.structure_pattern_key()
                    self.state = 6058
                    self.match(SystemVerilogParser.COLON)
                    self.state = 6059
                    self.expression(0)
                    self.state = 6065
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 3:
                self.state = 6066
                self.array_pattern_key()
                self.state = 6067
                self.match(SystemVerilogParser.COLON)
                self.state = 6068
                self.expression(0)
                self.state = 6076
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 6069
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6070
                    self.array_pattern_key()
                    self.state = 6071
                    self.match(SystemVerilogParser.COLON)
                    self.state = 6072
                    self.expression(0)
                    self.state = 6078
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass

            elif la_ == 4:
                self.state = 6079
                self.constant_expression(0)
                self.state = 6080
                self.match(SystemVerilogParser.LC)
                self.state = 6081
                self.expression(0)
                self.state = 6086
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 6082
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6083
                    self.expression(0)
                    self.state = 6088
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 6089
                self.match(SystemVerilogParser.RC)
                pass


            self.state = 6093
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Structure_pattern_keyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def member_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Member_identifierContext,0)


        def assignment_pattern_key(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_keyContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_structure_pattern_key

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStructure_pattern_key" ):
                listener.enterStructure_pattern_key(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStructure_pattern_key" ):
                listener.exitStructure_pattern_key(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStructure_pattern_key" ):
                return visitor.visitStructure_pattern_key(self)
            else:
                return visitor.visitChildren(self)




    def structure_pattern_key(self):

        localctx = SystemVerilogParser.Structure_pattern_keyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 782, self.RULE_structure_pattern_key)
        try:
            self.state = 6097
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,748,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6095
                self.member_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6096
                self.assignment_pattern_key()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Array_pattern_keyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def assignment_pattern_key(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_keyContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_array_pattern_key

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArray_pattern_key" ):
                listener.enterArray_pattern_key(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArray_pattern_key" ):
                listener.exitArray_pattern_key(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArray_pattern_key" ):
                return visitor.visitArray_pattern_key(self)
            else:
                return visitor.visitChildren(self)




    def array_pattern_key(self):

        localctx = SystemVerilogParser.Array_pattern_keyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 784, self.RULE_array_pattern_key)
        try:
            self.state = 6101
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,749,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6099
                self.constant_expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6100
                self.assignment_pattern_key()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assignment_pattern_keyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def simple_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_typeContext,0)


        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assignment_pattern_key

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssignment_pattern_key" ):
                listener.enterAssignment_pattern_key(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssignment_pattern_key" ):
                listener.exitAssignment_pattern_key(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssignment_pattern_key" ):
                return visitor.visitAssignment_pattern_key(self)
            else:
                return visitor.visitChildren(self)




    def assignment_pattern_key(self):

        localctx = SystemVerilogParser.Assignment_pattern_keyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 786, self.RULE_assignment_pattern_key)
        try:
            self.state = 6105
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DUNIT, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KTIME, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6103
                self.simple_type()
                pass
            elif token in [SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6104
                self.match(SystemVerilogParser.KDEFAULT)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assignment_pattern_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def assignment_pattern(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_patternContext,0)


        def assignment_pattern_expression_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_expression_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assignment_pattern_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssignment_pattern_expression" ):
                listener.enterAssignment_pattern_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssignment_pattern_expression" ):
                listener.exitAssignment_pattern_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssignment_pattern_expression" ):
                return visitor.visitAssignment_pattern_expression(self)
            else:
                return visitor.visitChildren(self)




    def assignment_pattern_expression(self):

        localctx = SystemVerilogParser.Assignment_pattern_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 788, self.RULE_assignment_pattern_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6108
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.DUNIT or _la==SystemVerilogParser.KBYTE or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 6107
                self.assignment_pattern_expression_type()


            self.state = 6110
            self.assignment_pattern()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assignment_pattern_expression_typeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ps_type_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_type_identifierContext,0)


        def ps_parameter_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_parameter_identifierContext,0)


        def integer_atom_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Integer_atom_typeContext,0)


        def type_reference(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_referenceContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assignment_pattern_expression_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssignment_pattern_expression_type" ):
                listener.enterAssignment_pattern_expression_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssignment_pattern_expression_type" ):
                listener.exitAssignment_pattern_expression_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssignment_pattern_expression_type" ):
                return visitor.visitAssignment_pattern_expression_type(self)
            else:
                return visitor.visitChildren(self)




    def assignment_pattern_expression_type(self):

        localctx = SystemVerilogParser.Assignment_pattern_expression_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 790, self.RULE_assignment_pattern_expression_type)
        try:
            self.state = 6116
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,752,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6112
                self.ps_type_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6113
                self.ps_parameter_identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 6114
                self.integer_atom_type()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 6115
                self.type_reference()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_assignment_pattern_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def assignment_pattern_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_assignment_pattern_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_assignment_pattern_expression" ):
                listener.enterConstant_assignment_pattern_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_assignment_pattern_expression" ):
                listener.exitConstant_assignment_pattern_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_assignment_pattern_expression" ):
                return visitor.visitConstant_assignment_pattern_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_assignment_pattern_expression(self):

        localctx = SystemVerilogParser.Constant_assignment_pattern_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 792, self.RULE_constant_assignment_pattern_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6118
            self.assignment_pattern_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assignment_pattern_net_lvalueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def QUOTE(self):
            return self.getToken(SystemVerilogParser.QUOTE, 0)

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def net_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Net_lvalueContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Net_lvalueContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assignment_pattern_net_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssignment_pattern_net_lvalue" ):
                listener.enterAssignment_pattern_net_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssignment_pattern_net_lvalue" ):
                listener.exitAssignment_pattern_net_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssignment_pattern_net_lvalue" ):
                return visitor.visitAssignment_pattern_net_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def assignment_pattern_net_lvalue(self):

        localctx = SystemVerilogParser.Assignment_pattern_net_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 794, self.RULE_assignment_pattern_net_lvalue)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6120
            self.match(SystemVerilogParser.QUOTE)
            self.state = 6121
            self.match(SystemVerilogParser.LC)
            self.state = 6122
            self.net_lvalue()
            self.state = 6127
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6123
                self.match(SystemVerilogParser.COMMA)
                self.state = 6124
                self.net_lvalue()
                self.state = 6129
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6130
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assignment_pattern_variable_lvalueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def QUOTE(self):
            return self.getToken(SystemVerilogParser.QUOTE, 0)

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def variable_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_lvalueContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assignment_pattern_variable_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssignment_pattern_variable_lvalue" ):
                listener.enterAssignment_pattern_variable_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssignment_pattern_variable_lvalue" ):
                listener.exitAssignment_pattern_variable_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssignment_pattern_variable_lvalue" ):
                return visitor.visitAssignment_pattern_variable_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def assignment_pattern_variable_lvalue(self):

        localctx = SystemVerilogParser.Assignment_pattern_variable_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 796, self.RULE_assignment_pattern_variable_lvalue)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6132
            self.match(SystemVerilogParser.QUOTE)
            self.state = 6133
            self.match(SystemVerilogParser.LC)
            self.state = 6134
            self.variable_lvalue()
            self.state = 6139
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6135
                self.match(SystemVerilogParser.COMMA)
                self.state = 6136
                self.variable_lvalue()
                self.state = 6141
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6142
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KFOREVER(self):
            return self.getToken(SystemVerilogParser.KFOREVER, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def KREPEAT(self):
            return self.getToken(SystemVerilogParser.KREPEAT, 0)

        def KWHILE(self):
            return self.getToken(SystemVerilogParser.KWHILE, 0)

        def KFOR(self):
            return self.getToken(SystemVerilogParser.KFOR, 0)

        def SEMI(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.SEMI)
            else:
                return self.getToken(SystemVerilogParser.SEMI, i)

        def for_initialization(self):
            return self.getTypedRuleContext(SystemVerilogParser.For_initializationContext,0)


        def for_step(self):
            return self.getTypedRuleContext(SystemVerilogParser.For_stepContext,0)


        def KDO(self):
            return self.getToken(SystemVerilogParser.KDO, 0)

        def KFOREACH(self):
            return self.getToken(SystemVerilogParser.KFOREACH, 0)

        def ps_or_hierarchical_array_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_or_hierarchical_array_identifierContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def loop_variables(self):
            return self.getTypedRuleContext(SystemVerilogParser.Loop_variablesContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.StatementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_statement" ):
                listener.enterLoop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_statement" ):
                listener.exitLoop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_statement" ):
                return visitor.visitLoop_statement(self)
            else:
                return visitor.visitChildren(self)




    def loop_statement(self):

        localctx = SystemVerilogParser.Loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 798, self.RULE_loop_statement)
        self._la = 0 # Token type
        try:
            self.state = 6184
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KFOREVER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6144
                self.match(SystemVerilogParser.KFOREVER)
                self.state = 6145
                self.statement_or_null()
                pass
            elif token in [SystemVerilogParser.KREPEAT, SystemVerilogParser.KWHILE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6146
                _la = self._input.LA(1)
                if not(_la==SystemVerilogParser.KREPEAT or _la==SystemVerilogParser.KWHILE):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 6147
                self.match(SystemVerilogParser.LP)
                self.state = 6148
                self.expression(0)
                self.state = 6149
                self.match(SystemVerilogParser.RP)
                self.state = 6150
                self.statement_or_null()
                pass
            elif token in [SystemVerilogParser.KFOR]:
                self.enterOuterAlt(localctx, 3)
                self.state = 6152
                self.match(SystemVerilogParser.KFOR)
                self.state = 6153
                self.match(SystemVerilogParser.LP)
                self.state = 6155
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSTRUCT - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNION - 276)) | (1 << (SystemVerilogParser.KVAR - 276)) | (1 << (SystemVerilogParser.KVIRTUAL - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 6154
                    self.for_initialization()


                self.state = 6157
                self.match(SystemVerilogParser.SEMI)
                self.state = 6159
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 6158
                    self.expression(0)


                self.state = 6161
                self.match(SystemVerilogParser.SEMI)
                self.state = 6163
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or _la==SystemVerilogParser.PLUSPLUS or _la==SystemVerilogParser.KBYTE or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 6162
                    self.for_step()


                self.state = 6165
                self.match(SystemVerilogParser.RP)
                self.state = 6166
                self.statement_or_null()
                pass
            elif token in [SystemVerilogParser.KDO]:
                self.enterOuterAlt(localctx, 4)
                self.state = 6167
                self.match(SystemVerilogParser.KDO)
                self.state = 6168
                self.statement_or_null()
                self.state = 6169
                self.match(SystemVerilogParser.KWHILE)
                self.state = 6170
                self.match(SystemVerilogParser.LP)
                self.state = 6171
                self.expression(0)
                self.state = 6172
                self.match(SystemVerilogParser.RP)
                self.state = 6173
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KFOREACH]:
                self.enterOuterAlt(localctx, 5)
                self.state = 6175
                self.match(SystemVerilogParser.KFOREACH)
                self.state = 6176
                self.match(SystemVerilogParser.LP)
                self.state = 6177
                self.ps_or_hierarchical_array_identifier()
                self.state = 6178
                self.match(SystemVerilogParser.LB)
                self.state = 6179
                self.loop_variables()
                self.state = 6180
                self.match(SystemVerilogParser.RB)
                self.state = 6181
                self.match(SystemVerilogParser.RP)
                self.state = 6182
                self.statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class For_initializationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_variable_assignments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_variable_assignmentsContext,0)


        def for_variable_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.For_variable_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.For_variable_declarationContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_for_initialization

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFor_initialization" ):
                listener.enterFor_initialization(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFor_initialization" ):
                listener.exitFor_initialization(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFor_initialization" ):
                return visitor.visitFor_initialization(self)
            else:
                return visitor.visitChildren(self)




    def for_initialization(self):

        localctx = SystemVerilogParser.For_initializationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 800, self.RULE_for_initialization)
        self._la = 0 # Token type
        try:
            self.state = 6195
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,760,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6186
                self.list_of_variable_assignments()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6187
                self.for_variable_declaration()
                self.state = 6192
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 6188
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6189
                    self.for_variable_declaration()
                    self.state = 6194
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class For_variable_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def variable_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,i)


        def EQ(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.EQ)
            else:
                return self.getToken(SystemVerilogParser.EQ, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def KVAR(self):
            return self.getToken(SystemVerilogParser.KVAR, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_for_variable_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFor_variable_declaration" ):
                listener.enterFor_variable_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFor_variable_declaration" ):
                listener.exitFor_variable_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFor_variable_declaration" ):
                return visitor.visitFor_variable_declaration(self)
            else:
                return visitor.visitChildren(self)




    def for_variable_declaration(self):

        localctx = SystemVerilogParser.For_variable_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 802, self.RULE_for_variable_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6198
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KVAR:
                self.state = 6197
                self.match(SystemVerilogParser.KVAR)


            self.state = 6200
            self.data_type()
            self.state = 6201
            self.variable_identifier()
            self.state = 6202
            self.match(SystemVerilogParser.EQ)
            self.state = 6203
            self.expression(0)
            self.state = 6211
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,762,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 6204
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6205
                    self.variable_identifier()
                    self.state = 6206
                    self.match(SystemVerilogParser.EQ)
                    self.state = 6207
                    self.expression(0) 
                self.state = 6213
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,762,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class For_stepContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def for_step_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.For_step_assignmentContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.For_step_assignmentContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_for_step

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFor_step" ):
                listener.enterFor_step(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFor_step" ):
                listener.exitFor_step(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFor_step" ):
                return visitor.visitFor_step(self)
            else:
                return visitor.visitChildren(self)




    def for_step(self):

        localctx = SystemVerilogParser.For_stepContext(self, self._ctx, self.state)
        self.enterRule(localctx, 804, self.RULE_for_step)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6214
            self.for_step_assignment()
            self.state = 6219
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6215
                self.match(SystemVerilogParser.COMMA)
                self.state = 6216
                self.for_step_assignment()
                self.state = 6221
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class For_step_assignmentContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def operator_assignment(self):
            return self.getTypedRuleContext(SystemVerilogParser.Operator_assignmentContext,0)


        def inc_or_dec_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inc_or_dec_expressionContext,0)


        def function_subroutine_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_subroutine_callContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_for_step_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFor_step_assignment" ):
                listener.enterFor_step_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFor_step_assignment" ):
                listener.exitFor_step_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFor_step_assignment" ):
                return visitor.visitFor_step_assignment(self)
            else:
                return visitor.visitChildren(self)




    def for_step_assignment(self):

        localctx = SystemVerilogParser.For_step_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 806, self.RULE_for_step_assignment)
        try:
            self.state = 6225
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,764,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6222
                self.operator_assignment()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6223
                self.inc_or_dec_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 6224
                self.function_subroutine_call()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_variablesContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def index_variable_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Index_variable_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Index_variable_identifierContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_loop_variables

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_variables" ):
                listener.enterLoop_variables(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_variables" ):
                listener.exitLoop_variables(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_variables" ):
                return visitor.visitLoop_variables(self)
            else:
                return visitor.visitChildren(self)




    def loop_variables(self):

        localctx = SystemVerilogParser.Loop_variablesContext(self, self._ctx, self.state)
        self.enterRule(localctx, 808, self.RULE_loop_variables)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6228
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 6227
                self.index_variable_identifier()


            self.state = 6236
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6230
                self.match(SystemVerilogParser.COMMA)
                self.state = 6232
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 6231
                    self.index_variable_identifier()


                self.state = 6238
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Subroutine_call_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def subroutine_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Subroutine_callContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KVOID(self):
            return self.getToken(SystemVerilogParser.KVOID, 0)

        def QUOTE(self):
            return self.getToken(SystemVerilogParser.QUOTE, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def function_subroutine_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_subroutine_callContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_subroutine_call_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSubroutine_call_statement" ):
                listener.enterSubroutine_call_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSubroutine_call_statement" ):
                listener.exitSubroutine_call_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSubroutine_call_statement" ):
                return visitor.visitSubroutine_call_statement(self)
            else:
                return visitor.visitChildren(self)




    def subroutine_call_statement(self):

        localctx = SystemVerilogParser.Subroutine_call_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 810, self.RULE_subroutine_call_statement)
        try:
            self.state = 6249
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.LC, SystemVerilogParser.KBYTE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSTD, SystemVerilogParser.KSUPER, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6239
                self.subroutine_call()
                self.state = 6240
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KVOID]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6242
                self.match(SystemVerilogParser.KVOID)
                self.state = 6243
                self.match(SystemVerilogParser.QUOTE)
                self.state = 6244
                self.match(SystemVerilogParser.LP)
                self.state = 6245
                self.function_subroutine_call()
                self.state = 6246
                self.match(SystemVerilogParser.RP)
                self.state = 6247
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assertion_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def concurrent_assertion_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Concurrent_assertion_itemContext,0)


        def deferred_immediate_assertion_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Deferred_immediate_assertion_itemContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_assertion_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssertion_item" ):
                listener.enterAssertion_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssertion_item" ):
                listener.exitAssertion_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssertion_item" ):
                return visitor.visitAssertion_item(self)
            else:
                return visitor.visitChildren(self)




    def assertion_item(self):

        localctx = SystemVerilogParser.Assertion_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 812, self.RULE_assertion_item)
        try:
            self.state = 6253
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,769,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6251
                self.concurrent_assertion_item()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6252
                self.deferred_immediate_assertion_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Deferred_immediate_assertion_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def deferred_immediate_assertion_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Deferred_immediate_assertion_statementContext,0)


        def block_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Block_identifierContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_deferred_immediate_assertion_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDeferred_immediate_assertion_item" ):
                listener.enterDeferred_immediate_assertion_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDeferred_immediate_assertion_item" ):
                listener.exitDeferred_immediate_assertion_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDeferred_immediate_assertion_item" ):
                return visitor.visitDeferred_immediate_assertion_item(self)
            else:
                return visitor.visitChildren(self)




    def deferred_immediate_assertion_item(self):

        localctx = SystemVerilogParser.Deferred_immediate_assertion_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 814, self.RULE_deferred_immediate_assertion_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6258
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 6255
                self.block_identifier()
                self.state = 6256
                self.match(SystemVerilogParser.COLON)


            self.state = 6260
            self.deferred_immediate_assertion_statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_assertion_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def concurrent_assertion_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Concurrent_assertion_statementContext,0)


        def immediate_assertion_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Immediate_assertion_statementContext,0)


        def checker_instantiation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_instantiationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_procedural_assertion_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_assertion_statement" ):
                listener.enterProcedural_assertion_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_assertion_statement" ):
                listener.exitProcedural_assertion_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_assertion_statement" ):
                return visitor.visitProcedural_assertion_statement(self)
            else:
                return visitor.visitChildren(self)




    def procedural_assertion_statement(self):

        localctx = SystemVerilogParser.Procedural_assertion_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 816, self.RULE_procedural_assertion_statement)
        try:
            self.state = 6265
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,771,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6262
                self.concurrent_assertion_statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6263
                self.immediate_assertion_statement()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 6264
                self.checker_instantiation()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Immediate_assertion_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def simple_immediate_assertion_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_immediate_assertion_statementContext,0)


        def deferred_immediate_assertion_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Deferred_immediate_assertion_statementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_immediate_assertion_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterImmediate_assertion_statement" ):
                listener.enterImmediate_assertion_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitImmediate_assertion_statement" ):
                listener.exitImmediate_assertion_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitImmediate_assertion_statement" ):
                return visitor.visitImmediate_assertion_statement(self)
            else:
                return visitor.visitChildren(self)




    def immediate_assertion_statement(self):

        localctx = SystemVerilogParser.Immediate_assertion_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 818, self.RULE_immediate_assertion_statement)
        try:
            self.state = 6269
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,772,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6267
                self.simple_immediate_assertion_statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6268
                self.deferred_immediate_assertion_statement()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Simple_immediate_assertion_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def simple_immediate_assert_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_immediate_assert_statementContext,0)


        def simple_immediate_assume_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_immediate_assume_statementContext,0)


        def simple_immediate_cover_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_immediate_cover_statementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_simple_immediate_assertion_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_immediate_assertion_statement" ):
                listener.enterSimple_immediate_assertion_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_immediate_assertion_statement" ):
                listener.exitSimple_immediate_assertion_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_immediate_assertion_statement" ):
                return visitor.visitSimple_immediate_assertion_statement(self)
            else:
                return visitor.visitChildren(self)




    def simple_immediate_assertion_statement(self):

        localctx = SystemVerilogParser.Simple_immediate_assertion_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 820, self.RULE_simple_immediate_assertion_statement)
        try:
            self.state = 6274
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KASSERT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6271
                self.simple_immediate_assert_statement()
                pass
            elif token in [SystemVerilogParser.KASSUME]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6272
                self.simple_immediate_assume_statement()
                pass
            elif token in [SystemVerilogParser.KCOVER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 6273
                self.simple_immediate_cover_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Simple_immediate_assert_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KASSERT(self):
            return self.getToken(SystemVerilogParser.KASSERT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def action_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Action_blockContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_simple_immediate_assert_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_immediate_assert_statement" ):
                listener.enterSimple_immediate_assert_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_immediate_assert_statement" ):
                listener.exitSimple_immediate_assert_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_immediate_assert_statement" ):
                return visitor.visitSimple_immediate_assert_statement(self)
            else:
                return visitor.visitChildren(self)




    def simple_immediate_assert_statement(self):

        localctx = SystemVerilogParser.Simple_immediate_assert_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 822, self.RULE_simple_immediate_assert_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6276
            self.match(SystemVerilogParser.KASSERT)
            self.state = 6277
            self.match(SystemVerilogParser.LP)
            self.state = 6278
            self.expression(0)
            self.state = 6279
            self.match(SystemVerilogParser.RP)
            self.state = 6280
            self.action_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Simple_immediate_assume_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KASSUME(self):
            return self.getToken(SystemVerilogParser.KASSUME, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def action_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Action_blockContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_simple_immediate_assume_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_immediate_assume_statement" ):
                listener.enterSimple_immediate_assume_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_immediate_assume_statement" ):
                listener.exitSimple_immediate_assume_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_immediate_assume_statement" ):
                return visitor.visitSimple_immediate_assume_statement(self)
            else:
                return visitor.visitChildren(self)




    def simple_immediate_assume_statement(self):

        localctx = SystemVerilogParser.Simple_immediate_assume_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 824, self.RULE_simple_immediate_assume_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6282
            self.match(SystemVerilogParser.KASSUME)
            self.state = 6283
            self.match(SystemVerilogParser.LP)
            self.state = 6284
            self.expression(0)
            self.state = 6285
            self.match(SystemVerilogParser.RP)
            self.state = 6286
            self.action_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Simple_immediate_cover_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCOVER(self):
            return self.getToken(SystemVerilogParser.KCOVER, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_simple_immediate_cover_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_immediate_cover_statement" ):
                listener.enterSimple_immediate_cover_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_immediate_cover_statement" ):
                listener.exitSimple_immediate_cover_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_immediate_cover_statement" ):
                return visitor.visitSimple_immediate_cover_statement(self)
            else:
                return visitor.visitChildren(self)




    def simple_immediate_cover_statement(self):

        localctx = SystemVerilogParser.Simple_immediate_cover_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 826, self.RULE_simple_immediate_cover_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6288
            self.match(SystemVerilogParser.KCOVER)
            self.state = 6289
            self.match(SystemVerilogParser.LP)
            self.state = 6290
            self.expression(0)
            self.state = 6291
            self.match(SystemVerilogParser.RP)
            self.state = 6292
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Deferred_immediate_assertion_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def deferred_immediate_assert_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Deferred_immediate_assert_statementContext,0)


        def deferred_immediate_assume_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Deferred_immediate_assume_statementContext,0)


        def deferred_immediate_cover_statement(self):
            return self.getTypedRuleContext(SystemVerilogParser.Deferred_immediate_cover_statementContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_deferred_immediate_assertion_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDeferred_immediate_assertion_statement" ):
                listener.enterDeferred_immediate_assertion_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDeferred_immediate_assertion_statement" ):
                listener.exitDeferred_immediate_assertion_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDeferred_immediate_assertion_statement" ):
                return visitor.visitDeferred_immediate_assertion_statement(self)
            else:
                return visitor.visitChildren(self)




    def deferred_immediate_assertion_statement(self):

        localctx = SystemVerilogParser.Deferred_immediate_assertion_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 828, self.RULE_deferred_immediate_assertion_statement)
        try:
            self.state = 6297
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KASSERT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6294
                self.deferred_immediate_assert_statement()
                pass
            elif token in [SystemVerilogParser.KASSUME]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6295
                self.deferred_immediate_assume_statement()
                pass
            elif token in [SystemVerilogParser.KCOVER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 6296
                self.deferred_immediate_cover_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Deferred_immediate_assert_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KASSERT(self):
            return self.getToken(SystemVerilogParser.KASSERT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def action_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Action_blockContext,0)


        def PZ(self):
            return self.getToken(SystemVerilogParser.PZ, 0)

        def KFINAL(self):
            return self.getToken(SystemVerilogParser.KFINAL, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_deferred_immediate_assert_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDeferred_immediate_assert_statement" ):
                listener.enterDeferred_immediate_assert_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDeferred_immediate_assert_statement" ):
                listener.exitDeferred_immediate_assert_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDeferred_immediate_assert_statement" ):
                return visitor.visitDeferred_immediate_assert_statement(self)
            else:
                return visitor.visitChildren(self)




    def deferred_immediate_assert_statement(self):

        localctx = SystemVerilogParser.Deferred_immediate_assert_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 830, self.RULE_deferred_immediate_assert_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6299
            self.match(SystemVerilogParser.KASSERT)
            self.state = 6300
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.PZ or _la==SystemVerilogParser.KFINAL):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 6301
            self.match(SystemVerilogParser.LP)
            self.state = 6302
            self.expression(0)
            self.state = 6303
            self.match(SystemVerilogParser.RP)
            self.state = 6304
            self.action_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Deferred_immediate_assume_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KASSUME(self):
            return self.getToken(SystemVerilogParser.KASSUME, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def action_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Action_blockContext,0)


        def PZ(self):
            return self.getToken(SystemVerilogParser.PZ, 0)

        def KFINAL(self):
            return self.getToken(SystemVerilogParser.KFINAL, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_deferred_immediate_assume_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDeferred_immediate_assume_statement" ):
                listener.enterDeferred_immediate_assume_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDeferred_immediate_assume_statement" ):
                listener.exitDeferred_immediate_assume_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDeferred_immediate_assume_statement" ):
                return visitor.visitDeferred_immediate_assume_statement(self)
            else:
                return visitor.visitChildren(self)




    def deferred_immediate_assume_statement(self):

        localctx = SystemVerilogParser.Deferred_immediate_assume_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 832, self.RULE_deferred_immediate_assume_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6306
            self.match(SystemVerilogParser.KASSUME)
            self.state = 6307
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.PZ or _la==SystemVerilogParser.KFINAL):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 6308
            self.match(SystemVerilogParser.LP)
            self.state = 6309
            self.expression(0)
            self.state = 6310
            self.match(SystemVerilogParser.RP)
            self.state = 6311
            self.action_block()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Deferred_immediate_cover_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCOVER(self):
            return self.getToken(SystemVerilogParser.KCOVER, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def statement_or_null(self):
            return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,0)


        def PZ(self):
            return self.getToken(SystemVerilogParser.PZ, 0)

        def KFINAL(self):
            return self.getToken(SystemVerilogParser.KFINAL, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_deferred_immediate_cover_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDeferred_immediate_cover_statement" ):
                listener.enterDeferred_immediate_cover_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDeferred_immediate_cover_statement" ):
                listener.exitDeferred_immediate_cover_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDeferred_immediate_cover_statement" ):
                return visitor.visitDeferred_immediate_cover_statement(self)
            else:
                return visitor.visitChildren(self)




    def deferred_immediate_cover_statement(self):

        localctx = SystemVerilogParser.Deferred_immediate_cover_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 834, self.RULE_deferred_immediate_cover_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6313
            self.match(SystemVerilogParser.KCOVER)
            self.state = 6314
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.PZ or _la==SystemVerilogParser.KFINAL):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 6315
            self.match(SystemVerilogParser.LP)
            self.state = 6316
            self.expression(0)
            self.state = 6317
            self.match(SystemVerilogParser.RP)
            self.state = 6318
            self.statement_or_null()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clocking_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCLOCKING(self):
            return self.getToken(SystemVerilogParser.KCLOCKING, 0)

        def clocking_event(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_eventContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KENDCLOCKING(self):
            return self.getToken(SystemVerilogParser.KENDCLOCKING, 0)

        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def clocking_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Clocking_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Clocking_identifierContext,i)


        def clocking_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Clocking_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Clocking_itemContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def KGLOBAL(self):
            return self.getToken(SystemVerilogParser.KGLOBAL, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clocking_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClocking_declaration" ):
                listener.enterClocking_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClocking_declaration" ):
                listener.exitClocking_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClocking_declaration" ):
                return visitor.visitClocking_declaration(self)
            else:
                return visitor.visitChildren(self)




    def clocking_declaration(self):

        localctx = SystemVerilogParser.Clocking_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 836, self.RULE_clocking_declaration)
        self._la = 0 # Token type
        try:
            self.state = 6352
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KCLOCKING, SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6321
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KDEFAULT:
                    self.state = 6320
                    self.match(SystemVerilogParser.KDEFAULT)


                self.state = 6323
                self.match(SystemVerilogParser.KCLOCKING)
                self.state = 6325
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 6324
                    self.clocking_identifier()


                self.state = 6327
                self.clocking_event()
                self.state = 6328
                self.match(SystemVerilogParser.SEMI)
                self.state = 6332
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS or ((((_la - 134)) & ~0x3f) == 0 and ((1 << (_la - 134)) & ((1 << (SystemVerilogParser.KDEFAULT - 134)) | (1 << (SystemVerilogParser.KINOUT - 134)) | (1 << (SystemVerilogParser.KINPUT - 134)))) != 0) or ((((_la - 204)) & ~0x3f) == 0 and ((1 << (_la - 204)) & ((1 << (SystemVerilogParser.KLET - 204)) | (1 << (SystemVerilogParser.KOUTPUT - 204)) | (1 << (SystemVerilogParser.KPROPERTY - 204)))) != 0) or _la==SystemVerilogParser.KSEQUENCE:
                    self.state = 6329
                    self.clocking_item()
                    self.state = 6334
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 6335
                self.match(SystemVerilogParser.KENDCLOCKING)
                self.state = 6338
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 6336
                    self.match(SystemVerilogParser.COLON)
                    self.state = 6337
                    self.clocking_identifier()


                pass
            elif token in [SystemVerilogParser.KGLOBAL]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6340
                self.match(SystemVerilogParser.KGLOBAL)
                self.state = 6341
                self.match(SystemVerilogParser.KCLOCKING)
                self.state = 6343
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 6342
                    self.clocking_identifier()


                self.state = 6345
                self.clocking_event()
                self.state = 6346
                self.match(SystemVerilogParser.SEMI)
                self.state = 6347
                self.match(SystemVerilogParser.KENDCLOCKING)
                self.state = 6350
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 6348
                    self.match(SystemVerilogParser.COLON)
                    self.state = 6349
                    self.clocking_identifier()


                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clocking_eventContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def AT(self):
            return self.getToken(SystemVerilogParser.AT, 0)

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def event_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Event_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clocking_event

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClocking_event" ):
                listener.enterClocking_event(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClocking_event" ):
                listener.exitClocking_event(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClocking_event" ):
                return visitor.visitClocking_event(self)
            else:
                return visitor.visitChildren(self)




    def clocking_event(self):

        localctx = SystemVerilogParser.Clocking_eventContext(self, self._ctx, self.state)
        self.enterRule(localctx, 838, self.RULE_clocking_event)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6354
            self.match(SystemVerilogParser.AT)
            self.state = 6360
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 6355
                self.identifier()
                pass
            elif token in [SystemVerilogParser.LP]:
                self.state = 6356
                self.match(SystemVerilogParser.LP)
                self.state = 6357
                self.event_expression(0)
                self.state = 6358
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clocking_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def default_skew(self):
            return self.getTypedRuleContext(SystemVerilogParser.Default_skewContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def clocking_direction(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_directionContext,0)


        def list_of_clocking_decl_assign(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_clocking_decl_assignContext,0)


        def assertion_item_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assertion_item_declarationContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clocking_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClocking_item" ):
                listener.enterClocking_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClocking_item" ):
                listener.exitClocking_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClocking_item" ):
                return visitor.visitClocking_item(self)
            else:
                return visitor.visitChildren(self)




    def clocking_item(self):

        localctx = SystemVerilogParser.Clocking_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 840, self.RULE_clocking_item)
        self._la = 0 # Token type
        try:
            self.state = 6377
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6362
                self.match(SystemVerilogParser.KDEFAULT)
                self.state = 6363
                self.default_skew()
                self.state = 6364
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KINOUT, SystemVerilogParser.KINPUT, SystemVerilogParser.KOUTPUT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6366
                self.clocking_direction()
                self.state = 6367
                self.list_of_clocking_decl_assign()
                self.state = 6368
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.LPS, SystemVerilogParser.KLET, SystemVerilogParser.KPROPERTY, SystemVerilogParser.KSEQUENCE]:
                self.enterOuterAlt(localctx, 3)
                self.state = 6373
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 6370
                    self.attribute_instance()
                    self.state = 6375
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 6376
                self.assertion_item_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Default_skewContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINPUT(self):
            return self.getToken(SystemVerilogParser.KINPUT, 0)

        def clocking_skew(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Clocking_skewContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Clocking_skewContext,i)


        def KOUTPUT(self):
            return self.getToken(SystemVerilogParser.KOUTPUT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_default_skew

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefault_skew" ):
                listener.enterDefault_skew(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefault_skew" ):
                listener.exitDefault_skew(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefault_skew" ):
                return visitor.visitDefault_skew(self)
            else:
                return visitor.visitChildren(self)




    def default_skew(self):

        localctx = SystemVerilogParser.Default_skewContext(self, self._ctx, self.state)
        self.enterRule(localctx, 842, self.RULE_default_skew)
        self._la = 0 # Token type
        try:
            self.state = 6387
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KINPUT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6379
                self.match(SystemVerilogParser.KINPUT)
                self.state = 6380
                self.clocking_skew()
                self.state = 6383
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KOUTPUT:
                    self.state = 6381
                    self.match(SystemVerilogParser.KOUTPUT)
                    self.state = 6382
                    self.clocking_skew()


                pass
            elif token in [SystemVerilogParser.KOUTPUT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6385
                self.match(SystemVerilogParser.KOUTPUT)
                self.state = 6386
                self.clocking_skew()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clocking_directionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KINPUT(self):
            return self.getToken(SystemVerilogParser.KINPUT, 0)

        def clocking_skew(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Clocking_skewContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Clocking_skewContext,i)


        def KOUTPUT(self):
            return self.getToken(SystemVerilogParser.KOUTPUT, 0)

        def KINOUT(self):
            return self.getToken(SystemVerilogParser.KINOUT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clocking_direction

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClocking_direction" ):
                listener.enterClocking_direction(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClocking_direction" ):
                listener.exitClocking_direction(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClocking_direction" ):
                return visitor.visitClocking_direction(self)
            else:
                return visitor.visitChildren(self)




    def clocking_direction(self):

        localctx = SystemVerilogParser.Clocking_directionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 844, self.RULE_clocking_direction)
        self._la = 0 # Token type
        try:
            self.state = 6404
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KINPUT]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6389
                self.match(SystemVerilogParser.KINPUT)
                self.state = 6391
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P or _la==SystemVerilogParser.KEDGE or _la==SystemVerilogParser.KNEGEDGE or _la==SystemVerilogParser.KPOSEDGE:
                    self.state = 6390
                    self.clocking_skew()


                self.state = 6397
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KOUTPUT:
                    self.state = 6393
                    self.match(SystemVerilogParser.KOUTPUT)
                    self.state = 6395
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.P or _la==SystemVerilogParser.KEDGE or _la==SystemVerilogParser.KNEGEDGE or _la==SystemVerilogParser.KPOSEDGE:
                        self.state = 6394
                        self.clocking_skew()




                pass
            elif token in [SystemVerilogParser.KOUTPUT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6399
                self.match(SystemVerilogParser.KOUTPUT)
                self.state = 6401
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P or _la==SystemVerilogParser.KEDGE or _la==SystemVerilogParser.KNEGEDGE or _la==SystemVerilogParser.KPOSEDGE:
                    self.state = 6400
                    self.clocking_skew()


                pass
            elif token in [SystemVerilogParser.KINOUT]:
                self.enterOuterAlt(localctx, 3)
                self.state = 6403
                self.match(SystemVerilogParser.KINOUT)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_clocking_decl_assignContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def clocking_decl_assign(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Clocking_decl_assignContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Clocking_decl_assignContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_clocking_decl_assign

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_clocking_decl_assign" ):
                listener.enterList_of_clocking_decl_assign(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_clocking_decl_assign" ):
                listener.exitList_of_clocking_decl_assign(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_clocking_decl_assign" ):
                return visitor.visitList_of_clocking_decl_assign(self)
            else:
                return visitor.visitChildren(self)




    def list_of_clocking_decl_assign(self):

        localctx = SystemVerilogParser.List_of_clocking_decl_assignContext(self, self._ctx, self.state)
        self.enterRule(localctx, 846, self.RULE_list_of_clocking_decl_assign)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6406
            self.clocking_decl_assign()
            self.state = 6411
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6407
                self.match(SystemVerilogParser.COMMA)
                self.state = 6408
                self.clocking_decl_assign()
                self.state = 6413
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clocking_decl_assignContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def signal_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Signal_identifierContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clocking_decl_assign

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClocking_decl_assign" ):
                listener.enterClocking_decl_assign(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClocking_decl_assign" ):
                listener.exitClocking_decl_assign(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClocking_decl_assign" ):
                return visitor.visitClocking_decl_assign(self)
            else:
                return visitor.visitChildren(self)




    def clocking_decl_assign(self):

        localctx = SystemVerilogParser.Clocking_decl_assignContext(self, self._ctx, self.state)
        self.enterRule(localctx, 848, self.RULE_clocking_decl_assign)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6414
            self.signal_identifier()
            self.state = 6417
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 6415
                self.match(SystemVerilogParser.EQ)
                self.state = 6416
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clocking_skewContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def edge_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Edge_identifierContext,0)


        def delay_control(self):
            return self.getTypedRuleContext(SystemVerilogParser.Delay_controlContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clocking_skew

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClocking_skew" ):
                listener.enterClocking_skew(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClocking_skew" ):
                listener.exitClocking_skew(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClocking_skew" ):
                return visitor.visitClocking_skew(self)
            else:
                return visitor.visitChildren(self)




    def clocking_skew(self):

        localctx = SystemVerilogParser.Clocking_skewContext(self, self._ctx, self.state)
        self.enterRule(localctx, 850, self.RULE_clocking_skew)
        self._la = 0 # Token type
        try:
            self.state = 6424
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KEDGE, SystemVerilogParser.KNEGEDGE, SystemVerilogParser.KPOSEDGE]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6419
                self.edge_identifier()
                self.state = 6421
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.P:
                    self.state = 6420
                    self.delay_control()


                pass
            elif token in [SystemVerilogParser.P]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6423
                self.delay_control()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clocking_driveContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def clockvar_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clockvar_expressionContext,0)


        def LTEQ(self):
            return self.getToken(SystemVerilogParser.LTEQ, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def cycle_delay(self):
            return self.getTypedRuleContext(SystemVerilogParser.Cycle_delayContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clocking_drive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClocking_drive" ):
                listener.enterClocking_drive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClocking_drive" ):
                listener.exitClocking_drive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClocking_drive" ):
                return visitor.visitClocking_drive(self)
            else:
                return visitor.visitChildren(self)




    def clocking_drive(self):

        localctx = SystemVerilogParser.Clocking_driveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 852, self.RULE_clocking_drive)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6426
            self.clockvar_expression()
            self.state = 6427
            self.match(SystemVerilogParser.LTEQ)
            self.state = 6429
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.PP:
                self.state = 6428
                self.cycle_delay()


            self.state = 6431
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cycle_delayContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PP(self):
            return self.getToken(SystemVerilogParser.PP, 0)

        def DECIMAL_NUMBER(self):
            return self.getToken(SystemVerilogParser.DECIMAL_NUMBER, 0)

        def UNSIGNED_NUMBER(self):
            return self.getToken(SystemVerilogParser.UNSIGNED_NUMBER, 0)

        def OCTAL_NUMBER(self):
            return self.getToken(SystemVerilogParser.OCTAL_NUMBER, 0)

        def BINARY_NUMBER(self):
            return self.getToken(SystemVerilogParser.BINARY_NUMBER, 0)

        def HEX_NUMBER(self):
            return self.getToken(SystemVerilogParser.HEX_NUMBER, 0)

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cycle_delay

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCycle_delay" ):
                listener.enterCycle_delay(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCycle_delay" ):
                listener.exitCycle_delay(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCycle_delay" ):
                return visitor.visitCycle_delay(self)
            else:
                return visitor.visitChildren(self)




    def cycle_delay(self):

        localctx = SystemVerilogParser.Cycle_delayContext(self, self._ctx, self.state)
        self.enterRule(localctx, 854, self.RULE_cycle_delay)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6433
            self.match(SystemVerilogParser.PP)
            self.state = 6444
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DECIMAL_NUMBER]:
                self.state = 6434
                self.match(SystemVerilogParser.DECIMAL_NUMBER)
                pass
            elif token in [SystemVerilogParser.UNSIGNED_NUMBER]:
                self.state = 6435
                self.match(SystemVerilogParser.UNSIGNED_NUMBER)
                pass
            elif token in [SystemVerilogParser.OCTAL_NUMBER]:
                self.state = 6436
                self.match(SystemVerilogParser.OCTAL_NUMBER)
                pass
            elif token in [SystemVerilogParser.BINARY_NUMBER]:
                self.state = 6437
                self.match(SystemVerilogParser.BINARY_NUMBER)
                pass
            elif token in [SystemVerilogParser.HEX_NUMBER]:
                self.state = 6438
                self.match(SystemVerilogParser.HEX_NUMBER)
                pass
            elif token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 6439
                self.identifier()
                pass
            elif token in [SystemVerilogParser.LP]:
                self.state = 6440
                self.match(SystemVerilogParser.LP)
                self.state = 6441
                self.expression(0)
                self.state = 6442
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ClockvarContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clockvar

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClockvar" ):
                listener.enterClockvar(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClockvar" ):
                listener.exitClockvar(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClockvar" ):
                return visitor.visitClockvar(self)
            else:
                return visitor.visitChildren(self)




    def clockvar(self):

        localctx = SystemVerilogParser.ClockvarContext(self, self._ctx, self.state)
        self.enterRule(localctx, 856, self.RULE_clockvar)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6446
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clockvar_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def clockvar(self):
            return self.getTypedRuleContext(SystemVerilogParser.ClockvarContext,0)


        def select_(self):
            return self.getTypedRuleContext(SystemVerilogParser.Select_Context,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clockvar_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClockvar_expression" ):
                listener.enterClockvar_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClockvar_expression" ):
                listener.exitClockvar_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClockvar_expression" ):
                return visitor.visitClockvar_expression(self)
            else:
                return visitor.visitChildren(self)




    def clockvar_expression(self):

        localctx = SystemVerilogParser.Clockvar_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 858, self.RULE_clockvar_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6448
            self.clockvar()
            self.state = 6449
            self.select_()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Randsequence_statementContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KRANDSEQUENCE(self):
            return self.getToken(SystemVerilogParser.KRANDSEQUENCE, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def production(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ProductionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ProductionContext,i)


        def KENDSEQUENCE(self):
            return self.getToken(SystemVerilogParser.KENDSEQUENCE, 0)

        def production_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Production_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_randsequence_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRandsequence_statement" ):
                listener.enterRandsequence_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRandsequence_statement" ):
                listener.exitRandsequence_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRandsequence_statement" ):
                return visitor.visitRandsequence_statement(self)
            else:
                return visitor.visitChildren(self)




    def randsequence_statement(self):

        localctx = SystemVerilogParser.Randsequence_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 860, self.RULE_randsequence_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6451
            self.match(SystemVerilogParser.KRANDSEQUENCE)
            self.state = 6452
            self.match(SystemVerilogParser.LP)
            self.state = 6454
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 6453
                self.production_identifier()


            self.state = 6456
            self.match(SystemVerilogParser.RP)
            self.state = 6457
            self.production()
            self.state = 6461
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.DUNIT or ((((_la - 109)) & ~0x3f) == 0 and ((1 << (_la - 109)) & ((1 << (SystemVerilogParser.KBIT - 109)) | (1 << (SystemVerilogParser.KBYTE - 109)) | (1 << (SystemVerilogParser.KCHANDLE - 109)) | (1 << (SystemVerilogParser.KENUM - 109)) | (1 << (SystemVerilogParser.KEVENT - 109)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSTRUCT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNION - 276)) | (1 << (SystemVerilogParser.KVIRTUAL - 276)) | (1 << (SystemVerilogParser.KVOID - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                self.state = 6458
                self.production()
                self.state = 6463
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6464
            self.match(SystemVerilogParser.KENDSEQUENCE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ProductionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def production_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Production_identifierContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def rs_rule(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Rs_ruleContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Rs_ruleContext,i)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def data_type_or_void(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_type_or_voidContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def tf_port_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_port_listContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def BAR(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.BAR)
            else:
                return self.getToken(SystemVerilogParser.BAR, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_production

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProduction" ):
                listener.enterProduction(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProduction" ):
                listener.exitProduction(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProduction" ):
                return visitor.visitProduction(self)
            else:
                return visitor.visitChildren(self)




    def production(self):

        localctx = SystemVerilogParser.ProductionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 862, self.RULE_production)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6467
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,800,self._ctx)
            if la_ == 1:
                self.state = 6466
                self.data_type_or_void()


            self.state = 6469
            self.production_identifier()
            self.state = 6474
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 6470
                self.match(SystemVerilogParser.LP)
                self.state = 6471
                self.tf_port_list()
                self.state = 6472
                self.match(SystemVerilogParser.RP)


            self.state = 6476
            self.match(SystemVerilogParser.COLON)
            self.state = 6477
            self.rs_rule()
            self.state = 6482
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.BAR:
                self.state = 6478
                self.match(SystemVerilogParser.BAR)
                self.state = 6479
                self.rs_rule()
                self.state = 6484
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6485
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Rs_ruleContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def rs_production_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Rs_production_listContext,0)


        def COLONEQ(self):
            return self.getToken(SystemVerilogParser.COLONEQ, 0)

        def weight_specification(self):
            return self.getTypedRuleContext(SystemVerilogParser.Weight_specificationContext,0)


        def rs_code_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Rs_code_blockContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_rs_rule

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRs_rule" ):
                listener.enterRs_rule(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRs_rule" ):
                listener.exitRs_rule(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRs_rule" ):
                return visitor.visitRs_rule(self)
            else:
                return visitor.visitChildren(self)




    def rs_rule(self):

        localctx = SystemVerilogParser.Rs_ruleContext(self, self._ctx, self.state)
        self.enterRule(localctx, 864, self.RULE_rs_rule)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6487
            self.rs_production_list()
            self.state = 6493
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLONEQ:
                self.state = 6488
                self.match(SystemVerilogParser.COLONEQ)
                self.state = 6489
                self.weight_specification()
                self.state = 6491
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LC:
                    self.state = 6490
                    self.rs_code_block()




        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Rs_production_listContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def rs_prod(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Rs_prodContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Rs_prodContext,i)


        def KRAND(self):
            return self.getToken(SystemVerilogParser.KRAND, 0)

        def KJOIN(self):
            return self.getToken(SystemVerilogParser.KJOIN, 0)

        def production_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Production_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Production_itemContext,i)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_rs_production_list

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRs_production_list" ):
                listener.enterRs_production_list(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRs_production_list" ):
                listener.exitRs_production_list(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRs_production_list" ):
                return visitor.visitRs_production_list(self)
            else:
                return visitor.visitChildren(self)




    def rs_production_list(self):

        localctx = SystemVerilogParser.Rs_production_listContext(self, self._ctx, self.state)
        self.enterRule(localctx, 866, self.RULE_rs_production_list)
        self._la = 0 # Token type
        try:
            self.state = 6518
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.LC, SystemVerilogParser.KCASE, SystemVerilogParser.KIF, SystemVerilogParser.KREPEAT, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6495
                self.rs_prod()
                self.state = 6499
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LC or _la==SystemVerilogParser.KCASE or _la==SystemVerilogParser.KIF or _la==SystemVerilogParser.KREPEAT or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 6496
                    self.rs_prod()
                    self.state = 6501
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            elif token in [SystemVerilogParser.KRAND]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6502
                self.match(SystemVerilogParser.KRAND)
                self.state = 6503
                self.match(SystemVerilogParser.KJOIN)
                self.state = 6508
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 6504
                    self.match(SystemVerilogParser.LP)
                    self.state = 6505
                    self.expression(0)
                    self.state = 6506
                    self.match(SystemVerilogParser.RP)


                self.state = 6510
                self.production_item()
                self.state = 6511
                self.production_item()
                self.state = 6515
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 6512
                    self.production_item()
                    self.state = 6517
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Weight_specificationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(SystemVerilogParser.DECIMAL_NUMBER, 0)

        def UNSIGNED_NUMBER(self):
            return self.getToken(SystemVerilogParser.UNSIGNED_NUMBER, 0)

        def OCTAL_NUMBER(self):
            return self.getToken(SystemVerilogParser.OCTAL_NUMBER, 0)

        def BINARY_NUMBER(self):
            return self.getToken(SystemVerilogParser.BINARY_NUMBER, 0)

        def HEX_NUMBER(self):
            return self.getToken(SystemVerilogParser.HEX_NUMBER, 0)

        def ps_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_weight_specification

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWeight_specification" ):
                listener.enterWeight_specification(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWeight_specification" ):
                listener.exitWeight_specification(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWeight_specification" ):
                return visitor.visitWeight_specification(self)
            else:
                return visitor.visitChildren(self)




    def weight_specification(self):

        localctx = SystemVerilogParser.Weight_specificationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 868, self.RULE_weight_specification)
        try:
            self.state = 6530
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DECIMAL_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6520
                self.match(SystemVerilogParser.DECIMAL_NUMBER)
                pass
            elif token in [SystemVerilogParser.UNSIGNED_NUMBER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6521
                self.match(SystemVerilogParser.UNSIGNED_NUMBER)
                pass
            elif token in [SystemVerilogParser.OCTAL_NUMBER]:
                self.enterOuterAlt(localctx, 3)
                self.state = 6522
                self.match(SystemVerilogParser.OCTAL_NUMBER)
                pass
            elif token in [SystemVerilogParser.BINARY_NUMBER]:
                self.enterOuterAlt(localctx, 4)
                self.state = 6523
                self.match(SystemVerilogParser.BINARY_NUMBER)
                pass
            elif token in [SystemVerilogParser.HEX_NUMBER]:
                self.enterOuterAlt(localctx, 5)
                self.state = 6524
                self.match(SystemVerilogParser.HEX_NUMBER)
                pass
            elif token in [SystemVerilogParser.DUNIT, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 6)
                self.state = 6525
                self.ps_identifier()
                pass
            elif token in [SystemVerilogParser.LP]:
                self.enterOuterAlt(localctx, 7)
                self.state = 6526
                self.match(SystemVerilogParser.LP)
                self.state = 6527
                self.expression(0)
                self.state = 6528
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Rs_code_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def data_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Data_declarationContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Data_declarationContext,i)


        def statement_or_null(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Statement_or_nullContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Statement_or_nullContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_rs_code_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRs_code_block" ):
                listener.enterRs_code_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRs_code_block" ):
                listener.exitRs_code_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRs_code_block" ):
                return visitor.visitRs_code_block(self)
            else:
                return visitor.visitChildren(self)




    def rs_code_block(self):

        localctx = SystemVerilogParser.Rs_code_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 870, self.RULE_rs_code_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6532
            self.match(SystemVerilogParser.LC)
            self.state = 6536
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,810,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 6533
                    self.data_declaration() 
                self.state = 6538
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,810,self._ctx)

            self.state = 6542
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.P) | (1 << SystemVerilogParser.PP) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DERROR) | (1 << SystemVerilogParser.DFATAL) | (1 << SystemVerilogParser.DINFO) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.DWARNING) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.LPS) | (1 << SystemVerilogParser.SEMI) | (1 << SystemVerilogParser.AT) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.LC))) != 0) or ((((_la - 69)) & ~0x3f) == 0 and ((1 << (_la - 69)) & ((1 << (SystemVerilogParser.PLUSPLUS - 69)) | (1 << (SystemVerilogParser.ARROW - 69)) | (1 << (SystemVerilogParser.MINUSGTGT - 69)) | (1 << (SystemVerilogParser.KASSERT - 69)) | (1 << (SystemVerilogParser.KASSIGN - 69)) | (1 << (SystemVerilogParser.KASSUME - 69)) | (1 << (SystemVerilogParser.KBEGIN - 69)) | (1 << (SystemVerilogParser.KBREAK - 69)) | (1 << (SystemVerilogParser.KBYTE - 69)) | (1 << (SystemVerilogParser.KCASE - 69)) | (1 << (SystemVerilogParser.KCASEX - 69)) | (1 << (SystemVerilogParser.KCASEZ - 69)) | (1 << (SystemVerilogParser.KCONTINUE - 69)) | (1 << (SystemVerilogParser.KCOVER - 69)))) != 0) or ((((_la - 133)) & ~0x3f) == 0 and ((1 << (_la - 133)) & ((1 << (SystemVerilogParser.KDEASSIGN - 133)) | (1 << (SystemVerilogParser.KDISABLE - 133)) | (1 << (SystemVerilogParser.KDO - 133)) | (1 << (SystemVerilogParser.KEXPECT - 133)) | (1 << (SystemVerilogParser.KFOR - 133)) | (1 << (SystemVerilogParser.KFORCE - 133)) | (1 << (SystemVerilogParser.KFOREACH - 133)) | (1 << (SystemVerilogParser.KFOREVER - 133)) | (1 << (SystemVerilogParser.KFORK - 133)) | (1 << (SystemVerilogParser.KIF - 133)) | (1 << (SystemVerilogParser.KINT - 133)) | (1 << (SystemVerilogParser.KINTEGER - 133)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KPRIORITY - 207)) | (1 << (SystemVerilogParser.KRANDCASE - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KRANDSEQUENCE - 207)) | (1 << (SystemVerilogParser.KRELEASE - 207)) | (1 << (SystemVerilogParser.KREPEAT - 207)) | (1 << (SystemVerilogParser.KRESTRICT - 207)) | (1 << (SystemVerilogParser.KRETURN - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNIQUE - 276)) | (1 << (SystemVerilogParser.KUNIQUE0 - 276)) | (1 << (SystemVerilogParser.KVOID - 276)) | (1 << (SystemVerilogParser.KWAIT - 276)) | (1 << (SystemVerilogParser.KWAIT_ORDER - 276)) | (1 << (SystemVerilogParser.KWHILE - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 6539
                self.statement_or_null()
                self.state = 6544
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6545
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Rs_prodContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def production_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Production_itemContext,0)


        def rs_code_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Rs_code_blockContext,0)


        def rs_if_else(self):
            return self.getTypedRuleContext(SystemVerilogParser.Rs_if_elseContext,0)


        def rs_repeat(self):
            return self.getTypedRuleContext(SystemVerilogParser.Rs_repeatContext,0)


        def rs_case(self):
            return self.getTypedRuleContext(SystemVerilogParser.Rs_caseContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_rs_prod

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRs_prod" ):
                listener.enterRs_prod(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRs_prod" ):
                listener.exitRs_prod(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRs_prod" ):
                return visitor.visitRs_prod(self)
            else:
                return visitor.visitChildren(self)




    def rs_prod(self):

        localctx = SystemVerilogParser.Rs_prodContext(self, self._ctx, self.state)
        self.enterRule(localctx, 872, self.RULE_rs_prod)
        try:
            self.state = 6552
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6547
                self.production_item()
                pass
            elif token in [SystemVerilogParser.LC]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6548
                self.rs_code_block()
                pass
            elif token in [SystemVerilogParser.KIF]:
                self.enterOuterAlt(localctx, 3)
                self.state = 6549
                self.rs_if_else()
                pass
            elif token in [SystemVerilogParser.KREPEAT]:
                self.enterOuterAlt(localctx, 4)
                self.state = 6550
                self.rs_repeat()
                pass
            elif token in [SystemVerilogParser.KCASE]:
                self.enterOuterAlt(localctx, 5)
                self.state = 6551
                self.rs_case()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Production_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def production_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Production_identifierContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_production_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProduction_item" ):
                listener.enterProduction_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProduction_item" ):
                listener.exitProduction_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProduction_item" ):
                return visitor.visitProduction_item(self)
            else:
                return visitor.visitChildren(self)




    def production_item(self):

        localctx = SystemVerilogParser.Production_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 874, self.RULE_production_item)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6554
            self.production_identifier()
            self.state = 6559
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LP:
                self.state = 6555
                self.match(SystemVerilogParser.LP)
                self.state = 6556
                self.list_of_arguments()
                self.state = 6557
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Rs_if_elseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KIF(self):
            return self.getToken(SystemVerilogParser.KIF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def production_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Production_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Production_itemContext,i)


        def KELSE(self):
            return self.getToken(SystemVerilogParser.KELSE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_rs_if_else

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRs_if_else" ):
                listener.enterRs_if_else(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRs_if_else" ):
                listener.exitRs_if_else(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRs_if_else" ):
                return visitor.visitRs_if_else(self)
            else:
                return visitor.visitChildren(self)




    def rs_if_else(self):

        localctx = SystemVerilogParser.Rs_if_elseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 876, self.RULE_rs_if_else)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6561
            self.match(SystemVerilogParser.KIF)
            self.state = 6562
            self.match(SystemVerilogParser.LP)
            self.state = 6563
            self.expression(0)
            self.state = 6564
            self.match(SystemVerilogParser.RP)
            self.state = 6565
            self.production_item()
            self.state = 6568
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KELSE:
                self.state = 6566
                self.match(SystemVerilogParser.KELSE)
                self.state = 6567
                self.production_item()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Rs_repeatContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KREPEAT(self):
            return self.getToken(SystemVerilogParser.KREPEAT, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def production_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Production_itemContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_rs_repeat

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRs_repeat" ):
                listener.enterRs_repeat(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRs_repeat" ):
                listener.exitRs_repeat(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRs_repeat" ):
                return visitor.visitRs_repeat(self)
            else:
                return visitor.visitChildren(self)




    def rs_repeat(self):

        localctx = SystemVerilogParser.Rs_repeatContext(self, self._ctx, self.state)
        self.enterRule(localctx, 878, self.RULE_rs_repeat)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6570
            self.match(SystemVerilogParser.KREPEAT)
            self.state = 6571
            self.match(SystemVerilogParser.LP)
            self.state = 6572
            self.expression(0)
            self.state = 6573
            self.match(SystemVerilogParser.RP)
            self.state = 6574
            self.production_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Rs_caseContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KCASE(self):
            return self.getToken(SystemVerilogParser.KCASE, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def case_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Case_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def rs_case_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Rs_case_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Rs_case_itemContext,i)


        def KENDCASE(self):
            return self.getToken(SystemVerilogParser.KENDCASE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_rs_case

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRs_case" ):
                listener.enterRs_case(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRs_case" ):
                listener.exitRs_case(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRs_case" ):
                return visitor.visitRs_case(self)
            else:
                return visitor.visitChildren(self)




    def rs_case(self):

        localctx = SystemVerilogParser.Rs_caseContext(self, self._ctx, self.state)
        self.enterRule(localctx, 880, self.RULE_rs_case)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6576
            self.match(SystemVerilogParser.KCASE)
            self.state = 6577
            self.match(SystemVerilogParser.LP)
            self.state = 6578
            self.case_expression()
            self.state = 6579
            self.match(SystemVerilogParser.RP)
            self.state = 6580
            self.rs_case_item()
            self.state = 6584
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 134)) & ~0x3f) == 0 and ((1 << (_la - 134)) & ((1 << (SystemVerilogParser.KDEFAULT - 134)) | (1 << (SystemVerilogParser.KINT - 134)) | (1 << (SystemVerilogParser.KINTEGER - 134)))) != 0) or ((((_la - 207)) & ~0x3f) == 0 and ((1 << (_la - 207)) & ((1 << (SystemVerilogParser.KLOCAL - 207)) | (1 << (SystemVerilogParser.KLOGIC - 207)) | (1 << (SystemVerilogParser.KLONGINT - 207)) | (1 << (SystemVerilogParser.KNULL - 207)) | (1 << (SystemVerilogParser.KRANDOMIZE - 207)) | (1 << (SystemVerilogParser.KREAL - 207)) | (1 << (SystemVerilogParser.KREALTIME - 207)) | (1 << (SystemVerilogParser.KREG - 207)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                self.state = 6581
                self.rs_case_item()
                self.state = 6586
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6587
            self.match(SystemVerilogParser.KENDCASE)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Rs_case_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def case_item_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Case_item_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Case_item_expressionContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def production_item(self):
            return self.getTypedRuleContext(SystemVerilogParser.Production_itemContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def KDEFAULT(self):
            return self.getToken(SystemVerilogParser.KDEFAULT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_rs_case_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRs_case_item" ):
                listener.enterRs_case_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRs_case_item" ):
                listener.exitRs_case_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRs_case_item" ):
                return visitor.visitRs_case_item(self)
            else:
                return visitor.visitChildren(self)




    def rs_case_item(self):

        localctx = SystemVerilogParser.Rs_case_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 882, self.RULE_rs_case_item)
        self._la = 0 # Token type
        try:
            self.state = 6608
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6589
                self.case_item_expression()
                self.state = 6594
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 6590
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6591
                    self.case_item_expression()
                    self.state = 6596
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 6597
                self.match(SystemVerilogParser.COLON)
                self.state = 6598
                self.production_item()
                self.state = 6599
                self.match(SystemVerilogParser.SEMI)
                pass
            elif token in [SystemVerilogParser.KDEFAULT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6601
                self.match(SystemVerilogParser.KDEFAULT)
                self.state = 6603
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COLON:
                    self.state = 6602
                    self.match(SystemVerilogParser.COLON)


                self.state = 6605
                self.production_item()
                self.state = 6606
                self.match(SystemVerilogParser.SEMI)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specify_blockContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KSPECIFY(self):
            return self.getToken(SystemVerilogParser.KSPECIFY, 0)

        def KENDSPECIFY(self):
            return self.getToken(SystemVerilogParser.KENDSPECIFY, 0)

        def specify_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Specify_itemContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Specify_itemContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_specify_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_block" ):
                listener.enterSpecify_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_block" ):
                listener.exitSpecify_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_block" ):
                return visitor.visitSpecify_block(self)
            else:
                return visitor.visitChildren(self)




    def specify_block(self):

        localctx = SystemVerilogParser.Specify_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 884, self.RULE_specify_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6610
            self.match(SystemVerilogParser.KSPECIFY)
            self.state = 6614
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.LP or ((((_la - 180)) & ~0x3f) == 0 and ((1 << (_la - 180)) & ((1 << (SystemVerilogParser.KIF - 180)) | (1 << (SystemVerilogParser.KIFNONE - 180)) | (1 << (SystemVerilogParser.KNOSHOWCANCELLED - 180)))) != 0) or ((((_la - 246)) & ~0x3f) == 0 and ((1 << (_la - 246)) & ((1 << (SystemVerilogParser.KPULSESTYLE_ONDETECT - 246)) | (1 << (SystemVerilogParser.KPULSESTYLE_ONEVENT - 246)) | (1 << (SystemVerilogParser.KSHOWCANCELLED - 246)) | (1 << (SystemVerilogParser.KSPECPARAM - 246)))) != 0):
                self.state = 6611
                self.specify_item()
                self.state = 6616
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6617
            self.match(SystemVerilogParser.KENDSPECIFY)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specify_itemContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specparam_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specparam_declarationContext,0)


        def pulsestyle_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Pulsestyle_declarationContext,0)


        def showcancelled_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Showcancelled_declarationContext,0)


        def path_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_specify_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_item" ):
                listener.enterSpecify_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_item" ):
                listener.exitSpecify_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_item" ):
                return visitor.visitSpecify_item(self)
            else:
                return visitor.visitChildren(self)




    def specify_item(self):

        localctx = SystemVerilogParser.Specify_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 886, self.RULE_specify_item)
        try:
            self.state = 6623
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KSPECPARAM]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6619
                self.specparam_declaration()
                pass
            elif token in [SystemVerilogParser.KPULSESTYLE_ONDETECT, SystemVerilogParser.KPULSESTYLE_ONEVENT]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6620
                self.pulsestyle_declaration()
                pass
            elif token in [SystemVerilogParser.KNOSHOWCANCELLED, SystemVerilogParser.KSHOWCANCELLED]:
                self.enterOuterAlt(localctx, 3)
                self.state = 6621
                self.showcancelled_declaration()
                pass
            elif token in [SystemVerilogParser.LP, SystemVerilogParser.KIF, SystemVerilogParser.KIFNONE]:
                self.enterOuterAlt(localctx, 4)
                self.state = 6622
                self.path_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pulsestyle_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_path_outputsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KPULSESTYLE_ONEVENT(self):
            return self.getToken(SystemVerilogParser.KPULSESTYLE_ONEVENT, 0)

        def KPULSESTYLE_ONDETECT(self):
            return self.getToken(SystemVerilogParser.KPULSESTYLE_ONDETECT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_pulsestyle_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulsestyle_declaration" ):
                listener.enterPulsestyle_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulsestyle_declaration" ):
                listener.exitPulsestyle_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulsestyle_declaration" ):
                return visitor.visitPulsestyle_declaration(self)
            else:
                return visitor.visitChildren(self)




    def pulsestyle_declaration(self):

        localctx = SystemVerilogParser.Pulsestyle_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 888, self.RULE_pulsestyle_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6625
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KPULSESTYLE_ONDETECT or _la==SystemVerilogParser.KPULSESTYLE_ONEVENT):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 6626
            self.list_of_path_outputs()
            self.state = 6627
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Showcancelled_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_path_outputsContext,0)


        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def KSHOWCANCELLED(self):
            return self.getToken(SystemVerilogParser.KSHOWCANCELLED, 0)

        def KNOSHOWCANCELLED(self):
            return self.getToken(SystemVerilogParser.KNOSHOWCANCELLED, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_showcancelled_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterShowcancelled_declaration" ):
                listener.enterShowcancelled_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitShowcancelled_declaration" ):
                listener.exitShowcancelled_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitShowcancelled_declaration" ):
                return visitor.visitShowcancelled_declaration(self)
            else:
                return visitor.visitChildren(self)




    def showcancelled_declaration(self):

        localctx = SystemVerilogParser.Showcancelled_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 890, self.RULE_showcancelled_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6629
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KNOSHOWCANCELLED or _la==SystemVerilogParser.KSHOWCANCELLED):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 6630
            self.list_of_path_outputs()
            self.state = 6631
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Path_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SEMI(self):
            return self.getToken(SystemVerilogParser.SEMI, 0)

        def simple_path_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_path_declarationContext,0)


        def edge_sensitive_path_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Edge_sensitive_path_declarationContext,0)


        def state_dependent_path_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.State_dependent_path_declarationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_declaration" ):
                listener.enterPath_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_declaration" ):
                listener.exitPath_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_declaration" ):
                return visitor.visitPath_declaration(self)
            else:
                return visitor.visitChildren(self)




    def path_declaration(self):

        localctx = SystemVerilogParser.Path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 892, self.RULE_path_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6636
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,821,self._ctx)
            if la_ == 1:
                self.state = 6633
                self.simple_path_declaration()
                pass

            elif la_ == 2:
                self.state = 6634
                self.edge_sensitive_path_declaration()
                pass

            elif la_ == 3:
                self.state = 6635
                self.state_dependent_path_declaration()
                pass


            self.state = 6638
            self.match(SystemVerilogParser.SEMI)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Simple_path_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def path_delay_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_valueContext,0)


        def parallel_path_description(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parallel_path_descriptionContext,0)


        def full_path_description(self):
            return self.getTypedRuleContext(SystemVerilogParser.Full_path_descriptionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_simple_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_path_declaration" ):
                listener.enterSimple_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_path_declaration" ):
                listener.exitSimple_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_path_declaration" ):
                return visitor.visitSimple_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def simple_path_declaration(self):

        localctx = SystemVerilogParser.Simple_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 894, self.RULE_simple_path_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6642
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,822,self._ctx)
            if la_ == 1:
                self.state = 6640
                self.parallel_path_description()
                pass

            elif la_ == 2:
                self.state = 6641
                self.full_path_description()
                pass


            self.state = 6644
            self.match(SystemVerilogParser.EQ)
            self.state = 6645
            self.path_delay_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parallel_path_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specify_input_terminal_descriptorContext,0)


        def EQGT(self):
            return self.getToken(SystemVerilogParser.EQGT, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specify_output_terminal_descriptorContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def polarity_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_parallel_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParallel_path_description" ):
                listener.enterParallel_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParallel_path_description" ):
                listener.exitParallel_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParallel_path_description" ):
                return visitor.visitParallel_path_description(self)
            else:
                return visitor.visitChildren(self)




    def parallel_path_description(self):

        localctx = SystemVerilogParser.Parallel_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 896, self.RULE_parallel_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6647
            self.match(SystemVerilogParser.LP)
            self.state = 6648
            self.specify_input_terminal_descriptor()
            self.state = 6650
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.MINUS or _la==SystemVerilogParser.PLUS:
                self.state = 6649
                self.polarity_operator()


            self.state = 6652
            self.match(SystemVerilogParser.EQGT)
            self.state = 6653
            self.specify_output_terminal_descriptor()
            self.state = 6654
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Full_path_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def list_of_path_inputs(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_path_inputsContext,0)


        def SGT(self):
            return self.getToken(SystemVerilogParser.SGT, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_path_outputsContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def polarity_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Polarity_operatorContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_full_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFull_path_description" ):
                listener.enterFull_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFull_path_description" ):
                listener.exitFull_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFull_path_description" ):
                return visitor.visitFull_path_description(self)
            else:
                return visitor.visitChildren(self)




    def full_path_description(self):

        localctx = SystemVerilogParser.Full_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 898, self.RULE_full_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6656
            self.match(SystemVerilogParser.LP)
            self.state = 6657
            self.list_of_path_inputs()
            self.state = 6659
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.MINUS or _la==SystemVerilogParser.PLUS:
                self.state = 6658
                self.polarity_operator()


            self.state = 6661
            self.match(SystemVerilogParser.SGT)
            self.state = 6662
            self.list_of_path_outputs()
            self.state = 6663
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_path_inputsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specify_input_terminal_descriptor(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Specify_input_terminal_descriptorContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Specify_input_terminal_descriptorContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_path_inputs

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_inputs" ):
                listener.enterList_of_path_inputs(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_inputs" ):
                listener.exitList_of_path_inputs(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_inputs" ):
                return visitor.visitList_of_path_inputs(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_inputs(self):

        localctx = SystemVerilogParser.List_of_path_inputsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 900, self.RULE_list_of_path_inputs)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6665
            self.specify_input_terminal_descriptor()
            self.state = 6670
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6666
                self.match(SystemVerilogParser.COMMA)
                self.state = 6667
                self.specify_input_terminal_descriptor()
                self.state = 6672
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_path_outputsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def specify_output_terminal_descriptor(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Specify_output_terminal_descriptorContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Specify_output_terminal_descriptorContext,i)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_path_outputs

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_outputs" ):
                listener.enterList_of_path_outputs(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_outputs" ):
                listener.exitList_of_path_outputs(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_outputs" ):
                return visitor.visitList_of_path_outputs(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_outputs(self):

        localctx = SystemVerilogParser.List_of_path_outputsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 902, self.RULE_list_of_path_outputs)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6673
            self.specify_output_terminal_descriptor()
            self.state = 6678
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6674
                self.match(SystemVerilogParser.COMMA)
                self.state = 6675
                self.specify_output_terminal_descriptor()
                self.state = 6680
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specify_input_terminal_descriptorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def input_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Input_identifierContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_range_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_specify_input_terminal_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_input_terminal_descriptor" ):
                listener.enterSpecify_input_terminal_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_input_terminal_descriptor" ):
                listener.exitSpecify_input_terminal_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_input_terminal_descriptor" ):
                return visitor.visitSpecify_input_terminal_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def specify_input_terminal_descriptor(self):

        localctx = SystemVerilogParser.Specify_input_terminal_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 904, self.RULE_specify_input_terminal_descriptor)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6681
            self.input_identifier()
            self.state = 6686
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LB:
                self.state = 6682
                self.match(SystemVerilogParser.LB)
                self.state = 6683
                self.constant_range_expression()
                self.state = 6684
                self.match(SystemVerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specify_output_terminal_descriptorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def output_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Output_identifierContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_range_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_specify_output_terminal_descriptor

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecify_output_terminal_descriptor" ):
                listener.enterSpecify_output_terminal_descriptor(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecify_output_terminal_descriptor" ):
                listener.exitSpecify_output_terminal_descriptor(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecify_output_terminal_descriptor" ):
                return visitor.visitSpecify_output_terminal_descriptor(self)
            else:
                return visitor.visitChildren(self)




    def specify_output_terminal_descriptor(self):

        localctx = SystemVerilogParser.Specify_output_terminal_descriptorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 906, self.RULE_specify_output_terminal_descriptor)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6688
            self.output_identifier()
            self.state = 6693
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.LB:
                self.state = 6689
                self.match(SystemVerilogParser.LB)
                self.state = 6690
                self.constant_range_expression()
                self.state = 6691
                self.match(SystemVerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def input_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Input_port_identifierContext,0)


        def inout_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inout_port_identifierContext,0)


        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_input_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_identifier" ):
                listener.enterInput_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_identifier" ):
                listener.exitInput_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_identifier" ):
                return visitor.visitInput_identifier(self)
            else:
                return visitor.visitChildren(self)




    def input_identifier(self):

        localctx = SystemVerilogParser.Input_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 908, self.RULE_input_identifier)
        try:
            self.state = 6701
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,829,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6695
                self.input_port_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6696
                self.inout_port_identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 6697
                self.interface_identifier()
                self.state = 6698
                self.match(SystemVerilogParser.DOT)
                self.state = 6699
                self.port_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def output_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Output_port_identifierContext,0)


        def inout_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inout_port_identifierContext,0)


        def interface_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Interface_identifierContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Port_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_output_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_identifier" ):
                listener.enterOutput_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_identifier" ):
                listener.exitOutput_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_identifier" ):
                return visitor.visitOutput_identifier(self)
            else:
                return visitor.visitChildren(self)




    def output_identifier(self):

        localctx = SystemVerilogParser.Output_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 910, self.RULE_output_identifier)
        try:
            self.state = 6709
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,830,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6703
                self.output_port_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6704
                self.inout_port_identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 6705
                self.interface_identifier()
                self.state = 6706
                self.match(SystemVerilogParser.DOT)
                self.state = 6707
                self.port_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Path_delay_valueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_path_delay_expressions(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_path_delay_expressionsContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_path_delay_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_delay_value" ):
                listener.enterPath_delay_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_delay_value" ):
                listener.exitPath_delay_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_delay_value" ):
                return visitor.visitPath_delay_value(self)
            else:
                return visitor.visitChildren(self)




    def path_delay_value(self):

        localctx = SystemVerilogParser.Path_delay_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 912, self.RULE_path_delay_value)
        try:
            self.state = 6716
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,831,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6711
                self.list_of_path_delay_expressions()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6712
                self.match(SystemVerilogParser.LP)
                self.state = 6713
                self.list_of_path_delay_expressions()
                self.state = 6714
                self.match(SystemVerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_path_delay_expressionsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def t_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.T_path_delay_expressionContext,0)


        def trise_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Trise_path_delay_expressionContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def tfall_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tfall_path_delay_expressionContext,0)


        def tz_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tz_path_delay_expressionContext,0)


        def t01_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.T01_path_delay_expressionContext,0)


        def t10_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.T10_path_delay_expressionContext,0)


        def t0z_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.T0z_path_delay_expressionContext,0)


        def tz1_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tz1_path_delay_expressionContext,0)


        def t1z_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.T1z_path_delay_expressionContext,0)


        def tz0_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tz0_path_delay_expressionContext,0)


        def t0x_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.T0x_path_delay_expressionContext,0)


        def tx1_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tx1_path_delay_expressionContext,0)


        def t1x_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.T1x_path_delay_expressionContext,0)


        def tx0_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tx0_path_delay_expressionContext,0)


        def txz_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Txz_path_delay_expressionContext,0)


        def tzx_path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tzx_path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_path_delay_expressions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_path_delay_expressions" ):
                listener.enterList_of_path_delay_expressions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_path_delay_expressions" ):
                listener.exitList_of_path_delay_expressions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_path_delay_expressions" ):
                return visitor.visitList_of_path_delay_expressions(self)
            else:
                return visitor.visitChildren(self)




    def list_of_path_delay_expressions(self):

        localctx = SystemVerilogParser.List_of_path_delay_expressionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 914, self.RULE_list_of_path_delay_expressions)
        self._la = 0 # Token type
        try:
            self.state = 6752
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,834,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6718
                self.t_path_delay_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6719
                self.trise_path_delay_expression()
                self.state = 6720
                self.match(SystemVerilogParser.COMMA)
                self.state = 6721
                self.tfall_path_delay_expression()
                self.state = 6724
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COMMA:
                    self.state = 6722
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6723
                    self.tz_path_delay_expression()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 6726
                self.t01_path_delay_expression()
                self.state = 6727
                self.match(SystemVerilogParser.COMMA)
                self.state = 6728
                self.t10_path_delay_expression()
                self.state = 6729
                self.match(SystemVerilogParser.COMMA)
                self.state = 6730
                self.t0z_path_delay_expression()
                self.state = 6731
                self.match(SystemVerilogParser.COMMA)
                self.state = 6732
                self.tz1_path_delay_expression()
                self.state = 6733
                self.match(SystemVerilogParser.COMMA)
                self.state = 6734
                self.t1z_path_delay_expression()
                self.state = 6735
                self.match(SystemVerilogParser.COMMA)
                self.state = 6736
                self.tz0_path_delay_expression()
                self.state = 6750
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.COMMA:
                    self.state = 6737
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6738
                    self.t0x_path_delay_expression()
                    self.state = 6739
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6740
                    self.tx1_path_delay_expression()
                    self.state = 6741
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6742
                    self.t1x_path_delay_expression()
                    self.state = 6743
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6744
                    self.tx0_path_delay_expression()
                    self.state = 6745
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6746
                    self.txz_path_delay_expression()
                    self.state = 6747
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 6748
                    self.tzx_path_delay_expression()


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_t_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT_path_delay_expression" ):
                listener.enterT_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT_path_delay_expression" ):
                listener.exitT_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT_path_delay_expression" ):
                return visitor.visitT_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t_path_delay_expression(self):

        localctx = SystemVerilogParser.T_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 916, self.RULE_t_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6754
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Trise_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_trise_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTrise_path_delay_expression" ):
                listener.enterTrise_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTrise_path_delay_expression" ):
                listener.exitTrise_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTrise_path_delay_expression" ):
                return visitor.visitTrise_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def trise_path_delay_expression(self):

        localctx = SystemVerilogParser.Trise_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 918, self.RULE_trise_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6756
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tfall_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tfall_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTfall_path_delay_expression" ):
                listener.enterTfall_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTfall_path_delay_expression" ):
                listener.exitTfall_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTfall_path_delay_expression" ):
                return visitor.visitTfall_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tfall_path_delay_expression(self):

        localctx = SystemVerilogParser.Tfall_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 920, self.RULE_tfall_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6758
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tz_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tz_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz_path_delay_expression" ):
                listener.enterTz_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz_path_delay_expression" ):
                listener.exitTz_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz_path_delay_expression" ):
                return visitor.visitTz_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz_path_delay_expression(self):

        localctx = SystemVerilogParser.Tz_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 922, self.RULE_tz_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6760
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T01_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_t01_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT01_path_delay_expression" ):
                listener.enterT01_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT01_path_delay_expression" ):
                listener.exitT01_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT01_path_delay_expression" ):
                return visitor.visitT01_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t01_path_delay_expression(self):

        localctx = SystemVerilogParser.T01_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 924, self.RULE_t01_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6762
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T10_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_t10_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT10_path_delay_expression" ):
                listener.enterT10_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT10_path_delay_expression" ):
                listener.exitT10_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT10_path_delay_expression" ):
                return visitor.visitT10_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t10_path_delay_expression(self):

        localctx = SystemVerilogParser.T10_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 926, self.RULE_t10_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6764
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T0z_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_t0z_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT0z_path_delay_expression" ):
                listener.enterT0z_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT0z_path_delay_expression" ):
                listener.exitT0z_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT0z_path_delay_expression" ):
                return visitor.visitT0z_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t0z_path_delay_expression(self):

        localctx = SystemVerilogParser.T0z_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 928, self.RULE_t0z_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6766
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tz1_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tz1_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz1_path_delay_expression" ):
                listener.enterTz1_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz1_path_delay_expression" ):
                listener.exitTz1_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz1_path_delay_expression" ):
                return visitor.visitTz1_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz1_path_delay_expression(self):

        localctx = SystemVerilogParser.Tz1_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 930, self.RULE_tz1_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6768
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T1z_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_t1z_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT1z_path_delay_expression" ):
                listener.enterT1z_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT1z_path_delay_expression" ):
                listener.exitT1z_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT1z_path_delay_expression" ):
                return visitor.visitT1z_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t1z_path_delay_expression(self):

        localctx = SystemVerilogParser.T1z_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 932, self.RULE_t1z_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6770
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tz0_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tz0_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTz0_path_delay_expression" ):
                listener.enterTz0_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTz0_path_delay_expression" ):
                listener.exitTz0_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTz0_path_delay_expression" ):
                return visitor.visitTz0_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tz0_path_delay_expression(self):

        localctx = SystemVerilogParser.Tz0_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 934, self.RULE_tz0_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6772
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T0x_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_t0x_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT0x_path_delay_expression" ):
                listener.enterT0x_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT0x_path_delay_expression" ):
                listener.exitT0x_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT0x_path_delay_expression" ):
                return visitor.visitT0x_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t0x_path_delay_expression(self):

        localctx = SystemVerilogParser.T0x_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 936, self.RULE_t0x_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6774
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tx1_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tx1_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTx1_path_delay_expression" ):
                listener.enterTx1_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTx1_path_delay_expression" ):
                listener.exitTx1_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTx1_path_delay_expression" ):
                return visitor.visitTx1_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tx1_path_delay_expression(self):

        localctx = SystemVerilogParser.Tx1_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 938, self.RULE_tx1_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6776
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class T1x_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_t1x_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterT1x_path_delay_expression" ):
                listener.enterT1x_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitT1x_path_delay_expression" ):
                listener.exitT1x_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitT1x_path_delay_expression" ):
                return visitor.visitT1x_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def t1x_path_delay_expression(self):

        localctx = SystemVerilogParser.T1x_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 940, self.RULE_t1x_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6778
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tx0_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tx0_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTx0_path_delay_expression" ):
                listener.enterTx0_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTx0_path_delay_expression" ):
                listener.exitTx0_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTx0_path_delay_expression" ):
                return visitor.visitTx0_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tx0_path_delay_expression(self):

        localctx = SystemVerilogParser.Tx0_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 942, self.RULE_tx0_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6780
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Txz_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_txz_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTxz_path_delay_expression" ):
                listener.enterTxz_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTxz_path_delay_expression" ):
                listener.exitTxz_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTxz_path_delay_expression" ):
                return visitor.visitTxz_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def txz_path_delay_expression(self):

        localctx = SystemVerilogParser.Txz_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 944, self.RULE_txz_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6782
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tzx_path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def path_delay_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tzx_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTzx_path_delay_expression" ):
                listener.enterTzx_path_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTzx_path_delay_expression" ):
                listener.exitTzx_path_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTzx_path_delay_expression" ):
                return visitor.visitTzx_path_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def tzx_path_delay_expression(self):

        localctx = SystemVerilogParser.Tzx_path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 946, self.RULE_tzx_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6784
            self.path_delay_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Path_delay_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_path_delay_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPath_delay_expression" ):
                listener.enterPath_delay_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPath_delay_expression" ):
                listener.exitPath_delay_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPath_delay_expression" ):
                return visitor.visitPath_delay_expression(self)
            else:
                return visitor.visitChildren(self)




    def path_delay_expression(self):

        localctx = SystemVerilogParser.Path_delay_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 948, self.RULE_path_delay_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6786
            self.constant_mintypmax_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Edge_sensitive_path_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def path_delay_value(self):
            return self.getTypedRuleContext(SystemVerilogParser.Path_delay_valueContext,0)


        def parallel_edge_sensitive_path_description(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parallel_edge_sensitive_path_descriptionContext,0)


        def full_edge_sensitive_path_description(self):
            return self.getTypedRuleContext(SystemVerilogParser.Full_edge_sensitive_path_descriptionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_edge_sensitive_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_sensitive_path_declaration" ):
                listener.enterEdge_sensitive_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_sensitive_path_declaration" ):
                listener.exitEdge_sensitive_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_sensitive_path_declaration" ):
                return visitor.visitEdge_sensitive_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def edge_sensitive_path_declaration(self):

        localctx = SystemVerilogParser.Edge_sensitive_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 950, self.RULE_edge_sensitive_path_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6790
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,835,self._ctx)
            if la_ == 1:
                self.state = 6788
                self.parallel_edge_sensitive_path_description()
                pass

            elif la_ == 2:
                self.state = 6789
                self.full_edge_sensitive_path_description()
                pass


            self.state = 6792
            self.match(SystemVerilogParser.EQ)
            self.state = 6793
            self.path_delay_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parallel_edge_sensitive_path_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def specify_input_terminal_descriptor(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specify_input_terminal_descriptorContext,0)


        def EQGT(self):
            return self.getToken(SystemVerilogParser.EQGT, 0)

        def specify_output_terminal_descriptor(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specify_output_terminal_descriptorContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def data_source_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_source_expressionContext,0)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def edge_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Edge_identifierContext,0)


        def polarity_operator(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Polarity_operatorContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Polarity_operatorContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_parallel_edge_sensitive_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParallel_edge_sensitive_path_description" ):
                listener.enterParallel_edge_sensitive_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParallel_edge_sensitive_path_description" ):
                listener.exitParallel_edge_sensitive_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParallel_edge_sensitive_path_description" ):
                return visitor.visitParallel_edge_sensitive_path_description(self)
            else:
                return visitor.visitChildren(self)




    def parallel_edge_sensitive_path_description(self):

        localctx = SystemVerilogParser.Parallel_edge_sensitive_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 952, self.RULE_parallel_edge_sensitive_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6795
            self.match(SystemVerilogParser.LP)
            self.state = 6797
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KEDGE or _la==SystemVerilogParser.KNEGEDGE or _la==SystemVerilogParser.KPOSEDGE:
                self.state = 6796
                self.edge_identifier()


            self.state = 6799
            self.specify_input_terminal_descriptor()
            self.state = 6801
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.MINUS or _la==SystemVerilogParser.PLUS:
                self.state = 6800
                self.polarity_operator()


            self.state = 6803
            self.match(SystemVerilogParser.EQGT)
            self.state = 6804
            self.match(SystemVerilogParser.LP)
            self.state = 6805
            self.specify_output_terminal_descriptor()
            self.state = 6807
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.MINUS or _la==SystemVerilogParser.PLUS:
                self.state = 6806
                self.polarity_operator()


            self.state = 6809
            self.match(SystemVerilogParser.COLON)
            self.state = 6810
            self.data_source_expression()
            self.state = 6811
            self.match(SystemVerilogParser.RP)
            self.state = 6812
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Full_edge_sensitive_path_descriptionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def list_of_path_inputs(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_path_inputsContext,0)


        def SGT(self):
            return self.getToken(SystemVerilogParser.SGT, 0)

        def list_of_path_outputs(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_path_outputsContext,0)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def data_source_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_source_expressionContext,0)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def edge_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Edge_identifierContext,0)


        def polarity_operator(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Polarity_operatorContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Polarity_operatorContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_full_edge_sensitive_path_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFull_edge_sensitive_path_description" ):
                listener.enterFull_edge_sensitive_path_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFull_edge_sensitive_path_description" ):
                listener.exitFull_edge_sensitive_path_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFull_edge_sensitive_path_description" ):
                return visitor.visitFull_edge_sensitive_path_description(self)
            else:
                return visitor.visitChildren(self)




    def full_edge_sensitive_path_description(self):

        localctx = SystemVerilogParser.Full_edge_sensitive_path_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 954, self.RULE_full_edge_sensitive_path_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6814
            self.match(SystemVerilogParser.LP)
            self.state = 6816
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KEDGE or _la==SystemVerilogParser.KNEGEDGE or _la==SystemVerilogParser.KPOSEDGE:
                self.state = 6815
                self.edge_identifier()


            self.state = 6818
            self.list_of_path_inputs()
            self.state = 6820
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.MINUS or _la==SystemVerilogParser.PLUS:
                self.state = 6819
                self.polarity_operator()


            self.state = 6822
            self.match(SystemVerilogParser.SGT)
            self.state = 6823
            self.match(SystemVerilogParser.LP)
            self.state = 6824
            self.list_of_path_outputs()
            self.state = 6826
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.MINUS or _la==SystemVerilogParser.PLUS:
                self.state = 6825
                self.polarity_operator()


            self.state = 6828
            self.match(SystemVerilogParser.COLON)
            self.state = 6829
            self.data_source_expression()
            self.state = 6830
            self.match(SystemVerilogParser.RP)
            self.state = 6831
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Data_source_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_data_source_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterData_source_expression" ):
                listener.enterData_source_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitData_source_expression" ):
                listener.exitData_source_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitData_source_expression" ):
                return visitor.visitData_source_expression(self)
            else:
                return visitor.visitChildren(self)




    def data_source_expression(self):

        localctx = SystemVerilogParser.Data_source_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 956, self.RULE_data_source_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6833
            self.expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Edge_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KPOSEDGE(self):
            return self.getToken(SystemVerilogParser.KPOSEDGE, 0)

        def KNEGEDGE(self):
            return self.getToken(SystemVerilogParser.KNEGEDGE, 0)

        def KEDGE(self):
            return self.getToken(SystemVerilogParser.KEDGE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_edge_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEdge_identifier" ):
                listener.enterEdge_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEdge_identifier" ):
                listener.exitEdge_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEdge_identifier" ):
                return visitor.visitEdge_identifier(self)
            else:
                return visitor.visitChildren(self)




    def edge_identifier(self):

        localctx = SystemVerilogParser.Edge_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 958, self.RULE_edge_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6835
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.KEDGE or _la==SystemVerilogParser.KNEGEDGE or _la==SystemVerilogParser.KPOSEDGE):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class State_dependent_path_declarationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KIF(self):
            return self.getToken(SystemVerilogParser.KIF, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def module_path_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_path_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def simple_path_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_path_declarationContext,0)


        def edge_sensitive_path_declaration(self):
            return self.getTypedRuleContext(SystemVerilogParser.Edge_sensitive_path_declarationContext,0)


        def KIFNONE(self):
            return self.getToken(SystemVerilogParser.KIFNONE, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_state_dependent_path_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterState_dependent_path_declaration" ):
                listener.enterState_dependent_path_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitState_dependent_path_declaration" ):
                listener.exitState_dependent_path_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitState_dependent_path_declaration" ):
                return visitor.visitState_dependent_path_declaration(self)
            else:
                return visitor.visitChildren(self)




    def state_dependent_path_declaration(self):

        localctx = SystemVerilogParser.State_dependent_path_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 960, self.RULE_state_dependent_path_declaration)
        try:
            self.state = 6847
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KIF]:
                self.enterOuterAlt(localctx, 1)
                self.state = 6837
                self.match(SystemVerilogParser.KIF)
                self.state = 6838
                self.match(SystemVerilogParser.LP)
                self.state = 6839
                self.module_path_expression(0)
                self.state = 6840
                self.match(SystemVerilogParser.RP)
                self.state = 6843
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,842,self._ctx)
                if la_ == 1:
                    self.state = 6841
                    self.simple_path_declaration()
                    pass

                elif la_ == 2:
                    self.state = 6842
                    self.edge_sensitive_path_declaration()
                    pass


                pass
            elif token in [SystemVerilogParser.KIFNONE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 6845
                self.match(SystemVerilogParser.KIFNONE)
                self.state = 6846
                self.simple_path_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Polarity_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PLUS(self):
            return self.getToken(SystemVerilogParser.PLUS, 0)

        def MINUS(self):
            return self.getToken(SystemVerilogParser.MINUS, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_polarity_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPolarity_operator" ):
                listener.enterPolarity_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPolarity_operator" ):
                listener.exitPolarity_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPolarity_operator" ):
                return visitor.visitPolarity_operator(self)
            else:
                return visitor.visitChildren(self)




    def polarity_operator(self):

        localctx = SystemVerilogParser.Polarity_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 962, self.RULE_polarity_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6849
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.MINUS or _la==SystemVerilogParser.PLUS):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ConcatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConcatenation" ):
                listener.enterConcatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConcatenation" ):
                listener.exitConcatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConcatenation" ):
                return visitor.visitConcatenation(self)
            else:
                return visitor.visitChildren(self)




    def concatenation(self):

        localctx = SystemVerilogParser.ConcatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 964, self.RULE_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6851
            self.match(SystemVerilogParser.LC)
            self.state = 6852
            self.expression(0)
            self.state = 6857
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6853
                self.match(SystemVerilogParser.COMMA)
                self.state = 6854
                self.expression(0)
                self.state = 6859
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6860
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_concatenation" ):
                listener.enterConstant_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_concatenation" ):
                listener.exitConstant_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_concatenation" ):
                return visitor.visitConstant_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def constant_concatenation(self):

        localctx = SystemVerilogParser.Constant_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 966, self.RULE_constant_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6862
            self.match(SystemVerilogParser.LC)
            self.state = 6863
            self.constant_expression(0)
            self.state = 6868
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6864
                self.match(SystemVerilogParser.COMMA)
                self.state = 6865
                self.constant_expression(0)
                self.state = 6870
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6871
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_multiple_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def constant_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_concatenationContext,0)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_multiple_concatenation" ):
                listener.enterConstant_multiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_multiple_concatenation" ):
                listener.exitConstant_multiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_multiple_concatenation" ):
                return visitor.visitConstant_multiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def constant_multiple_concatenation(self):

        localctx = SystemVerilogParser.Constant_multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 968, self.RULE_constant_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6873
            self.match(SystemVerilogParser.LC)
            self.state = 6874
            self.constant_expression(0)
            self.state = 6875
            self.constant_concatenation()
            self.state = 6876
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_path_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Module_path_expressionContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_path_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_concatenation" ):
                listener.enterModule_path_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_concatenation" ):
                listener.exitModule_path_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_concatenation" ):
                return visitor.visitModule_path_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def module_path_concatenation(self):

        localctx = SystemVerilogParser.Module_path_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 970, self.RULE_module_path_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6878
            self.match(SystemVerilogParser.LC)
            self.state = 6879
            self.module_path_expression(0)
            self.state = 6884
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6880
                self.match(SystemVerilogParser.COMMA)
                self.state = 6881
                self.module_path_expression(0)
                self.state = 6886
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6887
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_path_multiple_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def module_path_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_path_concatenationContext,0)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_path_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_multiple_concatenation" ):
                listener.enterModule_path_multiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_multiple_concatenation" ):
                listener.exitModule_path_multiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_multiple_concatenation" ):
                return visitor.visitModule_path_multiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def module_path_multiple_concatenation(self):

        localctx = SystemVerilogParser.Module_path_multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 972, self.RULE_module_path_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6889
            self.match(SystemVerilogParser.LC)
            self.state = 6890
            self.constant_expression(0)
            self.state = 6891
            self.module_path_concatenation()
            self.state = 6892
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Multiple_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.ConcatenationContext,0)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMultiple_concatenation" ):
                listener.enterMultiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMultiple_concatenation" ):
                listener.exitMultiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMultiple_concatenation" ):
                return visitor.visitMultiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def multiple_concatenation(self):

        localctx = SystemVerilogParser.Multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 974, self.RULE_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6894
            self.match(SystemVerilogParser.LC)
            self.state = 6895
            self.expression(0)
            self.state = 6896
            self.concatenation()
            self.state = 6897
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Streaming_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def stream_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Stream_operatorContext,0)


        def stream_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Stream_concatenationContext,0)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def slice_size(self):
            return self.getTypedRuleContext(SystemVerilogParser.Slice_sizeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_streaming_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStreaming_concatenation" ):
                listener.enterStreaming_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStreaming_concatenation" ):
                listener.exitStreaming_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStreaming_concatenation" ):
                return visitor.visitStreaming_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def streaming_concatenation(self):

        localctx = SystemVerilogParser.Streaming_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 976, self.RULE_streaming_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6899
            self.match(SystemVerilogParser.LC)
            self.state = 6900
            self.stream_operator()
            self.state = 6902
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,847,self._ctx)
            if la_ == 1:
                self.state = 6901
                self.slice_size()


            self.state = 6904
            self.stream_concatenation()
            self.state = 6905
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Stream_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def GTGT(self):
            return self.getToken(SystemVerilogParser.GTGT, 0)

        def LTLT(self):
            return self.getToken(SystemVerilogParser.LTLT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_stream_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStream_operator" ):
                listener.enterStream_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStream_operator" ):
                listener.exitStream_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStream_operator" ):
                return visitor.visitStream_operator(self)
            else:
                return visitor.visitChildren(self)




    def stream_operator(self):

        localctx = SystemVerilogParser.Stream_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 978, self.RULE_stream_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6907
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.LTLT or _la==SystemVerilogParser.GTGT):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Slice_sizeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def simple_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Simple_typeContext,0)


        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_slice_size

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSlice_size" ):
                listener.enterSlice_size(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSlice_size" ):
                listener.exitSlice_size(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSlice_size" ):
                return visitor.visitSlice_size(self)
            else:
                return visitor.visitChildren(self)




    def slice_size(self):

        localctx = SystemVerilogParser.Slice_sizeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 980, self.RULE_slice_size)
        try:
            self.state = 6911
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,848,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6909
                self.simple_type()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6910
                self.constant_expression(0)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Stream_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def stream_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Stream_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Stream_expressionContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_stream_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStream_concatenation" ):
                listener.enterStream_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStream_concatenation" ):
                listener.exitStream_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStream_concatenation" ):
                return visitor.visitStream_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def stream_concatenation(self):

        localctx = SystemVerilogParser.Stream_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 982, self.RULE_stream_concatenation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6913
            self.match(SystemVerilogParser.LC)
            self.state = 6914
            self.stream_expression()
            self.state = 6919
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 6915
                self.match(SystemVerilogParser.COMMA)
                self.state = 6916
                self.stream_expression()
                self.state = 6921
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 6922
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Stream_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def KWITH(self):
            return self.getToken(SystemVerilogParser.KWITH, 0)

        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def array_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Array_range_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_stream_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStream_expression" ):
                listener.enterStream_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStream_expression" ):
                listener.exitStream_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStream_expression" ):
                return visitor.visitStream_expression(self)
            else:
                return visitor.visitChildren(self)




    def stream_expression(self):

        localctx = SystemVerilogParser.Stream_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 984, self.RULE_stream_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6924
            self.expression(0)
            self.state = 6930
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KWITH:
                self.state = 6925
                self.match(SystemVerilogParser.KWITH)
                self.state = 6926
                self.match(SystemVerilogParser.LB)
                self.state = 6927
                self.array_range_expression()
                self.state = 6928
                self.match(SystemVerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Array_range_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def PLUSCOLON(self):
            return self.getToken(SystemVerilogParser.PLUSCOLON, 0)

        def MCOLON(self):
            return self.getToken(SystemVerilogParser.MCOLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_array_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArray_range_expression" ):
                listener.enterArray_range_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArray_range_expression" ):
                listener.exitArray_range_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArray_range_expression" ):
                return visitor.visitArray_range_expression(self)
            else:
                return visitor.visitChildren(self)




    def array_range_expression(self):

        localctx = SystemVerilogParser.Array_range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 986, self.RULE_array_range_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6932
            self.expression(0)
            self.state = 6935
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 41)) & ~0x3f) == 0 and ((1 << (_la - 41)) & ((1 << (SystemVerilogParser.COLON - 41)) | (1 << (SystemVerilogParser.MCOLON - 41)) | (1 << (SystemVerilogParser.PLUSCOLON - 41)))) != 0):
                self.state = 6933
                _la = self._input.LA(1)
                if not(((((_la - 41)) & ~0x3f) == 0 and ((1 << (_la - 41)) & ((1 << (SystemVerilogParser.COLON - 41)) | (1 << (SystemVerilogParser.MCOLON - 41)) | (1 << (SystemVerilogParser.PLUSCOLON - 41)))) != 0)):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()
                self.state = 6934
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Empty_unpacked_array_concatenationContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_empty_unpacked_array_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEmpty_unpacked_array_concatenation" ):
                listener.enterEmpty_unpacked_array_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEmpty_unpacked_array_concatenation" ):
                listener.exitEmpty_unpacked_array_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEmpty_unpacked_array_concatenation" ):
                return visitor.visitEmpty_unpacked_array_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def empty_unpacked_array_concatenation(self):

        localctx = SystemVerilogParser.Empty_unpacked_array_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 988, self.RULE_empty_unpacked_array_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6937
            self.match(SystemVerilogParser.LC)
            self.state = 6938
            self.match(SystemVerilogParser.RC)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_function_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_subroutine_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_subroutine_callContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_function_call" ):
                listener.enterConstant_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_function_call" ):
                listener.exitConstant_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_function_call" ):
                return visitor.visitConstant_function_call(self)
            else:
                return visitor.visitChildren(self)




    def constant_function_call(self):

        localctx = SystemVerilogParser.Constant_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 990, self.RULE_constant_function_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6940
            self.function_subroutine_call()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ps_or_hierarchical_tf_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_or_hierarchical_tf_identifierContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tf_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_call" ):
                listener.enterTf_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_call" ):
                listener.exitTf_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_call" ):
                return visitor.visitTf_call(self)
            else:
                return visitor.visitChildren(self)




    def tf_call(self):

        localctx = SystemVerilogParser.Tf_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 992, self.RULE_tf_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6942
            self.ps_or_hierarchical_tf_identifier()
            self.state = 6946
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,852,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 6943
                    self.attribute_instance() 
                self.state = 6948
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,852,self._ctx)

            self.state = 6953
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,853,self._ctx)
            if la_ == 1:
                self.state = 6949
                self.match(SystemVerilogParser.LP)
                self.state = 6950
                self.list_of_arguments()
                self.state = 6951
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_tf_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SYSTEM_TF_IDENTIFIER(self):
            return self.getToken(SystemVerilogParser.SYSTEM_TF_IDENTIFIER, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def clocking_event(self):
            return self.getTypedRuleContext(SystemVerilogParser.Clocking_eventContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_system_tf_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_tf_call" ):
                listener.enterSystem_tf_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_tf_call" ):
                listener.exitSystem_tf_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_tf_call" ):
                return visitor.visitSystem_tf_call(self)
            else:
                return visitor.visitChildren(self)




    def system_tf_call(self):

        localctx = SystemVerilogParser.System_tf_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 994, self.RULE_system_tf_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 6955
            self.match(SystemVerilogParser.SYSTEM_TF_IDENTIFIER)
            self.state = 6988
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,861,self._ctx)
            if la_ == 1:
                self.state = 6960
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,854,self._ctx)
                if la_ == 1:
                    self.state = 6956
                    self.match(SystemVerilogParser.LP)
                    self.state = 6957
                    self.list_of_arguments()
                    self.state = 6958
                    self.match(SystemVerilogParser.RP)


                pass

            elif la_ == 2:
                self.state = 6962
                self.match(SystemVerilogParser.LP)
                self.state = 6984
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,860,self._ctx)
                if la_ == 1:
                    self.state = 6963
                    self.data_type()
                    self.state = 6966
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.COMMA:
                        self.state = 6964
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 6965
                        self.expression(0)


                    pass

                elif la_ == 2:
                    self.state = 6968
                    self.expression(0)
                    self.state = 6975
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,857,self._ctx)
                    while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                        if _alt==1:
                            self.state = 6969
                            self.match(SystemVerilogParser.COMMA)
                            self.state = 6971
                            self._errHandler.sync(self)
                            _la = self._input.LA(1)
                            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                                self.state = 6970
                                self.expression(0)

                     
                        self.state = 6977
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,857,self._ctx)

                    self.state = 6982
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.COMMA:
                        self.state = 6978
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 6980
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if _la==SystemVerilogParser.AT:
                            self.state = 6979
                            self.clocking_event()




                    pass


                self.state = 6986
                self.match(SystemVerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Subroutine_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def tf_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_callContext,0)


        def system_tf_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.System_tf_callContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def method_call_body(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_call_bodyContext,0)


        def primary_literal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Primary_literalContext,0)


        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def select_(self):
            return self.getTypedRuleContext(SystemVerilogParser.Select_Context,0)


        def empty_unpacked_array_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Empty_unpacked_array_concatenationContext,0)


        def concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.ConcatenationContext,0)


        def multiple_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Multiple_concatenationContext,0)


        def let_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_expressionContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def assignment_pattern_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_expressionContext,0)


        def streaming_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Streaming_concatenationContext,0)


        def sequence_method_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_method_callContext,0)


        def KTHIS(self):
            return self.getToken(SystemVerilogParser.KTHIS, 0)

        def DOLLAR(self):
            return self.getToken(SystemVerilogParser.DOLLAR, 0)

        def KNULL(self):
            return self.getToken(SystemVerilogParser.KNULL, 0)

        def implicit_class_handle(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_class_handleContext,0)


        def class_qualifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_qualifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Range_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def randomize_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Randomize_callContext,0)


        def KSTD(self):
            return self.getToken(SystemVerilogParser.KSTD, 0)

        def COLONCOLON(self):
            return self.getToken(SystemVerilogParser.COLONCOLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_subroutine_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSubroutine_call" ):
                listener.enterSubroutine_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSubroutine_call" ):
                listener.exitSubroutine_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSubroutine_call" ):
                return visitor.visitSubroutine_call(self)
            else:
                return visitor.visitChildren(self)




    def subroutine_call(self):

        localctx = SystemVerilogParser.Subroutine_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 996, self.RULE_subroutine_call)
        self._la = 0 # Token type
        try:
            self.state = 7036
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,867,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 6990
                self.tf_call()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 6991
                self.system_tf_call()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 7027
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,865,self._ctx)
                if la_ == 1:
                    self.state = 6992
                    self.primary_literal()
                    pass

                elif la_ == 2:
                    self.state = 6995
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,862,self._ctx)
                    if la_ == 1:
                        self.state = 6993
                        self.class_qualifier()

                    elif la_ == 2:
                        self.state = 6994
                        self.package_scope()


                    self.state = 6997
                    self.hierarchical_identifier()
                    self.state = 6998
                    self.select_()
                    pass

                elif la_ == 3:
                    self.state = 7000
                    self.empty_unpacked_array_concatenation()
                    pass

                elif la_ == 4:
                    self.state = 7001
                    self.concatenation()
                    self.state = 7006
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.LB:
                        self.state = 7002
                        self.match(SystemVerilogParser.LB)
                        self.state = 7003
                        self.range_expression()
                        self.state = 7004
                        self.match(SystemVerilogParser.RB)


                    pass

                elif la_ == 5:
                    self.state = 7008
                    self.multiple_concatenation()
                    self.state = 7013
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.LB:
                        self.state = 7009
                        self.match(SystemVerilogParser.LB)
                        self.state = 7010
                        self.range_expression()
                        self.state = 7011
                        self.match(SystemVerilogParser.RB)


                    pass

                elif la_ == 6:
                    self.state = 7015
                    self.let_expression()
                    pass

                elif la_ == 7:
                    self.state = 7016
                    self.match(SystemVerilogParser.LP)
                    self.state = 7017
                    self.mintypmax_expression()
                    self.state = 7018
                    self.match(SystemVerilogParser.RP)
                    pass

                elif la_ == 8:
                    self.state = 7020
                    self.assignment_pattern_expression()
                    pass

                elif la_ == 9:
                    self.state = 7021
                    self.streaming_concatenation()
                    pass

                elif la_ == 10:
                    self.state = 7022
                    self.sequence_method_call()
                    pass

                elif la_ == 11:
                    self.state = 7023
                    self.match(SystemVerilogParser.KTHIS)
                    pass

                elif la_ == 12:
                    self.state = 7024
                    self.match(SystemVerilogParser.DOLLAR)
                    pass

                elif la_ == 13:
                    self.state = 7025
                    self.match(SystemVerilogParser.KNULL)
                    pass

                elif la_ == 14:
                    self.state = 7026
                    self.implicit_class_handle()
                    pass


                self.state = 7029
                self.match(SystemVerilogParser.DOT)
                self.state = 7030
                self.method_call_body()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 7033
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.KSTD:
                    self.state = 7031
                    self.match(SystemVerilogParser.KSTD)
                    self.state = 7032
                    self.match(SystemVerilogParser.COLONCOLON)


                self.state = 7035
                self.randomize_call()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_subroutine_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def subroutine_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Subroutine_callContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_function_subroutine_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_subroutine_call" ):
                listener.enterFunction_subroutine_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_subroutine_call" ):
                listener.exitFunction_subroutine_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_subroutine_call" ):
                return visitor.visitFunction_subroutine_call(self)
            else:
                return visitor.visitChildren(self)




    def function_subroutine_call(self):

        localctx = SystemVerilogParser.Function_subroutine_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 998, self.RULE_function_subroutine_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7038
            self.subroutine_call()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_argumentsContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.IdentifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,i)


        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_list_of_arguments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_arguments" ):
                listener.enterList_of_arguments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_arguments" ):
                listener.exitList_of_arguments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_arguments" ):
                return visitor.visitList_of_arguments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_arguments(self):

        localctx = SystemVerilogParser.List_of_argumentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1000, self.RULE_list_of_arguments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7060
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.RP, SystemVerilogParser.COMMA, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.state = 7041
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 7040
                    self.expression(0)


                self.state = 7049
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,870,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 7043
                        self.match(SystemVerilogParser.COMMA)
                        self.state = 7045
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                            self.state = 7044
                            self.expression(0)

                 
                    self.state = 7051
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,870,self._ctx)

                pass
            elif token in [SystemVerilogParser.DOT]:
                self.state = 7052
                self.match(SystemVerilogParser.DOT)
                self.state = 7053
                self.identifier()
                self.state = 7054
                self.match(SystemVerilogParser.LP)
                self.state = 7056
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 7055
                    self.expression(0)


                self.state = 7058
                self.match(SystemVerilogParser.RP)
                pass
            else:
                raise NoViableAltException(self)

            self.state = 7073
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 7062
                self.match(SystemVerilogParser.COMMA)
                self.state = 7063
                self.match(SystemVerilogParser.DOT)
                self.state = 7064
                self.identifier()
                self.state = 7065
                self.match(SystemVerilogParser.LP)
                self.state = 7067
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.DOLLAR) | (1 << SystemVerilogParser.DROOT) | (1 << SystemVerilogParser.DUNIT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.LP) | (1 << SystemVerilogParser.QUOTE) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.LC) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)) | (1 << (SystemVerilogParser.PLUSPLUS - 64)) | (1 << (SystemVerilogParser.KBIT - 64)) | (1 << (SystemVerilogParser.KBYTE - 64)) | (1 << (SystemVerilogParser.KCONST - 64)))) != 0) or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLOGIC - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)) | (1 << (SystemVerilogParser.KNULL - 195)) | (1 << (SystemVerilogParser.KRANDOMIZE - 195)) | (1 << (SystemVerilogParser.KREAL - 195)) | (1 << (SystemVerilogParser.KREALTIME - 195)) | (1 << (SystemVerilogParser.KREG - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KSHORTREAL - 276)) | (1 << (SystemVerilogParser.KSIGNED - 276)) | (1 << (SystemVerilogParser.KSTD - 276)) | (1 << (SystemVerilogParser.KSTRING - 276)) | (1 << (SystemVerilogParser.KSUPER - 276)) | (1 << (SystemVerilogParser.KTAGGED - 276)) | (1 << (SystemVerilogParser.KTHIS - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)) | (1 << (SystemVerilogParser.KUNSIGNED - 276)))) != 0) or ((((_la - 345)) & ~0x3f) == 0 and ((1 << (_la - 345)) & ((1 << (SystemVerilogParser.TIME_LITERAL - 345)) | (1 << (SystemVerilogParser.DECIMAL_NUMBER - 345)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 345)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 345)) | (1 << (SystemVerilogParser.HEX_NUMBER - 345)) | (1 << (SystemVerilogParser.REAL_NUMBER - 345)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 345)) | (1 << (SystemVerilogParser.STRING_LITERAL - 345)) | (1 << (SystemVerilogParser.SIMPLE_IDENTIFIER - 345)) | (1 << (SystemVerilogParser.SYSTEM_TF_IDENTIFIER - 345)))) != 0):
                    self.state = 7066
                    self.expression(0)


                self.state = 7069
                self.match(SystemVerilogParser.RP)
                self.state = 7075
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Method_call_bodyContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def method_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_identifierContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def built_in_method_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Built_in_method_callContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_method_call_body

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMethod_call_body" ):
                listener.enterMethod_call_body(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMethod_call_body" ):
                listener.exitMethod_call_body(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMethod_call_body" ):
                return visitor.visitMethod_call_body(self)
            else:
                return visitor.visitChildren(self)




    def method_call_body(self):

        localctx = SystemVerilogParser.Method_call_bodyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1002, self.RULE_method_call_body)
        try:
            self.state = 7090
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,877,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7076
                self.method_identifier()
                self.state = 7080
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,875,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 7077
                        self.attribute_instance() 
                    self.state = 7082
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,875,self._ctx)

                self.state = 7087
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,876,self._ctx)
                if la_ == 1:
                    self.state = 7083
                    self.match(SystemVerilogParser.LP)
                    self.state = 7084
                    self.list_of_arguments()
                    self.state = 7085
                    self.match(SystemVerilogParser.RP)


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7089
                self.built_in_method_call()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Built_in_method_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def array_manipulation_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Array_manipulation_callContext,0)


        def randomize_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Randomize_callContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_built_in_method_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBuilt_in_method_call" ):
                listener.enterBuilt_in_method_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBuilt_in_method_call" ):
                listener.exitBuilt_in_method_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBuilt_in_method_call" ):
                return visitor.visitBuilt_in_method_call(self)
            else:
                return visitor.visitChildren(self)




    def built_in_method_call(self):

        localctx = SystemVerilogParser.Built_in_method_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1004, self.RULE_built_in_method_call)
        try:
            self.state = 7094
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KAND, SystemVerilogParser.KOR, SystemVerilogParser.KUNIQUE, SystemVerilogParser.KXOR, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 7092
                self.array_manipulation_call()
                pass
            elif token in [SystemVerilogParser.KRANDOMIZE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 7093
                self.randomize_call()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Array_manipulation_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def array_method_name(self):
            return self.getTypedRuleContext(SystemVerilogParser.Array_method_nameContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def list_of_arguments(self):
            return self.getTypedRuleContext(SystemVerilogParser.List_of_argumentsContext,0)


        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def KWITH(self):
            return self.getToken(SystemVerilogParser.KWITH, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_array_manipulation_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArray_manipulation_call" ):
                listener.enterArray_manipulation_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArray_manipulation_call" ):
                listener.exitArray_manipulation_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArray_manipulation_call" ):
                return visitor.visitArray_manipulation_call(self)
            else:
                return visitor.visitChildren(self)




    def array_manipulation_call(self):

        localctx = SystemVerilogParser.Array_manipulation_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1006, self.RULE_array_manipulation_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7096
            self.array_method_name()
            self.state = 7100
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,879,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 7097
                    self.attribute_instance() 
                self.state = 7102
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,879,self._ctx)

            self.state = 7107
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,880,self._ctx)
            if la_ == 1:
                self.state = 7103
                self.match(SystemVerilogParser.LP)
                self.state = 7104
                self.list_of_arguments()
                self.state = 7105
                self.match(SystemVerilogParser.RP)


            self.state = 7114
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,881,self._ctx)
            if la_ == 1:
                self.state = 7109
                self.match(SystemVerilogParser.KWITH)
                self.state = 7110
                self.match(SystemVerilogParser.LP)
                self.state = 7111
                self.expression(0)
                self.state = 7112
                self.match(SystemVerilogParser.RP)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Randomize_callContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KRANDOMIZE(self):
            return self.getToken(SystemVerilogParser.KRANDOMIZE, 0)

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def LP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LP)
            else:
                return self.getToken(SystemVerilogParser.LP, i)

        def RP(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RP)
            else:
                return self.getToken(SystemVerilogParser.RP, i)

        def KWITH(self):
            return self.getToken(SystemVerilogParser.KWITH, 0)

        def constraint_block(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constraint_blockContext,0)


        def variable_identifier_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_identifier_listContext,0)


        def KNULL(self):
            return self.getToken(SystemVerilogParser.KNULL, 0)

        def identifier_list(self):
            return self.getTypedRuleContext(SystemVerilogParser.Identifier_listContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_randomize_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRandomize_call" ):
                listener.enterRandomize_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRandomize_call" ):
                listener.exitRandomize_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRandomize_call" ):
                return visitor.visitRandomize_call(self)
            else:
                return visitor.visitChildren(self)




    def randomize_call(self):

        localctx = SystemVerilogParser.Randomize_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1008, self.RULE_randomize_call)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7116
            self.match(SystemVerilogParser.KRANDOMIZE)
            self.state = 7120
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,882,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 7117
                    self.attribute_instance() 
                self.state = 7122
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,882,self._ctx)

            self.state = 7129
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,884,self._ctx)
            if la_ == 1:
                self.state = 7123
                self.match(SystemVerilogParser.LP)
                self.state = 7126
                self._errHandler.sync(self)
                token = self._input.LA(1)
                if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                    self.state = 7124
                    self.variable_identifier_list()
                    pass
                elif token in [SystemVerilogParser.KNULL]:
                    self.state = 7125
                    self.match(SystemVerilogParser.KNULL)
                    pass
                elif token in [SystemVerilogParser.RP]:
                    pass
                else:
                    pass
                self.state = 7128
                self.match(SystemVerilogParser.RP)


            self.state = 7140
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,887,self._ctx)
            if la_ == 1:
                self.state = 7131
                self.match(SystemVerilogParser.KWITH)
                self.state = 7137
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.LP:
                    self.state = 7132
                    self.match(SystemVerilogParser.LP)
                    self.state = 7134
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                        self.state = 7133
                        self.identifier_list()


                    self.state = 7136
                    self.match(SystemVerilogParser.RP)


                self.state = 7139
                self.constraint_block()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Array_method_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def method_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Method_identifierContext,0)


        def KUNIQUE(self):
            return self.getToken(SystemVerilogParser.KUNIQUE, 0)

        def KAND(self):
            return self.getToken(SystemVerilogParser.KAND, 0)

        def KOR(self):
            return self.getToken(SystemVerilogParser.KOR, 0)

        def KXOR(self):
            return self.getToken(SystemVerilogParser.KXOR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_array_method_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArray_method_name" ):
                listener.enterArray_method_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArray_method_name" ):
                listener.exitArray_method_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArray_method_name" ):
                return visitor.visitArray_method_name(self)
            else:
                return visitor.visitChildren(self)




    def array_method_name(self):

        localctx = SystemVerilogParser.Array_method_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1010, self.RULE_array_method_name)
        try:
            self.state = 7147
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 7142
                self.method_identifier()
                pass
            elif token in [SystemVerilogParser.KUNIQUE]:
                self.enterOuterAlt(localctx, 2)
                self.state = 7143
                self.match(SystemVerilogParser.KUNIQUE)
                pass
            elif token in [SystemVerilogParser.KAND]:
                self.enterOuterAlt(localctx, 3)
                self.state = 7144
                self.match(SystemVerilogParser.KAND)
                pass
            elif token in [SystemVerilogParser.KOR]:
                self.enterOuterAlt(localctx, 4)
                self.state = 7145
                self.match(SystemVerilogParser.KOR)
                pass
            elif token in [SystemVerilogParser.KXOR]:
                self.enterOuterAlt(localctx, 5)
                self.state = 7146
                self.match(SystemVerilogParser.KXOR)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inc_or_dec_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def inc_or_dec_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inc_or_dec_operatorContext,0)


        def variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_inc_or_dec_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInc_or_dec_expression" ):
                listener.enterInc_or_dec_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInc_or_dec_expression" ):
                listener.exitInc_or_dec_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInc_or_dec_expression" ):
                return visitor.visitInc_or_dec_expression(self)
            else:
                return visitor.visitChildren(self)




    def inc_or_dec_expression(self):

        localctx = SystemVerilogParser.Inc_or_dec_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1012, self.RULE_inc_or_dec_expression)
        self._la = 0 # Token type
        try:
            self.state = 7167
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUSMINS, SystemVerilogParser.PLUSPLUS]:
                self.enterOuterAlt(localctx, 1)
                self.state = 7149
                self.inc_or_dec_operator()
                self.state = 7153
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 7150
                    self.attribute_instance()
                    self.state = 7155
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 7156
                self.variable_lvalue()
                pass
            elif token in [SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.QUOTE, SystemVerilogParser.LC, SystemVerilogParser.KBYTE, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLONGINT, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSUPER, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 7158
                self.variable_lvalue()
                self.state = 7162
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 7159
                    self.attribute_instance()
                    self.state = 7164
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 7165
                self.inc_or_dec_operator()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_primary(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_primaryContext,0)


        def unary_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unary_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def binary_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Binary_operatorContext,0)


        def QUES(self):
            return self.getToken(SystemVerilogParser.QUES, 0)

        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_expression" ):
                listener.enterConstant_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_expression" ):
                listener.exitConstant_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_expression" ):
                return visitor.visitConstant_expression(self)
            else:
                return visitor.visitChildren(self)



    def constant_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = SystemVerilogParser.Constant_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 1014
        self.enterRecursionRule(localctx, 1014, self.RULE_constant_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7177
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)))) != 0):
                self.state = 7170
                self.unary_operator()
                self.state = 7174
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 7171
                    self.attribute_instance()
                    self.state = 7176
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



            self.state = 7179
            self.constant_primary()
            self._ctx.stop = self._input.LT(-1)
            self.state = 7205
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,897,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    localctx = SystemVerilogParser.Constant_expressionContext(self, _parentctx, _parentState)
                    self.pushNewRecursionContext(localctx, _startState, self.RULE_constant_expression)
                    self.state = 7181
                    if not self.precpred(self._ctx, 1):
                        from antlr4.error.Errors import FailedPredicateException
                        raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                    self.state = 7199
                    self._errHandler.sync(self)
                    token = self._input.LA(1)
                    if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NE, SystemVerilogParser.NEQ, SystemVerilogParser.NEE, SystemVerilogParser.PER, SystemVerilogParser.AND, SystemVerilogParser.ANDAND, SystemVerilogParser.STAR, SystemVerilogParser.SS, SystemVerilogParser.SLASH, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.BAR, SystemVerilogParser.BARBAR, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.LT, SystemVerilogParser.LTLT, SystemVerilogParser.LTLTLT, SystemVerilogParser.LTEQ, SystemVerilogParser.LTMINUSGT, SystemVerilogParser.EQEQ, SystemVerilogParser.EQEQQUEST, SystemVerilogParser.EQEQEQ, SystemVerilogParser.GT, SystemVerilogParser.ARROW, SystemVerilogParser.GE, SystemVerilogParser.GTGT, SystemVerilogParser.GTGTGT]:
                        self.state = 7182
                        self.binary_operator()
                        self.state = 7186
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        while _la==SystemVerilogParser.LPS:
                            self.state = 7183
                            self.attribute_instance()
                            self.state = 7188
                            self._errHandler.sync(self)
                            _la = self._input.LA(1)

                        pass
                    elif token in [SystemVerilogParser.QUES]:
                        self.state = 7189
                        self.match(SystemVerilogParser.QUES)
                        self.state = 7193
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        while _la==SystemVerilogParser.LPS:
                            self.state = 7190
                            self.attribute_instance()
                            self.state = 7195
                            self._errHandler.sync(self)
                            _la = self._input.LA(1)

                        self.state = 7196
                        self.constant_expression(0)
                        self.state = 7197
                        self.match(SystemVerilogParser.COLON)
                        pass
                    else:
                        raise NoViableAltException(self)

                    self.state = 7201
                    self.constant_expression(2) 
                self.state = 7207
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,897,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Constant_mintypmax_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLON)
            else:
                return self.getToken(SystemVerilogParser.COLON, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_mintypmax_expression" ):
                listener.enterConstant_mintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_mintypmax_expression" ):
                listener.exitConstant_mintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_mintypmax_expression" ):
                return visitor.visitConstant_mintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_mintypmax_expression(self):

        localctx = SystemVerilogParser.Constant_mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1016, self.RULE_constant_mintypmax_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7208
            self.constant_expression(0)
            self.state = 7214
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 7209
                self.match(SystemVerilogParser.COLON)
                self.state = 7210
                self.constant_expression(0)
                self.state = 7211
                self.match(SystemVerilogParser.COLON)
                self.state = 7212
                self.constant_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_param_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_mintypmax_expressionContext,0)


        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def DOLLAR(self):
            return self.getToken(SystemVerilogParser.DOLLAR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_param_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_param_expression" ):
                listener.enterConstant_param_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_param_expression" ):
                listener.exitConstant_param_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_param_expression" ):
                return visitor.visitConstant_param_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_param_expression(self):

        localctx = SystemVerilogParser.Constant_param_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1018, self.RULE_constant_param_expression)
        try:
            self.state = 7219
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,899,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7216
                self.constant_mintypmax_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7217
                self.data_type()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 7218
                self.match(SystemVerilogParser.DOLLAR)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Param_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Mintypmax_expressionContext,0)


        def data_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Data_typeContext,0)


        def DOLLAR(self):
            return self.getToken(SystemVerilogParser.DOLLAR, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_param_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParam_expression" ):
                listener.enterParam_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParam_expression" ):
                listener.exitParam_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParam_expression" ):
                return visitor.visitParam_expression(self)
            else:
                return visitor.visitChildren(self)




    def param_expression(self):

        localctx = SystemVerilogParser.Param_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1020, self.RULE_param_expression)
        try:
            self.state = 7224
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,900,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7221
                self.mintypmax_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7222
                self.data_type()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 7223
                self.match(SystemVerilogParser.DOLLAR)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_range_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def constant_part_select_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_part_select_rangeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_range_expression" ):
                listener.enterConstant_range_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_range_expression" ):
                listener.exitConstant_range_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_range_expression" ):
                return visitor.visitConstant_range_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_range_expression(self):

        localctx = SystemVerilogParser.Constant_range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1022, self.RULE_constant_range_expression)
        try:
            self.state = 7228
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,901,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7226
                self.constant_expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7227
                self.constant_part_select_range()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_part_select_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_rangeContext,0)


        def constant_indexed_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_indexed_rangeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_part_select_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_part_select_range" ):
                listener.enterConstant_part_select_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_part_select_range" ):
                listener.exitConstant_part_select_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_part_select_range" ):
                return visitor.visitConstant_part_select_range(self)
            else:
                return visitor.visitChildren(self)




    def constant_part_select_range(self):

        localctx = SystemVerilogParser.Constant_part_select_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1024, self.RULE_constant_part_select_range)
        try:
            self.state = 7232
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,902,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7230
                self.constant_range()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7231
                self.constant_indexed_range()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_range" ):
                listener.enterConstant_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_range" ):
                listener.exitConstant_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_range" ):
                return visitor.visitConstant_range(self)
            else:
                return visitor.visitChildren(self)




    def constant_range(self):

        localctx = SystemVerilogParser.Constant_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1026, self.RULE_constant_range)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7234
            self.constant_expression(0)
            self.state = 7235
            self.match(SystemVerilogParser.COLON)
            self.state = 7236
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_indexed_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def PLUSCOLON(self):
            return self.getToken(SystemVerilogParser.PLUSCOLON, 0)

        def MCOLON(self):
            return self.getToken(SystemVerilogParser.MCOLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_indexed_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_indexed_range" ):
                listener.enterConstant_indexed_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_indexed_range" ):
                listener.exitConstant_indexed_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_indexed_range" ):
                return visitor.visitConstant_indexed_range(self)
            else:
                return visitor.visitChildren(self)




    def constant_indexed_range(self):

        localctx = SystemVerilogParser.Constant_indexed_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1028, self.RULE_constant_indexed_range)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7238
            self.constant_expression(0)
            self.state = 7239
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.MCOLON or _la==SystemVerilogParser.PLUSCOLON):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 7240
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ExpressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def primary(self):
            return self.getTypedRuleContext(SystemVerilogParser.PrimaryContext,0)


        def unary_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unary_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def inc_or_dec_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Inc_or_dec_expressionContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,0)


        def assignment_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_operatorContext,0)


        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def KTAGGED(self):
            return self.getToken(SystemVerilogParser.KTAGGED, 0)

        def member_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Member_identifierContext,0)


        def binary_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Binary_operatorContext,0)


        def QUES(self):
            return self.getToken(SystemVerilogParser.QUES, 0)

        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def ANDANDAND(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.ANDANDAND)
            else:
                return self.getToken(SystemVerilogParser.ANDANDAND, i)

        def KINSIDE(self):
            return self.getToken(SystemVerilogParser.KINSIDE, 0)

        def open_range_list(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Open_range_listContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Open_range_listContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExpression" ):
                listener.enterExpression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExpression" ):
                listener.exitExpression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExpression" ):
                return visitor.visitExpression(self)
            else:
                return visitor.visitChildren(self)



    def expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = SystemVerilogParser.ExpressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 1030
        self.enterRecursionRule(localctx, 1030, self.RULE_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7265
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,906,self._ctx)
            if la_ == 1:
                self.state = 7250
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)))) != 0):
                    self.state = 7243
                    self.unary_operator()
                    self.state = 7247
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    while _la==SystemVerilogParser.LPS:
                        self.state = 7244
                        self.attribute_instance()
                        self.state = 7249
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)



                self.state = 7252
                self.primary()
                pass

            elif la_ == 2:
                self.state = 7253
                self.inc_or_dec_expression()
                pass

            elif la_ == 3:
                self.state = 7254
                self.match(SystemVerilogParser.LP)
                self.state = 7255
                self.variable_lvalue()
                self.state = 7256
                self.assignment_operator()
                self.state = 7257
                self.expression(0)
                self.state = 7258
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 4:
                self.state = 7260
                self.match(SystemVerilogParser.KTAGGED)
                self.state = 7261
                self.member_identifier()
                self.state = 7263
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,905,self._ctx)
                if la_ == 1:
                    self.state = 7262
                    self.expression(0)


                pass


            self._ctx.stop = self._input.LT(-1)
            self.state = 7306
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,912,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 7304
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,911,self._ctx)
                    if la_ == 1:
                        localctx = SystemVerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 7267
                        if not self.precpred(self._ctx, 4):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 4)")
                        self.state = 7268
                        self.binary_operator()
                        self.state = 7272
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        while _la==SystemVerilogParser.LPS:
                            self.state = 7269
                            self.attribute_instance()
                            self.state = 7274
                            self._errHandler.sync(self)
                            _la = self._input.LA(1)

                        self.state = 7275
                        self.expression(5)
                        pass

                    elif la_ == 2:
                        localctx = SystemVerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 7277
                        if not self.precpred(self._ctx, 3):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 3)")
                        self.state = 7282
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        while _la==SystemVerilogParser.ANDANDAND:
                            self.state = 7278
                            self.match(SystemVerilogParser.ANDANDAND)
                            self.state = 7279
                            self.expression(0)
                            self.state = 7284
                            self._errHandler.sync(self)
                            _la = self._input.LA(1)

                        self.state = 7285
                        self.match(SystemVerilogParser.QUES)
                        self.state = 7289
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        while _la==SystemVerilogParser.LPS:
                            self.state = 7286
                            self.attribute_instance()
                            self.state = 7291
                            self._errHandler.sync(self)
                            _la = self._input.LA(1)

                        self.state = 7292
                        self.expression(0)
                        self.state = 7293
                        self.match(SystemVerilogParser.COLON)
                        self.state = 7294
                        self.expression(4)
                        pass

                    elif la_ == 3:
                        localctx = SystemVerilogParser.ExpressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_expression)
                        self.state = 7296
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 7297
                        self.match(SystemVerilogParser.KINSIDE)
                        self.state = 7301
                        self._errHandler.sync(self)
                        _alt = self._interp.adaptivePredict(self._input,910,self._ctx)
                        while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                            if _alt==1:
                                self.state = 7298
                                self.open_range_list() 
                            self.state = 7303
                            self._errHandler.sync(self)
                            _alt = self._interp.adaptivePredict(self._input,910,self._ctx)

                        pass

             
                self.state = 7308
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,912,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Value_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_value_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterValue_range" ):
                listener.enterValue_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitValue_range" ):
                listener.exitValue_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitValue_range" ):
                return visitor.visitValue_range(self)
            else:
                return visitor.visitChildren(self)




    def value_range(self):

        localctx = SystemVerilogParser.Value_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1032, self.RULE_value_range)
        try:
            self.state = 7316
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.MINUS, SystemVerilogParser.MINUSMINS, SystemVerilogParser.NOT, SystemVerilogParser.DOLLAR, SystemVerilogParser.DROOT, SystemVerilogParser.DUNIT, SystemVerilogParser.AND, SystemVerilogParser.LP, SystemVerilogParser.QUOTE, SystemVerilogParser.CARET, SystemVerilogParser.CARETSQUIG, SystemVerilogParser.LC, SystemVerilogParser.BAR, SystemVerilogParser.SQUIG, SystemVerilogParser.SQUIGAND, SystemVerilogParser.SQUIGCARET, SystemVerilogParser.SQUIGBAR, SystemVerilogParser.PLUS, SystemVerilogParser.PLUSPLUS, SystemVerilogParser.KBIT, SystemVerilogParser.KBYTE, SystemVerilogParser.KCONST, SystemVerilogParser.KINT, SystemVerilogParser.KINTEGER, SystemVerilogParser.KLOCAL, SystemVerilogParser.KLOGIC, SystemVerilogParser.KLONGINT, SystemVerilogParser.KNULL, SystemVerilogParser.KRANDOMIZE, SystemVerilogParser.KREAL, SystemVerilogParser.KREALTIME, SystemVerilogParser.KREG, SystemVerilogParser.KSHORTINT, SystemVerilogParser.KSHORTREAL, SystemVerilogParser.KSIGNED, SystemVerilogParser.KSTD, SystemVerilogParser.KSTRING, SystemVerilogParser.KSUPER, SystemVerilogParser.KTAGGED, SystemVerilogParser.KTHIS, SystemVerilogParser.KTIME, SystemVerilogParser.KTYPE, SystemVerilogParser.KUNSIGNED, SystemVerilogParser.TIME_LITERAL, SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER, SystemVerilogParser.STRING_LITERAL, SystemVerilogParser.SIMPLE_IDENTIFIER, SystemVerilogParser.SYSTEM_TF_IDENTIFIER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 7309
                self.expression(0)
                pass
            elif token in [SystemVerilogParser.LB]:
                self.enterOuterAlt(localctx, 2)
                self.state = 7310
                self.match(SystemVerilogParser.LB)
                self.state = 7311
                self.expression(0)
                self.state = 7312
                self.match(SystemVerilogParser.COLON)
                self.state = 7313
                self.expression(0)
                self.state = 7314
                self.match(SystemVerilogParser.RB)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mintypmax_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLON)
            else:
                return self.getToken(SystemVerilogParser.COLON, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMintypmax_expression" ):
                listener.enterMintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMintypmax_expression" ):
                listener.exitMintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMintypmax_expression" ):
                return visitor.visitMintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def mintypmax_expression(self):

        localctx = SystemVerilogParser.Mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1034, self.RULE_mintypmax_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7318
            self.expression(0)
            self.state = 7324
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 7319
                self.match(SystemVerilogParser.COLON)
                self.state = 7320
                self.expression(0)
                self.state = 7321
                self.match(SystemVerilogParser.COLON)
                self.state = 7322
                self.expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_path_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_path_primary(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_path_primaryContext,0)


        def unary_module_path_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Unary_module_path_operatorContext,0)


        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attribute_instanceContext,i)


        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Module_path_expressionContext,i)


        def binary_module_path_operator(self):
            return self.getTypedRuleContext(SystemVerilogParser.Binary_module_path_operatorContext,0)


        def QUES(self):
            return self.getToken(SystemVerilogParser.QUES, 0)

        def COLON(self):
            return self.getToken(SystemVerilogParser.COLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_path_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_expression" ):
                listener.enterModule_path_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_expression" ):
                listener.exitModule_path_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_expression" ):
                return visitor.visitModule_path_expression(self)
            else:
                return visitor.visitChildren(self)



    def module_path_expression(self, _p:int=0):
        _parentctx = self._ctx
        _parentState = self.state
        localctx = SystemVerilogParser.Module_path_expressionContext(self, self._ctx, _parentState)
        _prevctx = localctx
        _startState = 1036
        self.enterRecursionRule(localctx, 1036, self.RULE_module_path_expression, _p)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7334
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 3)) & ~0x3f) == 0 and ((1 << (_la - 3)) & ((1 << (SystemVerilogParser.NOT - 3)) | (1 << (SystemVerilogParser.AND - 3)) | (1 << (SystemVerilogParser.CARET - 3)) | (1 << (SystemVerilogParser.CARETSQUIG - 3)) | (1 << (SystemVerilogParser.BAR - 3)) | (1 << (SystemVerilogParser.SQUIG - 3)) | (1 << (SystemVerilogParser.SQUIGAND - 3)) | (1 << (SystemVerilogParser.SQUIGCARET - 3)) | (1 << (SystemVerilogParser.SQUIGBAR - 3)))) != 0):
                self.state = 7327
                self.unary_module_path_operator()
                self.state = 7331
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.LPS:
                    self.state = 7328
                    self.attribute_instance()
                    self.state = 7333
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)



            self.state = 7336
            self.module_path_primary()
            self._ctx.stop = self._input.LT(-1)
            self.state = 7362
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,920,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    if self._parseListeners is not None:
                        self.triggerExitRuleEvent()
                    _prevctx = localctx
                    self.state = 7360
                    self._errHandler.sync(self)
                    la_ = self._interp.adaptivePredict(self._input,919,self._ctx)
                    if la_ == 1:
                        localctx = SystemVerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 7338
                        if not self.precpred(self._ctx, 2):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 2)")
                        self.state = 7339
                        self.binary_module_path_operator()
                        self.state = 7343
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        while _la==SystemVerilogParser.LPS:
                            self.state = 7340
                            self.attribute_instance()
                            self.state = 7345
                            self._errHandler.sync(self)
                            _la = self._input.LA(1)

                        self.state = 7346
                        self.module_path_expression(3)
                        pass

                    elif la_ == 2:
                        localctx = SystemVerilogParser.Module_path_expressionContext(self, _parentctx, _parentState)
                        self.pushNewRecursionContext(localctx, _startState, self.RULE_module_path_expression)
                        self.state = 7348
                        if not self.precpred(self._ctx, 1):
                            from antlr4.error.Errors import FailedPredicateException
                            raise FailedPredicateException(self, "self.precpred(self._ctx, 1)")
                        self.state = 7349
                        self.match(SystemVerilogParser.QUES)
                        self.state = 7353
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        while _la==SystemVerilogParser.LPS:
                            self.state = 7350
                            self.attribute_instance()
                            self.state = 7355
                            self._errHandler.sync(self)
                            _la = self._input.LA(1)

                        self.state = 7356
                        self.module_path_expression(0)
                        self.state = 7357
                        self.match(SystemVerilogParser.COLON)
                        self.state = 7358
                        self.module_path_expression(2)
                        pass

             
                self.state = 7364
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,920,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.unrollRecursionContexts(_parentctx)
        return localctx


    class Module_path_mintypmax_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_path_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Module_path_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Module_path_expressionContext,i)


        def COLON(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COLON)
            else:
                return self.getToken(SystemVerilogParser.COLON, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_path_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_mintypmax_expression" ):
                listener.enterModule_path_mintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_mintypmax_expression" ):
                listener.exitModule_path_mintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_mintypmax_expression" ):
                return visitor.visitModule_path_mintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def module_path_mintypmax_expression(self):

        localctx = SystemVerilogParser.Module_path_mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1038, self.RULE_module_path_mintypmax_expression)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7365
            self.module_path_expression(0)
            self.state = 7371
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.COLON:
                self.state = 7366
                self.match(SystemVerilogParser.COLON)
                self.state = 7367
                self.module_path_expression(0)
                self.state = 7368
                self.match(SystemVerilogParser.COLON)
                self.state = 7369
                self.module_path_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Part_select_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_rangeContext,0)


        def indexed_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Indexed_rangeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_part_select_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPart_select_range" ):
                listener.enterPart_select_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPart_select_range" ):
                listener.exitPart_select_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPart_select_range" ):
                return visitor.visitPart_select_range(self)
            else:
                return visitor.visitChildren(self)




    def part_select_range(self):

        localctx = SystemVerilogParser.Part_select_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1040, self.RULE_part_select_range)
        try:
            self.state = 7375
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,922,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7373
                self.constant_range()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7374
                self.indexed_range()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Indexed_rangeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def PLUSCOLON(self):
            return self.getToken(SystemVerilogParser.PLUSCOLON, 0)

        def MCOLON(self):
            return self.getToken(SystemVerilogParser.MCOLON, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_indexed_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIndexed_range" ):
                listener.enterIndexed_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIndexed_range" ):
                listener.exitIndexed_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIndexed_range" ):
                return visitor.visitIndexed_range(self)
            else:
                return visitor.visitChildren(self)




    def indexed_range(self):

        localctx = SystemVerilogParser.Indexed_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1042, self.RULE_indexed_range)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7377
            self.expression(0)
            self.state = 7378
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.MCOLON or _la==SystemVerilogParser.PLUSCOLON):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 7379
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_genvar_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_expression" ):
                listener.enterGenvar_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_expression" ):
                listener.exitGenvar_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_expression" ):
                return visitor.visitGenvar_expression(self)
            else:
                return visitor.visitChildren(self)




    def genvar_expression(self):

        localctx = SystemVerilogParser.Genvar_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1044, self.RULE_genvar_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7381
            self.constant_expression(0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_primaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def primary_literal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Primary_literalContext,0)


        def constant_select(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_selectContext,0)


        def ps_parameter_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_parameter_identifierContext,0)


        def formal_port_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Formal_port_identifierContext,0)


        def specparam_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Specparam_identifierContext,0)


        def constant_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_concatenationContext,0)


        def constant_multiple_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_multiple_concatenationContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def constant_range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_range_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def genvar_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Genvar_identifierContext,0)


        def enum_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Enum_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def constant_function_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_function_callContext,0)


        def constant_let_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_let_expressionContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def constant_mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def constant_assignment_pattern_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_assignment_pattern_expressionContext,0)


        def type_reference(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_referenceContext,0)


        def KNULL(self):
            return self.getToken(SystemVerilogParser.KNULL, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_primary" ):
                listener.enterConstant_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_primary" ):
                listener.exitConstant_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_primary" ):
                return visitor.visitConstant_primary(self)
            else:
                return visitor.visitChildren(self)




    def constant_primary(self):

        localctx = SystemVerilogParser.Constant_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1046, self.RULE_constant_primary)
        try:
            self.state = 7416
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,927,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7383
                self.primary_literal()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7386
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,923,self._ctx)
                if la_ == 1:
                    self.state = 7384
                    self.ps_parameter_identifier()
                    pass

                elif la_ == 2:
                    self.state = 7385
                    self.formal_port_identifier()
                    pass


                self.state = 7388
                self.constant_select()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 7393
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,924,self._ctx)
                if la_ == 1:
                    self.state = 7390
                    self.specparam_identifier()
                    pass

                elif la_ == 2:
                    self.state = 7391
                    self.constant_concatenation()
                    pass

                elif la_ == 3:
                    self.state = 7392
                    self.constant_multiple_concatenation()
                    pass


                self.state = 7399
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,925,self._ctx)
                if la_ == 1:
                    self.state = 7395
                    self.match(SystemVerilogParser.LB)
                    self.state = 7396
                    self.constant_range_expression()
                    self.state = 7397
                    self.match(SystemVerilogParser.RB)


                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 7401
                self.genvar_identifier()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 7404
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,926,self._ctx)
                if la_ == 1:
                    self.state = 7402
                    self.package_scope()

                elif la_ == 2:
                    self.state = 7403
                    self.class_scope()


                self.state = 7406
                self.enum_identifier()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 7407
                self.constant_function_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 7408
                self.constant_let_expression()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 7409
                self.match(SystemVerilogParser.LP)
                self.state = 7410
                self.constant_mintypmax_expression()
                self.state = 7411
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 7413
                self.constant_assignment_pattern_expression()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 7414
                self.type_reference()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 7415
                self.match(SystemVerilogParser.KNULL)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_path_primaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(SystemVerilogParser.NumberContext,0)


        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def module_path_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_path_concatenationContext,0)


        def module_path_multiple_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_path_multiple_concatenationContext,0)


        def function_subroutine_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_subroutine_callContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def module_path_mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Module_path_mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_path_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_path_primary" ):
                listener.enterModule_path_primary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_path_primary" ):
                listener.exitModule_path_primary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_path_primary" ):
                return visitor.visitModule_path_primary(self)
            else:
                return visitor.visitChildren(self)




    def module_path_primary(self):

        localctx = SystemVerilogParser.Module_path_primaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1048, self.RULE_module_path_primary)
        try:
            self.state = 7427
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,928,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7418
                self.number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7419
                self.identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 7420
                self.module_path_concatenation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 7421
                self.module_path_multiple_concatenation()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 7422
                self.function_subroutine_call()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 7423
                self.match(SystemVerilogParser.LP)
                self.state = 7424
                self.module_path_mintypmax_expression()
                self.state = 7425
                self.match(SystemVerilogParser.RP)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class PrimaryContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def primary_literal(self):
            return self.getTypedRuleContext(SystemVerilogParser.Primary_literalContext,0)


        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def select_(self):
            return self.getTypedRuleContext(SystemVerilogParser.Select_Context,0)


        def class_qualifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_qualifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def empty_unpacked_array_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Empty_unpacked_array_concatenationContext,0)


        def concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.ConcatenationContext,0)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def range_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Range_expressionContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def multiple_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Multiple_concatenationContext,0)


        def function_subroutine_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Function_subroutine_callContext,0)


        def let_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_expressionContext,0)


        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Mintypmax_expressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def cast(self):
            return self.getTypedRuleContext(SystemVerilogParser.CastContext,0)


        def assignment_pattern_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_expressionContext,0)


        def streaming_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Streaming_concatenationContext,0)


        def sequence_method_call(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_method_callContext,0)


        def KTHIS(self):
            return self.getToken(SystemVerilogParser.KTHIS, 0)

        def DOLLAR(self):
            return self.getToken(SystemVerilogParser.DOLLAR, 0)

        def KNULL(self):
            return self.getToken(SystemVerilogParser.KNULL, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrimary" ):
                listener.enterPrimary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrimary" ):
                listener.exitPrimary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrimary" ):
                return visitor.visitPrimary(self)
            else:
                return visitor.visitChildren(self)




    def primary(self):

        localctx = SystemVerilogParser.PrimaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1050, self.RULE_primary)
        try:
            self.state = 7465
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,932,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7429
                self.primary_literal()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7432
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,929,self._ctx)
                if la_ == 1:
                    self.state = 7430
                    self.class_qualifier()

                elif la_ == 2:
                    self.state = 7431
                    self.package_scope()


                self.state = 7434
                self.hierarchical_identifier()
                self.state = 7435
                self.select_()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 7437
                self.empty_unpacked_array_concatenation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 7438
                self.concatenation()
                self.state = 7443
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,930,self._ctx)
                if la_ == 1:
                    self.state = 7439
                    self.match(SystemVerilogParser.LB)
                    self.state = 7440
                    self.range_expression()
                    self.state = 7441
                    self.match(SystemVerilogParser.RB)


                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 7445
                self.multiple_concatenation()
                self.state = 7450
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,931,self._ctx)
                if la_ == 1:
                    self.state = 7446
                    self.match(SystemVerilogParser.LB)
                    self.state = 7447
                    self.range_expression()
                    self.state = 7448
                    self.match(SystemVerilogParser.RB)


                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 7452
                self.function_subroutine_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 7453
                self.let_expression()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 7454
                self.match(SystemVerilogParser.LP)
                self.state = 7455
                self.mintypmax_expression()
                self.state = 7456
                self.match(SystemVerilogParser.RP)
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 7458
                self.cast()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 7459
                self.assignment_pattern_expression()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 7460
                self.streaming_concatenation()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 7461
                self.sequence_method_call()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 7462
                self.match(SystemVerilogParser.KTHIS)
                pass

            elif la_ == 14:
                self.enterOuterAlt(localctx, 14)
                self.state = 7463
                self.match(SystemVerilogParser.DOLLAR)
                pass

            elif la_ == 15:
                self.enterOuterAlt(localctx, 15)
                self.state = 7464
                self.match(SystemVerilogParser.KNULL)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_qualifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KLOCAL(self):
            return self.getToken(SystemVerilogParser.KLOCAL, 0)

        def COLONCOLON(self):
            return self.getToken(SystemVerilogParser.COLONCOLON, 0)

        def implicit_class_handle(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_class_handleContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_qualifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_qualifier" ):
                listener.enterClass_qualifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_qualifier" ):
                listener.exitClass_qualifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_qualifier" ):
                return visitor.visitClass_qualifier(self)
            else:
                return visitor.visitChildren(self)




    def class_qualifier(self):

        localctx = SystemVerilogParser.Class_qualifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1052, self.RULE_class_qualifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7469
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.KLOCAL:
                self.state = 7467
                self.match(SystemVerilogParser.KLOCAL)
                self.state = 7468
                self.match(SystemVerilogParser.COLONCOLON)


            self.state = 7475
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,934,self._ctx)
            if la_ == 1:
                self.state = 7471
                self.implicit_class_handle()
                self.state = 7472
                self.match(SystemVerilogParser.DOT)

            elif la_ == 2:
                self.state = 7474
                self.class_scope()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Range_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def part_select_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Part_select_rangeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRange_expression" ):
                listener.enterRange_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRange_expression" ):
                listener.exitRange_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRange_expression" ):
                return visitor.visitRange_expression(self)
            else:
                return visitor.visitChildren(self)




    def range_expression(self):

        localctx = SystemVerilogParser.Range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1054, self.RULE_range_expression)
        try:
            self.state = 7479
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,935,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7477
                self.expression(0)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7478
                self.part_select_range()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Primary_literalContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(SystemVerilogParser.NumberContext,0)


        def TIME_LITERAL(self):
            return self.getToken(SystemVerilogParser.TIME_LITERAL, 0)

        def STRING_LITERAL(self):
            return self.getToken(SystemVerilogParser.STRING_LITERAL, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_primary_literal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrimary_literal" ):
                listener.enterPrimary_literal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrimary_literal" ):
                listener.exitPrimary_literal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrimary_literal" ):
                return visitor.visitPrimary_literal(self)
            else:
                return visitor.visitChildren(self)




    def primary_literal(self):

        localctx = SystemVerilogParser.Primary_literalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1056, self.RULE_primary_literal)
        try:
            self.state = 7484
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.DECIMAL_NUMBER, SystemVerilogParser.BINARY_NUMBER, SystemVerilogParser.OCTAL_NUMBER, SystemVerilogParser.HEX_NUMBER, SystemVerilogParser.REAL_NUMBER, SystemVerilogParser.UNSIGNED_NUMBER]:
                self.enterOuterAlt(localctx, 1)
                self.state = 7481
                self.number()
                pass
            elif token in [SystemVerilogParser.TIME_LITERAL]:
                self.enterOuterAlt(localctx, 2)
                self.state = 7482
                self.match(SystemVerilogParser.TIME_LITERAL)
                pass
            elif token in [SystemVerilogParser.STRING_LITERAL]:
                self.enterOuterAlt(localctx, 3)
                self.state = 7483
                self.match(SystemVerilogParser.STRING_LITERAL)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Implicit_class_handleContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def KTHIS(self):
            return self.getToken(SystemVerilogParser.KTHIS, 0)

        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def KSUPER(self):
            return self.getToken(SystemVerilogParser.KSUPER, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_implicit_class_handle

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterImplicit_class_handle" ):
                listener.enterImplicit_class_handle(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitImplicit_class_handle" ):
                listener.exitImplicit_class_handle(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitImplicit_class_handle" ):
                return visitor.visitImplicit_class_handle(self)
            else:
                return visitor.visitChildren(self)




    def implicit_class_handle(self):

        localctx = SystemVerilogParser.Implicit_class_handleContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1058, self.RULE_implicit_class_handle)
        try:
            self.state = 7492
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.KTHIS]:
                self.enterOuterAlt(localctx, 1)
                self.state = 7486
                self.match(SystemVerilogParser.KTHIS)
                self.state = 7489
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,937,self._ctx)
                if la_ == 1:
                    self.state = 7487
                    self.match(SystemVerilogParser.DOT)
                    self.state = 7488
                    self.match(SystemVerilogParser.KSUPER)


                pass
            elif token in [SystemVerilogParser.KSUPER]:
                self.enterOuterAlt(localctx, 2)
                self.state = 7491
                self.match(SystemVerilogParser.KSUPER)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bit_selectContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LB)
            else:
                return self.getToken(SystemVerilogParser.LB, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,i)


        def RB(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RB)
            else:
                return self.getToken(SystemVerilogParser.RB, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bit_select

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBit_select" ):
                listener.enterBit_select(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBit_select" ):
                listener.exitBit_select(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBit_select" ):
                return visitor.visitBit_select(self)
            else:
                return visitor.visitChildren(self)




    def bit_select(self):

        localctx = SystemVerilogParser.Bit_selectContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1060, self.RULE_bit_select)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7500
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,939,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 7494
                    self.match(SystemVerilogParser.LB)
                    self.state = 7495
                    self.expression(0)
                    self.state = 7496
                    self.match(SystemVerilogParser.RB) 
                self.state = 7502
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,939,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Select_Context(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def bit_select(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Bit_selectContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Bit_selectContext,i)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def member_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Member_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Member_identifierContext,i)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def part_select_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Part_select_rangeContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_select_

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSelect_" ):
                listener.enterSelect_(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSelect_" ):
                listener.exitSelect_(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSelect_" ):
                return visitor.visitSelect_(self)
            else:
                return visitor.visitChildren(self)




    def select_(self):

        localctx = SystemVerilogParser.Select_Context(self, self._ctx, self.state)
        self.enterRule(localctx, 1062, self.RULE_select_)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7514
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,941,self._ctx)
            if la_ == 1:
                self.state = 7509
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,940,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 7503
                        self.match(SystemVerilogParser.DOT)
                        self.state = 7504
                        self.member_identifier()
                        self.state = 7505
                        self.bit_select() 
                    self.state = 7511
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,940,self._ctx)

                self.state = 7512
                self.match(SystemVerilogParser.DOT)
                self.state = 7513
                self.member_identifier()


            self.state = 7516
            self.bit_select()
            self.state = 7521
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,942,self._ctx)
            if la_ == 1:
                self.state = 7517
                self.match(SystemVerilogParser.LB)
                self.state = 7518
                self.part_select_range()
                self.state = 7519
                self.match(SystemVerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Nonrange_selectContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def bit_select(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Bit_selectContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Bit_selectContext,i)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def member_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Member_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Member_identifierContext,i)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_nonrange_select

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNonrange_select" ):
                listener.enterNonrange_select(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNonrange_select" ):
                listener.exitNonrange_select(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNonrange_select" ):
                return visitor.visitNonrange_select(self)
            else:
                return visitor.visitChildren(self)




    def nonrange_select(self):

        localctx = SystemVerilogParser.Nonrange_selectContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1064, self.RULE_nonrange_select)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7534
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.DOT:
                self.state = 7529
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,943,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 7523
                        self.match(SystemVerilogParser.DOT)
                        self.state = 7524
                        self.member_identifier()
                        self.state = 7525
                        self.bit_select() 
                    self.state = 7531
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,943,self._ctx)

                self.state = 7532
                self.match(SystemVerilogParser.DOT)
                self.state = 7533
                self.member_identifier()


            self.state = 7536
            self.bit_select()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_bit_selectContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LB(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LB)
            else:
                return self.getToken(SystemVerilogParser.LB, i)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def RB(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RB)
            else:
                return self.getToken(SystemVerilogParser.RB, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_bit_select

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_bit_select" ):
                listener.enterConstant_bit_select(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_bit_select" ):
                listener.exitConstant_bit_select(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_bit_select" ):
                return visitor.visitConstant_bit_select(self)
            else:
                return visitor.visitChildren(self)




    def constant_bit_select(self):

        localctx = SystemVerilogParser.Constant_bit_selectContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1066, self.RULE_constant_bit_select)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7544
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,945,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 7538
                    self.match(SystemVerilogParser.LB)
                    self.state = 7539
                    self.constant_expression(0)
                    self.state = 7540
                    self.match(SystemVerilogParser.RB) 
                self.state = 7546
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,945,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_selectContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def constant_bit_select(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_bit_selectContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_bit_selectContext,i)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def member_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Member_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Member_identifierContext,i)


        def LB(self):
            return self.getToken(SystemVerilogParser.LB, 0)

        def constant_part_select_range(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_part_select_rangeContext,0)


        def RB(self):
            return self.getToken(SystemVerilogParser.RB, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_select

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_select" ):
                listener.enterConstant_select(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_select" ):
                listener.exitConstant_select(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_select" ):
                return visitor.visitConstant_select(self)
            else:
                return visitor.visitChildren(self)




    def constant_select(self):

        localctx = SystemVerilogParser.Constant_selectContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1068, self.RULE_constant_select)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7558
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,947,self._ctx)
            if la_ == 1:
                self.state = 7553
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,946,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 7547
                        self.match(SystemVerilogParser.DOT)
                        self.state = 7548
                        self.member_identifier()
                        self.state = 7549
                        self.constant_bit_select() 
                    self.state = 7555
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,946,self._ctx)

                self.state = 7556
                self.match(SystemVerilogParser.DOT)
                self.state = 7557
                self.member_identifier()


            self.state = 7560
            self.constant_bit_select()
            self.state = 7565
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,948,self._ctx)
            if la_ == 1:
                self.state = 7561
                self.match(SystemVerilogParser.LB)
                self.state = 7562
                self.constant_part_select_range()
                self.state = 7563
                self.match(SystemVerilogParser.RB)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_let_expressionContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def let_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Let_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constant_let_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_let_expression" ):
                listener.enterConstant_let_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_let_expression" ):
                listener.exitConstant_let_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_let_expression" ):
                return visitor.visitConstant_let_expression(self)
            else:
                return visitor.visitChildren(self)




    def constant_let_expression(self):

        localctx = SystemVerilogParser.Constant_let_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1070, self.RULE_constant_let_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7567
            self.let_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class CastContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def casting_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Casting_typeContext,0)


        def QUOTE(self):
            return self.getToken(SystemVerilogParser.QUOTE, 0)

        def LP(self):
            return self.getToken(SystemVerilogParser.LP, 0)

        def expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.ExpressionContext,0)


        def RP(self):
            return self.getToken(SystemVerilogParser.RP, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cast

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCast" ):
                listener.enterCast(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCast" ):
                listener.exitCast(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCast" ):
                return visitor.visitCast(self)
            else:
                return visitor.visitChildren(self)




    def cast(self):

        localctx = SystemVerilogParser.CastContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1072, self.RULE_cast)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7569
            self.casting_type()
            self.state = 7570
            self.match(SystemVerilogParser.QUOTE)
            self.state = 7571
            self.match(SystemVerilogParser.LP)
            self.state = 7572
            self.expression(0)
            self.state = 7573
            self.match(SystemVerilogParser.RP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_lvalueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ps_or_hierarchical_net_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Ps_or_hierarchical_net_identifierContext,0)


        def constant_select(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_selectContext,0)


        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def net_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Net_lvalueContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Net_lvalueContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def assignment_pattern_net_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_net_lvalueContext,0)


        def assignment_pattern_expression_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_expression_typeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_lvalue" ):
                listener.enterNet_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_lvalue" ):
                listener.exitNet_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_lvalue" ):
                return visitor.visitNet_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def net_lvalue(self):

        localctx = SystemVerilogParser.Net_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1074, self.RULE_net_lvalue)
        self._la = 0 # Token type
        try:
            self.state = 7593
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,951,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7575
                self.ps_or_hierarchical_net_identifier()
                self.state = 7576
                self.constant_select()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7578
                self.match(SystemVerilogParser.LC)
                self.state = 7579
                self.net_lvalue()
                self.state = 7584
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 7580
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 7581
                    self.net_lvalue()
                    self.state = 7586
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 7587
                self.match(SystemVerilogParser.RC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 7590
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.DUNIT or _la==SystemVerilogParser.KBYTE or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 7589
                    self.assignment_pattern_expression_type()


                self.state = 7592
                self.assignment_pattern_net_lvalue()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_lvalueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_variable_identifierContext,0)


        def select_(self):
            return self.getTypedRuleContext(SystemVerilogParser.Select_Context,0)


        def implicit_class_handle(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_class_handleContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def LC(self):
            return self.getToken(SystemVerilogParser.LC, 0)

        def variable_lvalue(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Variable_lvalueContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Variable_lvalueContext,i)


        def RC(self):
            return self.getToken(SystemVerilogParser.RC, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def assignment_pattern_variable_lvalue(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_variable_lvalueContext,0)


        def assignment_pattern_expression_type(self):
            return self.getTypedRuleContext(SystemVerilogParser.Assignment_pattern_expression_typeContext,0)


        def streaming_concatenation(self):
            return self.getTypedRuleContext(SystemVerilogParser.Streaming_concatenationContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_variable_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_lvalue" ):
                listener.enterVariable_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_lvalue" ):
                listener.exitVariable_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_lvalue" ):
                return visitor.visitVariable_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def variable_lvalue(self):

        localctx = SystemVerilogParser.Variable_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1076, self.RULE_variable_lvalue)
        self._la = 0 # Token type
        try:
            self.state = 7620
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,955,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7599
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,952,self._ctx)
                if la_ == 1:
                    self.state = 7595
                    self.implicit_class_handle()
                    self.state = 7596
                    self.match(SystemVerilogParser.DOT)

                elif la_ == 2:
                    self.state = 7598
                    self.package_scope()


                self.state = 7601
                self.hierarchical_variable_identifier()
                self.state = 7602
                self.select_()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7604
                self.match(SystemVerilogParser.LC)
                self.state = 7605
                self.variable_lvalue()
                self.state = 7610
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SystemVerilogParser.COMMA:
                    self.state = 7606
                    self.match(SystemVerilogParser.COMMA)
                    self.state = 7607
                    self.variable_lvalue()
                    self.state = 7612
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 7613
                self.match(SystemVerilogParser.RC)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 7616
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SystemVerilogParser.DUNIT or _la==SystemVerilogParser.KBYTE or ((((_la - 195)) & ~0x3f) == 0 and ((1 << (_la - 195)) & ((1 << (SystemVerilogParser.KINT - 195)) | (1 << (SystemVerilogParser.KINTEGER - 195)) | (1 << (SystemVerilogParser.KLOCAL - 195)) | (1 << (SystemVerilogParser.KLONGINT - 195)))) != 0) or ((((_la - 276)) & ~0x3f) == 0 and ((1 << (_la - 276)) & ((1 << (SystemVerilogParser.KSHORTINT - 276)) | (1 << (SystemVerilogParser.KTIME - 276)) | (1 << (SystemVerilogParser.KTYPE - 276)))) != 0) or _la==SystemVerilogParser.SIMPLE_IDENTIFIER:
                    self.state = 7615
                    self.assignment_pattern_expression_type()


                self.state = 7618
                self.assignment_pattern_variable_lvalue()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 7619
                self.streaming_concatenation()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Nonrange_variable_lvalueContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_variable_identifierContext,0)


        def nonrange_select(self):
            return self.getTypedRuleContext(SystemVerilogParser.Nonrange_selectContext,0)


        def implicit_class_handle(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_class_handleContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_nonrange_variable_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNonrange_variable_lvalue" ):
                listener.enterNonrange_variable_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNonrange_variable_lvalue" ):
                listener.exitNonrange_variable_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNonrange_variable_lvalue" ):
                return visitor.visitNonrange_variable_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def nonrange_variable_lvalue(self):

        localctx = SystemVerilogParser.Nonrange_variable_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1078, self.RULE_nonrange_variable_lvalue)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7626
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,956,self._ctx)
            if la_ == 1:
                self.state = 7622
                self.implicit_class_handle()
                self.state = 7623
                self.match(SystemVerilogParser.DOT)

            elif la_ == 2:
                self.state = 7625
                self.package_scope()


            self.state = 7628
            self.hierarchical_variable_identifier()
            self.state = 7629
            self.nonrange_select()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PLUS(self):
            return self.getToken(SystemVerilogParser.PLUS, 0)

        def MINUS(self):
            return self.getToken(SystemVerilogParser.MINUS, 0)

        def NOT(self):
            return self.getToken(SystemVerilogParser.NOT, 0)

        def SQUIG(self):
            return self.getToken(SystemVerilogParser.SQUIG, 0)

        def AND(self):
            return self.getToken(SystemVerilogParser.AND, 0)

        def SQUIGAND(self):
            return self.getToken(SystemVerilogParser.SQUIGAND, 0)

        def BAR(self):
            return self.getToken(SystemVerilogParser.BAR, 0)

        def SQUIGBAR(self):
            return self.getToken(SystemVerilogParser.SQUIGBAR, 0)

        def CARET(self):
            return self.getToken(SystemVerilogParser.CARET, 0)

        def SQUIGCARET(self):
            return self.getToken(SystemVerilogParser.SQUIGCARET, 0)

        def CARETSQUIG(self):
            return self.getToken(SystemVerilogParser.CARETSQUIG, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_unary_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_operator" ):
                listener.enterUnary_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_operator" ):
                listener.exitUnary_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_operator" ):
                return visitor.visitUnary_operator(self)
            else:
                return visitor.visitChildren(self)




    def unary_operator(self):

        localctx = SystemVerilogParser.Unary_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1080, self.RULE_unary_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7631
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.NOT) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.SQUIG))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SystemVerilogParser.SQUIGAND - 64)) | (1 << (SystemVerilogParser.SQUIGCARET - 64)) | (1 << (SystemVerilogParser.SQUIGBAR - 64)) | (1 << (SystemVerilogParser.PLUS - 64)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Binary_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PLUS(self):
            return self.getToken(SystemVerilogParser.PLUS, 0)

        def MINUS(self):
            return self.getToken(SystemVerilogParser.MINUS, 0)

        def STAR(self):
            return self.getToken(SystemVerilogParser.STAR, 0)

        def SLASH(self):
            return self.getToken(SystemVerilogParser.SLASH, 0)

        def PER(self):
            return self.getToken(SystemVerilogParser.PER, 0)

        def EQEQ(self):
            return self.getToken(SystemVerilogParser.EQEQ, 0)

        def NE(self):
            return self.getToken(SystemVerilogParser.NE, 0)

        def EQEQEQ(self):
            return self.getToken(SystemVerilogParser.EQEQEQ, 0)

        def NEE(self):
            return self.getToken(SystemVerilogParser.NEE, 0)

        def EQEQQUEST(self):
            return self.getToken(SystemVerilogParser.EQEQQUEST, 0)

        def NEQ(self):
            return self.getToken(SystemVerilogParser.NEQ, 0)

        def ANDAND(self):
            return self.getToken(SystemVerilogParser.ANDAND, 0)

        def BARBAR(self):
            return self.getToken(SystemVerilogParser.BARBAR, 0)

        def SS(self):
            return self.getToken(SystemVerilogParser.SS, 0)

        def LT(self):
            return self.getToken(SystemVerilogParser.LT, 0)

        def LTEQ(self):
            return self.getToken(SystemVerilogParser.LTEQ, 0)

        def GT(self):
            return self.getToken(SystemVerilogParser.GT, 0)

        def GE(self):
            return self.getToken(SystemVerilogParser.GE, 0)

        def AND(self):
            return self.getToken(SystemVerilogParser.AND, 0)

        def BAR(self):
            return self.getToken(SystemVerilogParser.BAR, 0)

        def CARET(self):
            return self.getToken(SystemVerilogParser.CARET, 0)

        def SQUIGCARET(self):
            return self.getToken(SystemVerilogParser.SQUIGCARET, 0)

        def CARETSQUIG(self):
            return self.getToken(SystemVerilogParser.CARETSQUIG, 0)

        def GTGT(self):
            return self.getToken(SystemVerilogParser.GTGT, 0)

        def LTLT(self):
            return self.getToken(SystemVerilogParser.LTLT, 0)

        def GTGTGT(self):
            return self.getToken(SystemVerilogParser.GTGTGT, 0)

        def LTLTLT(self):
            return self.getToken(SystemVerilogParser.LTLTLT, 0)

        def ARROW(self):
            return self.getToken(SystemVerilogParser.ARROW, 0)

        def LTMINUSGT(self):
            return self.getToken(SystemVerilogParser.LTMINUSGT, 0)

        def PLUSPLUS(self):
            return self.getToken(SystemVerilogParser.PLUSPLUS, 0)

        def MINUSMINS(self):
            return self.getToken(SystemVerilogParser.MINUSMINS, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_binary_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_operator" ):
                listener.enterBinary_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_operator" ):
                listener.exitBinary_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_operator" ):
                return visitor.visitBinary_operator(self)
            else:
                return visitor.visitChildren(self)




    def binary_operator(self):

        localctx = SystemVerilogParser.Binary_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1082, self.RULE_binary_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7633
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.MINUS) | (1 << SystemVerilogParser.MINUSMINS) | (1 << SystemVerilogParser.NE) | (1 << SystemVerilogParser.NEQ) | (1 << SystemVerilogParser.NEE) | (1 << SystemVerilogParser.PER) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.ANDAND) | (1 << SystemVerilogParser.STAR) | (1 << SystemVerilogParser.SS) | (1 << SystemVerilogParser.SLASH) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.BARBAR))) != 0) or ((((_la - 65)) & ~0x3f) == 0 and ((1 << (_la - 65)) & ((1 << (SystemVerilogParser.SQUIGCARET - 65)) | (1 << (SystemVerilogParser.PLUS - 65)) | (1 << (SystemVerilogParser.PLUSPLUS - 65)) | (1 << (SystemVerilogParser.LT - 65)) | (1 << (SystemVerilogParser.LTLT - 65)) | (1 << (SystemVerilogParser.LTLTLT - 65)) | (1 << (SystemVerilogParser.LTEQ - 65)) | (1 << (SystemVerilogParser.LTMINUSGT - 65)) | (1 << (SystemVerilogParser.EQEQ - 65)) | (1 << (SystemVerilogParser.EQEQQUEST - 65)) | (1 << (SystemVerilogParser.EQEQEQ - 65)) | (1 << (SystemVerilogParser.GT - 65)) | (1 << (SystemVerilogParser.ARROW - 65)) | (1 << (SystemVerilogParser.GE - 65)) | (1 << (SystemVerilogParser.GTGT - 65)) | (1 << (SystemVerilogParser.GTGTGT - 65)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inc_or_dec_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def PLUSPLUS(self):
            return self.getToken(SystemVerilogParser.PLUSPLUS, 0)

        def MINUSMINS(self):
            return self.getToken(SystemVerilogParser.MINUSMINS, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_inc_or_dec_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInc_or_dec_operator" ):
                listener.enterInc_or_dec_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInc_or_dec_operator" ):
                listener.exitInc_or_dec_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInc_or_dec_operator" ):
                return visitor.visitInc_or_dec_operator(self)
            else:
                return visitor.visitChildren(self)




    def inc_or_dec_operator(self):

        localctx = SystemVerilogParser.Inc_or_dec_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1084, self.RULE_inc_or_dec_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7635
            _la = self._input.LA(1)
            if not(_la==SystemVerilogParser.MINUSMINS or _la==SystemVerilogParser.PLUSPLUS):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_module_path_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def NOT(self):
            return self.getToken(SystemVerilogParser.NOT, 0)

        def SQUIG(self):
            return self.getToken(SystemVerilogParser.SQUIG, 0)

        def AND(self):
            return self.getToken(SystemVerilogParser.AND, 0)

        def SQUIGAND(self):
            return self.getToken(SystemVerilogParser.SQUIGAND, 0)

        def BAR(self):
            return self.getToken(SystemVerilogParser.BAR, 0)

        def SQUIGBAR(self):
            return self.getToken(SystemVerilogParser.SQUIGBAR, 0)

        def CARET(self):
            return self.getToken(SystemVerilogParser.CARET, 0)

        def SQUIGCARET(self):
            return self.getToken(SystemVerilogParser.SQUIGCARET, 0)

        def CARETSQUIG(self):
            return self.getToken(SystemVerilogParser.CARETSQUIG, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_unary_module_path_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_module_path_operator" ):
                listener.enterUnary_module_path_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_module_path_operator" ):
                listener.exitUnary_module_path_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_module_path_operator" ):
                return visitor.visitUnary_module_path_operator(self)
            else:
                return visitor.visitChildren(self)




    def unary_module_path_operator(self):

        localctx = SystemVerilogParser.Unary_module_path_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1086, self.RULE_unary_module_path_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7637
            _la = self._input.LA(1)
            if not(((((_la - 3)) & ~0x3f) == 0 and ((1 << (_la - 3)) & ((1 << (SystemVerilogParser.NOT - 3)) | (1 << (SystemVerilogParser.AND - 3)) | (1 << (SystemVerilogParser.CARET - 3)) | (1 << (SystemVerilogParser.CARETSQUIG - 3)) | (1 << (SystemVerilogParser.BAR - 3)) | (1 << (SystemVerilogParser.SQUIG - 3)) | (1 << (SystemVerilogParser.SQUIGAND - 3)) | (1 << (SystemVerilogParser.SQUIGCARET - 3)) | (1 << (SystemVerilogParser.SQUIGBAR - 3)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Binary_module_path_operatorContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def EQEQ(self):
            return self.getToken(SystemVerilogParser.EQEQ, 0)

        def NE(self):
            return self.getToken(SystemVerilogParser.NE, 0)

        def ANDAND(self):
            return self.getToken(SystemVerilogParser.ANDAND, 0)

        def BARBAR(self):
            return self.getToken(SystemVerilogParser.BARBAR, 0)

        def AND(self):
            return self.getToken(SystemVerilogParser.AND, 0)

        def BAR(self):
            return self.getToken(SystemVerilogParser.BAR, 0)

        def CARET(self):
            return self.getToken(SystemVerilogParser.CARET, 0)

        def CARETSQUIG(self):
            return self.getToken(SystemVerilogParser.CARETSQUIG, 0)

        def SQUIGCARET(self):
            return self.getToken(SystemVerilogParser.SQUIGCARET, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_binary_module_path_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_module_path_operator" ):
                listener.enterBinary_module_path_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_module_path_operator" ):
                listener.exitBinary_module_path_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_module_path_operator" ):
                return visitor.visitBinary_module_path_operator(self)
            else:
                return visitor.visitChildren(self)




    def binary_module_path_operator(self):

        localctx = SystemVerilogParser.Binary_module_path_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1088, self.RULE_binary_module_path_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7639
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SystemVerilogParser.NE) | (1 << SystemVerilogParser.AND) | (1 << SystemVerilogParser.ANDAND) | (1 << SystemVerilogParser.CARET) | (1 << SystemVerilogParser.CARETSQUIG) | (1 << SystemVerilogParser.BAR) | (1 << SystemVerilogParser.BARBAR))) != 0) or _la==SystemVerilogParser.SQUIGCARET or _la==SystemVerilogParser.EQEQ):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class NumberContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def DECIMAL_NUMBER(self):
            return self.getToken(SystemVerilogParser.DECIMAL_NUMBER, 0)

        def UNSIGNED_NUMBER(self):
            return self.getToken(SystemVerilogParser.UNSIGNED_NUMBER, 0)

        def OCTAL_NUMBER(self):
            return self.getToken(SystemVerilogParser.OCTAL_NUMBER, 0)

        def BINARY_NUMBER(self):
            return self.getToken(SystemVerilogParser.BINARY_NUMBER, 0)

        def HEX_NUMBER(self):
            return self.getToken(SystemVerilogParser.HEX_NUMBER, 0)

        def REAL_NUMBER(self):
            return self.getToken(SystemVerilogParser.REAL_NUMBER, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNumber" ):
                listener.enterNumber(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNumber" ):
                listener.exitNumber(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNumber" ):
                return visitor.visitNumber(self)
            else:
                return visitor.visitChildren(self)




    def number(self):

        localctx = SystemVerilogParser.NumberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1090, self.RULE_number)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7641
            _la = self._input.LA(1)
            if not(((((_la - 346)) & ~0x3f) == 0 and ((1 << (_la - 346)) & ((1 << (SystemVerilogParser.DECIMAL_NUMBER - 346)) | (1 << (SystemVerilogParser.BINARY_NUMBER - 346)) | (1 << (SystemVerilogParser.OCTAL_NUMBER - 346)) | (1 << (SystemVerilogParser.HEX_NUMBER - 346)) | (1 << (SystemVerilogParser.REAL_NUMBER - 346)) | (1 << (SystemVerilogParser.UNSIGNED_NUMBER - 346)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attribute_instanceContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def LPS(self):
            return self.getToken(SystemVerilogParser.LPS, 0)

        def attr_spec(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Attr_specContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Attr_specContext,i)


        def SRP(self):
            return self.getToken(SystemVerilogParser.SRP, 0)

        def COMMA(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.COMMA)
            else:
                return self.getToken(SystemVerilogParser.COMMA, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_attribute_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttribute_instance" ):
                listener.enterAttribute_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttribute_instance" ):
                listener.exitAttribute_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttribute_instance" ):
                return visitor.visitAttribute_instance(self)
            else:
                return visitor.visitChildren(self)




    def attribute_instance(self):

        localctx = SystemVerilogParser.Attribute_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1092, self.RULE_attribute_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7643
            self.match(SystemVerilogParser.LPS)
            self.state = 7644
            self.attr_spec()
            self.state = 7649
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SystemVerilogParser.COMMA:
                self.state = 7645
                self.match(SystemVerilogParser.COMMA)
                self.state = 7646
                self.attr_spec()
                self.state = 7651
                self._errHandler.sync(self)
                _la = self._input.LA(1)

            self.state = 7652
            self.match(SystemVerilogParser.SRP)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_specContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_name(self):
            return self.getTypedRuleContext(SystemVerilogParser.Attr_nameContext,0)


        def EQ(self):
            return self.getToken(SystemVerilogParser.EQ, 0)

        def constant_expression(self):
            return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_attr_spec

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_spec" ):
                listener.enterAttr_spec(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_spec" ):
                listener.exitAttr_spec(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_spec" ):
                return visitor.visitAttr_spec(self)
            else:
                return visitor.visitChildren(self)




    def attr_spec(self):

        localctx = SystemVerilogParser.Attr_specContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1094, self.RULE_attr_spec)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7654
            self.attr_name()
            self.state = 7657
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.EQ:
                self.state = 7655
                self.match(SystemVerilogParser.EQ)
                self.state = 7656
                self.constant_expression(0)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_nameContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_attr_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_name" ):
                listener.enterAttr_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_name" ):
                listener.exitAttr_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_name" ):
                return visitor.visitAttr_name(self)
            else:
                return visitor.visitChildren(self)




    def attr_name(self):

        localctx = SystemVerilogParser.Attr_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1096, self.RULE_attr_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7659
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Array_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_array_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArray_identifier" ):
                listener.enterArray_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArray_identifier" ):
                listener.exitArray_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArray_identifier" ):
                return visitor.visitArray_identifier(self)
            else:
                return visitor.visitChildren(self)




    def array_identifier(self):

        localctx = SystemVerilogParser.Array_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1098, self.RULE_array_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7661
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_identifier" ):
                listener.enterBlock_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_identifier" ):
                listener.exitBlock_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_identifier" ):
                return visitor.visitBlock_identifier(self)
            else:
                return visitor.visitChildren(self)




    def block_identifier(self):

        localctx = SystemVerilogParser.Block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1100, self.RULE_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7663
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bin_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_bin_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBin_identifier" ):
                listener.enterBin_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBin_identifier" ):
                listener.exitBin_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBin_identifier" ):
                return visitor.visitBin_identifier(self)
            else:
                return visitor.visitChildren(self)




    def bin_identifier(self):

        localctx = SystemVerilogParser.Bin_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1102, self.RULE_bin_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7665
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class C_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SIMPLE_IDENTIFIER(self):
            return self.getToken(SystemVerilogParser.SIMPLE_IDENTIFIER, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_c_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterC_identifier" ):
                listener.enterC_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitC_identifier" ):
                listener.exitC_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitC_identifier" ):
                return visitor.visitC_identifier(self)
            else:
                return visitor.visitChildren(self)




    def c_identifier(self):

        localctx = SystemVerilogParser.C_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1104, self.RULE_c_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7667
            self.match(SystemVerilogParser.SIMPLE_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cell_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cell_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCell_identifier" ):
                listener.enterCell_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCell_identifier" ):
                listener.exitCell_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCell_identifier" ):
                return visitor.visitCell_identifier(self)
            else:
                return visitor.visitChildren(self)




    def cell_identifier(self):

        localctx = SystemVerilogParser.Cell_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1106, self.RULE_cell_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7669
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Checker_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_checker_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterChecker_identifier" ):
                listener.enterChecker_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitChecker_identifier" ):
                listener.exitChecker_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitChecker_identifier" ):
                return visitor.visitChecker_identifier(self)
            else:
                return visitor.visitChildren(self)




    def checker_identifier(self):

        localctx = SystemVerilogParser.Checker_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1108, self.RULE_checker_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7671
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_identifier" ):
                listener.enterClass_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_identifier" ):
                listener.exitClass_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_identifier" ):
                return visitor.visitClass_identifier(self)
            else:
                return visitor.visitChildren(self)




    def class_identifier(self):

        localctx = SystemVerilogParser.Class_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1110, self.RULE_class_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7673
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Class_variable_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_class_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClass_variable_identifier" ):
                listener.enterClass_variable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClass_variable_identifier" ):
                listener.exitClass_variable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClass_variable_identifier" ):
                return visitor.visitClass_variable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def class_variable_identifier(self):

        localctx = SystemVerilogParser.Class_variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1112, self.RULE_class_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7675
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Clocking_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_clocking_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterClocking_identifier" ):
                listener.enterClocking_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitClocking_identifier" ):
                listener.exitClocking_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitClocking_identifier" ):
                return visitor.visitClocking_identifier(self)
            else:
                return visitor.visitChildren(self)




    def clocking_identifier(self):

        localctx = SystemVerilogParser.Clocking_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1114, self.RULE_clocking_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7677
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Config_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_config_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConfig_identifier" ):
                listener.enterConfig_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConfig_identifier" ):
                listener.exitConfig_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConfig_identifier" ):
                return visitor.visitConfig_identifier(self)
            else:
                return visitor.visitChildren(self)




    def config_identifier(self):

        localctx = SystemVerilogParser.Config_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1116, self.RULE_config_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7679
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Const_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_const_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConst_identifier" ):
                listener.enterConst_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConst_identifier" ):
                listener.exitConst_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConst_identifier" ):
                return visitor.visitConst_identifier(self)
            else:
                return visitor.visitChildren(self)




    def const_identifier(self):

        localctx = SystemVerilogParser.Const_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1118, self.RULE_const_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7681
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constraint_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_constraint_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstraint_identifier" ):
                listener.enterConstraint_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstraint_identifier" ):
                listener.exitConstraint_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstraint_identifier" ):
                return visitor.visitConstraint_identifier(self)
            else:
                return visitor.visitChildren(self)




    def constraint_identifier(self):

        localctx = SystemVerilogParser.Constraint_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1120, self.RULE_constraint_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7683
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Covergroup_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_covergroup_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCovergroup_identifier" ):
                listener.enterCovergroup_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCovergroup_identifier" ):
                listener.exitCovergroup_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCovergroup_identifier" ):
                return visitor.visitCovergroup_identifier(self)
            else:
                return visitor.visitChildren(self)




    def covergroup_identifier(self):

        localctx = SystemVerilogParser.Covergroup_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1122, self.RULE_covergroup_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7685
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Covergroup_variable_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_covergroup_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCovergroup_variable_identifier" ):
                listener.enterCovergroup_variable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCovergroup_variable_identifier" ):
                listener.exitCovergroup_variable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCovergroup_variable_identifier" ):
                return visitor.visitCovergroup_variable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def covergroup_variable_identifier(self):

        localctx = SystemVerilogParser.Covergroup_variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1124, self.RULE_covergroup_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7687
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cover_point_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cover_point_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCover_point_identifier" ):
                listener.enterCover_point_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCover_point_identifier" ):
                listener.exitCover_point_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCover_point_identifier" ):
                return visitor.visitCover_point_identifier(self)
            else:
                return visitor.visitChildren(self)




    def cover_point_identifier(self):

        localctx = SystemVerilogParser.Cover_point_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1126, self.RULE_cover_point_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7689
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cross_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_cross_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCross_identifier" ):
                listener.enterCross_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCross_identifier" ):
                listener.exitCross_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCross_identifier" ):
                return visitor.visitCross_identifier(self)
            else:
                return visitor.visitChildren(self)




    def cross_identifier(self):

        localctx = SystemVerilogParser.Cross_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1128, self.RULE_cross_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7691
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dynamic_array_variable_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Variable_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_dynamic_array_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDynamic_array_variable_identifier" ):
                listener.enterDynamic_array_variable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDynamic_array_variable_identifier" ):
                listener.exitDynamic_array_variable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDynamic_array_variable_identifier" ):
                return visitor.visitDynamic_array_variable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def dynamic_array_variable_identifier(self):

        localctx = SystemVerilogParser.Dynamic_array_variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1130, self.RULE_dynamic_array_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7693
            self.variable_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enum_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_enum_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnum_identifier" ):
                listener.enterEnum_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnum_identifier" ):
                listener.exitEnum_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnum_identifier" ):
                return visitor.visitEnum_identifier(self)
            else:
                return visitor.visitChildren(self)




    def enum_identifier(self):

        localctx = SystemVerilogParser.Enum_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1132, self.RULE_enum_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7695
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Formal_port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_formal_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFormal_port_identifier" ):
                listener.enterFormal_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFormal_port_identifier" ):
                listener.exitFormal_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFormal_port_identifier" ):
                return visitor.visitFormal_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def formal_port_identifier(self):

        localctx = SystemVerilogParser.Formal_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1134, self.RULE_formal_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7697
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_identifier" ):
                listener.enterFunction_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_identifier" ):
                listener.exitFunction_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_identifier" ):
                return visitor.visitFunction_identifier(self)
            else:
                return visitor.visitChildren(self)




    def function_identifier(self):

        localctx = SystemVerilogParser.Function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1136, self.RULE_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7699
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_block_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_generate_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block_identifier" ):
                listener.enterGenerate_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block_identifier" ):
                listener.exitGenerate_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block_identifier" ):
                return visitor.visitGenerate_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def generate_block_identifier(self):

        localctx = SystemVerilogParser.Generate_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1138, self.RULE_generate_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7701
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_genvar_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_identifier" ):
                listener.enterGenvar_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_identifier" ):
                listener.exitGenvar_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_identifier" ):
                return visitor.visitGenvar_identifier(self)
            else:
                return visitor.visitChildren(self)




    def genvar_identifier(self):

        localctx = SystemVerilogParser.Genvar_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1140, self.RULE_genvar_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7703
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_array_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_array_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_array_identifier" ):
                listener.enterHierarchical_array_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_array_identifier" ):
                listener.exitHierarchical_array_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_array_identifier" ):
                return visitor.visitHierarchical_array_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_array_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_array_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1142, self.RULE_hierarchical_array_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7705
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_block_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_block_identifier" ):
                listener.enterHierarchical_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_block_identifier" ):
                listener.exitHierarchical_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_block_identifier" ):
                return visitor.visitHierarchical_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_block_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1144, self.RULE_hierarchical_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7707
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_event_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_event_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_event_identifier" ):
                listener.enterHierarchical_event_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_event_identifier" ):
                listener.exitHierarchical_event_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_event_identifier" ):
                return visitor.visitHierarchical_event_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_event_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_event_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1146, self.RULE_hierarchical_event_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7709
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.IdentifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,i)


        def DROOT(self):
            return self.getToken(SystemVerilogParser.DROOT, 0)

        def constant_bit_select(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_bit_selectContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_bit_selectContext,i)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_identifier" ):
                listener.enterHierarchical_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_identifier" ):
                listener.exitHierarchical_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_identifier" ):
                return visitor.visitHierarchical_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1148, self.RULE_hierarchical_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7712
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SystemVerilogParser.DROOT:
                self.state = 7711
                self.match(SystemVerilogParser.DROOT)


            self.state = 7720
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,960,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 7714
                    self.identifier()
                    self.state = 7715
                    self.constant_bit_select()
                    self.state = 7716
                    self.match(SystemVerilogParser.DOT) 
                self.state = 7722
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,960,self._ctx)

            self.state = 7723
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_net_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_net_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_net_identifier" ):
                listener.enterHierarchical_net_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_net_identifier" ):
                listener.exitHierarchical_net_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_net_identifier" ):
                return visitor.visitHierarchical_net_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_net_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_net_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1150, self.RULE_hierarchical_net_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7725
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_parameter_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_parameter_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_parameter_identifier" ):
                listener.enterHierarchical_parameter_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_parameter_identifier" ):
                listener.exitHierarchical_parameter_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_parameter_identifier" ):
                return visitor.visitHierarchical_parameter_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_parameter_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_parameter_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1152, self.RULE_hierarchical_parameter_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7727
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_property_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_property_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_property_identifier" ):
                listener.enterHierarchical_property_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_property_identifier" ):
                listener.exitHierarchical_property_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_property_identifier" ):
                return visitor.visitHierarchical_property_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_property_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_property_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1154, self.RULE_hierarchical_property_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7729
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_sequence_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_sequence_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_sequence_identifier" ):
                listener.enterHierarchical_sequence_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_sequence_identifier" ):
                listener.exitHierarchical_sequence_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_sequence_identifier" ):
                return visitor.visitHierarchical_sequence_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_sequence_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_sequence_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1156, self.RULE_hierarchical_sequence_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7731
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_task_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_task_identifier" ):
                listener.enterHierarchical_task_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_task_identifier" ):
                listener.exitHierarchical_task_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_task_identifier" ):
                return visitor.visitHierarchical_task_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_task_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1158, self.RULE_hierarchical_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7733
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_tf_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_tf_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_tf_identifier" ):
                listener.enterHierarchical_tf_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_tf_identifier" ):
                listener.exitHierarchical_tf_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_tf_identifier" ):
                return visitor.visitHierarchical_tf_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_tf_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_tf_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1160, self.RULE_hierarchical_tf_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7735
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_variable_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_hierarchical_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_variable_identifier" ):
                listener.enterHierarchical_variable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_variable_identifier" ):
                listener.exitHierarchical_variable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_variable_identifier" ):
                return visitor.visitHierarchical_variable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_variable_identifier(self):

        localctx = SystemVerilogParser.Hierarchical_variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1162, self.RULE_hierarchical_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7737
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class IdentifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SIMPLE_IDENTIFIER(self):
            return self.getToken(SystemVerilogParser.SIMPLE_IDENTIFIER, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIdentifier" ):
                listener.enterIdentifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIdentifier" ):
                listener.exitIdentifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIdentifier" ):
                return visitor.visitIdentifier(self)
            else:
                return visitor.visitChildren(self)




    def identifier(self):

        localctx = SystemVerilogParser.IdentifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1164, self.RULE_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7739
            self.match(SystemVerilogParser.SIMPLE_IDENTIFIER)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Index_variable_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_index_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIndex_variable_identifier" ):
                listener.enterIndex_variable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIndex_variable_identifier" ):
                listener.exitIndex_variable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIndex_variable_identifier" ):
                return visitor.visitIndex_variable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def index_variable_identifier(self):

        localctx = SystemVerilogParser.Index_variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1166, self.RULE_index_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7741
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_identifier" ):
                listener.enterInterface_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_identifier" ):
                listener.exitInterface_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_identifier" ):
                return visitor.visitInterface_identifier(self)
            else:
                return visitor.visitChildren(self)




    def interface_identifier(self):

        localctx = SystemVerilogParser.Interface_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1168, self.RULE_interface_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7743
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Interface_instance_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_interface_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInterface_instance_identifier" ):
                listener.enterInterface_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInterface_instance_identifier" ):
                listener.exitInterface_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInterface_instance_identifier" ):
                return visitor.visitInterface_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def interface_instance_identifier(self):

        localctx = SystemVerilogParser.Interface_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1170, self.RULE_interface_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7745
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_inout_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_port_identifier" ):
                listener.enterInout_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_port_identifier" ):
                listener.exitInout_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_port_identifier" ):
                return visitor.visitInout_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def inout_port_identifier(self):

        localctx = SystemVerilogParser.Inout_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1172, self.RULE_inout_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7747
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_input_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_port_identifier" ):
                listener.enterInput_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_port_identifier" ):
                listener.exitInput_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_port_identifier" ):
                return visitor.visitInput_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def input_port_identifier(self):

        localctx = SystemVerilogParser.Input_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1174, self.RULE_input_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7749
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Instance_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInstance_identifier" ):
                listener.enterInstance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInstance_identifier" ):
                listener.exitInstance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInstance_identifier" ):
                return visitor.visitInstance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def instance_identifier(self):

        localctx = SystemVerilogParser.Instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1176, self.RULE_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7751
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Library_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_library_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLibrary_identifier" ):
                listener.enterLibrary_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLibrary_identifier" ):
                listener.exitLibrary_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLibrary_identifier" ):
                return visitor.visitLibrary_identifier(self)
            else:
                return visitor.visitChildren(self)




    def library_identifier(self):

        localctx = SystemVerilogParser.Library_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1178, self.RULE_library_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7753
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Member_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_member_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMember_identifier" ):
                listener.enterMember_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMember_identifier" ):
                listener.exitMember_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMember_identifier" ):
                return visitor.visitMember_identifier(self)
            else:
                return visitor.visitChildren(self)




    def member_identifier(self):

        localctx = SystemVerilogParser.Member_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1180, self.RULE_member_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7755
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Method_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_method_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMethod_identifier" ):
                listener.enterMethod_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMethod_identifier" ):
                listener.exitMethod_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMethod_identifier" ):
                return visitor.visitMethod_identifier(self)
            else:
                return visitor.visitChildren(self)




    def method_identifier(self):

        localctx = SystemVerilogParser.Method_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1182, self.RULE_method_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7757
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Modport_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_modport_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModport_identifier" ):
                listener.enterModport_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModport_identifier" ):
                listener.exitModport_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModport_identifier" ):
                return visitor.visitModport_identifier(self)
            else:
                return visitor.visitChildren(self)




    def modport_identifier(self):

        localctx = SystemVerilogParser.Modport_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1184, self.RULE_modport_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7759
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_module_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_identifier" ):
                listener.enterModule_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_identifier" ):
                listener.exitModule_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_identifier" ):
                return visitor.visitModule_identifier(self)
            else:
                return visitor.visitChildren(self)




    def module_identifier(self):

        localctx = SystemVerilogParser.Module_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1186, self.RULE_module_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7761
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_identifier" ):
                listener.enterNet_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_identifier" ):
                listener.exitNet_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_identifier" ):
                return visitor.visitNet_identifier(self)
            else:
                return visitor.visitChildren(self)




    def net_identifier(self):

        localctx = SystemVerilogParser.Net_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1188, self.RULE_net_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7763
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_type_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_net_type_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_type_identifier" ):
                listener.enterNet_type_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_type_identifier" ):
                listener.exitNet_type_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_type_identifier" ):
                return visitor.visitNet_type_identifier(self)
            else:
                return visitor.visitChildren(self)




    def net_type_identifier(self):

        localctx = SystemVerilogParser.Net_type_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1190, self.RULE_net_type_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7765
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_output_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_port_identifier" ):
                listener.enterOutput_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_port_identifier" ):
                listener.exitOutput_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_port_identifier" ):
                return visitor.visitOutput_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def output_port_identifier(self):

        localctx = SystemVerilogParser.Output_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1192, self.RULE_output_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7767
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_package_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_identifier" ):
                listener.enterPackage_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_identifier" ):
                listener.exitPackage_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_identifier" ):
                return visitor.visitPackage_identifier(self)
            else:
                return visitor.visitChildren(self)




    def package_identifier(self):

        localctx = SystemVerilogParser.Package_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1194, self.RULE_package_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7769
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_scopeContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def COLONCOLON(self):
            return self.getToken(SystemVerilogParser.COLONCOLON, 0)

        def package_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_identifierContext,0)


        def DUNIT(self):
            return self.getToken(SystemVerilogParser.DUNIT, 0)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_package_scope

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_scope" ):
                listener.enterPackage_scope(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_scope" ):
                listener.exitPackage_scope(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_scope" ):
                return visitor.visitPackage_scope(self)
            else:
                return visitor.visitChildren(self)




    def package_scope(self):

        localctx = SystemVerilogParser.Package_scopeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1196, self.RULE_package_scope)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7773
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SystemVerilogParser.SIMPLE_IDENTIFIER]:
                self.state = 7771
                self.package_identifier()
                pass
            elif token in [SystemVerilogParser.DUNIT]:
                self.state = 7772
                self.match(SystemVerilogParser.DUNIT)
                pass
            else:
                raise NoViableAltException(self)

            self.state = 7775
            self.match(SystemVerilogParser.COLONCOLON)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_parameter_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_identifier" ):
                listener.enterParameter_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_identifier" ):
                listener.exitParameter_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_identifier" ):
                return visitor.visitParameter_identifier(self)
            else:
                return visitor.visitChildren(self)




    def parameter_identifier(self):

        localctx = SystemVerilogParser.Parameter_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1198, self.RULE_parameter_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7777
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_identifier" ):
                listener.enterPort_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_identifier" ):
                listener.exitPort_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_identifier" ):
                return visitor.visitPort_identifier(self)
            else:
                return visitor.visitChildren(self)




    def port_identifier(self):

        localctx = SystemVerilogParser.Port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1200, self.RULE_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7779
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Production_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_production_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProduction_identifier" ):
                listener.enterProduction_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProduction_identifier" ):
                listener.exitProduction_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProduction_identifier" ):
                return visitor.visitProduction_identifier(self)
            else:
                return visitor.visitChildren(self)




    def production_identifier(self):

        localctx = SystemVerilogParser.Production_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1202, self.RULE_production_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7781
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Program_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_program_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProgram_identifier" ):
                listener.enterProgram_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProgram_identifier" ):
                listener.exitProgram_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProgram_identifier" ):
                return visitor.visitProgram_identifier(self)
            else:
                return visitor.visitChildren(self)




    def program_identifier(self):

        localctx = SystemVerilogParser.Program_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1204, self.RULE_program_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7783
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_property_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_identifier" ):
                listener.enterProperty_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_identifier" ):
                listener.exitProperty_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_identifier" ):
                return visitor.visitProperty_identifier(self)
            else:
                return visitor.visitChildren(self)




    def property_identifier(self):

        localctx = SystemVerilogParser.Property_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1206, self.RULE_property_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7785
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_class_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def class_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_class_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_class_identifier" ):
                listener.enterPs_class_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_class_identifier" ):
                listener.exitPs_class_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_class_identifier" ):
                return visitor.visitPs_class_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_class_identifier(self):

        localctx = SystemVerilogParser.Ps_class_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1208, self.RULE_ps_class_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7788
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,962,self._ctx)
            if la_ == 1:
                self.state = 7787
                self.package_scope()


            self.state = 7790
            self.class_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_covergroup_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def covergroup_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Covergroup_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_covergroup_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_covergroup_identifier" ):
                listener.enterPs_covergroup_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_covergroup_identifier" ):
                listener.exitPs_covergroup_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_covergroup_identifier" ):
                return visitor.visitPs_covergroup_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_covergroup_identifier(self):

        localctx = SystemVerilogParser.Ps_covergroup_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1210, self.RULE_ps_covergroup_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7793
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,963,self._ctx)
            if la_ == 1:
                self.state = 7792
                self.package_scope()


            self.state = 7795
            self.covergroup_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_checker_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def checker_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Checker_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_checker_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_checker_identifier" ):
                listener.enterPs_checker_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_checker_identifier" ):
                listener.exitPs_checker_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_checker_identifier" ):
                return visitor.visitPs_checker_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_checker_identifier(self):

        localctx = SystemVerilogParser.Ps_checker_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1212, self.RULE_ps_checker_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7798
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,964,self._ctx)
            if la_ == 1:
                self.state = 7797
                self.package_scope()


            self.state = 7800
            self.checker_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_identifier" ):
                listener.enterPs_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_identifier" ):
                listener.exitPs_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_identifier" ):
                return visitor.visitPs_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_identifier(self):

        localctx = SystemVerilogParser.Ps_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1214, self.RULE_ps_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7803
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,965,self._ctx)
            if la_ == 1:
                self.state = 7802
                self.package_scope()


            self.state = 7805
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_or_hierarchical_array_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_array_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_array_identifierContext,0)


        def implicit_class_handle(self):
            return self.getTypedRuleContext(SystemVerilogParser.Implicit_class_handleContext,0)


        def DOT(self):
            return self.getToken(SystemVerilogParser.DOT, 0)

        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_or_hierarchical_array_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_or_hierarchical_array_identifier" ):
                listener.enterPs_or_hierarchical_array_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_or_hierarchical_array_identifier" ):
                listener.exitPs_or_hierarchical_array_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_or_hierarchical_array_identifier" ):
                return visitor.visitPs_or_hierarchical_array_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_or_hierarchical_array_identifier(self):

        localctx = SystemVerilogParser.Ps_or_hierarchical_array_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1216, self.RULE_ps_or_hierarchical_array_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7812
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,966,self._ctx)
            if la_ == 1:
                self.state = 7807
                self.implicit_class_handle()
                self.state = 7808
                self.match(SystemVerilogParser.DOT)

            elif la_ == 2:
                self.state = 7810
                self.class_scope()

            elif la_ == 3:
                self.state = 7811
                self.package_scope()


            self.state = 7814
            self.hierarchical_array_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_or_hierarchical_net_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Net_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def hierarchical_net_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_net_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_or_hierarchical_net_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_or_hierarchical_net_identifier" ):
                listener.enterPs_or_hierarchical_net_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_or_hierarchical_net_identifier" ):
                listener.exitPs_or_hierarchical_net_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_or_hierarchical_net_identifier" ):
                return visitor.visitPs_or_hierarchical_net_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_or_hierarchical_net_identifier(self):

        localctx = SystemVerilogParser.Ps_or_hierarchical_net_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1218, self.RULE_ps_or_hierarchical_net_identifier)
        try:
            self.state = 7821
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,968,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7817
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,967,self._ctx)
                if la_ == 1:
                    self.state = 7816
                    self.package_scope()


                self.state = 7819
                self.net_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7820
                self.hierarchical_net_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_or_hierarchical_property_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def property_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Property_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def hierarchical_property_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_property_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_or_hierarchical_property_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_or_hierarchical_property_identifier" ):
                listener.enterPs_or_hierarchical_property_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_or_hierarchical_property_identifier" ):
                listener.exitPs_or_hierarchical_property_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_or_hierarchical_property_identifier" ):
                return visitor.visitPs_or_hierarchical_property_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_or_hierarchical_property_identifier(self):

        localctx = SystemVerilogParser.Ps_or_hierarchical_property_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1220, self.RULE_ps_or_hierarchical_property_identifier)
        try:
            self.state = 7828
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,970,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7824
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,969,self._ctx)
                if la_ == 1:
                    self.state = 7823
                    self.package_scope()


                self.state = 7826
                self.property_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7827
                self.hierarchical_property_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_or_hierarchical_sequence_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def sequence_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Sequence_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def hierarchical_sequence_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_sequence_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_or_hierarchical_sequence_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_or_hierarchical_sequence_identifier" ):
                listener.enterPs_or_hierarchical_sequence_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_or_hierarchical_sequence_identifier" ):
                listener.exitPs_or_hierarchical_sequence_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_or_hierarchical_sequence_identifier" ):
                return visitor.visitPs_or_hierarchical_sequence_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_or_hierarchical_sequence_identifier(self):

        localctx = SystemVerilogParser.Ps_or_hierarchical_sequence_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1222, self.RULE_ps_or_hierarchical_sequence_identifier)
        try:
            self.state = 7835
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,972,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7831
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,971,self._ctx)
                if la_ == 1:
                    self.state = 7830
                    self.package_scope()


                self.state = 7833
                self.sequence_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7834
                self.hierarchical_sequence_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_or_hierarchical_tf_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def tf_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Tf_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def hierarchical_tf_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Hierarchical_tf_identifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_or_hierarchical_tf_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_or_hierarchical_tf_identifier" ):
                listener.enterPs_or_hierarchical_tf_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_or_hierarchical_tf_identifier" ):
                listener.exitPs_or_hierarchical_tf_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_or_hierarchical_tf_identifier" ):
                return visitor.visitPs_or_hierarchical_tf_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_or_hierarchical_tf_identifier(self):

        localctx = SystemVerilogParser.Ps_or_hierarchical_tf_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1224, self.RULE_ps_or_hierarchical_tf_identifier)
        try:
            self.state = 7842
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,974,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7838
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,973,self._ctx)
                if la_ == 1:
                    self.state = 7837
                    self.package_scope()


                self.state = 7840
                self.tf_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7841
                self.hierarchical_tf_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_parameter_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Parameter_identifierContext,0)


        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def generate_block_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Generate_block_identifierContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Generate_block_identifierContext,i)


        def DOT(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.DOT)
            else:
                return self.getToken(SystemVerilogParser.DOT, i)

        def LB(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.LB)
            else:
                return self.getToken(SystemVerilogParser.LB, i)

        def constant_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SystemVerilogParser.Constant_expressionContext)
            else:
                return self.getTypedRuleContext(SystemVerilogParser.Constant_expressionContext,i)


        def RB(self, i:int=None):
            if i is None:
                return self.getTokens(SystemVerilogParser.RB)
            else:
                return self.getToken(SystemVerilogParser.RB, i)

        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_parameter_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_parameter_identifier" ):
                listener.enterPs_parameter_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_parameter_identifier" ):
                listener.exitPs_parameter_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_parameter_identifier" ):
                return visitor.visitPs_parameter_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_parameter_identifier(self):

        localctx = SystemVerilogParser.Ps_parameter_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1226, self.RULE_ps_parameter_identifier)
        self._la = 0 # Token type
        try:
            self.state = 7864
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,978,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 7846
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,975,self._ctx)
                if la_ == 1:
                    self.state = 7844
                    self.package_scope()

                elif la_ == 2:
                    self.state = 7845
                    self.class_scope()


                self.state = 7848
                self.parameter_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 7860
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,977,self._ctx)
                while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                    if _alt==1:
                        self.state = 7849
                        self.generate_block_identifier()
                        self.state = 7854
                        self._errHandler.sync(self)
                        _la = self._input.LA(1)
                        if _la==SystemVerilogParser.LB:
                            self.state = 7850
                            self.match(SystemVerilogParser.LB)
                            self.state = 7851
                            self.constant_expression(0)
                            self.state = 7852
                            self.match(SystemVerilogParser.RB)


                        self.state = 7856
                        self.match(SystemVerilogParser.DOT) 
                    self.state = 7862
                    self._errHandler.sync(self)
                    _alt = self._interp.adaptivePredict(self._input,977,self._ctx)

                self.state = 7863
                self.parameter_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ps_type_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def type_identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.Type_identifierContext,0)


        def KLOCAL(self):
            return self.getToken(SystemVerilogParser.KLOCAL, 0)

        def COLONCOLON(self):
            return self.getToken(SystemVerilogParser.COLONCOLON, 0)

        def package_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Package_scopeContext,0)


        def class_scope(self):
            return self.getTypedRuleContext(SystemVerilogParser.Class_scopeContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_ps_type_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPs_type_identifier" ):
                listener.enterPs_type_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPs_type_identifier" ):
                listener.exitPs_type_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPs_type_identifier" ):
                return visitor.visitPs_type_identifier(self)
            else:
                return visitor.visitChildren(self)




    def ps_type_identifier(self):

        localctx = SystemVerilogParser.Ps_type_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1228, self.RULE_ps_type_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7870
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,979,self._ctx)
            if la_ == 1:
                self.state = 7866
                self.match(SystemVerilogParser.KLOCAL)
                self.state = 7867
                self.match(SystemVerilogParser.COLONCOLON)

            elif la_ == 2:
                self.state = 7868
                self.package_scope()

            elif la_ == 3:
                self.state = 7869
                self.class_scope()


            self.state = 7872
            self.type_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sequence_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_sequence_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSequence_identifier" ):
                listener.enterSequence_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSequence_identifier" ):
                listener.exitSequence_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSequence_identifier" ):
                return visitor.visitSequence_identifier(self)
            else:
                return visitor.visitChildren(self)




    def sequence_identifier(self):

        localctx = SystemVerilogParser.Sequence_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1230, self.RULE_sequence_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7874
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Signal_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_signal_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSignal_identifier" ):
                listener.enterSignal_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSignal_identifier" ):
                listener.exitSignal_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSignal_identifier" ):
                return visitor.visitSignal_identifier(self)
            else:
                return visitor.visitChildren(self)




    def signal_identifier(self):

        localctx = SystemVerilogParser.Signal_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1232, self.RULE_signal_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7876
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Specparam_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_specparam_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSpecparam_identifier" ):
                listener.enterSpecparam_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSpecparam_identifier" ):
                listener.exitSpecparam_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSpecparam_identifier" ):
                return visitor.visitSpecparam_identifier(self)
            else:
                return visitor.visitChildren(self)




    def specparam_identifier(self):

        localctx = SystemVerilogParser.Specparam_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1234, self.RULE_specparam_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7878
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_identifier" ):
                listener.enterTask_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_identifier" ):
                listener.exitTask_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_identifier" ):
                return visitor.visitTask_identifier(self)
            else:
                return visitor.visitChildren(self)




    def task_identifier(self):

        localctx = SystemVerilogParser.Task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1236, self.RULE_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7880
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_tf_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_identifier" ):
                listener.enterTf_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_identifier" ):
                listener.exitTf_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_identifier" ):
                return visitor.visitTf_identifier(self)
            else:
                return visitor.visitChildren(self)




    def tf_identifier(self):

        localctx = SystemVerilogParser.Tf_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1238, self.RULE_tf_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7882
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Topmodule_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_topmodule_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTopmodule_identifier" ):
                listener.enterTopmodule_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTopmodule_identifier" ):
                listener.exitTopmodule_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTopmodule_identifier" ):
                return visitor.visitTopmodule_identifier(self)
            else:
                return visitor.visitChildren(self)




    def topmodule_identifier(self):

        localctx = SystemVerilogParser.Topmodule_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1240, self.RULE_topmodule_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7884
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Type_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_type_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterType_identifier" ):
                listener.enterType_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitType_identifier" ):
                listener.exitType_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitType_identifier" ):
                return visitor.visitType_identifier(self)
            else:
                return visitor.visitChildren(self)




    def type_identifier(self):

        localctx = SystemVerilogParser.Type_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1242, self.RULE_type_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7886
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_identifierContext(ParserRuleContext):
        __slots__ = 'parser'

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SystemVerilogParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SystemVerilogParser.RULE_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_identifier" ):
                listener.enterVariable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_identifier" ):
                listener.exitVariable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_identifier" ):
                return visitor.visitVariable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def variable_identifier(self):

        localctx = SystemVerilogParser.Variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 1244, self.RULE_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 7888
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx



    def sempred(self, localctx:RuleContext, ruleIndex:int, predIndex:int):
        if self._predicates == None:
            self._predicates = dict()
        self._predicates[224] = self.property_expr_sempred
        self._predicates[231] = self.sequence_expr_sempred
        self._predicates[252] = self.block_event_expression_sempred
        self._predicates[270] = self.select_expression_sempred
        self._predicates[367] = self.event_expression_sempred
        self._predicates[507] = self.constant_expression_sempred
        self._predicates[515] = self.expression_sempred
        self._predicates[518] = self.module_path_expression_sempred
        pred = self._predicates.get(ruleIndex, None)
        if pred is None:
            raise Exception("No predicate with index:" + str(ruleIndex))
        else:
            return pred(localctx, predIndex)

    def property_expr_sempred(self, localctx:Property_exprContext, predIndex:int):
            if predIndex == 0:
                return self.precpred(self._ctx, 9)
         

    def sequence_expr_sempred(self, localctx:Sequence_exprContext, predIndex:int):
            if predIndex == 1:
                return self.precpred(self._ctx, 3)
         

            if predIndex == 2:
                return self.precpred(self._ctx, 7)
         

    def block_event_expression_sempred(self, localctx:Block_event_expressionContext, predIndex:int):
            if predIndex == 3:
                return self.precpred(self._ctx, 2)
         

    def select_expression_sempred(self, localctx:Select_expressionContext, predIndex:int):
            if predIndex == 4:
                return self.precpred(self._ctx, 5)
         

            if predIndex == 5:
                return self.precpred(self._ctx, 3)
         

    def event_expression_sempred(self, localctx:Event_expressionContext, predIndex:int):
            if predIndex == 6:
                return self.precpred(self._ctx, 2)
         

    def constant_expression_sempred(self, localctx:Constant_expressionContext, predIndex:int):
            if predIndex == 7:
                return self.precpred(self._ctx, 1)
         

    def expression_sempred(self, localctx:ExpressionContext, predIndex:int):
            if predIndex == 8:
                return self.precpred(self._ctx, 4)
         

            if predIndex == 9:
                return self.precpred(self._ctx, 3)
         

            if predIndex == 10:
                return self.precpred(self._ctx, 2)
         

    def module_path_expression_sempred(self, localctx:Module_path_expressionContext, predIndex:int):
            if predIndex == 11:
                return self.precpred(self._ctx, 2)
         

            if predIndex == 12:
                return self.precpred(self._ctx, 1)
         




