# Generated from SysVerilogHDL.g4 by ANTLR 4.8
# encoding: utf-8
from antlr4 import *
from io import StringIO
import sys
if sys.version_info[1] > 5:
	from typing import TextIO
else:
	from typing.io import TextIO


def serializedATN():
    with StringIO() as buf:
        buf.write("\3\u608b\ua72a\u8133\ub9ed\u417c\u3be7\u7786\u5964\3\u00ea")
        buf.write("\u0c3c\4\2\t\2\4\3\t\3\4\4\t\4\4\5\t\5\4\6\t\6\4\7\t\7")
        buf.write("\4\b\t\b\4\t\t\t\4\n\t\n\4\13\t\13\4\f\t\f\4\r\t\r\4\16")
        buf.write("\t\16\4\17\t\17\4\20\t\20\4\21\t\21\4\22\t\22\4\23\t\23")
        buf.write("\4\24\t\24\4\25\t\25\4\26\t\26\4\27\t\27\4\30\t\30\4\31")
        buf.write("\t\31\4\32\t\32\4\33\t\33\4\34\t\34\4\35\t\35\4\36\t\36")
        buf.write("\4\37\t\37\4 \t \4!\t!\4\"\t\"\4#\t#\4$\t$\4%\t%\4&\t")
        buf.write("&\4\'\t\'\4(\t(\4)\t)\4*\t*\4+\t+\4,\t,\4-\t-\4.\t.\4")
        buf.write("/\t/\4\60\t\60\4\61\t\61\4\62\t\62\4\63\t\63\4\64\t\64")
        buf.write("\4\65\t\65\4\66\t\66\4\67\t\67\48\t8\49\t9\4:\t:\4;\t")
        buf.write(";\4<\t<\4=\t=\4>\t>\4?\t?\4@\t@\4A\tA\4B\tB\4C\tC\4D\t")
        buf.write("D\4E\tE\4F\tF\4G\tG\4H\tH\4I\tI\4J\tJ\4K\tK\4L\tL\4M\t")
        buf.write("M\4N\tN\4O\tO\4P\tP\4Q\tQ\4R\tR\4S\tS\4T\tT\4U\tU\4V\t")
        buf.write("V\4W\tW\4X\tX\4Y\tY\4Z\tZ\4[\t[\4\\\t\\\4]\t]\4^\t^\4")
        buf.write("_\t_\4`\t`\4a\ta\4b\tb\4c\tc\4d\td\4e\te\4f\tf\4g\tg\4")
        buf.write("h\th\4i\ti\4j\tj\4k\tk\4l\tl\4m\tm\4n\tn\4o\to\4p\tp\4")
        buf.write("q\tq\4r\tr\4s\ts\4t\tt\4u\tu\4v\tv\4w\tw\4x\tx\4y\ty\4")
        buf.write("z\tz\4{\t{\4|\t|\4}\t}\4~\t~\4\177\t\177\4\u0080\t\u0080")
        buf.write("\4\u0081\t\u0081\4\u0082\t\u0082\4\u0083\t\u0083\4\u0084")
        buf.write("\t\u0084\4\u0085\t\u0085\4\u0086\t\u0086\4\u0087\t\u0087")
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        buf.write("\u0995\u099b\u09a3\u09af\u09bb\u09d7\u09dc\u09e9\u09ed")
        buf.write("\u09f2\u09f5\u0a02\u0a12\u0a32\u0a41\u0a4a\u0a4d\u0a51")
        buf.write("\u0a63\u0a83\u0a8a\u0a92\u0a9e\u0aa7\u0aaa\u0ab9\u0ac3")
        buf.write("\u0ac9\u0ad9\u0afb\u0b07\u0b15\u0b1d\u0b34\u0b3c\u0b46")
        buf.write("\u0b4c\u0b5a\u0b5e\u0b76\u0b7c\u0b88\u0b8c\u0b90\u0b93")
        buf.write("\u0b9a\u0b9f\u0ba5\u0baa\u0bb0\u0bba\u0bcd\u0bd3\u0bd6")
        buf.write("\u0be1\u0bf9\u0c07\u0c0f\u0c1b\u0c23\u0c35")
        return buf.getvalue()


class SysVerilogHDLParser ( Parser ):

    grammarFileName = "SysVerilogHDL.g4"

    atn = ATNDeserializer().deserialize(serializedATN())

    decisionsToDFA = [ DFA(ds, i) for i, ds in enumerate(atn.decisionToState) ]

    sharedContextCache = PredictionContextCache()

    literalNames = [ "<INVALID>", "';;'", "'+'", "'-'", "'!'", "'&'", "'~&'", 
                     "'|'", "'~|'", "'^'", "'~^'", "'^~'", "'%'", "'=='", 
                     "'!='", "'==='", "'!=='", "'&&'", "'||'", "'**'", "'<'", 
                     "'>'", "'>='", "'>>'", "'<<'", "'>>>'", "'<<<'", "'++'", 
                     "'--'", "'+='", "'-='", "'&='", "'|='", "'\r'", "'//'", 
                     "'/*'", "'\n'", "'*/'", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                     "'always'", "'always_comb'", "'always_ff'", "'and'", 
                     "'assert'", "'assign'", "'automatic'", "'begin'", "'bit'", 
                     "'buf'", "'bufif0'", "'bufif1'", "'byte'", "'case'", 
                     "'casez'", "'casex'", "'cell'", "'cmos'", "'config'", 
                     "'const'", "'deassign'", "'default'", "'`default_nettype'", 
                     "'defparam'", "'design'", "'disable'", "'do'", "'edge'", 
                     "'else'", "'end'", "'endcase'", "'endconfig'", "'endfunction'", 
                     "'endgenerate'", "'endmodule'", "'endpackage'", "'endproperty'", 
                     "'endspecify'", "'endtask'", "'enum'", "'event'", "'final'", 
                     "'for'", "'force'", "'forever'", "'fork'", "'function'", 
                     "'generate'", "'genvar'", "'highz0'", "'highz1'", "'if'", 
                     "'iff'", "'ifnone'", "'import'", "'-incdir'", "'initial'", 
                     "'inout'", "'input'", "'instance'", "'int'", "'integer'", 
                     "'join'", "'join_any'", "'join_none'", "'large'", "'liblist'", 
                     "'`library'", "'localparam'", "'logic'", "'macromodule'", 
                     "'medium'", "'module'", "'nand'", "'negedge'", "'nmos'", 
                     "'none'", "'nor'", "'not'", "'notif0'", "'notif1'", 
                     "'noshowcancelled'", "'or '", "'output'", "'parameter'", 
                     "'PATHPULSE$'", "'posedge'", "'package'", "'packed'", 
                     "'pmos'", "'property'", "'pull0'", "'pull1'", "'pullup'", 
                     "'pulldown'", "'pulsestyle_ondetect'", "'pulsestyle_onevent'", 
                     "'rcmos'", "'real'", "'realtime'", "'ref'", "'reg'", 
                     "'release'", "'repeat'", "'return'", "'rnmos'", "'rpmos'", 
                     "'rtran'", "'rtranif0'", "'rtranif1'", "'scalared'", 
                     "'showcancelled'", "'signed'", "'small'", "'specify'", 
                     "'specparam'", "'static'", "'string'", "'strong0'", 
                     "'strong1'", "'struct'", "'supply0'", "'supply1'", 
                     "'task'", "'`timescale'", "'time'", "'timeprecision'", 
                     "'timeunit'", "'tran'", "'tranif0'", "'tranif1'", "'tri'", 
                     "'triand'", "'trior'", "'trireg'", "'tri0'", "'tri1'", 
                     "'typedef'", "'union'", "'unsigned'", "'use'", "'uwire'", 
                     "'vectored'", "'wait'", "'wand'", "'weak0'", "'weak1'", 
                     "'while'", "'wire'", "'wor'", "'xnor'", "'xor'", "<INVALID>", 
                     "<INVALID>", "<INVALID>", "<INVALID>", "'@'", "')'", 
                     "':'", "','", "'->'", "'.'", "'$'", "'::'", "'='", 
                     "'=>'", "'/'", "'#'", "'<='", "'['", "'{'", "'-:'", 
                     "'('", "'+:'", "'?'", "'''", "']'", "'}'", "';'", "'*'", 
                     "'*>'", "'~'" ]

    symbolicNames = [ "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                      "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                      "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                      "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                      "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                      "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                      "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                      "<INVALID>", "<INVALID>", "<INVALID>", "<INVALID>", 
                      "<INVALID>", "Carriage_return", "Forward_slash_forward_slash", 
                      "Forward_slash_star", "New_line", "Star_forward_slash", 
                      "Block_comment", "Line_directive", "One_line_comment", 
                      "WHITE_SPACE", "Binary_number", "Decimal_number", 
                      "Fixed_point_number", "Hex_number", "Octal_number", 
                      "Real_exp_form", "Unbased_unsized_literal", "Always", 
                      "Always_comb", "Always_ff", "And", "Assert", "Assign", 
                      "Automatic", "Begin", "Bit", "Buf", "Bufif0", "Bufif1", 
                      "Byte", "Case_keyword", "Casez", "Casex", "Cell", 
                      "Cmos", "Config", "Const", "Deassign", "Default", 
                      "Default_nettype", "Defparam", "Design", "Disable", 
                      "Do", "Edge", "Else", "End", "Endcase", "Endconfig", 
                      "Endfunction", "Endgenerate", "Endmodule", "Endpackage", 
                      "Endproperty", "Endspecify", "Endtask", "Enum", "Event_keyword", 
                      "Final", "For", "Force", "Forever", "Fork", "Function", 
                      "Generate", "Genvar", "Highz0", "Highz1", "If", "Iff", 
                      "Ifnone", "Import", "Incdir", "Initial", "Inout", 
                      "Input", "Instance", "Int", "Integer", "Join", "Join_any", 
                      "Join_none", "Large", "Liblist", "Library", "Localparam", 
                      "Logic", "Macromodule", "Medium", "Module_keyword_only", 
                      "Nand", "Negedge", "Nmos", "NONE", "Nor", "Not", "Notif0", 
                      "Notif1", "Noshowcancelled", "Or", "Output", "Parameter", 
                      "Path_pulse_dollar", "Posedge", "Package", "Packed", 
                      "Pmos", "Property", "Pull0", "Pull1", "Pullup", "Pulldown", 
                      "Pulsestyle_ondetect", "Pulsestyle_onevent", "Rcmos", 
                      "Real", "Realtime", "Ref", "Reg", "Release", "Repeat", 
                      "Return", "Rnmos", "Rpmos", "Rtran", "Rtranif0", "Rtranif1", 
                      "Scalared", "Showcancelled", "Signed", "Small", "Specify", 
                      "Specparam", "Static", "SVString", "Strong0", "Strong1", 
                      "Struct", "Supply0", "Supply1", "Task", "Tick_timescale", 
                      "Time", "Timeprecision", "Timeunit", "Tran", "Tranif0", 
                      "Tranif1", "Tri", "Tri_and", "Tri_or", "Tri_reg", 
                      "Tri0", "Tri1", "Typedef", "UnionStruct", "Unsigned", 
                      "Use", "Uwire", "Vectored", "Wait", "Wand", "Weak0", 
                      "Weak1", "While", "Wire", "Wor", "Xnor", "Xor", "Dollar_Identifier", 
                      "Escaped_identifier", "Simple_identifier", "String_literal", 
                      "At", "Close_parenthesis", "Colon", "Comma", "Dash_right_angle", 
                      "Dot", "Dollar", "Double_colon", "Equal", "Equals_right_angle", 
                      "Forward_slash", "Hash", "Left_angle_equals", "Left_bracket", 
                      "Left_curly_bracket", "Minus_colon", "Open_parenthesis", 
                      "Plus_colon", "Question_mark", "Quote", "Right_bracket", 
                      "Right_curly_bracket", "Semicolon", "Star", "Star_right_angle", 
                      "Tilde", "Time_literal", "Edge_control_specifier" ]

    RULE_module_keyword = 0
    RULE_struct_keyword = 1
    RULE_any_case_keyword = 2
    RULE_semicolon = 3
    RULE_unary_operator = 4
    RULE_binary_operator = 5
    RULE_unary_assign_operator = 6
    RULE_binary_assign_operator = 7
    RULE_source_text = 8
    RULE_description_star = 9
    RULE_header_text = 10
    RULE_design_attribute = 11
    RULE_compiler_directive = 12
    RULE_description = 13
    RULE_module_declaration = 14
    RULE_module_identifier = 15
    RULE_module_interface = 16
    RULE_module_parameter_interface = 17
    RULE_module_port_interface = 18
    RULE_module_item_star = 19
    RULE_module_item = 20
    RULE_colon_module_identifier = 21
    RULE_package_declaration = 22
    RULE_package_identifier = 23
    RULE_colon_package_identifier = 24
    RULE_package_item_star = 25
    RULE_package_item = 26
    RULE_import_package = 27
    RULE_package_item_identifier = 28
    RULE_parameter_item_semicolon = 29
    RULE_parameter_item = 30
    RULE_attr_port_item_semicolon = 31
    RULE_attr_variable_item_semicolon = 32
    RULE_variable_item = 33
    RULE_subroutine_item_semicolon = 34
    RULE_subroutine_item = 35
    RULE_attr_construct_item = 36
    RULE_construct_item = 37
    RULE_attr_component_item = 38
    RULE_component_item = 39
    RULE_compiler_item = 40
    RULE_type_item = 41
    RULE_null_item = 42
    RULE_list_of_interface_parameters = 43
    RULE_list_of_parameter_declarations = 44
    RULE_comma_parameter_declaration_star = 45
    RULE_comma_parameter_declaration = 46
    RULE_list_of_parameter_descriptions = 47
    RULE_param_declaration = 48
    RULE_param_description = 49
    RULE_parameter_declaration = 50
    RULE_local_parameter_declaration = 51
    RULE_parameter_override = 52
    RULE_list_of_tf_interface_ports = 53
    RULE_list_of_tf_port_declarations = 54
    RULE_list_of_tf_port_declarations_comma = 55
    RULE_comma_attr_tf_port_declaration_star = 56
    RULE_comma_attr_tf_port_declaration = 57
    RULE_list_of_tf_port_declarations_semicolon = 58
    RULE_attr_tf_port_declaration_semicolon_plus = 59
    RULE_attr_tf_port_declaration_semicolon_star = 60
    RULE_attr_tf_port_declaration_semicolon = 61
    RULE_attr_tf_port_declaration = 62
    RULE_tf_port_declaration = 63
    RULE_list_of_interface_ports = 64
    RULE_list_of_port_identifiers = 65
    RULE_comma_port_identifier_star = 66
    RULE_comma_port_identifier = 67
    RULE_port_identifier = 68
    RULE_list_of_port_declarations = 69
    RULE_list_of_port_declarations_comma = 70
    RULE_comma_attr_port_declaration_star = 71
    RULE_comma_attr_port_declaration = 72
    RULE_list_of_port_declarations_semicolon = 73
    RULE_attr_port_declaration_semicolon_plus = 74
    RULE_attr_port_declaration_semicolon_star = 75
    RULE_attr_port_declaration_semicolon = 76
    RULE_attr_port_declaration = 77
    RULE_port_declaration = 78
    RULE_port_description = 79
    RULE_inout_description = 80
    RULE_input_description = 81
    RULE_output_description = 82
    RULE_ref_description = 83
    RULE_tf_declaration = 84
    RULE_inout_declaration = 85
    RULE_input_declaration = 86
    RULE_output_declaration = 87
    RULE_ref_declaration = 88
    RULE_user_type = 89
    RULE_user_type_identifer = 90
    RULE_dimension_plus = 91
    RULE_dimension_star = 92
    RULE_dimension = 93
    RULE_range_expression = 94
    RULE_index_expression = 95
    RULE_sb_range = 96
    RULE_base_increment_range = 97
    RULE_base_decrement_range = 98
    RULE_base_expression = 99
    RULE_net_type = 100
    RULE_drive_strength = 101
    RULE_drive_strength_value_0 = 102
    RULE_drive_strength_value_1 = 103
    RULE_strength0 = 104
    RULE_strength1 = 105
    RULE_highz0 = 106
    RULE_highz1 = 107
    RULE_charge_strength = 108
    RULE_charge_size = 109
    RULE_list_of_variable_descriptions = 110
    RULE_comma_variable_description_star = 111
    RULE_comma_variable_description = 112
    RULE_variable_description = 113
    RULE_variable_identifier = 114
    RULE_list_of_hierarchical_variable_descriptions = 115
    RULE_comma_hierarchical_variable_description_star = 116
    RULE_comma_hierarchical_variable_description = 117
    RULE_hierarchical_variable_description = 118
    RULE_hierarchical_variable_identifier = 119
    RULE_net_declaration = 120
    RULE_reg_declaration = 121
    RULE_logic_declaration = 122
    RULE_bits_type = 123
    RULE_bits_declaration = 124
    RULE_integer_declaration = 125
    RULE_int_declaration = 126
    RULE_real_declaration = 127
    RULE_time_declaration = 128
    RULE_realtime_declaration = 129
    RULE_event_declaration = 130
    RULE_genvar_declaration = 131
    RULE_usertype_variable_declaration = 132
    RULE_string_declaration = 133
    RULE_struct_declaration = 134
    RULE_enum_declaration = 135
    RULE_function_declaration = 136
    RULE_function_type = 137
    RULE_function_identifier = 138
    RULE_function_interface = 139
    RULE_function_item_declaration_star = 140
    RULE_function_item_declaration_semicolon = 141
    RULE_function_item_declaration = 142
    RULE_function_statement = 143
    RULE_colon_function_identifier = 144
    RULE_task_declaration = 145
    RULE_task_identifier = 146
    RULE_task_interface = 147
    RULE_task_item_declaration_semicolon = 148
    RULE_task_item_declaration = 149
    RULE_task_item_declaration_star = 150
    RULE_task_statement = 151
    RULE_struct_item_semicolon = 152
    RULE_struct_item_star = 153
    RULE_struct_item = 154
    RULE_struct_type = 155
    RULE_enum_type = 156
    RULE_list_of_enum_items = 157
    RULE_enum_item = 158
    RULE_enum_identifier = 159
    RULE_comma_enum_item_star = 160
    RULE_comma_enum_item = 161
    RULE_enumerated_type = 162
    RULE_module_instantiation = 163
    RULE_parameter_interface_assignments = 164
    RULE_list_of_interface_assignments = 165
    RULE_list_of_ordered_interface_assignments = 166
    RULE_comma_ordered_interface_assignment_star = 167
    RULE_comma_ordered_interface_assignment = 168
    RULE_ordered_interface_assignment = 169
    RULE_list_of_named_interface_assignments = 170
    RULE_comma_named_interface_assignment_star = 171
    RULE_comma_named_interface_assignment = 172
    RULE_named_interface_assignment = 173
    RULE_list_of_module_instances = 174
    RULE_comma_module_instance_star = 175
    RULE_comma_module_instance = 176
    RULE_module_instance = 177
    RULE_module_instance_identifier = 178
    RULE_arrayed_identifier = 179
    RULE_simple_arrayed_identifier = 180
    RULE_escaped_arrayed_identifier = 181
    RULE_port_interface_assignments = 182
    RULE_delay = 183
    RULE_list_of_delay_values = 184
    RULE_comma_delay_value_star = 185
    RULE_comma_delay_value = 186
    RULE_delay_value = 187
    RULE_pulldown_strength = 188
    RULE_pullup_strength = 189
    RULE_gate_instance_identifier = 190
    RULE_gate_instantiation = 191
    RULE_enable_gatetype = 192
    RULE_mos_switchtype = 193
    RULE_cmos_switchtype = 194
    RULE_n_output_gatetype = 195
    RULE_n_input_gatetype = 196
    RULE_pass_switchtype = 197
    RULE_pass_enable_switchtype = 198
    RULE_pulldown_instantiation = 199
    RULE_pullup_instantiation = 200
    RULE_enable_instantiation = 201
    RULE_mos_instantiation = 202
    RULE_cmos_instantiation = 203
    RULE_n_output_instantiation = 204
    RULE_n_input_instantiation = 205
    RULE_pass_instantiation = 206
    RULE_pass_enable_instantiation = 207
    RULE_list_of_pull_gate_instance = 208
    RULE_list_of_enable_gate_instance = 209
    RULE_list_of_mos_switch_instance = 210
    RULE_list_of_cmos_switch_instance = 211
    RULE_list_of_n_input_gate_instance = 212
    RULE_list_of_n_output_gate_instance = 213
    RULE_list_of_pass_switch_instance = 214
    RULE_list_of_pass_enable_switch_instance = 215
    RULE_comma_pull_gate_instance_star = 216
    RULE_comma_enable_gate_instance_star = 217
    RULE_comma_mos_switch_instance_star = 218
    RULE_comma_cmos_switch_instance_star = 219
    RULE_comma_n_input_gate_instance_star = 220
    RULE_comma_n_output_gate_instance_star = 221
    RULE_comma_pass_switch_instance_star = 222
    RULE_comma_pass_enable_switch_instance_star = 223
    RULE_comma_pull_gate_instance = 224
    RULE_comma_enable_gate_instance = 225
    RULE_comma_mos_switch_instance = 226
    RULE_comma_cmos_switch_instance = 227
    RULE_comma_n_input_gate_instance = 228
    RULE_comma_n_output_gate_instance = 229
    RULE_comma_pass_switch_instance = 230
    RULE_comma_pass_enable_switch_instance = 231
    RULE_pull_gate_instance = 232
    RULE_enable_gate_instance = 233
    RULE_mos_switch_instance = 234
    RULE_cmos_switch_instance = 235
    RULE_n_input_gate_instance = 236
    RULE_n_output_gate_instance = 237
    RULE_pass_switch_instance = 238
    RULE_pass_enable_switch_instance = 239
    RULE_pull_gate_interface = 240
    RULE_enable_gate_interface = 241
    RULE_mos_switch_interface = 242
    RULE_cmos_switch_interface = 243
    RULE_n_input_gate_interface = 244
    RULE_n_output_gate_interface = 245
    RULE_pass_switch_interface = 246
    RULE_pass_enable_switch_interface = 247
    RULE_list_of_input_terminals = 248
    RULE_list_of_output_terminals = 249
    RULE_comma_input_terminal_star = 250
    RULE_comma_output_terminal_star = 251
    RULE_comma_input_terminal = 252
    RULE_comma_output_terminal = 253
    RULE_enable_terminal = 254
    RULE_input_terminal = 255
    RULE_inout_terminal = 256
    RULE_ncontrol_terminal = 257
    RULE_output_terminal = 258
    RULE_pcontrol_terminal = 259
    RULE_statement_star = 260
    RULE_statement_semicolon = 261
    RULE_statement = 262
    RULE_assignment_statement = 263
    RULE_flow_control_statement = 264
    RULE_block_statement = 265
    RULE_task_call_statement = 266
    RULE_event_statement = 267
    RULE_procedural_statement = 268
    RULE_expression_statement = 269
    RULE_subroutine_statement = 270
    RULE_return_statement = 271
    RULE_null_statement = 272
    RULE_procedural_continuous_assignments = 273
    RULE_assign_statement = 274
    RULE_deassign_statement = 275
    RULE_force_statement = 276
    RULE_release_statement = 277
    RULE_procedural_timing_control_statement = 278
    RULE_property_statement = 279
    RULE_disable_condition_statement = 280
    RULE_property_expression = 281
    RULE_procedural_assertion_statement = 282
    RULE_assert_else_statement = 283
    RULE_assert_statement = 284
    RULE_system_task_enable = 285
    RULE_system_task_identifier = 286
    RULE_task_interface_assignments = 287
    RULE_task_enable = 288
    RULE_hierarchical_task_identifier = 289
    RULE_disable_statement = 290
    RULE_hierarchical_block_identifier = 291
    RULE_variable_lvalue = 292
    RULE_hierarchical_variable_lvalue = 293
    RULE_variable_concatenation = 294
    RULE_variable_concatenation_value = 295
    RULE_comma_vcv_star = 296
    RULE_blocking_assignment = 297
    RULE_nonblocking_assignment = 298
    RULE_prefix_assignment = 299
    RULE_postfix_assignment = 300
    RULE_operator_assignment = 301
    RULE_declarative_assignment = 302
    RULE_delay_or_event_control = 303
    RULE_delay_control = 304
    RULE_event_control = 305
    RULE_event_control_identifier = 306
    RULE_event_control_expression = 307
    RULE_event_expression = 308
    RULE_single_event_expression = 309
    RULE_event_expression_edgespec = 310
    RULE_event_expression_or = 311
    RULE_list_of_event_expression_comma = 312
    RULE_comma_event_expression_star = 313
    RULE_comma_event_expression = 314
    RULE_list_of_event_expression_or = 315
    RULE_or_event_expression_star = 316
    RULE_or_event_expression = 317
    RULE_event_control_wildcard = 318
    RULE_repeat_event_control = 319
    RULE_event_trigger = 320
    RULE_hierarchical_event_identifier = 321
    RULE_event_identifier = 322
    RULE_wait_statement = 323
    RULE_attr_generated_instantiation = 324
    RULE_generated_instantiation = 325
    RULE_generate_item_star = 326
    RULE_generate_item = 327
    RULE_generate_block = 328
    RULE_generate_colon_block_identifier0 = 329
    RULE_generate_colon_block_identifier1 = 330
    RULE_generate_colon_block_identifier = 331
    RULE_generate_block_identifier = 332
    RULE_generate_conditional_statement = 333
    RULE_generate_if_statement = 334
    RULE_generate_else_statement = 335
    RULE_generate_loop_statement = 336
    RULE_generate_forever_loop_statement = 337
    RULE_generate_repeat_loop_statement = 338
    RULE_generate_while_loop_statement = 339
    RULE_generate_do_loop_statement = 340
    RULE_generate_for_loop_statement = 341
    RULE_generate_case_statement = 342
    RULE_generate_case_item_star = 343
    RULE_generate_case_item = 344
    RULE_conditional_statement = 345
    RULE_if_statement = 346
    RULE_else_statement = 347
    RULE_conditional_expression = 348
    RULE_loop_statement = 349
    RULE_forever_loop_statement = 350
    RULE_repeat_loop_statement = 351
    RULE_while_loop_statement = 352
    RULE_do_loop_statement = 353
    RULE_for_loop_statement = 354
    RULE_loop_init_assignment = 355
    RULE_loop_terminate_expression = 356
    RULE_loop_step_assignment = 357
    RULE_case_statement = 358
    RULE_case_item_star = 359
    RULE_case_item = 360
    RULE_case_switch = 361
    RULE_case_item_key = 362
    RULE_case_item_key_expression = 363
    RULE_comma_case_item_key_expression = 364
    RULE_comma_case_item_key_expression_star = 365
    RULE_expression = 366
    RULE_single_expression = 367
    RULE_primary_range = 368
    RULE_primary = 369
    RULE_unary_expression = 370
    RULE_unary_post_assign_expression = 371
    RULE_unary_pre_assign_expression = 372
    RULE_binary_expression = 373
    RULE_ternary_expression = 374
    RULE_mintypmax_expression = 375
    RULE_structured_value = 376
    RULE_arrayed_structured_value = 377
    RULE_arrayed_structure_item = 378
    RULE_comma_arrayed_structure_item = 379
    RULE_comma_arrayed_structure_item_star = 380
    RULE_arrayed_structure_item_plus = 381
    RULE_variable_type_cast = 382
    RULE_width_type_cast = 383
    RULE_sign_type_cast = 384
    RULE_null_type_cast = 385
    RULE_variable_type = 386
    RULE_type_cast_identifier = 387
    RULE_type_cast_expression = 388
    RULE_function_call = 389
    RULE_hierarchical_function_identifier = 390
    RULE_function_interface_assignments = 391
    RULE_system_function_call = 392
    RULE_system_function_identifier = 393
    RULE_constant_function_call = 394
    RULE_imported_function_call = 395
    RULE_imported_function_hierarchical_identifier = 396
    RULE_primary_hierarchical_identifier = 397
    RULE_primary_imported_hierarchical_identifier = 398
    RULE_imported_hierarchical_identifier = 399
    RULE_parenthesis_expression = 400
    RULE_concatenation = 401
    RULE_multiple_concatenation = 402
    RULE_comma_expression_plus = 403
    RULE_comma_expression_star = 404
    RULE_typedef_declaration = 405
    RULE_typedef_identifier = 406
    RULE_typedef_definition = 407
    RULE_typedef_definition_type = 408
    RULE_complex_type = 409
    RULE_typedef_type = 410
    RULE_par_block = 411
    RULE_seq_block = 412
    RULE_block_identifier = 413
    RULE_colon_block_identifier = 414
    RULE_block_item_declaration_star = 415
    RULE_block_item_declaration_semicolon = 416
    RULE_block_item_declaration = 417
    RULE_join_keyword = 418
    RULE_continuous_assign = 419
    RULE_list_of_variable_assignments = 420
    RULE_comma_variable_assignment_star = 421
    RULE_comma_variable_assignment = 422
    RULE_variable_assignment = 423
    RULE_initial_construct = 424
    RULE_final_construct = 425
    RULE_always_keyword = 426
    RULE_always_construct = 427
    RULE_attribute_instance_star = 428
    RULE_attribute_instance = 429
    RULE_attr_spec_star = 430
    RULE_attr_spec = 431
    RULE_attr_name = 432
    RULE_identifier = 433
    RULE_hierarchical_identifier = 434
    RULE_dot_hierarchical_identifier_branch_item_star = 435
    RULE_dot_hierarchical_identifier_branch_item = 436
    RULE_hierarchical_identifier_branch_item = 437
    RULE_timescale_compiler_directive = 438
    RULE_timeunit_directive = 439
    RULE_timeprecision_directive = 440
    RULE_default_nettype_statement = 441
    RULE_number = 442
    RULE_integral_number = 443
    RULE_real_number = 444

    ruleNames =  [ "module_keyword", "struct_keyword", "any_case_keyword", 
                   "semicolon", "unary_operator", "binary_operator", "unary_assign_operator", 
                   "binary_assign_operator", "source_text", "description_star", 
                   "header_text", "design_attribute", "compiler_directive", 
                   "description", "module_declaration", "module_identifier", 
                   "module_interface", "module_parameter_interface", "module_port_interface", 
                   "module_item_star", "module_item", "colon_module_identifier", 
                   "package_declaration", "package_identifier", "colon_package_identifier", 
                   "package_item_star", "package_item", "import_package", 
                   "package_item_identifier", "parameter_item_semicolon", 
                   "parameter_item", "attr_port_item_semicolon", "attr_variable_item_semicolon", 
                   "variable_item", "subroutine_item_semicolon", "subroutine_item", 
                   "attr_construct_item", "construct_item", "attr_component_item", 
                   "component_item", "compiler_item", "type_item", "null_item", 
                   "list_of_interface_parameters", "list_of_parameter_declarations", 
                   "comma_parameter_declaration_star", "comma_parameter_declaration", 
                   "list_of_parameter_descriptions", "param_declaration", 
                   "param_description", "parameter_declaration", "local_parameter_declaration", 
                   "parameter_override", "list_of_tf_interface_ports", "list_of_tf_port_declarations", 
                   "list_of_tf_port_declarations_comma", "comma_attr_tf_port_declaration_star", 
                   "comma_attr_tf_port_declaration", "list_of_tf_port_declarations_semicolon", 
                   "attr_tf_port_declaration_semicolon_plus", "attr_tf_port_declaration_semicolon_star", 
                   "attr_tf_port_declaration_semicolon", "attr_tf_port_declaration", 
                   "tf_port_declaration", "list_of_interface_ports", "list_of_port_identifiers", 
                   "comma_port_identifier_star", "comma_port_identifier", 
                   "port_identifier", "list_of_port_declarations", "list_of_port_declarations_comma", 
                   "comma_attr_port_declaration_star", "comma_attr_port_declaration", 
                   "list_of_port_declarations_semicolon", "attr_port_declaration_semicolon_plus", 
                   "attr_port_declaration_semicolon_star", "attr_port_declaration_semicolon", 
                   "attr_port_declaration", "port_declaration", "port_description", 
                   "inout_description", "input_description", "output_description", 
                   "ref_description", "tf_declaration", "inout_declaration", 
                   "input_declaration", "output_declaration", "ref_declaration", 
                   "user_type", "user_type_identifer", "dimension_plus", 
                   "dimension_star", "dimension", "range_expression", "index_expression", 
                   "sb_range", "base_increment_range", "base_decrement_range", 
                   "base_expression", "net_type", "drive_strength", "drive_strength_value_0", 
                   "drive_strength_value_1", "strength0", "strength1", "highz0", 
                   "highz1", "charge_strength", "charge_size", "list_of_variable_descriptions", 
                   "comma_variable_description_star", "comma_variable_description", 
                   "variable_description", "variable_identifier", "list_of_hierarchical_variable_descriptions", 
                   "comma_hierarchical_variable_description_star", "comma_hierarchical_variable_description", 
                   "hierarchical_variable_description", "hierarchical_variable_identifier", 
                   "net_declaration", "reg_declaration", "logic_declaration", 
                   "bits_type", "bits_declaration", "integer_declaration", 
                   "int_declaration", "real_declaration", "time_declaration", 
                   "realtime_declaration", "event_declaration", "genvar_declaration", 
                   "usertype_variable_declaration", "string_declaration", 
                   "struct_declaration", "enum_declaration", "function_declaration", 
                   "function_type", "function_identifier", "function_interface", 
                   "function_item_declaration_star", "function_item_declaration_semicolon", 
                   "function_item_declaration", "function_statement", "colon_function_identifier", 
                   "task_declaration", "task_identifier", "task_interface", 
                   "task_item_declaration_semicolon", "task_item_declaration", 
                   "task_item_declaration_star", "task_statement", "struct_item_semicolon", 
                   "struct_item_star", "struct_item", "struct_type", "enum_type", 
                   "list_of_enum_items", "enum_item", "enum_identifier", 
                   "comma_enum_item_star", "comma_enum_item", "enumerated_type", 
                   "module_instantiation", "parameter_interface_assignments", 
                   "list_of_interface_assignments", "list_of_ordered_interface_assignments", 
                   "comma_ordered_interface_assignment_star", "comma_ordered_interface_assignment", 
                   "ordered_interface_assignment", "list_of_named_interface_assignments", 
                   "comma_named_interface_assignment_star", "comma_named_interface_assignment", 
                   "named_interface_assignment", "list_of_module_instances", 
                   "comma_module_instance_star", "comma_module_instance", 
                   "module_instance", "module_instance_identifier", "arrayed_identifier", 
                   "simple_arrayed_identifier", "escaped_arrayed_identifier", 
                   "port_interface_assignments", "delay", "list_of_delay_values", 
                   "comma_delay_value_star", "comma_delay_value", "delay_value", 
                   "pulldown_strength", "pullup_strength", "gate_instance_identifier", 
                   "gate_instantiation", "enable_gatetype", "mos_switchtype", 
                   "cmos_switchtype", "n_output_gatetype", "n_input_gatetype", 
                   "pass_switchtype", "pass_enable_switchtype", "pulldown_instantiation", 
                   "pullup_instantiation", "enable_instantiation", "mos_instantiation", 
                   "cmos_instantiation", "n_output_instantiation", "n_input_instantiation", 
                   "pass_instantiation", "pass_enable_instantiation", "list_of_pull_gate_instance", 
                   "list_of_enable_gate_instance", "list_of_mos_switch_instance", 
                   "list_of_cmos_switch_instance", "list_of_n_input_gate_instance", 
                   "list_of_n_output_gate_instance", "list_of_pass_switch_instance", 
                   "list_of_pass_enable_switch_instance", "comma_pull_gate_instance_star", 
                   "comma_enable_gate_instance_star", "comma_mos_switch_instance_star", 
                   "comma_cmos_switch_instance_star", "comma_n_input_gate_instance_star", 
                   "comma_n_output_gate_instance_star", "comma_pass_switch_instance_star", 
                   "comma_pass_enable_switch_instance_star", "comma_pull_gate_instance", 
                   "comma_enable_gate_instance", "comma_mos_switch_instance", 
                   "comma_cmos_switch_instance", "comma_n_input_gate_instance", 
                   "comma_n_output_gate_instance", "comma_pass_switch_instance", 
                   "comma_pass_enable_switch_instance", "pull_gate_instance", 
                   "enable_gate_instance", "mos_switch_instance", "cmos_switch_instance", 
                   "n_input_gate_instance", "n_output_gate_instance", "pass_switch_instance", 
                   "pass_enable_switch_instance", "pull_gate_interface", 
                   "enable_gate_interface", "mos_switch_interface", "cmos_switch_interface", 
                   "n_input_gate_interface", "n_output_gate_interface", 
                   "pass_switch_interface", "pass_enable_switch_interface", 
                   "list_of_input_terminals", "list_of_output_terminals", 
                   "comma_input_terminal_star", "comma_output_terminal_star", 
                   "comma_input_terminal", "comma_output_terminal", "enable_terminal", 
                   "input_terminal", "inout_terminal", "ncontrol_terminal", 
                   "output_terminal", "pcontrol_terminal", "statement_star", 
                   "statement_semicolon", "statement", "assignment_statement", 
                   "flow_control_statement", "block_statement", "task_call_statement", 
                   "event_statement", "procedural_statement", "expression_statement", 
                   "subroutine_statement", "return_statement", "null_statement", 
                   "procedural_continuous_assignments", "assign_statement", 
                   "deassign_statement", "force_statement", "release_statement", 
                   "procedural_timing_control_statement", "property_statement", 
                   "disable_condition_statement", "property_expression", 
                   "procedural_assertion_statement", "assert_else_statement", 
                   "assert_statement", "system_task_enable", "system_task_identifier", 
                   "task_interface_assignments", "task_enable", "hierarchical_task_identifier", 
                   "disable_statement", "hierarchical_block_identifier", 
                   "variable_lvalue", "hierarchical_variable_lvalue", "variable_concatenation", 
                   "variable_concatenation_value", "comma_vcv_star", "blocking_assignment", 
                   "nonblocking_assignment", "prefix_assignment", "postfix_assignment", 
                   "operator_assignment", "declarative_assignment", "delay_or_event_control", 
                   "delay_control", "event_control", "event_control_identifier", 
                   "event_control_expression", "event_expression", "single_event_expression", 
                   "event_expression_edgespec", "event_expression_or", "list_of_event_expression_comma", 
                   "comma_event_expression_star", "comma_event_expression", 
                   "list_of_event_expression_or", "or_event_expression_star", 
                   "or_event_expression", "event_control_wildcard", "repeat_event_control", 
                   "event_trigger", "hierarchical_event_identifier", "event_identifier", 
                   "wait_statement", "attr_generated_instantiation", "generated_instantiation", 
                   "generate_item_star", "generate_item", "generate_block", 
                   "generate_colon_block_identifier0", "generate_colon_block_identifier1", 
                   "generate_colon_block_identifier", "generate_block_identifier", 
                   "generate_conditional_statement", "generate_if_statement", 
                   "generate_else_statement", "generate_loop_statement", 
                   "generate_forever_loop_statement", "generate_repeat_loop_statement", 
                   "generate_while_loop_statement", "generate_do_loop_statement", 
                   "generate_for_loop_statement", "generate_case_statement", 
                   "generate_case_item_star", "generate_case_item", "conditional_statement", 
                   "if_statement", "else_statement", "conditional_expression", 
                   "loop_statement", "forever_loop_statement", "repeat_loop_statement", 
                   "while_loop_statement", "do_loop_statement", "for_loop_statement", 
                   "loop_init_assignment", "loop_terminate_expression", 
                   "loop_step_assignment", "case_statement", "case_item_star", 
                   "case_item", "case_switch", "case_item_key", "case_item_key_expression", 
                   "comma_case_item_key_expression", "comma_case_item_key_expression_star", 
                   "expression", "single_expression", "primary_range", "primary", 
                   "unary_expression", "unary_post_assign_expression", "unary_pre_assign_expression", 
                   "binary_expression", "ternary_expression", "mintypmax_expression", 
                   "structured_value", "arrayed_structured_value", "arrayed_structure_item", 
                   "comma_arrayed_structure_item", "comma_arrayed_structure_item_star", 
                   "arrayed_structure_item_plus", "variable_type_cast", 
                   "width_type_cast", "sign_type_cast", "null_type_cast", 
                   "variable_type", "type_cast_identifier", "type_cast_expression", 
                   "function_call", "hierarchical_function_identifier", 
                   "function_interface_assignments", "system_function_call", 
                   "system_function_identifier", "constant_function_call", 
                   "imported_function_call", "imported_function_hierarchical_identifier", 
                   "primary_hierarchical_identifier", "primary_imported_hierarchical_identifier", 
                   "imported_hierarchical_identifier", "parenthesis_expression", 
                   "concatenation", "multiple_concatenation", "comma_expression_plus", 
                   "comma_expression_star", "typedef_declaration", "typedef_identifier", 
                   "typedef_definition", "typedef_definition_type", "complex_type", 
                   "typedef_type", "par_block", "seq_block", "block_identifier", 
                   "colon_block_identifier", "block_item_declaration_star", 
                   "block_item_declaration_semicolon", "block_item_declaration", 
                   "join_keyword", "continuous_assign", "list_of_variable_assignments", 
                   "comma_variable_assignment_star", "comma_variable_assignment", 
                   "variable_assignment", "initial_construct", "final_construct", 
                   "always_keyword", "always_construct", "attribute_instance_star", 
                   "attribute_instance", "attr_spec_star", "attr_spec", 
                   "attr_name", "identifier", "hierarchical_identifier", 
                   "dot_hierarchical_identifier_branch_item_star", "dot_hierarchical_identifier_branch_item", 
                   "hierarchical_identifier_branch_item", "timescale_compiler_directive", 
                   "timeunit_directive", "timeprecision_directive", "default_nettype_statement", 
                   "number", "integral_number", "real_number" ]

    EOF = Token.EOF
    T__0=1
    T__1=2
    T__2=3
    T__3=4
    T__4=5
    T__5=6
    T__6=7
    T__7=8
    T__8=9
    T__9=10
    T__10=11
    T__11=12
    T__12=13
    T__13=14
    T__14=15
    T__15=16
    T__16=17
    T__17=18
    T__18=19
    T__19=20
    T__20=21
    T__21=22
    T__22=23
    T__23=24
    T__24=25
    T__25=26
    T__26=27
    T__27=28
    T__28=29
    T__29=30
    T__30=31
    T__31=32
    Carriage_return=33
    Forward_slash_forward_slash=34
    Forward_slash_star=35
    New_line=36
    Star_forward_slash=37
    Block_comment=38
    Line_directive=39
    One_line_comment=40
    WHITE_SPACE=41
    Binary_number=42
    Decimal_number=43
    Fixed_point_number=44
    Hex_number=45
    Octal_number=46
    Real_exp_form=47
    Unbased_unsized_literal=48
    Always=49
    Always_comb=50
    Always_ff=51
    And=52
    Assert=53
    Assign=54
    Automatic=55
    Begin=56
    Bit=57
    Buf=58
    Bufif0=59
    Bufif1=60
    Byte=61
    Case_keyword=62
    Casez=63
    Casex=64
    Cell=65
    Cmos=66
    Config=67
    Const=68
    Deassign=69
    Default=70
    Default_nettype=71
    Defparam=72
    Design=73
    Disable=74
    Do=75
    Edge=76
    Else=77
    End=78
    Endcase=79
    Endconfig=80
    Endfunction=81
    Endgenerate=82
    Endmodule=83
    Endpackage=84
    Endproperty=85
    Endspecify=86
    Endtask=87
    Enum=88
    Event_keyword=89
    Final=90
    For=91
    Force=92
    Forever=93
    Fork=94
    Function=95
    Generate=96
    Genvar=97
    Highz0=98
    Highz1=99
    If=100
    Iff=101
    Ifnone=102
    Import=103
    Incdir=104
    Initial=105
    Inout=106
    Input=107
    Instance=108
    Int=109
    Integer=110
    Join=111
    Join_any=112
    Join_none=113
    Large=114
    Liblist=115
    Library=116
    Localparam=117
    Logic=118
    Macromodule=119
    Medium=120
    Module_keyword_only=121
    Nand=122
    Negedge=123
    Nmos=124
    NONE=125
    Nor=126
    Not=127
    Notif0=128
    Notif1=129
    Noshowcancelled=130
    Or=131
    Output=132
    Parameter=133
    Path_pulse_dollar=134
    Posedge=135
    Package=136
    Packed=137
    Pmos=138
    Property=139
    Pull0=140
    Pull1=141
    Pullup=142
    Pulldown=143
    Pulsestyle_ondetect=144
    Pulsestyle_onevent=145
    Rcmos=146
    Real=147
    Realtime=148
    Ref=149
    Reg=150
    Release=151
    Repeat=152
    Return=153
    Rnmos=154
    Rpmos=155
    Rtran=156
    Rtranif0=157
    Rtranif1=158
    Scalared=159
    Showcancelled=160
    Signed=161
    Small=162
    Specify=163
    Specparam=164
    Static=165
    SVString=166
    Strong0=167
    Strong1=168
    Struct=169
    Supply0=170
    Supply1=171
    Task=172
    Tick_timescale=173
    Time=174
    Timeprecision=175
    Timeunit=176
    Tran=177
    Tranif0=178
    Tranif1=179
    Tri=180
    Tri_and=181
    Tri_or=182
    Tri_reg=183
    Tri0=184
    Tri1=185
    Typedef=186
    UnionStruct=187
    Unsigned=188
    Use=189
    Uwire=190
    Vectored=191
    Wait=192
    Wand=193
    Weak0=194
    Weak1=195
    While=196
    Wire=197
    Wor=198
    Xnor=199
    Xor=200
    Dollar_Identifier=201
    Escaped_identifier=202
    Simple_identifier=203
    String_literal=204
    At=205
    Close_parenthesis=206
    Colon=207
    Comma=208
    Dash_right_angle=209
    Dot=210
    Dollar=211
    Double_colon=212
    Equal=213
    Equals_right_angle=214
    Forward_slash=215
    Hash=216
    Left_angle_equals=217
    Left_bracket=218
    Left_curly_bracket=219
    Minus_colon=220
    Open_parenthesis=221
    Plus_colon=222
    Question_mark=223
    Quote=224
    Right_bracket=225
    Right_curly_bracket=226
    Semicolon=227
    Star=228
    Star_right_angle=229
    Tilde=230
    Time_literal=231
    Edge_control_specifier=232

    def __init__(self, input:TokenStream, output:TextIO = sys.stdout):
        super().__init__(input, output)
        self.checkVersion("4.8")
        self._interp = ParserATNSimulator(self, self.atn, self.decisionsToDFA, self.sharedContextCache)
        self._predicates = None




    class Module_keywordContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Module_keyword_only(self):
            return self.getToken(SysVerilogHDLParser.Module_keyword_only, 0)

        def Macromodule(self):
            return self.getToken(SysVerilogHDLParser.Macromodule, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_keyword" ):
                listener.enterModule_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_keyword" ):
                listener.exitModule_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_keyword" ):
                return visitor.visitModule_keyword(self)
            else:
                return visitor.visitChildren(self)




    def module_keyword(self):

        localctx = SysVerilogHDLParser.Module_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 0, self.RULE_module_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 890
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Macromodule or _la==SysVerilogHDLParser.Module_keyword_only):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Struct_keywordContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Struct(self):
            return self.getToken(SysVerilogHDLParser.Struct, 0)

        def UnionStruct(self):
            return self.getToken(SysVerilogHDLParser.UnionStruct, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_struct_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStruct_keyword" ):
                listener.enterStruct_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStruct_keyword" ):
                listener.exitStruct_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStruct_keyword" ):
                return visitor.visitStruct_keyword(self)
            else:
                return visitor.visitChildren(self)




    def struct_keyword(self):

        localctx = SysVerilogHDLParser.Struct_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 2, self.RULE_struct_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 892
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Struct or _la==SysVerilogHDLParser.UnionStruct):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Any_case_keywordContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Case_keyword(self):
            return self.getToken(SysVerilogHDLParser.Case_keyword, 0)

        def Casez(self):
            return self.getToken(SysVerilogHDLParser.Casez, 0)

        def Casex(self):
            return self.getToken(SysVerilogHDLParser.Casex, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_any_case_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAny_case_keyword" ):
                listener.enterAny_case_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAny_case_keyword" ):
                listener.exitAny_case_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAny_case_keyword" ):
                return visitor.visitAny_case_keyword(self)
            else:
                return visitor.visitChildren(self)




    def any_case_keyword(self):

        localctx = SysVerilogHDLParser.Any_case_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 4, self.RULE_any_case_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 894
            _la = self._input.LA(1)
            if not(((((_la - 62)) & ~0x3f) == 0 and ((1 << (_la - 62)) & ((1 << (SysVerilogHDLParser.Case_keyword - 62)) | (1 << (SysVerilogHDLParser.Casez - 62)) | (1 << (SysVerilogHDLParser.Casex - 62)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class SemicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Semicolon(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Semicolon)
            else:
                return self.getToken(SysVerilogHDLParser.Semicolon, i)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSemicolon" ):
                listener.enterSemicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSemicolon" ):
                listener.exitSemicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSemicolon" ):
                return visitor.visitSemicolon(self)
            else:
                return visitor.visitChildren(self)




    def semicolon(self):

        localctx = SysVerilogHDLParser.SemicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 6, self.RULE_semicolon)
        try:
            self.state = 900
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,0,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 896
                self.match(SysVerilogHDLParser.Semicolon)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 897
                self.match(SysVerilogHDLParser.T__0)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 898
                self.match(SysVerilogHDLParser.Semicolon)
                self.state = 899
                self.match(SysVerilogHDLParser.Semicolon)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_operatorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Tilde(self):
            return self.getToken(SysVerilogHDLParser.Tilde, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_unary_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_operator" ):
                listener.enterUnary_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_operator" ):
                listener.exitUnary_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_operator" ):
                return visitor.visitUnary_operator(self)
            else:
                return visitor.visitChildren(self)




    def unary_operator(self):

        localctx = SysVerilogHDLParser.Unary_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 8, self.RULE_unary_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 902
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10))) != 0) or _la==SysVerilogHDLParser.Tilde):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Binary_operatorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Star(self):
            return self.getToken(SysVerilogHDLParser.Star, 0)

        def Forward_slash(self):
            return self.getToken(SysVerilogHDLParser.Forward_slash, 0)

        def Left_angle_equals(self):
            return self.getToken(SysVerilogHDLParser.Left_angle_equals, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_binary_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_operator" ):
                listener.enterBinary_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_operator" ):
                listener.exitBinary_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_operator" ):
                return visitor.visitBinary_operator(self)
            else:
                return visitor.visitChildren(self)




    def binary_operator(self):

        localctx = SysVerilogHDLParser.Binary_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 10, self.RULE_binary_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 904
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__11) | (1 << SysVerilogHDLParser.T__12) | (1 << SysVerilogHDLParser.T__13) | (1 << SysVerilogHDLParser.T__14) | (1 << SysVerilogHDLParser.T__15) | (1 << SysVerilogHDLParser.T__16) | (1 << SysVerilogHDLParser.T__17) | (1 << SysVerilogHDLParser.T__18) | (1 << SysVerilogHDLParser.T__19) | (1 << SysVerilogHDLParser.T__20) | (1 << SysVerilogHDLParser.T__21) | (1 << SysVerilogHDLParser.T__22) | (1 << SysVerilogHDLParser.T__23) | (1 << SysVerilogHDLParser.T__24) | (1 << SysVerilogHDLParser.T__25))) != 0) or ((((_la - 215)) & ~0x3f) == 0 and ((1 << (_la - 215)) & ((1 << (SysVerilogHDLParser.Forward_slash - 215)) | (1 << (SysVerilogHDLParser.Left_angle_equals - 215)) | (1 << (SysVerilogHDLParser.Star - 215)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_assign_operatorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_unary_assign_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_assign_operator" ):
                listener.enterUnary_assign_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_assign_operator" ):
                listener.exitUnary_assign_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_assign_operator" ):
                return visitor.visitUnary_assign_operator(self)
            else:
                return visitor.visitChildren(self)




    def unary_assign_operator(self):

        localctx = SysVerilogHDLParser.Unary_assign_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 12, self.RULE_unary_assign_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 906
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.T__26 or _la==SysVerilogHDLParser.T__27):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Binary_assign_operatorContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_binary_assign_operator

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_assign_operator" ):
                listener.enterBinary_assign_operator(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_assign_operator" ):
                listener.exitBinary_assign_operator(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_assign_operator" ):
                return visitor.visitBinary_assign_operator(self)
            else:
                return visitor.visitChildren(self)




    def binary_assign_operator(self):

        localctx = SysVerilogHDLParser.Binary_assign_operatorContext(self, self._ctx, self.state)
        self.enterRule(localctx, 14, self.RULE_binary_assign_operator)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 908
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__28) | (1 << SysVerilogHDLParser.T__29) | (1 << SysVerilogHDLParser.T__30) | (1 << SysVerilogHDLParser.T__31))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Source_textContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def description_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Description_starContext,0)


        def EOF(self):
            return self.getToken(SysVerilogHDLParser.EOF, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_source_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSource_text" ):
                listener.enterSource_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSource_text" ):
                listener.exitSource_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSource_text" ):
                return visitor.visitSource_text(self)
            else:
                return visitor.visitChildren(self)




    def source_text(self):

        localctx = SysVerilogHDLParser.Source_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 16, self.RULE_source_text)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 910
            self.description_star()
            self.state = 911
            self.match(SysVerilogHDLParser.EOF)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Description_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.DescriptionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.DescriptionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_description_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDescription_star" ):
                listener.enterDescription_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDescription_star" ):
                listener.exitDescription_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDescription_star" ):
                return visitor.visitDescription_star(self)
            else:
                return visitor.visitChildren(self)




    def description_star(self):

        localctx = SysVerilogHDLParser.Description_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 18, self.RULE_description_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 916
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 71)) & ~0x3f) == 0 and ((1 << (_la - 71)) & ((1 << (SysVerilogHDLParser.Default_nettype - 71)) | (1 << (SysVerilogHDLParser.Enum - 71)) | (1 << (SysVerilogHDLParser.Function - 71)) | (1 << (SysVerilogHDLParser.Import - 71)) | (1 << (SysVerilogHDLParser.Macromodule - 71)) | (1 << (SysVerilogHDLParser.Module_keyword_only - 71)))) != 0) or ((((_la - 136)) & ~0x3f) == 0 and ((1 << (_la - 136)) & ((1 << (SysVerilogHDLParser.Package - 136)) | (1 << (SysVerilogHDLParser.Tick_timescale - 136)) | (1 << (SysVerilogHDLParser.Typedef - 136)))) != 0) or _la==SysVerilogHDLParser.Open_parenthesis:
                self.state = 913
                self.description()
                self.state = 918
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Header_textContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def compiler_directive(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Compiler_directiveContext,0)


        def design_attribute(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Design_attributeContext,0)


        def import_package(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Import_packageContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_header_text

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHeader_text" ):
                listener.enterHeader_text(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHeader_text" ):
                listener.exitHeader_text(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHeader_text" ):
                return visitor.visitHeader_text(self)
            else:
                return visitor.visitChildren(self)




    def header_text(self):

        localctx = SysVerilogHDLParser.Header_textContext(self, self._ctx, self.state)
        self.enterRule(localctx, 20, self.RULE_header_text)
        try:
            self.state = 922
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Default_nettype, SysVerilogHDLParser.Tick_timescale]:
                self.enterOuterAlt(localctx, 1)
                self.state = 919
                self.compiler_directive()
                pass
            elif token in [SysVerilogHDLParser.Open_parenthesis]:
                self.enterOuterAlt(localctx, 2)
                self.state = 920
                self.design_attribute()
                pass
            elif token in [SysVerilogHDLParser.Import]:
                self.enterOuterAlt(localctx, 3)
                self.state = 921
                self.import_package()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Design_attributeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_design_attribute

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDesign_attribute" ):
                listener.enterDesign_attribute(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDesign_attribute" ):
                listener.exitDesign_attribute(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDesign_attribute" ):
                return visitor.visitDesign_attribute(self)
            else:
                return visitor.visitChildren(self)




    def design_attribute(self):

        localctx = SysVerilogHDLParser.Design_attributeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 22, self.RULE_design_attribute)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 924
            self.attribute_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Compiler_directiveContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def timescale_compiler_directive(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Timescale_compiler_directiveContext,0)


        def default_nettype_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Default_nettype_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_compiler_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCompiler_directive" ):
                listener.enterCompiler_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCompiler_directive" ):
                listener.exitCompiler_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCompiler_directive" ):
                return visitor.visitCompiler_directive(self)
            else:
                return visitor.visitChildren(self)




    def compiler_directive(self):

        localctx = SysVerilogHDLParser.Compiler_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 24, self.RULE_compiler_directive)
        try:
            self.state = 928
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Tick_timescale]:
                self.enterOuterAlt(localctx, 1)
                self.state = 926
                self.timescale_compiler_directive()
                pass
            elif token in [SysVerilogHDLParser.Default_nettype]:
                self.enterOuterAlt(localctx, 2)
                self.state = 927
                self.default_nettype_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class DescriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def header_text(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Header_textContext,0)


        def package_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Package_declarationContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def module_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_declarationContext,0)


        def function_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_declarationContext,0)


        def enum_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enum_declarationContext,0)


        def typedef_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Typedef_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDescription" ):
                listener.enterDescription(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDescription" ):
                listener.exitDescription(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDescription" ):
                return visitor.visitDescription(self)
            else:
                return visitor.visitChildren(self)




    def description(self):

        localctx = SysVerilogHDLParser.DescriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 26, self.RULE_description)
        self._la = 0 # Token type
        try:
            self.state = 951
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,9,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 930
                self.header_text()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 931
                self.package_declaration()
                self.state = 933
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SysVerilogHDLParser.T__0 or _la==SysVerilogHDLParser.Semicolon:
                    self.state = 932
                    self.semicolon()


                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 935
                self.module_declaration()
                self.state = 937
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SysVerilogHDLParser.T__0 or _la==SysVerilogHDLParser.Semicolon:
                    self.state = 936
                    self.semicolon()


                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 939
                self.function_declaration()
                self.state = 941
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SysVerilogHDLParser.T__0 or _la==SysVerilogHDLParser.Semicolon:
                    self.state = 940
                    self.semicolon()


                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 943
                self.enum_declaration()
                self.state = 945
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SysVerilogHDLParser.T__0 or _la==SysVerilogHDLParser.Semicolon:
                    self.state = 944
                    self.semicolon()


                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 947
                self.typedef_declaration()
                self.state = 949
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SysVerilogHDLParser.T__0 or _la==SysVerilogHDLParser.Semicolon:
                    self.state = 948
                    self.semicolon()


                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def module_keyword(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_keywordContext,0)


        def module_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_identifierContext,0)


        def module_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_interfaceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def module_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_item_starContext,0)


        def Endmodule(self):
            return self.getToken(SysVerilogHDLParser.Endmodule, 0)

        def colon_module_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Colon_module_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_declaration" ):
                listener.enterModule_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_declaration" ):
                listener.exitModule_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_declaration" ):
                return visitor.visitModule_declaration(self)
            else:
                return visitor.visitChildren(self)




    def module_declaration(self):

        localctx = SysVerilogHDLParser.Module_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 28, self.RULE_module_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 953
            self.attribute_instance_star()
            self.state = 954
            self.module_keyword()
            self.state = 955
            self.module_identifier()
            self.state = 956
            self.module_interface()
            self.state = 957
            self.semicolon()
            self.state = 958
            self.module_item_star()
            self.state = 959
            self.match(SysVerilogHDLParser.Endmodule)
            self.state = 961
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 960
                self.colon_module_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_identifier" ):
                listener.enterModule_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_identifier" ):
                listener.exitModule_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_identifier" ):
                return visitor.visitModule_identifier(self)
            else:
                return visitor.visitChildren(self)




    def module_identifier(self):

        localctx = SysVerilogHDLParser.Module_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 30, self.RULE_module_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 963
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_parameter_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_parameter_interfaceContext,0)


        def module_port_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_port_interfaceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_interface" ):
                listener.enterModule_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_interface" ):
                listener.exitModule_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_interface" ):
                return visitor.visitModule_interface(self)
            else:
                return visitor.visitChildren(self)




    def module_interface(self):

        localctx = SysVerilogHDLParser.Module_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 32, self.RULE_module_interface)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 966
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 965
                self.module_parameter_interface()


            self.state = 969
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Open_parenthesis:
                self.state = 968
                self.module_port_interface()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_parameter_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Hash(self):
            return self.getToken(SysVerilogHDLParser.Hash, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def list_of_interface_parameters(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_interface_parametersContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_parameter_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_parameter_interface" ):
                listener.enterModule_parameter_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_parameter_interface" ):
                listener.exitModule_parameter_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_parameter_interface" ):
                return visitor.visitModule_parameter_interface(self)
            else:
                return visitor.visitChildren(self)




    def module_parameter_interface(self):

        localctx = SysVerilogHDLParser.Module_parameter_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 34, self.RULE_module_parameter_interface)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 971
            self.match(SysVerilogHDLParser.Hash)
            self.state = 972
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 974
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Parameter or _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 973
                self.list_of_interface_parameters()


            self.state = 976
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_port_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def list_of_interface_ports(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_interface_portsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_port_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_port_interface" ):
                listener.enterModule_port_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_port_interface" ):
                listener.exitModule_port_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_port_interface" ):
                return visitor.visitModule_port_interface(self)
            else:
                return visitor.visitChildren(self)




    def module_port_interface(self):

        localctx = SysVerilogHDLParser.Module_port_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 36, self.RULE_module_port_interface)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 978
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 980
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 106)) & ~0x3f) == 0 and ((1 << (_la - 106)) & ((1 << (SysVerilogHDLParser.Inout - 106)) | (1 << (SysVerilogHDLParser.Input - 106)) | (1 << (SysVerilogHDLParser.Output - 106)) | (1 << (SysVerilogHDLParser.Ref - 106)))) != 0) or ((((_la - 202)) & ~0x3f) == 0 and ((1 << (_la - 202)) & ((1 << (SysVerilogHDLParser.Escaped_identifier - 202)) | (1 << (SysVerilogHDLParser.Simple_identifier - 202)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 202)))) != 0):
                self.state = 979
                self.list_of_interface_ports()


            self.state = 982
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Module_itemContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Module_itemContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_item_star" ):
                listener.enterModule_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_item_star" ):
                listener.exitModule_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_item_star" ):
                return visitor.visitModule_item_star(self)
            else:
                return visitor.visitChildren(self)




    def module_item_star(self):

        localctx = SysVerilogHDLParser.Module_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 38, self.RULE_module_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 987
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 49)) & ~0x3f) == 0 and ((1 << (_la - 49)) & ((1 << (SysVerilogHDLParser.Always - 49)) | (1 << (SysVerilogHDLParser.Always_comb - 49)) | (1 << (SysVerilogHDLParser.Always_ff - 49)) | (1 << (SysVerilogHDLParser.And - 49)) | (1 << (SysVerilogHDLParser.Assign - 49)) | (1 << (SysVerilogHDLParser.Automatic - 49)) | (1 << (SysVerilogHDLParser.Bit - 49)) | (1 << (SysVerilogHDLParser.Buf - 49)) | (1 << (SysVerilogHDLParser.Bufif0 - 49)) | (1 << (SysVerilogHDLParser.Bufif1 - 49)) | (1 << (SysVerilogHDLParser.Byte - 49)) | (1 << (SysVerilogHDLParser.Cmos - 49)) | (1 << (SysVerilogHDLParser.Const - 49)) | (1 << (SysVerilogHDLParser.Default_nettype - 49)) | (1 << (SysVerilogHDLParser.Defparam - 49)) | (1 << (SysVerilogHDLParser.Enum - 49)) | (1 << (SysVerilogHDLParser.Event_keyword - 49)) | (1 << (SysVerilogHDLParser.Final - 49)) | (1 << (SysVerilogHDLParser.Function - 49)) | (1 << (SysVerilogHDLParser.Generate - 49)) | (1 << (SysVerilogHDLParser.Genvar - 49)) | (1 << (SysVerilogHDLParser.Import - 49)) | (1 << (SysVerilogHDLParser.Initial - 49)) | (1 << (SysVerilogHDLParser.Inout - 49)) | (1 << (SysVerilogHDLParser.Input - 49)) | (1 << (SysVerilogHDLParser.Int - 49)) | (1 << (SysVerilogHDLParser.Integer - 49)))) != 0) or ((((_la - 117)) & ~0x3f) == 0 and ((1 << (_la - 117)) & ((1 << (SysVerilogHDLParser.Localparam - 117)) | (1 << (SysVerilogHDLParser.Logic - 117)) | (1 << (SysVerilogHDLParser.Nand - 117)) | (1 << (SysVerilogHDLParser.Nmos - 117)) | (1 << (SysVerilogHDLParser.NONE - 117)) | (1 << (SysVerilogHDLParser.Nor - 117)) | (1 << (SysVerilogHDLParser.Not - 117)) | (1 << (SysVerilogHDLParser.Notif0 - 117)) | (1 << (SysVerilogHDLParser.Notif1 - 117)) | (1 << (SysVerilogHDLParser.Or - 117)) | (1 << (SysVerilogHDLParser.Output - 117)) | (1 << (SysVerilogHDLParser.Parameter - 117)) | (1 << (SysVerilogHDLParser.Pmos - 117)) | (1 << (SysVerilogHDLParser.Pullup - 117)) | (1 << (SysVerilogHDLParser.Pulldown - 117)) | (1 << (SysVerilogHDLParser.Rcmos - 117)) | (1 << (SysVerilogHDLParser.Real - 117)) | (1 << (SysVerilogHDLParser.Realtime - 117)) | (1 << (SysVerilogHDLParser.Ref - 117)) | (1 << (SysVerilogHDLParser.Reg - 117)) | (1 << (SysVerilogHDLParser.Rnmos - 117)) | (1 << (SysVerilogHDLParser.Rpmos - 117)) | (1 << (SysVerilogHDLParser.Rtran - 117)) | (1 << (SysVerilogHDLParser.Rtranif0 - 117)) | (1 << (SysVerilogHDLParser.Rtranif1 - 117)) | (1 << (SysVerilogHDLParser.Static - 117)) | (1 << (SysVerilogHDLParser.SVString - 117)) | (1 << (SysVerilogHDLParser.Struct - 117)) | (1 << (SysVerilogHDLParser.Supply0 - 117)) | (1 << (SysVerilogHDLParser.Supply1 - 117)) | (1 << (SysVerilogHDLParser.Task - 117)) | (1 << (SysVerilogHDLParser.Tick_timescale - 117)) | (1 << (SysVerilogHDLParser.Time - 117)) | (1 << (SysVerilogHDLParser.Timeprecision - 117)) | (1 << (SysVerilogHDLParser.Timeunit - 117)) | (1 << (SysVerilogHDLParser.Tran - 117)) | (1 << (SysVerilogHDLParser.Tranif0 - 117)) | (1 << (SysVerilogHDLParser.Tranif1 - 117)) | (1 << (SysVerilogHDLParser.Tri - 117)))) != 0) or ((((_la - 181)) & ~0x3f) == 0 and ((1 << (_la - 181)) & ((1 << (SysVerilogHDLParser.Tri_and - 181)) | (1 << (SysVerilogHDLParser.Tri_or - 181)) | (1 << (SysVerilogHDLParser.Tri_reg - 181)) | (1 << (SysVerilogHDLParser.Tri0 - 181)) | (1 << (SysVerilogHDLParser.Tri1 - 181)) | (1 << (SysVerilogHDLParser.Typedef - 181)) | (1 << (SysVerilogHDLParser.UnionStruct - 181)) | (1 << (SysVerilogHDLParser.Uwire - 181)) | (1 << (SysVerilogHDLParser.Wand - 181)) | (1 << (SysVerilogHDLParser.Wire - 181)) | (1 << (SysVerilogHDLParser.Wor - 181)) | (1 << (SysVerilogHDLParser.Xnor - 181)) | (1 << (SysVerilogHDLParser.Xor - 181)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 181)) | (1 << (SysVerilogHDLParser.Simple_identifier - 181)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 181)))) != 0):
                self.state = 984
                self.module_item()
                self.state = 989
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def import_package(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Import_packageContext,0)


        def parameter_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_item_semicolonContext,0)


        def attr_port_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_port_item_semicolonContext,0)


        def attr_variable_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_variable_item_semicolonContext,0)


        def subroutine_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Subroutine_item_semicolonContext,0)


        def attr_construct_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_construct_itemContext,0)


        def attr_generated_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_generated_instantiationContext,0)


        def attr_component_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_component_itemContext,0)


        def compiler_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Compiler_itemContext,0)


        def type_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Type_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_item" ):
                listener.enterModule_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_item" ):
                listener.exitModule_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_item" ):
                return visitor.visitModule_item(self)
            else:
                return visitor.visitChildren(self)




    def module_item(self):

        localctx = SysVerilogHDLParser.Module_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 40, self.RULE_module_item)
        try:
            self.state = 1000
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,16,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 990
                self.import_package()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 991
                self.parameter_item_semicolon()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 992
                self.attr_port_item_semicolon()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 993
                self.attr_variable_item_semicolon()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 994
                self.subroutine_item_semicolon()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 995
                self.attr_construct_item()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 996
                self.attr_generated_instantiation()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 997
                self.attr_component_item()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 998
                self.compiler_item()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 999
                self.type_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Colon_module_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def module_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_colon_module_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterColon_module_identifier" ):
                listener.enterColon_module_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitColon_module_identifier" ):
                listener.exitColon_module_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitColon_module_identifier" ):
                return visitor.visitColon_module_identifier(self)
            else:
                return visitor.visitChildren(self)




    def colon_module_identifier(self):

        localctx = SysVerilogHDLParser.Colon_module_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 42, self.RULE_colon_module_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1002
            self.match(SysVerilogHDLParser.Colon)
            self.state = 1003
            self.module_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def Package(self):
            return self.getToken(SysVerilogHDLParser.Package, 0)

        def package_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Package_identifierContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def package_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Package_item_starContext,0)


        def Endpackage(self):
            return self.getToken(SysVerilogHDLParser.Endpackage, 0)

        def colon_package_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Colon_package_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_package_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_declaration" ):
                listener.enterPackage_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_declaration" ):
                listener.exitPackage_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_declaration" ):
                return visitor.visitPackage_declaration(self)
            else:
                return visitor.visitChildren(self)




    def package_declaration(self):

        localctx = SysVerilogHDLParser.Package_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 44, self.RULE_package_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1005
            self.attribute_instance_star()
            self.state = 1006
            self.match(SysVerilogHDLParser.Package)
            self.state = 1007
            self.package_identifier()
            self.state = 1008
            self.semicolon()
            self.state = 1009
            self.package_item_star()
            self.state = 1010
            self.match(SysVerilogHDLParser.Endpackage)
            self.state = 1012
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 1011
                self.colon_package_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_package_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_identifier" ):
                listener.enterPackage_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_identifier" ):
                listener.exitPackage_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_identifier" ):
                return visitor.visitPackage_identifier(self)
            else:
                return visitor.visitChildren(self)




    def package_identifier(self):

        localctx = SysVerilogHDLParser.Package_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 46, self.RULE_package_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1014
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Colon_package_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def package_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Package_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_colon_package_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterColon_package_identifier" ):
                listener.enterColon_package_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitColon_package_identifier" ):
                listener.exitColon_package_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitColon_package_identifier" ):
                return visitor.visitColon_package_identifier(self)
            else:
                return visitor.visitChildren(self)




    def colon_package_identifier(self):

        localctx = SysVerilogHDLParser.Colon_package_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 48, self.RULE_colon_package_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1016
            self.match(SysVerilogHDLParser.Colon)
            self.state = 1017
            self.package_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def package_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Package_itemContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Package_itemContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_package_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_item_star" ):
                listener.enterPackage_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_item_star" ):
                listener.exitPackage_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_item_star" ):
                return visitor.visitPackage_item_star(self)
            else:
                return visitor.visitChildren(self)




    def package_item_star(self):

        localctx = SysVerilogHDLParser.Package_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 50, self.RULE_package_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1022
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 52)) & ~0x3f) == 0 and ((1 << (_la - 52)) & ((1 << (SysVerilogHDLParser.And - 52)) | (1 << (SysVerilogHDLParser.Automatic - 52)) | (1 << (SysVerilogHDLParser.Bit - 52)) | (1 << (SysVerilogHDLParser.Buf - 52)) | (1 << (SysVerilogHDLParser.Bufif0 - 52)) | (1 << (SysVerilogHDLParser.Bufif1 - 52)) | (1 << (SysVerilogHDLParser.Byte - 52)) | (1 << (SysVerilogHDLParser.Cmos - 52)) | (1 << (SysVerilogHDLParser.Const - 52)) | (1 << (SysVerilogHDLParser.Default_nettype - 52)) | (1 << (SysVerilogHDLParser.Defparam - 52)) | (1 << (SysVerilogHDLParser.Enum - 52)) | (1 << (SysVerilogHDLParser.Event_keyword - 52)) | (1 << (SysVerilogHDLParser.Function - 52)) | (1 << (SysVerilogHDLParser.Genvar - 52)) | (1 << (SysVerilogHDLParser.Import - 52)) | (1 << (SysVerilogHDLParser.Int - 52)) | (1 << (SysVerilogHDLParser.Integer - 52)))) != 0) or ((((_la - 117)) & ~0x3f) == 0 and ((1 << (_la - 117)) & ((1 << (SysVerilogHDLParser.Localparam - 117)) | (1 << (SysVerilogHDLParser.Logic - 117)) | (1 << (SysVerilogHDLParser.Nand - 117)) | (1 << (SysVerilogHDLParser.Nmos - 117)) | (1 << (SysVerilogHDLParser.NONE - 117)) | (1 << (SysVerilogHDLParser.Nor - 117)) | (1 << (SysVerilogHDLParser.Not - 117)) | (1 << (SysVerilogHDLParser.Notif0 - 117)) | (1 << (SysVerilogHDLParser.Notif1 - 117)) | (1 << (SysVerilogHDLParser.Or - 117)) | (1 << (SysVerilogHDLParser.Parameter - 117)) | (1 << (SysVerilogHDLParser.Pmos - 117)) | (1 << (SysVerilogHDLParser.Pullup - 117)) | (1 << (SysVerilogHDLParser.Pulldown - 117)) | (1 << (SysVerilogHDLParser.Rcmos - 117)) | (1 << (SysVerilogHDLParser.Real - 117)) | (1 << (SysVerilogHDLParser.Realtime - 117)) | (1 << (SysVerilogHDLParser.Reg - 117)) | (1 << (SysVerilogHDLParser.Rnmos - 117)) | (1 << (SysVerilogHDLParser.Rpmos - 117)) | (1 << (SysVerilogHDLParser.Rtran - 117)) | (1 << (SysVerilogHDLParser.Rtranif0 - 117)) | (1 << (SysVerilogHDLParser.Rtranif1 - 117)) | (1 << (SysVerilogHDLParser.Static - 117)) | (1 << (SysVerilogHDLParser.SVString - 117)) | (1 << (SysVerilogHDLParser.Struct - 117)) | (1 << (SysVerilogHDLParser.Supply0 - 117)) | (1 << (SysVerilogHDLParser.Supply1 - 117)) | (1 << (SysVerilogHDLParser.Task - 117)) | (1 << (SysVerilogHDLParser.Tick_timescale - 117)) | (1 << (SysVerilogHDLParser.Time - 117)) | (1 << (SysVerilogHDLParser.Timeprecision - 117)) | (1 << (SysVerilogHDLParser.Timeunit - 117)) | (1 << (SysVerilogHDLParser.Tran - 117)) | (1 << (SysVerilogHDLParser.Tranif0 - 117)) | (1 << (SysVerilogHDLParser.Tranif1 - 117)) | (1 << (SysVerilogHDLParser.Tri - 117)))) != 0) or ((((_la - 181)) & ~0x3f) == 0 and ((1 << (_la - 181)) & ((1 << (SysVerilogHDLParser.Tri_and - 181)) | (1 << (SysVerilogHDLParser.Tri_or - 181)) | (1 << (SysVerilogHDLParser.Tri_reg - 181)) | (1 << (SysVerilogHDLParser.Tri0 - 181)) | (1 << (SysVerilogHDLParser.Tri1 - 181)) | (1 << (SysVerilogHDLParser.Typedef - 181)) | (1 << (SysVerilogHDLParser.UnionStruct - 181)) | (1 << (SysVerilogHDLParser.Uwire - 181)) | (1 << (SysVerilogHDLParser.Wand - 181)) | (1 << (SysVerilogHDLParser.Wire - 181)) | (1 << (SysVerilogHDLParser.Wor - 181)) | (1 << (SysVerilogHDLParser.Xnor - 181)) | (1 << (SysVerilogHDLParser.Xor - 181)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 181)) | (1 << (SysVerilogHDLParser.Simple_identifier - 181)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 181)))) != 0):
                self.state = 1019
                self.package_item()
                self.state = 1024
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def import_package(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Import_packageContext,0)


        def parameter_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_item_semicolonContext,0)


        def attr_variable_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_variable_item_semicolonContext,0)


        def subroutine_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Subroutine_item_semicolonContext,0)


        def attr_component_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_component_itemContext,0)


        def compiler_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Compiler_itemContext,0)


        def type_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Type_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_package_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_item" ):
                listener.enterPackage_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_item" ):
                listener.exitPackage_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_item" ):
                return visitor.visitPackage_item(self)
            else:
                return visitor.visitChildren(self)




    def package_item(self):

        localctx = SysVerilogHDLParser.Package_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 52, self.RULE_package_item)
        try:
            self.state = 1032
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,19,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1025
                self.import_package()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1026
                self.parameter_item_semicolon()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1027
                self.attr_variable_item_semicolon()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1028
                self.subroutine_item_semicolon()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1029
                self.attr_component_item()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1030
                self.compiler_item()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1031
                self.type_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Import_packageContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Import(self):
            return self.getToken(SysVerilogHDLParser.Import, 0)

        def package_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Package_identifierContext,0)


        def Double_colon(self):
            return self.getToken(SysVerilogHDLParser.Double_colon, 0)

        def Star(self):
            return self.getToken(SysVerilogHDLParser.Star, 0)

        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def package_item_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Package_item_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_import_package

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterImport_package" ):
                listener.enterImport_package(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitImport_package" ):
                listener.exitImport_package(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitImport_package" ):
                return visitor.visitImport_package(self)
            else:
                return visitor.visitChildren(self)




    def import_package(self):

        localctx = SysVerilogHDLParser.Import_packageContext(self, self._ctx, self.state)
        self.enterRule(localctx, 54, self.RULE_import_package)
        try:
            self.state = 1046
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,20,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1034
                self.match(SysVerilogHDLParser.Import)
                self.state = 1035
                self.package_identifier()
                self.state = 1036
                self.match(SysVerilogHDLParser.Double_colon)
                self.state = 1037
                self.match(SysVerilogHDLParser.Star)
                self.state = 1038
                self.semicolon()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1040
                self.match(SysVerilogHDLParser.Import)
                self.state = 1041
                self.package_identifier()
                self.state = 1042
                self.match(SysVerilogHDLParser.Double_colon)
                self.state = 1043
                self.package_item_identifier()
                self.state = 1044
                self.semicolon()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Package_item_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_package_item_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPackage_item_identifier" ):
                listener.enterPackage_item_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPackage_item_identifier" ):
                listener.exitPackage_item_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPackage_item_identifier" ):
                return visitor.visitPackage_item_identifier(self)
            else:
                return visitor.visitChildren(self)




    def package_item_identifier(self):

        localctx = SysVerilogHDLParser.Package_item_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 56, self.RULE_package_item_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1048
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_item_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_itemContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_parameter_item_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_item_semicolon" ):
                listener.enterParameter_item_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_item_semicolon" ):
                listener.exitParameter_item_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_item_semicolon" ):
                return visitor.visitParameter_item_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def parameter_item_semicolon(self):

        localctx = SysVerilogHDLParser.Parameter_item_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 58, self.RULE_parameter_item_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1050
            self.parameter_item()
            self.state = 1051
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_declarationContext,0)


        def local_parameter_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Local_parameter_declarationContext,0)


        def parameter_override(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_overrideContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_parameter_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_item" ):
                listener.enterParameter_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_item" ):
                listener.exitParameter_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_item" ):
                return visitor.visitParameter_item(self)
            else:
                return visitor.visitChildren(self)




    def parameter_item(self):

        localctx = SysVerilogHDLParser.Parameter_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 60, self.RULE_parameter_item)
        try:
            self.state = 1056
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Parameter]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1053
                self.parameter_declaration()
                pass
            elif token in [SysVerilogHDLParser.Localparam]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1054
                self.local_parameter_declaration()
                pass
            elif token in [SysVerilogHDLParser.Defparam]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1055
                self.parameter_override()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_port_item_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_declarationContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_port_item_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_port_item_semicolon" ):
                listener.enterAttr_port_item_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_port_item_semicolon" ):
                listener.exitAttr_port_item_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_port_item_semicolon" ):
                return visitor.visitAttr_port_item_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def attr_port_item_semicolon(self):

        localctx = SysVerilogHDLParser.Attr_port_item_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 62, self.RULE_attr_port_item_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1058
            self.attribute_instance_star()
            self.state = 1059
            self.port_declaration()
            self.state = 1060
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_variable_item_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def variable_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_itemContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_variable_item_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_variable_item_semicolon" ):
                listener.enterAttr_variable_item_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_variable_item_semicolon" ):
                listener.exitAttr_variable_item_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_variable_item_semicolon" ):
                return visitor.visitAttr_variable_item_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def attr_variable_item_semicolon(self):

        localctx = SysVerilogHDLParser.Attr_variable_item_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 64, self.RULE_attr_variable_item_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1062
            self.attribute_instance_star()
            self.state = 1063
            self.variable_item()
            self.state = 1064
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_declarationContext,0)


        def reg_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Reg_declarationContext,0)


        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def bits_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def int_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Int_declarationContext,0)


        def real_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Real_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Time_declarationContext,0)


        def realtime_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Realtime_declarationContext,0)


        def event_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_declarationContext,0)


        def genvar_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Genvar_declarationContext,0)


        def usertype_variable_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Usertype_variable_declarationContext,0)


        def string_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.String_declarationContext,0)


        def struct_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Struct_declarationContext,0)


        def enum_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enum_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_item" ):
                listener.enterVariable_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_item" ):
                listener.exitVariable_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_item" ):
                return visitor.visitVariable_item(self)
            else:
                return visitor.visitChildren(self)




    def variable_item(self):

        localctx = SysVerilogHDLParser.Variable_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 66, self.RULE_variable_item)
        try:
            self.state = 1081
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,22,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1066
                self.net_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1067
                self.reg_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1068
                self.logic_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1069
                self.bits_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1070
                self.integer_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1071
                self.int_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1072
                self.real_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1073
                self.time_declaration()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 1074
                self.realtime_declaration()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 1075
                self.event_declaration()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 1076
                self.genvar_declaration()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 1077
                self.usertype_variable_declaration()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 1078
                self.string_declaration()
                pass

            elif la_ == 14:
                self.enterOuterAlt(localctx, 14)
                self.state = 1079
                self.struct_declaration()
                pass

            elif la_ == 15:
                self.enterOuterAlt(localctx, 15)
                self.state = 1080
                self.enum_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Subroutine_item_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def subroutine_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Subroutine_itemContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_subroutine_item_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSubroutine_item_semicolon" ):
                listener.enterSubroutine_item_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSubroutine_item_semicolon" ):
                listener.exitSubroutine_item_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSubroutine_item_semicolon" ):
                return visitor.visitSubroutine_item_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def subroutine_item_semicolon(self):

        localctx = SysVerilogHDLParser.Subroutine_item_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 68, self.RULE_subroutine_item_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1083
            self.subroutine_item()
            self.state = 1085
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,23,self._ctx)
            if la_ == 1:
                self.state = 1084
                self.semicolon()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Subroutine_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_declarationContext,0)


        def function_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_subroutine_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSubroutine_item" ):
                listener.enterSubroutine_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSubroutine_item" ):
                listener.exitSubroutine_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSubroutine_item" ):
                return visitor.visitSubroutine_item(self)
            else:
                return visitor.visitChildren(self)




    def subroutine_item(self):

        localctx = SysVerilogHDLParser.Subroutine_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 70, self.RULE_subroutine_item)
        try:
            self.state = 1089
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Task]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1087
                self.task_declaration()
                pass
            elif token in [SysVerilogHDLParser.Function]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1088
                self.function_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_construct_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def construct_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Construct_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_construct_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_construct_item" ):
                listener.enterAttr_construct_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_construct_item" ):
                listener.exitAttr_construct_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_construct_item" ):
                return visitor.visitAttr_construct_item(self)
            else:
                return visitor.visitChildren(self)




    def attr_construct_item(self):

        localctx = SysVerilogHDLParser.Attr_construct_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 72, self.RULE_attr_construct_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1091
            self.attribute_instance_star()
            self.state = 1092
            self.construct_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Construct_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def continuous_assign(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Continuous_assignContext,0)


        def initial_construct(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Initial_constructContext,0)


        def final_construct(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Final_constructContext,0)


        def always_construct(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Always_constructContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_construct_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstruct_item" ):
                listener.enterConstruct_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstruct_item" ):
                listener.exitConstruct_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstruct_item" ):
                return visitor.visitConstruct_item(self)
            else:
                return visitor.visitChildren(self)




    def construct_item(self):

        localctx = SysVerilogHDLParser.Construct_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 74, self.RULE_construct_item)
        try:
            self.state = 1098
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Assign]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1094
                self.continuous_assign()
                pass
            elif token in [SysVerilogHDLParser.Initial]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1095
                self.initial_construct()
                pass
            elif token in [SysVerilogHDLParser.Final]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1096
                self.final_construct()
                pass
            elif token in [SysVerilogHDLParser.Always, SysVerilogHDLParser.Always_comb, SysVerilogHDLParser.Always_ff]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1097
                self.always_construct()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_component_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def component_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Component_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_component_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_component_item" ):
                listener.enterAttr_component_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_component_item" ):
                listener.exitAttr_component_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_component_item" ):
                return visitor.visitAttr_component_item(self)
            else:
                return visitor.visitChildren(self)




    def attr_component_item(self):

        localctx = SysVerilogHDLParser.Attr_component_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 76, self.RULE_attr_component_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1100
            self.attribute_instance_star()
            self.state = 1101
            self.component_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Component_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_instantiationContext,0)


        def gate_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instantiationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_component_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComponent_item" ):
                listener.enterComponent_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComponent_item" ):
                listener.exitComponent_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComponent_item" ):
                return visitor.visitComponent_item(self)
            else:
                return visitor.visitChildren(self)




    def component_item(self):

        localctx = SysVerilogHDLParser.Component_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 78, self.RULE_component_item)
        try:
            self.state = 1105
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1103
                self.module_instantiation()
                pass
            elif token in [SysVerilogHDLParser.And, SysVerilogHDLParser.Buf, SysVerilogHDLParser.Bufif0, SysVerilogHDLParser.Bufif1, SysVerilogHDLParser.Cmos, SysVerilogHDLParser.Nand, SysVerilogHDLParser.Nmos, SysVerilogHDLParser.Nor, SysVerilogHDLParser.Not, SysVerilogHDLParser.Notif0, SysVerilogHDLParser.Notif1, SysVerilogHDLParser.Or, SysVerilogHDLParser.Pmos, SysVerilogHDLParser.Pullup, SysVerilogHDLParser.Pulldown, SysVerilogHDLParser.Rcmos, SysVerilogHDLParser.Rnmos, SysVerilogHDLParser.Rpmos, SysVerilogHDLParser.Rtran, SysVerilogHDLParser.Rtranif0, SysVerilogHDLParser.Rtranif1, SysVerilogHDLParser.Tran, SysVerilogHDLParser.Tranif0, SysVerilogHDLParser.Tranif1, SysVerilogHDLParser.Xnor, SysVerilogHDLParser.Xor]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1104
                self.gate_instantiation()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Compiler_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def timescale_compiler_directive(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Timescale_compiler_directiveContext,0)


        def timeunit_directive(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Timeunit_directiveContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def timeprecision_directive(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Timeprecision_directiveContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_compiler_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCompiler_item" ):
                listener.enterCompiler_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCompiler_item" ):
                listener.exitCompiler_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCompiler_item" ):
                return visitor.visitCompiler_item(self)
            else:
                return visitor.visitChildren(self)




    def compiler_item(self):

        localctx = SysVerilogHDLParser.Compiler_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 80, self.RULE_compiler_item)
        try:
            self.state = 1114
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Tick_timescale]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1107
                self.timescale_compiler_directive()
                pass
            elif token in [SysVerilogHDLParser.Timeunit]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1108
                self.timeunit_directive()
                self.state = 1109
                self.semicolon()
                pass
            elif token in [SysVerilogHDLParser.Timeprecision]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1111
                self.timeprecision_directive()
                self.state = 1112
                self.semicolon()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Type_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def default_nettype_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Default_nettype_statementContext,0)


        def typedef_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Typedef_declarationContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_type_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterType_item" ):
                listener.enterType_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitType_item" ):
                listener.exitType_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitType_item" ):
                return visitor.visitType_item(self)
            else:
                return visitor.visitChildren(self)




    def type_item(self):

        localctx = SysVerilogHDLParser.Type_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 82, self.RULE_type_item)
        try:
            self.state = 1120
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Default_nettype]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1116
                self.default_nettype_statement()
                pass
            elif token in [SysVerilogHDLParser.Typedef]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1117
                self.typedef_declaration()
                self.state = 1118
                self.semicolon()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Null_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_null_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNull_item" ):
                listener.enterNull_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNull_item" ):
                listener.exitNull_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNull_item" ):
                return visitor.visitNull_item(self)
            else:
                return visitor.visitChildren(self)




    def null_item(self):

        localctx = SysVerilogHDLParser.Null_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 84, self.RULE_null_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1122
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_interface_parametersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_parameter_declarations(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_parameter_declarationsContext,0)


        def list_of_parameter_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_parameter_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_interface_parameters

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_interface_parameters" ):
                listener.enterList_of_interface_parameters(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_interface_parameters" ):
                listener.exitList_of_interface_parameters(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_interface_parameters" ):
                return visitor.visitList_of_interface_parameters(self)
            else:
                return visitor.visitChildren(self)




    def list_of_interface_parameters(self):

        localctx = SysVerilogHDLParser.List_of_interface_parametersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 86, self.RULE_list_of_interface_parameters)
        try:
            self.state = 1126
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Parameter]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1124
                self.list_of_parameter_declarations()
                pass
            elif token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1125
                self.list_of_parameter_descriptions()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_parameter_declarationsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def parameter_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_declarationContext,0)


        def comma_parameter_declaration_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_parameter_declaration_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_parameter_declarations

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_parameter_declarations" ):
                listener.enterList_of_parameter_declarations(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_parameter_declarations" ):
                listener.exitList_of_parameter_declarations(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_parameter_declarations" ):
                return visitor.visitList_of_parameter_declarations(self)
            else:
                return visitor.visitChildren(self)




    def list_of_parameter_declarations(self):

        localctx = SysVerilogHDLParser.List_of_parameter_declarationsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 88, self.RULE_list_of_parameter_declarations)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1128
            self.parameter_declaration()
            self.state = 1129
            self.comma_parameter_declaration_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_parameter_declaration_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_parameter_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_parameter_declarationContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_parameter_declarationContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_parameter_declaration_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_parameter_declaration_star" ):
                listener.enterComma_parameter_declaration_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_parameter_declaration_star" ):
                listener.exitComma_parameter_declaration_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_parameter_declaration_star" ):
                return visitor.visitComma_parameter_declaration_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_parameter_declaration_star(self):

        localctx = SysVerilogHDLParser.Comma_parameter_declaration_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 90, self.RULE_comma_parameter_declaration_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1134
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 1131
                self.comma_parameter_declaration()
                self.state = 1136
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_parameter_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def parameter_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_parameter_declaration" ):
                listener.enterComma_parameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_parameter_declaration" ):
                listener.exitComma_parameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_parameter_declaration" ):
                return visitor.visitComma_parameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def comma_parameter_declaration(self):

        localctx = SysVerilogHDLParser.Comma_parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 92, self.RULE_comma_parameter_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1137
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1138
            self.parameter_declaration()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_parameter_descriptionsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_parameter_descriptions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_parameter_descriptions" ):
                listener.enterList_of_parameter_descriptions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_parameter_descriptions" ):
                listener.exitList_of_parameter_descriptions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_parameter_descriptions" ):
                return visitor.visitList_of_parameter_descriptions(self)
            else:
                return visitor.visitChildren(self)




    def list_of_parameter_descriptions(self):

        localctx = SysVerilogHDLParser.List_of_parameter_descriptionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 94, self.RULE_list_of_parameter_descriptions)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1140
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Param_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_hierarchical_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_hierarchical_variable_descriptionsContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_param_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParam_declaration" ):
                listener.enterParam_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParam_declaration" ):
                listener.exitParam_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParam_declaration" ):
                return visitor.visitParam_declaration(self)
            else:
                return visitor.visitChildren(self)




    def param_declaration(self):

        localctx = SysVerilogHDLParser.Param_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 96, self.RULE_param_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1143
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1142
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1146
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1145
                self.dimension_plus()


            self.state = 1148
            self.list_of_hierarchical_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Param_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def param_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Param_declarationContext,0)


        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def int_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Int_declarationContext,0)


        def real_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Real_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Time_declarationContext,0)


        def realtime_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Realtime_declarationContext,0)


        def usertype_variable_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Usertype_variable_declarationContext,0)


        def string_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.String_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_param_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParam_description" ):
                listener.enterParam_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParam_description" ):
                listener.exitParam_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParam_description" ):
                return visitor.visitParam_description(self)
            else:
                return visitor.visitChildren(self)




    def param_description(self):

        localctx = SysVerilogHDLParser.Param_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 98, self.RULE_param_description)
        try:
            self.state = 1159
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,33,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1150
                self.param_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1151
                self.logic_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1152
                self.integer_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1153
                self.int_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1154
                self.real_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1155
                self.time_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1156
                self.realtime_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1157
                self.usertype_variable_declaration()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 1158
                self.string_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Parameter(self):
            return self.getToken(SysVerilogHDLParser.Parameter, 0)

        def param_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Param_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_declaration" ):
                listener.enterParameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_declaration" ):
                listener.exitParameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_declaration" ):
                return visitor.visitParameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def parameter_declaration(self):

        localctx = SysVerilogHDLParser.Parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 100, self.RULE_parameter_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1161
            self.match(SysVerilogHDLParser.Parameter)
            self.state = 1162
            self.param_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Local_parameter_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Localparam(self):
            return self.getToken(SysVerilogHDLParser.Localparam, 0)

        def param_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Param_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_local_parameter_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLocal_parameter_declaration" ):
                listener.enterLocal_parameter_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLocal_parameter_declaration" ):
                listener.exitLocal_parameter_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLocal_parameter_declaration" ):
                return visitor.visitLocal_parameter_declaration(self)
            else:
                return visitor.visitChildren(self)




    def local_parameter_declaration(self):

        localctx = SysVerilogHDLParser.Local_parameter_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 102, self.RULE_local_parameter_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1164
            self.match(SysVerilogHDLParser.Localparam)
            self.state = 1165
            self.param_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_overrideContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Defparam(self):
            return self.getToken(SysVerilogHDLParser.Defparam, 0)

        def param_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Param_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_parameter_override

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_override" ):
                listener.enterParameter_override(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_override" ):
                listener.exitParameter_override(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_override" ):
                return visitor.visitParameter_override(self)
            else:
                return visitor.visitChildren(self)




    def parameter_override(self):

        localctx = SysVerilogHDLParser.Parameter_overrideContext(self, self._ctx, self.state)
        self.enterRule(localctx, 104, self.RULE_parameter_override)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1167
            self.match(SysVerilogHDLParser.Defparam)
            self.state = 1168
            self.param_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_tf_interface_portsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_port_identifiersContext,0)


        def list_of_tf_port_declarations(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_tf_port_declarationsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_tf_interface_ports

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_tf_interface_ports" ):
                listener.enterList_of_tf_interface_ports(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_tf_interface_ports" ):
                listener.exitList_of_tf_interface_ports(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_tf_interface_ports" ):
                return visitor.visitList_of_tf_interface_ports(self)
            else:
                return visitor.visitChildren(self)




    def list_of_tf_interface_ports(self):

        localctx = SysVerilogHDLParser.List_of_tf_interface_portsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 106, self.RULE_list_of_tf_interface_ports)
        try:
            self.state = 1172
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,34,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1170
                self.list_of_port_identifiers()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1171
                self.list_of_tf_port_declarations()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_tf_port_declarationsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_tf_port_declarations_comma(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_tf_port_declarations_commaContext,0)


        def list_of_tf_port_declarations_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_tf_port_declarations_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_tf_port_declarations

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_tf_port_declarations" ):
                listener.enterList_of_tf_port_declarations(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_tf_port_declarations" ):
                listener.exitList_of_tf_port_declarations(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_tf_port_declarations" ):
                return visitor.visitList_of_tf_port_declarations(self)
            else:
                return visitor.visitChildren(self)




    def list_of_tf_port_declarations(self):

        localctx = SysVerilogHDLParser.List_of_tf_port_declarationsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 108, self.RULE_list_of_tf_port_declarations)
        try:
            self.state = 1176
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,35,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1174
                self.list_of_tf_port_declarations_comma()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1175
                self.list_of_tf_port_declarations_semicolon()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_tf_port_declarations_commaContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_tf_port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_tf_port_declarationContext,0)


        def comma_attr_tf_port_declaration_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_attr_tf_port_declaration_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_tf_port_declarations_comma

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_tf_port_declarations_comma" ):
                listener.enterList_of_tf_port_declarations_comma(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_tf_port_declarations_comma" ):
                listener.exitList_of_tf_port_declarations_comma(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_tf_port_declarations_comma" ):
                return visitor.visitList_of_tf_port_declarations_comma(self)
            else:
                return visitor.visitChildren(self)




    def list_of_tf_port_declarations_comma(self):

        localctx = SysVerilogHDLParser.List_of_tf_port_declarations_commaContext(self, self._ctx, self.state)
        self.enterRule(localctx, 110, self.RULE_list_of_tf_port_declarations_comma)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1178
            self.attr_tf_port_declaration()
            self.state = 1179
            self.comma_attr_tf_port_declaration_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_attr_tf_port_declaration_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_attr_tf_port_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_attr_tf_port_declarationContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_attr_tf_port_declarationContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_attr_tf_port_declaration_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_attr_tf_port_declaration_star" ):
                listener.enterComma_attr_tf_port_declaration_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_attr_tf_port_declaration_star" ):
                listener.exitComma_attr_tf_port_declaration_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_attr_tf_port_declaration_star" ):
                return visitor.visitComma_attr_tf_port_declaration_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_attr_tf_port_declaration_star(self):

        localctx = SysVerilogHDLParser.Comma_attr_tf_port_declaration_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 112, self.RULE_comma_attr_tf_port_declaration_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1184
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 1181
                self.comma_attr_tf_port_declaration()
                self.state = 1186
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_attr_tf_port_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def attr_tf_port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_tf_port_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_attr_tf_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_attr_tf_port_declaration" ):
                listener.enterComma_attr_tf_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_attr_tf_port_declaration" ):
                listener.exitComma_attr_tf_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_attr_tf_port_declaration" ):
                return visitor.visitComma_attr_tf_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def comma_attr_tf_port_declaration(self):

        localctx = SysVerilogHDLParser.Comma_attr_tf_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 114, self.RULE_comma_attr_tf_port_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1187
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1188
            self.attr_tf_port_declaration()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_tf_port_declarations_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_tf_port_declaration_semicolon_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_tf_port_declaration_semicolon_plusContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_tf_port_declarations_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_tf_port_declarations_semicolon" ):
                listener.enterList_of_tf_port_declarations_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_tf_port_declarations_semicolon" ):
                listener.exitList_of_tf_port_declarations_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_tf_port_declarations_semicolon" ):
                return visitor.visitList_of_tf_port_declarations_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def list_of_tf_port_declarations_semicolon(self):

        localctx = SysVerilogHDLParser.List_of_tf_port_declarations_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 116, self.RULE_list_of_tf_port_declarations_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1190
            self.attr_tf_port_declaration_semicolon_plus()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_tf_port_declaration_semicolon_plusContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_tf_port_declaration_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Attr_tf_port_declaration_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Attr_tf_port_declaration_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_tf_port_declaration_semicolon_plus

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_tf_port_declaration_semicolon_plus" ):
                listener.enterAttr_tf_port_declaration_semicolon_plus(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_tf_port_declaration_semicolon_plus" ):
                listener.exitAttr_tf_port_declaration_semicolon_plus(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_tf_port_declaration_semicolon_plus" ):
                return visitor.visitAttr_tf_port_declaration_semicolon_plus(self)
            else:
                return visitor.visitChildren(self)




    def attr_tf_port_declaration_semicolon_plus(self):

        localctx = SysVerilogHDLParser.Attr_tf_port_declaration_semicolon_plusContext(self, self._ctx, self.state)
        self.enterRule(localctx, 118, self.RULE_attr_tf_port_declaration_semicolon_plus)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1193 
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while True:
                self.state = 1192
                self.attr_tf_port_declaration_semicolon()
                self.state = 1195 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if not (((((_la - 55)) & ~0x3f) == 0 and ((1 << (_la - 55)) & ((1 << (SysVerilogHDLParser.Automatic - 55)) | (1 << (SysVerilogHDLParser.Bit - 55)) | (1 << (SysVerilogHDLParser.Byte - 55)) | (1 << (SysVerilogHDLParser.Const - 55)) | (1 << (SysVerilogHDLParser.Inout - 55)) | (1 << (SysVerilogHDLParser.Input - 55)) | (1 << (SysVerilogHDLParser.Int - 55)) | (1 << (SysVerilogHDLParser.Integer - 55)) | (1 << (SysVerilogHDLParser.Logic - 55)))) != 0) or ((((_la - 125)) & ~0x3f) == 0 and ((1 << (_la - 125)) & ((1 << (SysVerilogHDLParser.NONE - 125)) | (1 << (SysVerilogHDLParser.Output - 125)) | (1 << (SysVerilogHDLParser.Real - 125)) | (1 << (SysVerilogHDLParser.Ref - 125)) | (1 << (SysVerilogHDLParser.Reg - 125)) | (1 << (SysVerilogHDLParser.Signed - 125)) | (1 << (SysVerilogHDLParser.Static - 125)) | (1 << (SysVerilogHDLParser.SVString - 125)) | (1 << (SysVerilogHDLParser.Supply0 - 125)) | (1 << (SysVerilogHDLParser.Supply1 - 125)) | (1 << (SysVerilogHDLParser.Time - 125)) | (1 << (SysVerilogHDLParser.Tri - 125)) | (1 << (SysVerilogHDLParser.Tri_and - 125)) | (1 << (SysVerilogHDLParser.Tri_or - 125)) | (1 << (SysVerilogHDLParser.Tri_reg - 125)) | (1 << (SysVerilogHDLParser.Tri0 - 125)) | (1 << (SysVerilogHDLParser.Tri1 - 125)) | (1 << (SysVerilogHDLParser.Unsigned - 125)))) != 0) or ((((_la - 190)) & ~0x3f) == 0 and ((1 << (_la - 190)) & ((1 << (SysVerilogHDLParser.Uwire - 190)) | (1 << (SysVerilogHDLParser.Wand - 190)) | (1 << (SysVerilogHDLParser.Wire - 190)) | (1 << (SysVerilogHDLParser.Wor - 190)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 190)) | (1 << (SysVerilogHDLParser.Simple_identifier - 190)) | (1 << (SysVerilogHDLParser.Left_bracket - 190)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 190)))) != 0)):
                    break

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_tf_port_declaration_semicolon_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_tf_port_declaration_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Attr_tf_port_declaration_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Attr_tf_port_declaration_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_tf_port_declaration_semicolon_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_tf_port_declaration_semicolon_star" ):
                listener.enterAttr_tf_port_declaration_semicolon_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_tf_port_declaration_semicolon_star" ):
                listener.exitAttr_tf_port_declaration_semicolon_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_tf_port_declaration_semicolon_star" ):
                return visitor.visitAttr_tf_port_declaration_semicolon_star(self)
            else:
                return visitor.visitChildren(self)




    def attr_tf_port_declaration_semicolon_star(self):

        localctx = SysVerilogHDLParser.Attr_tf_port_declaration_semicolon_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 120, self.RULE_attr_tf_port_declaration_semicolon_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1200
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 55)) & ~0x3f) == 0 and ((1 << (_la - 55)) & ((1 << (SysVerilogHDLParser.Automatic - 55)) | (1 << (SysVerilogHDLParser.Bit - 55)) | (1 << (SysVerilogHDLParser.Byte - 55)) | (1 << (SysVerilogHDLParser.Const - 55)) | (1 << (SysVerilogHDLParser.Inout - 55)) | (1 << (SysVerilogHDLParser.Input - 55)) | (1 << (SysVerilogHDLParser.Int - 55)) | (1 << (SysVerilogHDLParser.Integer - 55)) | (1 << (SysVerilogHDLParser.Logic - 55)))) != 0) or ((((_la - 125)) & ~0x3f) == 0 and ((1 << (_la - 125)) & ((1 << (SysVerilogHDLParser.NONE - 125)) | (1 << (SysVerilogHDLParser.Output - 125)) | (1 << (SysVerilogHDLParser.Real - 125)) | (1 << (SysVerilogHDLParser.Ref - 125)) | (1 << (SysVerilogHDLParser.Reg - 125)) | (1 << (SysVerilogHDLParser.Signed - 125)) | (1 << (SysVerilogHDLParser.Static - 125)) | (1 << (SysVerilogHDLParser.SVString - 125)) | (1 << (SysVerilogHDLParser.Supply0 - 125)) | (1 << (SysVerilogHDLParser.Supply1 - 125)) | (1 << (SysVerilogHDLParser.Time - 125)) | (1 << (SysVerilogHDLParser.Tri - 125)) | (1 << (SysVerilogHDLParser.Tri_and - 125)) | (1 << (SysVerilogHDLParser.Tri_or - 125)) | (1 << (SysVerilogHDLParser.Tri_reg - 125)) | (1 << (SysVerilogHDLParser.Tri0 - 125)) | (1 << (SysVerilogHDLParser.Tri1 - 125)) | (1 << (SysVerilogHDLParser.Unsigned - 125)))) != 0) or ((((_la - 190)) & ~0x3f) == 0 and ((1 << (_la - 190)) & ((1 << (SysVerilogHDLParser.Uwire - 190)) | (1 << (SysVerilogHDLParser.Wand - 190)) | (1 << (SysVerilogHDLParser.Wire - 190)) | (1 << (SysVerilogHDLParser.Wor - 190)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 190)) | (1 << (SysVerilogHDLParser.Simple_identifier - 190)) | (1 << (SysVerilogHDLParser.Left_bracket - 190)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 190)))) != 0):
                self.state = 1197
                self.attr_tf_port_declaration_semicolon()
                self.state = 1202
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_tf_port_declaration_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_tf_port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_tf_port_declarationContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_tf_port_declaration_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_tf_port_declaration_semicolon" ):
                listener.enterAttr_tf_port_declaration_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_tf_port_declaration_semicolon" ):
                listener.exitAttr_tf_port_declaration_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_tf_port_declaration_semicolon" ):
                return visitor.visitAttr_tf_port_declaration_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def attr_tf_port_declaration_semicolon(self):

        localctx = SysVerilogHDLParser.Attr_tf_port_declaration_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 122, self.RULE_attr_tf_port_declaration_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1203
            self.attr_tf_port_declaration()
            self.state = 1204
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_tf_port_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def tf_port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Tf_port_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_tf_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_tf_port_declaration" ):
                listener.enterAttr_tf_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_tf_port_declaration" ):
                listener.exitAttr_tf_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_tf_port_declaration" ):
                return visitor.visitAttr_tf_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def attr_tf_port_declaration(self):

        localctx = SysVerilogHDLParser.Attr_tf_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 124, self.RULE_attr_tf_port_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1206
            self.attribute_instance_star()
            self.state = 1207
            self.tf_port_declaration()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_port_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def inout_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Inout_declarationContext,0)


        def input_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_declarationContext,0)


        def output_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_declarationContext,0)


        def ref_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Ref_declarationContext,0)


        def tf_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Tf_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_tf_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_port_declaration" ):
                listener.enterTf_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_port_declaration" ):
                listener.exitTf_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_port_declaration" ):
                return visitor.visitTf_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_port_declaration(self):

        localctx = SysVerilogHDLParser.Tf_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 126, self.RULE_tf_port_declaration)
        try:
            self.state = 1214
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Inout]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1209
                self.inout_declaration()
                pass
            elif token in [SysVerilogHDLParser.Input]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1210
                self.input_declaration()
                pass
            elif token in [SysVerilogHDLParser.Output]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1211
                self.output_declaration()
                pass
            elif token in [SysVerilogHDLParser.Ref]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1212
                self.ref_declaration()
                pass
            elif token in [SysVerilogHDLParser.Automatic, SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte, SysVerilogHDLParser.Const, SysVerilogHDLParser.Int, SysVerilogHDLParser.Integer, SysVerilogHDLParser.Logic, SysVerilogHDLParser.NONE, SysVerilogHDLParser.Real, SysVerilogHDLParser.Reg, SysVerilogHDLParser.Signed, SysVerilogHDLParser.Static, SysVerilogHDLParser.SVString, SysVerilogHDLParser.Supply0, SysVerilogHDLParser.Supply1, SysVerilogHDLParser.Time, SysVerilogHDLParser.Tri, SysVerilogHDLParser.Tri_and, SysVerilogHDLParser.Tri_or, SysVerilogHDLParser.Tri_reg, SysVerilogHDLParser.Tri0, SysVerilogHDLParser.Tri1, SysVerilogHDLParser.Unsigned, SysVerilogHDLParser.Uwire, SysVerilogHDLParser.Wand, SysVerilogHDLParser.Wire, SysVerilogHDLParser.Wor, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier, SysVerilogHDLParser.Left_bracket]:
                self.enterOuterAlt(localctx, 5)
                self.state = 1213
                self.tf_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_interface_portsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_port_identifiers(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_port_identifiersContext,0)


        def list_of_port_declarations(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_port_declarationsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_interface_ports

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_interface_ports" ):
                listener.enterList_of_interface_ports(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_interface_ports" ):
                listener.exitList_of_interface_ports(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_interface_ports" ):
                return visitor.visitList_of_interface_ports(self)
            else:
                return visitor.visitChildren(self)




    def list_of_interface_ports(self):

        localctx = SysVerilogHDLParser.List_of_interface_portsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 128, self.RULE_list_of_interface_ports)
        try:
            self.state = 1218
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1216
                self.list_of_port_identifiers()
                pass
            elif token in [SysVerilogHDLParser.Inout, SysVerilogHDLParser.Input, SysVerilogHDLParser.Output, SysVerilogHDLParser.Ref, SysVerilogHDLParser.Open_parenthesis]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1217
                self.list_of_port_declarations()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_identifiersContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_identifierContext,0)


        def comma_port_identifier_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_port_identifier_starContext,0)


        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_port_identifiers

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_identifiers" ):
                listener.enterList_of_port_identifiers(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_identifiers" ):
                listener.exitList_of_port_identifiers(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_identifiers" ):
                return visitor.visitList_of_port_identifiers(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_identifiers(self):

        localctx = SysVerilogHDLParser.List_of_port_identifiersContext(self, self._ctx, self.state)
        self.enterRule(localctx, 130, self.RULE_list_of_port_identifiers)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1220
            self.port_identifier()
            self.state = 1221
            self.comma_port_identifier_star()
            self.state = 1223
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Comma:
                self.state = 1222
                self.match(SysVerilogHDLParser.Comma)


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_port_identifier_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_port_identifier(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_port_identifierContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_port_identifierContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_port_identifier_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_port_identifier_star" ):
                listener.enterComma_port_identifier_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_port_identifier_star" ):
                listener.exitComma_port_identifier_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_port_identifier_star" ):
                return visitor.visitComma_port_identifier_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_port_identifier_star(self):

        localctx = SysVerilogHDLParser.Comma_port_identifier_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 132, self.RULE_comma_port_identifier_star)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1228
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,42,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1225
                    self.comma_port_identifier() 
                self.state = 1230
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,42,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_port_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def port_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_port_identifier" ):
                listener.enterComma_port_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_port_identifier" ):
                listener.exitComma_port_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_port_identifier" ):
                return visitor.visitComma_port_identifier(self)
            else:
                return visitor.visitChildren(self)




    def comma_port_identifier(self):

        localctx = SysVerilogHDLParser.Comma_port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 134, self.RULE_comma_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1231
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1232
            self.port_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_port_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_identifier" ):
                listener.enterPort_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_identifier" ):
                listener.exitPort_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_identifier" ):
                return visitor.visitPort_identifier(self)
            else:
                return visitor.visitChildren(self)




    def port_identifier(self):

        localctx = SysVerilogHDLParser.Port_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 136, self.RULE_port_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1234
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_declarationsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_port_declarations_comma(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_port_declarations_commaContext,0)


        def list_of_port_declarations_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_port_declarations_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_port_declarations

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_declarations" ):
                listener.enterList_of_port_declarations(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_declarations" ):
                listener.exitList_of_port_declarations(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_declarations" ):
                return visitor.visitList_of_port_declarations(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_declarations(self):

        localctx = SysVerilogHDLParser.List_of_port_declarationsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 138, self.RULE_list_of_port_declarations)
        try:
            self.state = 1238
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,43,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1236
                self.list_of_port_declarations_comma()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1237
                self.list_of_port_declarations_semicolon()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_declarations_commaContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_port_declarationContext,0)


        def comma_attr_port_declaration_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_attr_port_declaration_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_port_declarations_comma

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_declarations_comma" ):
                listener.enterList_of_port_declarations_comma(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_declarations_comma" ):
                listener.exitList_of_port_declarations_comma(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_declarations_comma" ):
                return visitor.visitList_of_port_declarations_comma(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_declarations_comma(self):

        localctx = SysVerilogHDLParser.List_of_port_declarations_commaContext(self, self._ctx, self.state)
        self.enterRule(localctx, 140, self.RULE_list_of_port_declarations_comma)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1240
            self.attr_port_declaration()
            self.state = 1241
            self.comma_attr_port_declaration_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_attr_port_declaration_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_attr_port_declaration(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_attr_port_declarationContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_attr_port_declarationContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_attr_port_declaration_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_attr_port_declaration_star" ):
                listener.enterComma_attr_port_declaration_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_attr_port_declaration_star" ):
                listener.exitComma_attr_port_declaration_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_attr_port_declaration_star" ):
                return visitor.visitComma_attr_port_declaration_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_attr_port_declaration_star(self):

        localctx = SysVerilogHDLParser.Comma_attr_port_declaration_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 142, self.RULE_comma_attr_port_declaration_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1246
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 1243
                self.comma_attr_port_declaration()
                self.state = 1248
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_attr_port_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def attr_port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_port_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_attr_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_attr_port_declaration" ):
                listener.enterComma_attr_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_attr_port_declaration" ):
                listener.exitComma_attr_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_attr_port_declaration" ):
                return visitor.visitComma_attr_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def comma_attr_port_declaration(self):

        localctx = SysVerilogHDLParser.Comma_attr_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 144, self.RULE_comma_attr_port_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1249
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1250
            self.attr_port_declaration()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_port_declarations_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_port_declaration_semicolon_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_port_declaration_semicolon_plusContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_port_declarations_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_port_declarations_semicolon" ):
                listener.enterList_of_port_declarations_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_port_declarations_semicolon" ):
                listener.exitList_of_port_declarations_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_port_declarations_semicolon" ):
                return visitor.visitList_of_port_declarations_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def list_of_port_declarations_semicolon(self):

        localctx = SysVerilogHDLParser.List_of_port_declarations_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 146, self.RULE_list_of_port_declarations_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1252
            self.attr_port_declaration_semicolon_plus()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_port_declaration_semicolon_plusContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_port_declaration_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Attr_port_declaration_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Attr_port_declaration_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_port_declaration_semicolon_plus

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_port_declaration_semicolon_plus" ):
                listener.enterAttr_port_declaration_semicolon_plus(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_port_declaration_semicolon_plus" ):
                listener.exitAttr_port_declaration_semicolon_plus(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_port_declaration_semicolon_plus" ):
                return visitor.visitAttr_port_declaration_semicolon_plus(self)
            else:
                return visitor.visitChildren(self)




    def attr_port_declaration_semicolon_plus(self):

        localctx = SysVerilogHDLParser.Attr_port_declaration_semicolon_plusContext(self, self._ctx, self.state)
        self.enterRule(localctx, 148, self.RULE_attr_port_declaration_semicolon_plus)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1255 
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while True:
                self.state = 1254
                self.attr_port_declaration_semicolon()
                self.state = 1257 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if not (((((_la - 106)) & ~0x3f) == 0 and ((1 << (_la - 106)) & ((1 << (SysVerilogHDLParser.Inout - 106)) | (1 << (SysVerilogHDLParser.Input - 106)) | (1 << (SysVerilogHDLParser.Output - 106)) | (1 << (SysVerilogHDLParser.Ref - 106)))) != 0) or _la==SysVerilogHDLParser.Open_parenthesis):
                    break

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_port_declaration_semicolon_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_port_declaration_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Attr_port_declaration_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Attr_port_declaration_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_port_declaration_semicolon_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_port_declaration_semicolon_star" ):
                listener.enterAttr_port_declaration_semicolon_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_port_declaration_semicolon_star" ):
                listener.exitAttr_port_declaration_semicolon_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_port_declaration_semicolon_star" ):
                return visitor.visitAttr_port_declaration_semicolon_star(self)
            else:
                return visitor.visitChildren(self)




    def attr_port_declaration_semicolon_star(self):

        localctx = SysVerilogHDLParser.Attr_port_declaration_semicolon_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 150, self.RULE_attr_port_declaration_semicolon_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1262
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 106)) & ~0x3f) == 0 and ((1 << (_la - 106)) & ((1 << (SysVerilogHDLParser.Inout - 106)) | (1 << (SysVerilogHDLParser.Input - 106)) | (1 << (SysVerilogHDLParser.Output - 106)) | (1 << (SysVerilogHDLParser.Ref - 106)))) != 0) or _la==SysVerilogHDLParser.Open_parenthesis:
                self.state = 1259
                self.attr_port_declaration_semicolon()
                self.state = 1264
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_port_declaration_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_port_declarationContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_port_declaration_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_port_declaration_semicolon" ):
                listener.enterAttr_port_declaration_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_port_declaration_semicolon" ):
                listener.exitAttr_port_declaration_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_port_declaration_semicolon" ):
                return visitor.visitAttr_port_declaration_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def attr_port_declaration_semicolon(self):

        localctx = SysVerilogHDLParser.Attr_port_declaration_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 152, self.RULE_attr_port_declaration_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1265
            self.attr_port_declaration()
            self.state = 1266
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_port_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_port_declaration" ):
                listener.enterAttr_port_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_port_declaration" ):
                listener.exitAttr_port_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_port_declaration" ):
                return visitor.visitAttr_port_declaration(self)
            else:
                return visitor.visitChildren(self)




    def attr_port_declaration(self):

        localctx = SysVerilogHDLParser.Attr_port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 154, self.RULE_attr_port_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1268
            self.attribute_instance_star()
            self.state = 1269
            self.port_declaration()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def inout_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Inout_declarationContext,0)


        def input_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_declarationContext,0)


        def output_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_declarationContext,0)


        def ref_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Ref_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_port_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_declaration" ):
                listener.enterPort_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_declaration" ):
                listener.exitPort_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_declaration" ):
                return visitor.visitPort_declaration(self)
            else:
                return visitor.visitChildren(self)




    def port_declaration(self):

        localctx = SysVerilogHDLParser.Port_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 156, self.RULE_port_declaration)
        try:
            self.state = 1275
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Inout]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1271
                self.inout_declaration()
                pass
            elif token in [SysVerilogHDLParser.Input]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1272
                self.input_declaration()
                pass
            elif token in [SysVerilogHDLParser.Output]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1273
                self.output_declaration()
                pass
            elif token in [SysVerilogHDLParser.Ref]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1274
                self.ref_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_port_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_description" ):
                listener.enterPort_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_description" ):
                listener.exitPort_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_description" ):
                return visitor.visitPort_description(self)
            else:
                return visitor.visitChildren(self)




    def port_description(self):

        localctx = SysVerilogHDLParser.Port_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 158, self.RULE_port_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1278
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1277
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1281
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1280
                self.dimension_plus()


            self.state = 1283
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_descriptionContext,0)


        def net_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_inout_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_description" ):
                listener.enterInout_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_description" ):
                listener.exitInout_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_description" ):
                return visitor.visitInout_description(self)
            else:
                return visitor.visitChildren(self)




    def inout_description(self):

        localctx = SysVerilogHDLParser.Inout_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 160, self.RULE_inout_description)
        try:
            self.state = 1287
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Signed, SysVerilogHDLParser.Unsigned, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier, SysVerilogHDLParser.Left_bracket]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1285
                self.port_description()
                pass
            elif token in [SysVerilogHDLParser.NONE, SysVerilogHDLParser.Supply0, SysVerilogHDLParser.Supply1, SysVerilogHDLParser.Tri, SysVerilogHDLParser.Tri_and, SysVerilogHDLParser.Tri_or, SysVerilogHDLParser.Tri_reg, SysVerilogHDLParser.Tri0, SysVerilogHDLParser.Tri1, SysVerilogHDLParser.Uwire, SysVerilogHDLParser.Wand, SysVerilogHDLParser.Wire, SysVerilogHDLParser.Wor]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1286
                self.net_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_descriptionContext,0)


        def net_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_declarationContext,0)


        def reg_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Reg_declarationContext,0)


        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def bits_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_declarationContext,0)


        def int_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Int_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def real_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Real_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Time_declarationContext,0)


        def usertype_variable_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Usertype_variable_declarationContext,0)


        def string_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.String_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_input_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_description" ):
                listener.enterInput_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_description" ):
                listener.exitInput_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_description" ):
                return visitor.visitInput_description(self)
            else:
                return visitor.visitChildren(self)




    def input_description(self):

        localctx = SysVerilogHDLParser.Input_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 162, self.RULE_input_description)
        try:
            self.state = 1300
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,51,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1289
                self.port_description()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1290
                self.net_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1291
                self.reg_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1292
                self.logic_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1293
                self.bits_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1294
                self.int_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1295
                self.integer_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1296
                self.real_declaration()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 1297
                self.time_declaration()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 1298
                self.usertype_variable_declaration()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 1299
                self.string_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_descriptionContext,0)


        def net_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_declarationContext,0)


        def reg_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Reg_declarationContext,0)


        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Time_declarationContext,0)


        def usertype_variable_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Usertype_variable_declarationContext,0)


        def string_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.String_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_output_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_description" ):
                listener.enterOutput_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_description" ):
                listener.exitOutput_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_description" ):
                return visitor.visitOutput_description(self)
            else:
                return visitor.visitChildren(self)




    def output_description(self):

        localctx = SysVerilogHDLParser.Output_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 164, self.RULE_output_description)
        try:
            self.state = 1310
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,52,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1302
                self.port_description()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1303
                self.net_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1304
                self.reg_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1305
                self.logic_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1306
                self.integer_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1307
                self.time_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1308
                self.usertype_variable_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1309
                self.string_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ref_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_descriptionContext,0)


        def net_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_declarationContext,0)


        def reg_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Reg_declarationContext,0)


        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Time_declarationContext,0)


        def usertype_variable_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Usertype_variable_declarationContext,0)


        def string_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.String_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_ref_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRef_description" ):
                listener.enterRef_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRef_description" ):
                listener.exitRef_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRef_description" ):
                return visitor.visitRef_description(self)
            else:
                return visitor.visitChildren(self)




    def ref_description(self):

        localctx = SysVerilogHDLParser.Ref_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 166, self.RULE_ref_description)
        try:
            self.state = 1320
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,53,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1312
                self.port_description()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1313
                self.net_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1314
                self.reg_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1315
                self.logic_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1316
                self.integer_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1317
                self.time_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1318
                self.usertype_variable_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1319
                self.string_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Tf_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def port_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_descriptionContext,0)


        def real_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Real_declarationContext,0)


        def net_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_declarationContext,0)


        def reg_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Reg_declarationContext,0)


        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def bits_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_declarationContext,0)


        def int_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Int_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Time_declarationContext,0)


        def usertype_variable_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Usertype_variable_declarationContext,0)


        def string_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.String_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_tf_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTf_declaration" ):
                listener.enterTf_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTf_declaration" ):
                listener.exitTf_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTf_declaration" ):
                return visitor.visitTf_declaration(self)
            else:
                return visitor.visitChildren(self)




    def tf_declaration(self):

        localctx = SysVerilogHDLParser.Tf_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 168, self.RULE_tf_declaration)
        try:
            self.state = 1333
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,54,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1322
                self.port_description()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1323
                self.real_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1324
                self.net_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1325
                self.reg_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1326
                self.logic_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1327
                self.bits_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 1328
                self.int_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 1329
                self.integer_declaration()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 1330
                self.time_declaration()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 1331
                self.usertype_variable_declaration()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 1332
                self.string_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Inout(self):
            return self.getToken(SysVerilogHDLParser.Inout, 0)

        def inout_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Inout_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_inout_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_declaration" ):
                listener.enterInout_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_declaration" ):
                listener.exitInout_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_declaration" ):
                return visitor.visitInout_declaration(self)
            else:
                return visitor.visitChildren(self)




    def inout_declaration(self):

        localctx = SysVerilogHDLParser.Inout_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 170, self.RULE_inout_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1335
            self.match(SysVerilogHDLParser.Inout)
            self.state = 1336
            self.inout_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Input(self):
            return self.getToken(SysVerilogHDLParser.Input, 0)

        def input_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_input_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_declaration" ):
                listener.enterInput_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_declaration" ):
                listener.exitInput_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_declaration" ):
                return visitor.visitInput_declaration(self)
            else:
                return visitor.visitChildren(self)




    def input_declaration(self):

        localctx = SysVerilogHDLParser.Input_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 172, self.RULE_input_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1338
            self.match(SysVerilogHDLParser.Input)
            self.state = 1339
            self.input_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Output(self):
            return self.getToken(SysVerilogHDLParser.Output, 0)

        def output_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_output_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_declaration" ):
                listener.enterOutput_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_declaration" ):
                listener.exitOutput_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_declaration" ):
                return visitor.visitOutput_declaration(self)
            else:
                return visitor.visitChildren(self)




    def output_declaration(self):

        localctx = SysVerilogHDLParser.Output_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 174, self.RULE_output_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1341
            self.match(SysVerilogHDLParser.Output)
            self.state = 1342
            self.output_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ref_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Ref(self):
            return self.getToken(SysVerilogHDLParser.Ref, 0)

        def ref_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Ref_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_ref_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRef_declaration" ):
                listener.enterRef_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRef_declaration" ):
                listener.exitRef_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRef_declaration" ):
                return visitor.visitRef_declaration(self)
            else:
                return visitor.visitChildren(self)




    def ref_declaration(self):

        localctx = SysVerilogHDLParser.Ref_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 176, self.RULE_ref_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1344
            self.match(SysVerilogHDLParser.Ref)
            self.state = 1345
            self.ref_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class User_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def user_type_identifer(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.User_type_identiferContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_user_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUser_type" ):
                listener.enterUser_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUser_type" ):
                listener.exitUser_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUser_type" ):
                return visitor.visitUser_type(self)
            else:
                return visitor.visitChildren(self)




    def user_type(self):

        localctx = SysVerilogHDLParser.User_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 178, self.RULE_user_type)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1347
            self.user_type_identifer()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class User_type_identiferContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_user_type_identifer

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUser_type_identifer" ):
                listener.enterUser_type_identifer(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUser_type_identifer" ):
                listener.exitUser_type_identifer(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUser_type_identifer" ):
                return visitor.visitUser_type_identifer(self)
            else:
                return visitor.visitChildren(self)




    def user_type_identifer(self):

        localctx = SysVerilogHDLParser.User_type_identiferContext(self, self._ctx, self.state)
        self.enterRule(localctx, 180, self.RULE_user_type_identifer)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1349
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dimension_plusContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.DimensionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.DimensionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_dimension_plus

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDimension_plus" ):
                listener.enterDimension_plus(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDimension_plus" ):
                listener.exitDimension_plus(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDimension_plus" ):
                return visitor.visitDimension_plus(self)
            else:
                return visitor.visitChildren(self)




    def dimension_plus(self):

        localctx = SysVerilogHDLParser.Dimension_plusContext(self, self._ctx, self.state)
        self.enterRule(localctx, 182, self.RULE_dimension_plus)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1352 
            self._errHandler.sync(self)
            _alt = 1
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt == 1:
                    self.state = 1351
                    self.dimension()

                else:
                    raise NoViableAltException(self)
                self.state = 1354 
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,55,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dimension_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def dimension(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.DimensionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.DimensionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_dimension_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDimension_star" ):
                listener.enterDimension_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDimension_star" ):
                listener.exitDimension_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDimension_star" ):
                return visitor.visitDimension_star(self)
            else:
                return visitor.visitChildren(self)




    def dimension_star(self):

        localctx = SysVerilogHDLParser.Dimension_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 184, self.RULE_dimension_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1359
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1356
                self.dimension()
                self.state = 1361
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class DimensionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Left_bracket(self):
            return self.getToken(SysVerilogHDLParser.Left_bracket, 0)

        def range_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Range_expressionContext,0)


        def Right_bracket(self):
            return self.getToken(SysVerilogHDLParser.Right_bracket, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_dimension

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDimension" ):
                listener.enterDimension(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDimension" ):
                listener.exitDimension(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDimension" ):
                return visitor.visitDimension(self)
            else:
                return visitor.visitChildren(self)




    def dimension(self):

        localctx = SysVerilogHDLParser.DimensionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 186, self.RULE_dimension)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1362
            self.match(SysVerilogHDLParser.Left_bracket)
            self.state = 1363
            self.range_expression()
            self.state = 1364
            self.match(SysVerilogHDLParser.Right_bracket)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Range_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def index_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Index_expressionContext,0)


        def sb_range(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Sb_rangeContext,0)


        def base_increment_range(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Base_increment_rangeContext,0)


        def base_decrement_range(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Base_decrement_rangeContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_range_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRange_expression" ):
                listener.enterRange_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRange_expression" ):
                listener.exitRange_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRange_expression" ):
                return visitor.visitRange_expression(self)
            else:
                return visitor.visitChildren(self)




    def range_expression(self):

        localctx = SysVerilogHDLParser.Range_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 188, self.RULE_range_expression)
        try:
            self.state = 1370
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,57,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1366
                self.index_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1367
                self.sb_range()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1368
                self.base_increment_range()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1369
                self.base_decrement_range()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Index_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def Dollar(self):
            return self.getToken(SysVerilogHDLParser.Dollar, 0)

        def Star(self):
            return self.getToken(SysVerilogHDLParser.Star, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_index_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIndex_expression" ):
                listener.enterIndex_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIndex_expression" ):
                listener.exitIndex_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIndex_expression" ):
                return visitor.visitIndex_expression(self)
            else:
                return visitor.visitChildren(self)




    def index_expression(self):

        localctx = SysVerilogHDLParser.Index_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 190, self.RULE_index_expression)
        try:
            self.state = 1375
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.T__1, SysVerilogHDLParser.T__2, SysVerilogHDLParser.T__3, SysVerilogHDLParser.T__4, SysVerilogHDLParser.T__5, SysVerilogHDLParser.T__6, SysVerilogHDLParser.T__7, SysVerilogHDLParser.T__8, SysVerilogHDLParser.T__9, SysVerilogHDLParser.T__10, SysVerilogHDLParser.T__26, SysVerilogHDLParser.T__27, SysVerilogHDLParser.Binary_number, SysVerilogHDLParser.Decimal_number, SysVerilogHDLParser.Fixed_point_number, SysVerilogHDLParser.Hex_number, SysVerilogHDLParser.Octal_number, SysVerilogHDLParser.Real_exp_form, SysVerilogHDLParser.Int, SysVerilogHDLParser.Signed, SysVerilogHDLParser.Unsigned, SysVerilogHDLParser.Dollar_Identifier, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier, SysVerilogHDLParser.String_literal, SysVerilogHDLParser.Left_curly_bracket, SysVerilogHDLParser.Open_parenthesis, SysVerilogHDLParser.Quote, SysVerilogHDLParser.Tilde]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1372
                self.expression()
                pass
            elif token in [SysVerilogHDLParser.Dollar]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1373
                self.match(SysVerilogHDLParser.Dollar)
                pass
            elif token in [SysVerilogHDLParser.Star]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1374
                self.match(SysVerilogHDLParser.Star)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sb_rangeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def base_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Base_expressionContext,0)


        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_sb_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSb_range" ):
                listener.enterSb_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSb_range" ):
                listener.exitSb_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSb_range" ):
                return visitor.visitSb_range(self)
            else:
                return visitor.visitChildren(self)




    def sb_range(self):

        localctx = SysVerilogHDLParser.Sb_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 192, self.RULE_sb_range)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1377
            self.base_expression()
            self.state = 1378
            self.match(SysVerilogHDLParser.Colon)
            self.state = 1379
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Base_increment_rangeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def base_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Base_expressionContext,0)


        def Plus_colon(self):
            return self.getToken(SysVerilogHDLParser.Plus_colon, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_base_increment_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBase_increment_range" ):
                listener.enterBase_increment_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBase_increment_range" ):
                listener.exitBase_increment_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBase_increment_range" ):
                return visitor.visitBase_increment_range(self)
            else:
                return visitor.visitChildren(self)




    def base_increment_range(self):

        localctx = SysVerilogHDLParser.Base_increment_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 194, self.RULE_base_increment_range)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1381
            self.base_expression()
            self.state = 1382
            self.match(SysVerilogHDLParser.Plus_colon)
            self.state = 1383
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Base_decrement_rangeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def base_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Base_expressionContext,0)


        def Minus_colon(self):
            return self.getToken(SysVerilogHDLParser.Minus_colon, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_base_decrement_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBase_decrement_range" ):
                listener.enterBase_decrement_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBase_decrement_range" ):
                listener.exitBase_decrement_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBase_decrement_range" ):
                return visitor.visitBase_decrement_range(self)
            else:
                return visitor.visitChildren(self)




    def base_decrement_range(self):

        localctx = SysVerilogHDLParser.Base_decrement_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 196, self.RULE_base_decrement_range)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1385
            self.base_expression()
            self.state = 1386
            self.match(SysVerilogHDLParser.Minus_colon)
            self.state = 1387
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Base_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_base_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBase_expression" ):
                listener.enterBase_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBase_expression" ):
                listener.exitBase_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBase_expression" ):
                return visitor.visitBase_expression(self)
            else:
                return visitor.visitChildren(self)




    def base_expression(self):

        localctx = SysVerilogHDLParser.Base_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 198, self.RULE_base_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1389
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Supply0(self):
            return self.getToken(SysVerilogHDLParser.Supply0, 0)

        def Supply1(self):
            return self.getToken(SysVerilogHDLParser.Supply1, 0)

        def Tri(self):
            return self.getToken(SysVerilogHDLParser.Tri, 0)

        def Tri_and(self):
            return self.getToken(SysVerilogHDLParser.Tri_and, 0)

        def Tri_or(self):
            return self.getToken(SysVerilogHDLParser.Tri_or, 0)

        def Tri_reg(self):
            return self.getToken(SysVerilogHDLParser.Tri_reg, 0)

        def Tri0(self):
            return self.getToken(SysVerilogHDLParser.Tri0, 0)

        def Tri1(self):
            return self.getToken(SysVerilogHDLParser.Tri1, 0)

        def Uwire(self):
            return self.getToken(SysVerilogHDLParser.Uwire, 0)

        def Wire(self):
            return self.getToken(SysVerilogHDLParser.Wire, 0)

        def Wand(self):
            return self.getToken(SysVerilogHDLParser.Wand, 0)

        def Wor(self):
            return self.getToken(SysVerilogHDLParser.Wor, 0)

        def NONE(self):
            return self.getToken(SysVerilogHDLParser.NONE, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_net_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_type" ):
                listener.enterNet_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_type" ):
                listener.exitNet_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_type" ):
                return visitor.visitNet_type(self)
            else:
                return visitor.visitChildren(self)




    def net_type(self):

        localctx = SysVerilogHDLParser.Net_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 200, self.RULE_net_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1391
            _la = self._input.LA(1)
            if not(((((_la - 125)) & ~0x3f) == 0 and ((1 << (_la - 125)) & ((1 << (SysVerilogHDLParser.NONE - 125)) | (1 << (SysVerilogHDLParser.Supply0 - 125)) | (1 << (SysVerilogHDLParser.Supply1 - 125)) | (1 << (SysVerilogHDLParser.Tri - 125)) | (1 << (SysVerilogHDLParser.Tri_and - 125)) | (1 << (SysVerilogHDLParser.Tri_or - 125)) | (1 << (SysVerilogHDLParser.Tri_reg - 125)) | (1 << (SysVerilogHDLParser.Tri0 - 125)) | (1 << (SysVerilogHDLParser.Tri1 - 125)))) != 0) or ((((_la - 190)) & ~0x3f) == 0 and ((1 << (_la - 190)) & ((1 << (SysVerilogHDLParser.Uwire - 190)) | (1 << (SysVerilogHDLParser.Wand - 190)) | (1 << (SysVerilogHDLParser.Wire - 190)) | (1 << (SysVerilogHDLParser.Wor - 190)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Drive_strengthContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def drive_strength_value_0(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Drive_strength_value_0Context,0)


        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def drive_strength_value_1(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Drive_strength_value_1Context,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_drive_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDrive_strength" ):
                listener.enterDrive_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDrive_strength" ):
                listener.exitDrive_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDrive_strength" ):
                return visitor.visitDrive_strength(self)
            else:
                return visitor.visitChildren(self)




    def drive_strength(self):

        localctx = SysVerilogHDLParser.Drive_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 202, self.RULE_drive_strength)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1393
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 1394
            self.drive_strength_value_0()
            self.state = 1395
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1396
            self.drive_strength_value_1()
            self.state = 1397
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Drive_strength_value_0Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def strength0(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Strength0Context,0)


        def strength1(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Strength1Context,0)


        def highz0(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Highz0Context,0)


        def highz1(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Highz1Context,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_drive_strength_value_0

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDrive_strength_value_0" ):
                listener.enterDrive_strength_value_0(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDrive_strength_value_0" ):
                listener.exitDrive_strength_value_0(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDrive_strength_value_0" ):
                return visitor.visitDrive_strength_value_0(self)
            else:
                return visitor.visitChildren(self)




    def drive_strength_value_0(self):

        localctx = SysVerilogHDLParser.Drive_strength_value_0Context(self, self._ctx, self.state)
        self.enterRule(localctx, 204, self.RULE_drive_strength_value_0)
        try:
            self.state = 1403
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Pull0, SysVerilogHDLParser.Strong0, SysVerilogHDLParser.Supply0, SysVerilogHDLParser.Weak0]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1399
                self.strength0()
                pass
            elif token in [SysVerilogHDLParser.Pull1, SysVerilogHDLParser.Strong1, SysVerilogHDLParser.Supply1, SysVerilogHDLParser.Weak1]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1400
                self.strength1()
                pass
            elif token in [SysVerilogHDLParser.Highz0]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1401
                self.highz0()
                pass
            elif token in [SysVerilogHDLParser.Highz1]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1402
                self.highz1()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Drive_strength_value_1Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def strength0(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Strength0Context,0)


        def strength1(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Strength1Context,0)


        def highz0(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Highz0Context,0)


        def highz1(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Highz1Context,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_drive_strength_value_1

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDrive_strength_value_1" ):
                listener.enterDrive_strength_value_1(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDrive_strength_value_1" ):
                listener.exitDrive_strength_value_1(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDrive_strength_value_1" ):
                return visitor.visitDrive_strength_value_1(self)
            else:
                return visitor.visitChildren(self)




    def drive_strength_value_1(self):

        localctx = SysVerilogHDLParser.Drive_strength_value_1Context(self, self._ctx, self.state)
        self.enterRule(localctx, 206, self.RULE_drive_strength_value_1)
        try:
            self.state = 1409
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Pull0, SysVerilogHDLParser.Strong0, SysVerilogHDLParser.Supply0, SysVerilogHDLParser.Weak0]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1405
                self.strength0()
                pass
            elif token in [SysVerilogHDLParser.Pull1, SysVerilogHDLParser.Strong1, SysVerilogHDLParser.Supply1, SysVerilogHDLParser.Weak1]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1406
                self.strength1()
                pass
            elif token in [SysVerilogHDLParser.Highz0]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1407
                self.highz0()
                pass
            elif token in [SysVerilogHDLParser.Highz1]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1408
                self.highz1()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Strength0Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Supply0(self):
            return self.getToken(SysVerilogHDLParser.Supply0, 0)

        def Strong0(self):
            return self.getToken(SysVerilogHDLParser.Strong0, 0)

        def Pull0(self):
            return self.getToken(SysVerilogHDLParser.Pull0, 0)

        def Weak0(self):
            return self.getToken(SysVerilogHDLParser.Weak0, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_strength0

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrength0" ):
                listener.enterStrength0(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrength0" ):
                listener.exitStrength0(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrength0" ):
                return visitor.visitStrength0(self)
            else:
                return visitor.visitChildren(self)




    def strength0(self):

        localctx = SysVerilogHDLParser.Strength0Context(self, self._ctx, self.state)
        self.enterRule(localctx, 208, self.RULE_strength0)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1411
            _la = self._input.LA(1)
            if not(((((_la - 140)) & ~0x3f) == 0 and ((1 << (_la - 140)) & ((1 << (SysVerilogHDLParser.Pull0 - 140)) | (1 << (SysVerilogHDLParser.Strong0 - 140)) | (1 << (SysVerilogHDLParser.Supply0 - 140)) | (1 << (SysVerilogHDLParser.Weak0 - 140)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Strength1Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Supply1(self):
            return self.getToken(SysVerilogHDLParser.Supply1, 0)

        def Strong1(self):
            return self.getToken(SysVerilogHDLParser.Strong1, 0)

        def Pull1(self):
            return self.getToken(SysVerilogHDLParser.Pull1, 0)

        def Weak1(self):
            return self.getToken(SysVerilogHDLParser.Weak1, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_strength1

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStrength1" ):
                listener.enterStrength1(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStrength1" ):
                listener.exitStrength1(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStrength1" ):
                return visitor.visitStrength1(self)
            else:
                return visitor.visitChildren(self)




    def strength1(self):

        localctx = SysVerilogHDLParser.Strength1Context(self, self._ctx, self.state)
        self.enterRule(localctx, 210, self.RULE_strength1)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1413
            _la = self._input.LA(1)
            if not(((((_la - 141)) & ~0x3f) == 0 and ((1 << (_la - 141)) & ((1 << (SysVerilogHDLParser.Pull1 - 141)) | (1 << (SysVerilogHDLParser.Strong1 - 141)) | (1 << (SysVerilogHDLParser.Supply1 - 141)) | (1 << (SysVerilogHDLParser.Weak1 - 141)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Highz0Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Highz0(self):
            return self.getToken(SysVerilogHDLParser.Highz0, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_highz0

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHighz0" ):
                listener.enterHighz0(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHighz0" ):
                listener.exitHighz0(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHighz0" ):
                return visitor.visitHighz0(self)
            else:
                return visitor.visitChildren(self)




    def highz0(self):

        localctx = SysVerilogHDLParser.Highz0Context(self, self._ctx, self.state)
        self.enterRule(localctx, 212, self.RULE_highz0)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1415
            self.match(SysVerilogHDLParser.Highz0)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Highz1Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Highz1(self):
            return self.getToken(SysVerilogHDLParser.Highz1, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_highz1

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHighz1" ):
                listener.enterHighz1(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHighz1" ):
                listener.exitHighz1(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHighz1" ):
                return visitor.visitHighz1(self)
            else:
                return visitor.visitChildren(self)




    def highz1(self):

        localctx = SysVerilogHDLParser.Highz1Context(self, self._ctx, self.state)
        self.enterRule(localctx, 214, self.RULE_highz1)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1417
            self.match(SysVerilogHDLParser.Highz1)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Charge_strengthContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def charge_size(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Charge_sizeContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_charge_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCharge_strength" ):
                listener.enterCharge_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCharge_strength" ):
                listener.exitCharge_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCharge_strength" ):
                return visitor.visitCharge_strength(self)
            else:
                return visitor.visitChildren(self)




    def charge_strength(self):

        localctx = SysVerilogHDLParser.Charge_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 216, self.RULE_charge_strength)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1419
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 1420
            self.charge_size()
            self.state = 1421
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Charge_sizeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Small(self):
            return self.getToken(SysVerilogHDLParser.Small, 0)

        def Medium(self):
            return self.getToken(SysVerilogHDLParser.Medium, 0)

        def Large(self):
            return self.getToken(SysVerilogHDLParser.Large, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_charge_size

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCharge_size" ):
                listener.enterCharge_size(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCharge_size" ):
                listener.exitCharge_size(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCharge_size" ):
                return visitor.visitCharge_size(self)
            else:
                return visitor.visitChildren(self)




    def charge_size(self):

        localctx = SysVerilogHDLParser.Charge_sizeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 218, self.RULE_charge_size)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1423
            _la = self._input.LA(1)
            if not(((((_la - 114)) & ~0x3f) == 0 and ((1 << (_la - 114)) & ((1 << (SysVerilogHDLParser.Large - 114)) | (1 << (SysVerilogHDLParser.Medium - 114)) | (1 << (SysVerilogHDLParser.Small - 114)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_variable_descriptionsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_descriptionContext,0)


        def comma_variable_description_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_variable_description_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_variable_descriptions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_descriptions" ):
                listener.enterList_of_variable_descriptions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_descriptions" ):
                listener.exitList_of_variable_descriptions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_descriptions" ):
                return visitor.visitList_of_variable_descriptions(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_descriptions(self):

        localctx = SysVerilogHDLParser.List_of_variable_descriptionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 220, self.RULE_list_of_variable_descriptions)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1425
            self.variable_description()
            self.state = 1426
            self.comma_variable_description_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_variable_description_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_variable_description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_variable_descriptionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_variable_descriptionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_variable_description_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_variable_description_star" ):
                listener.enterComma_variable_description_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_variable_description_star" ):
                listener.exitComma_variable_description_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_variable_description_star" ):
                return visitor.visitComma_variable_description_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_variable_description_star(self):

        localctx = SysVerilogHDLParser.Comma_variable_description_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 222, self.RULE_comma_variable_description_star)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1431
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,61,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1428
                    self.comma_variable_description() 
                self.state = 1433
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,61,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_variable_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def variable_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_variable_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_variable_description" ):
                listener.enterComma_variable_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_variable_description" ):
                listener.exitComma_variable_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_variable_description" ):
                return visitor.visitComma_variable_description(self)
            else:
                return visitor.visitChildren(self)




    def comma_variable_description(self):

        localctx = SysVerilogHDLParser.Comma_variable_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 224, self.RULE_comma_variable_description)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1434
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1435
            self.variable_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_identifierContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def Equal(self):
            return self.getToken(SysVerilogHDLParser.Equal, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_description" ):
                listener.enterVariable_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_description" ):
                listener.exitVariable_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_description" ):
                return visitor.visitVariable_description(self)
            else:
                return visitor.visitChildren(self)




    def variable_description(self):

        localctx = SysVerilogHDLParser.Variable_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 226, self.RULE_variable_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1437
            self.variable_identifier()
            self.state = 1439
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1438
                self.dimension_plus()


            self.state = 1443
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Equal:
                self.state = 1441
                self.match(SysVerilogHDLParser.Equal)
                self.state = 1442
                self.expression()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_identifier" ):
                listener.enterVariable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_identifier" ):
                listener.exitVariable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_identifier" ):
                return visitor.visitVariable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def variable_identifier(self):

        localctx = SysVerilogHDLParser.Variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 228, self.RULE_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1445
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_hierarchical_variable_descriptionsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_variable_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_variable_descriptionContext,0)


        def comma_hierarchical_variable_description_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_hierarchical_variable_description_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_hierarchical_variable_descriptions

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_hierarchical_variable_descriptions" ):
                listener.enterList_of_hierarchical_variable_descriptions(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_hierarchical_variable_descriptions" ):
                listener.exitList_of_hierarchical_variable_descriptions(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_hierarchical_variable_descriptions" ):
                return visitor.visitList_of_hierarchical_variable_descriptions(self)
            else:
                return visitor.visitChildren(self)




    def list_of_hierarchical_variable_descriptions(self):

        localctx = SysVerilogHDLParser.List_of_hierarchical_variable_descriptionsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 230, self.RULE_list_of_hierarchical_variable_descriptions)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1447
            self.hierarchical_variable_description()
            self.state = 1448
            self.comma_hierarchical_variable_description_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_hierarchical_variable_description_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_hierarchical_variable_description(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_hierarchical_variable_descriptionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_hierarchical_variable_descriptionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_hierarchical_variable_description_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_hierarchical_variable_description_star" ):
                listener.enterComma_hierarchical_variable_description_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_hierarchical_variable_description_star" ):
                listener.exitComma_hierarchical_variable_description_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_hierarchical_variable_description_star" ):
                return visitor.visitComma_hierarchical_variable_description_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_hierarchical_variable_description_star(self):

        localctx = SysVerilogHDLParser.Comma_hierarchical_variable_description_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 232, self.RULE_comma_hierarchical_variable_description_star)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1453
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,64,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1450
                    self.comma_hierarchical_variable_description() 
                self.state = 1455
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,64,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_hierarchical_variable_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def hierarchical_variable_description(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_variable_descriptionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_hierarchical_variable_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_hierarchical_variable_description" ):
                listener.enterComma_hierarchical_variable_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_hierarchical_variable_description" ):
                listener.exitComma_hierarchical_variable_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_hierarchical_variable_description" ):
                return visitor.visitComma_hierarchical_variable_description(self)
            else:
                return visitor.visitChildren(self)




    def comma_hierarchical_variable_description(self):

        localctx = SysVerilogHDLParser.Comma_hierarchical_variable_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 234, self.RULE_comma_hierarchical_variable_description)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1456
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1457
            self.hierarchical_variable_description()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_variable_descriptionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_variable_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_variable_identifierContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def Equal(self):
            return self.getToken(SysVerilogHDLParser.Equal, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_variable_description

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_variable_description" ):
                listener.enterHierarchical_variable_description(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_variable_description" ):
                listener.exitHierarchical_variable_description(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_variable_description" ):
                return visitor.visitHierarchical_variable_description(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_variable_description(self):

        localctx = SysVerilogHDLParser.Hierarchical_variable_descriptionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 236, self.RULE_hierarchical_variable_description)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1459
            self.hierarchical_variable_identifier()
            self.state = 1461
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1460
                self.dimension_plus()


            self.state = 1465
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Equal:
                self.state = 1463
                self.match(SysVerilogHDLParser.Equal)
                self.state = 1464
                self.expression()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_variable_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_variable_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_variable_identifier" ):
                listener.enterHierarchical_variable_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_variable_identifier" ):
                listener.exitHierarchical_variable_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_variable_identifier" ):
                return visitor.visitHierarchical_variable_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_variable_identifier(self):

        localctx = SysVerilogHDLParser.Hierarchical_variable_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 238, self.RULE_hierarchical_variable_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1467
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Net_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def net_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_typeContext,0)


        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def user_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.User_typeContext,0)


        def drive_strength(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Drive_strengthContext,0)


        def charge_strength(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Charge_strengthContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def delay(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DelayContext,0)


        def Vectored(self):
            return self.getToken(SysVerilogHDLParser.Vectored, 0)

        def Scalared(self):
            return self.getToken(SysVerilogHDLParser.Scalared, 0)

        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_net_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNet_declaration" ):
                listener.enterNet_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNet_declaration" ):
                listener.exitNet_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNet_declaration" ):
                return visitor.visitNet_declaration(self)
            else:
                return visitor.visitChildren(self)




    def net_declaration(self):

        localctx = SysVerilogHDLParser.Net_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 240, self.RULE_net_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1469
            self.net_type()
            self.state = 1471
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,67,self._ctx)
            if la_ == 1:
                self.state = 1470
                self.user_type()


            self.state = 1474
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,68,self._ctx)
            if la_ == 1:
                self.state = 1473
                self.drive_strength()


            self.state = 1477
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Open_parenthesis:
                self.state = 1476
                self.charge_strength()


            self.state = 1480
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Scalared or _la==SysVerilogHDLParser.Vectored:
                self.state = 1479
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Scalared or _la==SysVerilogHDLParser.Vectored):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1483
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1482
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1486
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1485
                self.dimension_plus()


            self.state = 1489
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 1488
                self.delay()


            self.state = 1491
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Reg_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Reg(self):
            return self.getToken(SysVerilogHDLParser.Reg, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_reg_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReg_declaration" ):
                listener.enterReg_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReg_declaration" ):
                listener.exitReg_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReg_declaration" ):
                return visitor.visitReg_declaration(self)
            else:
                return visitor.visitChildren(self)




    def reg_declaration(self):

        localctx = SysVerilogHDLParser.Reg_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 242, self.RULE_reg_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1493
            self.match(SysVerilogHDLParser.Reg)
            self.state = 1495
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1494
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1498
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1497
                self.dimension_plus()


            self.state = 1500
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Logic_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Logic(self):
            return self.getToken(SysVerilogHDLParser.Logic, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_logic_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLogic_declaration" ):
                listener.enterLogic_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLogic_declaration" ):
                listener.exitLogic_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLogic_declaration" ):
                return visitor.visitLogic_declaration(self)
            else:
                return visitor.visitChildren(self)




    def logic_declaration(self):

        localctx = SysVerilogHDLParser.Logic_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 244, self.RULE_logic_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1502
            self.match(SysVerilogHDLParser.Logic)
            self.state = 1504
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1503
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1507
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1506
                self.dimension_plus()


            self.state = 1509
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bits_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Bit(self):
            return self.getToken(SysVerilogHDLParser.Bit, 0)

        def Byte(self):
            return self.getToken(SysVerilogHDLParser.Byte, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_bits_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBits_type" ):
                listener.enterBits_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBits_type" ):
                listener.exitBits_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBits_type" ):
                return visitor.visitBits_type(self)
            else:
                return visitor.visitChildren(self)




    def bits_type(self):

        localctx = SysVerilogHDLParser.Bits_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 246, self.RULE_bits_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1511
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Bit or _la==SysVerilogHDLParser.Byte):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Bits_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def bits_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_typeContext,0)


        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_bits_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBits_declaration" ):
                listener.enterBits_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBits_declaration" ):
                listener.exitBits_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBits_declaration" ):
                return visitor.visitBits_declaration(self)
            else:
                return visitor.visitChildren(self)




    def bits_declaration(self):

        localctx = SysVerilogHDLParser.Bits_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 248, self.RULE_bits_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1513
            self.bits_type()
            self.state = 1515
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1514
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1518
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1517
                self.dimension_plus()


            self.state = 1520
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Integer_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Integer(self):
            return self.getToken(SysVerilogHDLParser.Integer, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def Automatic(self):
            return self.getToken(SysVerilogHDLParser.Automatic, 0)

        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_integer_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInteger_declaration" ):
                listener.enterInteger_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInteger_declaration" ):
                listener.exitInteger_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInteger_declaration" ):
                return visitor.visitInteger_declaration(self)
            else:
                return visitor.visitChildren(self)




    def integer_declaration(self):

        localctx = SysVerilogHDLParser.Integer_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 250, self.RULE_integer_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1523
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Automatic:
                self.state = 1522
                self.match(SysVerilogHDLParser.Automatic)


            self.state = 1525
            self.match(SysVerilogHDLParser.Integer)
            self.state = 1527
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1526
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1529
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Int_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Int(self):
            return self.getToken(SysVerilogHDLParser.Int, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def Automatic(self):
            return self.getToken(SysVerilogHDLParser.Automatic, 0)

        def Static(self):
            return self.getToken(SysVerilogHDLParser.Static, 0)

        def Const(self):
            return self.getToken(SysVerilogHDLParser.Const, 0)

        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_int_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInt_declaration" ):
                listener.enterInt_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInt_declaration" ):
                listener.exitInt_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInt_declaration" ):
                return visitor.visitInt_declaration(self)
            else:
                return visitor.visitChildren(self)




    def int_declaration(self):

        localctx = SysVerilogHDLParser.Int_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 252, self.RULE_int_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1532
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Automatic or _la==SysVerilogHDLParser.Const or _la==SysVerilogHDLParser.Static:
                self.state = 1531
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Automatic or _la==SysVerilogHDLParser.Const or _la==SysVerilogHDLParser.Static):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1534
            self.match(SysVerilogHDLParser.Int)
            self.state = 1536
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1535
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1538
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Real_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Real(self):
            return self.getToken(SysVerilogHDLParser.Real, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_real_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_declaration" ):
                listener.enterReal_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_declaration" ):
                listener.exitReal_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_declaration" ):
                return visitor.visitReal_declaration(self)
            else:
                return visitor.visitChildren(self)




    def real_declaration(self):

        localctx = SysVerilogHDLParser.Real_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 254, self.RULE_real_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1540
            self.match(SysVerilogHDLParser.Real)
            self.state = 1541
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Time_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Time(self):
            return self.getToken(SysVerilogHDLParser.Time, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_time_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTime_declaration" ):
                listener.enterTime_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTime_declaration" ):
                listener.exitTime_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTime_declaration" ):
                return visitor.visitTime_declaration(self)
            else:
                return visitor.visitChildren(self)




    def time_declaration(self):

        localctx = SysVerilogHDLParser.Time_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 256, self.RULE_time_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1543
            self.match(SysVerilogHDLParser.Time)
            self.state = 1544
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Realtime_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Realtime(self):
            return self.getToken(SysVerilogHDLParser.Realtime, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_realtime_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRealtime_declaration" ):
                listener.enterRealtime_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRealtime_declaration" ):
                listener.exitRealtime_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRealtime_declaration" ):
                return visitor.visitRealtime_declaration(self)
            else:
                return visitor.visitChildren(self)




    def realtime_declaration(self):

        localctx = SysVerilogHDLParser.Realtime_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 258, self.RULE_realtime_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1546
            self.match(SysVerilogHDLParser.Realtime)
            self.state = 1547
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Event_keyword(self):
            return self.getToken(SysVerilogHDLParser.Event_keyword, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_declaration" ):
                listener.enterEvent_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_declaration" ):
                listener.exitEvent_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_declaration" ):
                return visitor.visitEvent_declaration(self)
            else:
                return visitor.visitChildren(self)




    def event_declaration(self):

        localctx = SysVerilogHDLParser.Event_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 260, self.RULE_event_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1549
            self.match(SysVerilogHDLParser.Event_keyword)
            self.state = 1550
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Genvar_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Genvar(self):
            return self.getToken(SysVerilogHDLParser.Genvar, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_genvar_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenvar_declaration" ):
                listener.enterGenvar_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenvar_declaration" ):
                listener.exitGenvar_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenvar_declaration" ):
                return visitor.visitGenvar_declaration(self)
            else:
                return visitor.visitChildren(self)




    def genvar_declaration(self):

        localctx = SysVerilogHDLParser.Genvar_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 262, self.RULE_genvar_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1552
            self.match(SysVerilogHDLParser.Genvar)
            self.state = 1553
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Usertype_variable_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def user_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.User_typeContext,0)


        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def Automatic(self):
            return self.getToken(SysVerilogHDLParser.Automatic, 0)

        def dimension(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DimensionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_usertype_variable_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUsertype_variable_declaration" ):
                listener.enterUsertype_variable_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUsertype_variable_declaration" ):
                listener.exitUsertype_variable_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUsertype_variable_declaration" ):
                return visitor.visitUsertype_variable_declaration(self)
            else:
                return visitor.visitChildren(self)




    def usertype_variable_declaration(self):

        localctx = SysVerilogHDLParser.Usertype_variable_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 264, self.RULE_usertype_variable_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1556
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Automatic:
                self.state = 1555
                self.match(SysVerilogHDLParser.Automatic)


            self.state = 1558
            self.user_type()
            self.state = 1560
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1559
                self.dimension()


            self.state = 1562
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class String_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def SVString(self):
            return self.getToken(SysVerilogHDLParser.SVString, 0)

        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_string_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterString_declaration" ):
                listener.enterString_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitString_declaration" ):
                listener.exitString_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitString_declaration" ):
                return visitor.visitString_declaration(self)
            else:
                return visitor.visitChildren(self)




    def string_declaration(self):

        localctx = SysVerilogHDLParser.String_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 266, self.RULE_string_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1564
            self.match(SysVerilogHDLParser.SVString)
            self.state = 1565
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Struct_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def struct_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Struct_typeContext,0)


        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_struct_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStruct_declaration" ):
                listener.enterStruct_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStruct_declaration" ):
                listener.exitStruct_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStruct_declaration" ):
                return visitor.visitStruct_declaration(self)
            else:
                return visitor.visitChildren(self)




    def struct_declaration(self):

        localctx = SysVerilogHDLParser.Struct_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 268, self.RULE_struct_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1567
            self.struct_type()
            self.state = 1568
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enum_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def enumerated_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enumerated_typeContext,0)


        def list_of_variable_descriptions(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_descriptionsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enum_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnum_declaration" ):
                listener.enterEnum_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnum_declaration" ):
                listener.exitEnum_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnum_declaration" ):
                return visitor.visitEnum_declaration(self)
            else:
                return visitor.visitChildren(self)




    def enum_declaration(self):

        localctx = SysVerilogHDLParser.Enum_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 270, self.RULE_enum_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1570
            self.enumerated_type()
            self.state = 1571
            self.list_of_variable_descriptions()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Function(self):
            return self.getToken(SysVerilogHDLParser.Function, 0)

        def function_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_identifierContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def function_item_declaration_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_item_declaration_starContext,0)


        def function_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_statementContext,0)


        def Endfunction(self):
            return self.getToken(SysVerilogHDLParser.Endfunction, 0)

        def Automatic(self):
            return self.getToken(SysVerilogHDLParser.Automatic, 0)

        def function_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_typeContext,0)


        def dimension(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DimensionContext,0)


        def function_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_interfaceContext,0)


        def colon_function_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Colon_function_identifierContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_declaration" ):
                listener.enterFunction_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_declaration" ):
                listener.exitFunction_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_declaration" ):
                return visitor.visitFunction_declaration(self)
            else:
                return visitor.visitChildren(self)




    def function_declaration(self):

        localctx = SysVerilogHDLParser.Function_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 272, self.RULE_function_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1573
            self.match(SysVerilogHDLParser.Function)
            self.state = 1575
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Automatic:
                self.state = 1574
                self.match(SysVerilogHDLParser.Automatic)


            self.state = 1578
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1577
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1581
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,88,self._ctx)
            if la_ == 1:
                self.state = 1580
                self.function_type()


            self.state = 1584
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1583
                self.dimension()


            self.state = 1586
            self.function_identifier()
            self.state = 1588
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Open_parenthesis:
                self.state = 1587
                self.function_interface()


            self.state = 1590
            self.semicolon()
            self.state = 1591
            self.function_item_declaration_star()
            self.state = 1592
            self.function_statement()
            self.state = 1593
            self.match(SysVerilogHDLParser.Endfunction)
            self.state = 1595
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 1594
                self.colon_function_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Logic(self):
            return self.getToken(SysVerilogHDLParser.Logic, 0)

        def Integer(self):
            return self.getToken(SysVerilogHDLParser.Integer, 0)

        def Int(self):
            return self.getToken(SysVerilogHDLParser.Int, 0)

        def Real(self):
            return self.getToken(SysVerilogHDLParser.Real, 0)

        def Realtime(self):
            return self.getToken(SysVerilogHDLParser.Realtime, 0)

        def Time(self):
            return self.getToken(SysVerilogHDLParser.Time, 0)

        def Reg(self):
            return self.getToken(SysVerilogHDLParser.Reg, 0)

        def SVString(self):
            return self.getToken(SysVerilogHDLParser.SVString, 0)

        def bits_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_typeContext,0)


        def user_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.User_typeContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_type" ):
                listener.enterFunction_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_type" ):
                listener.exitFunction_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_type" ):
                return visitor.visitFunction_type(self)
            else:
                return visitor.visitChildren(self)




    def function_type(self):

        localctx = SysVerilogHDLParser.Function_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 274, self.RULE_function_type)
        try:
            self.state = 1607
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Logic]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1597
                self.match(SysVerilogHDLParser.Logic)
                pass
            elif token in [SysVerilogHDLParser.Integer]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1598
                self.match(SysVerilogHDLParser.Integer)
                pass
            elif token in [SysVerilogHDLParser.Int]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1599
                self.match(SysVerilogHDLParser.Int)
                pass
            elif token in [SysVerilogHDLParser.Real]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1600
                self.match(SysVerilogHDLParser.Real)
                pass
            elif token in [SysVerilogHDLParser.Realtime]:
                self.enterOuterAlt(localctx, 5)
                self.state = 1601
                self.match(SysVerilogHDLParser.Realtime)
                pass
            elif token in [SysVerilogHDLParser.Time]:
                self.enterOuterAlt(localctx, 6)
                self.state = 1602
                self.match(SysVerilogHDLParser.Time)
                pass
            elif token in [SysVerilogHDLParser.Reg]:
                self.enterOuterAlt(localctx, 7)
                self.state = 1603
                self.match(SysVerilogHDLParser.Reg)
                pass
            elif token in [SysVerilogHDLParser.SVString]:
                self.enterOuterAlt(localctx, 8)
                self.state = 1604
                self.match(SysVerilogHDLParser.SVString)
                pass
            elif token in [SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte]:
                self.enterOuterAlt(localctx, 9)
                self.state = 1605
                self.bits_type()
                pass
            elif token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 10)
                self.state = 1606
                self.user_type()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_identifier" ):
                listener.enterFunction_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_identifier" ):
                listener.exitFunction_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_identifier" ):
                return visitor.visitFunction_identifier(self)
            else:
                return visitor.visitChildren(self)




    def function_identifier(self):

        localctx = SysVerilogHDLParser.Function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 276, self.RULE_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1609
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def list_of_tf_interface_ports(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_tf_interface_portsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_interface" ):
                listener.enterFunction_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_interface" ):
                listener.exitFunction_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_interface" ):
                return visitor.visitFunction_interface(self)
            else:
                return visitor.visitChildren(self)




    def function_interface(self):

        localctx = SysVerilogHDLParser.Function_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 278, self.RULE_function_interface)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1611
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 1613
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 55)) & ~0x3f) == 0 and ((1 << (_la - 55)) & ((1 << (SysVerilogHDLParser.Automatic - 55)) | (1 << (SysVerilogHDLParser.Bit - 55)) | (1 << (SysVerilogHDLParser.Byte - 55)) | (1 << (SysVerilogHDLParser.Const - 55)) | (1 << (SysVerilogHDLParser.Inout - 55)) | (1 << (SysVerilogHDLParser.Input - 55)) | (1 << (SysVerilogHDLParser.Int - 55)) | (1 << (SysVerilogHDLParser.Integer - 55)) | (1 << (SysVerilogHDLParser.Logic - 55)))) != 0) or ((((_la - 125)) & ~0x3f) == 0 and ((1 << (_la - 125)) & ((1 << (SysVerilogHDLParser.NONE - 125)) | (1 << (SysVerilogHDLParser.Output - 125)) | (1 << (SysVerilogHDLParser.Real - 125)) | (1 << (SysVerilogHDLParser.Ref - 125)) | (1 << (SysVerilogHDLParser.Reg - 125)) | (1 << (SysVerilogHDLParser.Signed - 125)) | (1 << (SysVerilogHDLParser.Static - 125)) | (1 << (SysVerilogHDLParser.SVString - 125)) | (1 << (SysVerilogHDLParser.Supply0 - 125)) | (1 << (SysVerilogHDLParser.Supply1 - 125)) | (1 << (SysVerilogHDLParser.Time - 125)) | (1 << (SysVerilogHDLParser.Tri - 125)) | (1 << (SysVerilogHDLParser.Tri_and - 125)) | (1 << (SysVerilogHDLParser.Tri_or - 125)) | (1 << (SysVerilogHDLParser.Tri_reg - 125)) | (1 << (SysVerilogHDLParser.Tri0 - 125)) | (1 << (SysVerilogHDLParser.Tri1 - 125)) | (1 << (SysVerilogHDLParser.Unsigned - 125)))) != 0) or ((((_la - 190)) & ~0x3f) == 0 and ((1 << (_la - 190)) & ((1 << (SysVerilogHDLParser.Uwire - 190)) | (1 << (SysVerilogHDLParser.Wand - 190)) | (1 << (SysVerilogHDLParser.Wire - 190)) | (1 << (SysVerilogHDLParser.Wor - 190)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 190)) | (1 << (SysVerilogHDLParser.Simple_identifier - 190)) | (1 << (SysVerilogHDLParser.Left_bracket - 190)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 190)))) != 0):
                self.state = 1612
                self.list_of_tf_interface_ports()


            self.state = 1615
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_item_declaration_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_item_declaration_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Function_item_declaration_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Function_item_declaration_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_item_declaration_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_item_declaration_star" ):
                listener.enterFunction_item_declaration_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_item_declaration_star" ):
                listener.exitFunction_item_declaration_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_item_declaration_star" ):
                return visitor.visitFunction_item_declaration_star(self)
            else:
                return visitor.visitChildren(self)




    def function_item_declaration_star(self):

        localctx = SysVerilogHDLParser.Function_item_declaration_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 280, self.RULE_function_item_declaration_star)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1620
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,94,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1617
                    self.function_item_declaration_semicolon() 
                self.state = 1622
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,94,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_item_declaration_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_item_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_item_declarationContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_item_declaration_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_item_declaration_semicolon" ):
                listener.enterFunction_item_declaration_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_item_declaration_semicolon" ):
                listener.exitFunction_item_declaration_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_item_declaration_semicolon" ):
                return visitor.visitFunction_item_declaration_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def function_item_declaration_semicolon(self):

        localctx = SysVerilogHDLParser.Function_item_declaration_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 282, self.RULE_function_item_declaration_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1623
            self.function_item_declaration()
            self.state = 1624
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_item_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_item_declarationContext,0)


        def port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_item_declaration" ):
                listener.enterFunction_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_item_declaration" ):
                listener.exitFunction_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_item_declaration" ):
                return visitor.visitFunction_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def function_item_declaration(self):

        localctx = SysVerilogHDLParser.Function_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 284, self.RULE_function_item_declaration)
        try:
            self.state = 1628
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Automatic, SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte, SysVerilogHDLParser.Const, SysVerilogHDLParser.Event_keyword, SysVerilogHDLParser.Int, SysVerilogHDLParser.Integer, SysVerilogHDLParser.Localparam, SysVerilogHDLParser.Logic, SysVerilogHDLParser.Parameter, SysVerilogHDLParser.Real, SysVerilogHDLParser.Realtime, SysVerilogHDLParser.Reg, SysVerilogHDLParser.Static, SysVerilogHDLParser.SVString, SysVerilogHDLParser.Time, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1626
                self.block_item_declaration()
                pass
            elif token in [SysVerilogHDLParser.Inout, SysVerilogHDLParser.Input, SysVerilogHDLParser.Output, SysVerilogHDLParser.Ref]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1627
                self.port_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_statement" ):
                listener.enterFunction_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_statement" ):
                listener.exitFunction_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_statement" ):
                return visitor.visitFunction_statement(self)
            else:
                return visitor.visitChildren(self)




    def function_statement(self):

        localctx = SysVerilogHDLParser.Function_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 286, self.RULE_function_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1630
            self.statement_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Colon_function_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def function_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_colon_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterColon_function_identifier" ):
                listener.enterColon_function_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitColon_function_identifier" ):
                listener.exitColon_function_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitColon_function_identifier" ):
                return visitor.visitColon_function_identifier(self)
            else:
                return visitor.visitChildren(self)




    def colon_function_identifier(self):

        localctx = SysVerilogHDLParser.Colon_function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 288, self.RULE_colon_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1632
            self.match(SysVerilogHDLParser.Colon)
            self.state = 1633
            self.function_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Task(self):
            return self.getToken(SysVerilogHDLParser.Task, 0)

        def task_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_identifierContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def task_item_declaration_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_item_declaration_starContext,0)


        def task_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_statementContext,0)


        def Endtask(self):
            return self.getToken(SysVerilogHDLParser.Endtask, 0)

        def Automatic(self):
            return self.getToken(SysVerilogHDLParser.Automatic, 0)

        def task_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_interfaceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_declaration" ):
                listener.enterTask_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_declaration" ):
                listener.exitTask_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_declaration" ):
                return visitor.visitTask_declaration(self)
            else:
                return visitor.visitChildren(self)




    def task_declaration(self):

        localctx = SysVerilogHDLParser.Task_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 290, self.RULE_task_declaration)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1635
            self.match(SysVerilogHDLParser.Task)
            self.state = 1637
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Automatic:
                self.state = 1636
                self.match(SysVerilogHDLParser.Automatic)


            self.state = 1639
            self.task_identifier()
            self.state = 1641
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Open_parenthesis:
                self.state = 1640
                self.task_interface()


            self.state = 1643
            self.semicolon()
            self.state = 1644
            self.task_item_declaration_star()
            self.state = 1645
            self.task_statement()
            self.state = 1646
            self.match(SysVerilogHDLParser.Endtask)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_identifier" ):
                listener.enterTask_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_identifier" ):
                listener.exitTask_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_identifier" ):
                return visitor.visitTask_identifier(self)
            else:
                return visitor.visitChildren(self)




    def task_identifier(self):

        localctx = SysVerilogHDLParser.Task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 292, self.RULE_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1648
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def list_of_tf_interface_ports(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_tf_interface_portsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_interface" ):
                listener.enterTask_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_interface" ):
                listener.exitTask_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_interface" ):
                return visitor.visitTask_interface(self)
            else:
                return visitor.visitChildren(self)




    def task_interface(self):

        localctx = SysVerilogHDLParser.Task_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 294, self.RULE_task_interface)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1650
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 1652
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 55)) & ~0x3f) == 0 and ((1 << (_la - 55)) & ((1 << (SysVerilogHDLParser.Automatic - 55)) | (1 << (SysVerilogHDLParser.Bit - 55)) | (1 << (SysVerilogHDLParser.Byte - 55)) | (1 << (SysVerilogHDLParser.Const - 55)) | (1 << (SysVerilogHDLParser.Inout - 55)) | (1 << (SysVerilogHDLParser.Input - 55)) | (1 << (SysVerilogHDLParser.Int - 55)) | (1 << (SysVerilogHDLParser.Integer - 55)) | (1 << (SysVerilogHDLParser.Logic - 55)))) != 0) or ((((_la - 125)) & ~0x3f) == 0 and ((1 << (_la - 125)) & ((1 << (SysVerilogHDLParser.NONE - 125)) | (1 << (SysVerilogHDLParser.Output - 125)) | (1 << (SysVerilogHDLParser.Real - 125)) | (1 << (SysVerilogHDLParser.Ref - 125)) | (1 << (SysVerilogHDLParser.Reg - 125)) | (1 << (SysVerilogHDLParser.Signed - 125)) | (1 << (SysVerilogHDLParser.Static - 125)) | (1 << (SysVerilogHDLParser.SVString - 125)) | (1 << (SysVerilogHDLParser.Supply0 - 125)) | (1 << (SysVerilogHDLParser.Supply1 - 125)) | (1 << (SysVerilogHDLParser.Time - 125)) | (1 << (SysVerilogHDLParser.Tri - 125)) | (1 << (SysVerilogHDLParser.Tri_and - 125)) | (1 << (SysVerilogHDLParser.Tri_or - 125)) | (1 << (SysVerilogHDLParser.Tri_reg - 125)) | (1 << (SysVerilogHDLParser.Tri0 - 125)) | (1 << (SysVerilogHDLParser.Tri1 - 125)) | (1 << (SysVerilogHDLParser.Unsigned - 125)))) != 0) or ((((_la - 190)) & ~0x3f) == 0 and ((1 << (_la - 190)) & ((1 << (SysVerilogHDLParser.Uwire - 190)) | (1 << (SysVerilogHDLParser.Wand - 190)) | (1 << (SysVerilogHDLParser.Wire - 190)) | (1 << (SysVerilogHDLParser.Wor - 190)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 190)) | (1 << (SysVerilogHDLParser.Simple_identifier - 190)) | (1 << (SysVerilogHDLParser.Left_bracket - 190)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 190)))) != 0):
                self.state = 1651
                self.list_of_tf_interface_ports()


            self.state = 1654
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_item_declaration_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_item_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_item_declarationContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_item_declaration_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_item_declaration_semicolon" ):
                listener.enterTask_item_declaration_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_item_declaration_semicolon" ):
                listener.exitTask_item_declaration_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_item_declaration_semicolon" ):
                return visitor.visitTask_item_declaration_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def task_item_declaration_semicolon(self):

        localctx = SysVerilogHDLParser.Task_item_declaration_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 296, self.RULE_task_item_declaration_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1656
            self.task_item_declaration()
            self.state = 1657
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_item_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_item_declarationContext,0)


        def port_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_item_declaration" ):
                listener.enterTask_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_item_declaration" ):
                listener.exitTask_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_item_declaration" ):
                return visitor.visitTask_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def task_item_declaration(self):

        localctx = SysVerilogHDLParser.Task_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 298, self.RULE_task_item_declaration)
        try:
            self.state = 1661
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Automatic, SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte, SysVerilogHDLParser.Const, SysVerilogHDLParser.Event_keyword, SysVerilogHDLParser.Int, SysVerilogHDLParser.Integer, SysVerilogHDLParser.Localparam, SysVerilogHDLParser.Logic, SysVerilogHDLParser.Parameter, SysVerilogHDLParser.Real, SysVerilogHDLParser.Realtime, SysVerilogHDLParser.Reg, SysVerilogHDLParser.Static, SysVerilogHDLParser.SVString, SysVerilogHDLParser.Time, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1659
                self.block_item_declaration()
                pass
            elif token in [SysVerilogHDLParser.Inout, SysVerilogHDLParser.Input, SysVerilogHDLParser.Output, SysVerilogHDLParser.Ref]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1660
                self.port_declaration()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_item_declaration_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_item_declaration_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Task_item_declaration_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Task_item_declaration_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_item_declaration_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_item_declaration_star" ):
                listener.enterTask_item_declaration_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_item_declaration_star" ):
                listener.exitTask_item_declaration_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_item_declaration_star" ):
                return visitor.visitTask_item_declaration_star(self)
            else:
                return visitor.visitChildren(self)




    def task_item_declaration_star(self):

        localctx = SysVerilogHDLParser.Task_item_declaration_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 300, self.RULE_task_item_declaration_star)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1666
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,100,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 1663
                    self.task_item_declaration_semicolon() 
                self.state = 1668
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,100,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_statement" ):
                listener.enterTask_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_statement" ):
                listener.exitTask_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_statement" ):
                return visitor.visitTask_statement(self)
            else:
                return visitor.visitChildren(self)




    def task_statement(self):

        localctx = SysVerilogHDLParser.Task_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 302, self.RULE_task_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1669
            self.statement_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Struct_item_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def struct_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Struct_itemContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_struct_item_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStruct_item_semicolon" ):
                listener.enterStruct_item_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStruct_item_semicolon" ):
                listener.exitStruct_item_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStruct_item_semicolon" ):
                return visitor.visitStruct_item_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def struct_item_semicolon(self):

        localctx = SysVerilogHDLParser.Struct_item_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 304, self.RULE_struct_item_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1671
            self.struct_item()
            self.state = 1672
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Struct_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def struct_item_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Struct_item_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Struct_item_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_struct_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStruct_item_star" ):
                listener.enterStruct_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStruct_item_star" ):
                listener.exitStruct_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStruct_item_star" ):
                return visitor.visitStruct_item_star(self)
            else:
                return visitor.visitChildren(self)




    def struct_item_star(self):

        localctx = SysVerilogHDLParser.Struct_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 306, self.RULE_struct_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1677
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while ((((_la - 55)) & ~0x3f) == 0 and ((1 << (_la - 55)) & ((1 << (SysVerilogHDLParser.Automatic - 55)) | (1 << (SysVerilogHDLParser.Bit - 55)) | (1 << (SysVerilogHDLParser.Byte - 55)) | (1 << (SysVerilogHDLParser.Const - 55)) | (1 << (SysVerilogHDLParser.Int - 55)) | (1 << (SysVerilogHDLParser.Integer - 55)) | (1 << (SysVerilogHDLParser.Logic - 55)))) != 0) or ((((_la - 165)) & ~0x3f) == 0 and ((1 << (_la - 165)) & ((1 << (SysVerilogHDLParser.Static - 165)) | (1 << (SysVerilogHDLParser.Time - 165)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 165)) | (1 << (SysVerilogHDLParser.Simple_identifier - 165)))) != 0):
                self.state = 1674
                self.struct_item_semicolon()
                self.state = 1679
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Struct_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def bits_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_declarationContext,0)


        def int_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Int_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def usertype_variable_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Usertype_variable_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Time_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_struct_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStruct_item" ):
                listener.enterStruct_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStruct_item" ):
                listener.exitStruct_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStruct_item" ):
                return visitor.visitStruct_item(self)
            else:
                return visitor.visitChildren(self)




    def struct_item(self):

        localctx = SysVerilogHDLParser.Struct_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 308, self.RULE_struct_item)
        try:
            self.state = 1686
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,102,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1680
                self.logic_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1681
                self.bits_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1682
                self.int_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 1683
                self.integer_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 1684
                self.usertype_variable_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 1685
                self.time_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Struct_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def struct_keyword(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Struct_keywordContext,0)


        def Left_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Left_curly_bracket, 0)

        def struct_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Struct_item_starContext,0)


        def Right_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Right_curly_bracket, 0)

        def Packed(self):
            return self.getToken(SysVerilogHDLParser.Packed, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_struct_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStruct_type" ):
                listener.enterStruct_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStruct_type" ):
                listener.exitStruct_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStruct_type" ):
                return visitor.visitStruct_type(self)
            else:
                return visitor.visitChildren(self)




    def struct_type(self):

        localctx = SysVerilogHDLParser.Struct_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 310, self.RULE_struct_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1688
            self.struct_keyword()
            self.state = 1690
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Packed:
                self.state = 1689
                self.match(SysVerilogHDLParser.Packed)


            self.state = 1692
            self.match(SysVerilogHDLParser.Left_curly_bracket)
            self.state = 1693
            self.struct_item_star()
            self.state = 1694
            self.match(SysVerilogHDLParser.Right_curly_bracket)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enum_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Integer(self):
            return self.getToken(SysVerilogHDLParser.Integer, 0)

        def Logic(self):
            return self.getToken(SysVerilogHDLParser.Logic, 0)

        def bits_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_typeContext,0)


        def Int(self):
            return self.getToken(SysVerilogHDLParser.Int, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enum_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnum_type" ):
                listener.enterEnum_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnum_type" ):
                listener.exitEnum_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnum_type" ):
                return visitor.visitEnum_type(self)
            else:
                return visitor.visitChildren(self)




    def enum_type(self):

        localctx = SysVerilogHDLParser.Enum_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 312, self.RULE_enum_type)
        try:
            self.state = 1700
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Integer]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1696
                self.match(SysVerilogHDLParser.Integer)
                pass
            elif token in [SysVerilogHDLParser.Logic]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1697
                self.match(SysVerilogHDLParser.Logic)
                pass
            elif token in [SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1698
                self.bits_type()
                pass
            elif token in [SysVerilogHDLParser.Int]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1699
                self.match(SysVerilogHDLParser.Int)
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_enum_itemsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def enum_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enum_itemContext,0)


        def comma_enum_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_enum_item_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_enum_items

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_enum_items" ):
                listener.enterList_of_enum_items(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_enum_items" ):
                listener.exitList_of_enum_items(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_enum_items" ):
                return visitor.visitList_of_enum_items(self)
            else:
                return visitor.visitChildren(self)




    def list_of_enum_items(self):

        localctx = SysVerilogHDLParser.List_of_enum_itemsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 314, self.RULE_list_of_enum_items)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1702
            self.enum_item()
            self.state = 1703
            self.comma_enum_item_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enum_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def enum_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enum_identifierContext,0)


        def Equal(self):
            return self.getToken(SysVerilogHDLParser.Equal, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enum_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnum_item" ):
                listener.enterEnum_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnum_item" ):
                listener.exitEnum_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnum_item" ):
                return visitor.visitEnum_item(self)
            else:
                return visitor.visitChildren(self)




    def enum_item(self):

        localctx = SysVerilogHDLParser.Enum_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 316, self.RULE_enum_item)
        try:
            self.state = 1710
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,105,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1705
                self.enum_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1706
                self.enum_identifier()
                self.state = 1707
                self.match(SysVerilogHDLParser.Equal)
                self.state = 1708
                self.expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enum_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enum_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnum_identifier" ):
                listener.enterEnum_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnum_identifier" ):
                listener.exitEnum_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnum_identifier" ):
                return visitor.visitEnum_identifier(self)
            else:
                return visitor.visitChildren(self)




    def enum_identifier(self):

        localctx = SysVerilogHDLParser.Enum_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 318, self.RULE_enum_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1712
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_enum_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_enum_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_enum_itemContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_enum_itemContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_enum_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_enum_item_star" ):
                listener.enterComma_enum_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_enum_item_star" ):
                listener.exitComma_enum_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_enum_item_star" ):
                return visitor.visitComma_enum_item_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_enum_item_star(self):

        localctx = SysVerilogHDLParser.Comma_enum_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 320, self.RULE_comma_enum_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1717
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 1714
                self.comma_enum_item()
                self.state = 1719
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_enum_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def enum_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enum_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_enum_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_enum_item" ):
                listener.enterComma_enum_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_enum_item" ):
                listener.exitComma_enum_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_enum_item" ):
                return visitor.visitComma_enum_item(self)
            else:
                return visitor.visitChildren(self)




    def comma_enum_item(self):

        localctx = SysVerilogHDLParser.Comma_enum_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 322, self.RULE_comma_enum_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1720
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1721
            self.enum_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enumerated_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Enum(self):
            return self.getToken(SysVerilogHDLParser.Enum, 0)

        def Left_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Left_curly_bracket, 0)

        def list_of_enum_items(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_enum_itemsContext,0)


        def Right_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Right_curly_bracket, 0)

        def enum_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enum_typeContext,0)


        def dimension(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DimensionContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enumerated_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnumerated_type" ):
                listener.enterEnumerated_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnumerated_type" ):
                listener.exitEnumerated_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnumerated_type" ):
                return visitor.visitEnumerated_type(self)
            else:
                return visitor.visitChildren(self)




    def enumerated_type(self):

        localctx = SysVerilogHDLParser.Enumerated_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 324, self.RULE_enumerated_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1723
            self.match(SysVerilogHDLParser.Enum)
            self.state = 1725
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if ((((_la - 57)) & ~0x3f) == 0 and ((1 << (_la - 57)) & ((1 << (SysVerilogHDLParser.Bit - 57)) | (1 << (SysVerilogHDLParser.Byte - 57)) | (1 << (SysVerilogHDLParser.Int - 57)) | (1 << (SysVerilogHDLParser.Integer - 57)) | (1 << (SysVerilogHDLParser.Logic - 57)))) != 0):
                self.state = 1724
                self.enum_type()


            self.state = 1728
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 1727
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 1731
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1730
                self.dimension()


            self.state = 1733
            self.match(SysVerilogHDLParser.Left_curly_bracket)
            self.state = 1734
            self.list_of_enum_items()
            self.state = 1735
            self.match(SysVerilogHDLParser.Right_curly_bracket)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_identifierContext,0)


        def list_of_module_instances(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_module_instancesContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def parameter_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instantiation" ):
                listener.enterModule_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instantiation" ):
                listener.exitModule_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instantiation" ):
                return visitor.visitModule_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def module_instantiation(self):

        localctx = SysVerilogHDLParser.Module_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 326, self.RULE_module_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1737
            self.module_identifier()
            self.state = 1739
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 1738
                self.parameter_interface_assignments()


            self.state = 1741
            self.list_of_module_instances()
            self.state = 1742
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parameter_interface_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Hash(self):
            return self.getToken(SysVerilogHDLParser.Hash, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def list_of_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_parameter_interface_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParameter_interface_assignments" ):
                listener.enterParameter_interface_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParameter_interface_assignments" ):
                listener.exitParameter_interface_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParameter_interface_assignments" ):
                return visitor.visitParameter_interface_assignments(self)
            else:
                return visitor.visitChildren(self)




    def parameter_interface_assignments(self):

        localctx = SysVerilogHDLParser.Parameter_interface_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 328, self.RULE_parameter_interface_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1744
            self.match(SysVerilogHDLParser.Hash)
            self.state = 1745
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 1747
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form))) != 0) or _la==SysVerilogHDLParser.Int or _la==SysVerilogHDLParser.Signed or ((((_la - 188)) & ~0x3f) == 0 and ((1 << (_la - 188)) & ((1 << (SysVerilogHDLParser.Unsigned - 188)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 188)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 188)) | (1 << (SysVerilogHDLParser.Simple_identifier - 188)) | (1 << (SysVerilogHDLParser.String_literal - 188)) | (1 << (SysVerilogHDLParser.Dot - 188)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 188)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 188)) | (1 << (SysVerilogHDLParser.Quote - 188)) | (1 << (SysVerilogHDLParser.Tilde - 188)))) != 0):
                self.state = 1746
                self.list_of_interface_assignments()


            self.state = 1749
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_interface_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_ordered_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_ordered_interface_assignmentsContext,0)


        def list_of_named_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_named_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_interface_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_interface_assignments" ):
                listener.enterList_of_interface_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_interface_assignments" ):
                listener.exitList_of_interface_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_interface_assignments" ):
                return visitor.visitList_of_interface_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_interface_assignments(self):

        localctx = SysVerilogHDLParser.List_of_interface_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 330, self.RULE_list_of_interface_assignments)
        try:
            self.state = 1753
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.T__1, SysVerilogHDLParser.T__2, SysVerilogHDLParser.T__3, SysVerilogHDLParser.T__4, SysVerilogHDLParser.T__5, SysVerilogHDLParser.T__6, SysVerilogHDLParser.T__7, SysVerilogHDLParser.T__8, SysVerilogHDLParser.T__9, SysVerilogHDLParser.T__10, SysVerilogHDLParser.T__26, SysVerilogHDLParser.T__27, SysVerilogHDLParser.Binary_number, SysVerilogHDLParser.Decimal_number, SysVerilogHDLParser.Fixed_point_number, SysVerilogHDLParser.Hex_number, SysVerilogHDLParser.Octal_number, SysVerilogHDLParser.Real_exp_form, SysVerilogHDLParser.Int, SysVerilogHDLParser.Signed, SysVerilogHDLParser.Unsigned, SysVerilogHDLParser.Dollar_Identifier, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier, SysVerilogHDLParser.String_literal, SysVerilogHDLParser.Left_curly_bracket, SysVerilogHDLParser.Open_parenthesis, SysVerilogHDLParser.Quote, SysVerilogHDLParser.Tilde]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1751
                self.list_of_ordered_interface_assignments()
                pass
            elif token in [SysVerilogHDLParser.Dot]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1752
                self.list_of_named_interface_assignments()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_ordered_interface_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def ordered_interface_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Ordered_interface_assignmentContext,0)


        def comma_ordered_interface_assignment_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_ordered_interface_assignment_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_ordered_interface_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_ordered_interface_assignments" ):
                listener.enterList_of_ordered_interface_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_ordered_interface_assignments" ):
                listener.exitList_of_ordered_interface_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_ordered_interface_assignments" ):
                return visitor.visitList_of_ordered_interface_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_ordered_interface_assignments(self):

        localctx = SysVerilogHDLParser.List_of_ordered_interface_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 332, self.RULE_list_of_ordered_interface_assignments)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1755
            self.ordered_interface_assignment()
            self.state = 1756
            self.comma_ordered_interface_assignment_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_ordered_interface_assignment_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_ordered_interface_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_ordered_interface_assignmentContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_ordered_interface_assignmentContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_ordered_interface_assignment_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_ordered_interface_assignment_star" ):
                listener.enterComma_ordered_interface_assignment_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_ordered_interface_assignment_star" ):
                listener.exitComma_ordered_interface_assignment_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_ordered_interface_assignment_star" ):
                return visitor.visitComma_ordered_interface_assignment_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_ordered_interface_assignment_star(self):

        localctx = SysVerilogHDLParser.Comma_ordered_interface_assignment_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 334, self.RULE_comma_ordered_interface_assignment_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1761
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 1758
                self.comma_ordered_interface_assignment()
                self.state = 1763
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_ordered_interface_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def ordered_interface_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Ordered_interface_assignmentContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_ordered_interface_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_ordered_interface_assignment" ):
                listener.enterComma_ordered_interface_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_ordered_interface_assignment" ):
                listener.exitComma_ordered_interface_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_ordered_interface_assignment" ):
                return visitor.visitComma_ordered_interface_assignment(self)
            else:
                return visitor.visitChildren(self)




    def comma_ordered_interface_assignment(self):

        localctx = SysVerilogHDLParser.Comma_ordered_interface_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 336, self.RULE_comma_ordered_interface_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1764
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1766
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form))) != 0) or _la==SysVerilogHDLParser.Int or _la==SysVerilogHDLParser.Signed or ((((_la - 188)) & ~0x3f) == 0 and ((1 << (_la - 188)) & ((1 << (SysVerilogHDLParser.Unsigned - 188)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 188)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 188)) | (1 << (SysVerilogHDLParser.Simple_identifier - 188)) | (1 << (SysVerilogHDLParser.String_literal - 188)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 188)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 188)) | (1 << (SysVerilogHDLParser.Quote - 188)) | (1 << (SysVerilogHDLParser.Tilde - 188)))) != 0):
                self.state = 1765
                self.ordered_interface_assignment()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ordered_interface_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_ordered_interface_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOrdered_interface_assignment" ):
                listener.enterOrdered_interface_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOrdered_interface_assignment" ):
                listener.exitOrdered_interface_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOrdered_interface_assignment" ):
                return visitor.visitOrdered_interface_assignment(self)
            else:
                return visitor.visitChildren(self)




    def ordered_interface_assignment(self):

        localctx = SysVerilogHDLParser.Ordered_interface_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 338, self.RULE_ordered_interface_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1768
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_named_interface_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def named_interface_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Named_interface_assignmentContext,0)


        def comma_named_interface_assignment_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_named_interface_assignment_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_named_interface_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_named_interface_assignments" ):
                listener.enterList_of_named_interface_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_named_interface_assignments" ):
                listener.exitList_of_named_interface_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_named_interface_assignments" ):
                return visitor.visitList_of_named_interface_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_named_interface_assignments(self):

        localctx = SysVerilogHDLParser.List_of_named_interface_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 340, self.RULE_list_of_named_interface_assignments)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1770
            self.named_interface_assignment()
            self.state = 1771
            self.comma_named_interface_assignment_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_named_interface_assignment_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_named_interface_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_named_interface_assignmentContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_named_interface_assignmentContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_named_interface_assignment_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_named_interface_assignment_star" ):
                listener.enterComma_named_interface_assignment_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_named_interface_assignment_star" ):
                listener.exitComma_named_interface_assignment_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_named_interface_assignment_star" ):
                return visitor.visitComma_named_interface_assignment_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_named_interface_assignment_star(self):

        localctx = SysVerilogHDLParser.Comma_named_interface_assignment_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 342, self.RULE_comma_named_interface_assignment_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1776
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 1773
                self.comma_named_interface_assignment()
                self.state = 1778
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_named_interface_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def named_interface_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Named_interface_assignmentContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_named_interface_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_named_interface_assignment" ):
                listener.enterComma_named_interface_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_named_interface_assignment" ):
                listener.exitComma_named_interface_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_named_interface_assignment" ):
                return visitor.visitComma_named_interface_assignment(self)
            else:
                return visitor.visitChildren(self)




    def comma_named_interface_assignment(self):

        localctx = SysVerilogHDLParser.Comma_named_interface_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 344, self.RULE_comma_named_interface_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1779
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1780
            self.named_interface_assignment()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Named_interface_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Dot(self):
            return self.getToken(SysVerilogHDLParser.Dot, 0)

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def Star(self):
            return self.getToken(SysVerilogHDLParser.Star, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_named_interface_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNamed_interface_assignment" ):
                listener.enterNamed_interface_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNamed_interface_assignment" ):
                listener.exitNamed_interface_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNamed_interface_assignment" ):
                return visitor.visitNamed_interface_assignment(self)
            else:
                return visitor.visitChildren(self)




    def named_interface_assignment(self):

        localctx = SysVerilogHDLParser.Named_interface_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 346, self.RULE_named_interface_assignment)
        self._la = 0 # Token type
        try:
            self.state = 1793
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,118,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1782
                self.match(SysVerilogHDLParser.Dot)
                self.state = 1783
                self.identifier()
                self.state = 1789
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SysVerilogHDLParser.Open_parenthesis:
                    self.state = 1784
                    self.match(SysVerilogHDLParser.Open_parenthesis)
                    self.state = 1786
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)
                    if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form))) != 0) or _la==SysVerilogHDLParser.Int or _la==SysVerilogHDLParser.Signed or ((((_la - 188)) & ~0x3f) == 0 and ((1 << (_la - 188)) & ((1 << (SysVerilogHDLParser.Unsigned - 188)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 188)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 188)) | (1 << (SysVerilogHDLParser.Simple_identifier - 188)) | (1 << (SysVerilogHDLParser.String_literal - 188)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 188)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 188)) | (1 << (SysVerilogHDLParser.Quote - 188)) | (1 << (SysVerilogHDLParser.Tilde - 188)))) != 0):
                        self.state = 1785
                        self.expression()


                    self.state = 1788
                    self.match(SysVerilogHDLParser.Close_parenthesis)


                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1791
                self.match(SysVerilogHDLParser.Dot)
                self.state = 1792
                self.match(SysVerilogHDLParser.Star)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_module_instancesContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_instanceContext,0)


        def comma_module_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_module_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_module_instances

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_module_instances" ):
                listener.enterList_of_module_instances(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_module_instances" ):
                listener.exitList_of_module_instances(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_module_instances" ):
                return visitor.visitList_of_module_instances(self)
            else:
                return visitor.visitChildren(self)




    def list_of_module_instances(self):

        localctx = SysVerilogHDLParser.List_of_module_instancesContext(self, self._ctx, self.state)
        self.enterRule(localctx, 348, self.RULE_list_of_module_instances)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1795
            self.module_instance()
            self.state = 1796
            self.comma_module_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_module_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_module_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_module_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_module_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_module_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_module_instance_star" ):
                listener.enterComma_module_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_module_instance_star" ):
                listener.exitComma_module_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_module_instance_star" ):
                return visitor.visitComma_module_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_module_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_module_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 350, self.RULE_comma_module_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1801
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 1798
                self.comma_module_instance()
                self.state = 1803
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_module_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def module_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_module_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_module_instance" ):
                listener.enterComma_module_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_module_instance" ):
                listener.exitComma_module_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_module_instance" ):
                return visitor.visitComma_module_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_module_instance(self):

        localctx = SysVerilogHDLParser.Comma_module_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 352, self.RULE_comma_module_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1804
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1805
            self.module_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def module_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Module_instance_identifierContext,0)


        def port_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Port_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instance" ):
                listener.enterModule_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instance" ):
                listener.exitModule_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instance" ):
                return visitor.visitModule_instance(self)
            else:
                return visitor.visitChildren(self)




    def module_instance(self):

        localctx = SysVerilogHDLParser.Module_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 354, self.RULE_module_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1807
            self.module_instance_identifier()
            self.state = 1809
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Open_parenthesis:
                self.state = 1808
                self.port_interface_assignments()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Module_instance_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def arrayed_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Arrayed_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_module_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterModule_instance_identifier" ):
                listener.enterModule_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitModule_instance_identifier" ):
                listener.exitModule_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitModule_instance_identifier" ):
                return visitor.visitModule_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def module_instance_identifier(self):

        localctx = SysVerilogHDLParser.Module_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 356, self.RULE_module_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1811
            self.arrayed_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Arrayed_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def simple_arrayed_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Simple_arrayed_identifierContext,0)


        def escaped_arrayed_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Escaped_arrayed_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_arrayed_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArrayed_identifier" ):
                listener.enterArrayed_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArrayed_identifier" ):
                listener.exitArrayed_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArrayed_identifier" ):
                return visitor.visitArrayed_identifier(self)
            else:
                return visitor.visitChildren(self)




    def arrayed_identifier(self):

        localctx = SysVerilogHDLParser.Arrayed_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 358, self.RULE_arrayed_identifier)
        try:
            self.state = 1815
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1813
                self.simple_arrayed_identifier()
                pass
            elif token in [SysVerilogHDLParser.Escaped_identifier]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1814
                self.escaped_arrayed_identifier()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Simple_arrayed_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Simple_identifier(self):
            return self.getToken(SysVerilogHDLParser.Simple_identifier, 0)

        def dimension(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DimensionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_simple_arrayed_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSimple_arrayed_identifier" ):
                listener.enterSimple_arrayed_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSimple_arrayed_identifier" ):
                listener.exitSimple_arrayed_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSimple_arrayed_identifier" ):
                return visitor.visitSimple_arrayed_identifier(self)
            else:
                return visitor.visitChildren(self)




    def simple_arrayed_identifier(self):

        localctx = SysVerilogHDLParser.Simple_arrayed_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 360, self.RULE_simple_arrayed_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1817
            self.match(SysVerilogHDLParser.Simple_identifier)
            self.state = 1819
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1818
                self.dimension()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Escaped_arrayed_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Escaped_identifier(self):
            return self.getToken(SysVerilogHDLParser.Escaped_identifier, 0)

        def dimension(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DimensionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_escaped_arrayed_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEscaped_arrayed_identifier" ):
                listener.enterEscaped_arrayed_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEscaped_arrayed_identifier" ):
                listener.exitEscaped_arrayed_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEscaped_arrayed_identifier" ):
                return visitor.visitEscaped_arrayed_identifier(self)
            else:
                return visitor.visitChildren(self)




    def escaped_arrayed_identifier(self):

        localctx = SysVerilogHDLParser.Escaped_arrayed_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 362, self.RULE_escaped_arrayed_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1821
            self.match(SysVerilogHDLParser.Escaped_identifier)
            self.state = 1823
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 1822
                self.dimension()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Port_interface_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def list_of_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_port_interface_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPort_interface_assignments" ):
                listener.enterPort_interface_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPort_interface_assignments" ):
                listener.exitPort_interface_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPort_interface_assignments" ):
                return visitor.visitPort_interface_assignments(self)
            else:
                return visitor.visitChildren(self)




    def port_interface_assignments(self):

        localctx = SysVerilogHDLParser.Port_interface_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 364, self.RULE_port_interface_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1825
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 1827
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form))) != 0) or _la==SysVerilogHDLParser.Int or _la==SysVerilogHDLParser.Signed or ((((_la - 188)) & ~0x3f) == 0 and ((1 << (_la - 188)) & ((1 << (SysVerilogHDLParser.Unsigned - 188)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 188)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 188)) | (1 << (SysVerilogHDLParser.Simple_identifier - 188)) | (1 << (SysVerilogHDLParser.String_literal - 188)) | (1 << (SysVerilogHDLParser.Dot - 188)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 188)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 188)) | (1 << (SysVerilogHDLParser.Quote - 188)) | (1 << (SysVerilogHDLParser.Tilde - 188)))) != 0):
                self.state = 1826
                self.list_of_interface_assignments()


            self.state = 1829
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class DelayContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Hash(self):
            return self.getToken(SysVerilogHDLParser.Hash, 0)

        def delay_value(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Delay_valueContext,0)


        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def list_of_delay_values(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_delay_valuesContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_delay

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay" ):
                listener.enterDelay(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay" ):
                listener.exitDelay(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay" ):
                return visitor.visitDelay(self)
            else:
                return visitor.visitChildren(self)




    def delay(self):

        localctx = SysVerilogHDLParser.DelayContext(self, self._ctx, self.state)
        self.enterRule(localctx, 366, self.RULE_delay)
        try:
            self.state = 1838
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,125,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1831
                self.match(SysVerilogHDLParser.Hash)
                self.state = 1832
                self.delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1833
                self.match(SysVerilogHDLParser.Hash)
                self.state = 1834
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 1835
                self.list_of_delay_values()
                self.state = 1836
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_delay_valuesContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_value(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Delay_valueContext,0)


        def comma_delay_value_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_delay_value_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_delay_values

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_delay_values" ):
                listener.enterList_of_delay_values(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_delay_values" ):
                listener.exitList_of_delay_values(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_delay_values" ):
                return visitor.visitList_of_delay_values(self)
            else:
                return visitor.visitChildren(self)




    def list_of_delay_values(self):

        localctx = SysVerilogHDLParser.List_of_delay_valuesContext(self, self._ctx, self.state)
        self.enterRule(localctx, 368, self.RULE_list_of_delay_values)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1840
            self.delay_value()
            self.state = 1841
            self.comma_delay_value_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_delay_value_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_delay_value(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_delay_valueContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_delay_valueContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_delay_value_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_delay_value_star" ):
                listener.enterComma_delay_value_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_delay_value_star" ):
                listener.exitComma_delay_value_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_delay_value_star" ):
                return visitor.visitComma_delay_value_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_delay_value_star(self):

        localctx = SysVerilogHDLParser.Comma_delay_value_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 370, self.RULE_comma_delay_value_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1846
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 1843
                self.comma_delay_value()
                self.state = 1848
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_delay_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def delay_value(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Delay_valueContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_delay_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_delay_value" ):
                listener.enterComma_delay_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_delay_value" ):
                listener.exitComma_delay_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_delay_value" ):
                return visitor.visitComma_delay_value(self)
            else:
                return visitor.visitChildren(self)




    def comma_delay_value(self):

        localctx = SysVerilogHDLParser.Comma_delay_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 372, self.RULE_comma_delay_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1849
            self.match(SysVerilogHDLParser.Comma)
            self.state = 1850
            self.delay_value()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_delay_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_value" ):
                listener.enterDelay_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_value" ):
                listener.exitDelay_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_value" ):
                return visitor.visitDelay_value(self)
            else:
                return visitor.visitChildren(self)




    def delay_value(self):

        localctx = SysVerilogHDLParser.Delay_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 374, self.RULE_delay_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1852
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pulldown_strengthContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def strength0(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Strength0Context,0)


        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def strength1(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Strength1Context,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pulldown_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulldown_strength" ):
                listener.enterPulldown_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulldown_strength" ):
                listener.exitPulldown_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulldown_strength" ):
                return visitor.visitPulldown_strength(self)
            else:
                return visitor.visitChildren(self)




    def pulldown_strength(self):

        localctx = SysVerilogHDLParser.Pulldown_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 376, self.RULE_pulldown_strength)
        try:
            self.state = 1870
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,127,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1854
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 1855
                self.strength0()
                self.state = 1856
                self.match(SysVerilogHDLParser.Comma)
                self.state = 1857
                self.strength1()
                self.state = 1858
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1860
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 1861
                self.strength1()
                self.state = 1862
                self.match(SysVerilogHDLParser.Comma)
                self.state = 1863
                self.strength0()
                self.state = 1864
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1866
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 1867
                self.strength0()
                self.state = 1868
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pullup_strengthContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def strength0(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Strength0Context,0)


        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def strength1(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Strength1Context,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pullup_strength

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPullup_strength" ):
                listener.enterPullup_strength(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPullup_strength" ):
                listener.exitPullup_strength(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPullup_strength" ):
                return visitor.visitPullup_strength(self)
            else:
                return visitor.visitChildren(self)




    def pullup_strength(self):

        localctx = SysVerilogHDLParser.Pullup_strengthContext(self, self._ctx, self.state)
        self.enterRule(localctx, 378, self.RULE_pullup_strength)
        try:
            self.state = 1888
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,128,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 1872
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 1873
                self.strength0()
                self.state = 1874
                self.match(SysVerilogHDLParser.Comma)
                self.state = 1875
                self.strength1()
                self.state = 1876
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 1878
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 1879
                self.strength1()
                self.state = 1880
                self.match(SysVerilogHDLParser.Comma)
                self.state = 1881
                self.strength0()
                self.state = 1882
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 1884
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 1885
                self.strength1()
                self.state = 1886
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Gate_instance_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def arrayed_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Arrayed_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_gate_instance_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGate_instance_identifier" ):
                listener.enterGate_instance_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGate_instance_identifier" ):
                listener.exitGate_instance_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGate_instance_identifier" ):
                return visitor.visitGate_instance_identifier(self)
            else:
                return visitor.visitChildren(self)




    def gate_instance_identifier(self):

        localctx = SysVerilogHDLParser.Gate_instance_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 380, self.RULE_gate_instance_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1890
            self.arrayed_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Gate_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cmos_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Cmos_instantiationContext,0)


        def mos_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Mos_instantiationContext,0)


        def pass_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_instantiationContext,0)


        def pulldown_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pulldown_instantiationContext,0)


        def pullup_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pullup_instantiationContext,0)


        def enable_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enable_instantiationContext,0)


        def n_input_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_input_instantiationContext,0)


        def n_output_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_output_instantiationContext,0)


        def pass_enable_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_enable_instantiationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_gate_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGate_instantiation" ):
                listener.enterGate_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGate_instantiation" ):
                listener.exitGate_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGate_instantiation" ):
                return visitor.visitGate_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def gate_instantiation(self):

        localctx = SysVerilogHDLParser.Gate_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 382, self.RULE_gate_instantiation)
        try:
            self.state = 1901
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Cmos, SysVerilogHDLParser.Rcmos]:
                self.enterOuterAlt(localctx, 1)
                self.state = 1892
                self.cmos_instantiation()
                pass
            elif token in [SysVerilogHDLParser.Nmos, SysVerilogHDLParser.Pmos, SysVerilogHDLParser.Rnmos, SysVerilogHDLParser.Rpmos]:
                self.enterOuterAlt(localctx, 2)
                self.state = 1893
                self.mos_instantiation()
                pass
            elif token in [SysVerilogHDLParser.Rtran, SysVerilogHDLParser.Tran]:
                self.enterOuterAlt(localctx, 3)
                self.state = 1894
                self.pass_instantiation()
                pass
            elif token in [SysVerilogHDLParser.Pulldown]:
                self.enterOuterAlt(localctx, 4)
                self.state = 1895
                self.pulldown_instantiation()
                pass
            elif token in [SysVerilogHDLParser.Pullup]:
                self.enterOuterAlt(localctx, 5)
                self.state = 1896
                self.pullup_instantiation()
                pass
            elif token in [SysVerilogHDLParser.Bufif0, SysVerilogHDLParser.Bufif1, SysVerilogHDLParser.Notif0, SysVerilogHDLParser.Notif1]:
                self.enterOuterAlt(localctx, 6)
                self.state = 1897
                self.enable_instantiation()
                pass
            elif token in [SysVerilogHDLParser.And, SysVerilogHDLParser.Nand, SysVerilogHDLParser.Nor, SysVerilogHDLParser.Or, SysVerilogHDLParser.Xnor, SysVerilogHDLParser.Xor]:
                self.enterOuterAlt(localctx, 7)
                self.state = 1898
                self.n_input_instantiation()
                pass
            elif token in [SysVerilogHDLParser.Buf, SysVerilogHDLParser.Not]:
                self.enterOuterAlt(localctx, 8)
                self.state = 1899
                self.n_output_instantiation()
                pass
            elif token in [SysVerilogHDLParser.Rtranif0, SysVerilogHDLParser.Rtranif1, SysVerilogHDLParser.Tranif0, SysVerilogHDLParser.Tranif1]:
                self.enterOuterAlt(localctx, 9)
                self.state = 1900
                self.pass_enable_instantiation()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_gatetypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Bufif0(self):
            return self.getToken(SysVerilogHDLParser.Bufif0, 0)

        def Bufif1(self):
            return self.getToken(SysVerilogHDLParser.Bufif1, 0)

        def Notif0(self):
            return self.getToken(SysVerilogHDLParser.Notif0, 0)

        def Notif1(self):
            return self.getToken(SysVerilogHDLParser.Notif1, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enable_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gatetype" ):
                listener.enterEnable_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gatetype" ):
                listener.exitEnable_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gatetype" ):
                return visitor.visitEnable_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def enable_gatetype(self):

        localctx = SysVerilogHDLParser.Enable_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 384, self.RULE_enable_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1903
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Bufif0 or _la==SysVerilogHDLParser.Bufif1 or _la==SysVerilogHDLParser.Notif0 or _la==SysVerilogHDLParser.Notif1):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mos_switchtypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Nmos(self):
            return self.getToken(SysVerilogHDLParser.Nmos, 0)

        def Pmos(self):
            return self.getToken(SysVerilogHDLParser.Pmos, 0)

        def Rnmos(self):
            return self.getToken(SysVerilogHDLParser.Rnmos, 0)

        def Rpmos(self):
            return self.getToken(SysVerilogHDLParser.Rpmos, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_mos_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switchtype" ):
                listener.enterMos_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switchtype" ):
                listener.exitMos_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switchtype" ):
                return visitor.visitMos_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def mos_switchtype(self):

        localctx = SysVerilogHDLParser.Mos_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 386, self.RULE_mos_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1905
            _la = self._input.LA(1)
            if not(((((_la - 124)) & ~0x3f) == 0 and ((1 << (_la - 124)) & ((1 << (SysVerilogHDLParser.Nmos - 124)) | (1 << (SysVerilogHDLParser.Pmos - 124)) | (1 << (SysVerilogHDLParser.Rnmos - 124)) | (1 << (SysVerilogHDLParser.Rpmos - 124)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cmos_switchtypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Cmos(self):
            return self.getToken(SysVerilogHDLParser.Cmos, 0)

        def Rcmos(self):
            return self.getToken(SysVerilogHDLParser.Rcmos, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_cmos_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switchtype" ):
                listener.enterCmos_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switchtype" ):
                listener.exitCmos_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switchtype" ):
                return visitor.visitCmos_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switchtype(self):

        localctx = SysVerilogHDLParser.Cmos_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 388, self.RULE_cmos_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1907
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Cmos or _la==SysVerilogHDLParser.Rcmos):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_output_gatetypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Buf(self):
            return self.getToken(SysVerilogHDLParser.Buf, 0)

        def Not(self):
            return self.getToken(SysVerilogHDLParser.Not, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_n_output_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gatetype" ):
                listener.enterN_output_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gatetype" ):
                listener.exitN_output_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gatetype" ):
                return visitor.visitN_output_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gatetype(self):

        localctx = SysVerilogHDLParser.N_output_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 390, self.RULE_n_output_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1909
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Buf or _la==SysVerilogHDLParser.Not):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_input_gatetypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def And(self):
            return self.getToken(SysVerilogHDLParser.And, 0)

        def Nand(self):
            return self.getToken(SysVerilogHDLParser.Nand, 0)

        def Or(self):
            return self.getToken(SysVerilogHDLParser.Or, 0)

        def Nor(self):
            return self.getToken(SysVerilogHDLParser.Nor, 0)

        def Xor(self):
            return self.getToken(SysVerilogHDLParser.Xor, 0)

        def Xnor(self):
            return self.getToken(SysVerilogHDLParser.Xnor, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_n_input_gatetype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gatetype" ):
                listener.enterN_input_gatetype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gatetype" ):
                listener.exitN_input_gatetype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gatetype" ):
                return visitor.visitN_input_gatetype(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gatetype(self):

        localctx = SysVerilogHDLParser.N_input_gatetypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 392, self.RULE_n_input_gatetype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1911
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.And or ((((_la - 122)) & ~0x3f) == 0 and ((1 << (_la - 122)) & ((1 << (SysVerilogHDLParser.Nand - 122)) | (1 << (SysVerilogHDLParser.Nor - 122)) | (1 << (SysVerilogHDLParser.Or - 122)))) != 0) or _la==SysVerilogHDLParser.Xnor or _la==SysVerilogHDLParser.Xor):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_switchtypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Tran(self):
            return self.getToken(SysVerilogHDLParser.Tran, 0)

        def Rtran(self):
            return self.getToken(SysVerilogHDLParser.Rtran, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pass_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switchtype" ):
                listener.enterPass_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switchtype" ):
                listener.exitPass_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switchtype" ):
                return visitor.visitPass_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def pass_switchtype(self):

        localctx = SysVerilogHDLParser.Pass_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 394, self.RULE_pass_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1913
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Rtran or _la==SysVerilogHDLParser.Tran):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_enable_switchtypeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Tranif0(self):
            return self.getToken(SysVerilogHDLParser.Tranif0, 0)

        def Tranif1(self):
            return self.getToken(SysVerilogHDLParser.Tranif1, 0)

        def Rtranif1(self):
            return self.getToken(SysVerilogHDLParser.Rtranif1, 0)

        def Rtranif0(self):
            return self.getToken(SysVerilogHDLParser.Rtranif0, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pass_enable_switchtype

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_enable_switchtype" ):
                listener.enterPass_enable_switchtype(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_enable_switchtype" ):
                listener.exitPass_enable_switchtype(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_enable_switchtype" ):
                return visitor.visitPass_enable_switchtype(self)
            else:
                return visitor.visitChildren(self)




    def pass_enable_switchtype(self):

        localctx = SysVerilogHDLParser.Pass_enable_switchtypeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 396, self.RULE_pass_enable_switchtype)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1915
            _la = self._input.LA(1)
            if not(((((_la - 157)) & ~0x3f) == 0 and ((1 << (_la - 157)) & ((1 << (SysVerilogHDLParser.Rtranif0 - 157)) | (1 << (SysVerilogHDLParser.Rtranif1 - 157)) | (1 << (SysVerilogHDLParser.Tranif0 - 157)) | (1 << (SysVerilogHDLParser.Tranif1 - 157)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pulldown_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Pulldown(self):
            return self.getToken(SysVerilogHDLParser.Pulldown, 0)

        def list_of_pull_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_pull_gate_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def pulldown_strength(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pulldown_strengthContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pulldown_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPulldown_instantiation" ):
                listener.enterPulldown_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPulldown_instantiation" ):
                listener.exitPulldown_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPulldown_instantiation" ):
                return visitor.visitPulldown_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def pulldown_instantiation(self):

        localctx = SysVerilogHDLParser.Pulldown_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 398, self.RULE_pulldown_instantiation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1917
            self.match(SysVerilogHDLParser.Pulldown)
            self.state = 1919
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,130,self._ctx)
            if la_ == 1:
                self.state = 1918
                self.pulldown_strength()


            self.state = 1921
            self.list_of_pull_gate_instance()
            self.state = 1922
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pullup_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Pullup(self):
            return self.getToken(SysVerilogHDLParser.Pullup, 0)

        def list_of_pull_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_pull_gate_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def pullup_strength(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pullup_strengthContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pullup_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPullup_instantiation" ):
                listener.enterPullup_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPullup_instantiation" ):
                listener.exitPullup_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPullup_instantiation" ):
                return visitor.visitPullup_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def pullup_instantiation(self):

        localctx = SysVerilogHDLParser.Pullup_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 400, self.RULE_pullup_instantiation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1924
            self.match(SysVerilogHDLParser.Pullup)
            self.state = 1926
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,131,self._ctx)
            if la_ == 1:
                self.state = 1925
                self.pullup_strength()


            self.state = 1928
            self.list_of_pull_gate_instance()
            self.state = 1929
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def enable_gatetype(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enable_gatetypeContext,0)


        def list_of_enable_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_enable_gate_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def drive_strength(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Drive_strengthContext,0)


        def delay(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DelayContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enable_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_instantiation" ):
                listener.enterEnable_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_instantiation" ):
                listener.exitEnable_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_instantiation" ):
                return visitor.visitEnable_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def enable_instantiation(self):

        localctx = SysVerilogHDLParser.Enable_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 402, self.RULE_enable_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1931
            self.enable_gatetype()
            self.state = 1933
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,132,self._ctx)
            if la_ == 1:
                self.state = 1932
                self.drive_strength()


            self.state = 1936
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 1935
                self.delay()


            self.state = 1938
            self.list_of_enable_gate_instance()
            self.state = 1939
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mos_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def mos_switchtype(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Mos_switchtypeContext,0)


        def list_of_mos_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_mos_switch_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def delay(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DelayContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_mos_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_instantiation" ):
                listener.enterMos_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_instantiation" ):
                listener.exitMos_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_instantiation" ):
                return visitor.visitMos_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def mos_instantiation(self):

        localctx = SysVerilogHDLParser.Mos_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 404, self.RULE_mos_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1941
            self.mos_switchtype()
            self.state = 1943
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 1942
                self.delay()


            self.state = 1945
            self.list_of_mos_switch_instance()
            self.state = 1946
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cmos_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cmos_switchtype(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Cmos_switchtypeContext,0)


        def list_of_cmos_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_cmos_switch_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def delay(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DelayContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_cmos_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_instantiation" ):
                listener.enterCmos_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_instantiation" ):
                listener.exitCmos_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_instantiation" ):
                return visitor.visitCmos_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def cmos_instantiation(self):

        localctx = SysVerilogHDLParser.Cmos_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 406, self.RULE_cmos_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1948
            self.cmos_switchtype()
            self.state = 1950
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 1949
                self.delay()


            self.state = 1952
            self.list_of_cmos_switch_instance()
            self.state = 1953
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_output_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def n_output_gatetype(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_output_gatetypeContext,0)


        def list_of_n_output_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_n_output_gate_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def drive_strength(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Drive_strengthContext,0)


        def delay(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DelayContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_n_output_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_instantiation" ):
                listener.enterN_output_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_instantiation" ):
                listener.exitN_output_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_instantiation" ):
                return visitor.visitN_output_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def n_output_instantiation(self):

        localctx = SysVerilogHDLParser.N_output_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 408, self.RULE_n_output_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1955
            self.n_output_gatetype()
            self.state = 1957
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,136,self._ctx)
            if la_ == 1:
                self.state = 1956
                self.drive_strength()


            self.state = 1960
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 1959
                self.delay()


            self.state = 1962
            self.list_of_n_output_gate_instance()
            self.state = 1963
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_input_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def n_input_gatetype(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_input_gatetypeContext,0)


        def list_of_n_input_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_n_input_gate_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def drive_strength(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Drive_strengthContext,0)


        def delay(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DelayContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_n_input_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_instantiation" ):
                listener.enterN_input_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_instantiation" ):
                listener.exitN_input_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_instantiation" ):
                return visitor.visitN_input_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def n_input_instantiation(self):

        localctx = SysVerilogHDLParser.N_input_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 410, self.RULE_n_input_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1965
            self.n_input_gatetype()
            self.state = 1967
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,138,self._ctx)
            if la_ == 1:
                self.state = 1966
                self.drive_strength()


            self.state = 1970
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 1969
                self.delay()


            self.state = 1972
            self.list_of_n_input_gate_instance()
            self.state = 1973
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pass_switchtype(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_switchtypeContext,0)


        def list_of_pass_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_pass_switch_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pass_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_instantiation" ):
                listener.enterPass_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_instantiation" ):
                listener.exitPass_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_instantiation" ):
                return visitor.visitPass_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def pass_instantiation(self):

        localctx = SysVerilogHDLParser.Pass_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 412, self.RULE_pass_instantiation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1975
            self.pass_switchtype()
            self.state = 1976
            self.list_of_pass_switch_instance()
            self.state = 1977
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_enable_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pass_enable_switchtype(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_enable_switchtypeContext,0)


        def list_of_pass_enable_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_pass_enable_switch_instanceContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def delay(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DelayContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pass_enable_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_enable_instantiation" ):
                listener.enterPass_enable_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_enable_instantiation" ):
                listener.exitPass_enable_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_enable_instantiation" ):
                return visitor.visitPass_enable_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def pass_enable_instantiation(self):

        localctx = SysVerilogHDLParser.Pass_enable_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 414, self.RULE_pass_enable_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1979
            self.pass_enable_switchtype()
            self.state = 1981
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 1980
                self.delay()


            self.state = 1983
            self.list_of_pass_enable_switch_instance()
            self.state = 1984
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_pull_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pull_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pull_gate_instanceContext,0)


        def comma_pull_gate_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_pull_gate_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_pull_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_pull_gate_instance" ):
                listener.enterList_of_pull_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_pull_gate_instance" ):
                listener.exitList_of_pull_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_pull_gate_instance" ):
                return visitor.visitList_of_pull_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def list_of_pull_gate_instance(self):

        localctx = SysVerilogHDLParser.List_of_pull_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 416, self.RULE_list_of_pull_gate_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1986
            self.pull_gate_instance()
            self.state = 1987
            self.comma_pull_gate_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_enable_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def enable_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enable_gate_instanceContext,0)


        def comma_enable_gate_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_enable_gate_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_enable_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_enable_gate_instance" ):
                listener.enterList_of_enable_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_enable_gate_instance" ):
                listener.exitList_of_enable_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_enable_gate_instance" ):
                return visitor.visitList_of_enable_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def list_of_enable_gate_instance(self):

        localctx = SysVerilogHDLParser.List_of_enable_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 418, self.RULE_list_of_enable_gate_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1989
            self.enable_gate_instance()
            self.state = 1990
            self.comma_enable_gate_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_mos_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def mos_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Mos_switch_instanceContext,0)


        def comma_mos_switch_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_mos_switch_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_mos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_mos_switch_instance" ):
                listener.enterList_of_mos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_mos_switch_instance" ):
                listener.exitList_of_mos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_mos_switch_instance" ):
                return visitor.visitList_of_mos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def list_of_mos_switch_instance(self):

        localctx = SysVerilogHDLParser.List_of_mos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 420, self.RULE_list_of_mos_switch_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1992
            self.mos_switch_instance()
            self.state = 1993
            self.comma_mos_switch_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_cmos_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cmos_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Cmos_switch_instanceContext,0)


        def comma_cmos_switch_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_cmos_switch_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_cmos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_cmos_switch_instance" ):
                listener.enterList_of_cmos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_cmos_switch_instance" ):
                listener.exitList_of_cmos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_cmos_switch_instance" ):
                return visitor.visitList_of_cmos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def list_of_cmos_switch_instance(self):

        localctx = SysVerilogHDLParser.List_of_cmos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 422, self.RULE_list_of_cmos_switch_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1995
            self.cmos_switch_instance()
            self.state = 1996
            self.comma_cmos_switch_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_n_input_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def n_input_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_input_gate_instanceContext,0)


        def comma_n_input_gate_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_n_input_gate_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_n_input_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_n_input_gate_instance" ):
                listener.enterList_of_n_input_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_n_input_gate_instance" ):
                listener.exitList_of_n_input_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_n_input_gate_instance" ):
                return visitor.visitList_of_n_input_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def list_of_n_input_gate_instance(self):

        localctx = SysVerilogHDLParser.List_of_n_input_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 424, self.RULE_list_of_n_input_gate_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 1998
            self.n_input_gate_instance()
            self.state = 1999
            self.comma_n_input_gate_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_n_output_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def n_output_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_output_gate_instanceContext,0)


        def comma_n_output_gate_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_n_output_gate_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_n_output_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_n_output_gate_instance" ):
                listener.enterList_of_n_output_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_n_output_gate_instance" ):
                listener.exitList_of_n_output_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_n_output_gate_instance" ):
                return visitor.visitList_of_n_output_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def list_of_n_output_gate_instance(self):

        localctx = SysVerilogHDLParser.List_of_n_output_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 426, self.RULE_list_of_n_output_gate_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2001
            self.n_output_gate_instance()
            self.state = 2002
            self.comma_n_output_gate_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_pass_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pass_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_switch_instanceContext,0)


        def comma_pass_switch_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_pass_switch_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_pass_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_pass_switch_instance" ):
                listener.enterList_of_pass_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_pass_switch_instance" ):
                listener.exitList_of_pass_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_pass_switch_instance" ):
                return visitor.visitList_of_pass_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def list_of_pass_switch_instance(self):

        localctx = SysVerilogHDLParser.List_of_pass_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 428, self.RULE_list_of_pass_switch_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2004
            self.pass_switch_instance()
            self.state = 2005
            self.comma_pass_switch_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_pass_enable_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pass_enable_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_enable_switch_instanceContext,0)


        def comma_pass_enable_switch_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_pass_enable_switch_instance_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_pass_enable_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_pass_enable_switch_instance" ):
                listener.enterList_of_pass_enable_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_pass_enable_switch_instance" ):
                listener.exitList_of_pass_enable_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_pass_enable_switch_instance" ):
                return visitor.visitList_of_pass_enable_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def list_of_pass_enable_switch_instance(self):

        localctx = SysVerilogHDLParser.List_of_pass_enable_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 430, self.RULE_list_of_pass_enable_switch_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2007
            self.pass_enable_switch_instance()
            self.state = 2008
            self.comma_pass_enable_switch_instance_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_pull_gate_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_pull_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_pull_gate_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_pull_gate_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_pull_gate_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_pull_gate_instance_star" ):
                listener.enterComma_pull_gate_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_pull_gate_instance_star" ):
                listener.exitComma_pull_gate_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_pull_gate_instance_star" ):
                return visitor.visitComma_pull_gate_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_pull_gate_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_pull_gate_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 432, self.RULE_comma_pull_gate_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2013
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2010
                self.comma_pull_gate_instance()
                self.state = 2015
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_enable_gate_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_enable_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_enable_gate_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_enable_gate_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_enable_gate_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_enable_gate_instance_star" ):
                listener.enterComma_enable_gate_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_enable_gate_instance_star" ):
                listener.exitComma_enable_gate_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_enable_gate_instance_star" ):
                return visitor.visitComma_enable_gate_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_enable_gate_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_enable_gate_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 434, self.RULE_comma_enable_gate_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2019
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2016
                self.comma_enable_gate_instance()
                self.state = 2021
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_mos_switch_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_mos_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_mos_switch_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_mos_switch_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_mos_switch_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_mos_switch_instance_star" ):
                listener.enterComma_mos_switch_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_mos_switch_instance_star" ):
                listener.exitComma_mos_switch_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_mos_switch_instance_star" ):
                return visitor.visitComma_mos_switch_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_mos_switch_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_mos_switch_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 436, self.RULE_comma_mos_switch_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2025
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2022
                self.comma_mos_switch_instance()
                self.state = 2027
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_cmos_switch_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_cmos_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_cmos_switch_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_cmos_switch_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_cmos_switch_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_cmos_switch_instance_star" ):
                listener.enterComma_cmos_switch_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_cmos_switch_instance_star" ):
                listener.exitComma_cmos_switch_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_cmos_switch_instance_star" ):
                return visitor.visitComma_cmos_switch_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_cmos_switch_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_cmos_switch_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 438, self.RULE_comma_cmos_switch_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2031
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2028
                self.comma_cmos_switch_instance()
                self.state = 2033
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_n_input_gate_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_n_input_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_n_input_gate_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_n_input_gate_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_n_input_gate_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_n_input_gate_instance_star" ):
                listener.enterComma_n_input_gate_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_n_input_gate_instance_star" ):
                listener.exitComma_n_input_gate_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_n_input_gate_instance_star" ):
                return visitor.visitComma_n_input_gate_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_n_input_gate_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_n_input_gate_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 440, self.RULE_comma_n_input_gate_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2037
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2034
                self.comma_n_input_gate_instance()
                self.state = 2039
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_n_output_gate_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_n_output_gate_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_n_output_gate_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_n_output_gate_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_n_output_gate_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_n_output_gate_instance_star" ):
                listener.enterComma_n_output_gate_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_n_output_gate_instance_star" ):
                listener.exitComma_n_output_gate_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_n_output_gate_instance_star" ):
                return visitor.visitComma_n_output_gate_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_n_output_gate_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_n_output_gate_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 442, self.RULE_comma_n_output_gate_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2043
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2040
                self.comma_n_output_gate_instance()
                self.state = 2045
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_pass_switch_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_pass_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_pass_switch_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_pass_switch_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_pass_switch_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_pass_switch_instance_star" ):
                listener.enterComma_pass_switch_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_pass_switch_instance_star" ):
                listener.exitComma_pass_switch_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_pass_switch_instance_star" ):
                return visitor.visitComma_pass_switch_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_pass_switch_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_pass_switch_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 444, self.RULE_comma_pass_switch_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2049
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2046
                self.comma_pass_switch_instance()
                self.state = 2051
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_pass_enable_switch_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_pass_enable_switch_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_pass_enable_switch_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_pass_enable_switch_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_pass_enable_switch_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_pass_enable_switch_instance_star" ):
                listener.enterComma_pass_enable_switch_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_pass_enable_switch_instance_star" ):
                listener.exitComma_pass_enable_switch_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_pass_enable_switch_instance_star" ):
                return visitor.visitComma_pass_enable_switch_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_pass_enable_switch_instance_star(self):

        localctx = SysVerilogHDLParser.Comma_pass_enable_switch_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 446, self.RULE_comma_pass_enable_switch_instance_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2055
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2052
                self.comma_pass_enable_switch_instance()
                self.state = 2057
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_pull_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def pull_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pull_gate_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_pull_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_pull_gate_instance" ):
                listener.enterComma_pull_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_pull_gate_instance" ):
                listener.exitComma_pull_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_pull_gate_instance" ):
                return visitor.visitComma_pull_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_pull_gate_instance(self):

        localctx = SysVerilogHDLParser.Comma_pull_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 448, self.RULE_comma_pull_gate_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2058
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2059
            self.pull_gate_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_enable_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def enable_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enable_gate_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_enable_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_enable_gate_instance" ):
                listener.enterComma_enable_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_enable_gate_instance" ):
                listener.exitComma_enable_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_enable_gate_instance" ):
                return visitor.visitComma_enable_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_enable_gate_instance(self):

        localctx = SysVerilogHDLParser.Comma_enable_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 450, self.RULE_comma_enable_gate_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2061
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2062
            self.enable_gate_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_mos_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def mos_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Mos_switch_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_mos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_mos_switch_instance" ):
                listener.enterComma_mos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_mos_switch_instance" ):
                listener.exitComma_mos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_mos_switch_instance" ):
                return visitor.visitComma_mos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_mos_switch_instance(self):

        localctx = SysVerilogHDLParser.Comma_mos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 452, self.RULE_comma_mos_switch_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2064
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2065
            self.mos_switch_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_cmos_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def cmos_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Cmos_switch_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_cmos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_cmos_switch_instance" ):
                listener.enterComma_cmos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_cmos_switch_instance" ):
                listener.exitComma_cmos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_cmos_switch_instance" ):
                return visitor.visitComma_cmos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_cmos_switch_instance(self):

        localctx = SysVerilogHDLParser.Comma_cmos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 454, self.RULE_comma_cmos_switch_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2067
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2068
            self.cmos_switch_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_n_input_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def n_input_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_input_gate_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_n_input_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_n_input_gate_instance" ):
                listener.enterComma_n_input_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_n_input_gate_instance" ):
                listener.exitComma_n_input_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_n_input_gate_instance" ):
                return visitor.visitComma_n_input_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_n_input_gate_instance(self):

        localctx = SysVerilogHDLParser.Comma_n_input_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 456, self.RULE_comma_n_input_gate_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2070
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2071
            self.n_input_gate_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_n_output_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def n_output_gate_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_output_gate_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_n_output_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_n_output_gate_instance" ):
                listener.enterComma_n_output_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_n_output_gate_instance" ):
                listener.exitComma_n_output_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_n_output_gate_instance" ):
                return visitor.visitComma_n_output_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_n_output_gate_instance(self):

        localctx = SysVerilogHDLParser.Comma_n_output_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 458, self.RULE_comma_n_output_gate_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2073
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2074
            self.n_output_gate_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_pass_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def pass_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_switch_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_pass_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_pass_switch_instance" ):
                listener.enterComma_pass_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_pass_switch_instance" ):
                listener.exitComma_pass_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_pass_switch_instance" ):
                return visitor.visitComma_pass_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_pass_switch_instance(self):

        localctx = SysVerilogHDLParser.Comma_pass_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 460, self.RULE_comma_pass_switch_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2076
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2077
            self.pass_switch_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_pass_enable_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def pass_enable_switch_instance(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_enable_switch_instanceContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_pass_enable_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_pass_enable_switch_instance" ):
                listener.enterComma_pass_enable_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_pass_enable_switch_instance" ):
                listener.exitComma_pass_enable_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_pass_enable_switch_instance" ):
                return visitor.visitComma_pass_enable_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def comma_pass_enable_switch_instance(self):

        localctx = SysVerilogHDLParser.Comma_pass_enable_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 462, self.RULE_comma_pass_enable_switch_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2079
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2080
            self.pass_enable_switch_instance()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pull_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pull_gate_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pull_gate_interfaceContext,0)


        def gate_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instance_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pull_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPull_gate_instance" ):
                listener.enterPull_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPull_gate_instance" ):
                listener.exitPull_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPull_gate_instance" ):
                return visitor.visitPull_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def pull_gate_instance(self):

        localctx = SysVerilogHDLParser.Pull_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 464, self.RULE_pull_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2083
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2082
                self.gate_instance_identifier()


            self.state = 2085
            self.pull_gate_interface()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def enable_gate_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enable_gate_interfaceContext,0)


        def gate_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instance_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enable_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gate_instance" ):
                listener.enterEnable_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gate_instance" ):
                listener.exitEnable_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gate_instance" ):
                return visitor.visitEnable_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def enable_gate_instance(self):

        localctx = SysVerilogHDLParser.Enable_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 466, self.RULE_enable_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2088
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2087
                self.gate_instance_identifier()


            self.state = 2090
            self.enable_gate_interface()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mos_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def mos_switch_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Mos_switch_interfaceContext,0)


        def gate_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instance_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_mos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switch_instance" ):
                listener.enterMos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switch_instance" ):
                listener.exitMos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switch_instance" ):
                return visitor.visitMos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def mos_switch_instance(self):

        localctx = SysVerilogHDLParser.Mos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 468, self.RULE_mos_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2093
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2092
                self.gate_instance_identifier()


            self.state = 2095
            self.mos_switch_interface()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cmos_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def cmos_switch_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Cmos_switch_interfaceContext,0)


        def gate_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instance_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_cmos_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switch_instance" ):
                listener.enterCmos_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switch_instance" ):
                listener.exitCmos_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switch_instance" ):
                return visitor.visitCmos_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switch_instance(self):

        localctx = SysVerilogHDLParser.Cmos_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 470, self.RULE_cmos_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2098
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2097
                self.gate_instance_identifier()


            self.state = 2100
            self.cmos_switch_interface()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_input_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def n_input_gate_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_input_gate_interfaceContext,0)


        def gate_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instance_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_n_input_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gate_instance" ):
                listener.enterN_input_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gate_instance" ):
                listener.exitN_input_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gate_instance" ):
                return visitor.visitN_input_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gate_instance(self):

        localctx = SysVerilogHDLParser.N_input_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 472, self.RULE_n_input_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2103
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2102
                self.gate_instance_identifier()


            self.state = 2105
            self.n_input_gate_interface()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_output_gate_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def n_output_gate_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.N_output_gate_interfaceContext,0)


        def gate_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instance_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_n_output_gate_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gate_instance" ):
                listener.enterN_output_gate_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gate_instance" ):
                listener.exitN_output_gate_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gate_instance" ):
                return visitor.visitN_output_gate_instance(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gate_instance(self):

        localctx = SysVerilogHDLParser.N_output_gate_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 474, self.RULE_n_output_gate_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2108
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2107
                self.gate_instance_identifier()


            self.state = 2110
            self.n_output_gate_interface()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pass_switch_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_switch_interfaceContext,0)


        def gate_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instance_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pass_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switch_instance" ):
                listener.enterPass_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switch_instance" ):
                listener.exitPass_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switch_instance" ):
                return visitor.visitPass_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def pass_switch_instance(self):

        localctx = SysVerilogHDLParser.Pass_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 476, self.RULE_pass_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2113
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2112
                self.gate_instance_identifier()


            self.state = 2115
            self.pass_switch_interface()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_enable_switch_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def pass_enable_switch_interface(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pass_enable_switch_interfaceContext,0)


        def gate_instance_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Gate_instance_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pass_enable_switch_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_enable_switch_instance" ):
                listener.enterPass_enable_switch_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_enable_switch_instance" ):
                listener.exitPass_enable_switch_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_enable_switch_instance" ):
                return visitor.visitPass_enable_switch_instance(self)
            else:
                return visitor.visitChildren(self)




    def pass_enable_switch_instance(self):

        localctx = SysVerilogHDLParser.Pass_enable_switch_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 478, self.RULE_pass_enable_switch_instance)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2118
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2117
                self.gate_instance_identifier()


            self.state = 2120
            self.pass_enable_switch_interface()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pull_gate_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_terminalContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pull_gate_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPull_gate_interface" ):
                listener.enterPull_gate_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPull_gate_interface" ):
                listener.exitPull_gate_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPull_gate_interface" ):
                return visitor.visitPull_gate_interface(self)
            else:
                return visitor.visitChildren(self)




    def pull_gate_interface(self):

        localctx = SysVerilogHDLParser.Pull_gate_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 480, self.RULE_pull_gate_interface)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2122
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2123
            self.output_terminal()
            self.state = 2124
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_gate_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_terminalContext,0)


        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def input_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_terminalContext,0)


        def enable_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enable_terminalContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enable_gate_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_gate_interface" ):
                listener.enterEnable_gate_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_gate_interface" ):
                listener.exitEnable_gate_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_gate_interface" ):
                return visitor.visitEnable_gate_interface(self)
            else:
                return visitor.visitChildren(self)




    def enable_gate_interface(self):

        localctx = SysVerilogHDLParser.Enable_gate_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 482, self.RULE_enable_gate_interface)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2126
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2127
            self.output_terminal()
            self.state = 2128
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2129
            self.input_terminal()
            self.state = 2130
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2131
            self.enable_terminal()
            self.state = 2132
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mos_switch_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_terminalContext,0)


        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def input_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_terminalContext,0)


        def enable_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enable_terminalContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_mos_switch_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMos_switch_interface" ):
                listener.enterMos_switch_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMos_switch_interface" ):
                listener.exitMos_switch_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMos_switch_interface" ):
                return visitor.visitMos_switch_interface(self)
            else:
                return visitor.visitChildren(self)




    def mos_switch_interface(self):

        localctx = SysVerilogHDLParser.Mos_switch_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 484, self.RULE_mos_switch_interface)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2134
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2135
            self.output_terminal()
            self.state = 2136
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2137
            self.input_terminal()
            self.state = 2138
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2139
            self.enable_terminal()
            self.state = 2140
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Cmos_switch_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_terminalContext,0)


        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def input_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_terminalContext,0)


        def ncontrol_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Ncontrol_terminalContext,0)


        def pcontrol_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Pcontrol_terminalContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_cmos_switch_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCmos_switch_interface" ):
                listener.enterCmos_switch_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCmos_switch_interface" ):
                listener.exitCmos_switch_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCmos_switch_interface" ):
                return visitor.visitCmos_switch_interface(self)
            else:
                return visitor.visitChildren(self)




    def cmos_switch_interface(self):

        localctx = SysVerilogHDLParser.Cmos_switch_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 486, self.RULE_cmos_switch_interface)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2142
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2143
            self.output_terminal()
            self.state = 2144
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2145
            self.input_terminal()
            self.state = 2146
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2147
            self.ncontrol_terminal()
            self.state = 2148
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2149
            self.pcontrol_terminal()
            self.state = 2150
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_input_gate_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_terminalContext,0)


        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def list_of_input_terminals(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_input_terminalsContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_n_input_gate_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_input_gate_interface" ):
                listener.enterN_input_gate_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_input_gate_interface" ):
                listener.exitN_input_gate_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_input_gate_interface" ):
                return visitor.visitN_input_gate_interface(self)
            else:
                return visitor.visitChildren(self)




    def n_input_gate_interface(self):

        localctx = SysVerilogHDLParser.N_input_gate_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 488, self.RULE_n_input_gate_interface)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2152
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2153
            self.output_terminal()
            self.state = 2154
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2155
            self.list_of_input_terminals()
            self.state = 2156
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class N_output_gate_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def list_of_output_terminals(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_output_terminalsContext,0)


        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def input_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_terminalContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_n_output_gate_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterN_output_gate_interface" ):
                listener.enterN_output_gate_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitN_output_gate_interface" ):
                listener.exitN_output_gate_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitN_output_gate_interface" ):
                return visitor.visitN_output_gate_interface(self)
            else:
                return visitor.visitChildren(self)




    def n_output_gate_interface(self):

        localctx = SysVerilogHDLParser.N_output_gate_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 490, self.RULE_n_output_gate_interface)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2158
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2159
            self.list_of_output_terminals()
            self.state = 2160
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2161
            self.input_terminal()
            self.state = 2162
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_switch_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def inout_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Inout_terminalContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Inout_terminalContext,i)


        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pass_switch_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_switch_interface" ):
                listener.enterPass_switch_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_switch_interface" ):
                listener.exitPass_switch_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_switch_interface" ):
                return visitor.visitPass_switch_interface(self)
            else:
                return visitor.visitChildren(self)




    def pass_switch_interface(self):

        localctx = SysVerilogHDLParser.Pass_switch_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 492, self.RULE_pass_switch_interface)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2164
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2165
            self.inout_terminal()
            self.state = 2166
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2167
            self.inout_terminal()
            self.state = 2168
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pass_enable_switch_interfaceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def inout_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Inout_terminalContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Inout_terminalContext,i)


        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def enable_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enable_terminalContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pass_enable_switch_interface

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPass_enable_switch_interface" ):
                listener.enterPass_enable_switch_interface(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPass_enable_switch_interface" ):
                listener.exitPass_enable_switch_interface(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPass_enable_switch_interface" ):
                return visitor.visitPass_enable_switch_interface(self)
            else:
                return visitor.visitChildren(self)




    def pass_enable_switch_interface(self):

        localctx = SysVerilogHDLParser.Pass_enable_switch_interfaceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 494, self.RULE_pass_enable_switch_interface)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2170
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2171
            self.inout_terminal()
            self.state = 2172
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2173
            self.inout_terminal()
            self.state = 2174
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2175
            self.enable_terminal()
            self.state = 2176
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_input_terminalsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def input_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_terminalContext,0)


        def comma_input_terminal_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_input_terminal_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_input_terminals

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_input_terminals" ):
                listener.enterList_of_input_terminals(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_input_terminals" ):
                listener.exitList_of_input_terminals(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_input_terminals" ):
                return visitor.visitList_of_input_terminals(self)
            else:
                return visitor.visitChildren(self)




    def list_of_input_terminals(self):

        localctx = SysVerilogHDLParser.List_of_input_terminalsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 496, self.RULE_list_of_input_terminals)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2178
            self.input_terminal()
            self.state = 2179
            self.comma_input_terminal_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_output_terminalsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def output_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_terminalContext,0)


        def comma_output_terminal_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_output_terminal_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_output_terminals

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_output_terminals" ):
                listener.enterList_of_output_terminals(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_output_terminals" ):
                listener.exitList_of_output_terminals(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_output_terminals" ):
                return visitor.visitList_of_output_terminals(self)
            else:
                return visitor.visitChildren(self)




    def list_of_output_terminals(self):

        localctx = SysVerilogHDLParser.List_of_output_terminalsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 498, self.RULE_list_of_output_terminals)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2181
            self.output_terminal()
            self.state = 2182
            self.comma_output_terminal_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_input_terminal_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_input_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_input_terminalContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_input_terminalContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_input_terminal_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_input_terminal_star" ):
                listener.enterComma_input_terminal_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_input_terminal_star" ):
                listener.exitComma_input_terminal_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_input_terminal_star" ):
                return visitor.visitComma_input_terminal_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_input_terminal_star(self):

        localctx = SysVerilogHDLParser.Comma_input_terminal_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 500, self.RULE_comma_input_terminal_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2187
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2184
                self.comma_input_terminal()
                self.state = 2189
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_output_terminal_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_output_terminal(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_output_terminalContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_output_terminalContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_output_terminal_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_output_terminal_star" ):
                listener.enterComma_output_terminal_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_output_terminal_star" ):
                listener.exitComma_output_terminal_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_output_terminal_star" ):
                return visitor.visitComma_output_terminal_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_output_terminal_star(self):

        localctx = SysVerilogHDLParser.Comma_output_terminal_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 502, self.RULE_comma_output_terminal_star)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2193
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,158,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 2190
                    self.comma_output_terminal() 
                self.state = 2195
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,158,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_input_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def input_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Input_terminalContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_input_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_input_terminal" ):
                listener.enterComma_input_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_input_terminal" ):
                listener.exitComma_input_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_input_terminal" ):
                return visitor.visitComma_input_terminal(self)
            else:
                return visitor.visitChildren(self)




    def comma_input_terminal(self):

        localctx = SysVerilogHDLParser.Comma_input_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 504, self.RULE_comma_input_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2196
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2197
            self.input_terminal()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_output_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def output_terminal(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Output_terminalContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_output_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_output_terminal" ):
                listener.enterComma_output_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_output_terminal" ):
                listener.exitComma_output_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_output_terminal" ):
                return visitor.visitComma_output_terminal(self)
            else:
                return visitor.visitChildren(self)




    def comma_output_terminal(self):

        localctx = SysVerilogHDLParser.Comma_output_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 506, self.RULE_comma_output_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2199
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2200
            self.output_terminal()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Enable_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_enable_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEnable_terminal" ):
                listener.enterEnable_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEnable_terminal" ):
                listener.exitEnable_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEnable_terminal" ):
                return visitor.visitEnable_terminal(self)
            else:
                return visitor.visitChildren(self)




    def enable_terminal(self):

        localctx = SysVerilogHDLParser.Enable_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 508, self.RULE_enable_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2202
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Input_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_input_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInput_terminal" ):
                listener.enterInput_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInput_terminal" ):
                listener.exitInput_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInput_terminal" ):
                return visitor.visitInput_terminal(self)
            else:
                return visitor.visitChildren(self)




    def input_terminal(self):

        localctx = SysVerilogHDLParser.Input_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 510, self.RULE_input_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2204
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Inout_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_inout_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInout_terminal" ):
                listener.enterInout_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInout_terminal" ):
                listener.exitInout_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInout_terminal" ):
                return visitor.visitInout_terminal(self)
            else:
                return visitor.visitChildren(self)




    def inout_terminal(self):

        localctx = SysVerilogHDLParser.Inout_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 512, self.RULE_inout_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2206
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ncontrol_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_ncontrol_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNcontrol_terminal" ):
                listener.enterNcontrol_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNcontrol_terminal" ):
                listener.exitNcontrol_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNcontrol_terminal" ):
                return visitor.visitNcontrol_terminal(self)
            else:
                return visitor.visitChildren(self)




    def ncontrol_terminal(self):

        localctx = SysVerilogHDLParser.Ncontrol_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 514, self.RULE_ncontrol_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2208
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Output_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_output_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOutput_terminal" ):
                listener.enterOutput_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOutput_terminal" ):
                listener.exitOutput_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOutput_terminal" ):
                return visitor.visitOutput_terminal(self)
            else:
                return visitor.visitChildren(self)




    def output_terminal(self):

        localctx = SysVerilogHDLParser.Output_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 516, self.RULE_output_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2210
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Pcontrol_terminalContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_pcontrol_terminal

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPcontrol_terminal" ):
                listener.enterPcontrol_terminal(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPcontrol_terminal" ):
                listener.exitPcontrol_terminal(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPcontrol_terminal" ):
                return visitor.visitPcontrol_terminal(self)
            else:
                return visitor.visitChildren(self)




    def pcontrol_terminal(self):

        localctx = SysVerilogHDLParser.Pcontrol_terminalContext(self, self._ctx, self.state)
        self.enterRule(localctx, 518, self.RULE_pcontrol_terminal)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2212
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Statement_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def statement_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Statement_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_statement_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement_star" ):
                listener.enterStatement_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement_star" ):
                listener.exitStatement_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement_star" ):
                return visitor.visitStatement_star(self)
            else:
                return visitor.visitChildren(self)




    def statement_star(self):

        localctx = SysVerilogHDLParser.Statement_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 520, self.RULE_statement_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2217
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__0) | (1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form) | (1 << SysVerilogHDLParser.Assert) | (1 << SysVerilogHDLParser.Assign) | (1 << SysVerilogHDLParser.Automatic) | (1 << SysVerilogHDLParser.Begin) | (1 << SysVerilogHDLParser.Bit) | (1 << SysVerilogHDLParser.Byte) | (1 << SysVerilogHDLParser.Case_keyword) | (1 << SysVerilogHDLParser.Casez))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SysVerilogHDLParser.Casex - 64)) | (1 << (SysVerilogHDLParser.Const - 64)) | (1 << (SysVerilogHDLParser.Deassign - 64)) | (1 << (SysVerilogHDLParser.Disable - 64)) | (1 << (SysVerilogHDLParser.Do - 64)) | (1 << (SysVerilogHDLParser.For - 64)) | (1 << (SysVerilogHDLParser.Force - 64)) | (1 << (SysVerilogHDLParser.Forever - 64)) | (1 << (SysVerilogHDLParser.Fork - 64)) | (1 << (SysVerilogHDLParser.Genvar - 64)) | (1 << (SysVerilogHDLParser.If - 64)) | (1 << (SysVerilogHDLParser.Int - 64)) | (1 << (SysVerilogHDLParser.Integer - 64)) | (1 << (SysVerilogHDLParser.Logic - 64)))) != 0) or ((((_la - 150)) & ~0x3f) == 0 and ((1 << (_la - 150)) & ((1 << (SysVerilogHDLParser.Reg - 150)) | (1 << (SysVerilogHDLParser.Release - 150)) | (1 << (SysVerilogHDLParser.Repeat - 150)) | (1 << (SysVerilogHDLParser.Return - 150)) | (1 << (SysVerilogHDLParser.Signed - 150)) | (1 << (SysVerilogHDLParser.Static - 150)) | (1 << (SysVerilogHDLParser.Unsigned - 150)) | (1 << (SysVerilogHDLParser.Wait - 150)) | (1 << (SysVerilogHDLParser.While - 150)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 150)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 150)) | (1 << (SysVerilogHDLParser.Simple_identifier - 150)) | (1 << (SysVerilogHDLParser.String_literal - 150)) | (1 << (SysVerilogHDLParser.At - 150)) | (1 << (SysVerilogHDLParser.Dash_right_angle - 150)))) != 0) or ((((_la - 216)) & ~0x3f) == 0 and ((1 << (_la - 216)) & ((1 << (SysVerilogHDLParser.Hash - 216)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 216)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 216)) | (1 << (SysVerilogHDLParser.Quote - 216)) | (1 << (SysVerilogHDLParser.Semicolon - 216)) | (1 << (SysVerilogHDLParser.Tilde - 216)))) != 0):
                self.state = 2214
                self.statement_semicolon()
                self.state = 2219
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Statement_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.StatementContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def null_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Null_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_statement_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement_semicolon" ):
                listener.enterStatement_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement_semicolon" ):
                listener.exitStatement_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement_semicolon" ):
                return visitor.visitStatement_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def statement_semicolon(self):

        localctx = SysVerilogHDLParser.Statement_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 522, self.RULE_statement_semicolon)
        try:
            self.state = 2226
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.T__1, SysVerilogHDLParser.T__2, SysVerilogHDLParser.T__3, SysVerilogHDLParser.T__4, SysVerilogHDLParser.T__5, SysVerilogHDLParser.T__6, SysVerilogHDLParser.T__7, SysVerilogHDLParser.T__8, SysVerilogHDLParser.T__9, SysVerilogHDLParser.T__10, SysVerilogHDLParser.T__26, SysVerilogHDLParser.T__27, SysVerilogHDLParser.Binary_number, SysVerilogHDLParser.Decimal_number, SysVerilogHDLParser.Fixed_point_number, SysVerilogHDLParser.Hex_number, SysVerilogHDLParser.Octal_number, SysVerilogHDLParser.Real_exp_form, SysVerilogHDLParser.Assert, SysVerilogHDLParser.Assign, SysVerilogHDLParser.Automatic, SysVerilogHDLParser.Begin, SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte, SysVerilogHDLParser.Case_keyword, SysVerilogHDLParser.Casez, SysVerilogHDLParser.Casex, SysVerilogHDLParser.Const, SysVerilogHDLParser.Deassign, SysVerilogHDLParser.Disable, SysVerilogHDLParser.Do, SysVerilogHDLParser.For, SysVerilogHDLParser.Force, SysVerilogHDLParser.Forever, SysVerilogHDLParser.Fork, SysVerilogHDLParser.Genvar, SysVerilogHDLParser.If, SysVerilogHDLParser.Int, SysVerilogHDLParser.Integer, SysVerilogHDLParser.Logic, SysVerilogHDLParser.Reg, SysVerilogHDLParser.Release, SysVerilogHDLParser.Repeat, SysVerilogHDLParser.Return, SysVerilogHDLParser.Signed, SysVerilogHDLParser.Static, SysVerilogHDLParser.Unsigned, SysVerilogHDLParser.Wait, SysVerilogHDLParser.While, SysVerilogHDLParser.Dollar_Identifier, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier, SysVerilogHDLParser.String_literal, SysVerilogHDLParser.At, SysVerilogHDLParser.Dash_right_angle, SysVerilogHDLParser.Hash, SysVerilogHDLParser.Left_curly_bracket, SysVerilogHDLParser.Open_parenthesis, SysVerilogHDLParser.Quote, SysVerilogHDLParser.Tilde]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2220
                self.attribute_instance_star()
                self.state = 2221
                self.statement()
                self.state = 2223
                self._errHandler.sync(self)
                la_ = self._interp.adaptivePredict(self._input,160,self._ctx)
                if la_ == 1:
                    self.state = 2222
                    self.semicolon()


                pass
            elif token in [SysVerilogHDLParser.T__0, SysVerilogHDLParser.Semicolon]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2225
                self.null_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class StatementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def assignment_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Assignment_statementContext,0)


        def flow_control_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Flow_control_statementContext,0)


        def block_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_statementContext,0)


        def task_call_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_call_statementContext,0)


        def event_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_statementContext,0)


        def procedural_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Procedural_statementContext,0)


        def expression_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Expression_statementContext,0)


        def subroutine_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Subroutine_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStatement" ):
                listener.enterStatement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStatement" ):
                listener.exitStatement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStatement" ):
                return visitor.visitStatement(self)
            else:
                return visitor.visitChildren(self)




    def statement(self):

        localctx = SysVerilogHDLParser.StatementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 524, self.RULE_statement)
        try:
            self.state = 2236
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,162,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2228
                self.assignment_statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2229
                self.flow_control_statement()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2230
                self.block_statement()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2231
                self.task_call_statement()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2232
                self.event_statement()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2233
                self.procedural_statement()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2234
                self.expression_statement()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2235
                self.subroutine_statement()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assignment_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def blocking_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Blocking_assignmentContext,0)


        def nonblocking_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Nonblocking_assignmentContext,0)


        def prefix_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Prefix_assignmentContext,0)


        def postfix_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Postfix_assignmentContext,0)


        def operator_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Operator_assignmentContext,0)


        def declarative_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Declarative_assignmentContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_assignment_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssignment_statement" ):
                listener.enterAssignment_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssignment_statement" ):
                listener.exitAssignment_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssignment_statement" ):
                return visitor.visitAssignment_statement(self)
            else:
                return visitor.visitChildren(self)




    def assignment_statement(self):

        localctx = SysVerilogHDLParser.Assignment_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 526, self.RULE_assignment_statement)
        try:
            self.state = 2244
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,163,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2238
                self.blocking_assignment()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2239
                self.nonblocking_assignment()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2240
                self.prefix_assignment()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2241
                self.postfix_assignment()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2242
                self.operator_assignment()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2243
                self.declarative_assignment()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Flow_control_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def case_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Case_statementContext,0)


        def conditional_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Conditional_statementContext,0)


        def loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_flow_control_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFlow_control_statement" ):
                listener.enterFlow_control_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFlow_control_statement" ):
                listener.exitFlow_control_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFlow_control_statement" ):
                return visitor.visitFlow_control_statement(self)
            else:
                return visitor.visitChildren(self)




    def flow_control_statement(self):

        localctx = SysVerilogHDLParser.Flow_control_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 528, self.RULE_flow_control_statement)
        try:
            self.state = 2249
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Case_keyword, SysVerilogHDLParser.Casez, SysVerilogHDLParser.Casex]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2246
                self.case_statement()
                pass
            elif token in [SysVerilogHDLParser.If]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2247
                self.conditional_statement()
                pass
            elif token in [SysVerilogHDLParser.Do, SysVerilogHDLParser.For, SysVerilogHDLParser.Forever, SysVerilogHDLParser.Repeat, SysVerilogHDLParser.While]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2248
                self.loop_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def par_block(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Par_blockContext,0)


        def seq_block(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Seq_blockContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_block_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_statement" ):
                listener.enterBlock_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_statement" ):
                listener.exitBlock_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_statement" ):
                return visitor.visitBlock_statement(self)
            else:
                return visitor.visitChildren(self)




    def block_statement(self):

        localctx = SysVerilogHDLParser.Block_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 530, self.RULE_block_statement)
        try:
            self.state = 2253
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Fork]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2251
                self.par_block()
                pass
            elif token in [SysVerilogHDLParser.Begin]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2252
                self.seq_block()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_call_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def task_enable(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_enableContext,0)


        def system_task_enable(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.System_task_enableContext,0)


        def disable_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Disable_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_call_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_call_statement" ):
                listener.enterTask_call_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_call_statement" ):
                listener.exitTask_call_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_call_statement" ):
                return visitor.visitTask_call_statement(self)
            else:
                return visitor.visitChildren(self)




    def task_call_statement(self):

        localctx = SysVerilogHDLParser.Task_call_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 532, self.RULE_task_call_statement)
        try:
            self.state = 2258
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2255
                self.task_enable()
                pass
            elif token in [SysVerilogHDLParser.Dollar_Identifier]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2256
                self.system_task_enable()
                pass
            elif token in [SysVerilogHDLParser.Disable]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2257
                self.disable_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def event_trigger(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_triggerContext,0)


        def wait_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Wait_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_statement" ):
                listener.enterEvent_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_statement" ):
                listener.exitEvent_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_statement" ):
                return visitor.visitEvent_statement(self)
            else:
                return visitor.visitChildren(self)




    def event_statement(self):

        localctx = SysVerilogHDLParser.Event_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 534, self.RULE_event_statement)
        try:
            self.state = 2262
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Dash_right_angle]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2260
                self.event_trigger()
                pass
            elif token in [SysVerilogHDLParser.Wait]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2261
                self.wait_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def procedural_continuous_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Procedural_continuous_assignmentsContext,0)


        def procedural_timing_control_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Procedural_timing_control_statementContext,0)


        def procedural_assertion_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Procedural_assertion_statementContext,0)


        def property_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Property_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_procedural_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_statement" ):
                listener.enterProcedural_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_statement" ):
                listener.exitProcedural_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_statement" ):
                return visitor.visitProcedural_statement(self)
            else:
                return visitor.visitChildren(self)




    def procedural_statement(self):

        localctx = SysVerilogHDLParser.Procedural_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 536, self.RULE_procedural_statement)
        try:
            self.state = 2268
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Assign, SysVerilogHDLParser.Deassign, SysVerilogHDLParser.Force, SysVerilogHDLParser.Release]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2264
                self.procedural_continuous_assignments()
                pass
            elif token in [SysVerilogHDLParser.Repeat, SysVerilogHDLParser.At, SysVerilogHDLParser.Hash]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2265
                self.procedural_timing_control_statement()
                pass
            elif token in [SysVerilogHDLParser.Assert, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2266
                self.procedural_assertion_statement()
                pass
            elif token in [SysVerilogHDLParser.Disable]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2267
                self.property_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Expression_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_expression_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExpression_statement" ):
                listener.enterExpression_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExpression_statement" ):
                listener.exitExpression_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExpression_statement" ):
                return visitor.visitExpression_statement(self)
            else:
                return visitor.visitChildren(self)




    def expression_statement(self):

        localctx = SysVerilogHDLParser.Expression_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 538, self.RULE_expression_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2270
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Subroutine_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def return_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Return_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_subroutine_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSubroutine_statement" ):
                listener.enterSubroutine_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSubroutine_statement" ):
                listener.exitSubroutine_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSubroutine_statement" ):
                return visitor.visitSubroutine_statement(self)
            else:
                return visitor.visitChildren(self)




    def subroutine_statement(self):

        localctx = SysVerilogHDLParser.Subroutine_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 540, self.RULE_subroutine_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2272
            self.return_statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Return_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Return(self):
            return self.getToken(SysVerilogHDLParser.Return, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_return_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReturn_statement" ):
                listener.enterReturn_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReturn_statement" ):
                listener.exitReturn_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReturn_statement" ):
                return visitor.visitReturn_statement(self)
            else:
                return visitor.visitChildren(self)




    def return_statement(self):

        localctx = SysVerilogHDLParser.Return_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 542, self.RULE_return_statement)
        try:
            self.state = 2277
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,169,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2274
                self.match(SysVerilogHDLParser.Return)
                self.state = 2275
                self.expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2276
                self.match(SysVerilogHDLParser.Return)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Null_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_null_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNull_statement" ):
                listener.enterNull_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNull_statement" ):
                listener.exitNull_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNull_statement" ):
                return visitor.visitNull_statement(self)
            else:
                return visitor.visitChildren(self)




    def null_statement(self):

        localctx = SysVerilogHDLParser.Null_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 544, self.RULE_null_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2279
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_continuous_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def assign_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Assign_statementContext,0)


        def deassign_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Deassign_statementContext,0)


        def force_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Force_statementContext,0)


        def release_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Release_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_procedural_continuous_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_continuous_assignments" ):
                listener.enterProcedural_continuous_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_continuous_assignments" ):
                listener.exitProcedural_continuous_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_continuous_assignments" ):
                return visitor.visitProcedural_continuous_assignments(self)
            else:
                return visitor.visitChildren(self)




    def procedural_continuous_assignments(self):

        localctx = SysVerilogHDLParser.Procedural_continuous_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 546, self.RULE_procedural_continuous_assignments)
        try:
            self.state = 2285
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Assign]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2281
                self.assign_statement()
                pass
            elif token in [SysVerilogHDLParser.Deassign]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2282
                self.deassign_statement()
                pass
            elif token in [SysVerilogHDLParser.Force]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2283
                self.force_statement()
                pass
            elif token in [SysVerilogHDLParser.Release]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2284
                self.release_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assign_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Assign(self):
            return self.getToken(SysVerilogHDLParser.Assign, 0)

        def assignment_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Assignment_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_assign_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssign_statement" ):
                listener.enterAssign_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssign_statement" ):
                listener.exitAssign_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssign_statement" ):
                return visitor.visitAssign_statement(self)
            else:
                return visitor.visitChildren(self)




    def assign_statement(self):

        localctx = SysVerilogHDLParser.Assign_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 548, self.RULE_assign_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2287
            self.match(SysVerilogHDLParser.Assign)
            self.state = 2288
            self.assignment_statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Deassign_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Deassign(self):
            return self.getToken(SysVerilogHDLParser.Deassign, 0)

        def variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_lvalueContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_deassign_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDeassign_statement" ):
                listener.enterDeassign_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDeassign_statement" ):
                listener.exitDeassign_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDeassign_statement" ):
                return visitor.visitDeassign_statement(self)
            else:
                return visitor.visitChildren(self)




    def deassign_statement(self):

        localctx = SysVerilogHDLParser.Deassign_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 550, self.RULE_deassign_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2290
            self.match(SysVerilogHDLParser.Deassign)
            self.state = 2291
            self.variable_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Force_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Force(self):
            return self.getToken(SysVerilogHDLParser.Force, 0)

        def assignment_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Assignment_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_force_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterForce_statement" ):
                listener.enterForce_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitForce_statement" ):
                listener.exitForce_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitForce_statement" ):
                return visitor.visitForce_statement(self)
            else:
                return visitor.visitChildren(self)




    def force_statement(self):

        localctx = SysVerilogHDLParser.Force_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 552, self.RULE_force_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2293
            self.match(SysVerilogHDLParser.Force)
            self.state = 2294
            self.assignment_statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Release_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Release(self):
            return self.getToken(SysVerilogHDLParser.Release, 0)

        def variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_lvalueContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_release_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRelease_statement" ):
                listener.enterRelease_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRelease_statement" ):
                listener.exitRelease_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRelease_statement" ):
                return visitor.visitRelease_statement(self)
            else:
                return visitor.visitChildren(self)




    def release_statement(self):

        localctx = SysVerilogHDLParser.Release_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 554, self.RULE_release_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2296
            self.match(SysVerilogHDLParser.Release)
            self.state = 2297
            self.variable_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_timing_control_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_or_event_control(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Delay_or_event_controlContext,0)


        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_procedural_timing_control_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_timing_control_statement" ):
                listener.enterProcedural_timing_control_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_timing_control_statement" ):
                listener.exitProcedural_timing_control_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_timing_control_statement" ):
                return visitor.visitProcedural_timing_control_statement(self)
            else:
                return visitor.visitChildren(self)




    def procedural_timing_control_statement(self):

        localctx = SysVerilogHDLParser.Procedural_timing_control_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 556, self.RULE_procedural_timing_control_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2299
            self.delay_or_event_control()
            self.state = 2300
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def disable_condition_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Disable_condition_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_property_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_statement" ):
                listener.enterProperty_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_statement" ):
                listener.exitProperty_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_statement" ):
                return visitor.visitProperty_statement(self)
            else:
                return visitor.visitChildren(self)




    def property_statement(self):

        localctx = SysVerilogHDLParser.Property_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 558, self.RULE_property_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2302
            self.disable_condition_statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Disable_condition_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Disable(self):
            return self.getToken(SysVerilogHDLParser.Disable, 0)

        def Iff(self):
            return self.getToken(SysVerilogHDLParser.Iff, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def property_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Property_expressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_disable_condition_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDisable_condition_statement" ):
                listener.enterDisable_condition_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDisable_condition_statement" ):
                listener.exitDisable_condition_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDisable_condition_statement" ):
                return visitor.visitDisable_condition_statement(self)
            else:
                return visitor.visitChildren(self)




    def disable_condition_statement(self):

        localctx = SysVerilogHDLParser.Disable_condition_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 560, self.RULE_disable_condition_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2304
            self.match(SysVerilogHDLParser.Disable)
            self.state = 2305
            self.match(SysVerilogHDLParser.Iff)
            self.state = 2306
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2307
            self.expression()
            self.state = 2308
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2309
            self.property_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Property_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_property_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProperty_expression" ):
                listener.enterProperty_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProperty_expression" ):
                listener.exitProperty_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProperty_expression" ):
                return visitor.visitProperty_expression(self)
            else:
                return visitor.visitChildren(self)




    def property_expression(self):

        localctx = SysVerilogHDLParser.Property_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 562, self.RULE_property_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2311
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Procedural_assertion_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def assert_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Assert_statementContext,0)


        def assert_else_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Assert_else_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_procedural_assertion_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterProcedural_assertion_statement" ):
                listener.enterProcedural_assertion_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitProcedural_assertion_statement" ):
                listener.exitProcedural_assertion_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitProcedural_assertion_statement" ):
                return visitor.visitProcedural_assertion_statement(self)
            else:
                return visitor.visitChildren(self)




    def procedural_assertion_statement(self):

        localctx = SysVerilogHDLParser.Procedural_assertion_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 564, self.RULE_procedural_assertion_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2313
            self.assert_statement()
            self.state = 2315
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,171,self._ctx)
            if la_ == 1:
                self.state = 2314
                self.assert_else_statement()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assert_else_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Else(self):
            return self.getToken(SysVerilogHDLParser.Else, 0)

        def statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.StatementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_assert_else_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssert_else_statement" ):
                listener.enterAssert_else_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssert_else_statement" ):
                listener.exitAssert_else_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssert_else_statement" ):
                return visitor.visitAssert_else_statement(self)
            else:
                return visitor.visitChildren(self)




    def assert_else_statement(self):

        localctx = SysVerilogHDLParser.Assert_else_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 566, self.RULE_assert_else_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2317
            self.match(SysVerilogHDLParser.Else)
            self.state = 2318
            self.statement()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Assert_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Assert(self):
            return self.getToken(SysVerilogHDLParser.Assert, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_assert_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAssert_statement" ):
                listener.enterAssert_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAssert_statement" ):
                listener.exitAssert_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAssert_statement" ):
                return visitor.visitAssert_statement(self)
            else:
                return visitor.visitChildren(self)




    def assert_statement(self):

        localctx = SysVerilogHDLParser.Assert_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 568, self.RULE_assert_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2323
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier:
                self.state = 2320
                self.hierarchical_identifier()
                self.state = 2321
                self.match(SysVerilogHDLParser.Colon)


            self.state = 2325
            self.match(SysVerilogHDLParser.Assert)
            self.state = 2326
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2327
            self.expression()
            self.state = 2328
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_task_enableContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def system_task_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.System_task_identifierContext,0)


        def task_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_system_task_enable

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_task_enable" ):
                listener.enterSystem_task_enable(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_task_enable" ):
                listener.exitSystem_task_enable(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_task_enable" ):
                return visitor.visitSystem_task_enable(self)
            else:
                return visitor.visitChildren(self)




    def system_task_enable(self):

        localctx = SysVerilogHDLParser.System_task_enableContext(self, self._ctx, self.state)
        self.enterRule(localctx, 570, self.RULE_system_task_enable)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2330
            self.system_task_identifier()
            self.state = 2332
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,173,self._ctx)
            if la_ == 1:
                self.state = 2331
                self.task_interface_assignments()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_task_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Dollar_Identifier(self):
            return self.getToken(SysVerilogHDLParser.Dollar_Identifier, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_system_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_task_identifier" ):
                listener.enterSystem_task_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_task_identifier" ):
                listener.exitSystem_task_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_task_identifier" ):
                return visitor.visitSystem_task_identifier(self)
            else:
                return visitor.visitChildren(self)




    def system_task_identifier(self):

        localctx = SysVerilogHDLParser.System_task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 572, self.RULE_system_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2334
            self.match(SysVerilogHDLParser.Dollar_Identifier)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_interface_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def list_of_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_interface_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_interface_assignments" ):
                listener.enterTask_interface_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_interface_assignments" ):
                listener.exitTask_interface_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_interface_assignments" ):
                return visitor.visitTask_interface_assignments(self)
            else:
                return visitor.visitChildren(self)




    def task_interface_assignments(self):

        localctx = SysVerilogHDLParser.Task_interface_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 574, self.RULE_task_interface_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2336
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2338
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form))) != 0) or _la==SysVerilogHDLParser.Int or _la==SysVerilogHDLParser.Signed or ((((_la - 188)) & ~0x3f) == 0 and ((1 << (_la - 188)) & ((1 << (SysVerilogHDLParser.Unsigned - 188)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 188)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 188)) | (1 << (SysVerilogHDLParser.Simple_identifier - 188)) | (1 << (SysVerilogHDLParser.String_literal - 188)) | (1 << (SysVerilogHDLParser.Dot - 188)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 188)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 188)) | (1 << (SysVerilogHDLParser.Quote - 188)) | (1 << (SysVerilogHDLParser.Tilde - 188)))) != 0):
                self.state = 2337
                self.list_of_interface_assignments()


            self.state = 2340
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Task_enableContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_task_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_task_identifierContext,0)


        def task_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Task_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_task_enable

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTask_enable" ):
                listener.enterTask_enable(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTask_enable" ):
                listener.exitTask_enable(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTask_enable" ):
                return visitor.visitTask_enable(self)
            else:
                return visitor.visitChildren(self)




    def task_enable(self):

        localctx = SysVerilogHDLParser.Task_enableContext(self, self._ctx, self.state)
        self.enterRule(localctx, 576, self.RULE_task_enable)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2342
            self.hierarchical_task_identifier()
            self.state = 2344
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,175,self._ctx)
            if la_ == 1:
                self.state = 2343
                self.task_interface_assignments()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_task_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_task_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_task_identifier" ):
                listener.enterHierarchical_task_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_task_identifier" ):
                listener.exitHierarchical_task_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_task_identifier" ):
                return visitor.visitHierarchical_task_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_task_identifier(self):

        localctx = SysVerilogHDLParser.Hierarchical_task_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 578, self.RULE_hierarchical_task_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2346
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Disable_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Disable(self):
            return self.getToken(SysVerilogHDLParser.Disable, 0)

        def hierarchical_task_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_task_identifierContext,0)


        def hierarchical_block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_block_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_disable_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDisable_statement" ):
                listener.enterDisable_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDisable_statement" ):
                listener.exitDisable_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDisable_statement" ):
                return visitor.visitDisable_statement(self)
            else:
                return visitor.visitChildren(self)




    def disable_statement(self):

        localctx = SysVerilogHDLParser.Disable_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 580, self.RULE_disable_statement)
        try:
            self.state = 2352
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,176,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2348
                self.match(SysVerilogHDLParser.Disable)
                self.state = 2349
                self.hierarchical_task_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2350
                self.match(SysVerilogHDLParser.Disable)
                self.state = 2351
                self.hierarchical_block_identifier()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_block_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_block_identifier" ):
                listener.enterHierarchical_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_block_identifier" ):
                listener.exitHierarchical_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_block_identifier" ):
                return visitor.visitHierarchical_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_block_identifier(self):

        localctx = SysVerilogHDLParser.Hierarchical_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 582, self.RULE_hierarchical_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2354
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_lvalueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_variable_lvalueContext,0)


        def variable_concatenation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_concatenationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_lvalue" ):
                listener.enterVariable_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_lvalue" ):
                listener.exitVariable_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_lvalue" ):
                return visitor.visitVariable_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def variable_lvalue(self):

        localctx = SysVerilogHDLParser.Variable_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 584, self.RULE_variable_lvalue)
        try:
            self.state = 2358
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2356
                self.hierarchical_variable_lvalue()
                pass
            elif token in [SysVerilogHDLParser.Left_curly_bracket]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2357
                self.variable_concatenation()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_variable_lvalueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def primary_hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Primary_hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_variable_lvalue

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_variable_lvalue" ):
                listener.enterHierarchical_variable_lvalue(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_variable_lvalue" ):
                listener.exitHierarchical_variable_lvalue(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_variable_lvalue" ):
                return visitor.visitHierarchical_variable_lvalue(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_variable_lvalue(self):

        localctx = SysVerilogHDLParser.Hierarchical_variable_lvalueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 586, self.RULE_hierarchical_variable_lvalue)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2360
            self.primary_hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_concatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Left_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Left_curly_bracket, 0)

        def variable_concatenation_value(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_concatenation_valueContext,0)


        def comma_vcv_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_vcv_starContext,0)


        def Right_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Right_curly_bracket, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_concatenation" ):
                listener.enterVariable_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_concatenation" ):
                listener.exitVariable_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_concatenation" ):
                return visitor.visitVariable_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def variable_concatenation(self):

        localctx = SysVerilogHDLParser.Variable_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 588, self.RULE_variable_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2362
            self.match(SysVerilogHDLParser.Left_curly_bracket)
            self.state = 2363
            self.variable_concatenation_value()
            self.state = 2364
            self.comma_vcv_star()
            self.state = 2365
            self.match(SysVerilogHDLParser.Right_curly_bracket)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_concatenation_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def primary_hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Primary_hierarchical_identifierContext,0)


        def variable_concatenation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_concatenationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_concatenation_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_concatenation_value" ):
                listener.enterVariable_concatenation_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_concatenation_value" ):
                listener.exitVariable_concatenation_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_concatenation_value" ):
                return visitor.visitVariable_concatenation_value(self)
            else:
                return visitor.visitChildren(self)




    def variable_concatenation_value(self):

        localctx = SysVerilogHDLParser.Variable_concatenation_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 590, self.RULE_variable_concatenation_value)
        try:
            self.state = 2369
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2367
                self.primary_hierarchical_identifier()
                pass
            elif token in [SysVerilogHDLParser.Left_curly_bracket]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2368
                self.variable_concatenation()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_vcv_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def variable_concatenation_value(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Variable_concatenation_valueContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Variable_concatenation_valueContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_vcv_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_vcv_star" ):
                listener.enterComma_vcv_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_vcv_star" ):
                listener.exitComma_vcv_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_vcv_star" ):
                return visitor.visitComma_vcv_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_vcv_star(self):

        localctx = SysVerilogHDLParser.Comma_vcv_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 592, self.RULE_comma_vcv_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2375
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2371
                self.match(SysVerilogHDLParser.Comma)
                self.state = 2372
                self.variable_concatenation_value()
                self.state = 2377
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Blocking_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_lvalueContext,0)


        def Equal(self):
            return self.getToken(SysVerilogHDLParser.Equal, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def delay_or_event_control(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Delay_or_event_controlContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_blocking_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlocking_assignment" ):
                listener.enterBlocking_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlocking_assignment" ):
                listener.exitBlocking_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlocking_assignment" ):
                return visitor.visitBlocking_assignment(self)
            else:
                return visitor.visitChildren(self)




    def blocking_assignment(self):

        localctx = SysVerilogHDLParser.Blocking_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 594, self.RULE_blocking_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2378
            self.variable_lvalue()
            self.state = 2379
            self.match(SysVerilogHDLParser.Equal)
            self.state = 2381
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Repeat or _la==SysVerilogHDLParser.At or _la==SysVerilogHDLParser.Hash:
                self.state = 2380
                self.delay_or_event_control()


            self.state = 2383
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Nonblocking_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_lvalueContext,0)


        def Left_angle_equals(self):
            return self.getToken(SysVerilogHDLParser.Left_angle_equals, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def delay_or_event_control(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Delay_or_event_controlContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_nonblocking_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNonblocking_assignment" ):
                listener.enterNonblocking_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNonblocking_assignment" ):
                listener.exitNonblocking_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNonblocking_assignment" ):
                return visitor.visitNonblocking_assignment(self)
            else:
                return visitor.visitChildren(self)




    def nonblocking_assignment(self):

        localctx = SysVerilogHDLParser.Nonblocking_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 596, self.RULE_nonblocking_assignment)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2385
            self.variable_lvalue()
            self.state = 2386
            self.match(SysVerilogHDLParser.Left_angle_equals)
            self.state = 2388
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Repeat or _la==SysVerilogHDLParser.At or _la==SysVerilogHDLParser.Hash:
                self.state = 2387
                self.delay_or_event_control()


            self.state = 2390
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Prefix_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def unary_assign_operator(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Unary_assign_operatorContext,0)


        def variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_lvalueContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_prefix_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrefix_assignment" ):
                listener.enterPrefix_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrefix_assignment" ):
                listener.exitPrefix_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrefix_assignment" ):
                return visitor.visitPrefix_assignment(self)
            else:
                return visitor.visitChildren(self)




    def prefix_assignment(self):

        localctx = SysVerilogHDLParser.Prefix_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 598, self.RULE_prefix_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2392
            self.unary_assign_operator()
            self.state = 2393
            self.variable_lvalue()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Postfix_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_lvalueContext,0)


        def unary_assign_operator(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Unary_assign_operatorContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_postfix_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPostfix_assignment" ):
                listener.enterPostfix_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPostfix_assignment" ):
                listener.exitPostfix_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPostfix_assignment" ):
                return visitor.visitPostfix_assignment(self)
            else:
                return visitor.visitChildren(self)




    def postfix_assignment(self):

        localctx = SysVerilogHDLParser.Postfix_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 600, self.RULE_postfix_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2395
            self.variable_lvalue()
            self.state = 2396
            self.unary_assign_operator()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Operator_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_lvalueContext,0)


        def binary_assign_operator(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Binary_assign_operatorContext,0)


        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_operator_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOperator_assignment" ):
                listener.enterOperator_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOperator_assignment" ):
                listener.exitOperator_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOperator_assignment" ):
                return visitor.visitOperator_assignment(self)
            else:
                return visitor.visitChildren(self)




    def operator_assignment(self):

        localctx = SysVerilogHDLParser.Operator_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 602, self.RULE_operator_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2398
            self.variable_lvalue()
            self.state = 2399
            self.binary_assign_operator()
            self.state = 2400
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Declarative_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def reg_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Reg_declarationContext,0)


        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def bits_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def int_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Int_declarationContext,0)


        def genvar_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Genvar_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_declarative_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDeclarative_assignment" ):
                listener.enterDeclarative_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDeclarative_assignment" ):
                listener.exitDeclarative_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDeclarative_assignment" ):
                return visitor.visitDeclarative_assignment(self)
            else:
                return visitor.visitChildren(self)




    def declarative_assignment(self):

        localctx = SysVerilogHDLParser.Declarative_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 604, self.RULE_declarative_assignment)
        try:
            self.state = 2408
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,182,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2402
                self.reg_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2403
                self.logic_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2404
                self.bits_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2405
                self.integer_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2406
                self.int_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2407
                self.genvar_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_or_event_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def delay_control(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Delay_controlContext,0)


        def event_control(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_controlContext,0)


        def repeat_event_control(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Repeat_event_controlContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_delay_or_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_or_event_control" ):
                listener.enterDelay_or_event_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_or_event_control" ):
                listener.exitDelay_or_event_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_or_event_control" ):
                return visitor.visitDelay_or_event_control(self)
            else:
                return visitor.visitChildren(self)




    def delay_or_event_control(self):

        localctx = SysVerilogHDLParser.Delay_or_event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 606, self.RULE_delay_or_event_control)
        try:
            self.state = 2413
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Hash]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2410
                self.delay_control()
                pass
            elif token in [SysVerilogHDLParser.At]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2411
                self.event_control()
                pass
            elif token in [SysVerilogHDLParser.Repeat]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2412
                self.repeat_event_control()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Delay_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Hash(self):
            return self.getToken(SysVerilogHDLParser.Hash, 0)

        def delay_value(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Delay_valueContext,0)


        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def mintypmax_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Mintypmax_expressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_delay_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDelay_control" ):
                listener.enterDelay_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDelay_control" ):
                listener.exitDelay_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDelay_control" ):
                return visitor.visitDelay_control(self)
            else:
                return visitor.visitChildren(self)




    def delay_control(self):

        localctx = SysVerilogHDLParser.Delay_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 608, self.RULE_delay_control)
        try:
            self.state = 2427
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,184,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2415
                self.match(SysVerilogHDLParser.Hash)
                self.state = 2416
                self.delay_value()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2417
                self.match(SysVerilogHDLParser.Hash)
                self.state = 2418
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 2419
                self.delay_value()
                self.state = 2420
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2422
                self.match(SysVerilogHDLParser.Hash)
                self.state = 2423
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 2424
                self.mintypmax_expression()
                self.state = 2425
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def event_control_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_control_identifierContext,0)


        def event_control_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_control_expressionContext,0)


        def event_control_wildcard(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_control_wildcardContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_control" ):
                listener.enterEvent_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_control" ):
                listener.exitEvent_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_control" ):
                return visitor.visitEvent_control(self)
            else:
                return visitor.visitChildren(self)




    def event_control(self):

        localctx = SysVerilogHDLParser.Event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 610, self.RULE_event_control)
        try:
            self.state = 2432
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,185,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2429
                self.event_control_identifier()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2430
                self.event_control_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2431
                self.event_control_wildcard()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_control_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def At(self):
            return self.getToken(SysVerilogHDLParser.At, 0)

        def event_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_control_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_control_identifier" ):
                listener.enterEvent_control_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_control_identifier" ):
                listener.exitEvent_control_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_control_identifier" ):
                return visitor.visitEvent_control_identifier(self)
            else:
                return visitor.visitChildren(self)




    def event_control_identifier(self):

        localctx = SysVerilogHDLParser.Event_control_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 612, self.RULE_event_control_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2434
            self.match(SysVerilogHDLParser.At)
            self.state = 2435
            self.event_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_control_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def At(self):
            return self.getToken(SysVerilogHDLParser.At, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def event_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_control_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_control_expression" ):
                listener.enterEvent_control_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_control_expression" ):
                listener.exitEvent_control_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_control_expression" ):
                return visitor.visitEvent_control_expression(self)
            else:
                return visitor.visitChildren(self)




    def event_control_expression(self):

        localctx = SysVerilogHDLParser.Event_control_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 614, self.RULE_event_control_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2437
            self.match(SysVerilogHDLParser.At)
            self.state = 2438
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2439
            self.event_expression()
            self.state = 2440
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def single_event_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_event_expressionContext,0)


        def event_expression_or(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_expression_orContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_expression" ):
                listener.enterEvent_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_expression" ):
                listener.exitEvent_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_expression" ):
                return visitor.visitEvent_expression(self)
            else:
                return visitor.visitChildren(self)




    def event_expression(self):

        localctx = SysVerilogHDLParser.Event_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 616, self.RULE_event_expression)
        try:
            self.state = 2444
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,186,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2442
                self.single_event_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2443
                self.event_expression_or()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Single_event_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def event_expression_edgespec(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_expression_edgespecContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_single_event_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSingle_event_expression" ):
                listener.enterSingle_event_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSingle_event_expression" ):
                listener.exitSingle_event_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSingle_event_expression" ):
                return visitor.visitSingle_event_expression(self)
            else:
                return visitor.visitChildren(self)




    def single_event_expression(self):

        localctx = SysVerilogHDLParser.Single_event_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 618, self.RULE_single_event_expression)
        try:
            self.state = 2451
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,187,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2446
                self.expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2447
                self.hierarchical_identifier()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2448
                self.event_expression_edgespec()
                self.state = 2449
                self.expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_expression_edgespecContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Posedge(self):
            return self.getToken(SysVerilogHDLParser.Posedge, 0)

        def Negedge(self):
            return self.getToken(SysVerilogHDLParser.Negedge, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_expression_edgespec

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_expression_edgespec" ):
                listener.enterEvent_expression_edgespec(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_expression_edgespec" ):
                listener.exitEvent_expression_edgespec(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_expression_edgespec" ):
                return visitor.visitEvent_expression_edgespec(self)
            else:
                return visitor.visitChildren(self)




    def event_expression_edgespec(self):

        localctx = SysVerilogHDLParser.Event_expression_edgespecContext(self, self._ctx, self.state)
        self.enterRule(localctx, 620, self.RULE_event_expression_edgespec)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2453
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Negedge or _la==SysVerilogHDLParser.Posedge):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_expression_orContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def list_of_event_expression_comma(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_event_expression_commaContext,0)


        def list_of_event_expression_or(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_event_expression_orContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_expression_or

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_expression_or" ):
                listener.enterEvent_expression_or(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_expression_or" ):
                listener.exitEvent_expression_or(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_expression_or" ):
                return visitor.visitEvent_expression_or(self)
            else:
                return visitor.visitChildren(self)




    def event_expression_or(self):

        localctx = SysVerilogHDLParser.Event_expression_orContext(self, self._ctx, self.state)
        self.enterRule(localctx, 622, self.RULE_event_expression_or)
        try:
            self.state = 2457
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,188,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2455
                self.list_of_event_expression_comma()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2456
                self.list_of_event_expression_or()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_event_expression_commaContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def single_event_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_event_expressionContext,0)


        def comma_event_expression_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_event_expression_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_event_expression_comma

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_event_expression_comma" ):
                listener.enterList_of_event_expression_comma(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_event_expression_comma" ):
                listener.exitList_of_event_expression_comma(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_event_expression_comma" ):
                return visitor.visitList_of_event_expression_comma(self)
            else:
                return visitor.visitChildren(self)




    def list_of_event_expression_comma(self):

        localctx = SysVerilogHDLParser.List_of_event_expression_commaContext(self, self._ctx, self.state)
        self.enterRule(localctx, 624, self.RULE_list_of_event_expression_comma)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2459
            self.single_event_expression()
            self.state = 2460
            self.comma_event_expression_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_event_expression_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_event_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_event_expressionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_event_expressionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_event_expression_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_event_expression_star" ):
                listener.enterComma_event_expression_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_event_expression_star" ):
                listener.exitComma_event_expression_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_event_expression_star" ):
                return visitor.visitComma_event_expression_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_event_expression_star(self):

        localctx = SysVerilogHDLParser.Comma_event_expression_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 626, self.RULE_comma_event_expression_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2465
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2462
                self.comma_event_expression()
                self.state = 2467
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_event_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def single_event_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_event_expressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_event_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_event_expression" ):
                listener.enterComma_event_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_event_expression" ):
                listener.exitComma_event_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_event_expression" ):
                return visitor.visitComma_event_expression(self)
            else:
                return visitor.visitChildren(self)




    def comma_event_expression(self):

        localctx = SysVerilogHDLParser.Comma_event_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 628, self.RULE_comma_event_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2468
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2469
            self.single_event_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_event_expression_orContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def single_event_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_event_expressionContext,0)


        def or_event_expression_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Or_event_expression_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_event_expression_or

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_event_expression_or" ):
                listener.enterList_of_event_expression_or(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_event_expression_or" ):
                listener.exitList_of_event_expression_or(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_event_expression_or" ):
                return visitor.visitList_of_event_expression_or(self)
            else:
                return visitor.visitChildren(self)




    def list_of_event_expression_or(self):

        localctx = SysVerilogHDLParser.List_of_event_expression_orContext(self, self._ctx, self.state)
        self.enterRule(localctx, 630, self.RULE_list_of_event_expression_or)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2471
            self.single_event_expression()
            self.state = 2472
            self.or_event_expression_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Or_event_expression_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def or_event_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Or_event_expressionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Or_event_expressionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_or_event_expression_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOr_event_expression_star" ):
                listener.enterOr_event_expression_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOr_event_expression_star" ):
                listener.exitOr_event_expression_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOr_event_expression_star" ):
                return visitor.visitOr_event_expression_star(self)
            else:
                return visitor.visitChildren(self)




    def or_event_expression_star(self):

        localctx = SysVerilogHDLParser.Or_event_expression_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 632, self.RULE_or_event_expression_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2477
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Or:
                self.state = 2474
                self.or_event_expression()
                self.state = 2479
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Or_event_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Or(self):
            return self.getToken(SysVerilogHDLParser.Or, 0)

        def single_event_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_event_expressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_or_event_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterOr_event_expression" ):
                listener.enterOr_event_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitOr_event_expression" ):
                listener.exitOr_event_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitOr_event_expression" ):
                return visitor.visitOr_event_expression(self)
            else:
                return visitor.visitChildren(self)




    def or_event_expression(self):

        localctx = SysVerilogHDLParser.Or_event_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 634, self.RULE_or_event_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2480
            self.match(SysVerilogHDLParser.Or)
            self.state = 2481
            self.single_event_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_control_wildcardContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def At(self):
            return self.getToken(SysVerilogHDLParser.At, 0)

        def Star(self):
            return self.getToken(SysVerilogHDLParser.Star, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_control_wildcard

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_control_wildcard" ):
                listener.enterEvent_control_wildcard(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_control_wildcard" ):
                listener.exitEvent_control_wildcard(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_control_wildcard" ):
                return visitor.visitEvent_control_wildcard(self)
            else:
                return visitor.visitChildren(self)




    def event_control_wildcard(self):

        localctx = SysVerilogHDLParser.Event_control_wildcardContext(self, self._ctx, self.state)
        self.enterRule(localctx, 636, self.RULE_event_control_wildcard)
        try:
            self.state = 2489
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,191,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2483
                self.match(SysVerilogHDLParser.At)
                self.state = 2484
                self.match(SysVerilogHDLParser.Star)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2485
                self.match(SysVerilogHDLParser.At)
                self.state = 2486
                self.match(SysVerilogHDLParser.Open_parenthesis)
                self.state = 2487
                self.match(SysVerilogHDLParser.Star)
                self.state = 2488
                self.match(SysVerilogHDLParser.Close_parenthesis)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Repeat_event_controlContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Repeat(self):
            return self.getToken(SysVerilogHDLParser.Repeat, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def event_control(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_controlContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_repeat_event_control

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRepeat_event_control" ):
                listener.enterRepeat_event_control(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRepeat_event_control" ):
                listener.exitRepeat_event_control(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRepeat_event_control" ):
                return visitor.visitRepeat_event_control(self)
            else:
                return visitor.visitChildren(self)




    def repeat_event_control(self):

        localctx = SysVerilogHDLParser.Repeat_event_controlContext(self, self._ctx, self.state)
        self.enterRule(localctx, 638, self.RULE_repeat_event_control)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2491
            self.match(SysVerilogHDLParser.Repeat)
            self.state = 2492
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2493
            self.expression()
            self.state = 2494
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2495
            self.event_control()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_triggerContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Dash_right_angle(self):
            return self.getToken(SysVerilogHDLParser.Dash_right_angle, 0)

        def hierarchical_event_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_event_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_trigger

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_trigger" ):
                listener.enterEvent_trigger(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_trigger" ):
                listener.exitEvent_trigger(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_trigger" ):
                return visitor.visitEvent_trigger(self)
            else:
                return visitor.visitChildren(self)




    def event_trigger(self):

        localctx = SysVerilogHDLParser.Event_triggerContext(self, self._ctx, self.state)
        self.enterRule(localctx, 640, self.RULE_event_trigger)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2497
            self.match(SysVerilogHDLParser.Dash_right_angle)
            self.state = 2498
            self.hierarchical_event_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_event_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_event_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_event_identifier" ):
                listener.enterHierarchical_event_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_event_identifier" ):
                listener.exitHierarchical_event_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_event_identifier" ):
                return visitor.visitHierarchical_event_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_event_identifier(self):

        localctx = SysVerilogHDLParser.Hierarchical_event_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 642, self.RULE_hierarchical_event_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2500
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Event_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_event_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterEvent_identifier" ):
                listener.enterEvent_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitEvent_identifier" ):
                listener.exitEvent_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitEvent_identifier" ):
                return visitor.visitEvent_identifier(self)
            else:
                return visitor.visitChildren(self)




    def event_identifier(self):

        localctx = SysVerilogHDLParser.Event_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 644, self.RULE_event_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2502
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Wait_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Wait(self):
            return self.getToken(SysVerilogHDLParser.Wait, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_wait_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWait_statement" ):
                listener.enterWait_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWait_statement" ):
                listener.exitWait_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWait_statement" ):
                return visitor.visitWait_statement(self)
            else:
                return visitor.visitChildren(self)




    def wait_statement(self):

        localctx = SysVerilogHDLParser.Wait_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 646, self.RULE_wait_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2504
            self.match(SysVerilogHDLParser.Wait)
            self.state = 2505
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2506
            self.expression()
            self.state = 2507
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2508
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_generated_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def generated_instantiation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generated_instantiationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_generated_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_generated_instantiation" ):
                listener.enterAttr_generated_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_generated_instantiation" ):
                listener.exitAttr_generated_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_generated_instantiation" ):
                return visitor.visitAttr_generated_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def attr_generated_instantiation(self):

        localctx = SysVerilogHDLParser.Attr_generated_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 648, self.RULE_attr_generated_instantiation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2510
            self.attribute_instance_star()
            self.state = 2511
            self.generated_instantiation()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generated_instantiationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Generate(self):
            return self.getToken(SysVerilogHDLParser.Generate, 0)

        def generate_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_item_starContext,0)


        def Endgenerate(self):
            return self.getToken(SysVerilogHDLParser.Endgenerate, 0)

        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generated_instantiation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerated_instantiation" ):
                listener.enterGenerated_instantiation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerated_instantiation" ):
                listener.exitGenerated_instantiation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerated_instantiation" ):
                return visitor.visitGenerated_instantiation(self)
            else:
                return visitor.visitChildren(self)




    def generated_instantiation(self):

        localctx = SysVerilogHDLParser.Generated_instantiationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 650, self.RULE_generated_instantiation)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2513
            self.match(SysVerilogHDLParser.Generate)
            self.state = 2514
            self.generate_item_star()
            self.state = 2515
            self.match(SysVerilogHDLParser.Endgenerate)
            self.state = 2517
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.T__0 or _la==SysVerilogHDLParser.Semicolon:
                self.state = 2516
                self.semicolon()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Generate_itemContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_item_star" ):
                listener.enterGenerate_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_item_star" ):
                listener.exitGenerate_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_item_star" ):
                return visitor.visitGenerate_item_star(self)
            else:
                return visitor.visitChildren(self)




    def generate_item_star(self):

        localctx = SysVerilogHDLParser.Generate_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 652, self.RULE_generate_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2522
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__0) | (1 << SysVerilogHDLParser.Always) | (1 << SysVerilogHDLParser.Always_comb) | (1 << SysVerilogHDLParser.Always_ff) | (1 << SysVerilogHDLParser.And) | (1 << SysVerilogHDLParser.Assign) | (1 << SysVerilogHDLParser.Automatic) | (1 << SysVerilogHDLParser.Begin) | (1 << SysVerilogHDLParser.Bit) | (1 << SysVerilogHDLParser.Buf) | (1 << SysVerilogHDLParser.Bufif0) | (1 << SysVerilogHDLParser.Bufif1) | (1 << SysVerilogHDLParser.Byte) | (1 << SysVerilogHDLParser.Case_keyword) | (1 << SysVerilogHDLParser.Casez))) != 0) or ((((_la - 64)) & ~0x3f) == 0 and ((1 << (_la - 64)) & ((1 << (SysVerilogHDLParser.Casex - 64)) | (1 << (SysVerilogHDLParser.Cmos - 64)) | (1 << (SysVerilogHDLParser.Const - 64)) | (1 << (SysVerilogHDLParser.Defparam - 64)) | (1 << (SysVerilogHDLParser.Do - 64)) | (1 << (SysVerilogHDLParser.Enum - 64)) | (1 << (SysVerilogHDLParser.Event_keyword - 64)) | (1 << (SysVerilogHDLParser.Final - 64)) | (1 << (SysVerilogHDLParser.For - 64)) | (1 << (SysVerilogHDLParser.Forever - 64)) | (1 << (SysVerilogHDLParser.Function - 64)) | (1 << (SysVerilogHDLParser.Genvar - 64)) | (1 << (SysVerilogHDLParser.If - 64)) | (1 << (SysVerilogHDLParser.Initial - 64)) | (1 << (SysVerilogHDLParser.Int - 64)) | (1 << (SysVerilogHDLParser.Integer - 64)) | (1 << (SysVerilogHDLParser.Localparam - 64)) | (1 << (SysVerilogHDLParser.Logic - 64)) | (1 << (SysVerilogHDLParser.Nand - 64)) | (1 << (SysVerilogHDLParser.Nmos - 64)) | (1 << (SysVerilogHDLParser.NONE - 64)) | (1 << (SysVerilogHDLParser.Nor - 64)) | (1 << (SysVerilogHDLParser.Not - 64)))) != 0) or ((((_la - 128)) & ~0x3f) == 0 and ((1 << (_la - 128)) & ((1 << (SysVerilogHDLParser.Notif0 - 128)) | (1 << (SysVerilogHDLParser.Notif1 - 128)) | (1 << (SysVerilogHDLParser.Or - 128)) | (1 << (SysVerilogHDLParser.Parameter - 128)) | (1 << (SysVerilogHDLParser.Pmos - 128)) | (1 << (SysVerilogHDLParser.Pullup - 128)) | (1 << (SysVerilogHDLParser.Pulldown - 128)) | (1 << (SysVerilogHDLParser.Rcmos - 128)) | (1 << (SysVerilogHDLParser.Real - 128)) | (1 << (SysVerilogHDLParser.Realtime - 128)) | (1 << (SysVerilogHDLParser.Reg - 128)) | (1 << (SysVerilogHDLParser.Repeat - 128)) | (1 << (SysVerilogHDLParser.Rnmos - 128)) | (1 << (SysVerilogHDLParser.Rpmos - 128)) | (1 << (SysVerilogHDLParser.Rtran - 128)) | (1 << (SysVerilogHDLParser.Rtranif0 - 128)) | (1 << (SysVerilogHDLParser.Rtranif1 - 128)) | (1 << (SysVerilogHDLParser.Static - 128)) | (1 << (SysVerilogHDLParser.SVString - 128)) | (1 << (SysVerilogHDLParser.Struct - 128)) | (1 << (SysVerilogHDLParser.Supply0 - 128)) | (1 << (SysVerilogHDLParser.Supply1 - 128)) | (1 << (SysVerilogHDLParser.Task - 128)) | (1 << (SysVerilogHDLParser.Time - 128)) | (1 << (SysVerilogHDLParser.Tran - 128)) | (1 << (SysVerilogHDLParser.Tranif0 - 128)) | (1 << (SysVerilogHDLParser.Tranif1 - 128)) | (1 << (SysVerilogHDLParser.Tri - 128)) | (1 << (SysVerilogHDLParser.Tri_and - 128)) | (1 << (SysVerilogHDLParser.Tri_or - 128)) | (1 << (SysVerilogHDLParser.Tri_reg - 128)) | (1 << (SysVerilogHDLParser.Tri0 - 128)) | (1 << (SysVerilogHDLParser.Tri1 - 128)) | (1 << (SysVerilogHDLParser.UnionStruct - 128)) | (1 << (SysVerilogHDLParser.Uwire - 128)))) != 0) or ((((_la - 193)) & ~0x3f) == 0 and ((1 << (_la - 193)) & ((1 << (SysVerilogHDLParser.Wand - 193)) | (1 << (SysVerilogHDLParser.While - 193)) | (1 << (SysVerilogHDLParser.Wire - 193)) | (1 << (SysVerilogHDLParser.Wor - 193)) | (1 << (SysVerilogHDLParser.Xnor - 193)) | (1 << (SysVerilogHDLParser.Xor - 193)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 193)) | (1 << (SysVerilogHDLParser.Simple_identifier - 193)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 193)) | (1 << (SysVerilogHDLParser.Semicolon - 193)))) != 0):
                self.state = 2519
                self.generate_item()
                self.state = 2524
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_conditional_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_conditional_statementContext,0)


        def generate_case_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_case_statementContext,0)


        def generate_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_loop_statementContext,0)


        def generate_block(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_blockContext,0)


        def parameter_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_item_semicolonContext,0)


        def attr_variable_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_variable_item_semicolonContext,0)


        def subroutine_item_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Subroutine_item_semicolonContext,0)


        def attr_construct_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_construct_itemContext,0)


        def attr_component_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_component_itemContext,0)


        def null_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Null_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_item" ):
                listener.enterGenerate_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_item" ):
                listener.exitGenerate_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_item" ):
                return visitor.visitGenerate_item(self)
            else:
                return visitor.visitChildren(self)




    def generate_item(self):

        localctx = SysVerilogHDLParser.Generate_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 654, self.RULE_generate_item)
        try:
            self.state = 2535
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,194,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2525
                self.generate_conditional_statement()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2526
                self.generate_case_statement()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2527
                self.generate_loop_statement()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2528
                self.generate_block()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2529
                self.parameter_item_semicolon()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2530
                self.attr_variable_item_semicolon()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2531
                self.subroutine_item_semicolon()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2532
                self.attr_construct_item()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 2533
                self.attr_component_item()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 2534
                self.null_item()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_blockContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Begin(self):
            return self.getToken(SysVerilogHDLParser.Begin, 0)

        def generate_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_item_starContext,0)


        def End(self):
            return self.getToken(SysVerilogHDLParser.End, 0)

        def generate_colon_block_identifier0(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_colon_block_identifier0Context,0)


        def generate_colon_block_identifier1(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_colon_block_identifier1Context,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block" ):
                listener.enterGenerate_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block" ):
                listener.exitGenerate_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block" ):
                return visitor.visitGenerate_block(self)
            else:
                return visitor.visitChildren(self)




    def generate_block(self):

        localctx = SysVerilogHDLParser.Generate_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 656, self.RULE_generate_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2537
            self.match(SysVerilogHDLParser.Begin)
            self.state = 2539
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 2538
                self.generate_colon_block_identifier0()


            self.state = 2541
            self.generate_item_star()
            self.state = 2542
            self.match(SysVerilogHDLParser.End)
            self.state = 2544
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 2543
                self.generate_colon_block_identifier1()


            self.state = 2547
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,197,self._ctx)
            if la_ == 1:
                self.state = 2546
                self.semicolon()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_colon_block_identifier0Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_colon_block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_colon_block_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_colon_block_identifier0

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_colon_block_identifier0" ):
                listener.enterGenerate_colon_block_identifier0(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_colon_block_identifier0" ):
                listener.exitGenerate_colon_block_identifier0(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_colon_block_identifier0" ):
                return visitor.visitGenerate_colon_block_identifier0(self)
            else:
                return visitor.visitChildren(self)




    def generate_colon_block_identifier0(self):

        localctx = SysVerilogHDLParser.Generate_colon_block_identifier0Context(self, self._ctx, self.state)
        self.enterRule(localctx, 658, self.RULE_generate_colon_block_identifier0)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2549
            self.generate_colon_block_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_colon_block_identifier1Context(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_colon_block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_colon_block_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_colon_block_identifier1

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_colon_block_identifier1" ):
                listener.enterGenerate_colon_block_identifier1(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_colon_block_identifier1" ):
                listener.exitGenerate_colon_block_identifier1(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_colon_block_identifier1" ):
                return visitor.visitGenerate_colon_block_identifier1(self)
            else:
                return visitor.visitChildren(self)




    def generate_colon_block_identifier1(self):

        localctx = SysVerilogHDLParser.Generate_colon_block_identifier1Context(self, self._ctx, self.state)
        self.enterRule(localctx, 660, self.RULE_generate_colon_block_identifier1)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2551
            self.generate_colon_block_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_colon_block_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def generate_block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_block_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_colon_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_colon_block_identifier" ):
                listener.enterGenerate_colon_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_colon_block_identifier" ):
                listener.exitGenerate_colon_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_colon_block_identifier" ):
                return visitor.visitGenerate_colon_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def generate_colon_block_identifier(self):

        localctx = SysVerilogHDLParser.Generate_colon_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 662, self.RULE_generate_colon_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2553
            self.match(SysVerilogHDLParser.Colon)
            self.state = 2554
            self.generate_block_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_block_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_block_identifier" ):
                listener.enterGenerate_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_block_identifier" ):
                listener.exitGenerate_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_block_identifier" ):
                return visitor.visitGenerate_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def generate_block_identifier(self):

        localctx = SysVerilogHDLParser.Generate_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 664, self.RULE_generate_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2556
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_conditional_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_if_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_if_statementContext,0)


        def generate_else_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_else_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_conditional_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_conditional_statement" ):
                listener.enterGenerate_conditional_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_conditional_statement" ):
                listener.exitGenerate_conditional_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_conditional_statement" ):
                return visitor.visitGenerate_conditional_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_conditional_statement(self):

        localctx = SysVerilogHDLParser.Generate_conditional_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 666, self.RULE_generate_conditional_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2558
            self.generate_if_statement()
            self.state = 2560
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,198,self._ctx)
            if la_ == 1:
                self.state = 2559
                self.generate_else_statement()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_if_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def If(self):
            return self.getToken(SysVerilogHDLParser.If, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def conditional_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Conditional_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def generate_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_if_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_if_statement" ):
                listener.enterGenerate_if_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_if_statement" ):
                listener.exitGenerate_if_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_if_statement" ):
                return visitor.visitGenerate_if_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_if_statement(self):

        localctx = SysVerilogHDLParser.Generate_if_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 668, self.RULE_generate_if_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2562
            self.match(SysVerilogHDLParser.If)
            self.state = 2563
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2564
            self.conditional_expression()
            self.state = 2565
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2566
            self.generate_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_else_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Else(self):
            return self.getToken(SysVerilogHDLParser.Else, 0)

        def generate_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_else_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_else_statement" ):
                listener.enterGenerate_else_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_else_statement" ):
                listener.exitGenerate_else_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_else_statement" ):
                return visitor.visitGenerate_else_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_else_statement(self):

        localctx = SysVerilogHDLParser.Generate_else_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 670, self.RULE_generate_else_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2568
            self.match(SysVerilogHDLParser.Else)
            self.state = 2569
            self.generate_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_forever_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_forever_loop_statementContext,0)


        def generate_repeat_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_repeat_loop_statementContext,0)


        def generate_while_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_while_loop_statementContext,0)


        def generate_do_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_do_loop_statementContext,0)


        def generate_for_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_for_loop_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_loop_statement" ):
                listener.enterGenerate_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_loop_statement" ):
                listener.exitGenerate_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_loop_statement" ):
                return visitor.visitGenerate_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_loop_statement(self):

        localctx = SysVerilogHDLParser.Generate_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 672, self.RULE_generate_loop_statement)
        try:
            self.state = 2576
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Forever]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2571
                self.generate_forever_loop_statement()
                pass
            elif token in [SysVerilogHDLParser.Repeat]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2572
                self.generate_repeat_loop_statement()
                pass
            elif token in [SysVerilogHDLParser.While]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2573
                self.generate_while_loop_statement()
                pass
            elif token in [SysVerilogHDLParser.Do]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2574
                self.generate_do_loop_statement()
                pass
            elif token in [SysVerilogHDLParser.For]:
                self.enterOuterAlt(localctx, 5)
                self.state = 2575
                self.generate_for_loop_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_forever_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Forever(self):
            return self.getToken(SysVerilogHDLParser.Forever, 0)

        def generate_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_forever_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_forever_loop_statement" ):
                listener.enterGenerate_forever_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_forever_loop_statement" ):
                listener.exitGenerate_forever_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_forever_loop_statement" ):
                return visitor.visitGenerate_forever_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_forever_loop_statement(self):

        localctx = SysVerilogHDLParser.Generate_forever_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 674, self.RULE_generate_forever_loop_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2578
            self.match(SysVerilogHDLParser.Forever)
            self.state = 2579
            self.generate_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_repeat_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Repeat(self):
            return self.getToken(SysVerilogHDLParser.Repeat, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def loop_terminate_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_terminate_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def generate_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_repeat_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_repeat_loop_statement" ):
                listener.enterGenerate_repeat_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_repeat_loop_statement" ):
                listener.exitGenerate_repeat_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_repeat_loop_statement" ):
                return visitor.visitGenerate_repeat_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_repeat_loop_statement(self):

        localctx = SysVerilogHDLParser.Generate_repeat_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 676, self.RULE_generate_repeat_loop_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2581
            self.match(SysVerilogHDLParser.Repeat)
            self.state = 2582
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2583
            self.loop_terminate_expression()
            self.state = 2584
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2585
            self.generate_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_while_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def While(self):
            return self.getToken(SysVerilogHDLParser.While, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def loop_terminate_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_terminate_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def generate_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_while_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_while_loop_statement" ):
                listener.enterGenerate_while_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_while_loop_statement" ):
                listener.exitGenerate_while_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_while_loop_statement" ):
                return visitor.visitGenerate_while_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_while_loop_statement(self):

        localctx = SysVerilogHDLParser.Generate_while_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 678, self.RULE_generate_while_loop_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2587
            self.match(SysVerilogHDLParser.While)
            self.state = 2588
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2589
            self.loop_terminate_expression()
            self.state = 2590
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2591
            self.generate_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_do_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Do(self):
            return self.getToken(SysVerilogHDLParser.Do, 0)

        def generate_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,0)


        def While(self):
            return self.getToken(SysVerilogHDLParser.While, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def loop_terminate_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_terminate_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_do_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_do_loop_statement" ):
                listener.enterGenerate_do_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_do_loop_statement" ):
                listener.exitGenerate_do_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_do_loop_statement" ):
                return visitor.visitGenerate_do_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_do_loop_statement(self):

        localctx = SysVerilogHDLParser.Generate_do_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 680, self.RULE_generate_do_loop_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2593
            self.match(SysVerilogHDLParser.Do)
            self.state = 2594
            self.generate_item()
            self.state = 2595
            self.match(SysVerilogHDLParser.While)
            self.state = 2596
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2597
            self.loop_terminate_expression()
            self.state = 2598
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2599
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_for_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def For(self):
            return self.getToken(SysVerilogHDLParser.For, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def loop_init_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_init_assignmentContext,0)


        def semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.SemicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,i)


        def loop_terminate_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_terminate_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def generate_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,0)


        def loop_step_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_step_assignmentContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_for_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_for_loop_statement" ):
                listener.enterGenerate_for_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_for_loop_statement" ):
                listener.exitGenerate_for_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_for_loop_statement" ):
                return visitor.visitGenerate_for_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_for_loop_statement(self):

        localctx = SysVerilogHDLParser.Generate_for_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 682, self.RULE_generate_for_loop_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2601
            self.match(SysVerilogHDLParser.For)
            self.state = 2602
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2603
            self.loop_init_assignment()
            self.state = 2604
            self.semicolon()
            self.state = 2605
            self.loop_terminate_expression()
            self.state = 2606
            self.semicolon()
            self.state = 2608
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.T__26 or _la==SysVerilogHDLParser.T__27 or ((((_la - 202)) & ~0x3f) == 0 and ((1 << (_la - 202)) & ((1 << (SysVerilogHDLParser.Escaped_identifier - 202)) | (1 << (SysVerilogHDLParser.Simple_identifier - 202)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 202)))) != 0):
                self.state = 2607
                self.loop_step_assignment()


            self.state = 2610
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2611
            self.generate_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_case_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def any_case_keyword(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Any_case_keywordContext,0)


        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def case_switch(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Case_switchContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def generate_case_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_case_item_starContext,0)


        def Endcase(self):
            return self.getToken(SysVerilogHDLParser.Endcase, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_case_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_case_statement" ):
                listener.enterGenerate_case_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_case_statement" ):
                listener.exitGenerate_case_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_case_statement" ):
                return visitor.visitGenerate_case_statement(self)
            else:
                return visitor.visitChildren(self)




    def generate_case_statement(self):

        localctx = SysVerilogHDLParser.Generate_case_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 684, self.RULE_generate_case_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2613
            self.any_case_keyword()
            self.state = 2614
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2615
            self.case_switch()
            self.state = 2616
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2617
            self.generate_case_item_star()
            self.state = 2618
            self.match(SysVerilogHDLParser.Endcase)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_case_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def generate_case_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Generate_case_itemContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Generate_case_itemContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_case_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_case_item_star" ):
                listener.enterGenerate_case_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_case_item_star" ):
                listener.exitGenerate_case_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_case_item_star" ):
                return visitor.visitGenerate_case_item_star(self)
            else:
                return visitor.visitChildren(self)




    def generate_case_item_star(self):

        localctx = SysVerilogHDLParser.Generate_case_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 686, self.RULE_generate_case_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2623
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form))) != 0) or _la==SysVerilogHDLParser.Default or _la==SysVerilogHDLParser.Int or ((((_la - 161)) & ~0x3f) == 0 and ((1 << (_la - 161)) & ((1 << (SysVerilogHDLParser.Signed - 161)) | (1 << (SysVerilogHDLParser.Unsigned - 161)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 161)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 161)) | (1 << (SysVerilogHDLParser.Simple_identifier - 161)) | (1 << (SysVerilogHDLParser.String_literal - 161)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 161)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 161)) | (1 << (SysVerilogHDLParser.Quote - 161)))) != 0) or _la==SysVerilogHDLParser.Tilde:
                self.state = 2620
                self.generate_case_item()
                self.state = 2625
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Generate_case_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def generate_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Generate_itemContext,0)


        def case_item_key(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Case_item_keyContext,0)


        def Default(self):
            return self.getToken(SysVerilogHDLParser.Default, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_generate_case_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterGenerate_case_item" ):
                listener.enterGenerate_case_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitGenerate_case_item" ):
                listener.exitGenerate_case_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitGenerate_case_item" ):
                return visitor.visitGenerate_case_item(self)
            else:
                return visitor.visitChildren(self)




    def generate_case_item(self):

        localctx = SysVerilogHDLParser.Generate_case_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 688, self.RULE_generate_case_item)
        self._la = 0 # Token type
        try:
            self.state = 2635
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.T__1, SysVerilogHDLParser.T__2, SysVerilogHDLParser.T__3, SysVerilogHDLParser.T__4, SysVerilogHDLParser.T__5, SysVerilogHDLParser.T__6, SysVerilogHDLParser.T__7, SysVerilogHDLParser.T__8, SysVerilogHDLParser.T__9, SysVerilogHDLParser.T__10, SysVerilogHDLParser.T__26, SysVerilogHDLParser.T__27, SysVerilogHDLParser.Binary_number, SysVerilogHDLParser.Decimal_number, SysVerilogHDLParser.Fixed_point_number, SysVerilogHDLParser.Hex_number, SysVerilogHDLParser.Octal_number, SysVerilogHDLParser.Real_exp_form, SysVerilogHDLParser.Int, SysVerilogHDLParser.Signed, SysVerilogHDLParser.Unsigned, SysVerilogHDLParser.Dollar_Identifier, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier, SysVerilogHDLParser.String_literal, SysVerilogHDLParser.Left_curly_bracket, SysVerilogHDLParser.Open_parenthesis, SysVerilogHDLParser.Quote, SysVerilogHDLParser.Tilde]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2626
                self.case_item_key()
                self.state = 2627
                self.match(SysVerilogHDLParser.Colon)
                self.state = 2628
                self.generate_item()
                pass
            elif token in [SysVerilogHDLParser.Default]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2630
                self.match(SysVerilogHDLParser.Default)
                self.state = 2632
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SysVerilogHDLParser.Colon:
                    self.state = 2631
                    self.match(SysVerilogHDLParser.Colon)


                self.state = 2634
                self.generate_item()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Conditional_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def if_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.If_statementContext,0)


        def else_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Else_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_conditional_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConditional_statement" ):
                listener.enterConditional_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConditional_statement" ):
                listener.exitConditional_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConditional_statement" ):
                return visitor.visitConditional_statement(self)
            else:
                return visitor.visitChildren(self)




    def conditional_statement(self):

        localctx = SysVerilogHDLParser.Conditional_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 690, self.RULE_conditional_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2637
            self.if_statement()
            self.state = 2639
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,204,self._ctx)
            if la_ == 1:
                self.state = 2638
                self.else_statement()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class If_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def If(self):
            return self.getToken(SysVerilogHDLParser.If, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def conditional_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Conditional_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_if_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIf_statement" ):
                listener.enterIf_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIf_statement" ):
                listener.exitIf_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIf_statement" ):
                return visitor.visitIf_statement(self)
            else:
                return visitor.visitChildren(self)




    def if_statement(self):

        localctx = SysVerilogHDLParser.If_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 692, self.RULE_if_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2641
            self.match(SysVerilogHDLParser.If)
            self.state = 2642
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2643
            self.conditional_expression()
            self.state = 2644
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2645
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Else_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Else(self):
            return self.getToken(SysVerilogHDLParser.Else, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_else_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterElse_statement" ):
                listener.enterElse_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitElse_statement" ):
                listener.exitElse_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitElse_statement" ):
                return visitor.visitElse_statement(self)
            else:
                return visitor.visitChildren(self)




    def else_statement(self):

        localctx = SysVerilogHDLParser.Else_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 694, self.RULE_else_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2647
            self.match(SysVerilogHDLParser.Else)
            self.state = 2648
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Conditional_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_conditional_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConditional_expression" ):
                listener.enterConditional_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConditional_expression" ):
                listener.exitConditional_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConditional_expression" ):
                return visitor.visitConditional_expression(self)
            else:
                return visitor.visitChildren(self)




    def conditional_expression(self):

        localctx = SysVerilogHDLParser.Conditional_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 696, self.RULE_conditional_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2650
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def forever_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Forever_loop_statementContext,0)


        def repeat_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Repeat_loop_statementContext,0)


        def while_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.While_loop_statementContext,0)


        def do_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Do_loop_statementContext,0)


        def for_loop_statement(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.For_loop_statementContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_statement" ):
                listener.enterLoop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_statement" ):
                listener.exitLoop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_statement" ):
                return visitor.visitLoop_statement(self)
            else:
                return visitor.visitChildren(self)




    def loop_statement(self):

        localctx = SysVerilogHDLParser.Loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 698, self.RULE_loop_statement)
        try:
            self.state = 2657
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Forever]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2652
                self.forever_loop_statement()
                pass
            elif token in [SysVerilogHDLParser.Repeat]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2653
                self.repeat_loop_statement()
                pass
            elif token in [SysVerilogHDLParser.While]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2654
                self.while_loop_statement()
                pass
            elif token in [SysVerilogHDLParser.Do]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2655
                self.do_loop_statement()
                pass
            elif token in [SysVerilogHDLParser.For]:
                self.enterOuterAlt(localctx, 5)
                self.state = 2656
                self.for_loop_statement()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Forever_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Forever(self):
            return self.getToken(SysVerilogHDLParser.Forever, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_forever_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterForever_loop_statement" ):
                listener.enterForever_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitForever_loop_statement" ):
                listener.exitForever_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitForever_loop_statement" ):
                return visitor.visitForever_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def forever_loop_statement(self):

        localctx = SysVerilogHDLParser.Forever_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 700, self.RULE_forever_loop_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2659
            self.match(SysVerilogHDLParser.Forever)
            self.state = 2660
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Repeat_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Repeat(self):
            return self.getToken(SysVerilogHDLParser.Repeat, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def loop_terminate_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_terminate_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_repeat_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterRepeat_loop_statement" ):
                listener.enterRepeat_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitRepeat_loop_statement" ):
                listener.exitRepeat_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitRepeat_loop_statement" ):
                return visitor.visitRepeat_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def repeat_loop_statement(self):

        localctx = SysVerilogHDLParser.Repeat_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 702, self.RULE_repeat_loop_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2662
            self.match(SysVerilogHDLParser.Repeat)
            self.state = 2663
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2664
            self.loop_terminate_expression()
            self.state = 2665
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2666
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class While_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def While(self):
            return self.getToken(SysVerilogHDLParser.While, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def loop_terminate_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_terminate_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_while_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWhile_loop_statement" ):
                listener.enterWhile_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWhile_loop_statement" ):
                listener.exitWhile_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWhile_loop_statement" ):
                return visitor.visitWhile_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def while_loop_statement(self):

        localctx = SysVerilogHDLParser.While_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 704, self.RULE_while_loop_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2668
            self.match(SysVerilogHDLParser.While)
            self.state = 2669
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2670
            self.loop_terminate_expression()
            self.state = 2671
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2672
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Do_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Do(self):
            return self.getToken(SysVerilogHDLParser.Do, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def While(self):
            return self.getToken(SysVerilogHDLParser.While, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def loop_terminate_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_terminate_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_do_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDo_loop_statement" ):
                listener.enterDo_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDo_loop_statement" ):
                listener.exitDo_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDo_loop_statement" ):
                return visitor.visitDo_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def do_loop_statement(self):

        localctx = SysVerilogHDLParser.Do_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 706, self.RULE_do_loop_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2674
            self.match(SysVerilogHDLParser.Do)
            self.state = 2675
            self.statement_semicolon()
            self.state = 2676
            self.match(SysVerilogHDLParser.While)
            self.state = 2677
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2678
            self.loop_terminate_expression()
            self.state = 2679
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2680
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class For_loop_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def For(self):
            return self.getToken(SysVerilogHDLParser.For, 0)

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def loop_init_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_init_assignmentContext,0)


        def semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.SemicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,i)


        def loop_terminate_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_terminate_expressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def loop_step_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Loop_step_assignmentContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_for_loop_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFor_loop_statement" ):
                listener.enterFor_loop_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFor_loop_statement" ):
                listener.exitFor_loop_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFor_loop_statement" ):
                return visitor.visitFor_loop_statement(self)
            else:
                return visitor.visitChildren(self)




    def for_loop_statement(self):

        localctx = SysVerilogHDLParser.For_loop_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 708, self.RULE_for_loop_statement)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2682
            self.match(SysVerilogHDLParser.For)
            self.state = 2683
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2684
            self.loop_init_assignment()
            self.state = 2685
            self.semicolon()
            self.state = 2686
            self.loop_terminate_expression()
            self.state = 2687
            self.semicolon()
            self.state = 2689
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.T__26 or _la==SysVerilogHDLParser.T__27 or ((((_la - 202)) & ~0x3f) == 0 and ((1 << (_la - 202)) & ((1 << (SysVerilogHDLParser.Escaped_identifier - 202)) | (1 << (SysVerilogHDLParser.Simple_identifier - 202)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 202)))) != 0):
                self.state = 2688
                self.loop_step_assignment()


            self.state = 2691
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2692
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_init_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def declarative_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Declarative_assignmentContext,0)


        def blocking_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Blocking_assignmentContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_loop_init_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_init_assignment" ):
                listener.enterLoop_init_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_init_assignment" ):
                listener.exitLoop_init_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_init_assignment" ):
                return visitor.visitLoop_init_assignment(self)
            else:
                return visitor.visitChildren(self)




    def loop_init_assignment(self):

        localctx = SysVerilogHDLParser.Loop_init_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 710, self.RULE_loop_init_assignment)
        try:
            self.state = 2696
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Automatic, SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte, SysVerilogHDLParser.Const, SysVerilogHDLParser.Genvar, SysVerilogHDLParser.Int, SysVerilogHDLParser.Integer, SysVerilogHDLParser.Logic, SysVerilogHDLParser.Reg, SysVerilogHDLParser.Static]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2694
                self.declarative_assignment()
                pass
            elif token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier, SysVerilogHDLParser.Left_curly_bracket]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2695
                self.blocking_assignment()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_terminate_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_loop_terminate_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_terminate_expression" ):
                listener.enterLoop_terminate_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_terminate_expression" ):
                listener.exitLoop_terminate_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_terminate_expression" ):
                return visitor.visitLoop_terminate_expression(self)
            else:
                return visitor.visitChildren(self)




    def loop_terminate_expression(self):

        localctx = SysVerilogHDLParser.Loop_terminate_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 712, self.RULE_loop_terminate_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2698
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Loop_step_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def blocking_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Blocking_assignmentContext,0)


        def postfix_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Postfix_assignmentContext,0)


        def prefix_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Prefix_assignmentContext,0)


        def operator_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Operator_assignmentContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_loop_step_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterLoop_step_assignment" ):
                listener.enterLoop_step_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitLoop_step_assignment" ):
                listener.exitLoop_step_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitLoop_step_assignment" ):
                return visitor.visitLoop_step_assignment(self)
            else:
                return visitor.visitChildren(self)




    def loop_step_assignment(self):

        localctx = SysVerilogHDLParser.Loop_step_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 714, self.RULE_loop_step_assignment)
        try:
            self.state = 2704
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,208,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2700
                self.blocking_assignment()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2701
                self.postfix_assignment()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2702
                self.prefix_assignment()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2703
                self.operator_assignment()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def any_case_keyword(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Any_case_keywordContext,0)


        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def case_switch(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Case_switchContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def case_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Case_item_starContext,0)


        def Endcase(self):
            return self.getToken(SysVerilogHDLParser.Endcase, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_case_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_statement" ):
                listener.enterCase_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_statement" ):
                listener.exitCase_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_statement" ):
                return visitor.visitCase_statement(self)
            else:
                return visitor.visitChildren(self)




    def case_statement(self):

        localctx = SysVerilogHDLParser.Case_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 716, self.RULE_case_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2706
            self.any_case_keyword()
            self.state = 2707
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2708
            self.case_switch()
            self.state = 2709
            self.match(SysVerilogHDLParser.Close_parenthesis)
            self.state = 2710
            self.case_item_star()
            self.state = 2711
            self.match(SysVerilogHDLParser.Endcase)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def case_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Case_itemContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Case_itemContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_case_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_item_star" ):
                listener.enterCase_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_item_star" ):
                listener.exitCase_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_item_star" ):
                return visitor.visitCase_item_star(self)
            else:
                return visitor.visitChildren(self)




    def case_item_star(self):

        localctx = SysVerilogHDLParser.Case_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 718, self.RULE_case_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2716
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form))) != 0) or _la==SysVerilogHDLParser.Default or _la==SysVerilogHDLParser.Int or ((((_la - 161)) & ~0x3f) == 0 and ((1 << (_la - 161)) & ((1 << (SysVerilogHDLParser.Signed - 161)) | (1 << (SysVerilogHDLParser.Unsigned - 161)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 161)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 161)) | (1 << (SysVerilogHDLParser.Simple_identifier - 161)) | (1 << (SysVerilogHDLParser.String_literal - 161)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 161)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 161)) | (1 << (SysVerilogHDLParser.Quote - 161)))) != 0) or _la==SysVerilogHDLParser.Tilde:
                self.state = 2713
                self.case_item()
                self.state = 2718
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def case_item_key(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Case_item_keyContext,0)


        def Default(self):
            return self.getToken(SysVerilogHDLParser.Default, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_case_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_item" ):
                listener.enterCase_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_item" ):
                listener.exitCase_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_item" ):
                return visitor.visitCase_item(self)
            else:
                return visitor.visitChildren(self)




    def case_item(self):

        localctx = SysVerilogHDLParser.Case_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 720, self.RULE_case_item)
        self._la = 0 # Token type
        try:
            self.state = 2728
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.T__1, SysVerilogHDLParser.T__2, SysVerilogHDLParser.T__3, SysVerilogHDLParser.T__4, SysVerilogHDLParser.T__5, SysVerilogHDLParser.T__6, SysVerilogHDLParser.T__7, SysVerilogHDLParser.T__8, SysVerilogHDLParser.T__9, SysVerilogHDLParser.T__10, SysVerilogHDLParser.T__26, SysVerilogHDLParser.T__27, SysVerilogHDLParser.Binary_number, SysVerilogHDLParser.Decimal_number, SysVerilogHDLParser.Fixed_point_number, SysVerilogHDLParser.Hex_number, SysVerilogHDLParser.Octal_number, SysVerilogHDLParser.Real_exp_form, SysVerilogHDLParser.Int, SysVerilogHDLParser.Signed, SysVerilogHDLParser.Unsigned, SysVerilogHDLParser.Dollar_Identifier, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier, SysVerilogHDLParser.String_literal, SysVerilogHDLParser.Left_curly_bracket, SysVerilogHDLParser.Open_parenthesis, SysVerilogHDLParser.Quote, SysVerilogHDLParser.Tilde]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2719
                self.case_item_key()
                self.state = 2720
                self.match(SysVerilogHDLParser.Colon)
                self.state = 2721
                self.statement_semicolon()
                pass
            elif token in [SysVerilogHDLParser.Default]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2723
                self.match(SysVerilogHDLParser.Default)
                self.state = 2725
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if _la==SysVerilogHDLParser.Colon:
                    self.state = 2724
                    self.match(SysVerilogHDLParser.Colon)


                self.state = 2727
                self.statement_semicolon()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_switchContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_case_switch

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_switch" ):
                listener.enterCase_switch(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_switch" ):
                listener.exitCase_switch(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_switch" ):
                return visitor.visitCase_switch(self)
            else:
                return visitor.visitChildren(self)




    def case_switch(self):

        localctx = SysVerilogHDLParser.Case_switchContext(self, self._ctx, self.state)
        self.enterRule(localctx, 722, self.RULE_case_switch)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2730
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_item_keyContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def case_item_key_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Case_item_key_expressionContext,0)


        def comma_case_item_key_expression_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_case_item_key_expression_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_case_item_key

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_item_key" ):
                listener.enterCase_item_key(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_item_key" ):
                listener.exitCase_item_key(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_item_key" ):
                return visitor.visitCase_item_key(self)
            else:
                return visitor.visitChildren(self)




    def case_item_key(self):

        localctx = SysVerilogHDLParser.Case_item_keyContext(self, self._ctx, self.state)
        self.enterRule(localctx, 724, self.RULE_case_item_key)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2732
            self.case_item_key_expression()
            self.state = 2733
            self.comma_case_item_key_expression_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Case_item_key_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_case_item_key_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterCase_item_key_expression" ):
                listener.enterCase_item_key_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitCase_item_key_expression" ):
                listener.exitCase_item_key_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitCase_item_key_expression" ):
                return visitor.visitCase_item_key_expression(self)
            else:
                return visitor.visitChildren(self)




    def case_item_key_expression(self):

        localctx = SysVerilogHDLParser.Case_item_key_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 726, self.RULE_case_item_key_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2735
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_case_item_key_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def case_item_key_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Case_item_key_expressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_case_item_key_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_case_item_key_expression" ):
                listener.enterComma_case_item_key_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_case_item_key_expression" ):
                listener.exitComma_case_item_key_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_case_item_key_expression" ):
                return visitor.visitComma_case_item_key_expression(self)
            else:
                return visitor.visitChildren(self)




    def comma_case_item_key_expression(self):

        localctx = SysVerilogHDLParser.Comma_case_item_key_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 728, self.RULE_comma_case_item_key_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2737
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2738
            self.case_item_key_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_case_item_key_expression_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_case_item_key_expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_case_item_key_expressionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_case_item_key_expressionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_case_item_key_expression_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_case_item_key_expression_star" ):
                listener.enterComma_case_item_key_expression_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_case_item_key_expression_star" ):
                listener.exitComma_case_item_key_expression_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_case_item_key_expression_star" ):
                return visitor.visitComma_case_item_key_expression_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_case_item_key_expression_star(self):

        localctx = SysVerilogHDLParser.Comma_case_item_key_expression_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 730, self.RULE_comma_case_item_key_expression_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2743
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2740
                self.comma_case_item_key_expression()
                self.state = 2745
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ExpressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def unary_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Unary_expressionContext,0)


        def unary_post_assign_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Unary_post_assign_expressionContext,0)


        def unary_pre_assign_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Unary_pre_assign_expressionContext,0)


        def binary_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Binary_expressionContext,0)


        def ternary_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Ternary_expressionContext,0)


        def mintypmax_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Mintypmax_expressionContext,0)


        def single_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_expressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterExpression" ):
                listener.enterExpression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitExpression" ):
                listener.exitExpression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitExpression" ):
                return visitor.visitExpression(self)
            else:
                return visitor.visitChildren(self)




    def expression(self):

        localctx = SysVerilogHDLParser.ExpressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 732, self.RULE_expression)
        try:
            self.state = 2753
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,213,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2746
                self.unary_expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2747
                self.unary_post_assign_expression()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2748
                self.unary_pre_assign_expression()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2749
                self.binary_expression()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2750
                self.ternary_expression()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2751
                self.mintypmax_expression()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2752
                self.single_expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Single_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def String_literal(self):
            return self.getToken(SysVerilogHDLParser.String_literal, 0)

        def primary(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.PrimaryContext,0)


        def arrayed_structured_value(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Arrayed_structured_valueContext,0)


        def structured_value(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Structured_valueContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_single_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSingle_expression" ):
                listener.enterSingle_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSingle_expression" ):
                listener.exitSingle_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSingle_expression" ):
                return visitor.visitSingle_expression(self)
            else:
                return visitor.visitChildren(self)




    def single_expression(self):

        localctx = SysVerilogHDLParser.Single_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 734, self.RULE_single_expression)
        try:
            self.state = 2759
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,214,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2755
                self.match(SysVerilogHDLParser.String_literal)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2756
                self.primary()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2757
                self.arrayed_structured_value()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2758
                self.structured_value()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Primary_rangeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def primary(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.PrimaryContext,0)


        def dimension(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DimensionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_primary_range

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrimary_range" ):
                listener.enterPrimary_range(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrimary_range" ):
                listener.exitPrimary_range(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrimary_range" ):
                return visitor.visitPrimary_range(self)
            else:
                return visitor.visitChildren(self)




    def primary_range(self):

        localctx = SysVerilogHDLParser.Primary_rangeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 736, self.RULE_primary_range)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2761
            self.primary()
            self.state = 2762
            self.dimension()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class PrimaryContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.NumberContext,0)


        def concatenation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ConcatenationContext,0)


        def multiple_concatenation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Multiple_concatenationContext,0)


        def function_call(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_callContext,0)


        def system_function_call(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.System_function_callContext,0)


        def constant_function_call(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Constant_function_callContext,0)


        def imported_function_call(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Imported_function_callContext,0)


        def primary_imported_hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Primary_imported_hierarchical_identifierContext,0)


        def primary_hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Primary_hierarchical_identifierContext,0)


        def type_cast_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Type_cast_expressionContext,0)


        def parenthesis_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parenthesis_expressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_primary

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrimary" ):
                listener.enterPrimary(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrimary" ):
                listener.exitPrimary(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrimary" ):
                return visitor.visitPrimary(self)
            else:
                return visitor.visitChildren(self)




    def primary(self):

        localctx = SysVerilogHDLParser.PrimaryContext(self, self._ctx, self.state)
        self.enterRule(localctx, 738, self.RULE_primary)
        try:
            self.state = 2775
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,215,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2764
                self.number()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2765
                self.concatenation()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2766
                self.multiple_concatenation()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 2767
                self.function_call()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 2768
                self.system_function_call()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 2769
                self.constant_function_call()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 2770
                self.imported_function_call()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 2771
                self.primary_imported_hierarchical_identifier()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 2772
                self.primary_hierarchical_identifier()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 2773
                self.type_cast_expression()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 2774
                self.parenthesis_expression()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def unary_operator(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Unary_operatorContext,0)


        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_unary_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_expression" ):
                listener.enterUnary_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_expression" ):
                listener.exitUnary_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_expression" ):
                return visitor.visitUnary_expression(self)
            else:
                return visitor.visitChildren(self)




    def unary_expression(self):

        localctx = SysVerilogHDLParser.Unary_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 740, self.RULE_unary_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2777
            self.unary_operator()
            self.state = 2778
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_post_assign_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def single_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_expressionContext,0)


        def unary_assign_operator(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Unary_assign_operatorContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_unary_post_assign_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_post_assign_expression" ):
                listener.enterUnary_post_assign_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_post_assign_expression" ):
                listener.exitUnary_post_assign_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_post_assign_expression" ):
                return visitor.visitUnary_post_assign_expression(self)
            else:
                return visitor.visitChildren(self)




    def unary_post_assign_expression(self):

        localctx = SysVerilogHDLParser.Unary_post_assign_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 742, self.RULE_unary_post_assign_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2780
            self.single_expression()
            self.state = 2781
            self.unary_assign_operator()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Unary_pre_assign_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def unary_assign_operator(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Unary_assign_operatorContext,0)


        def single_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_expressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_unary_pre_assign_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterUnary_pre_assign_expression" ):
                listener.enterUnary_pre_assign_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitUnary_pre_assign_expression" ):
                listener.exitUnary_pre_assign_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitUnary_pre_assign_expression" ):
                return visitor.visitUnary_pre_assign_expression(self)
            else:
                return visitor.visitChildren(self)




    def unary_pre_assign_expression(self):

        localctx = SysVerilogHDLParser.Unary_pre_assign_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 744, self.RULE_unary_pre_assign_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2783
            self.unary_assign_operator()
            self.state = 2784
            self.single_expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Binary_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def single_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_expressionContext,0)


        def binary_operator(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Binary_operatorContext,0)


        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_binary_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBinary_expression" ):
                listener.enterBinary_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBinary_expression" ):
                listener.exitBinary_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBinary_expression" ):
                return visitor.visitBinary_expression(self)
            else:
                return visitor.visitChildren(self)




    def binary_expression(self):

        localctx = SysVerilogHDLParser.Binary_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 746, self.RULE_binary_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2786
            self.single_expression()
            self.state = 2787
            self.binary_operator()
            self.state = 2788
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Ternary_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def single_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_expressionContext,0)


        def Question_mark(self):
            return self.getToken(SysVerilogHDLParser.Question_mark, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,i)


        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_ternary_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTernary_expression" ):
                listener.enterTernary_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTernary_expression" ):
                listener.exitTernary_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTernary_expression" ):
                return visitor.visitTernary_expression(self)
            else:
                return visitor.visitChildren(self)




    def ternary_expression(self):

        localctx = SysVerilogHDLParser.Ternary_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 748, self.RULE_ternary_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2790
            self.single_expression()
            self.state = 2791
            self.match(SysVerilogHDLParser.Question_mark)
            self.state = 2792
            self.expression()
            self.state = 2793
            self.match(SysVerilogHDLParser.Colon)
            self.state = 2794
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Mintypmax_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def single_expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Single_expressionContext,0)


        def Colon(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Colon)
            else:
                return self.getToken(SysVerilogHDLParser.Colon, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_mintypmax_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMintypmax_expression" ):
                listener.enterMintypmax_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMintypmax_expression" ):
                listener.exitMintypmax_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMintypmax_expression" ):
                return visitor.visitMintypmax_expression(self)
            else:
                return visitor.visitChildren(self)




    def mintypmax_expression(self):

        localctx = SysVerilogHDLParser.Mintypmax_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 750, self.RULE_mintypmax_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2796
            self.single_expression()
            self.state = 2797
            self.match(SysVerilogHDLParser.Colon)
            self.state = 2798
            self.expression()
            self.state = 2799
            self.match(SysVerilogHDLParser.Colon)
            self.state = 2800
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Structured_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Quote(self):
            return self.getToken(SysVerilogHDLParser.Quote, 0)

        def Left_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Left_curly_bracket, 0)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,i)


        def Right_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Right_curly_bracket, 0)

        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_structured_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterStructured_value" ):
                listener.enterStructured_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitStructured_value" ):
                listener.exitStructured_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitStructured_value" ):
                return visitor.visitStructured_value(self)
            else:
                return visitor.visitChildren(self)




    def structured_value(self):

        localctx = SysVerilogHDLParser.Structured_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 752, self.RULE_structured_value)
        self._la = 0 # Token type
        try:
            self.state = 2821
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,217,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2802
                self.match(SysVerilogHDLParser.Quote)
                self.state = 2803
                self.match(SysVerilogHDLParser.Left_curly_bracket)
                self.state = 2804
                self.expression()
                self.state = 2809
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                while _la==SysVerilogHDLParser.Comma:
                    self.state = 2805
                    self.match(SysVerilogHDLParser.Comma)
                    self.state = 2806
                    self.expression()
                    self.state = 2811
                    self._errHandler.sync(self)
                    _la = self._input.LA(1)

                self.state = 2812
                self.match(SysVerilogHDLParser.Right_curly_bracket)
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2814
                self.match(SysVerilogHDLParser.Quote)
                self.state = 2815
                self.match(SysVerilogHDLParser.Left_curly_bracket)
                self.state = 2816
                self.expression()
                self.state = 2817
                self.match(SysVerilogHDLParser.Right_curly_bracket)
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 2819
                self.match(SysVerilogHDLParser.Left_curly_bracket)
                self.state = 2820
                self.match(SysVerilogHDLParser.Right_curly_bracket)
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Arrayed_structured_valueContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Quote(self):
            return self.getToken(SysVerilogHDLParser.Quote, 0)

        def Left_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Left_curly_bracket, 0)

        def arrayed_structure_item_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Arrayed_structure_item_plusContext,0)


        def Right_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Right_curly_bracket, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_arrayed_structured_value

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArrayed_structured_value" ):
                listener.enterArrayed_structured_value(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArrayed_structured_value" ):
                listener.exitArrayed_structured_value(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArrayed_structured_value" ):
                return visitor.visitArrayed_structured_value(self)
            else:
                return visitor.visitChildren(self)




    def arrayed_structured_value(self):

        localctx = SysVerilogHDLParser.Arrayed_structured_valueContext(self, self._ctx, self.state)
        self.enterRule(localctx, 754, self.RULE_arrayed_structured_value)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2823
            self.match(SysVerilogHDLParser.Quote)
            self.state = 2824
            self.match(SysVerilogHDLParser.Left_curly_bracket)
            self.state = 2825
            self.arrayed_structure_item_plus()
            self.state = 2826
            self.match(SysVerilogHDLParser.Right_curly_bracket)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Arrayed_structure_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Default(self):
            return self.getToken(SysVerilogHDLParser.Default, 0)

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_arrayed_structure_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArrayed_structure_item" ):
                listener.enterArrayed_structure_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArrayed_structure_item" ):
                listener.exitArrayed_structure_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArrayed_structure_item" ):
                return visitor.visitArrayed_structure_item(self)
            else:
                return visitor.visitChildren(self)




    def arrayed_structure_item(self):

        localctx = SysVerilogHDLParser.Arrayed_structure_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 756, self.RULE_arrayed_structure_item)
        try:
            self.state = 2835
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Default]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2828
                self.match(SysVerilogHDLParser.Default)
                self.state = 2829
                self.match(SysVerilogHDLParser.Colon)
                self.state = 2830
                self.expression()
                pass
            elif token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2831
                self.hierarchical_identifier()
                self.state = 2832
                self.match(SysVerilogHDLParser.Colon)
                self.state = 2833
                self.expression()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_arrayed_structure_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def arrayed_structure_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Arrayed_structure_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_arrayed_structure_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_arrayed_structure_item" ):
                listener.enterComma_arrayed_structure_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_arrayed_structure_item" ):
                listener.exitComma_arrayed_structure_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_arrayed_structure_item" ):
                return visitor.visitComma_arrayed_structure_item(self)
            else:
                return visitor.visitChildren(self)




    def comma_arrayed_structure_item(self):

        localctx = SysVerilogHDLParser.Comma_arrayed_structure_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 758, self.RULE_comma_arrayed_structure_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2837
            self.match(SysVerilogHDLParser.Comma)
            self.state = 2838
            self.arrayed_structure_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_arrayed_structure_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_arrayed_structure_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_arrayed_structure_itemContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_arrayed_structure_itemContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_arrayed_structure_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_arrayed_structure_item_star" ):
                listener.enterComma_arrayed_structure_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_arrayed_structure_item_star" ):
                listener.exitComma_arrayed_structure_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_arrayed_structure_item_star" ):
                return visitor.visitComma_arrayed_structure_item_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_arrayed_structure_item_star(self):

        localctx = SysVerilogHDLParser.Comma_arrayed_structure_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 760, self.RULE_comma_arrayed_structure_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2843
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2840
                self.comma_arrayed_structure_item()
                self.state = 2845
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Arrayed_structure_item_plusContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def arrayed_structure_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Arrayed_structure_itemContext,0)


        def comma_arrayed_structure_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_arrayed_structure_item_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_arrayed_structure_item_plus

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterArrayed_structure_item_plus" ):
                listener.enterArrayed_structure_item_plus(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitArrayed_structure_item_plus" ):
                listener.exitArrayed_structure_item_plus(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitArrayed_structure_item_plus" ):
                return visitor.visitArrayed_structure_item_plus(self)
            else:
                return visitor.visitChildren(self)




    def arrayed_structure_item_plus(self):

        localctx = SysVerilogHDLParser.Arrayed_structure_item_plusContext(self, self._ctx, self.state)
        self.enterRule(localctx, 762, self.RULE_arrayed_structure_item_plus)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2846
            self.arrayed_structure_item()
            self.state = 2847
            self.comma_arrayed_structure_item_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_type_castContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_typeContext,0)


        def Quote(self):
            return self.getToken(SysVerilogHDLParser.Quote, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_type_cast

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_type_cast" ):
                listener.enterVariable_type_cast(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_type_cast" ):
                listener.exitVariable_type_cast(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_type_cast" ):
                return visitor.visitVariable_type_cast(self)
            else:
                return visitor.visitChildren(self)




    def variable_type_cast(self):

        localctx = SysVerilogHDLParser.Variable_type_castContext(self, self._ctx, self.state)
        self.enterRule(localctx, 764, self.RULE_variable_type_cast)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2849
            self.variable_type()
            self.state = 2850
            self.match(SysVerilogHDLParser.Quote)
            self.state = 2851
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Width_type_castContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def number(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.NumberContext,0)


        def Quote(self):
            return self.getToken(SysVerilogHDLParser.Quote, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_width_type_cast

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterWidth_type_cast" ):
                listener.enterWidth_type_cast(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitWidth_type_cast" ):
                listener.exitWidth_type_cast(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitWidth_type_cast" ):
                return visitor.visitWidth_type_cast(self)
            else:
                return visitor.visitChildren(self)




    def width_type_cast(self):

        localctx = SysVerilogHDLParser.Width_type_castContext(self, self._ctx, self.state)
        self.enterRule(localctx, 766, self.RULE_width_type_cast)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2853
            self.number()
            self.state = 2854
            self.match(SysVerilogHDLParser.Quote)
            self.state = 2855
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Sign_type_castContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Quote(self):
            return self.getToken(SysVerilogHDLParser.Quote, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_sign_type_cast

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSign_type_cast" ):
                listener.enterSign_type_cast(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSign_type_cast" ):
                listener.exitSign_type_cast(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSign_type_cast" ):
                return visitor.visitSign_type_cast(self)
            else:
                return visitor.visitChildren(self)




    def sign_type_cast(self):

        localctx = SysVerilogHDLParser.Sign_type_castContext(self, self._ctx, self.state)
        self.enterRule(localctx, 768, self.RULE_sign_type_cast)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2857
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
            self.state = 2858
            self.match(SysVerilogHDLParser.Quote)
            self.state = 2859
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Null_type_castContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Quote(self):
            return self.getToken(SysVerilogHDLParser.Quote, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_null_type_cast

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNull_type_cast" ):
                listener.enterNull_type_cast(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNull_type_cast" ):
                listener.exitNull_type_cast(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNull_type_cast" ):
                return visitor.visitNull_type_cast(self)
            else:
                return visitor.visitChildren(self)




    def null_type_cast(self):

        localctx = SysVerilogHDLParser.Null_type_castContext(self, self._ctx, self.state)
        self.enterRule(localctx, 770, self.RULE_null_type_cast)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2861
            self.match(SysVerilogHDLParser.Quote)
            self.state = 2862
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Int(self):
            return self.getToken(SysVerilogHDLParser.Int, 0)

        def user_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.User_typeContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_type" ):
                listener.enterVariable_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_type" ):
                listener.exitVariable_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_type" ):
                return visitor.visitVariable_type(self)
            else:
                return visitor.visitChildren(self)




    def variable_type(self):

        localctx = SysVerilogHDLParser.Variable_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 772, self.RULE_variable_type)
        try:
            self.state = 2866
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Int]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2864
                self.match(SysVerilogHDLParser.Int)
                pass
            elif token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2865
                self.user_type()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Type_cast_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_type_cast_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterType_cast_identifier" ):
                listener.enterType_cast_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitType_cast_identifier" ):
                listener.exitType_cast_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitType_cast_identifier" ):
                return visitor.visitType_cast_identifier(self)
            else:
                return visitor.visitChildren(self)




    def type_cast_identifier(self):

        localctx = SysVerilogHDLParser.Type_cast_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 774, self.RULE_type_cast_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2868
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Type_cast_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_type_cast(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_type_castContext,0)


        def width_type_cast(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Width_type_castContext,0)


        def sign_type_cast(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Sign_type_castContext,0)


        def null_type_cast(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Null_type_castContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_type_cast_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterType_cast_expression" ):
                listener.enterType_cast_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitType_cast_expression" ):
                listener.exitType_cast_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitType_cast_expression" ):
                return visitor.visitType_cast_expression(self)
            else:
                return visitor.visitChildren(self)




    def type_cast_expression(self):

        localctx = SysVerilogHDLParser.Type_cast_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 776, self.RULE_type_cast_expression)
        try:
            self.state = 2874
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Int, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2870
                self.variable_type_cast()
                pass
            elif token in [SysVerilogHDLParser.Binary_number, SysVerilogHDLParser.Decimal_number, SysVerilogHDLParser.Fixed_point_number, SysVerilogHDLParser.Hex_number, SysVerilogHDLParser.Octal_number, SysVerilogHDLParser.Real_exp_form]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2871
                self.width_type_cast()
                pass
            elif token in [SysVerilogHDLParser.Signed, SysVerilogHDLParser.Unsigned]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2872
                self.sign_type_cast()
                pass
            elif token in [SysVerilogHDLParser.Quote]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2873
                self.null_type_cast()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_callContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_function_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_function_identifierContext,0)


        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def function_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_call" ):
                listener.enterFunction_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_call" ):
                listener.exitFunction_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_call" ):
                return visitor.visitFunction_call(self)
            else:
                return visitor.visitChildren(self)




    def function_call(self):

        localctx = SysVerilogHDLParser.Function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 778, self.RULE_function_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2876
            self.hierarchical_function_identifier()
            self.state = 2877
            self.attribute_instance_star()
            self.state = 2878
            self.function_interface_assignments()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_function_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_function_identifier" ):
                listener.enterHierarchical_function_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_function_identifier" ):
                listener.exitHierarchical_function_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_function_identifier" ):
                return visitor.visitHierarchical_function_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_function_identifier(self):

        localctx = SysVerilogHDLParser.Hierarchical_function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 780, self.RULE_hierarchical_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2880
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Function_interface_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def list_of_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_function_interface_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFunction_interface_assignments" ):
                listener.enterFunction_interface_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFunction_interface_assignments" ):
                listener.exitFunction_interface_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFunction_interface_assignments" ):
                return visitor.visitFunction_interface_assignments(self)
            else:
                return visitor.visitChildren(self)




    def function_interface_assignments(self):

        localctx = SysVerilogHDLParser.Function_interface_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 782, self.RULE_function_interface_assignments)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2882
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2884
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if (((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.T__1) | (1 << SysVerilogHDLParser.T__2) | (1 << SysVerilogHDLParser.T__3) | (1 << SysVerilogHDLParser.T__4) | (1 << SysVerilogHDLParser.T__5) | (1 << SysVerilogHDLParser.T__6) | (1 << SysVerilogHDLParser.T__7) | (1 << SysVerilogHDLParser.T__8) | (1 << SysVerilogHDLParser.T__9) | (1 << SysVerilogHDLParser.T__10) | (1 << SysVerilogHDLParser.T__26) | (1 << SysVerilogHDLParser.T__27) | (1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Fixed_point_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number) | (1 << SysVerilogHDLParser.Real_exp_form))) != 0) or _la==SysVerilogHDLParser.Int or _la==SysVerilogHDLParser.Signed or ((((_la - 188)) & ~0x3f) == 0 and ((1 << (_la - 188)) & ((1 << (SysVerilogHDLParser.Unsigned - 188)) | (1 << (SysVerilogHDLParser.Dollar_Identifier - 188)) | (1 << (SysVerilogHDLParser.Escaped_identifier - 188)) | (1 << (SysVerilogHDLParser.Simple_identifier - 188)) | (1 << (SysVerilogHDLParser.String_literal - 188)) | (1 << (SysVerilogHDLParser.Dot - 188)) | (1 << (SysVerilogHDLParser.Left_curly_bracket - 188)) | (1 << (SysVerilogHDLParser.Open_parenthesis - 188)) | (1 << (SysVerilogHDLParser.Quote - 188)) | (1 << (SysVerilogHDLParser.Tilde - 188)))) != 0):
                self.state = 2883
                self.list_of_interface_assignments()


            self.state = 2886
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_function_callContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def system_function_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.System_function_identifierContext,0)


        def function_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_system_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_function_call" ):
                listener.enterSystem_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_function_call" ):
                listener.exitSystem_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_function_call" ):
                return visitor.visitSystem_function_call(self)
            else:
                return visitor.visitChildren(self)




    def system_function_call(self):

        localctx = SysVerilogHDLParser.System_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 784, self.RULE_system_function_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2888
            self.system_function_identifier()
            self.state = 2890
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,223,self._ctx)
            if la_ == 1:
                self.state = 2889
                self.function_interface_assignments()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class System_function_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Dollar_Identifier(self):
            return self.getToken(SysVerilogHDLParser.Dollar_Identifier, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_system_function_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSystem_function_identifier" ):
                listener.enterSystem_function_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSystem_function_identifier" ):
                listener.exitSystem_function_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSystem_function_identifier" ):
                return visitor.visitSystem_function_identifier(self)
            else:
                return visitor.visitChildren(self)




    def system_function_identifier(self):

        localctx = SysVerilogHDLParser.System_function_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 786, self.RULE_system_function_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2892
            self.match(SysVerilogHDLParser.Dollar_Identifier)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Constant_function_callContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def function_call(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_callContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_constant_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConstant_function_call" ):
                listener.enterConstant_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConstant_function_call" ):
                listener.exitConstant_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConstant_function_call" ):
                return visitor.visitConstant_function_call(self)
            else:
                return visitor.visitChildren(self)




    def constant_function_call(self):

        localctx = SysVerilogHDLParser.Constant_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 788, self.RULE_constant_function_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2894
            self.function_call()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Imported_function_callContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def imported_function_hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Imported_function_hierarchical_identifierContext,0)


        def attribute_instance_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instance_starContext,0)


        def function_interface_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Function_interface_assignmentsContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_imported_function_call

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterImported_function_call" ):
                listener.enterImported_function_call(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitImported_function_call" ):
                listener.exitImported_function_call(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitImported_function_call" ):
                return visitor.visitImported_function_call(self)
            else:
                return visitor.visitChildren(self)




    def imported_function_call(self):

        localctx = SysVerilogHDLParser.Imported_function_callContext(self, self._ctx, self.state)
        self.enterRule(localctx, 790, self.RULE_imported_function_call)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2896
            self.imported_function_hierarchical_identifier()
            self.state = 2897
            self.attribute_instance_star()
            self.state = 2898
            self.function_interface_assignments()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Imported_function_hierarchical_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def imported_hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Imported_hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_imported_function_hierarchical_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterImported_function_hierarchical_identifier" ):
                listener.enterImported_function_hierarchical_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitImported_function_hierarchical_identifier" ):
                listener.exitImported_function_hierarchical_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitImported_function_hierarchical_identifier" ):
                return visitor.visitImported_function_hierarchical_identifier(self)
            else:
                return visitor.visitChildren(self)




    def imported_function_hierarchical_identifier(self):

        localctx = SysVerilogHDLParser.Imported_function_hierarchical_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 792, self.RULE_imported_function_hierarchical_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2900
            self.imported_hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Primary_hierarchical_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_primary_hierarchical_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrimary_hierarchical_identifier" ):
                listener.enterPrimary_hierarchical_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrimary_hierarchical_identifier" ):
                listener.exitPrimary_hierarchical_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrimary_hierarchical_identifier" ):
                return visitor.visitPrimary_hierarchical_identifier(self)
            else:
                return visitor.visitChildren(self)




    def primary_hierarchical_identifier(self):

        localctx = SysVerilogHDLParser.Primary_hierarchical_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 794, self.RULE_primary_hierarchical_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2902
            self.hierarchical_identifier()
            self.state = 2904
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,224,self._ctx)
            if la_ == 1:
                self.state = 2903
                self.dimension_plus()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Primary_imported_hierarchical_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def imported_hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Imported_hierarchical_identifierContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_primary_imported_hierarchical_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPrimary_imported_hierarchical_identifier" ):
                listener.enterPrimary_imported_hierarchical_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPrimary_imported_hierarchical_identifier" ):
                listener.exitPrimary_imported_hierarchical_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPrimary_imported_hierarchical_identifier" ):
                return visitor.visitPrimary_imported_hierarchical_identifier(self)
            else:
                return visitor.visitChildren(self)




    def primary_imported_hierarchical_identifier(self):

        localctx = SysVerilogHDLParser.Primary_imported_hierarchical_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 796, self.RULE_primary_imported_hierarchical_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2906
            self.imported_hierarchical_identifier()
            self.state = 2908
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,225,self._ctx)
            if la_ == 1:
                self.state = 2907
                self.dimension_plus()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Imported_hierarchical_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def Double_colon(self):
            return self.getToken(SysVerilogHDLParser.Double_colon, 0)

        def hierarchical_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_imported_hierarchical_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterImported_hierarchical_identifier" ):
                listener.enterImported_hierarchical_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitImported_hierarchical_identifier" ):
                listener.exitImported_hierarchical_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitImported_hierarchical_identifier" ):
                return visitor.visitImported_hierarchical_identifier(self)
            else:
                return visitor.visitChildren(self)




    def imported_hierarchical_identifier(self):

        localctx = SysVerilogHDLParser.Imported_hierarchical_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 798, self.RULE_imported_hierarchical_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2910
            self.identifier()
            self.state = 2911
            self.match(SysVerilogHDLParser.Double_colon)
            self.state = 2912
            self.hierarchical_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Parenthesis_expressionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_parenthesis_expression

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterParenthesis_expression" ):
                listener.enterParenthesis_expression(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitParenthesis_expression" ):
                listener.exitParenthesis_expression(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitParenthesis_expression" ):
                return visitor.visitParenthesis_expression(self)
            else:
                return visitor.visitChildren(self)




    def parenthesis_expression(self):

        localctx = SysVerilogHDLParser.Parenthesis_expressionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 800, self.RULE_parenthesis_expression)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2914
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 2915
            self.expression()
            self.state = 2916
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class ConcatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Left_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Left_curly_bracket, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def comma_expression_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_expression_starContext,0)


        def Right_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Right_curly_bracket, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterConcatenation" ):
                listener.enterConcatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitConcatenation" ):
                listener.exitConcatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitConcatenation" ):
                return visitor.visitConcatenation(self)
            else:
                return visitor.visitChildren(self)




    def concatenation(self):

        localctx = SysVerilogHDLParser.ConcatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 802, self.RULE_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2918
            self.match(SysVerilogHDLParser.Left_curly_bracket)
            self.state = 2919
            self.expression()
            self.state = 2920
            self.comma_expression_star()
            self.state = 2921
            self.match(SysVerilogHDLParser.Right_curly_bracket)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Multiple_concatenationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Left_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Left_curly_bracket, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def concatenation(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ConcatenationContext,0)


        def Right_curly_bracket(self):
            return self.getToken(SysVerilogHDLParser.Right_curly_bracket, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_multiple_concatenation

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterMultiple_concatenation" ):
                listener.enterMultiple_concatenation(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitMultiple_concatenation" ):
                listener.exitMultiple_concatenation(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitMultiple_concatenation" ):
                return visitor.visitMultiple_concatenation(self)
            else:
                return visitor.visitChildren(self)




    def multiple_concatenation(self):

        localctx = SysVerilogHDLParser.Multiple_concatenationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 804, self.RULE_multiple_concatenation)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2923
            self.match(SysVerilogHDLParser.Left_curly_bracket)
            self.state = 2924
            self.expression()
            self.state = 2925
            self.concatenation()
            self.state = 2926
            self.match(SysVerilogHDLParser.Right_curly_bracket)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_expression_plusContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_expression_plus

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_expression_plus" ):
                listener.enterComma_expression_plus(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_expression_plus" ):
                listener.exitComma_expression_plus(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_expression_plus" ):
                return visitor.visitComma_expression_plus(self)
            else:
                return visitor.visitChildren(self)




    def comma_expression_plus(self):

        localctx = SysVerilogHDLParser.Comma_expression_plusContext(self, self._ctx, self.state)
        self.enterRule(localctx, 806, self.RULE_comma_expression_plus)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2930 
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while True:
                self.state = 2928
                self.match(SysVerilogHDLParser.Comma)
                self.state = 2929
                self.expression()
                self.state = 2932 
                self._errHandler.sync(self)
                _la = self._input.LA(1)
                if not (_la==SysVerilogHDLParser.Comma):
                    break

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_expression_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def expression(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.ExpressionContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_expression_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_expression_star" ):
                listener.enterComma_expression_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_expression_star" ):
                listener.exitComma_expression_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_expression_star" ):
                return visitor.visitComma_expression_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_expression_star(self):

        localctx = SysVerilogHDLParser.Comma_expression_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 808, self.RULE_comma_expression_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2938
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 2934
                self.match(SysVerilogHDLParser.Comma)
                self.state = 2935
                self.expression()
                self.state = 2940
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Typedef_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Typedef(self):
            return self.getToken(SysVerilogHDLParser.Typedef, 0)

        def typedef_definition(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Typedef_definitionContext,0)


        def typedef_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Typedef_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_typedef_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTypedef_declaration" ):
                listener.enterTypedef_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTypedef_declaration" ):
                listener.exitTypedef_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTypedef_declaration" ):
                return visitor.visitTypedef_declaration(self)
            else:
                return visitor.visitChildren(self)




    def typedef_declaration(self):

        localctx = SysVerilogHDLParser.Typedef_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 810, self.RULE_typedef_declaration)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2941
            self.match(SysVerilogHDLParser.Typedef)
            self.state = 2942
            self.typedef_definition()
            self.state = 2943
            self.typedef_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Typedef_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_typedef_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTypedef_identifier" ):
                listener.enterTypedef_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTypedef_identifier" ):
                listener.exitTypedef_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTypedef_identifier" ):
                return visitor.visitTypedef_identifier(self)
            else:
                return visitor.visitChildren(self)




    def typedef_identifier(self):

        localctx = SysVerilogHDLParser.Typedef_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 812, self.RULE_typedef_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2945
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Typedef_definitionContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def typedef_definition_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Typedef_definition_typeContext,0)


        def enumerated_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Enumerated_typeContext,0)


        def struct_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Struct_typeContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_typedef_definition

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTypedef_definition" ):
                listener.enterTypedef_definition(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTypedef_definition" ):
                listener.exitTypedef_definition(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTypedef_definition" ):
                return visitor.visitTypedef_definition(self)
            else:
                return visitor.visitChildren(self)




    def typedef_definition(self):

        localctx = SysVerilogHDLParser.Typedef_definitionContext(self, self._ctx, self.state)
        self.enterRule(localctx, 814, self.RULE_typedef_definition)
        try:
            self.state = 2950
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte, SysVerilogHDLParser.Logic, SysVerilogHDLParser.NONE, SysVerilogHDLParser.Reg, SysVerilogHDLParser.Supply0, SysVerilogHDLParser.Supply1, SysVerilogHDLParser.Tri, SysVerilogHDLParser.Tri_and, SysVerilogHDLParser.Tri_or, SysVerilogHDLParser.Tri_reg, SysVerilogHDLParser.Tri0, SysVerilogHDLParser.Tri1, SysVerilogHDLParser.Uwire, SysVerilogHDLParser.Wand, SysVerilogHDLParser.Wire, SysVerilogHDLParser.Wor, SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2947
                self.typedef_definition_type()
                pass
            elif token in [SysVerilogHDLParser.Enum]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2948
                self.enumerated_type()
                pass
            elif token in [SysVerilogHDLParser.Struct, SysVerilogHDLParser.UnionStruct]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2949
                self.struct_type()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Typedef_definition_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def complex_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Complex_typeContext,0)


        def typedef_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Typedef_typeContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_typedef_definition_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTypedef_definition_type" ):
                listener.enterTypedef_definition_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTypedef_definition_type" ):
                listener.exitTypedef_definition_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTypedef_definition_type" ):
                return visitor.visitTypedef_definition_type(self)
            else:
                return visitor.visitChildren(self)




    def typedef_definition_type(self):

        localctx = SysVerilogHDLParser.Typedef_definition_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 816, self.RULE_typedef_definition_type)
        try:
            self.state = 2954
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,229,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 2952
                self.complex_type()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 2953
                self.typedef_type()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Complex_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def typedef_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Typedef_typeContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def Signed(self):
            return self.getToken(SysVerilogHDLParser.Signed, 0)

        def Unsigned(self):
            return self.getToken(SysVerilogHDLParser.Unsigned, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_complex_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComplex_type" ):
                listener.enterComplex_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComplex_type" ):
                listener.exitComplex_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComplex_type" ):
                return visitor.visitComplex_type(self)
            else:
                return visitor.visitChildren(self)




    def complex_type(self):

        localctx = SysVerilogHDLParser.Complex_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 818, self.RULE_complex_type)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2956
            self.typedef_type()
            self.state = 2958
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned:
                self.state = 2957
                _la = self._input.LA(1)
                if not(_la==SysVerilogHDLParser.Signed or _la==SysVerilogHDLParser.Unsigned):
                    self._errHandler.recoverInline(self)
                else:
                    self._errHandler.reportMatch(self)
                    self.consume()


            self.state = 2961
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Left_bracket:
                self.state = 2960
                self.dimension_plus()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Typedef_typeContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Reg(self):
            return self.getToken(SysVerilogHDLParser.Reg, 0)

        def Logic(self):
            return self.getToken(SysVerilogHDLParser.Logic, 0)

        def bits_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_typeContext,0)


        def net_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_typeContext,0)


        def user_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.User_typeContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_typedef_type

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTypedef_type" ):
                listener.enterTypedef_type(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTypedef_type" ):
                listener.exitTypedef_type(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTypedef_type" ):
                return visitor.visitTypedef_type(self)
            else:
                return visitor.visitChildren(self)




    def typedef_type(self):

        localctx = SysVerilogHDLParser.Typedef_typeContext(self, self._ctx, self.state)
        self.enterRule(localctx, 820, self.RULE_typedef_type)
        try:
            self.state = 2968
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Reg]:
                self.enterOuterAlt(localctx, 1)
                self.state = 2963
                self.match(SysVerilogHDLParser.Reg)
                pass
            elif token in [SysVerilogHDLParser.Logic]:
                self.enterOuterAlt(localctx, 2)
                self.state = 2964
                self.match(SysVerilogHDLParser.Logic)
                pass
            elif token in [SysVerilogHDLParser.Bit, SysVerilogHDLParser.Byte]:
                self.enterOuterAlt(localctx, 3)
                self.state = 2965
                self.bits_type()
                pass
            elif token in [SysVerilogHDLParser.NONE, SysVerilogHDLParser.Supply0, SysVerilogHDLParser.Supply1, SysVerilogHDLParser.Tri, SysVerilogHDLParser.Tri_and, SysVerilogHDLParser.Tri_or, SysVerilogHDLParser.Tri_reg, SysVerilogHDLParser.Tri0, SysVerilogHDLParser.Tri1, SysVerilogHDLParser.Uwire, SysVerilogHDLParser.Wand, SysVerilogHDLParser.Wire, SysVerilogHDLParser.Wor]:
                self.enterOuterAlt(localctx, 4)
                self.state = 2966
                self.net_type()
                pass
            elif token in [SysVerilogHDLParser.Escaped_identifier, SysVerilogHDLParser.Simple_identifier]:
                self.enterOuterAlt(localctx, 5)
                self.state = 2967
                self.user_type()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Par_blockContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Fork(self):
            return self.getToken(SysVerilogHDLParser.Fork, 0)

        def block_item_declaration_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_item_declaration_starContext,0)


        def statement_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_starContext,0)


        def join_keyword(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Join_keywordContext,0)


        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_identifierContext,0)


        def colon_block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Colon_block_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_par_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterPar_block" ):
                listener.enterPar_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitPar_block" ):
                listener.exitPar_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitPar_block" ):
                return visitor.visitPar_block(self)
            else:
                return visitor.visitChildren(self)




    def par_block(self):

        localctx = SysVerilogHDLParser.Par_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 822, self.RULE_par_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2970
            self.match(SysVerilogHDLParser.Fork)
            self.state = 2973
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 2971
                self.match(SysVerilogHDLParser.Colon)
                self.state = 2972
                self.block_identifier()


            self.state = 2975
            self.block_item_declaration_star()
            self.state = 2976
            self.statement_star()
            self.state = 2977
            self.join_keyword()
            self.state = 2979
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 2978
                self.colon_block_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Seq_blockContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Begin(self):
            return self.getToken(SysVerilogHDLParser.Begin, 0)

        def block_item_declaration_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_item_declaration_starContext,0)


        def statement_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_starContext,0)


        def End(self):
            return self.getToken(SysVerilogHDLParser.End, 0)

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_identifierContext,0)


        def colon_block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Colon_block_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_seq_block

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterSeq_block" ):
                listener.enterSeq_block(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitSeq_block" ):
                listener.exitSeq_block(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitSeq_block" ):
                return visitor.visitSeq_block(self)
            else:
                return visitor.visitChildren(self)




    def seq_block(self):

        localctx = SysVerilogHDLParser.Seq_blockContext(self, self._ctx, self.state)
        self.enterRule(localctx, 824, self.RULE_seq_block)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2981
            self.match(SysVerilogHDLParser.Begin)
            self.state = 2984
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 2982
                self.match(SysVerilogHDLParser.Colon)
                self.state = 2983
                self.block_identifier()


            self.state = 2986
            self.block_item_declaration_star()
            self.state = 2987
            self.statement_star()
            self.state = 2988
            self.match(SysVerilogHDLParser.End)
            self.state = 2990
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Colon:
                self.state = 2989
                self.colon_block_identifier()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_identifier" ):
                listener.enterBlock_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_identifier" ):
                listener.exitBlock_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_identifier" ):
                return visitor.visitBlock_identifier(self)
            else:
                return visitor.visitChildren(self)




    def block_identifier(self):

        localctx = SysVerilogHDLParser.Block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 826, self.RULE_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2992
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Colon_block_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Colon(self):
            return self.getToken(SysVerilogHDLParser.Colon, 0)

        def block_identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_identifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_colon_block_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterColon_block_identifier" ):
                listener.enterColon_block_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitColon_block_identifier" ):
                listener.exitColon_block_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitColon_block_identifier" ):
                return visitor.visitColon_block_identifier(self)
            else:
                return visitor.visitChildren(self)




    def colon_block_identifier(self):

        localctx = SysVerilogHDLParser.Colon_block_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 828, self.RULE_colon_block_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 2994
            self.match(SysVerilogHDLParser.Colon)
            self.state = 2995
            self.block_identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_item_declaration_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration_semicolon(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Block_item_declaration_semicolonContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Block_item_declaration_semicolonContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_block_item_declaration_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_item_declaration_star" ):
                listener.enterBlock_item_declaration_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_item_declaration_star" ):
                listener.exitBlock_item_declaration_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_item_declaration_star" ):
                return visitor.visitBlock_item_declaration_star(self)
            else:
                return visitor.visitChildren(self)




    def block_item_declaration_star(self):

        localctx = SysVerilogHDLParser.Block_item_declaration_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 830, self.RULE_block_item_declaration_star)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3000
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,237,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 2997
                    self.block_item_declaration_semicolon() 
                self.state = 3002
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,237,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_item_declaration_semicolonContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def block_item_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Block_item_declarationContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_block_item_declaration_semicolon

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_item_declaration_semicolon" ):
                listener.enterBlock_item_declaration_semicolon(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_item_declaration_semicolon" ):
                listener.exitBlock_item_declaration_semicolon(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_item_declaration_semicolon" ):
                return visitor.visitBlock_item_declaration_semicolon(self)
            else:
                return visitor.visitChildren(self)




    def block_item_declaration_semicolon(self):

        localctx = SysVerilogHDLParser.Block_item_declaration_semicolonContext(self, self._ctx, self.state)
        self.enterRule(localctx, 832, self.RULE_block_item_declaration_semicolon)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3003
            self.block_item_declaration()
            self.state = 3004
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Block_item_declarationContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def reg_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Reg_declarationContext,0)


        def event_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Event_declarationContext,0)


        def logic_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Logic_declarationContext,0)


        def bits_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Bits_declarationContext,0)


        def integer_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integer_declarationContext,0)


        def int_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Int_declarationContext,0)


        def local_parameter_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Local_parameter_declarationContext,0)


        def parameter_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Parameter_declarationContext,0)


        def real_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Real_declarationContext,0)


        def realtime_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Realtime_declarationContext,0)


        def time_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Time_declarationContext,0)


        def string_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.String_declarationContext,0)


        def usertype_variable_declaration(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Usertype_variable_declarationContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_block_item_declaration

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterBlock_item_declaration" ):
                listener.enterBlock_item_declaration(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitBlock_item_declaration" ):
                listener.exitBlock_item_declaration(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitBlock_item_declaration" ):
                return visitor.visitBlock_item_declaration(self)
            else:
                return visitor.visitChildren(self)




    def block_item_declaration(self):

        localctx = SysVerilogHDLParser.Block_item_declarationContext(self, self._ctx, self.state)
        self.enterRule(localctx, 834, self.RULE_block_item_declaration)
        try:
            self.state = 3019
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,238,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3006
                self.reg_declaration()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3007
                self.event_declaration()
                pass

            elif la_ == 3:
                self.enterOuterAlt(localctx, 3)
                self.state = 3008
                self.logic_declaration()
                pass

            elif la_ == 4:
                self.enterOuterAlt(localctx, 4)
                self.state = 3009
                self.bits_declaration()
                pass

            elif la_ == 5:
                self.enterOuterAlt(localctx, 5)
                self.state = 3010
                self.integer_declaration()
                pass

            elif la_ == 6:
                self.enterOuterAlt(localctx, 6)
                self.state = 3011
                self.int_declaration()
                pass

            elif la_ == 7:
                self.enterOuterAlt(localctx, 7)
                self.state = 3012
                self.local_parameter_declaration()
                pass

            elif la_ == 8:
                self.enterOuterAlt(localctx, 8)
                self.state = 3013
                self.parameter_declaration()
                pass

            elif la_ == 9:
                self.enterOuterAlt(localctx, 9)
                self.state = 3014
                self.real_declaration()
                pass

            elif la_ == 10:
                self.enterOuterAlt(localctx, 10)
                self.state = 3015
                self.realtime_declaration()
                pass

            elif la_ == 11:
                self.enterOuterAlt(localctx, 11)
                self.state = 3016
                self.time_declaration()
                pass

            elif la_ == 12:
                self.enterOuterAlt(localctx, 12)
                self.state = 3017
                self.string_declaration()
                pass

            elif la_ == 13:
                self.enterOuterAlt(localctx, 13)
                self.state = 3018
                self.usertype_variable_declaration()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Join_keywordContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Join(self):
            return self.getToken(SysVerilogHDLParser.Join, 0)

        def Join_none(self):
            return self.getToken(SysVerilogHDLParser.Join_none, 0)

        def Join_any(self):
            return self.getToken(SysVerilogHDLParser.Join_any, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_join_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterJoin_keyword" ):
                listener.enterJoin_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitJoin_keyword" ):
                listener.exitJoin_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitJoin_keyword" ):
                return visitor.visitJoin_keyword(self)
            else:
                return visitor.visitChildren(self)




    def join_keyword(self):

        localctx = SysVerilogHDLParser.Join_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 836, self.RULE_join_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3021
            _la = self._input.LA(1)
            if not(((((_la - 111)) & ~0x3f) == 0 and ((1 << (_la - 111)) & ((1 << (SysVerilogHDLParser.Join - 111)) | (1 << (SysVerilogHDLParser.Join_any - 111)) | (1 << (SysVerilogHDLParser.Join_none - 111)))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Continuous_assignContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Assign(self):
            return self.getToken(SysVerilogHDLParser.Assign, 0)

        def list_of_variable_assignments(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.List_of_variable_assignmentsContext,0)


        def semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.SemicolonContext,0)


        def drive_strength(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Drive_strengthContext,0)


        def delay(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.DelayContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_continuous_assign

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterContinuous_assign" ):
                listener.enterContinuous_assign(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitContinuous_assign" ):
                listener.exitContinuous_assign(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitContinuous_assign" ):
                return visitor.visitContinuous_assign(self)
            else:
                return visitor.visitChildren(self)




    def continuous_assign(self):

        localctx = SysVerilogHDLParser.Continuous_assignContext(self, self._ctx, self.state)
        self.enterRule(localctx, 838, self.RULE_continuous_assign)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3023
            self.match(SysVerilogHDLParser.Assign)
            self.state = 3025
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Open_parenthesis:
                self.state = 3024
                self.drive_strength()


            self.state = 3028
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            if _la==SysVerilogHDLParser.Hash:
                self.state = 3027
                self.delay()


            self.state = 3030
            self.list_of_variable_assignments()
            self.state = 3031
            self.semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class List_of_variable_assignmentsContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_assignmentContext,0)


        def comma_variable_assignment_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Comma_variable_assignment_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_list_of_variable_assignments

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterList_of_variable_assignments" ):
                listener.enterList_of_variable_assignments(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitList_of_variable_assignments" ):
                listener.exitList_of_variable_assignments(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitList_of_variable_assignments" ):
                return visitor.visitList_of_variable_assignments(self)
            else:
                return visitor.visitChildren(self)




    def list_of_variable_assignments(self):

        localctx = SysVerilogHDLParser.List_of_variable_assignmentsContext(self, self._ctx, self.state)
        self.enterRule(localctx, 840, self.RULE_list_of_variable_assignments)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3033
            self.variable_assignment()
            self.state = 3034
            self.comma_variable_assignment_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_variable_assignment_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def comma_variable_assignment(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Comma_variable_assignmentContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Comma_variable_assignmentContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_variable_assignment_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_variable_assignment_star" ):
                listener.enterComma_variable_assignment_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_variable_assignment_star" ):
                listener.exitComma_variable_assignment_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_variable_assignment_star" ):
                return visitor.visitComma_variable_assignment_star(self)
            else:
                return visitor.visitChildren(self)




    def comma_variable_assignment_star(self):

        localctx = SysVerilogHDLParser.Comma_variable_assignment_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 842, self.RULE_comma_variable_assignment_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3039
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 3036
                self.comma_variable_assignment()
                self.state = 3041
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Comma_variable_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self):
            return self.getToken(SysVerilogHDLParser.Comma, 0)

        def variable_assignment(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_assignmentContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_comma_variable_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterComma_variable_assignment" ):
                listener.enterComma_variable_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitComma_variable_assignment" ):
                listener.exitComma_variable_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitComma_variable_assignment" ):
                return visitor.visitComma_variable_assignment(self)
            else:
                return visitor.visitChildren(self)




    def comma_variable_assignment(self):

        localctx = SysVerilogHDLParser.Comma_variable_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 844, self.RULE_comma_variable_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3042
            self.match(SysVerilogHDLParser.Comma)
            self.state = 3043
            self.variable_assignment()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Variable_assignmentContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def variable_lvalue(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Variable_lvalueContext,0)


        def Equal(self):
            return self.getToken(SysVerilogHDLParser.Equal, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_variable_assignment

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterVariable_assignment" ):
                listener.enterVariable_assignment(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitVariable_assignment" ):
                listener.exitVariable_assignment(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitVariable_assignment" ):
                return visitor.visitVariable_assignment(self)
            else:
                return visitor.visitChildren(self)




    def variable_assignment(self):

        localctx = SysVerilogHDLParser.Variable_assignmentContext(self, self._ctx, self.state)
        self.enterRule(localctx, 846, self.RULE_variable_assignment)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3045
            self.variable_lvalue()
            self.state = 3046
            self.match(SysVerilogHDLParser.Equal)
            self.state = 3047
            self.expression()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Initial_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Initial(self):
            return self.getToken(SysVerilogHDLParser.Initial, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_initial_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterInitial_construct" ):
                listener.enterInitial_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitInitial_construct" ):
                listener.exitInitial_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitInitial_construct" ):
                return visitor.visitInitial_construct(self)
            else:
                return visitor.visitChildren(self)




    def initial_construct(self):

        localctx = SysVerilogHDLParser.Initial_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 848, self.RULE_initial_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3049
            self.match(SysVerilogHDLParser.Initial)
            self.state = 3050
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Final_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Final(self):
            return self.getToken(SysVerilogHDLParser.Final, 0)

        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_final_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterFinal_construct" ):
                listener.enterFinal_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitFinal_construct" ):
                listener.exitFinal_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitFinal_construct" ):
                return visitor.visitFinal_construct(self)
            else:
                return visitor.visitChildren(self)




    def final_construct(self):

        localctx = SysVerilogHDLParser.Final_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 850, self.RULE_final_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3052
            self.match(SysVerilogHDLParser.Final)
            self.state = 3053
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Always_keywordContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Always(self):
            return self.getToken(SysVerilogHDLParser.Always, 0)

        def Always_comb(self):
            return self.getToken(SysVerilogHDLParser.Always_comb, 0)

        def Always_ff(self):
            return self.getToken(SysVerilogHDLParser.Always_ff, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_always_keyword

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAlways_keyword" ):
                listener.enterAlways_keyword(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAlways_keyword" ):
                listener.exitAlways_keyword(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAlways_keyword" ):
                return visitor.visitAlways_keyword(self)
            else:
                return visitor.visitChildren(self)




    def always_keyword(self):

        localctx = SysVerilogHDLParser.Always_keywordContext(self, self._ctx, self.state)
        self.enterRule(localctx, 852, self.RULE_always_keyword)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3055
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.Always) | (1 << SysVerilogHDLParser.Always_comb) | (1 << SysVerilogHDLParser.Always_ff))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Always_constructContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def always_keyword(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Always_keywordContext,0)


        def statement_semicolon(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Statement_semicolonContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_always_construct

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAlways_construct" ):
                listener.enterAlways_construct(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAlways_construct" ):
                listener.exitAlways_construct(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAlways_construct" ):
                return visitor.visitAlways_construct(self)
            else:
                return visitor.visitChildren(self)




    def always_construct(self):

        localctx = SysVerilogHDLParser.Always_constructContext(self, self._ctx, self.state)
        self.enterRule(localctx, 854, self.RULE_always_construct)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3057
            self.always_keyword()
            self.state = 3058
            self.statement_semicolon()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attribute_instance_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attribute_instance(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Attribute_instanceContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Attribute_instanceContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attribute_instance_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttribute_instance_star" ):
                listener.enterAttribute_instance_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttribute_instance_star" ):
                listener.exitAttribute_instance_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttribute_instance_star" ):
                return visitor.visitAttribute_instance_star(self)
            else:
                return visitor.visitChildren(self)




    def attribute_instance_star(self):

        localctx = SysVerilogHDLParser.Attribute_instance_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 856, self.RULE_attribute_instance_star)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3063
            self._errHandler.sync(self)
            _alt = self._interp.adaptivePredict(self._input,242,self._ctx)
            while _alt!=2 and _alt!=ATN.INVALID_ALT_NUMBER:
                if _alt==1:
                    self.state = 3060
                    self.attribute_instance() 
                self.state = 3065
                self._errHandler.sync(self)
                _alt = self._interp.adaptivePredict(self._input,242,self._ctx)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attribute_instanceContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Open_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Open_parenthesis, 0)

        def Star(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Star)
            else:
                return self.getToken(SysVerilogHDLParser.Star, i)

        def attr_spec(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_specContext,0)


        def attr_spec_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_spec_starContext,0)


        def Close_parenthesis(self):
            return self.getToken(SysVerilogHDLParser.Close_parenthesis, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attribute_instance

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttribute_instance" ):
                listener.enterAttribute_instance(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttribute_instance" ):
                listener.exitAttribute_instance(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttribute_instance" ):
                return visitor.visitAttribute_instance(self)
            else:
                return visitor.visitChildren(self)




    def attribute_instance(self):

        localctx = SysVerilogHDLParser.Attribute_instanceContext(self, self._ctx, self.state)
        self.enterRule(localctx, 858, self.RULE_attribute_instance)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3066
            self.match(SysVerilogHDLParser.Open_parenthesis)
            self.state = 3067
            self.match(SysVerilogHDLParser.Star)
            self.state = 3068
            self.attr_spec()
            self.state = 3069
            self.attr_spec_star()
            self.state = 3070
            self.match(SysVerilogHDLParser.Star)
            self.state = 3071
            self.match(SysVerilogHDLParser.Close_parenthesis)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_spec_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Comma(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Comma)
            else:
                return self.getToken(SysVerilogHDLParser.Comma, i)

        def attr_spec(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Attr_specContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Attr_specContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_spec_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_spec_star" ):
                listener.enterAttr_spec_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_spec_star" ):
                listener.exitAttr_spec_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_spec_star" ):
                return visitor.visitAttr_spec_star(self)
            else:
                return visitor.visitChildren(self)




    def attr_spec_star(self):

        localctx = SysVerilogHDLParser.Attr_spec_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 860, self.RULE_attr_spec_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3077
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Comma:
                self.state = 3073
                self.match(SysVerilogHDLParser.Comma)
                self.state = 3074
                self.attr_spec()
                self.state = 3079
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_specContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def attr_name(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Attr_nameContext,0)


        def Equal(self):
            return self.getToken(SysVerilogHDLParser.Equal, 0)

        def expression(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.ExpressionContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_spec

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_spec" ):
                listener.enterAttr_spec(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_spec" ):
                listener.exitAttr_spec(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_spec" ):
                return visitor.visitAttr_spec(self)
            else:
                return visitor.visitChildren(self)




    def attr_spec(self):

        localctx = SysVerilogHDLParser.Attr_specContext(self, self._ctx, self.state)
        self.enterRule(localctx, 862, self.RULE_attr_spec)
        try:
            self.state = 3085
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,244,self._ctx)
            if la_ == 1:
                self.enterOuterAlt(localctx, 1)
                self.state = 3080
                self.attr_name()
                self.state = 3081
                self.match(SysVerilogHDLParser.Equal)
                self.state = 3082
                self.expression()
                pass

            elif la_ == 2:
                self.enterOuterAlt(localctx, 2)
                self.state = 3084
                self.attr_name()
                pass


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Attr_nameContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_attr_name

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterAttr_name" ):
                listener.enterAttr_name(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitAttr_name" ):
                listener.exitAttr_name(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitAttr_name" ):
                return visitor.visitAttr_name(self)
            else:
                return visitor.visitChildren(self)




    def attr_name(self):

        localctx = SysVerilogHDLParser.Attr_nameContext(self, self._ctx, self.state)
        self.enterRule(localctx, 864, self.RULE_attr_name)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3087
            self.identifier()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class IdentifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Simple_identifier(self):
            return self.getToken(SysVerilogHDLParser.Simple_identifier, 0)

        def Escaped_identifier(self):
            return self.getToken(SysVerilogHDLParser.Escaped_identifier, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIdentifier" ):
                listener.enterIdentifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIdentifier" ):
                listener.exitIdentifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIdentifier" ):
                return visitor.visitIdentifier(self)
            else:
                return visitor.visitChildren(self)




    def identifier(self):

        localctx = SysVerilogHDLParser.IdentifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 866, self.RULE_identifier)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3089
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Escaped_identifier or _la==SysVerilogHDLParser.Simple_identifier):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_identifierContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def hierarchical_identifier_branch_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifier_branch_itemContext,0)


        def dot_hierarchical_identifier_branch_item_star(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dot_hierarchical_identifier_branch_item_starContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_identifier

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_identifier" ):
                listener.enterHierarchical_identifier(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_identifier" ):
                listener.exitHierarchical_identifier(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_identifier" ):
                return visitor.visitHierarchical_identifier(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_identifier(self):

        localctx = SysVerilogHDLParser.Hierarchical_identifierContext(self, self._ctx, self.state)
        self.enterRule(localctx, 868, self.RULE_hierarchical_identifier)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3091
            self.hierarchical_identifier_branch_item()
            self.state = 3092
            self.dot_hierarchical_identifier_branch_item_star()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dot_hierarchical_identifier_branch_item_starContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def dot_hierarchical_identifier_branch_item(self, i:int=None):
            if i is None:
                return self.getTypedRuleContexts(SysVerilogHDLParser.Dot_hierarchical_identifier_branch_itemContext)
            else:
                return self.getTypedRuleContext(SysVerilogHDLParser.Dot_hierarchical_identifier_branch_itemContext,i)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_dot_hierarchical_identifier_branch_item_star

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDot_hierarchical_identifier_branch_item_star" ):
                listener.enterDot_hierarchical_identifier_branch_item_star(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDot_hierarchical_identifier_branch_item_star" ):
                listener.exitDot_hierarchical_identifier_branch_item_star(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDot_hierarchical_identifier_branch_item_star" ):
                return visitor.visitDot_hierarchical_identifier_branch_item_star(self)
            else:
                return visitor.visitChildren(self)




    def dot_hierarchical_identifier_branch_item_star(self):

        localctx = SysVerilogHDLParser.Dot_hierarchical_identifier_branch_item_starContext(self, self._ctx, self.state)
        self.enterRule(localctx, 870, self.RULE_dot_hierarchical_identifier_branch_item_star)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3097
            self._errHandler.sync(self)
            _la = self._input.LA(1)
            while _la==SysVerilogHDLParser.Dot:
                self.state = 3094
                self.dot_hierarchical_identifier_branch_item()
                self.state = 3099
                self._errHandler.sync(self)
                _la = self._input.LA(1)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Dot_hierarchical_identifier_branch_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Dot(self):
            return self.getToken(SysVerilogHDLParser.Dot, 0)

        def hierarchical_identifier_branch_item(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Hierarchical_identifier_branch_itemContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_dot_hierarchical_identifier_branch_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDot_hierarchical_identifier_branch_item" ):
                listener.enterDot_hierarchical_identifier_branch_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDot_hierarchical_identifier_branch_item" ):
                listener.exitDot_hierarchical_identifier_branch_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDot_hierarchical_identifier_branch_item" ):
                return visitor.visitDot_hierarchical_identifier_branch_item(self)
            else:
                return visitor.visitChildren(self)




    def dot_hierarchical_identifier_branch_item(self):

        localctx = SysVerilogHDLParser.Dot_hierarchical_identifier_branch_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 872, self.RULE_dot_hierarchical_identifier_branch_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3100
            self.match(SysVerilogHDLParser.Dot)
            self.state = 3101
            self.hierarchical_identifier_branch_item()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Hierarchical_identifier_branch_itemContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def identifier(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.IdentifierContext,0)


        def dimension_plus(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Dimension_plusContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_hierarchical_identifier_branch_item

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterHierarchical_identifier_branch_item" ):
                listener.enterHierarchical_identifier_branch_item(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitHierarchical_identifier_branch_item" ):
                listener.exitHierarchical_identifier_branch_item(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitHierarchical_identifier_branch_item" ):
                return visitor.visitHierarchical_identifier_branch_item(self)
            else:
                return visitor.visitChildren(self)




    def hierarchical_identifier_branch_item(self):

        localctx = SysVerilogHDLParser.Hierarchical_identifier_branch_itemContext(self, self._ctx, self.state)
        self.enterRule(localctx, 874, self.RULE_hierarchical_identifier_branch_item)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3103
            self.identifier()
            self.state = 3105
            self._errHandler.sync(self)
            la_ = self._interp.adaptivePredict(self._input,246,self._ctx)
            if la_ == 1:
                self.state = 3104
                self.dimension_plus()


        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Timescale_compiler_directiveContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Tick_timescale(self):
            return self.getToken(SysVerilogHDLParser.Tick_timescale, 0)

        def Time_literal(self, i:int=None):
            if i is None:
                return self.getTokens(SysVerilogHDLParser.Time_literal)
            else:
                return self.getToken(SysVerilogHDLParser.Time_literal, i)

        def Forward_slash(self):
            return self.getToken(SysVerilogHDLParser.Forward_slash, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_timescale_compiler_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTimescale_compiler_directive" ):
                listener.enterTimescale_compiler_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTimescale_compiler_directive" ):
                listener.exitTimescale_compiler_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTimescale_compiler_directive" ):
                return visitor.visitTimescale_compiler_directive(self)
            else:
                return visitor.visitChildren(self)




    def timescale_compiler_directive(self):

        localctx = SysVerilogHDLParser.Timescale_compiler_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 876, self.RULE_timescale_compiler_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3107
            self.match(SysVerilogHDLParser.Tick_timescale)
            self.state = 3108
            self.match(SysVerilogHDLParser.Time_literal)
            self.state = 3109
            self.match(SysVerilogHDLParser.Forward_slash)
            self.state = 3110
            self.match(SysVerilogHDLParser.Time_literal)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Timeunit_directiveContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Timeunit(self):
            return self.getToken(SysVerilogHDLParser.Timeunit, 0)

        def Time_literal(self):
            return self.getToken(SysVerilogHDLParser.Time_literal, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_timeunit_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTimeunit_directive" ):
                listener.enterTimeunit_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTimeunit_directive" ):
                listener.exitTimeunit_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTimeunit_directive" ):
                return visitor.visitTimeunit_directive(self)
            else:
                return visitor.visitChildren(self)




    def timeunit_directive(self):

        localctx = SysVerilogHDLParser.Timeunit_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 878, self.RULE_timeunit_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3112
            self.match(SysVerilogHDLParser.Timeunit)
            self.state = 3113
            self.match(SysVerilogHDLParser.Time_literal)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Timeprecision_directiveContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Timeprecision(self):
            return self.getToken(SysVerilogHDLParser.Timeprecision, 0)

        def Time_literal(self):
            return self.getToken(SysVerilogHDLParser.Time_literal, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_timeprecision_directive

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterTimeprecision_directive" ):
                listener.enterTimeprecision_directive(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitTimeprecision_directive" ):
                listener.exitTimeprecision_directive(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitTimeprecision_directive" ):
                return visitor.visitTimeprecision_directive(self)
            else:
                return visitor.visitChildren(self)




    def timeprecision_directive(self):

        localctx = SysVerilogHDLParser.Timeprecision_directiveContext(self, self._ctx, self.state)
        self.enterRule(localctx, 880, self.RULE_timeprecision_directive)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3115
            self.match(SysVerilogHDLParser.Timeprecision)
            self.state = 3116
            self.match(SysVerilogHDLParser.Time_literal)
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Default_nettype_statementContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Default_nettype(self):
            return self.getToken(SysVerilogHDLParser.Default_nettype, 0)

        def net_type(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Net_typeContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_default_nettype_statement

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterDefault_nettype_statement" ):
                listener.enterDefault_nettype_statement(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitDefault_nettype_statement" ):
                listener.exitDefault_nettype_statement(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitDefault_nettype_statement" ):
                return visitor.visitDefault_nettype_statement(self)
            else:
                return visitor.visitChildren(self)




    def default_nettype_statement(self):

        localctx = SysVerilogHDLParser.Default_nettype_statementContext(self, self._ctx, self.state)
        self.enterRule(localctx, 882, self.RULE_default_nettype_statement)
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3118
            self.match(SysVerilogHDLParser.Default_nettype)
            self.state = 3119
            self.net_type()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class NumberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def integral_number(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Integral_numberContext,0)


        def real_number(self):
            return self.getTypedRuleContext(SysVerilogHDLParser.Real_numberContext,0)


        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterNumber" ):
                listener.enterNumber(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitNumber" ):
                listener.exitNumber(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitNumber" ):
                return visitor.visitNumber(self)
            else:
                return visitor.visitChildren(self)




    def number(self):

        localctx = SysVerilogHDLParser.NumberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 884, self.RULE_number)
        try:
            self.state = 3123
            self._errHandler.sync(self)
            token = self._input.LA(1)
            if token in [SysVerilogHDLParser.Binary_number, SysVerilogHDLParser.Decimal_number, SysVerilogHDLParser.Hex_number, SysVerilogHDLParser.Octal_number]:
                self.enterOuterAlt(localctx, 1)
                self.state = 3121
                self.integral_number()
                pass
            elif token in [SysVerilogHDLParser.Fixed_point_number, SysVerilogHDLParser.Real_exp_form]:
                self.enterOuterAlt(localctx, 2)
                self.state = 3122
                self.real_number()
                pass
            else:
                raise NoViableAltException(self)

        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Integral_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Decimal_number(self):
            return self.getToken(SysVerilogHDLParser.Decimal_number, 0)

        def Octal_number(self):
            return self.getToken(SysVerilogHDLParser.Octal_number, 0)

        def Binary_number(self):
            return self.getToken(SysVerilogHDLParser.Binary_number, 0)

        def Hex_number(self):
            return self.getToken(SysVerilogHDLParser.Hex_number, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_integral_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterIntegral_number" ):
                listener.enterIntegral_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitIntegral_number" ):
                listener.exitIntegral_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitIntegral_number" ):
                return visitor.visitIntegral_number(self)
            else:
                return visitor.visitChildren(self)




    def integral_number(self):

        localctx = SysVerilogHDLParser.Integral_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 886, self.RULE_integral_number)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3125
            _la = self._input.LA(1)
            if not((((_la) & ~0x3f) == 0 and ((1 << _la) & ((1 << SysVerilogHDLParser.Binary_number) | (1 << SysVerilogHDLParser.Decimal_number) | (1 << SysVerilogHDLParser.Hex_number) | (1 << SysVerilogHDLParser.Octal_number))) != 0)):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx


    class Real_numberContext(ParserRuleContext):

        def __init__(self, parser, parent:ParserRuleContext=None, invokingState:int=-1):
            super().__init__(parent, invokingState)
            self.parser = parser

        def Fixed_point_number(self):
            return self.getToken(SysVerilogHDLParser.Fixed_point_number, 0)

        def Real_exp_form(self):
            return self.getToken(SysVerilogHDLParser.Real_exp_form, 0)

        def getRuleIndex(self):
            return SysVerilogHDLParser.RULE_real_number

        def enterRule(self, listener:ParseTreeListener):
            if hasattr( listener, "enterReal_number" ):
                listener.enterReal_number(self)

        def exitRule(self, listener:ParseTreeListener):
            if hasattr( listener, "exitReal_number" ):
                listener.exitReal_number(self)

        def accept(self, visitor:ParseTreeVisitor):
            if hasattr( visitor, "visitReal_number" ):
                return visitor.visitReal_number(self)
            else:
                return visitor.visitChildren(self)




    def real_number(self):

        localctx = SysVerilogHDLParser.Real_numberContext(self, self._ctx, self.state)
        self.enterRule(localctx, 888, self.RULE_real_number)
        self._la = 0 # Token type
        try:
            self.enterOuterAlt(localctx, 1)
            self.state = 3127
            _la = self._input.LA(1)
            if not(_la==SysVerilogHDLParser.Fixed_point_number or _la==SysVerilogHDLParser.Real_exp_form):
                self._errHandler.recoverInline(self)
            else:
                self._errHandler.reportMatch(self)
                self.consume()
        except RecognitionException as re:
            localctx.exception = re
            self._errHandler.reportError(self, re)
            self._errHandler.recover(self, re)
        finally:
            self.exitRule()
        return localctx





