# Generated from Verilog2001.g4 by ANTLR 4.8
from antlr4 import *
if __name__ is not None and "." in __name__:
    from .Verilog2001Parser import Verilog2001Parser
else:
    from Verilog2001Parser import Verilog2001Parser

# This class defines a complete listener for a parse tree produced by Verilog2001Parser.
class Verilog2001Listener(ParseTreeListener):

    # Enter a parse tree produced by Verilog2001Parser#config_declaration.
    def enterConfig_declaration(self, ctx:Verilog2001Parser.Config_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#config_declaration.
    def exitConfig_declaration(self, ctx:Verilog2001Parser.Config_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#design_statement.
    def enterDesign_statement(self, ctx:Verilog2001Parser.Design_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#design_statement.
    def exitDesign_statement(self, ctx:Verilog2001Parser.Design_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#config_rule_statement.
    def enterConfig_rule_statement(self, ctx:Verilog2001Parser.Config_rule_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#config_rule_statement.
    def exitConfig_rule_statement(self, ctx:Verilog2001Parser.Config_rule_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#default_clause.
    def enterDefault_clause(self, ctx:Verilog2001Parser.Default_clauseContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#default_clause.
    def exitDefault_clause(self, ctx:Verilog2001Parser.Default_clauseContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#inst_clause.
    def enterInst_clause(self, ctx:Verilog2001Parser.Inst_clauseContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#inst_clause.
    def exitInst_clause(self, ctx:Verilog2001Parser.Inst_clauseContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#inst_name.
    def enterInst_name(self, ctx:Verilog2001Parser.Inst_nameContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#inst_name.
    def exitInst_name(self, ctx:Verilog2001Parser.Inst_nameContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#liblist_clause.
    def enterLiblist_clause(self, ctx:Verilog2001Parser.Liblist_clauseContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#liblist_clause.
    def exitLiblist_clause(self, ctx:Verilog2001Parser.Liblist_clauseContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#cell_clause.
    def enterCell_clause(self, ctx:Verilog2001Parser.Cell_clauseContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#cell_clause.
    def exitCell_clause(self, ctx:Verilog2001Parser.Cell_clauseContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#use_clause.
    def enterUse_clause(self, ctx:Verilog2001Parser.Use_clauseContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#use_clause.
    def exitUse_clause(self, ctx:Verilog2001Parser.Use_clauseContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#source_text.
    def enterSource_text(self, ctx:Verilog2001Parser.Source_textContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#source_text.
    def exitSource_text(self, ctx:Verilog2001Parser.Source_textContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#description.
    def enterDescription(self, ctx:Verilog2001Parser.DescriptionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#description.
    def exitDescription(self, ctx:Verilog2001Parser.DescriptionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_declaration.
    def enterModule_declaration(self, ctx:Verilog2001Parser.Module_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_declaration.
    def exitModule_declaration(self, ctx:Verilog2001Parser.Module_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_keyword.
    def enterModule_keyword(self, ctx:Verilog2001Parser.Module_keywordContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_keyword.
    def exitModule_keyword(self, ctx:Verilog2001Parser.Module_keywordContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_parameter_port_list.
    def enterModule_parameter_port_list(self, ctx:Verilog2001Parser.Module_parameter_port_listContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_parameter_port_list.
    def exitModule_parameter_port_list(self, ctx:Verilog2001Parser.Module_parameter_port_listContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_ports.
    def enterList_of_ports(self, ctx:Verilog2001Parser.List_of_portsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_ports.
    def exitList_of_ports(self, ctx:Verilog2001Parser.List_of_portsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_port_declarations.
    def enterList_of_port_declarations(self, ctx:Verilog2001Parser.List_of_port_declarationsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_port_declarations.
    def exitList_of_port_declarations(self, ctx:Verilog2001Parser.List_of_port_declarationsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#port.
    def enterPort(self, ctx:Verilog2001Parser.PortContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#port.
    def exitPort(self, ctx:Verilog2001Parser.PortContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#port_expression.
    def enterPort_expression(self, ctx:Verilog2001Parser.Port_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#port_expression.
    def exitPort_expression(self, ctx:Verilog2001Parser.Port_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#port_reference.
    def enterPort_reference(self, ctx:Verilog2001Parser.Port_referenceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#port_reference.
    def exitPort_reference(self, ctx:Verilog2001Parser.Port_referenceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#port_declaration.
    def enterPort_declaration(self, ctx:Verilog2001Parser.Port_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#port_declaration.
    def exitPort_declaration(self, ctx:Verilog2001Parser.Port_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_item.
    def enterModule_item(self, ctx:Verilog2001Parser.Module_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_item.
    def exitModule_item(self, ctx:Verilog2001Parser.Module_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_or_generate_item.
    def enterModule_or_generate_item(self, ctx:Verilog2001Parser.Module_or_generate_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_or_generate_item.
    def exitModule_or_generate_item(self, ctx:Verilog2001Parser.Module_or_generate_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#non_port_module_item.
    def enterNon_port_module_item(self, ctx:Verilog2001Parser.Non_port_module_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#non_port_module_item.
    def exitNon_port_module_item(self, ctx:Verilog2001Parser.Non_port_module_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_or_generate_item_declaration.
    def enterModule_or_generate_item_declaration(self, ctx:Verilog2001Parser.Module_or_generate_item_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_or_generate_item_declaration.
    def exitModule_or_generate_item_declaration(self, ctx:Verilog2001Parser.Module_or_generate_item_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#parameter_override.
    def enterParameter_override(self, ctx:Verilog2001Parser.Parameter_overrideContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#parameter_override.
    def exitParameter_override(self, ctx:Verilog2001Parser.Parameter_overrideContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#local_parameter_declaration.
    def enterLocal_parameter_declaration(self, ctx:Verilog2001Parser.Local_parameter_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#local_parameter_declaration.
    def exitLocal_parameter_declaration(self, ctx:Verilog2001Parser.Local_parameter_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#parameter_declaration.
    def enterParameter_declaration(self, ctx:Verilog2001Parser.Parameter_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#parameter_declaration.
    def exitParameter_declaration(self, ctx:Verilog2001Parser.Parameter_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#parameter_declaration_.
    def enterParameter_declaration_(self, ctx:Verilog2001Parser.Parameter_declaration_Context):
        pass

    # Exit a parse tree produced by Verilog2001Parser#parameter_declaration_.
    def exitParameter_declaration_(self, ctx:Verilog2001Parser.Parameter_declaration_Context):
        pass


    # Enter a parse tree produced by Verilog2001Parser#specparam_declaration.
    def enterSpecparam_declaration(self, ctx:Verilog2001Parser.Specparam_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#specparam_declaration.
    def exitSpecparam_declaration(self, ctx:Verilog2001Parser.Specparam_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#inout_declaration.
    def enterInout_declaration(self, ctx:Verilog2001Parser.Inout_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#inout_declaration.
    def exitInout_declaration(self, ctx:Verilog2001Parser.Inout_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#input_declaration.
    def enterInput_declaration(self, ctx:Verilog2001Parser.Input_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#input_declaration.
    def exitInput_declaration(self, ctx:Verilog2001Parser.Input_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#output_declaration.
    def enterOutput_declaration(self, ctx:Verilog2001Parser.Output_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#output_declaration.
    def exitOutput_declaration(self, ctx:Verilog2001Parser.Output_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#event_declaration.
    def enterEvent_declaration(self, ctx:Verilog2001Parser.Event_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#event_declaration.
    def exitEvent_declaration(self, ctx:Verilog2001Parser.Event_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#genvar_declaration.
    def enterGenvar_declaration(self, ctx:Verilog2001Parser.Genvar_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#genvar_declaration.
    def exitGenvar_declaration(self, ctx:Verilog2001Parser.Genvar_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#integer_declaration.
    def enterInteger_declaration(self, ctx:Verilog2001Parser.Integer_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#integer_declaration.
    def exitInteger_declaration(self, ctx:Verilog2001Parser.Integer_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#time_declaration.
    def enterTime_declaration(self, ctx:Verilog2001Parser.Time_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#time_declaration.
    def exitTime_declaration(self, ctx:Verilog2001Parser.Time_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#real_declaration.
    def enterReal_declaration(self, ctx:Verilog2001Parser.Real_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#real_declaration.
    def exitReal_declaration(self, ctx:Verilog2001Parser.Real_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#realtime_declaration.
    def enterRealtime_declaration(self, ctx:Verilog2001Parser.Realtime_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#realtime_declaration.
    def exitRealtime_declaration(self, ctx:Verilog2001Parser.Realtime_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#reg_declaration.
    def enterReg_declaration(self, ctx:Verilog2001Parser.Reg_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#reg_declaration.
    def exitReg_declaration(self, ctx:Verilog2001Parser.Reg_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#net_declaration.
    def enterNet_declaration(self, ctx:Verilog2001Parser.Net_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#net_declaration.
    def exitNet_declaration(self, ctx:Verilog2001Parser.Net_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#net_type.
    def enterNet_type(self, ctx:Verilog2001Parser.Net_typeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#net_type.
    def exitNet_type(self, ctx:Verilog2001Parser.Net_typeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#output_variable_type.
    def enterOutput_variable_type(self, ctx:Verilog2001Parser.Output_variable_typeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#output_variable_type.
    def exitOutput_variable_type(self, ctx:Verilog2001Parser.Output_variable_typeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#real_type.
    def enterReal_type(self, ctx:Verilog2001Parser.Real_typeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#real_type.
    def exitReal_type(self, ctx:Verilog2001Parser.Real_typeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#variable_type.
    def enterVariable_type(self, ctx:Verilog2001Parser.Variable_typeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#variable_type.
    def exitVariable_type(self, ctx:Verilog2001Parser.Variable_typeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#drive_strength.
    def enterDrive_strength(self, ctx:Verilog2001Parser.Drive_strengthContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#drive_strength.
    def exitDrive_strength(self, ctx:Verilog2001Parser.Drive_strengthContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#strength0.
    def enterStrength0(self, ctx:Verilog2001Parser.Strength0Context):
        pass

    # Exit a parse tree produced by Verilog2001Parser#strength0.
    def exitStrength0(self, ctx:Verilog2001Parser.Strength0Context):
        pass


    # Enter a parse tree produced by Verilog2001Parser#strength1.
    def enterStrength1(self, ctx:Verilog2001Parser.Strength1Context):
        pass

    # Exit a parse tree produced by Verilog2001Parser#strength1.
    def exitStrength1(self, ctx:Verilog2001Parser.Strength1Context):
        pass


    # Enter a parse tree produced by Verilog2001Parser#charge_strength.
    def enterCharge_strength(self, ctx:Verilog2001Parser.Charge_strengthContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#charge_strength.
    def exitCharge_strength(self, ctx:Verilog2001Parser.Charge_strengthContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#delay3.
    def enterDelay3(self, ctx:Verilog2001Parser.Delay3Context):
        pass

    # Exit a parse tree produced by Verilog2001Parser#delay3.
    def exitDelay3(self, ctx:Verilog2001Parser.Delay3Context):
        pass


    # Enter a parse tree produced by Verilog2001Parser#delay2.
    def enterDelay2(self, ctx:Verilog2001Parser.Delay2Context):
        pass

    # Exit a parse tree produced by Verilog2001Parser#delay2.
    def exitDelay2(self, ctx:Verilog2001Parser.Delay2Context):
        pass


    # Enter a parse tree produced by Verilog2001Parser#delay_value.
    def enterDelay_value(self, ctx:Verilog2001Parser.Delay_valueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#delay_value.
    def exitDelay_value(self, ctx:Verilog2001Parser.Delay_valueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_event_identifiers.
    def enterList_of_event_identifiers(self, ctx:Verilog2001Parser.List_of_event_identifiersContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_event_identifiers.
    def exitList_of_event_identifiers(self, ctx:Verilog2001Parser.List_of_event_identifiersContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_net_identifiers.
    def enterList_of_net_identifiers(self, ctx:Verilog2001Parser.List_of_net_identifiersContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_net_identifiers.
    def exitList_of_net_identifiers(self, ctx:Verilog2001Parser.List_of_net_identifiersContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_genvar_identifiers.
    def enterList_of_genvar_identifiers(self, ctx:Verilog2001Parser.List_of_genvar_identifiersContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_genvar_identifiers.
    def exitList_of_genvar_identifiers(self, ctx:Verilog2001Parser.List_of_genvar_identifiersContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_port_identifiers.
    def enterList_of_port_identifiers(self, ctx:Verilog2001Parser.List_of_port_identifiersContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_port_identifiers.
    def exitList_of_port_identifiers(self, ctx:Verilog2001Parser.List_of_port_identifiersContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_net_decl_assignments.
    def enterList_of_net_decl_assignments(self, ctx:Verilog2001Parser.List_of_net_decl_assignmentsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_net_decl_assignments.
    def exitList_of_net_decl_assignments(self, ctx:Verilog2001Parser.List_of_net_decl_assignmentsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_param_assignments.
    def enterList_of_param_assignments(self, ctx:Verilog2001Parser.List_of_param_assignmentsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_param_assignments.
    def exitList_of_param_assignments(self, ctx:Verilog2001Parser.List_of_param_assignmentsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_specparam_assignments.
    def enterList_of_specparam_assignments(self, ctx:Verilog2001Parser.List_of_specparam_assignmentsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_specparam_assignments.
    def exitList_of_specparam_assignments(self, ctx:Verilog2001Parser.List_of_specparam_assignmentsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_real_identifiers.
    def enterList_of_real_identifiers(self, ctx:Verilog2001Parser.List_of_real_identifiersContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_real_identifiers.
    def exitList_of_real_identifiers(self, ctx:Verilog2001Parser.List_of_real_identifiersContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_variable_identifiers.
    def enterList_of_variable_identifiers(self, ctx:Verilog2001Parser.List_of_variable_identifiersContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_variable_identifiers.
    def exitList_of_variable_identifiers(self, ctx:Verilog2001Parser.List_of_variable_identifiersContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_variable_port_identifiers.
    def enterList_of_variable_port_identifiers(self, ctx:Verilog2001Parser.List_of_variable_port_identifiersContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_variable_port_identifiers.
    def exitList_of_variable_port_identifiers(self, ctx:Verilog2001Parser.List_of_variable_port_identifiersContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#net_decl_assignment.
    def enterNet_decl_assignment(self, ctx:Verilog2001Parser.Net_decl_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#net_decl_assignment.
    def exitNet_decl_assignment(self, ctx:Verilog2001Parser.Net_decl_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#param_assignment.
    def enterParam_assignment(self, ctx:Verilog2001Parser.Param_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#param_assignment.
    def exitParam_assignment(self, ctx:Verilog2001Parser.Param_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#specparam_assignment.
    def enterSpecparam_assignment(self, ctx:Verilog2001Parser.Specparam_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#specparam_assignment.
    def exitSpecparam_assignment(self, ctx:Verilog2001Parser.Specparam_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pulse_control_specparam.
    def enterPulse_control_specparam(self, ctx:Verilog2001Parser.Pulse_control_specparamContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pulse_control_specparam.
    def exitPulse_control_specparam(self, ctx:Verilog2001Parser.Pulse_control_specparamContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#error_limit_value.
    def enterError_limit_value(self, ctx:Verilog2001Parser.Error_limit_valueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#error_limit_value.
    def exitError_limit_value(self, ctx:Verilog2001Parser.Error_limit_valueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#reject_limit_value.
    def enterReject_limit_value(self, ctx:Verilog2001Parser.Reject_limit_valueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#reject_limit_value.
    def exitReject_limit_value(self, ctx:Verilog2001Parser.Reject_limit_valueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#limit_value.
    def enterLimit_value(self, ctx:Verilog2001Parser.Limit_valueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#limit_value.
    def exitLimit_value(self, ctx:Verilog2001Parser.Limit_valueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#dimension.
    def enterDimension(self, ctx:Verilog2001Parser.DimensionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#dimension.
    def exitDimension(self, ctx:Verilog2001Parser.DimensionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#range_.
    def enterRange_(self, ctx:Verilog2001Parser.Range_Context):
        pass

    # Exit a parse tree produced by Verilog2001Parser#range_.
    def exitRange_(self, ctx:Verilog2001Parser.Range_Context):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_declaration.
    def enterFunction_declaration(self, ctx:Verilog2001Parser.Function_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_declaration.
    def exitFunction_declaration(self, ctx:Verilog2001Parser.Function_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_item_declaration.
    def enterFunction_item_declaration(self, ctx:Verilog2001Parser.Function_item_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_item_declaration.
    def exitFunction_item_declaration(self, ctx:Verilog2001Parser.Function_item_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_port_list.
    def enterFunction_port_list(self, ctx:Verilog2001Parser.Function_port_listContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_port_list.
    def exitFunction_port_list(self, ctx:Verilog2001Parser.Function_port_listContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_port.
    def enterFunction_port(self, ctx:Verilog2001Parser.Function_portContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_port.
    def exitFunction_port(self, ctx:Verilog2001Parser.Function_portContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#range_or_type.
    def enterRange_or_type(self, ctx:Verilog2001Parser.Range_or_typeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#range_or_type.
    def exitRange_or_type(self, ctx:Verilog2001Parser.Range_or_typeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#task_declaration.
    def enterTask_declaration(self, ctx:Verilog2001Parser.Task_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#task_declaration.
    def exitTask_declaration(self, ctx:Verilog2001Parser.Task_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#task_item_declaration.
    def enterTask_item_declaration(self, ctx:Verilog2001Parser.Task_item_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#task_item_declaration.
    def exitTask_item_declaration(self, ctx:Verilog2001Parser.Task_item_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#task_port_list.
    def enterTask_port_list(self, ctx:Verilog2001Parser.Task_port_listContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#task_port_list.
    def exitTask_port_list(self, ctx:Verilog2001Parser.Task_port_listContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#task_port_item.
    def enterTask_port_item(self, ctx:Verilog2001Parser.Task_port_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#task_port_item.
    def exitTask_port_item(self, ctx:Verilog2001Parser.Task_port_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tf_decl_header.
    def enterTf_decl_header(self, ctx:Verilog2001Parser.Tf_decl_headerContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tf_decl_header.
    def exitTf_decl_header(self, ctx:Verilog2001Parser.Tf_decl_headerContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tf_declaration.
    def enterTf_declaration(self, ctx:Verilog2001Parser.Tf_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tf_declaration.
    def exitTf_declaration(self, ctx:Verilog2001Parser.Tf_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#task_port_type.
    def enterTask_port_type(self, ctx:Verilog2001Parser.Task_port_typeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#task_port_type.
    def exitTask_port_type(self, ctx:Verilog2001Parser.Task_port_typeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#block_item_declaration.
    def enterBlock_item_declaration(self, ctx:Verilog2001Parser.Block_item_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#block_item_declaration.
    def exitBlock_item_declaration(self, ctx:Verilog2001Parser.Block_item_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#block_reg_declaration.
    def enterBlock_reg_declaration(self, ctx:Verilog2001Parser.Block_reg_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#block_reg_declaration.
    def exitBlock_reg_declaration(self, ctx:Verilog2001Parser.Block_reg_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_block_variable_identifiers.
    def enterList_of_block_variable_identifiers(self, ctx:Verilog2001Parser.List_of_block_variable_identifiersContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_block_variable_identifiers.
    def exitList_of_block_variable_identifiers(self, ctx:Verilog2001Parser.List_of_block_variable_identifiersContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#block_variable_type.
    def enterBlock_variable_type(self, ctx:Verilog2001Parser.Block_variable_typeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#block_variable_type.
    def exitBlock_variable_type(self, ctx:Verilog2001Parser.Block_variable_typeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#gate_instantiation.
    def enterGate_instantiation(self, ctx:Verilog2001Parser.Gate_instantiationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#gate_instantiation.
    def exitGate_instantiation(self, ctx:Verilog2001Parser.Gate_instantiationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#cmos_switch_instance.
    def enterCmos_switch_instance(self, ctx:Verilog2001Parser.Cmos_switch_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#cmos_switch_instance.
    def exitCmos_switch_instance(self, ctx:Verilog2001Parser.Cmos_switch_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#enable_gate_instance.
    def enterEnable_gate_instance(self, ctx:Verilog2001Parser.Enable_gate_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#enable_gate_instance.
    def exitEnable_gate_instance(self, ctx:Verilog2001Parser.Enable_gate_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#mos_switch_instance.
    def enterMos_switch_instance(self, ctx:Verilog2001Parser.Mos_switch_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#mos_switch_instance.
    def exitMos_switch_instance(self, ctx:Verilog2001Parser.Mos_switch_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#n_input_gate_instance.
    def enterN_input_gate_instance(self, ctx:Verilog2001Parser.N_input_gate_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#n_input_gate_instance.
    def exitN_input_gate_instance(self, ctx:Verilog2001Parser.N_input_gate_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#n_output_gate_instance.
    def enterN_output_gate_instance(self, ctx:Verilog2001Parser.N_output_gate_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#n_output_gate_instance.
    def exitN_output_gate_instance(self, ctx:Verilog2001Parser.N_output_gate_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pass_switch_instance.
    def enterPass_switch_instance(self, ctx:Verilog2001Parser.Pass_switch_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pass_switch_instance.
    def exitPass_switch_instance(self, ctx:Verilog2001Parser.Pass_switch_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pass_enable_switch_instance.
    def enterPass_enable_switch_instance(self, ctx:Verilog2001Parser.Pass_enable_switch_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pass_enable_switch_instance.
    def exitPass_enable_switch_instance(self, ctx:Verilog2001Parser.Pass_enable_switch_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pull_gate_instance.
    def enterPull_gate_instance(self, ctx:Verilog2001Parser.Pull_gate_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pull_gate_instance.
    def exitPull_gate_instance(self, ctx:Verilog2001Parser.Pull_gate_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#name_of_gate_instance.
    def enterName_of_gate_instance(self, ctx:Verilog2001Parser.Name_of_gate_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#name_of_gate_instance.
    def exitName_of_gate_instance(self, ctx:Verilog2001Parser.Name_of_gate_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pulldown_strength.
    def enterPulldown_strength(self, ctx:Verilog2001Parser.Pulldown_strengthContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pulldown_strength.
    def exitPulldown_strength(self, ctx:Verilog2001Parser.Pulldown_strengthContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pullup_strength.
    def enterPullup_strength(self, ctx:Verilog2001Parser.Pullup_strengthContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pullup_strength.
    def exitPullup_strength(self, ctx:Verilog2001Parser.Pullup_strengthContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#enable_terminal.
    def enterEnable_terminal(self, ctx:Verilog2001Parser.Enable_terminalContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#enable_terminal.
    def exitEnable_terminal(self, ctx:Verilog2001Parser.Enable_terminalContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#ncontrol_terminal.
    def enterNcontrol_terminal(self, ctx:Verilog2001Parser.Ncontrol_terminalContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#ncontrol_terminal.
    def exitNcontrol_terminal(self, ctx:Verilog2001Parser.Ncontrol_terminalContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pcontrol_terminal.
    def enterPcontrol_terminal(self, ctx:Verilog2001Parser.Pcontrol_terminalContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pcontrol_terminal.
    def exitPcontrol_terminal(self, ctx:Verilog2001Parser.Pcontrol_terminalContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#input_terminal.
    def enterInput_terminal(self, ctx:Verilog2001Parser.Input_terminalContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#input_terminal.
    def exitInput_terminal(self, ctx:Verilog2001Parser.Input_terminalContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#inout_terminal.
    def enterInout_terminal(self, ctx:Verilog2001Parser.Inout_terminalContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#inout_terminal.
    def exitInout_terminal(self, ctx:Verilog2001Parser.Inout_terminalContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#output_terminal.
    def enterOutput_terminal(self, ctx:Verilog2001Parser.Output_terminalContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#output_terminal.
    def exitOutput_terminal(self, ctx:Verilog2001Parser.Output_terminalContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#cmos_switchtype.
    def enterCmos_switchtype(self, ctx:Verilog2001Parser.Cmos_switchtypeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#cmos_switchtype.
    def exitCmos_switchtype(self, ctx:Verilog2001Parser.Cmos_switchtypeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#enable_gatetype.
    def enterEnable_gatetype(self, ctx:Verilog2001Parser.Enable_gatetypeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#enable_gatetype.
    def exitEnable_gatetype(self, ctx:Verilog2001Parser.Enable_gatetypeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#mos_switchtype.
    def enterMos_switchtype(self, ctx:Verilog2001Parser.Mos_switchtypeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#mos_switchtype.
    def exitMos_switchtype(self, ctx:Verilog2001Parser.Mos_switchtypeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#n_input_gatetype.
    def enterN_input_gatetype(self, ctx:Verilog2001Parser.N_input_gatetypeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#n_input_gatetype.
    def exitN_input_gatetype(self, ctx:Verilog2001Parser.N_input_gatetypeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#n_output_gatetype.
    def enterN_output_gatetype(self, ctx:Verilog2001Parser.N_output_gatetypeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#n_output_gatetype.
    def exitN_output_gatetype(self, ctx:Verilog2001Parser.N_output_gatetypeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pass_en_switchtype.
    def enterPass_en_switchtype(self, ctx:Verilog2001Parser.Pass_en_switchtypeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pass_en_switchtype.
    def exitPass_en_switchtype(self, ctx:Verilog2001Parser.Pass_en_switchtypeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pass_switchtype.
    def enterPass_switchtype(self, ctx:Verilog2001Parser.Pass_switchtypeContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pass_switchtype.
    def exitPass_switchtype(self, ctx:Verilog2001Parser.Pass_switchtypeContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_instantiation.
    def enterModule_instantiation(self, ctx:Verilog2001Parser.Module_instantiationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_instantiation.
    def exitModule_instantiation(self, ctx:Verilog2001Parser.Module_instantiationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#parameter_value_assignment.
    def enterParameter_value_assignment(self, ctx:Verilog2001Parser.Parameter_value_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#parameter_value_assignment.
    def exitParameter_value_assignment(self, ctx:Verilog2001Parser.Parameter_value_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_parameter_assignments.
    def enterList_of_parameter_assignments(self, ctx:Verilog2001Parser.List_of_parameter_assignmentsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_parameter_assignments.
    def exitList_of_parameter_assignments(self, ctx:Verilog2001Parser.List_of_parameter_assignmentsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#ordered_parameter_assignment.
    def enterOrdered_parameter_assignment(self, ctx:Verilog2001Parser.Ordered_parameter_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#ordered_parameter_assignment.
    def exitOrdered_parameter_assignment(self, ctx:Verilog2001Parser.Ordered_parameter_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#named_parameter_assignment.
    def enterNamed_parameter_assignment(self, ctx:Verilog2001Parser.Named_parameter_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#named_parameter_assignment.
    def exitNamed_parameter_assignment(self, ctx:Verilog2001Parser.Named_parameter_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_instance.
    def enterModule_instance(self, ctx:Verilog2001Parser.Module_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_instance.
    def exitModule_instance(self, ctx:Verilog2001Parser.Module_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#name_of_instance.
    def enterName_of_instance(self, ctx:Verilog2001Parser.Name_of_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#name_of_instance.
    def exitName_of_instance(self, ctx:Verilog2001Parser.Name_of_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_port_connections.
    def enterList_of_port_connections(self, ctx:Verilog2001Parser.List_of_port_connectionsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_port_connections.
    def exitList_of_port_connections(self, ctx:Verilog2001Parser.List_of_port_connectionsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#ordered_port_connection.
    def enterOrdered_port_connection(self, ctx:Verilog2001Parser.Ordered_port_connectionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#ordered_port_connection.
    def exitOrdered_port_connection(self, ctx:Verilog2001Parser.Ordered_port_connectionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#named_port_connection.
    def enterNamed_port_connection(self, ctx:Verilog2001Parser.Named_port_connectionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#named_port_connection.
    def exitNamed_port_connection(self, ctx:Verilog2001Parser.Named_port_connectionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#generated_instantiation.
    def enterGenerated_instantiation(self, ctx:Verilog2001Parser.Generated_instantiationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#generated_instantiation.
    def exitGenerated_instantiation(self, ctx:Verilog2001Parser.Generated_instantiationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#generate_item_or_null.
    def enterGenerate_item_or_null(self, ctx:Verilog2001Parser.Generate_item_or_nullContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#generate_item_or_null.
    def exitGenerate_item_or_null(self, ctx:Verilog2001Parser.Generate_item_or_nullContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#generate_item.
    def enterGenerate_item(self, ctx:Verilog2001Parser.Generate_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#generate_item.
    def exitGenerate_item(self, ctx:Verilog2001Parser.Generate_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#generate_conditional_statement.
    def enterGenerate_conditional_statement(self, ctx:Verilog2001Parser.Generate_conditional_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#generate_conditional_statement.
    def exitGenerate_conditional_statement(self, ctx:Verilog2001Parser.Generate_conditional_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#generate_case_statement.
    def enterGenerate_case_statement(self, ctx:Verilog2001Parser.Generate_case_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#generate_case_statement.
    def exitGenerate_case_statement(self, ctx:Verilog2001Parser.Generate_case_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#genvar_case_item.
    def enterGenvar_case_item(self, ctx:Verilog2001Parser.Genvar_case_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#genvar_case_item.
    def exitGenvar_case_item(self, ctx:Verilog2001Parser.Genvar_case_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#generate_loop_statement.
    def enterGenerate_loop_statement(self, ctx:Verilog2001Parser.Generate_loop_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#generate_loop_statement.
    def exitGenerate_loop_statement(self, ctx:Verilog2001Parser.Generate_loop_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#genvar_assignment.
    def enterGenvar_assignment(self, ctx:Verilog2001Parser.Genvar_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#genvar_assignment.
    def exitGenvar_assignment(self, ctx:Verilog2001Parser.Genvar_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#generate_block.
    def enterGenerate_block(self, ctx:Verilog2001Parser.Generate_blockContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#generate_block.
    def exitGenerate_block(self, ctx:Verilog2001Parser.Generate_blockContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#continuous_assign.
    def enterContinuous_assign(self, ctx:Verilog2001Parser.Continuous_assignContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#continuous_assign.
    def exitContinuous_assign(self, ctx:Verilog2001Parser.Continuous_assignContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_net_assignments.
    def enterList_of_net_assignments(self, ctx:Verilog2001Parser.List_of_net_assignmentsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_net_assignments.
    def exitList_of_net_assignments(self, ctx:Verilog2001Parser.List_of_net_assignmentsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#net_assignment.
    def enterNet_assignment(self, ctx:Verilog2001Parser.Net_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#net_assignment.
    def exitNet_assignment(self, ctx:Verilog2001Parser.Net_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#initial_construct.
    def enterInitial_construct(self, ctx:Verilog2001Parser.Initial_constructContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#initial_construct.
    def exitInitial_construct(self, ctx:Verilog2001Parser.Initial_constructContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#always_construct.
    def enterAlways_construct(self, ctx:Verilog2001Parser.Always_constructContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#always_construct.
    def exitAlways_construct(self, ctx:Verilog2001Parser.Always_constructContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#blocking_assignment.
    def enterBlocking_assignment(self, ctx:Verilog2001Parser.Blocking_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#blocking_assignment.
    def exitBlocking_assignment(self, ctx:Verilog2001Parser.Blocking_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#nonblocking_assignment.
    def enterNonblocking_assignment(self, ctx:Verilog2001Parser.Nonblocking_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#nonblocking_assignment.
    def exitNonblocking_assignment(self, ctx:Verilog2001Parser.Nonblocking_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#procedural_continuous_assignments.
    def enterProcedural_continuous_assignments(self, ctx:Verilog2001Parser.Procedural_continuous_assignmentsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#procedural_continuous_assignments.
    def exitProcedural_continuous_assignments(self, ctx:Verilog2001Parser.Procedural_continuous_assignmentsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_blocking_assignment.
    def enterFunction_blocking_assignment(self, ctx:Verilog2001Parser.Function_blocking_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_blocking_assignment.
    def exitFunction_blocking_assignment(self, ctx:Verilog2001Parser.Function_blocking_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_statement_or_null.
    def enterFunction_statement_or_null(self, ctx:Verilog2001Parser.Function_statement_or_nullContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_statement_or_null.
    def exitFunction_statement_or_null(self, ctx:Verilog2001Parser.Function_statement_or_nullContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_seq_block.
    def enterFunction_seq_block(self, ctx:Verilog2001Parser.Function_seq_blockContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_seq_block.
    def exitFunction_seq_block(self, ctx:Verilog2001Parser.Function_seq_blockContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#variable_assignment.
    def enterVariable_assignment(self, ctx:Verilog2001Parser.Variable_assignmentContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#variable_assignment.
    def exitVariable_assignment(self, ctx:Verilog2001Parser.Variable_assignmentContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#par_block.
    def enterPar_block(self, ctx:Verilog2001Parser.Par_blockContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#par_block.
    def exitPar_block(self, ctx:Verilog2001Parser.Par_blockContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#seq_block.
    def enterSeq_block(self, ctx:Verilog2001Parser.Seq_blockContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#seq_block.
    def exitSeq_block(self, ctx:Verilog2001Parser.Seq_blockContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#statement.
    def enterStatement(self, ctx:Verilog2001Parser.StatementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#statement.
    def exitStatement(self, ctx:Verilog2001Parser.StatementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#statement_or_null.
    def enterStatement_or_null(self, ctx:Verilog2001Parser.Statement_or_nullContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#statement_or_null.
    def exitStatement_or_null(self, ctx:Verilog2001Parser.Statement_or_nullContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_statement.
    def enterFunction_statement(self, ctx:Verilog2001Parser.Function_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_statement.
    def exitFunction_statement(self, ctx:Verilog2001Parser.Function_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#delay_or_event_control.
    def enterDelay_or_event_control(self, ctx:Verilog2001Parser.Delay_or_event_controlContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#delay_or_event_control.
    def exitDelay_or_event_control(self, ctx:Verilog2001Parser.Delay_or_event_controlContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#delay_control.
    def enterDelay_control(self, ctx:Verilog2001Parser.Delay_controlContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#delay_control.
    def exitDelay_control(self, ctx:Verilog2001Parser.Delay_controlContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#disable_statement.
    def enterDisable_statement(self, ctx:Verilog2001Parser.Disable_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#disable_statement.
    def exitDisable_statement(self, ctx:Verilog2001Parser.Disable_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#event_control.
    def enterEvent_control(self, ctx:Verilog2001Parser.Event_controlContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#event_control.
    def exitEvent_control(self, ctx:Verilog2001Parser.Event_controlContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#event_trigger.
    def enterEvent_trigger(self, ctx:Verilog2001Parser.Event_triggerContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#event_trigger.
    def exitEvent_trigger(self, ctx:Verilog2001Parser.Event_triggerContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#event_expression.
    def enterEvent_expression(self, ctx:Verilog2001Parser.Event_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#event_expression.
    def exitEvent_expression(self, ctx:Verilog2001Parser.Event_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#event_primary.
    def enterEvent_primary(self, ctx:Verilog2001Parser.Event_primaryContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#event_primary.
    def exitEvent_primary(self, ctx:Verilog2001Parser.Event_primaryContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#procedural_timing_control_statement.
    def enterProcedural_timing_control_statement(self, ctx:Verilog2001Parser.Procedural_timing_control_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#procedural_timing_control_statement.
    def exitProcedural_timing_control_statement(self, ctx:Verilog2001Parser.Procedural_timing_control_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#wait_statement.
    def enterWait_statement(self, ctx:Verilog2001Parser.Wait_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#wait_statement.
    def exitWait_statement(self, ctx:Verilog2001Parser.Wait_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#conditional_statement.
    def enterConditional_statement(self, ctx:Verilog2001Parser.Conditional_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#conditional_statement.
    def exitConditional_statement(self, ctx:Verilog2001Parser.Conditional_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#if_else_if_statement.
    def enterIf_else_if_statement(self, ctx:Verilog2001Parser.If_else_if_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#if_else_if_statement.
    def exitIf_else_if_statement(self, ctx:Verilog2001Parser.If_else_if_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_conditional_statement.
    def enterFunction_conditional_statement(self, ctx:Verilog2001Parser.Function_conditional_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_conditional_statement.
    def exitFunction_conditional_statement(self, ctx:Verilog2001Parser.Function_conditional_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_if_else_if_statement.
    def enterFunction_if_else_if_statement(self, ctx:Verilog2001Parser.Function_if_else_if_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_if_else_if_statement.
    def exitFunction_if_else_if_statement(self, ctx:Verilog2001Parser.Function_if_else_if_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#case_statement.
    def enterCase_statement(self, ctx:Verilog2001Parser.Case_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#case_statement.
    def exitCase_statement(self, ctx:Verilog2001Parser.Case_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#case_item.
    def enterCase_item(self, ctx:Verilog2001Parser.Case_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#case_item.
    def exitCase_item(self, ctx:Verilog2001Parser.Case_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_case_statement.
    def enterFunction_case_statement(self, ctx:Verilog2001Parser.Function_case_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_case_statement.
    def exitFunction_case_statement(self, ctx:Verilog2001Parser.Function_case_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_case_item.
    def enterFunction_case_item(self, ctx:Verilog2001Parser.Function_case_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_case_item.
    def exitFunction_case_item(self, ctx:Verilog2001Parser.Function_case_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_loop_statement.
    def enterFunction_loop_statement(self, ctx:Verilog2001Parser.Function_loop_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_loop_statement.
    def exitFunction_loop_statement(self, ctx:Verilog2001Parser.Function_loop_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#loop_statement.
    def enterLoop_statement(self, ctx:Verilog2001Parser.Loop_statementContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#loop_statement.
    def exitLoop_statement(self, ctx:Verilog2001Parser.Loop_statementContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#system_task_enable.
    def enterSystem_task_enable(self, ctx:Verilog2001Parser.System_task_enableContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#system_task_enable.
    def exitSystem_task_enable(self, ctx:Verilog2001Parser.System_task_enableContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#task_enable.
    def enterTask_enable(self, ctx:Verilog2001Parser.Task_enableContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#task_enable.
    def exitTask_enable(self, ctx:Verilog2001Parser.Task_enableContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#specify_block.
    def enterSpecify_block(self, ctx:Verilog2001Parser.Specify_blockContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#specify_block.
    def exitSpecify_block(self, ctx:Verilog2001Parser.Specify_blockContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#specify_item.
    def enterSpecify_item(self, ctx:Verilog2001Parser.Specify_itemContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#specify_item.
    def exitSpecify_item(self, ctx:Verilog2001Parser.Specify_itemContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#pulsestyle_declaration.
    def enterPulsestyle_declaration(self, ctx:Verilog2001Parser.Pulsestyle_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#pulsestyle_declaration.
    def exitPulsestyle_declaration(self, ctx:Verilog2001Parser.Pulsestyle_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#showcancelled_declaration.
    def enterShowcancelled_declaration(self, ctx:Verilog2001Parser.Showcancelled_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#showcancelled_declaration.
    def exitShowcancelled_declaration(self, ctx:Verilog2001Parser.Showcancelled_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#path_declaration.
    def enterPath_declaration(self, ctx:Verilog2001Parser.Path_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#path_declaration.
    def exitPath_declaration(self, ctx:Verilog2001Parser.Path_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#simple_path_declaration.
    def enterSimple_path_declaration(self, ctx:Verilog2001Parser.Simple_path_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#simple_path_declaration.
    def exitSimple_path_declaration(self, ctx:Verilog2001Parser.Simple_path_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#parallel_path_description.
    def enterParallel_path_description(self, ctx:Verilog2001Parser.Parallel_path_descriptionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#parallel_path_description.
    def exitParallel_path_description(self, ctx:Verilog2001Parser.Parallel_path_descriptionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#full_path_description.
    def enterFull_path_description(self, ctx:Verilog2001Parser.Full_path_descriptionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#full_path_description.
    def exitFull_path_description(self, ctx:Verilog2001Parser.Full_path_descriptionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_path_inputs.
    def enterList_of_path_inputs(self, ctx:Verilog2001Parser.List_of_path_inputsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_path_inputs.
    def exitList_of_path_inputs(self, ctx:Verilog2001Parser.List_of_path_inputsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_path_outputs.
    def enterList_of_path_outputs(self, ctx:Verilog2001Parser.List_of_path_outputsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_path_outputs.
    def exitList_of_path_outputs(self, ctx:Verilog2001Parser.List_of_path_outputsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#specify_input_terminal_descriptor.
    def enterSpecify_input_terminal_descriptor(self, ctx:Verilog2001Parser.Specify_input_terminal_descriptorContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#specify_input_terminal_descriptor.
    def exitSpecify_input_terminal_descriptor(self, ctx:Verilog2001Parser.Specify_input_terminal_descriptorContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#specify_output_terminal_descriptor.
    def enterSpecify_output_terminal_descriptor(self, ctx:Verilog2001Parser.Specify_output_terminal_descriptorContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#specify_output_terminal_descriptor.
    def exitSpecify_output_terminal_descriptor(self, ctx:Verilog2001Parser.Specify_output_terminal_descriptorContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#input_identifier.
    def enterInput_identifier(self, ctx:Verilog2001Parser.Input_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#input_identifier.
    def exitInput_identifier(self, ctx:Verilog2001Parser.Input_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#output_identifier.
    def enterOutput_identifier(self, ctx:Verilog2001Parser.Output_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#output_identifier.
    def exitOutput_identifier(self, ctx:Verilog2001Parser.Output_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#path_delay_value.
    def enterPath_delay_value(self, ctx:Verilog2001Parser.Path_delay_valueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#path_delay_value.
    def exitPath_delay_value(self, ctx:Verilog2001Parser.Path_delay_valueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#list_of_path_delay_expressions.
    def enterList_of_path_delay_expressions(self, ctx:Verilog2001Parser.List_of_path_delay_expressionsContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#list_of_path_delay_expressions.
    def exitList_of_path_delay_expressions(self, ctx:Verilog2001Parser.List_of_path_delay_expressionsContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#t_path_delay_expression.
    def enterT_path_delay_expression(self, ctx:Verilog2001Parser.T_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#t_path_delay_expression.
    def exitT_path_delay_expression(self, ctx:Verilog2001Parser.T_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#trise_path_delay_expression.
    def enterTrise_path_delay_expression(self, ctx:Verilog2001Parser.Trise_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#trise_path_delay_expression.
    def exitTrise_path_delay_expression(self, ctx:Verilog2001Parser.Trise_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tfall_path_delay_expression.
    def enterTfall_path_delay_expression(self, ctx:Verilog2001Parser.Tfall_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tfall_path_delay_expression.
    def exitTfall_path_delay_expression(self, ctx:Verilog2001Parser.Tfall_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tz_path_delay_expression.
    def enterTz_path_delay_expression(self, ctx:Verilog2001Parser.Tz_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tz_path_delay_expression.
    def exitTz_path_delay_expression(self, ctx:Verilog2001Parser.Tz_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#t01_path_delay_expression.
    def enterT01_path_delay_expression(self, ctx:Verilog2001Parser.T01_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#t01_path_delay_expression.
    def exitT01_path_delay_expression(self, ctx:Verilog2001Parser.T01_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#t10_path_delay_expression.
    def enterT10_path_delay_expression(self, ctx:Verilog2001Parser.T10_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#t10_path_delay_expression.
    def exitT10_path_delay_expression(self, ctx:Verilog2001Parser.T10_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#t0z_path_delay_expression.
    def enterT0z_path_delay_expression(self, ctx:Verilog2001Parser.T0z_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#t0z_path_delay_expression.
    def exitT0z_path_delay_expression(self, ctx:Verilog2001Parser.T0z_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tz1_path_delay_expression.
    def enterTz1_path_delay_expression(self, ctx:Verilog2001Parser.Tz1_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tz1_path_delay_expression.
    def exitTz1_path_delay_expression(self, ctx:Verilog2001Parser.Tz1_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#t1z_path_delay_expression.
    def enterT1z_path_delay_expression(self, ctx:Verilog2001Parser.T1z_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#t1z_path_delay_expression.
    def exitT1z_path_delay_expression(self, ctx:Verilog2001Parser.T1z_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tz0_path_delay_expression.
    def enterTz0_path_delay_expression(self, ctx:Verilog2001Parser.Tz0_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tz0_path_delay_expression.
    def exitTz0_path_delay_expression(self, ctx:Verilog2001Parser.Tz0_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#t0x_path_delay_expression.
    def enterT0x_path_delay_expression(self, ctx:Verilog2001Parser.T0x_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#t0x_path_delay_expression.
    def exitT0x_path_delay_expression(self, ctx:Verilog2001Parser.T0x_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tx1_path_delay_expression.
    def enterTx1_path_delay_expression(self, ctx:Verilog2001Parser.Tx1_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tx1_path_delay_expression.
    def exitTx1_path_delay_expression(self, ctx:Verilog2001Parser.Tx1_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#t1x_path_delay_expression.
    def enterT1x_path_delay_expression(self, ctx:Verilog2001Parser.T1x_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#t1x_path_delay_expression.
    def exitT1x_path_delay_expression(self, ctx:Verilog2001Parser.T1x_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tx0_path_delay_expression.
    def enterTx0_path_delay_expression(self, ctx:Verilog2001Parser.Tx0_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tx0_path_delay_expression.
    def exitTx0_path_delay_expression(self, ctx:Verilog2001Parser.Tx0_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#txz_path_delay_expression.
    def enterTxz_path_delay_expression(self, ctx:Verilog2001Parser.Txz_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#txz_path_delay_expression.
    def exitTxz_path_delay_expression(self, ctx:Verilog2001Parser.Txz_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#tzx_path_delay_expression.
    def enterTzx_path_delay_expression(self, ctx:Verilog2001Parser.Tzx_path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#tzx_path_delay_expression.
    def exitTzx_path_delay_expression(self, ctx:Verilog2001Parser.Tzx_path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#path_delay_expression.
    def enterPath_delay_expression(self, ctx:Verilog2001Parser.Path_delay_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#path_delay_expression.
    def exitPath_delay_expression(self, ctx:Verilog2001Parser.Path_delay_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#edge_sensitive_path_declaration.
    def enterEdge_sensitive_path_declaration(self, ctx:Verilog2001Parser.Edge_sensitive_path_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#edge_sensitive_path_declaration.
    def exitEdge_sensitive_path_declaration(self, ctx:Verilog2001Parser.Edge_sensitive_path_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#parallel_edge_sensitive_path_description.
    def enterParallel_edge_sensitive_path_description(self, ctx:Verilog2001Parser.Parallel_edge_sensitive_path_descriptionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#parallel_edge_sensitive_path_description.
    def exitParallel_edge_sensitive_path_description(self, ctx:Verilog2001Parser.Parallel_edge_sensitive_path_descriptionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#full_edge_sensitive_path_description.
    def enterFull_edge_sensitive_path_description(self, ctx:Verilog2001Parser.Full_edge_sensitive_path_descriptionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#full_edge_sensitive_path_description.
    def exitFull_edge_sensitive_path_description(self, ctx:Verilog2001Parser.Full_edge_sensitive_path_descriptionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#data_source_expression.
    def enterData_source_expression(self, ctx:Verilog2001Parser.Data_source_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#data_source_expression.
    def exitData_source_expression(self, ctx:Verilog2001Parser.Data_source_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#edge_identifier.
    def enterEdge_identifier(self, ctx:Verilog2001Parser.Edge_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#edge_identifier.
    def exitEdge_identifier(self, ctx:Verilog2001Parser.Edge_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#state_dependent_path_declaration.
    def enterState_dependent_path_declaration(self, ctx:Verilog2001Parser.State_dependent_path_declarationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#state_dependent_path_declaration.
    def exitState_dependent_path_declaration(self, ctx:Verilog2001Parser.State_dependent_path_declarationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#polarity_operator.
    def enterPolarity_operator(self, ctx:Verilog2001Parser.Polarity_operatorContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#polarity_operator.
    def exitPolarity_operator(self, ctx:Verilog2001Parser.Polarity_operatorContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#checktime_condition.
    def enterChecktime_condition(self, ctx:Verilog2001Parser.Checktime_conditionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#checktime_condition.
    def exitChecktime_condition(self, ctx:Verilog2001Parser.Checktime_conditionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#delayed_data.
    def enterDelayed_data(self, ctx:Verilog2001Parser.Delayed_dataContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#delayed_data.
    def exitDelayed_data(self, ctx:Verilog2001Parser.Delayed_dataContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#delayed_reference.
    def enterDelayed_reference(self, ctx:Verilog2001Parser.Delayed_referenceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#delayed_reference.
    def exitDelayed_reference(self, ctx:Verilog2001Parser.Delayed_referenceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#end_edge_offset.
    def enterEnd_edge_offset(self, ctx:Verilog2001Parser.End_edge_offsetContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#end_edge_offset.
    def exitEnd_edge_offset(self, ctx:Verilog2001Parser.End_edge_offsetContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#event_based_flag.
    def enterEvent_based_flag(self, ctx:Verilog2001Parser.Event_based_flagContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#event_based_flag.
    def exitEvent_based_flag(self, ctx:Verilog2001Parser.Event_based_flagContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#notify_reg.
    def enterNotify_reg(self, ctx:Verilog2001Parser.Notify_regContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#notify_reg.
    def exitNotify_reg(self, ctx:Verilog2001Parser.Notify_regContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#remain_active_flag.
    def enterRemain_active_flag(self, ctx:Verilog2001Parser.Remain_active_flagContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#remain_active_flag.
    def exitRemain_active_flag(self, ctx:Verilog2001Parser.Remain_active_flagContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#stamptime_condition.
    def enterStamptime_condition(self, ctx:Verilog2001Parser.Stamptime_conditionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#stamptime_condition.
    def exitStamptime_condition(self, ctx:Verilog2001Parser.Stamptime_conditionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#start_edge_offset.
    def enterStart_edge_offset(self, ctx:Verilog2001Parser.Start_edge_offsetContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#start_edge_offset.
    def exitStart_edge_offset(self, ctx:Verilog2001Parser.Start_edge_offsetContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#threshold.
    def enterThreshold(self, ctx:Verilog2001Parser.ThresholdContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#threshold.
    def exitThreshold(self, ctx:Verilog2001Parser.ThresholdContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#timing_check_limit.
    def enterTiming_check_limit(self, ctx:Verilog2001Parser.Timing_check_limitContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#timing_check_limit.
    def exitTiming_check_limit(self, ctx:Verilog2001Parser.Timing_check_limitContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#concatenation.
    def enterConcatenation(self, ctx:Verilog2001Parser.ConcatenationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#concatenation.
    def exitConcatenation(self, ctx:Verilog2001Parser.ConcatenationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#constant_concatenation.
    def enterConstant_concatenation(self, ctx:Verilog2001Parser.Constant_concatenationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#constant_concatenation.
    def exitConstant_concatenation(self, ctx:Verilog2001Parser.Constant_concatenationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#constant_multiple_concatenation.
    def enterConstant_multiple_concatenation(self, ctx:Verilog2001Parser.Constant_multiple_concatenationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#constant_multiple_concatenation.
    def exitConstant_multiple_concatenation(self, ctx:Verilog2001Parser.Constant_multiple_concatenationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_path_concatenation.
    def enterModule_path_concatenation(self, ctx:Verilog2001Parser.Module_path_concatenationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_path_concatenation.
    def exitModule_path_concatenation(self, ctx:Verilog2001Parser.Module_path_concatenationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_path_multiple_concatenation.
    def enterModule_path_multiple_concatenation(self, ctx:Verilog2001Parser.Module_path_multiple_concatenationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_path_multiple_concatenation.
    def exitModule_path_multiple_concatenation(self, ctx:Verilog2001Parser.Module_path_multiple_concatenationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#multiple_concatenation.
    def enterMultiple_concatenation(self, ctx:Verilog2001Parser.Multiple_concatenationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#multiple_concatenation.
    def exitMultiple_concatenation(self, ctx:Verilog2001Parser.Multiple_concatenationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#net_concatenation.
    def enterNet_concatenation(self, ctx:Verilog2001Parser.Net_concatenationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#net_concatenation.
    def exitNet_concatenation(self, ctx:Verilog2001Parser.Net_concatenationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#net_concatenation_value.
    def enterNet_concatenation_value(self, ctx:Verilog2001Parser.Net_concatenation_valueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#net_concatenation_value.
    def exitNet_concatenation_value(self, ctx:Verilog2001Parser.Net_concatenation_valueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#variable_concatenation.
    def enterVariable_concatenation(self, ctx:Verilog2001Parser.Variable_concatenationContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#variable_concatenation.
    def exitVariable_concatenation(self, ctx:Verilog2001Parser.Variable_concatenationContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#variable_concatenation_value.
    def enterVariable_concatenation_value(self, ctx:Verilog2001Parser.Variable_concatenation_valueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#variable_concatenation_value.
    def exitVariable_concatenation_value(self, ctx:Verilog2001Parser.Variable_concatenation_valueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#constant_function_call.
    def enterConstant_function_call(self, ctx:Verilog2001Parser.Constant_function_callContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#constant_function_call.
    def exitConstant_function_call(self, ctx:Verilog2001Parser.Constant_function_callContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_call.
    def enterFunction_call(self, ctx:Verilog2001Parser.Function_callContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_call.
    def exitFunction_call(self, ctx:Verilog2001Parser.Function_callContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#system_function_call.
    def enterSystem_function_call(self, ctx:Verilog2001Parser.System_function_callContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#system_function_call.
    def exitSystem_function_call(self, ctx:Verilog2001Parser.System_function_callContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#genvar_function_call.
    def enterGenvar_function_call(self, ctx:Verilog2001Parser.Genvar_function_callContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#genvar_function_call.
    def exitGenvar_function_call(self, ctx:Verilog2001Parser.Genvar_function_callContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#base_expression.
    def enterBase_expression(self, ctx:Verilog2001Parser.Base_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#base_expression.
    def exitBase_expression(self, ctx:Verilog2001Parser.Base_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#constant_base_expression.
    def enterConstant_base_expression(self, ctx:Verilog2001Parser.Constant_base_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#constant_base_expression.
    def exitConstant_base_expression(self, ctx:Verilog2001Parser.Constant_base_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#constant_expression.
    def enterConstant_expression(self, ctx:Verilog2001Parser.Constant_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#constant_expression.
    def exitConstant_expression(self, ctx:Verilog2001Parser.Constant_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#constant_mintypmax_expression.
    def enterConstant_mintypmax_expression(self, ctx:Verilog2001Parser.Constant_mintypmax_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#constant_mintypmax_expression.
    def exitConstant_mintypmax_expression(self, ctx:Verilog2001Parser.Constant_mintypmax_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#constant_range_expression.
    def enterConstant_range_expression(self, ctx:Verilog2001Parser.Constant_range_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#constant_range_expression.
    def exitConstant_range_expression(self, ctx:Verilog2001Parser.Constant_range_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#dimension_constant_expression.
    def enterDimension_constant_expression(self, ctx:Verilog2001Parser.Dimension_constant_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#dimension_constant_expression.
    def exitDimension_constant_expression(self, ctx:Verilog2001Parser.Dimension_constant_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#expression.
    def enterExpression(self, ctx:Verilog2001Parser.ExpressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#expression.
    def exitExpression(self, ctx:Verilog2001Parser.ExpressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#term.
    def enterTerm(self, ctx:Verilog2001Parser.TermContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#term.
    def exitTerm(self, ctx:Verilog2001Parser.TermContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#lsb_constant_expression.
    def enterLsb_constant_expression(self, ctx:Verilog2001Parser.Lsb_constant_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#lsb_constant_expression.
    def exitLsb_constant_expression(self, ctx:Verilog2001Parser.Lsb_constant_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#mintypmax_expression.
    def enterMintypmax_expression(self, ctx:Verilog2001Parser.Mintypmax_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#mintypmax_expression.
    def exitMintypmax_expression(self, ctx:Verilog2001Parser.Mintypmax_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_path_conditional_expression.
    def enterModule_path_conditional_expression(self, ctx:Verilog2001Parser.Module_path_conditional_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_path_conditional_expression.
    def exitModule_path_conditional_expression(self, ctx:Verilog2001Parser.Module_path_conditional_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_path_expression.
    def enterModule_path_expression(self, ctx:Verilog2001Parser.Module_path_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_path_expression.
    def exitModule_path_expression(self, ctx:Verilog2001Parser.Module_path_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_path_mintypmax_expression.
    def enterModule_path_mintypmax_expression(self, ctx:Verilog2001Parser.Module_path_mintypmax_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_path_mintypmax_expression.
    def exitModule_path_mintypmax_expression(self, ctx:Verilog2001Parser.Module_path_mintypmax_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#msb_constant_expression.
    def enterMsb_constant_expression(self, ctx:Verilog2001Parser.Msb_constant_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#msb_constant_expression.
    def exitMsb_constant_expression(self, ctx:Verilog2001Parser.Msb_constant_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#range_expression.
    def enterRange_expression(self, ctx:Verilog2001Parser.Range_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#range_expression.
    def exitRange_expression(self, ctx:Verilog2001Parser.Range_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#width_constant_expression.
    def enterWidth_constant_expression(self, ctx:Verilog2001Parser.Width_constant_expressionContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#width_constant_expression.
    def exitWidth_constant_expression(self, ctx:Verilog2001Parser.Width_constant_expressionContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#constant_primary.
    def enterConstant_primary(self, ctx:Verilog2001Parser.Constant_primaryContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#constant_primary.
    def exitConstant_primary(self, ctx:Verilog2001Parser.Constant_primaryContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_path_primary.
    def enterModule_path_primary(self, ctx:Verilog2001Parser.Module_path_primaryContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_path_primary.
    def exitModule_path_primary(self, ctx:Verilog2001Parser.Module_path_primaryContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#primary.
    def enterPrimary(self, ctx:Verilog2001Parser.PrimaryContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#primary.
    def exitPrimary(self, ctx:Verilog2001Parser.PrimaryContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#net_lvalue.
    def enterNet_lvalue(self, ctx:Verilog2001Parser.Net_lvalueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#net_lvalue.
    def exitNet_lvalue(self, ctx:Verilog2001Parser.Net_lvalueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#variable_lvalue.
    def enterVariable_lvalue(self, ctx:Verilog2001Parser.Variable_lvalueContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#variable_lvalue.
    def exitVariable_lvalue(self, ctx:Verilog2001Parser.Variable_lvalueContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#unary_operator.
    def enterUnary_operator(self, ctx:Verilog2001Parser.Unary_operatorContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#unary_operator.
    def exitUnary_operator(self, ctx:Verilog2001Parser.Unary_operatorContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#binary_operator.
    def enterBinary_operator(self, ctx:Verilog2001Parser.Binary_operatorContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#binary_operator.
    def exitBinary_operator(self, ctx:Verilog2001Parser.Binary_operatorContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#unary_module_path_operator.
    def enterUnary_module_path_operator(self, ctx:Verilog2001Parser.Unary_module_path_operatorContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#unary_module_path_operator.
    def exitUnary_module_path_operator(self, ctx:Verilog2001Parser.Unary_module_path_operatorContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#binary_module_path_operator.
    def enterBinary_module_path_operator(self, ctx:Verilog2001Parser.Binary_module_path_operatorContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#binary_module_path_operator.
    def exitBinary_module_path_operator(self, ctx:Verilog2001Parser.Binary_module_path_operatorContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#number.
    def enterNumber(self, ctx:Verilog2001Parser.NumberContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#number.
    def exitNumber(self, ctx:Verilog2001Parser.NumberContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#timing_spec.
    def enterTiming_spec(self, ctx:Verilog2001Parser.Timing_specContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#timing_spec.
    def exitTiming_spec(self, ctx:Verilog2001Parser.Timing_specContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#attribute_instance.
    def enterAttribute_instance(self, ctx:Verilog2001Parser.Attribute_instanceContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#attribute_instance.
    def exitAttribute_instance(self, ctx:Verilog2001Parser.Attribute_instanceContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#attr_spec.
    def enterAttr_spec(self, ctx:Verilog2001Parser.Attr_specContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#attr_spec.
    def exitAttr_spec(self, ctx:Verilog2001Parser.Attr_specContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#attr_name.
    def enterAttr_name(self, ctx:Verilog2001Parser.Attr_nameContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#attr_name.
    def exitAttr_name(self, ctx:Verilog2001Parser.Attr_nameContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#arrayed_identifier.
    def enterArrayed_identifier(self, ctx:Verilog2001Parser.Arrayed_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#arrayed_identifier.
    def exitArrayed_identifier(self, ctx:Verilog2001Parser.Arrayed_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#block_identifier.
    def enterBlock_identifier(self, ctx:Verilog2001Parser.Block_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#block_identifier.
    def exitBlock_identifier(self, ctx:Verilog2001Parser.Block_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#cell_identifier.
    def enterCell_identifier(self, ctx:Verilog2001Parser.Cell_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#cell_identifier.
    def exitCell_identifier(self, ctx:Verilog2001Parser.Cell_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#config_identifier.
    def enterConfig_identifier(self, ctx:Verilog2001Parser.Config_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#config_identifier.
    def exitConfig_identifier(self, ctx:Verilog2001Parser.Config_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#escaped_arrayed_identifier.
    def enterEscaped_arrayed_identifier(self, ctx:Verilog2001Parser.Escaped_arrayed_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#escaped_arrayed_identifier.
    def exitEscaped_arrayed_identifier(self, ctx:Verilog2001Parser.Escaped_arrayed_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#escaped_hierarchical_identifier.
    def enterEscaped_hierarchical_identifier(self, ctx:Verilog2001Parser.Escaped_hierarchical_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#escaped_hierarchical_identifier.
    def exitEscaped_hierarchical_identifier(self, ctx:Verilog2001Parser.Escaped_hierarchical_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#event_identifier.
    def enterEvent_identifier(self, ctx:Verilog2001Parser.Event_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#event_identifier.
    def exitEvent_identifier(self, ctx:Verilog2001Parser.Event_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#function_identifier.
    def enterFunction_identifier(self, ctx:Verilog2001Parser.Function_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#function_identifier.
    def exitFunction_identifier(self, ctx:Verilog2001Parser.Function_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#gate_instance_identifier.
    def enterGate_instance_identifier(self, ctx:Verilog2001Parser.Gate_instance_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#gate_instance_identifier.
    def exitGate_instance_identifier(self, ctx:Verilog2001Parser.Gate_instance_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#generate_block_identifier.
    def enterGenerate_block_identifier(self, ctx:Verilog2001Parser.Generate_block_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#generate_block_identifier.
    def exitGenerate_block_identifier(self, ctx:Verilog2001Parser.Generate_block_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#genvar_function_identifier.
    def enterGenvar_function_identifier(self, ctx:Verilog2001Parser.Genvar_function_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#genvar_function_identifier.
    def exitGenvar_function_identifier(self, ctx:Verilog2001Parser.Genvar_function_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#genvar_identifier.
    def enterGenvar_identifier(self, ctx:Verilog2001Parser.Genvar_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#genvar_identifier.
    def exitGenvar_identifier(self, ctx:Verilog2001Parser.Genvar_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#hierarchical_block_identifier.
    def enterHierarchical_block_identifier(self, ctx:Verilog2001Parser.Hierarchical_block_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#hierarchical_block_identifier.
    def exitHierarchical_block_identifier(self, ctx:Verilog2001Parser.Hierarchical_block_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#hierarchical_event_identifier.
    def enterHierarchical_event_identifier(self, ctx:Verilog2001Parser.Hierarchical_event_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#hierarchical_event_identifier.
    def exitHierarchical_event_identifier(self, ctx:Verilog2001Parser.Hierarchical_event_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#hierarchical_function_identifier.
    def enterHierarchical_function_identifier(self, ctx:Verilog2001Parser.Hierarchical_function_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#hierarchical_function_identifier.
    def exitHierarchical_function_identifier(self, ctx:Verilog2001Parser.Hierarchical_function_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#hierarchical_identifier.
    def enterHierarchical_identifier(self, ctx:Verilog2001Parser.Hierarchical_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#hierarchical_identifier.
    def exitHierarchical_identifier(self, ctx:Verilog2001Parser.Hierarchical_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#hierarchical_net_identifier.
    def enterHierarchical_net_identifier(self, ctx:Verilog2001Parser.Hierarchical_net_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#hierarchical_net_identifier.
    def exitHierarchical_net_identifier(self, ctx:Verilog2001Parser.Hierarchical_net_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#hierarchical_variable_identifier.
    def enterHierarchical_variable_identifier(self, ctx:Verilog2001Parser.Hierarchical_variable_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#hierarchical_variable_identifier.
    def exitHierarchical_variable_identifier(self, ctx:Verilog2001Parser.Hierarchical_variable_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#hierarchical_task_identifier.
    def enterHierarchical_task_identifier(self, ctx:Verilog2001Parser.Hierarchical_task_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#hierarchical_task_identifier.
    def exitHierarchical_task_identifier(self, ctx:Verilog2001Parser.Hierarchical_task_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#identifier.
    def enterIdentifier(self, ctx:Verilog2001Parser.IdentifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#identifier.
    def exitIdentifier(self, ctx:Verilog2001Parser.IdentifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#inout_port_identifier.
    def enterInout_port_identifier(self, ctx:Verilog2001Parser.Inout_port_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#inout_port_identifier.
    def exitInout_port_identifier(self, ctx:Verilog2001Parser.Inout_port_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#input_port_identifier.
    def enterInput_port_identifier(self, ctx:Verilog2001Parser.Input_port_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#input_port_identifier.
    def exitInput_port_identifier(self, ctx:Verilog2001Parser.Input_port_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#instance_identifier.
    def enterInstance_identifier(self, ctx:Verilog2001Parser.Instance_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#instance_identifier.
    def exitInstance_identifier(self, ctx:Verilog2001Parser.Instance_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#library_identifier.
    def enterLibrary_identifier(self, ctx:Verilog2001Parser.Library_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#library_identifier.
    def exitLibrary_identifier(self, ctx:Verilog2001Parser.Library_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#memory_identifier.
    def enterMemory_identifier(self, ctx:Verilog2001Parser.Memory_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#memory_identifier.
    def exitMemory_identifier(self, ctx:Verilog2001Parser.Memory_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_identifier.
    def enterModule_identifier(self, ctx:Verilog2001Parser.Module_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_identifier.
    def exitModule_identifier(self, ctx:Verilog2001Parser.Module_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#module_instance_identifier.
    def enterModule_instance_identifier(self, ctx:Verilog2001Parser.Module_instance_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#module_instance_identifier.
    def exitModule_instance_identifier(self, ctx:Verilog2001Parser.Module_instance_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#net_identifier.
    def enterNet_identifier(self, ctx:Verilog2001Parser.Net_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#net_identifier.
    def exitNet_identifier(self, ctx:Verilog2001Parser.Net_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#output_port_identifier.
    def enterOutput_port_identifier(self, ctx:Verilog2001Parser.Output_port_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#output_port_identifier.
    def exitOutput_port_identifier(self, ctx:Verilog2001Parser.Output_port_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#parameter_identifier.
    def enterParameter_identifier(self, ctx:Verilog2001Parser.Parameter_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#parameter_identifier.
    def exitParameter_identifier(self, ctx:Verilog2001Parser.Parameter_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#port_identifier.
    def enterPort_identifier(self, ctx:Verilog2001Parser.Port_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#port_identifier.
    def exitPort_identifier(self, ctx:Verilog2001Parser.Port_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#real_identifier.
    def enterReal_identifier(self, ctx:Verilog2001Parser.Real_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#real_identifier.
    def exitReal_identifier(self, ctx:Verilog2001Parser.Real_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#simple_arrayed_identifier.
    def enterSimple_arrayed_identifier(self, ctx:Verilog2001Parser.Simple_arrayed_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#simple_arrayed_identifier.
    def exitSimple_arrayed_identifier(self, ctx:Verilog2001Parser.Simple_arrayed_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#simple_hierarchical_identifier.
    def enterSimple_hierarchical_identifier(self, ctx:Verilog2001Parser.Simple_hierarchical_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#simple_hierarchical_identifier.
    def exitSimple_hierarchical_identifier(self, ctx:Verilog2001Parser.Simple_hierarchical_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#specparam_identifier.
    def enterSpecparam_identifier(self, ctx:Verilog2001Parser.Specparam_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#specparam_identifier.
    def exitSpecparam_identifier(self, ctx:Verilog2001Parser.Specparam_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#system_function_identifier.
    def enterSystem_function_identifier(self, ctx:Verilog2001Parser.System_function_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#system_function_identifier.
    def exitSystem_function_identifier(self, ctx:Verilog2001Parser.System_function_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#system_task_identifier.
    def enterSystem_task_identifier(self, ctx:Verilog2001Parser.System_task_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#system_task_identifier.
    def exitSystem_task_identifier(self, ctx:Verilog2001Parser.System_task_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#task_identifier.
    def enterTask_identifier(self, ctx:Verilog2001Parser.Task_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#task_identifier.
    def exitTask_identifier(self, ctx:Verilog2001Parser.Task_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#terminal_identifier.
    def enterTerminal_identifier(self, ctx:Verilog2001Parser.Terminal_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#terminal_identifier.
    def exitTerminal_identifier(self, ctx:Verilog2001Parser.Terminal_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#text_macro_identifier.
    def enterText_macro_identifier(self, ctx:Verilog2001Parser.Text_macro_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#text_macro_identifier.
    def exitText_macro_identifier(self, ctx:Verilog2001Parser.Text_macro_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#topmodule_identifier.
    def enterTopmodule_identifier(self, ctx:Verilog2001Parser.Topmodule_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#topmodule_identifier.
    def exitTopmodule_identifier(self, ctx:Verilog2001Parser.Topmodule_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#udp_identifier.
    def enterUdp_identifier(self, ctx:Verilog2001Parser.Udp_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#udp_identifier.
    def exitUdp_identifier(self, ctx:Verilog2001Parser.Udp_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#udp_instance_identifier.
    def enterUdp_instance_identifier(self, ctx:Verilog2001Parser.Udp_instance_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#udp_instance_identifier.
    def exitUdp_instance_identifier(self, ctx:Verilog2001Parser.Udp_instance_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#variable_identifier.
    def enterVariable_identifier(self, ctx:Verilog2001Parser.Variable_identifierContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#variable_identifier.
    def exitVariable_identifier(self, ctx:Verilog2001Parser.Variable_identifierContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#simple_hierarchical_branch.
    def enterSimple_hierarchical_branch(self, ctx:Verilog2001Parser.Simple_hierarchical_branchContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#simple_hierarchical_branch.
    def exitSimple_hierarchical_branch(self, ctx:Verilog2001Parser.Simple_hierarchical_branchContext):
        pass


    # Enter a parse tree produced by Verilog2001Parser#escaped_hierarchical_branch.
    def enterEscaped_hierarchical_branch(self, ctx:Verilog2001Parser.Escaped_hierarchical_branchContext):
        pass

    # Exit a parse tree produced by Verilog2001Parser#escaped_hierarchical_branch.
    def exitEscaped_hierarchical_branch(self, ctx:Verilog2001Parser.Escaped_hierarchical_branchContext):
        pass



del Verilog2001Parser