#!/usr/bin/env python3
"""
DooPourd v0.6.0 - Standalone Windows Demo
No external tools required!
Works on any Windows PC with just Python
"""

from verilog_framework.core import parse_verilog
from pathlib import Path

print("=" * 70)
print("DooPourd v0.6.0 - Standalone Verilog Parser")
print("Windows Only - No External Tools Required!")
print("=" * 70)

# Example 1: Parse from string
print("\n[Example 1] Parse from String\n")
code1 = """
module mux(
    input a,
    input b,
    input sel,
    output out
);
    assign out = a;
endmodule
"""

ast1 = parse_verilog(code1)
print(f"✓ Module name: {ast1.name}")
print(f"✓ Number of ports: {len(ast1.port_list)}")
print(f"✓ Port list:")
for port in ast1.port_list:
    print(f"    - {port.direction}: {port.name}")

# Example 2: Parse from file
print("\n[Example 2] Parse from File\n")
test_file = Path("counter.v")
code2 = """
module counter(
    input clk,
    input reset,
    output [7:0] count
);
    reg [7:0] count;
endmodule
"""

test_file.write_text(code2)
ast2 = parse_verilog(test_file.read_text())
print(f"✓ Module: {ast2.name}")
print(f"✓ Ports: {len(ast2.port_list)}")

# Example 3: Analyze complex module
print("\n[Example 3] Complex Module Analysis\n")
code3 = """
module alu(
    input [7:0] a,
    input [7:0] b,
    output [7:0] result
);
    assign result = a;
endmodule
"""

ast3 = parse_verilog(code3)
print(f"✓ Module: {ast3.name}")
print(f"✓ Inputs: {sum(1 for p in ast3.port_list if p.direction == 'input')}")
print(f"✓ Outputs: {sum(1 for p in ast3.port_list if p.direction == 'output')}")
print(f"✓ Logic statements: {len(ast3.statements)}")

# Example 4: Extract design metrics
print("\n[Example 4] Design Metrics\n")
modules = [
    ("adder", """
module adder(input a, input b, output sum);
    assign sum = a + b;
endmodule
"""),
    ("buffer", """
module buffer(input x, output y);
    assign y = x;
endmodule
"""),
    ("inverter", """
module inverter(input in, output out);
    assign out = in;
endmodule
"""),
]

print("Available modules:")
for name, code in modules:
    try:
        ast = parse_verilog(code)
        in_count = sum(1 for p in ast.port_list if p.direction == 'input')
        out_count = sum(1 for p in ast.port_list if p.direction == 'output')
        print(f"  ✓ {ast.name:12} - {in_count} input(s), {out_count} output(s)")
    except Exception as e:
        print(f"  ✗ {name:12} - Parse error: {str(e)[:40]}")

# Example 5: Statistics
print("\n[Example 5] Parsing Statistics\n")
test_codes = [code1, code2, code3]
total_lines = sum(len(c.split('\n')) for c in test_codes)
total_chars = sum(len(c) for c in test_codes)

print(f"✓ Parsed modules: {len(test_codes)}")
print(f"✓ Total lines: {total_lines}")
print(f"✓ Total characters: {total_chars}")
print(f"✓ Average lines per module: {total_lines // len(test_codes)}")

print("\n" + "=" * 70)
print("Summary:")
print("=" * 70)
print("✓ Core parsing works on any Windows PC!")
print("✓ No external dependencies required!")
print("✓ No Yosys, no Linux, no WSL needed!")
print("\nFor circuit diagrams, you can:")
print("  1. Use Docker (if installed)")
print("  2. Use Ubuntu/WSL (if available)")
print("  3. Convert SVG to PNG using:")
print("     - ImageMagick: imagemagick.org")
print("     - Inkscape: inkscape.org")
print("     - Online tools: cloudconvert.com/svg-to-png")
print("\nBut core parsing? ✓ Works perfectly!")
print("=" * 70)

# Cleanup
test_file.unlink()
