import sys
from pathlib import Path

sys.path.insert(0, str(Path(__file__).parent.parent))

from verilog_framework.core.lexer import VerilogLexer
from verilog_framework.core.parser import VerilogParser
from verilog_framework.verilogtoimage import VerilogToImagePipeline, get_logger


def example_adder_circuit():
    logger = get_logger()
    
    verilog_code = """
    module adder(
        input a,
        input b,
        output sum,
        output carry
    );
        assign sum = a ^ b;
        assign carry = a & b;
    endmodule
    """
    
    logger.info("Example: 1-bit Adder Circuit")
    logger.info("-" * 50)
    
    lexer = VerilogLexer(verilog_code)
    tokens = lexer.tokenize()
    parser = VerilogParser(tokens)
    ast = parser.parse()
    
    logger.info(f"Module: {ast.name}")
    logger.info(f"Inputs: {[p.name for p in ast.port_list if p.direction == 'input']}")
    logger.info(f"Outputs: {[p.name for p in ast.port_list if p.direction == 'output']}")
    
    pipeline = VerilogToImagePipeline()
    
    svg_result = pipeline.verilog_to_svg(verilog_code, "adder.svg")
    if svg_result:
        logger.info(f"SVG generated: {svg_result}")
        
        png_result = pipeline.cairo_svg.svg_to_png(svg_result, "adder.png")
        if png_result:
            logger.info(f"PNG generated: {png_result}")


if __name__ == "__main__":
    example_adder_circuit()
