import sys
from pathlib import Path

sys.path.insert(0, str(Path(__file__).parent.parent))

from verilog_framework.core.lexer import VerilogLexer
from verilog_framework.core.parser import VerilogParser
from verilog_framework.verilogtoimage import VerilogToImagePipeline


def test_simple_verilog_to_image():
    code = """
    module and_gate(
        input a,
        input b,
        output out
    );
        assign out = a & b;
    endmodule
    """
    
    print("Test: Simple Verilog to SVG conversion")
    print("=" * 50)
    
    lexer = VerilogLexer(code)
    tokens = lexer.tokenize()
    parser = VerilogParser(tokens)
    ast = parser.parse()
    
    print(f"✓ Parsed module: {ast.name}")
    print(f"✓ Ports: {len(ast.port_list)}")
    print(f"✓ Statements: {len(ast.statements)}")
    
    print("\nStarting image generation pipeline...")
    pipeline = VerilogToImagePipeline()
    
    output_svg = pipeline.verilog_to_svg(code, "test_and_gate.svg")
    
    if output_svg:
        print(f"✓ SVG generated: {output_svg}")
    else:
        print("✗ SVG generation failed")
    
    print("=" * 50)


if __name__ == "__main__":
    test_simple_verilog_to_image()
