import sys
from pathlib import Path

sys.path.insert(0, str(Path(__file__).parent.parent))

from verilog_framework.core.lexer import VerilogLexer
from verilog_framework.core.parser import VerilogParser
from verilog_framework.visualization.visualizer import GraphvizVisualizer


def test_visualizer_dot_generation():
    code = """
    module test(
        input a,
        output b
    );
        assign b = a;
    endmodule
    """
    lexer = VerilogLexer(code)
    tokens = lexer.tokenize()
    parser = VerilogParser(tokens)
    ast = parser.parse()
    
    visualizer = GraphvizVisualizer()
    dot = visualizer.generate_dot(ast)
    
    assert "digraph G" in dot
    assert "test" in dot
    assert "rankdir=TB" in dot
    assert "->" in dot
    print("✓ test_visualizer_dot_generation passed")


def test_visualizer_node_creation():
    code = """
    module test();
        wire sig;
        assign sig = 1;
    endmodule
    """
    lexer = VerilogLexer(code)
    tokens = lexer.tokenize()
    parser = VerilogParser(tokens)
    ast = parser.parse()
    
    visualizer = GraphvizVisualizer()
    dot = visualizer.generate_dot(ast)
    
    assert "Module: test" in dot
    assert "Wire: sig" in dot
    assert "Assign" in dot
    print("✓ test_visualizer_node_creation passed")


def test_visualizer_with_ports():
    code = """
    module adder(
        input a,
        input b,
        output result
    );
        assign result = a + b;
    endmodule
    """
    lexer = VerilogLexer(code)
    tokens = lexer.tokenize()
    parser = VerilogParser(tokens)
    ast = parser.parse()
    
    visualizer = GraphvizVisualizer()
    dot = visualizer.generate_dot(ast)
    
    assert "(input)" in dot
    assert "(output)" in dot
    assert "Op: +" in dot
    print("✓ test_visualizer_with_ports passed")


def test_visualizer_with_always():
    code = """
    module test();
        always @(posedge clk) begin
            out <= in;
        end
    endmodule
    """
    lexer = VerilogLexer(code)
    tokens = lexer.tokenize()
    parser = VerilogParser(tokens)
    ast = parser.parse()
    
    visualizer = GraphvizVisualizer()
    dot = visualizer.generate_dot(ast)
    
    assert "Always:" in dot
    print("✓ test_visualizer_with_always passed")


def test_visualizer_complex_structure():
    code = """
    module complex(
        input data_in,
        output data_out
    );
        wire temp;
        assign temp = data_in;
        assign data_out = temp;
        always @(posedge clk) begin
            data_out <= temp;
        end
    endmodule
    """
    lexer = VerilogLexer(code)
    tokens = lexer.tokenize()
    parser = VerilogParser(tokens)
    ast = parser.parse()
    
    visualizer = GraphvizVisualizer()
    dot = visualizer.generate_dot(ast)
    
    assert "complex" in dot
    assert "data_in" in dot
    assert "data_out" in dot
    print("✓ test_visualizer_complex_structure passed")


if __name__ == "__main__":
    test_visualizer_dot_generation()
    test_visualizer_node_creation()
    test_visualizer_with_ports()
    test_visualizer_with_always()
    test_visualizer_complex_structure()
    print("\nAll visualizer tests passed! ✓")
