# Core imports (no external dependencies required)
try:
    from verilog_framework.core import (
        Module, Port, VerilogLexer, VerilogParser
    )
except ImportError:
    from .core import (
        Module, Port, VerilogLexer, VerilogParser
    )

# Optional: Visualization (requires graphviz)
try:
    try:
        from verilog_framework.visualization import GraphvizVisualizer
    except ImportError:
        from .visualization import GraphvizVisualizer
    _visualization_available = True
except (ImportError, Exception):
    GraphvizVisualizer = None
    _visualization_available = False

# Optional: Circuit diagram generation (requires graphviz, cairosvg, and external tools)
try:
    try:
        from verilog_framework.verilogtoimage import VerilogToImagePipeline, get_logger
    except ImportError:
        from .verilogtoimage import VerilogToImagePipeline, get_logger
    _circuit_available = True
except (ImportError, Exception):
    VerilogToImagePipeline = None
    get_logger = None
    _circuit_available = False

__version__ = "0.7.0"
__author__ = "vesper"
__email__ = "vesper.oneold@gmail.com"
__license__ = "MIT"

__all__ = [
    # Core (always available)
    'Module', 'Port',
    'VerilogLexer', 'VerilogParser',
    # Optional
    'GraphvizVisualizer',
    'VerilogToImagePipeline', 'get_logger',
    # Metadata
    '__version__', '__author__', '__email__', '__license__'
]
