import sys
from pathlib import Path

sys.path.insert(0, str(Path(__file__).parent.parent))

from examples.cli import VerilogProcessor


def test_processor_load_file():
    processor = VerilogProcessor("examples/test_module.v")
    content = processor.load_file()
    assert "module" in content
    assert "adder" in content
    print("✓ test_processor_load_file passed")


def test_processor_parse():
    processor = VerilogProcessor("examples/test_module.v")
    ast = processor.process()
    
    assert ast is not None
    assert ast.name == "adder"
    assert len(ast.port_list) > 0
    print("✓ test_processor_parse passed")


def test_processor_visualize():
    processor = VerilogProcessor("examples/test_module.v")
    ast = processor.process()
    output_path = processor.visualize("test_output")
    
    assert output_path is not None
    assert "test_output" in output_path
    print("✓ test_processor_visualize passed")


if __name__ == "__main__":
    test_processor_load_file()
    test_processor_parse()
    test_processor_visualize()
    print("\nAll processor tests passed! ✓")
