try:
    from verilog_framework.core.ast_nodes import (
        Module, Port, WireDeclaration, RegDeclaration,
        Assign, Always, Identifier, Number, BinaryOp, UnaryOp
    )
    from verilog_framework.core.lexer import VerilogLexer, Token, TokenType
    from verilog_framework.core.parser import VerilogParser
except ImportError:
    from .ast_nodes import (
        Module, Port, WireDeclaration, RegDeclaration,
        Assign, Always, Identifier, Number, BinaryOp, UnaryOp
    )
    from .lexer import VerilogLexer, Token, TokenType
    from .parser import VerilogParser


def parse_verilog(code: str) -> Module:
    """
    Parse Verilog code and return AST.
    
    Args:
        code: Verilog source code string
        
    Returns:
        Module AST node
        
    Example:
        >>> ast = parse_verilog("module adder(input a, b, output sum); assign sum = a + b; endmodule")
        >>> print(ast.name)
        'adder'
    """
    lexer = VerilogLexer(code)
    tokens = lexer.tokenize()
    parser = VerilogParser(tokens)
    return parser.parse()


__all__ = [
    'Module', 'Port', 'WireDeclaration', 'RegDeclaration',
    'Assign', 'Always', 'Identifier', 'Number', 'BinaryOp', 'UnaryOp',
    'VerilogLexer', 'VerilogParser', 'Token', 'TokenType',
    'parse_verilog'
]
