{#- Many thanks to github.com/EgorVorontsov for providing base for this template #}

{#- MACRO #}
{#- bit field range #}
{% macro range(bf) %}
    {% if bf.width == 1 %}
{{ bf.msb }}
    {%- else %}
{{ bf.msb }}:{{ bf.lsb }}
    {%- endif %}
{%- endmacro %}

{#- bit field mode #}
{% macro mode(bf) %}
{{ bf.access }}
{%- endmacro %}

{#- value in hex format #}
{% macro literal(initial, width) %}
{{ "0x%0{w}x".format(w=width // 4) % initial }}
{%- endmacro %}

{#- TEMPLATE NAMESPACE #}
{% set tmp = namespace() %}

{#- TEMPLATE #}
== {{ title }}

Created with https://github.com/esynr3z/corsair[Corsair] v{{ corsair_ver }}.

{% if print_conventions %}
=== Conventions

[#table-Register_access_modes,cols="1,1", options="header"]
|==========================
| Access mode | Description
| rw          | Read and Write
| rw1c        | Read and Write 1 to Clear
| rw1s        | Read and Write 1 to Set
| ro          | Read Only
| roc         | Read Only to Clear
| roll        | Read Only / Latch Low
| rolh        | Read Only / Latch High
| wo          | Write only
| wosc        | Write Only / Self Clear
|==========================
{% endif %}

[[register_map_summary]]
=== Register map summary

Base address: {{ "0x%08x" % config['base_address'] }}

[#table-Register_map,cols="1,1,1", options="header"]
|==========================
| Name | Address | Description
{% for reg in rmap %}
{{ "| %-24s | %-10s | %s" % ("<<%s>>" % (reg.name), literal(reg.address, config['address_width']), reg.description) }}
{% endfor %}
|==========================


{% for reg in rmap %}

[[{{ reg.name }}]]
=== {{ reg.name }}

{{ reg.description }}

Address offset: {{ literal(reg.address, config['address_width']) }}

Reset value: {{ literal(reg.reset, config['data_width']) }}

{% if print_images %}
image::{{ image_dir }}/{{ reg.name.lower()}}.svg[{{ reg.name.lower()}}]
{% endif %}

[#table-{{ reg.name }},cols="1,1,1,1,1", options="header"]
|==========================
| Name | Bits | Mode | Reset | Description
{% for bf in reg.bitfields[::-1] %}
{{ "| %-16s | %-6s | %-15s | %-10s | %s" % (bf.name, range(bf), mode(bf), literal(bf.reset, bf.width), bf.description) }}
{% endfor %}
|==========================

{% for bf in reg %}
    {% if bf.enums %}

Enumerated values for {{ reg.name }}.{{ bf.name }}.

[#table-{{ reg.name }}_{{ bf.name }}_enums,cols="1,1,1", options="header"]
|==========================
| Name | Bits | Description
            {% for enum in bf %}
{{ "| %-16s | %-6s | %s" % (enum.name, literal(enum.value, bf.width), enum.description) }}
            {% endfor %}
|==========================
    {% endif %}
{% endfor %}

Back to  <<register_map_summary>>
{% endfor %}
