Metadata-Version: 2.1
Name: chipscopy
Version: 2023.1.dev1671238423
Summary: Open-source project from Xilinx® that enables high-level control of Versal debug IP running in hardware
Home-page: https://github.com/Xilinx/chipscopy
License: Apache-2.0 AND EPL-2.0
Author: Xilinx ChipScope Team
Maintainer: Xilinx ChipScope Team
Requires-Python: >=3.7.1,<4.0.0
Classifier: License :: Other/Proprietary License
Classifier: Programming Language :: Python :: 3
Classifier: Programming Language :: Python :: 3.8
Classifier: Programming Language :: Python :: 3.9
Classifier: Programming Language :: Python :: 3.10
Classifier: Programming Language :: Python :: 3.11
Provides-Extra: core-addons
Provides-Extra: jupyter
Requires-Dist: Click (>7,<9)
Requires-Dist: PyQt5 (>=5.15.4,<6.0.0) ; extra == "core-addons"
Requires-Dist: antlr4-python3-runtime (>=4.10,<5.0)
Requires-Dist: importlib_metadata (>=4.4,<5.0)
Requires-Dist: ipywidgets (>=7.5.1,<8.0.0) ; extra == "jupyter"
Requires-Dist: kaleido (>=0.0.2,<0.0.3) ; extra == "core-addons"
Requires-Dist: loguru (>=0.5.0,<0.6.0)
Requires-Dist: matplotlib (>=3.4.0,<4.0.0) ; extra == "core-addons"
Requires-Dist: more-itertools (>=8.2.0,<9.0.0)
Requires-Dist: notebook (>=6.0.3,<7.0.0) ; extra == "jupyter"
Requires-Dist: pandas (>=1.2.3,<2.0.0) ; extra == "core-addons"
Requires-Dist: plotly (>=4.9.0,<5.0.0) ; extra == "core-addons"
Requires-Dist: rich (>=9.12.4,<10.0.0)
Requires-Dist: typing_extensions (>=3.7.4,<4.0.0)
Project-URL: Bug Tracker, https://github.com/Xilinx/chipscopy/issues
Project-URL: Documentation, https://xilinx.github.io/chipscopy/
Project-URL: Repository, https://github.com/Xilinx/chipscopy
Description-Content-Type: text/markdown

# 🐍 ChipScoPy README

[![](https://img.shields.io/badge/code%20style-black-000000.svg)](https://github.com/psf/black)

![](https://raw.githubusercontent.com/Xilinx/chipscopy/master/docs/images/chipscopy_logo_head_right_transparent_background.png)

ChipScoPy is an open-source project from Xilinx® that enables high-level control of Versal debug IP running in hardware.
Using a simple Python API, developers can control and communicate with ChipScope® debug IP such as the Integrated Logic
Analyzer (ILA), Virtual IO (VIO), device memory access, and more.

ChipScoPy communicates with Versal devices. It does not work with older devices such as Ultrascale+ and 7-Series devices.

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![](https://raw.githubusercontent.com/Xilinx/chipscopy/master/docs/images/chipscopy_overview.png)

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[ChipScoPy Overview](https://xilinx.github.io/chipscopy/2023.1/overview.html)

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[System Requirements](https://xilinx.github.io/chipscopy/2023.1/system_requirements.html)

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[ChipScoPy Installation](https://xilinx.github.io/chipscopy/2023.1/chipscopy_installation.html)

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[ChipScoPy Examples](https://github.com/Xilinx/chipscopy/tree/master/chipscopy/examples)

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[FAQ](https://github.com/Xilinx/chipscopy/blob/master/FAQ.md)

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[API Documentation](https://xilinx.github.io/chipscopy/)

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