# 🐍 ChipScoPy README

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ChipScoPy is an open-source project from Xilinx® that enables high-level control of Versal debug IP running in hardware.
Using a simple Python API, developers can control and communicate with ChipScope® debug IP such as the Integrated Logic
Analyzer (ILA), Virtual IO (VIO), device memory access, and more.

ChipScoPy communicates with Versal devices. It does not work with older devices such as Ultrascale+ and 7-Series devices.

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![](https://raw.githubusercontent.com/Xilinx/chipscopy/master/docs/images/chipscopy_overview.png)

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[ChipScoPy Overview](https://xilinx.github.io/chipscopy/2023.1/overview.html)

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[System Requirements](https://xilinx.github.io/chipscopy/2023.1/system_requirements.html)

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[ChipScoPy Installation](https://xilinx.github.io/chipscopy/2023.1/chipscopy_installation.html)

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[ChipScoPy Examples](https://github.com/Xilinx/chipscopy/tree/master/chipscopy/examples)

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[FAQ](https://github.com/Xilinx/chipscopy/blob/master/FAQ.md)

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[API Documentation](https://xilinx.github.io/chipscopy/)

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