// Generated register defines for clock
#ifndef _CLOCK_REG_DEFS_
#define _CLOCK_REG_DEFS_

#ifdef __cplusplus
extern "C" {
#endif
// Register width
#define CLOCK_PARAM_REG_WIDTH 32

// PLL control register
#define CLOCK_CONTROL_REG_OFFSET 0x0
#define CLOCK_CONTROL_REG_RESVAL 0x3
#define CLOCK_CONTROL_RESET_BIT 0
#define CLOCK_CONTROL_BYPASS_BIT 1
#define CLOCK_CONTROL_NEWDIV_BIT 2
#define CLOCK_CONTROL_USEREF_BIT 3

// PLL pre-divider register
#define CLOCK_PRE_DIVIDE_REG_OFFSET 0x4
#define CLOCK_PRE_DIVIDE_REG_RESVAL 0x0
#define CLOCK_PRE_DIVIDE_DIVR_MASK 0x3f
#define CLOCK_PRE_DIVIDE_DIVR_OFFSET 0
#define CLOCK_PRE_DIVIDE_DIVR_FIELD \
  ((bitfield_field32_t) { .mask = CLOCK_PRE_DIVIDE_DIVR_MASK, .index = CLOCK_PRE_DIVIDE_DIVR_OFFSET })

// PLL feedback integer divider register
#define CLOCK_FB_DIVIDE_INTEGER_REG_OFFSET 0x8
#define CLOCK_FB_DIVIDE_INTEGER_REG_RESVAL 0x0
#define CLOCK_FB_DIVIDE_INTEGER_DIVFI_MASK 0x1ff
#define CLOCK_FB_DIVIDE_INTEGER_DIVFI_OFFSET 0
#define CLOCK_FB_DIVIDE_INTEGER_DIVFI_FIELD \
  ((bitfield_field32_t) { .mask = CLOCK_FB_DIVIDE_INTEGER_DIVFI_MASK, .index = CLOCK_FB_DIVIDE_INTEGER_DIVFI_OFFSET })

// PLL feedback factional divider register
#define CLOCK_FB_DIVIDE_FRACTION_REG_OFFSET 0xc
#define CLOCK_FB_DIVIDE_FRACTION_REG_RESVAL 0x0
#define CLOCK_FB_DIVIDE_FRACTION_DIVFF_MASK 0xffffff
#define CLOCK_FB_DIVIDE_FRACTION_DIVFF_OFFSET 0
#define CLOCK_FB_DIVIDE_FRACTION_DIVFF_FIELD \
  ((bitfield_field32_t) { .mask = CLOCK_FB_DIVIDE_FRACTION_DIVFF_MASK, .index = CLOCK_FB_DIVIDE_FRACTION_DIVFF_OFFSET })

// PLL post-divider register
#define CLOCK_POST_DIVIDE_REG_OFFSET 0x10
#define CLOCK_POST_DIVIDE_REG_RESVAL 0x0
#define CLOCK_POST_DIVIDE_DIVQ_MASK 0x1f
#define CLOCK_POST_DIVIDE_DIVQ_OFFSET 0
#define CLOCK_POST_DIVIDE_DIVQ_FIELD \
  ((bitfield_field32_t) { .mask = CLOCK_POST_DIVIDE_DIVQ_MASK, .index = CLOCK_POST_DIVIDE_DIVQ_OFFSET })

// PLL filter range selection
#define CLOCK_FILTER_RANGE_REG_OFFSET 0x14
#define CLOCK_FILTER_RANGE_REG_RESVAL 0x0
#define CLOCK_FILTER_RANGE_RANGE_MASK 0x7
#define CLOCK_FILTER_RANGE_RANGE_OFFSET 0
#define CLOCK_FILTER_RANGE_RANGE_FIELD \
  ((bitfield_field32_t) { .mask = CLOCK_FILTER_RANGE_RANGE_MASK, .index = CLOCK_FILTER_RANGE_RANGE_OFFSET })

// PLL spread spectrum controls
#define CLOCK_SPREAD_SPECTRUM_REG_OFFSET 0x18
#define CLOCK_SPREAD_SPECTRUM_REG_RESVAL 0x0
#define CLOCK_SPREAD_SPECTRUM_ENABLE_BIT 0
#define CLOCK_SPREAD_SPECTRUM_DOWN_SPREAD_BIT 1
#define CLOCK_SPREAD_SPECTRUM_MODULATION_DEPTH_MASK 0x7
#define CLOCK_SPREAD_SPECTRUM_MODULATION_DEPTH_OFFSET 4
#define CLOCK_SPREAD_SPECTRUM_MODULATION_DEPTH_FIELD \
  ((bitfield_field32_t) { .mask = CLOCK_SPREAD_SPECTRUM_MODULATION_DEPTH_MASK, .index = CLOCK_SPREAD_SPECTRUM_MODULATION_DEPTH_OFFSET })
#define CLOCK_SPREAD_SPECTRUM_MODULATION_FREQUENCY_MASK 0xf
#define CLOCK_SPREAD_SPECTRUM_MODULATION_FREQUENCY_OFFSET 8
#define CLOCK_SPREAD_SPECTRUM_MODULATION_FREQUENCY_FIELD \
  ((bitfield_field32_t) { .mask = CLOCK_SPREAD_SPECTRUM_MODULATION_FREQUENCY_MASK, .index = CLOCK_SPREAD_SPECTRUM_MODULATION_FREQUENCY_OFFSET })

// PLL status register
#define CLOCK_STATUS_REG_OFFSET 0x1c
#define CLOCK_STATUS_REG_RESVAL 0x0
#define CLOCK_STATUS_LOCK_BIT 0
#define CLOCK_STATUS_DIVACK_BIT 1

// Mark the end of the address space
#define CLOCK_END_OF_RANGE_REG_OFFSET 0xfffc
#define CLOCK_END_OF_RANGE_REG_RESVAL 0x0
#define CLOCK_END_OF_RANGE_MARKER_BIT 0

#ifdef __cplusplus
}  // extern "C"
#endif
#endif  // _CLOCK_REG_DEFS_
// End generated register defines for clock
