/**
 *
 * @file        apm32f407xx.h
 *
 * @brief       CMSIS APM32F407xx Device Peripheral Access Layer Header File.
 *
 * @version     V1.0.0
 *
 * @date        2023-07-31
 *
 * @attention
 *
 * Licensed under the Apache License, Version 2.0 (the License); you may
 * not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 * www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 * The original code has been modified by Geehy Semiconductor.
 *
 * Copyright (c) 2017 STMicroelectronics.
 * Copyright (C) 2023 Geehy Semiconductor.
 * All rights reserved.
 *
 * This software is licensed under terms that can be found in the LICENSE file
 * in the root directory of this software component.
 * If no LICENSE file comes with this software, it is provided AS-IS.
 *
 */

/** @addtogroup CMSIS_Device
  * @{
  */

/** @addtogroup apm32f407xx
  * @{
  */
    
#ifndef __APM32F407xx_H
#define __APM32F407xx_H

#ifdef __cplusplus
 extern "C" {
#endif /* __cplusplus */

/** @addtogroup Configuration_section_for_CMSIS
  * @{
  */

/**
  * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
  */
#define __CM4_REV                 0x0001U  /*!< Core revision r0p1                            */
#define __MPU_PRESENT             1U       /*!< APM32F4XX provides an MPU                     */
#define __NVIC_PRIO_BITS          4U       /*!< APM32F4XX uses 4 Bits for the Priority Levels */
#define __Vendor_SysTickConfig    0U       /*!< Set to 1 if different SysTick Config is used  */
#define __FPU_PRESENT             1U       /*!< FPU present                                   */

/**
  * @}
  */
  
/** @addtogroup Peripheral_interrupt_number_definition
  * @{
  */

/**
 * @brief APM32F4XX Interrupt Number Definition, according to the selected device 
 *        in @ref Library_configuration_section 
 */
typedef enum
{
/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
/******  APM32 specific Interrupt Numbers **********************************************************************/
  WWDT_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
  PVD_IRQn                    = 1,      /*!< PVD through EINT Line detection Interrupt                         */
  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EINT line             */
  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EINT line                        */
  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
  RCM_IRQn                    = 5,      /*!< RCM global Interrupt                                              */
  EINT0_IRQn                  = 6,      /*!< EINT Line0 Interrupt                                              */
  EINT1_IRQn                  = 7,      /*!< EINT Line1 Interrupt                                              */
  EINT2_IRQn                  = 8,      /*!< EINT Line2 Interrupt                                              */
  EINT3_IRQn                  = 9,      /*!< EINT Line3 Interrupt                                              */
  EINT4_IRQn                  = 10,     /*!< EINT Line4 Interrupt                                              */
  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
  EINT9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
  TMR1_BRK_TMR9_IRQn          = 24,     /*!< TMR1 Break interrupt and TMR9 global interrupt                    */
  TMR1_UP_TMR10_IRQn          = 25,     /*!< TMR1 Update Interrupt and TMR10 global interrupt                  */
  TMR1_TRG_COM_TMR11_IRQn     = 26,     /*!< TMR1 Trigger and Commutation Interrupt and TMR11 global interrupt */
  TMR1_CC_IRQn                = 27,     /*!< TMR1 Capture Compare Interrupt                                    */
  TMR2_IRQn                   = 28,     /*!< TMR2 global Interrupt                                             */
  TMR3_IRQn                   = 29,     /*!< TMR3 global Interrupt                                             */
  TMR4_IRQn                   = 30,     /*!< TMR4 global Interrupt                                             */
  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */
  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
  EINT15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EINT Line Interrupt                   */
  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EINT line interrupt                     */
  TMR8_BRK_TMR12_IRQn         = 43,     /*!< TMR8 Break Interrupt and TMR12 global interrupt                   */
  TMR8_UP_TMR13_IRQn          = 44,     /*!< TMR8 Update Interrupt and TMR13 global interrupt                  */
  TMR8_TRG_COM_TMR14_IRQn     = 45,     /*!< TMR8 Trigger and Commutation Interrupt and TMR14 global interrupt */
  TMR8_CC_IRQn                = 46,     /*!< TMR8 Capture Compare global interrupt                             */
  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
  EMMC_IRQn                   = 48,     /*!< EMMC global Interrupt                                             */
  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
  TMR5_IRQn                   = 50,     /*!< TMR5 global Interrupt                                             */
  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
  TMR6_DAC_IRQn               = 54,     /*!< TMR6 global and DAC1&2 underrun error  interrupts                 */
  TMR7_IRQn                   = 55,     /*!< TMR7 global interrupt                                             */
  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EINT line Interrupt                       */
  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */
  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EINT interrupt                          */
  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
  DCI_IRQn                    = 78,     /*!< DCI global interrupt                                              */
  RNG_IRQn                    = 80,     /*!< RNG global Interrupt                                              */
  FPU_IRQn                    = 81,     /*!< FPU global interrupt                                              */
  SM3_IRQn                    = 82,     /*!< SM3 global interrupt                                              */
  SM4_IRQn                    = 83,     /*!< SM4 global interrupt                                              */
  BN_IRQn                     = 84      /*!< BN global interrupt                                               */
} IRQn_Type;
/* Legacy define */
#define  HASH_RNG_IRQn      RNG_IRQn

/**
  * @}
  */

#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
#include "system_apm32f4xx.h"
#include <stdint.h>

/** @addtogroup Peripheral_registers_structures
  * @{
  */   

/** 
  * @brief Analog to Digital Converter  
  */

typedef struct
{
  __IO uint32_t STS;      /*!< ADC status register,                         Address offset: 0x00 */
  __IO uint32_t CTRL1;    /*!< ADC control register 1,                      Address offset: 0x04 */
  __IO uint32_t CTRL2;    /*!< ADC control register 2,                      Address offset: 0x08 */
  __IO uint32_t SMPTIM1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
  __IO uint32_t SMPTIM2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
  __IO uint32_t INJDOF1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
  __IO uint32_t INJDOF2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
  __IO uint32_t INJDOF3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
  __IO uint32_t INJDOF4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
  __IO uint32_t AWDHT;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
  __IO uint32_t AWDLT;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
  __IO uint32_t REGSEQ1;  /*!< ADC regular sequence register 1,             Address offset: 0x2C */
  __IO uint32_t REGSEQ2;  /*!< ADC regular sequence register 2,             Address offset: 0x30 */
  __IO uint32_t REGSEQ3;  /*!< ADC regular sequence register 3,             Address offset: 0x34 */
  __IO uint32_t INJSEQ;   /*!< ADC injected sequence register,              Address offset: 0x38 */
  __IO uint32_t INJDATA1; /*!< ADC injected data register 1,                Address offset: 0x3C */
  __IO uint32_t INJDATA2; /*!< ADC injected data register 2,                Address offset: 0x40 */
  __IO uint32_t INJDATA3; /*!< ADC injected data register 3,                Address offset: 0x44 */
  __IO uint32_t INJDATA4; /*!< ADC injected data register 4,                Address offset: 0x48 */
  __IO uint32_t REGDATA;  /*!< ADC regular data register,                   Address offset: 0x4C */
} ADC_TypeDef;

typedef struct
{
  __IO uint32_t CSTS;   /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
  __IO uint32_t CCTRL;  /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
  __IO uint32_t CDATA;  /*!< ADC common regular data register for dual
                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
} ADC_Common_TypeDef;


/** 
  * @brief Controller Area Network TxMailBox 
  */

typedef struct
{
  __IO uint32_t TXMID;  /*!< CAN TX mailbox identifier register */
  __IO uint32_t TXDLEN; /*!< CAN mailbox data length control and time stamp register */
  __IO uint32_t TXMDL;  /*!< CAN mailbox data low register */
  __IO uint32_t TXMDH;  /*!< CAN mailbox data high register */
} CAN_TxMailBox_TypeDef;

/** 
  * @brief Controller Area Network FIFOMailBox 
  */
  
typedef struct
{
  __IO uint32_t RXMID;  /*!< CAN receive FIFO mailbox identifier register */
  __IO uint32_t RXDLEN; /*!< CAN receive FIFO mailbox data length control and time stamp register */
  __IO uint32_t RXMDL;  /*!< CAN receive FIFO mailbox data low register */
  __IO uint32_t RXMDH;  /*!< CAN receive FIFO mailbox data high register */
} CAN_FIFOMailBox_TypeDef;

/** 
  * @brief Controller Area Network FilterRegister 
  */
  
typedef struct
{
  __IO uint32_t FBANK1; /*!< CAN Filter bank register 1 */
  __IO uint32_t FBANK2; /*!< CAN Filter bank register 1 */
} CAN_FilterRegister_TypeDef;

/** 
  * @brief Controller Area Network 
  */
  
typedef struct
{
  __IO uint32_t              MCTRL;               /*!< CAN master control register,         Address offset: 0x00          */
  __IO uint32_t              MSTS;                /*!< CAN master status register,          Address offset: 0x04          */
  __IO uint32_t              TXSTS;               /*!< CAN transmit status register,        Address offset: 0x08          */
  __IO uint32_t              RXF0;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
  __IO uint32_t              RXF1;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
  __IO uint32_t              INTEN;               /*!< CAN interrupt enable register,       Address offset: 0x14          */
  __IO uint32_t              ERRSTS;              /*!< CAN error status register,           Address offset: 0x18          */
  __IO uint32_t              BITTIM;              /*!< CAN bit timing register,             Address offset: 0x1C          */
  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
  __IO uint32_t              FCTRL;               /*!< CAN filter master register,          Address offset: 0x200         */
  __IO uint32_t              FMCFG;               /*!< CAN filter mode register,            Address offset: 0x204         */
  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
  __IO uint32_t              FSCFG;               /*!< CAN filter scale register,           Address offset: 0x20C         */
  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
  __IO uint32_t              FFASS;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
  __IO uint32_t              FACT;                /*!< CAN filter activation register,      Address offset: 0x21C         */
  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
} CAN_TypeDef;

/** 
  * @brief CRC calculation unit 
  */

typedef struct
{
  __IO uint32_t DATA;       /*!< CRC Data register,             Address offset: 0x00 */
  __IO uint8_t  INDATA;     /*!< CRC Independent data register, Address offset: 0x04 */
  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
  __IO uint32_t CTRL;       /*!< CRC Control register,          Address offset: 0x08 */
} CRC_TypeDef;

/** 
  * @brief Digital to Analog Converter
  */

typedef struct
{
  __IO uint32_t CTRL;       /*!< DAC control register,                                    Address offset: 0x00 */
  __IO uint32_t SWTRG;      /*!< DAC software trigger register,                           Address offset: 0x04 */
  __IO uint32_t DH12R1;     /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
  __IO uint32_t DH12L1;     /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
  __IO uint32_t DH8R1;      /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
  __IO uint32_t DH12R2;     /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
  __IO uint32_t DH12L2;     /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
  __IO uint32_t DH8R2;      /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
  __IO uint32_t DH12RDUAL;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
  __IO uint32_t DH12LDUAL;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
  __IO uint32_t DH8RDUAL;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
  __IO uint32_t DATAOCH1;   /*!< DAC channel1 data output register,                       Address offset: 0x2C */
  __IO uint32_t DATAOCH2;   /*!< DAC channel2 data output register,                       Address offset: 0x30 */
  __IO uint32_t STS;        /*!< DAC status register,                                     Address offset: 0x34 */
} DAC_TypeDef;

/** 
  * @brief Debug MCU
  */

typedef struct
{
  __IO uint32_t IDCODE;   /*!< MCU device ID code,               Address offset: 0x00 */
  __IO uint32_t CFG;      /*!< Debug MCU configuration register, Address offset: 0x04 */
  __IO uint32_t APB1F;    /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
  __IO uint32_t APB2F;    /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
} DBGMCU_TypeDef;

/** 
  * @brief DCI
  */

typedef struct
{
  __IO uint32_t CTRL;       /*!< DCI control register 1,                       Address offset: 0x00 */
  __IO uint32_t STS;        /*!< DCI status register,                          Address offset: 0x04 */
  __IO uint32_t RINTSTS;    /*!< DCI raw interrupt status register,            Address offset: 0x08 */
  __IO uint32_t INTEN;      /*!< DCI interrupt enable register,                Address offset: 0x0C */
  __IO uint32_t MINTSTS;    /*!< DCI masked interrupt status register,         Address offset: 0x10 */
  __IO uint32_t INTCLR;     /*!< DCI interrupt clear register,                 Address offset: 0x14 */
  __IO uint32_t ESYNCC;     /*!< DCI embedded synchronization code register,   Address offset: 0x18 */
  __IO uint32_t ESYNCUM;    /*!< DCI embedded synchronization unmask register, Address offset: 0x1C */
  __IO uint32_t CROPWSTAT;  /*!< DCI crop window start,                        Address offset: 0x20 */
  __IO uint32_t CROPWSIZE;  /*!< DCI crop window size,                         Address offset: 0x24 */
  __IO uint32_t DATA;       /*!< DCI data register,                            Address offset: 0x28 */
} DCI_TypeDef;

/** 
  * @brief DMA Controller
  */

typedef struct
{
  __IO uint32_t SCFG;   /*!< DMA stream x configuration register      */
  __IO uint32_t NDATA;  /*!< DMA stream x number of data register     */
  __IO uint32_t PADDR;  /*!< DMA stream x peripheral address register */
  __IO uint32_t M0ADDR; /*!< DMA stream x memory 0 address register   */
  __IO uint32_t M1ADDR; /*!< DMA stream x memory 1 address register   */
  __IO uint32_t FCTRL;  /*!< DMA stream x FIFO control register       */
} DMA_Stream_TypeDef;

typedef struct
{
  __IO uint32_t LINTSTS;  /*!< DMA low interrupt status register,      Address offset: 0x00 */
  __IO uint32_t HINTSTS;  /*!< DMA high interrupt status register,     Address offset: 0x04 */
  __IO uint32_t LIFCLR;   /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
  __IO uint32_t HIFCLR;   /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
} DMA_TypeDef;

/** 
  * @brief Ethernet MAC
  */

typedef struct
{
  __IO uint32_t MACCFG;
  __IO uint32_t MACFRAF;
  __IO uint32_t MACHTH;
  __IO uint32_t MACHTL;
  __IO uint32_t MACADDR;
  __IO uint32_t MACDATA;
  __IO uint32_t MACFCTRL;
  __IO uint32_t MACVLANT;              /*    8 */
  uint32_t      RESERVED0[2];
  __IO uint32_t MACREMWKUPFFL;         /*   11 */
  __IO uint32_t MACPMTCTRLSTS;
  uint32_t      RESERVED1;
  __IO uint32_t MACDBG;
  __IO uint32_t MACISTS;               /*   15 */
  __IO uint32_t MACIMASK;
  __IO uint32_t MACADDR0H;
  __IO uint32_t MACADDR0L;
  __IO uint32_t MACADDR1H;
  __IO uint32_t MACADDR1L;
  __IO uint32_t MACADDR2H;
  __IO uint32_t MACADDR2L;
  __IO uint32_t MACADDR3H;
  __IO uint32_t MACADDR3L;            /*   24 */
  uint32_t      RESERVED2[40];
  __IO uint32_t MMCCTRL;              /*   65 */
  __IO uint32_t MMCRXINT;
  __IO uint32_t MMCTXINT;
  __IO uint32_t MMCRXINTMASK;
  __IO uint32_t MMCTXINTMASK;         /*   69 */
  uint32_t      RESERVED3[14];
  __IO uint32_t MMCTXGFSCCNT;         /*   84 */
  __IO uint32_t MMCTXGFMCCNT;
  uint32_t      RESERVED4[5];
  __IO uint32_t MMCTXGFCNT;
  uint32_t      RESERVED5[10];
  __IO uint32_t MMCRXFCECNT;
  __IO uint32_t MMCRXFAECNT;
  uint32_t      RESERVED6[10];
  __IO uint32_t MMCRXGUNCNT;
  uint32_t      RESERVED7[334];
  __IO uint32_t PTPTSCTRL;
  __IO uint32_t PTPSUBSECI;
  __IO uint32_t PTPTSH;
  __IO uint32_t PTPTSL;
  __IO uint32_t PTPTSHUD;
  __IO uint32_t PTPTSLUD;
  __IO uint32_t PTPTSA;
  __IO uint32_t PTPTTSH;
  __IO uint32_t PTPTTSL;
  __IO uint32_t RESERVED8;
  __IO uint32_t PTPTSSTS;
  uint32_t      RESERVED9[565];
  __IO uint32_t DMABMOD;
  __IO uint32_t DMATXPD;
  __IO uint32_t DMARXPD;
  __IO uint32_t DMARXDLADDR;
  __IO uint32_t DMATXDLADDR;
  __IO uint32_t DMASTS;
  __IO uint32_t DMAOPMOD;
  __IO uint32_t DMAINTEN;
  __IO uint32_t DMAMFABOCNT;
  __IO uint32_t DMARXFLGWDT;
  uint32_t      RESERVED10[8];
  __IO uint32_t DMAHTXD;
  __IO uint32_t DMAHRXD;
  __IO uint32_t DMAHTXBADDR;
  __IO uint32_t DMAHRXBADDR;
} ETH_TypeDef;

/** 
  * @brief External Interrupt/Event Controller
  */

typedef struct
{
  __IO uint32_t IMASK;    /*!< EINT Interrupt mask register,            Address offset: 0x00 */
  __IO uint32_t EMASK;    /*!< EINT Event mask register,                Address offset: 0x04 */
  __IO uint32_t RTEN;     /*!< EINT Rising trigger selection register,  Address offset: 0x08 */
  __IO uint32_t FTEN;     /*!< EINT Falling trigger selection register, Address offset: 0x0C */
  __IO uint32_t SWINTE;   /*!< EINT Software interrupt event register,  Address offset: 0x10 */
  __IO uint32_t IPEND;    /*!< EINT Pending register,                   Address offset: 0x14 */
} EINT_TypeDef;

/** 
  * @brief FLASH Registers
  */

typedef struct
{
  __IO uint32_t ACCTRL;   /*!< FLASH access control register,   Address offset: 0x00 */
  __IO uint32_t KEY;      /*!< FLASH key register,              Address offset: 0x04 */
  __IO uint32_t OPTKEY;   /*!< FLASH option key register,       Address offset: 0x08 */
  __IO uint32_t STS;      /*!< FLASH status register,           Address offset: 0x0C */
  __IO uint32_t CTRL;     /*!< FLASH control register,          Address offset: 0x10 */
  __IO uint32_t OPTCTRL;  /*!< FLASH option control register ,  Address offset: 0x14 */
  __IO uint32_t OPTCTRL1; /*!< FLASH option control register 1, Address offset: 0x18 */
} FLASH_TypeDef;

/**
  * @brief Dynamic memory controler (DMC)
  */
typedef struct 
{
  __IO uint32_t CFG;            /*!< Configuraion register,    Address offset: 0x00 */
  __IO uint32_t TIM0;           /*!< Timing register 0,        Address offset: 0x04 */
  __IO uint32_t TIM1;           /*!< Timing register 1,        Address offset: 0x08 */
  __IO uint32_t CTRL1;          /*!< Control register 1,       Address offset: 0x0C */
  __IO uint32_t REF;            /*!< refresh register,         Address offset: 0x10 */
  uint32_t      RESERVED[251];
  __IO uint32_t SW;             /*!< switch register,          Address offset: 0x400 */
  __IO uint32_t CTRL2;          /*!< Control register 2,       Address offset: 0x404 */
} DMC_TypeDef;

/** 
  * @brief Flexible Static Memory Controller
  */

typedef struct
{
  __IO uint32_t CSTR[8];    /*!< NOR/PSRAM chip-select control register(CSCTRL) and chip-select timing register(CSTIM), Address offset: 0x00-1C */   
} SMC_Bank1_TypeDef;

/** 
  * @brief Flexible Static Memory Controller Bank1E
  */

typedef struct
{
  __IO uint32_t WRTTIM[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
} SMC_Bank1E_TypeDef;

/** 
  * @brief Flexible Static Memory Controller Bank2
  */
  
typedef struct
{
  __IO uint32_t CTRL2;        /*!< NAND Flash control register 2,                       Address offset: 0x60 */
  __IO uint32_t STSINT2;      /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
  __IO uint32_t CMSTIM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
  __IO uint32_t AMSTIM2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
  uint32_t      RESERVED0;    /*!< Reserved, 0x70                                                            */
  __IO uint32_t ECCRS2;       /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
  uint32_t      RESERVED1;    /*!< Reserved, 0x78                                                            */
  uint32_t      RESERVED2;    /*!< Reserved, 0x7C                                                            */
  __IO uint32_t CTRL3;        /*!< NAND Flash control register 3,                       Address offset: 0x80 */
  __IO uint32_t STSINT3;      /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
  __IO uint32_t CMSTIM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
  __IO uint32_t AMSTIM3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
  uint32_t      RESERVED3;    /*!< Reserved, 0x90                                                            */
  __IO uint32_t ECCRS3;       /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
} SMC_Bank2_3_TypeDef;

/** 
  * @brief Flexible Static Memory Controller Bank4
  */

typedef struct
{
  __IO uint32_t CTRL4;        /*!< PC Card  control register 4,                       Address offset: 0xA0 */
  __IO uint32_t STSINT4;      /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
  __IO uint32_t CMSTIM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
  __IO uint32_t AMSTIM4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
  __IO uint32_t IOSTIM4;      /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
} SMC_Bank4_TypeDef; 

/** 
  * @brief General Purpose I/O
  */

typedef struct
{
  __IO uint32_t MODE;     /*!< GPIO port mode register,               Address offset: 0x00      */
  __IO uint32_t OMODE;    /*!< GPIO port output type register,        Address offset: 0x04      */
  __IO uint32_t OSSEL;    /*!< GPIO port output speed register,       Address offset: 0x08      */
  __IO uint32_t PUPD;     /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
  __IO uint32_t IDATA;    /*!< GPIO port input data register,         Address offset: 0x10      */
  __IO uint32_t ODATA;    /*!< GPIO port output data register,        Address offset: 0x14      */
  __IO uint32_t BSC;      /*!< GPIO port bit set/reset register,      Address offset: 0x18      */
  __IO uint32_t LOCK;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
  __IO uint32_t ALF[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */
} GPIO_TypeDef;

/** 
  * @brief System configuration controller
  */

typedef struct
{
  __IO uint32_t MMSEL;        /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
  __IO uint32_t PMCFG;        /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
  __IO uint32_t EINTCFG[4];   /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */
  __IO uint32_t CCCTRL;       /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
} SYSCFG_TypeDef;

/** 
  * @brief Inter-integrated Circuit Interface
  */

typedef struct
{
  __IO uint32_t CTRL1;      /*!< I2C Control register 1,     Address offset: 0x00 */
  __IO uint32_t CTRL2;      /*!< I2C Control register 2,     Address offset: 0x04 */
  __IO uint32_t SADDR1;     /*!< I2C Own address register 1, Address offset: 0x08 */
  __IO uint32_t SADDR2;     /*!< I2C Own address register 2, Address offset: 0x0C */
  __IO uint32_t DATA;       /*!< I2C Data register,          Address offset: 0x10 */
  __IO uint32_t STS1;       /*!< I2C Status register 1,      Address offset: 0x14 */
  __IO uint32_t STS2;       /*!< I2C Status register 2,      Address offset: 0x18 */
  __IO uint32_t CLKCTRL;    /*!< I2C Clock control register, Address offset: 0x1C */
  __IO uint32_t RISETMAX;   /*!< I2C RISETMAX register,      Address offset: 0x20 */
} I2C_TypeDef;

/** 
  * @brief Independent WATCHDOG
  */

typedef struct
{
  __IO uint32_t KEY;    /*!< IWDT Key register,       Address offset: 0x00 */
  __IO uint32_t PSC;    /*!< IWDT Prescaler register, Address offset: 0x04 */
  __IO uint32_t CNTRLD; /*!< IWDT Reload register,    Address offset: 0x08 */
  __IO uint32_t STS;    /*!< IWDT Status register,    Address offset: 0x0C */
} IWDT_TypeDef;


/** 
  * @brief Power Control
  */

typedef struct
{
  __IO uint32_t CTRL; /*!< PMU power control register,        Address offset: 0x00 */
  __IO uint32_t CSTS; /*!< PMU power control/status register, Address offset: 0x04 */
} PMU_TypeDef;

/** 
  * @brief Reset and Clock Control
  */

typedef struct
{
  __IO uint32_t CTRL;           /*!< RCM clock control register,                                  Address offset: 0x00 */
  __IO uint32_t PLL1CFG;        /*!< RCM PLL configuration register,                              Address offset: 0x04 */
  __IO uint32_t CFG;            /*!< RCM clock configuration register,                            Address offset: 0x08 */
  __IO uint32_t INT;            /*!< RCM clock interrupt register,                                Address offset: 0x0C */
  __IO uint32_t AHB1RST;        /*!< RCM AHB1 peripheral reset register,                          Address offset: 0x10 */
  __IO uint32_t AHB2RST;        /*!< RCM AHB2 peripheral reset register,                          Address offset: 0x14 */
  __IO uint32_t AHB3RST;        /*!< RCM AHB3 peripheral reset register,                          Address offset: 0x18 */
  uint32_t      RESERVED0;      /*!< Reserved, 0x1C                                                                    */
  __IO uint32_t APB1RST;        /*!< RCM APB1 peripheral reset register,                          Address offset: 0x20 */
  __IO uint32_t APB2RST;        /*!< RCM APB2 peripheral reset register,                          Address offset: 0x24 */
  uint32_t      RESERVED1[2];   /*!< Reserved, 0x28-0x2C                                                               */
  __IO uint32_t AHB1CLKEN;      /*!< RCM AHB1 peripheral clock register,                          Address offset: 0x30 */
  __IO uint32_t AHB2CLKEN;      /*!< RCM AHB2 peripheral clock register,                          Address offset: 0x34 */
  __IO uint32_t AHB3CLKEN;      /*!< RCM AHB3 peripheral clock register,                          Address offset: 0x38 */
  uint32_t      RESERVED2;      /*!< Reserved, 0x3C                                                                    */
  __IO uint32_t APB1CLKEN;      /*!< RCM APB1 peripheral clock enable register,                   Address offset: 0x40 */
  __IO uint32_t APB2CLKEN;      /*!< RCM APB2 peripheral clock enable register,                   Address offset: 0x44 */
  uint32_t      RESERVED3[2];   /*!< Reserved, 0x48-0x4C                                                               */
  __IO uint32_t LPAHB1CLKEN;    /*!< RCM AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
  __IO uint32_t LPAHB2CLKEN;    /*!< RCM AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
  __IO uint32_t LPAHB3CLKEN;    /*!< RCM AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
  uint32_t      RESERVED4;      /*!< Reserved, 0x5C                                                                    */
  __IO uint32_t LPAPB1CLKEN;    /*!< RCM APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
  __IO uint32_t LPAPB2CLKEN;    /*!< RCM APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
  uint32_t      RESERVED5[2];   /*!< Reserved, 0x68-0x6C                                                               */
  __IO uint32_t BDCTRL;         /*!< RCM Backup domain control register,                          Address offset: 0x70 */
  __IO uint32_t CSTS;           /*!< RCM clock control & status register,                         Address offset: 0x74 */
  uint32_t      RESERVED6[2];   /*!< Reserved, 0x78-0x7C                                                               */
  __IO uint32_t SSCCFG;         /*!< RCM spread spectrum clock generation register,               Address offset: 0x80 */
  __IO uint32_t PLL2CFG;        /*!< RCM PLLI2S configuration register,                           Address offset: 0x84 */
} RCM_TypeDef;

/** 
  * @brief Real-Time Clock
  */

typedef struct
{
  __IO uint32_t TIME;     /*!< RTC time register,                                        Address offset: 0x00 */
  __IO uint32_t DATE;     /*!< RTC date register,                                        Address offset: 0x04 */
  __IO uint32_t CTRL;     /*!< RTC control register,                                     Address offset: 0x08 */
  __IO uint32_t STS;      /*!< RTC initialization and status register,                   Address offset: 0x0C */
  __IO uint32_t PSC;      /*!< RTC prescaler register,                                   Address offset: 0x10 */
  __IO uint32_t AUTORLD;  /*!< RTC wakeup timer register,                                Address offset: 0x14 */
  __IO uint32_t DCAL;     /*!< RTC calibration register,                                 Address offset: 0x18 */
  __IO uint32_t ALRMA;    /*!< RTC alarm A register,                                     Address offset: 0x1C */
  __IO uint32_t ALRMB;    /*!< RTC alarm B register,                                     Address offset: 0x20 */
  __IO uint32_t WRPROT;   /*!< RTC write protection register,                            Address offset: 0x24 */
  __IO uint32_t SUBSEC;   /*!< RTC sub second register,                                  Address offset: 0x28 */
  __IO uint32_t SHIFT;    /*!< RTC shift control register,                               Address offset: 0x2C */
  __IO uint32_t TSTIME;   /*!< RTC time stamp time register,                             Address offset: 0x30 */
  __IO uint32_t TSDATE;   /*!< RTC time stamp date register,                             Address offset: 0x34 */
  __IO uint32_t TSSUBSEC; /*!< RTC time-stamp sub second register,                       Address offset: 0x38 */
  __IO uint32_t CAL;      /*!< RTC calibration register,                                 Address offset: 0x3C */
  __IO uint32_t TACFG;    /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
  __IO uint32_t ALRMASS;  /*!< RTC alarm A sub second register,                          Address offset: 0x44 */
  __IO uint32_t ALRMBSS;  /*!< RTC alarm B sub second register,                          Address offset: 0x48 */
  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
  __IO uint32_t BAKP0;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
  __IO uint32_t BAKP1;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
  __IO uint32_t BAKP2;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
  __IO uint32_t BAKP3;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
  __IO uint32_t BAKP4;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
  __IO uint32_t BAKP5;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
  __IO uint32_t BAKP6;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
  __IO uint32_t BAKP7;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
  __IO uint32_t BAKP8;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
  __IO uint32_t BAKP9;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
  __IO uint32_t BAKP10;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
  __IO uint32_t BAKP11;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
  __IO uint32_t BAKP12;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
  __IO uint32_t BAKP13;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
  __IO uint32_t BAKP14;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
  __IO uint32_t BAKP15;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
  __IO uint32_t BAKP16;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
  __IO uint32_t BAKP17;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
  __IO uint32_t BAKP18;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
  __IO uint32_t BAKP19;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
} RTC_TypeDef;

/** 
  * @brief SD host Interface
  */

typedef struct
{
  __IO uint32_t PWRCTRL;              /*!< SDIO power control register,    Address offset: 0x00 */
  __IO uint32_t CLKCTRL;              /*!< SDI clock control register,     Address offset: 0x04 */
  __IO uint32_t ARG;                  /*!< SDIO argument register,         Address offset: 0x08 */
  __IO uint32_t CMD;                  /*!< SDIO command register,          Address offset: 0x0C */
  __IO const uint32_t  CMDRES;        /*!< SDIO command response register, Address offset: 0x10 */
  __IO const uint32_t  RES1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
  __IO const uint32_t  RES2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
  __IO const uint32_t  RES3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
  __IO const uint32_t  RES4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
  __IO uint32_t DATATIME;             /*!< SDIO data timer register,       Address offset: 0x24 */
  __IO uint32_t DATALEN;              /*!< SDIO data length register,      Address offset: 0x28 */
  __IO uint32_t DCTRL;                /*!< SDIO data control register,     Address offset: 0x2C */
  __IO const uint32_t  DCNT;          /*!< SDIO data counter register,     Address offset: 0x30 */
  __IO const uint32_t  STS;           /*!< SDIO status register,           Address offset: 0x34 */
  __IO uint32_t ICF;                  /*!< SDIO interrupt clear register,  Address offset: 0x38 */
  __IO uint32_t MASK;                 /*!< SDIO mask register,             Address offset: 0x3C */
  uint32_t      RESERVED0[2];         /*!< Reserved, 0x40-0x44                                  */
  __IO const uint32_t  FIFOCNT;       /*!< SDIO FIFO counter register,     Address offset: 0x48 */
  uint32_t      RESERVED1[13];        /*!< Reserved, 0x4C-0x7C                                  */
  __IO uint32_t FIFODATA;             /*!< SDIO data FIFO register,        Address offset: 0x80 */
} SDIO_TypeDef;

/** 
  * @brief Serial Peripheral Interface
  */

typedef struct
{
  __IO uint32_t CTRL1;      /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
  __IO uint32_t CTRL2;      /*!< SPI control register 2,                             Address offset: 0x04 */
  __IO uint32_t STS;        /*!< SPI status register,                                Address offset: 0x08 */
  __IO uint32_t DATA;       /*!< SPI data register,                                  Address offset: 0x0C */
  __IO uint32_t CRCPOLY;    /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
  __IO uint32_t RXCRC;      /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
  __IO uint32_t TXCRC;      /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
  __IO uint32_t I2SCFG;     /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
  __IO uint32_t I2SPSC;     /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
} SPI_TypeDef;


/** 
  * @brief TMR
  */

typedef struct
{
  __IO uint32_t CTRL1;        /*!< TMR control register 1,              Address offset: 0x00 */
  __IO uint32_t CTRL2;        /*!< TMR control register 2,              Address offset: 0x04 */
  __IO uint32_t SMCTRL;       /*!< TMR slave mode control register,     Address offset: 0x08 */
  __IO uint32_t DIEN;         /*!< TMR DMA/interrupt enable register,   Address offset: 0x0C */
  __IO uint32_t STS;          /*!< TMR status register,                 Address offset: 0x10 */
  __IO uint32_t CEG;          /*!< TMR event generation register,       Address offset: 0x14 */
  __IO uint32_t CCM1;         /*!< TMR capture/compare mode register 1, Address offset: 0x18 */
  __IO uint32_t CCM2;         /*!< TMR capture/compare mode register 2, Address offset: 0x1C */
  __IO uint32_t CCEN;         /*!< TMR capture/compare enable register, Address offset: 0x20 */
  __IO uint32_t CNT;          /*!< TMR counter register,                Address offset: 0x24 */
  __IO uint32_t PSC;          /*!< TMR prescaler,                       Address offset: 0x28 */
  __IO uint32_t AUTORLD;      /*!< TMR auto-reload register,            Address offset: 0x2C */
  __IO uint32_t REPCNT;       /*!< TMR repetition counter register,     Address offset: 0x30 */
  __IO uint32_t CC1;          /*!< TMR capture/compare register 1,      Address offset: 0x34 */
  __IO uint32_t CC2;          /*!< TMR capture/compare register 2,      Address offset: 0x38 */
  __IO uint32_t CC3;          /*!< TMR capture/compare register 3,      Address offset: 0x3C */
  __IO uint32_t CC4;          /*!< TMR capture/compare register 4,      Address offset: 0x40 */
  __IO uint32_t BDT;          /*!< TMR break and dead-time register,    Address offset: 0x44 */
  __IO uint32_t DCTRL;        /*!< TMR DMA control register,            Address offset: 0x48 */
  __IO uint32_t DMAR;         /*!< TMR DMA address for full transfer,   Address offset: 0x4C */
  __IO uint32_t OR;           /*!< TMR option register,                 Address offset: 0x50 */
} TMR_TypeDef;

/** 
  * @brief Universal Synchronous Asynchronous Receiver Transmitter
  */
 
typedef struct
{
  __IO uint32_t STS;        /*!< USART Status register,                   Address offset: 0x00 */
  __IO uint32_t DATA;       /*!< USART Data register,                     Address offset: 0x04 */
  __IO uint32_t BR;         /*!< USART Baud rate register,                Address offset: 0x08 */
  __IO uint32_t CTRL1;      /*!< USART Control register 1,                Address offset: 0x0C */
  __IO uint32_t CTRL2;      /*!< USART Control register 2,                Address offset: 0x10 */
  __IO uint32_t CTRL3;      /*!< USART Control register 3,                Address offset: 0x14 */
  __IO uint32_t GTPSC;      /*!< USART Guard time and prescaler register, Address offset: 0x18 */
} USART_TypeDef;

/** 
  * @brief Window WATCHDOG
  */

typedef struct
{
  __IO uint32_t CTRL; /*!< WWDT Control register,       Address offset: 0x00 */
  __IO uint32_t CFR;  /*!< WWDT Configuration register, Address offset: 0x04 */
  __IO uint32_t STS;  /*!< WWDT Status register,        Address offset: 0x08 */
} WWDT_TypeDef;

/** 
  * @brief RNG
  */
  
typedef struct 
{
  __IO uint32_t CTRL; /*!< RNG control register, Address offset: 0x00 */
  __IO uint32_t STS;  /*!< RNG status register,  Address offset: 0x04 */
  __IO uint32_t DATA; /*!< RNG data register,    Address offset: 0x08 */
} RNG_TypeDef;

/** 
  * @brief USB_OTG_Core_Registers
  */
typedef struct
{
  __IO uint32_t GCTRLSTS;             /*!< USB_OTG Control and Status Register          000h */
  __IO uint32_t GINT;                 /*!< USB_OTG Interrupt Register                   004h */
  __IO uint32_t GAHBCFG;              /*!< Core AHB Configuration Register              008h */
  __IO uint32_t GUSBCFG;              /*!< Core USB Configuration Register              00Ch */
  __IO uint32_t GRSTCTRL;             /*!< Core Reset Register                          010h */
  __IO uint32_t GCINT;                /*!< Core Interrupt Register                      014h */
  __IO uint32_t GINTMASK;             /*!< Core Interrupt Mask Register                 018h */
  __IO uint32_t GRXSTS;               /*!< Receive Sts Q Read Register                  01Ch */
  __IO uint32_t GRXSTSP;              /*!< Receive Sts Q Read & POP Register            020h */
  __IO uint32_t GRXFIFO;              /*!< Receive FIFO Size Register                   024h */
  __IO uint32_t GTXFCFG;              /*!< EP0 / Non Periodic Tx FIFO Size Register     028h */
  __IO uint32_t GNPTXFQSTS;           /*!< Non Periodic Tx FIFO/Queue Sts reg           02Ch */
  uint32_t Reserved30[2];             /*!< Reserved                                     030h */
  __IO uint32_t GGCCFG;               /*!< General Purpose IO Register                  038h */
  __IO uint32_t GCID;                 /*!< User ID Register                             03Ch */
  uint32_t  Reserved40[48];           /*!< Reserved                                0x40-0xFF */
  __IO uint32_t GHPTXFSIZE;           /*!< Host Periodic Tx FIFO Size Reg               100h */
  __IO uint32_t DTXFIFO[0x0F];        /*!< dev Periodic Transmit FIFO                        */
} USB_OTG_GlobalTypeDef;

/** 
  * @brief USB_OTG_device_Registers
  */
typedef struct 
{
  __IO uint32_t DCFG;           /*!< dev Configuration Register   800h */
  __IO uint32_t DCTRL;          /*!< dev Control Register         804h */
  __IO uint32_t DSTS;           /*!< dev Status Register (RO)     808h */
  uint32_t Reserved0C;          /*!< Reserved                     80Ch */
  __IO uint32_t DINIMASK;       /*!< dev IN Endpoint Mask         810h */
  __IO uint32_t DOUTIMASK;      /*!< dev OUT Endpoint Mask        814h */
  __IO uint32_t DAEPINT;        /*!< dev All Endpoints Itr Reg    818h */
  __IO uint32_t DAEPIMASK;      /*!< dev All Endpoints Itr Mask   81Ch */
  uint32_t  Reserved20;         /*!< Reserved                     820h */
  uint32_t Reserved9;           /*!< Reserved                     824h */
  __IO uint32_t DVBUSDTIM;      /*!< dev VBUS discharge Register  828h */
  __IO uint32_t DVBUSPTIM;      /*!< dev VBUS Pulse Register      82Ch */
  __IO uint32_t DTHCTRL;        /*!< dev threshold                830h */
  __IO uint32_t DIEIMASK;       /*!< dev empty msk                834h */
  __IO uint32_t DEPINT;         /*!< dedicated EP interrupt       838h */
  __IO uint32_t DEPIMASK;       /*!< dedicated EP msk             83Ch */
  uint32_t Reserved40;          /*!< dedicated EP mask            840h */
  __IO uint32_t DIN1IMASK;      /*!< dedicated EP mask            844h */
  uint32_t  Reserved44[15];     /*!< Reserved                 844-87Ch */
  __IO uint32_t DOUT1MASK;      /*!< dedicated EP msk             884h */
} USB_OTG_DeviceTypeDef;

/** 
  * @brief USB_OTG_IN_Endpoint-Specific_Register
  */
typedef struct 
{
  __IO uint32_t DIEPCTRL;         /*!< dev IN Endpoint Control Reg    900h + (ep_num * 20h) + 00h */
  uint32_t Reserved04;            /*!< Reserved                       900h + (ep_num * 20h) + 04h */
  __IO uint32_t DIEPINT;          /*!< dev IN Endpoint Itr Reg        900h + (ep_num * 20h) + 08h */
  uint32_t Reserved0C;            /*!< Reserved                       900h + (ep_num * 20h) + 0Ch */
  __IO uint32_t DIEPTRS;          /*!< IN Endpoint Txfer Size         900h + (ep_num * 20h) + 10h */
  __IO uint32_t DIEPDMA;          /*!< IN Endpoint DMA Address Reg    900h + (ep_num * 20h) + 14h */
  __IO uint32_t DITXFSTS;         /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
  uint32_t Reserved18;            /*!< Reserved  900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
} USB_OTG_INEndpointTypeDef;

/** 
  * @brief USB_OTG_OUT_Endpoint-Specific_Registers
  */
typedef struct 
{
  __IO uint32_t DOEPCTRL;       /*!< dev OUT Endpoint Control Reg           B00h + (ep_num * 20h) + 00h */
  uint32_t Reserved04;          /*!< Reserved                               B00h + (ep_num * 20h) + 04h */
  __IO uint32_t DOEPINT;        /*!< dev OUT Endpoint Itr Reg               B00h + (ep_num * 20h) + 08h */
  uint32_t Reserved0C;          /*!< Reserved                               B00h + (ep_num * 20h) + 0Ch */
  __IO uint32_t DOEPTRS;        /*!< dev OUT Endpoint Txfer Size            B00h + (ep_num * 20h) + 10h */
  __IO uint32_t DOEPDMA;        /*!< dev OUT Endpoint DMA Address           B00h + (ep_num * 20h) + 14h */
  uint32_t Reserved18[2];       /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
} USB_OTG_OUTEndpointTypeDef;

/** 
  * @brief USB_OTG_Host_Mode_Register_Structures
  */
typedef struct 
{
  __IO uint32_t HCFG;             /*!< Host Configuration Register          400h */
  __IO uint32_t HFIVL;            /*!< Host Frame Interval Register         404h */
  __IO uint32_t HFIFM;            /*!< Host Frame Nbr/Frame Remaining       408h */
  uint32_t Reserved40C;           /*!< Reserved                             40Ch */
  __IO uint32_t HPTXSTS;          /*!< Host Periodic Tx FIFO/ Queue Status  410h */
  __IO uint32_t HACHINT;          /*!< Host All Channels Interrupt Register 414h */
  __IO uint32_t HACHIMASK;        /*!< Host All Channels Interrupt Mask     418h */
} USB_OTG_HostTypeDef;

/** 
  * @brief USB_OTG_Host_Channel_Specific_Registers
  */
typedef struct
{
  __IO uint32_t HCH;              /*!< Host Channel Characteristics Register    500h */
  __IO uint32_t HCHSCTRL;         /*!< Host Channel Split Control Register      504h */
  __IO uint32_t HCHINT;           /*!< Host Channel Interrupt Register          508h */
  __IO uint32_t HCHIMASK;         /*!< Host Channel Interrupt Mask Register     50Ch */
  __IO uint32_t HCHTSIZE;         /*!< Host Channel Transfer Size Register      510h */
  __IO uint32_t HCHDMA;           /*!< Host Channel DMA Address Register        514h */
  uint32_t Reserved[2];           /*!< Reserved                                      */
} USB_OTG_HostChannelTypeDef;

/** 
  * @brief USB_OTG_HS2_Specific_Registers
  */
typedef struct
{
    __IO uint32_t USB_SWITCH;               /*!< USB Switch Register 200h */
    __IO uint32_t POWERON_CORE;             /*!< Power On Core Register 204h */
    __IO uint32_t USB_PLL_EN;               /*!< USB PLL Enable Register 208h */
    __IO uint32_t SHORT_5V_ENABLE;          /*!< VBUS Short 5V Enable 20Ch */
    __IO uint32_t OTG_SUSPENDM;             /*!< OTG VBUS Suspend 210h */
    __IO uint32_t TXBITSTUFFENABLE;         /*!< TX Bit Stuff Enable 214h */
    __IO uint32_t PLLICP_SEL_I2C;           /*!< PLL Charge Current Setting 218h */
    __IO uint32_t HSZR_CNTL_I2C;            /*!< The DP/DM to the Ground Impedance Setting 21Ch */
    __IO uint32_t SQVTH_CNTL_I2C;           /*!< The SQ Reference Voltage Setting 220h*/
    __IO uint32_t SW_RREF_I2C;              /*!< The DP/DM Output Swing Setting When HS Mode 224h */
    __IO uint32_t SW_BUF_I2C;               /*!< The TX Driver Setting 228h */
    __IO uint32_t TX2RX_T_CFG_I2C;          /*!< Debug Control Signal 22Ch */
    __IO uint32_t TEST_ANA_FAST_I2C;        /*!< Debug Control Signal 230h */
    __IO uint32_t CLK_MODE_I2C;             /*!< Debug control signal 234h */
    __IO uint32_t USB_DBNCE_FLTR_BYPASS;    /*!< Bypass debounce filters for avalid, bvalid, vbusvalid,
                                                 sessend, iddig signals when enabled 238h */
    __IO uint32_t USB_SS_SCALEDOWN_MODE;    /*!< Used only in simulation 23Ch */                                                 
} USB_OTG_HS2TypeDef;

/**
  * @}
  */

/** @addtogroup Peripheral_memory_map
  * @{
  */
#define FLASH_BASE            0x08000000UL /*!< FLASH(up to 1 MB) base address in the alias region                         */
#define CCMDATARAM_BASE       0x10000000UL /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */
#define SRAM1_BASE            0x20000000UL /*!< SRAM1(112 KB) base address in the alias region                             */
#define SRAM2_BASE            0x2001C000UL /*!< SRAM2(16 KB) base address in the alias region                              */
#define PERIPH_BASE           0x40000000UL /*!< Peripheral base address in the alias region                                */
#define BKPSRAM_BASE          0x40024000UL /*!< Backup SRAM(4 KB) base address in the alias region                         */
#define SMC_R_BASE            0xA0000000UL /*!< SMC registers base address                                                 */
#define SRAM1_BB_BASE         0x22000000UL /*!< SRAM1(112 KB) base address in the bit-band region                          */
#define SRAM2_BB_BASE         0x22380000UL /*!< SRAM2(16 KB) base address in the bit-band region                           */
#define PERIPH_BB_BASE        0x42000000UL /*!< Peripheral base address in the bit-band region                             */
#define BKPSRAM_BB_BASE       0x42480000UL /*!< Backup SRAM(4 KB) base address in the bit-band region                      */
#define FLASH_END             0x080FFFFFUL /*!< FLASH end address                                                          */
#define FLASH_OTP_BASE        0x1FFF7800UL /*!< Base address of : (up to 528 Bytes) embedded FLASH OTP Area                */
#define FLASH_OTP_END         0x1FFF7A0FUL /*!< End address of : (up to 528 Bytes) embedded FLASH OTP Area                 */
#define CCMDATARAM_END        0x1000FFFFUL /*!< CCM data RAM end address                                                   */

/* Legacy defines */
#define SRAM_BASE             SRAM1_BASE
#define SRAM_BB_BASE          SRAM1_BB_BASE

/*!< Peripheral memory map */
#define APB1PERIPH_BASE       PERIPH_BASE
#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000UL)
#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000UL)
#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000UL)

/*!< APB1 peripherals */
#define TMR2_BASE             (APB1PERIPH_BASE + 0x0000UL)
#define TMR3_BASE             (APB1PERIPH_BASE + 0x0400UL)
#define TMR4_BASE             (APB1PERIPH_BASE + 0x0800UL)
#define TMR5_BASE             (APB1PERIPH_BASE + 0x0C00UL)
#define TMR6_BASE             (APB1PERIPH_BASE + 0x1000UL)
#define TMR7_BASE             (APB1PERIPH_BASE + 0x1400UL)
#define TMR12_BASE            (APB1PERIPH_BASE + 0x1800UL)
#define TMR13_BASE            (APB1PERIPH_BASE + 0x1C00UL)
#define TMR14_BASE            (APB1PERIPH_BASE + 0x2000UL)
#define RTC_BASE              (APB1PERIPH_BASE + 0x2800UL)
#define WWDT_BASE             (APB1PERIPH_BASE + 0x2C00UL)
#define IWDT_BASE             (APB1PERIPH_BASE + 0x3000UL)
#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400UL)
#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800UL)
#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00UL)
#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000UL)
#define USART2_BASE           (APB1PERIPH_BASE + 0x4400UL)
#define USART3_BASE           (APB1PERIPH_BASE + 0x4800UL)
#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00UL)
#define UART5_BASE            (APB1PERIPH_BASE + 0x5000UL)
#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400UL)
#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800UL)
#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00UL)
#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400UL)
#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800UL)
#define PMU_BASE              (APB1PERIPH_BASE + 0x7000UL)
#define DAC_BASE              (APB1PERIPH_BASE + 0x7400UL)

/*!< APB2 peripherals */
#define TMR1_BASE             (APB2PERIPH_BASE + 0x0000UL)
#define TMR8_BASE             (APB2PERIPH_BASE + 0x0400UL)
#define USART1_BASE           (APB2PERIPH_BASE + 0x1000UL)
#define USART6_BASE           (APB2PERIPH_BASE + 0x1400UL)
#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000UL)
#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100UL)
#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200UL)
#define ADC123_COMMON_BASE    (APB2PERIPH_BASE + 0x2300UL)
/* Legacy define */
#define ADC_BASE               ADC123_COMMON_BASE
#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00UL)
#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000UL)
#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800UL)
#define EINT_BASE             (APB2PERIPH_BASE + 0x3C00UL)
#define TMR9_BASE             (APB2PERIPH_BASE + 0x4000UL)
#define TMR10_BASE            (APB2PERIPH_BASE + 0x4400UL)
#define TMR11_BASE            (APB2PERIPH_BASE + 0x4800UL)

/*!< AHB1 peripherals */
#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000UL)
#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400UL)
#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800UL)
#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00UL)
#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000UL)
#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400UL)
#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800UL)
#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00UL)
#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000UL)
#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000UL)
#define RCM_BASE              (AHB1PERIPH_BASE + 0x3800UL)
#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00UL)
#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000UL)
#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010UL)
#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028UL)
#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040UL)
#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058UL)
#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070UL)
#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088UL)
#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0UL)
#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8UL)
#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400UL)
#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010UL)
#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028UL)
#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040UL)
#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058UL)
#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070UL)
#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088UL)
#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0UL)
#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8UL)
#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000UL)
#define ETH_MAC_BASE          (ETH_BASE)
#define ETH_MMC_BASE          (ETH_BASE + 0x0100UL)
#define ETH_PTP_BASE          (ETH_BASE + 0x0700UL)
#define ETH_DMA_BASE          (ETH_BASE + 0x1000UL)

/*!< AHB2 peripherals */
#define DCI_BASE              (AHB2PERIPH_BASE + 0x50000UL)
#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800UL)

/*!< SMC Bankx registers base address */
#define SMC_Bank1_R_BASE     (SMC_R_BASE + 0x0000UL)
#define SMC_Bank1E_R_BASE    (SMC_R_BASE + 0x0104UL)
#define SMC_Bank2_3_R_BASE   (SMC_R_BASE + 0x0060UL)
#define SMC_Bank4_R_BASE     (SMC_R_BASE + 0x00A0UL)

/*!< DMC registers base address */
#define DMC_BASE             ((uint32_t)0xA0000000UL)

/*!< Debug MCU registers base address */
#define DBGMCU_BASE           0xE0042000UL
/*!< USB registers base address */
#define USB_OTG_HS2_PERIPH_BASE              0x40040200UL
#define USB_OTG_HS_PERIPH_BASE               0x40040000UL
#define USB_OTG_FS_PERIPH_BASE               0x50000000UL

#define USB_OTG_GLOBAL_BASE                  0x000UL
#define USB_OTG_DEVICE_BASE                  0x800UL
#define USB_OTG_IN_ENDPOINT_BASE             0x900UL
#define USB_OTG_OUT_ENDPOINT_BASE            0xB00UL
#define USB_OTG_EP_REG_SIZE                  0x20UL
#define USB_OTG_HOST_BASE                    0x400UL
#define USB_OTG_HOST_PORT_BASE               0x440UL
#define USB_OTG_HOST_CHANNEL_BASE            0x500UL
#define USB_OTG_HOST_CHANNEL_SIZE            0x20UL
#define USB_OTG_PCGCCTL_BASE                 0xE00UL
#define USB_OTG_FIFO_BASE                    0x1000UL
#define USB_OTG_FIFO_SIZE                    0x1000UL

#define UID_BASE                     0x1FFF7A10UL           /*!< Unique device ID register base address */
#define FLASHSIZE_BASE               0x1FFF7A22UL           /*!< FLASH Size register base address       */
#define PACKAGE_BASE                 0x1FFF7BF0UL           /*!< Package size register base address     */
/**
  * @}
  */

/** @addtogroup Peripheral_declaration
  * @{
  */  
#define TMR2                ((TMR_TypeDef *) TMR2_BASE)
#define TMR3                ((TMR_TypeDef *) TMR3_BASE)
#define TMR4                ((TMR_TypeDef *) TMR4_BASE)
#define TMR5                ((TMR_TypeDef *) TMR5_BASE)
#define TMR6                ((TMR_TypeDef *) TMR6_BASE)
#define TMR7                ((TMR_TypeDef *) TMR7_BASE)
#define TMR12               ((TMR_TypeDef *) TMR12_BASE)
#define TMR13               ((TMR_TypeDef *) TMR13_BASE)
#define TMR14               ((TMR_TypeDef *) TMR14_BASE)
#define RTC                 ((RTC_TypeDef *) RTC_BASE)
#define WWDT                ((WWDT_TypeDef *) WWDT_BASE)
#define IWDT                ((IWDT_TypeDef *) IWDT_BASE)
#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
#define USART2              ((USART_TypeDef *) USART2_BASE)
#define USART3              ((USART_TypeDef *) USART3_BASE)
#define UART4               ((USART_TypeDef *) UART4_BASE)
#define UART5               ((USART_TypeDef *) UART5_BASE)
#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
#define PMU                 ((PMU_TypeDef *) PMU_BASE)
#define DAC1                ((DAC_TypeDef *) DAC_BASE)
#define DAC                 ((DAC_TypeDef *) DAC_BASE) /* Kept for legacy purpose */
#define TMR1                ((TMR_TypeDef *) TMR1_BASE)
#define TMR8                ((TMR_TypeDef *) TMR8_BASE)
#define USART1              ((USART_TypeDef *) USART1_BASE)
#define USART6              ((USART_TypeDef *) USART6_BASE)
#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
#define ADC123_COMMON       ((ADC_Common_TypeDef *) ADC123_COMMON_BASE)
/* Legacy define */
#define ADC                  ADC123_COMMON
#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
#define EINT                ((EINT_TypeDef *) EINT_BASE)
#define TMR9                ((TMR_TypeDef *) TMR9_BASE)
#define TMR10               ((TMR_TypeDef *) TMR10_BASE)
#define TMR11               ((TMR_TypeDef *) TMR11_BASE)
#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
#define CRC                 ((CRC_TypeDef *) CRC_BASE)
#define RCM                 ((RCM_TypeDef *) RCM_BASE)
#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
#define DCI                 ((DCI_TypeDef *) DCI_BASE)
#define RNG                 ((RNG_TypeDef *) RNG_BASE)
#define SMC_Bank1           ((SMC_Bank1_TypeDef *) SMC_Bank1_R_BASE)
#define SMC_Bank1E          ((SMC_Bank1E_TypeDef *) SMC_Bank1E_R_BASE)
#define SMC_Bank2_3         ((SMC_Bank2_3_TypeDef *) SMC_Bank2_3_R_BASE)
#define SMC_Bank4           ((SMC_Bank4_TypeDef *) SMC_Bank4_R_BASE)
#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
#define USB_OTG_FS          ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
#define USB_OTG_HS          ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
#define USB_OTG_HS2         ((USB_OTG_HS2TypeDef *) USB_OTG_HS2_PERIPH_BASE)
#define DMC                 ((DMC_TypeDef *) DMC_BASE)

/**
  * @}
  */

/** @addtogroup Exported_constants
  * @{
  */

/** @addtogroup Hardware_Constant_Definition
  * @{
  */
#define LSI_STARTUP_TIME                40U /*!< LSI Maximum startup time in us */
/**
  * @}
  */

  /** @addtogroup Peripheral_Registers_Bits_Definition
  * @{
  */
    
/******************************************************************************/
/*                         Peripheral Registers_Bits_Definition               */
/******************************************************************************/

/******************************************************************************/
/*                                                                            */
/*                        Analog to Digital Converter                         */
/*                                                                            */
/******************************************************************************/
/*
 * @brief Specific device feature definitions (not present on all devices in the APM32F4 serie)
 */
#define ADC_MULTIMODE_SUPPORT                                                                                                      /*!<ADC Multimode feature available on specific devices */

/********************  Bit definition for ADC_STS register  ********************/
#define ADC_STS_AWDFLG_Pos                                          (0U)
#define ADC_STS_AWDFLG_Msk                                          (0x1UL << ADC_STS_AWDFLG_Pos)                                  /*!< 0x00000001 */
#define ADC_STS_AWDFLG                                              ADC_STS_AWDFLG_Msk                                             /*!<Analog watchdog flag */
#define ADC_STS_EOCFLG_Pos                                          (1U)
#define ADC_STS_EOCFLG_Msk                                          (0x1UL << ADC_STS_EOCFLG_Pos)                                  /*!< 0x00000002 */
#define ADC_STS_EOCFLG                                              ADC_STS_EOCFLG_Msk                                             /*!<End of conversion */
#define ADC_STS_INJEOCFLG_Pos                                       (2U)
#define ADC_STS_INJEOCFLG_Msk                                       (0x1UL << ADC_STS_INJEOCFLG_Pos)                               /*!< 0x00000004 */
#define ADC_STS_INJEOCFLG                                           ADC_STS_INJEOCFLG_Msk                                          /*!<Injected channel end of conversion */
#define ADC_STS_INJCSFLG_Pos                                        (3U)
#define ADC_STS_INJCSFLG_Msk                                        (0x1UL << ADC_STS_INJCSFLG_Pos)                                /*!< 0x00000008 */
#define ADC_STS_INJCSFLG                                            ADC_STS_INJCSFLG_Msk                                           /*!<Injected channel Start flag */
#define ADC_STS_REGCSFLG_Pos                                        (4U)
#define ADC_STS_REGCSFLG_Msk                                        (0x1UL << ADC_STS_REGCSFLG_Pos)                                /*!< 0x00000010 */
#define ADC_STS_REGCSFLG                                            ADC_STS_REGCSFLG_Msk                                           /*!<Regular channel Start flag */
#define ADC_STS_OVRFLG_Pos                                          (5U)
#define ADC_STS_OVRFLG_Msk                                          (0x1UL << ADC_STS_OVRFLG_Pos)                                  /*!< 0x00000020 */
#define ADC_STS_OVRFLG                                              ADC_STS_OVRFLG_Msk                                             /*!<Overrun flag */

/*******************  Bit definition for ADC_CTRL1 register  ********************/
#define ADC_CTRL1_AWDCHSEL_Pos                                      (0U)
#define ADC_CTRL1_AWDCHSEL_Msk                                      (0x1FUL << ADC_CTRL1_AWDCHSEL_Pos)                             /*!< 0x0000001F */
#define ADC_CTRL1_AWDCHSEL                                          ADC_CTRL1_AWDCHSEL_Msk                                         /*!<AWDCH[4:0] bits (Analog watchdog channel select bits) */
#define ADC_CTRL1_AWDCHSEL_0                                        (0x01UL << ADC_CTRL1_AWDCHSEL_Pos)                             /*!< 0x00000001 */
#define ADC_CTRL1_AWDCHSEL_1                                        (0x02UL << ADC_CTRL1_AWDCHSEL_Pos)                             /*!< 0x00000002 */
#define ADC_CTRL1_AWDCHSEL_2                                        (0x04UL << ADC_CTRL1_AWDCHSEL_Pos)                             /*!< 0x00000004 */
#define ADC_CTRL1_AWDCHSEL_3                                        (0x08UL << ADC_CTRL1_AWDCHSEL_Pos)                             /*!< 0x00000008 */
#define ADC_CTRL1_AWDCHSEL_4                                        (0x10UL << ADC_CTRL1_AWDCHSEL_Pos)                             /*!< 0x00000010 */
#define ADC_CTRL1_EOCIEN_Pos                                        (5U)
#define ADC_CTRL1_EOCIEN_Msk                                        (0x1UL << ADC_CTRL1_EOCIEN_Pos)                                /*!< 0x00000020 */
#define ADC_CTRL1_EOCIEN                                            ADC_CTRL1_EOCIEN_Msk                                           /*!<Interrupt enable for EOC */
#define ADC_CTRL1_AWDIEN_Pos                                        (6U)
#define ADC_CTRL1_AWDIEN_Msk                                        (0x1UL << ADC_CTRL1_AWDIEN_Pos)                                /*!< 0x00000040 */
#define ADC_CTRL1_AWDIEN                                            ADC_CTRL1_AWDIEN_Msk                                           /*!<AAnalog Watchdog interrupt enable */
#define ADC_CTRL1_INJEOCIEN_Pos                                     (7U)
#define ADC_CTRL1_INJEOCIEN_Msk                                     (0x1UL << ADC_CTRL1_INJEOCIEN_Pos)                             /*!< 0x00000080 */
#define ADC_CTRL1_INJEOCIEN                                         ADC_CTRL1_INJEOCIEN_Msk                                        /*!<Interrupt enable for injected channels */
#define ADC_CTRL1_SCANEN_Pos                                        (8U)
#define ADC_CTRL1_SCANEN_Msk                                        (0x1UL << ADC_CTRL1_SCANEN_Pos)                                /*!< 0x00000100 */
#define ADC_CTRL1_SCANEN                                            ADC_CTRL1_SCANEN_Msk                                           /*!<Scan mode */
#define ADC_CTRL1_AWDSGLEN_Pos                                      (9U)
#define ADC_CTRL1_AWDSGLEN_Msk                                      (0x1UL << ADC_CTRL1_AWDSGLEN_Pos)                              /*!< 0x00000200 */
#define ADC_CTRL1_AWDSGLEN                                          ADC_CTRL1_AWDSGLEN_Msk                                         /*!<Enable the watchdog on a single channel in scan mode */
#define ADC_CTRL1_INJGACEN_Pos                                      (10U)
#define ADC_CTRL1_INJGACEN_Msk                                      (0x1UL << ADC_CTRL1_INJGACEN_Pos)                              /*!< 0x00000400 */
#define ADC_CTRL1_INJGACEN                                          ADC_CTRL1_INJGACEN_Msk                                         /*!<Automatic injected group conversion */
#define ADC_CTRL1_REGDISCEN_Pos                                     (11U)
#define ADC_CTRL1_REGDISCEN_Msk                                     (0x1UL << ADC_CTRL1_REGDISCEN_Pos)                             /*!< 0x00000800 */
#define ADC_CTRL1_REGDISCEN                                         ADC_CTRL1_REGDISCEN_Msk                                        /*!<Discontinuous mode on regular channels */
#define ADC_CTRL1_INJDISCEN_Pos                                     (12U)
#define ADC_CTRL1_INJDISCEN_Msk                                     (0x1UL << ADC_CTRL1_INJDISCEN_Pos)                             /*!< 0x00001000 */
#define ADC_CTRL1_INJDISCEN                                         ADC_CTRL1_INJDISCEN_Msk                                        /*!<Discontinuous mode on injected channels */
#define ADC_CTRL1_DISCNUMCFG_Pos                                    (13U)
#define ADC_CTRL1_DISCNUMCFG_Msk                                    (0x7UL << ADC_CTRL1_DISCNUMCFG_Pos)                            /*!< 0x0000E000 */
#define ADC_CTRL1_DISCNUMCFG                                        ADC_CTRL1_DISCNUMCFG_Msk                                       /*!<DISCNUM[2:0] bits (Discontinuous mode channel count) */
#define ADC_CTRL1_DISCNUMCFG_0                                      (0x1UL << ADC_CTRL1_DISCNUMCFG_Pos)                            /*!< 0x00002000 */
#define ADC_CTRL1_DISCNUMCFG_1                                      (0x2UL << ADC_CTRL1_DISCNUMCFG_Pos)                            /*!< 0x00004000 */
#define ADC_CTRL1_DISCNUMCFG_2                                      (0x4UL << ADC_CTRL1_DISCNUMCFG_Pos)                            /*!< 0x00008000 */
#define ADC_CTRL1_INJAWDEN_Pos                                      (22U)
#define ADC_CTRL1_INJAWDEN_Msk                                      (0x1UL << ADC_CTRL1_INJAWDEN_Pos)                              /*!< 0x00400000 */
#define ADC_CTRL1_INJAWDEN                                          ADC_CTRL1_INJAWDEN_Msk                                         /*!<Analog watchdog enable on injected channels */
#define ADC_CTRL1_REGAWDEN_Pos                                      (23U)
#define ADC_CTRL1_REGAWDEN_Msk                                      (0x1UL << ADC_CTRL1_REGAWDEN_Pos)                              /*!< 0x00800000 */
#define ADC_CTRL1_REGAWDEN                                          ADC_CTRL1_REGAWDEN_Msk                                         /*!<Analog watchdog enable on regular channels */
#define ADC_CTRL1_RESSEL_Pos                                        (24U)
#define ADC_CTRL1_RESSEL_Msk                                        (0x3UL << ADC_CTRL1_RESSEL_Pos)                                /*!< 0x03000000 */
#define ADC_CTRL1_RESSEL                                            ADC_CTRL1_RESSEL_Msk                                           /*!<RES[2:0] bits (Resolution) */
#define ADC_CTRL1_RESSEL_0                                          (0x1UL << ADC_CTRL1_RESSEL_Pos)                                /*!< 0x01000000 */
#define ADC_CTRL1_RESSEL_1                                          (0x2UL << ADC_CTRL1_RESSEL_Pos)                                /*!< 0x02000000 */
#define ADC_CTRL1_OVRIEN_Pos                                        (26U)
#define ADC_CTRL1_OVRIEN_Msk                                        (0x1UL << ADC_CTRL1_OVRIEN_Pos)                                /*!< 0x04000000 */
#define ADC_CTRL1_OVRIEN                                            ADC_CTRL1_OVRIEN_Msk                                           /*!<overrun interrupt enable */
  
/*******************  Bit definition for ADC_CTRL2 register  ********************/
#define ADC_CTRL2_ADCEN_Pos                                         (0U)
#define ADC_CTRL2_ADCEN_Msk                                         (0x1UL << ADC_CTRL2_ADCEN_Pos)                                 /*!< 0x00000001 */
#define ADC_CTRL2_ADCEN                                             ADC_CTRL2_ADCEN_Msk                                            /*!<A/D Converter ON / OFF */
#define ADC_CTRL2_CONTCEN_Pos                                       (1U)
#define ADC_CTRL2_CONTCEN_Msk                                       (0x1UL << ADC_CTRL2_CONTCEN_Pos)                               /*!< 0x00000002 */
#define ADC_CTRL2_CONTCEN                                           ADC_CTRL2_CONTCEN_Msk                                          /*!<Continuous Conversion */
#define ADC_CTRL2_DMAEN_Pos                                         (8U)
#define ADC_CTRL2_DMAEN_Msk                                         (0x1UL << ADC_CTRL2_DMAEN_Pos)                                 /*!< 0x00000100 */
#define ADC_CTRL2_DMAEN                                             ADC_CTRL2_DMAEN_Msk                                            /*!<Direct Memory access mode */
#define ADC_CTRL2_DMADISSEL_Pos                                     (9U)
#define ADC_CTRL2_DMADISSEL_Msk                                     (0x1UL << ADC_CTRL2_DMADISSEL_Pos)                             /*!< 0x00000200 */
#define ADC_CTRL2_DMADISSEL                                         ADC_CTRL2_DMADISSEL_Msk                                        /*!<DMA disable selection (Single ADC) */
#define ADC_CTRL2_EOCSEL_Pos                                        (10U)
#define ADC_CTRL2_EOCSEL_Msk                                        (0x1UL << ADC_CTRL2_EOCSEL_Pos)                                /*!< 0x00000400 */
#define ADC_CTRL2_EOCSEL                                            ADC_CTRL2_EOCSEL_Msk                                           /*!<End of conversion selection */
#define ADC_CTRL2_DALIGNCFG_Pos                                     (11U)
#define ADC_CTRL2_DALIGNCFG_Msk                                     (0x1UL << ADC_CTRL2_DALIGNCFG_Pos)                             /*!< 0x00000800 */
#define ADC_CTRL2_DALIGNCFG                                         ADC_CTRL2_DALIGNCFG_Msk                                        /*!<Data Alignment */
#define ADC_CTRL2_INJGEXTTRGSEL_Pos                                 (16U)
#define ADC_CTRL2_INJGEXTTRGSEL_Msk                                 (0xFUL << ADC_CTRL2_INJGEXTTRGSEL_Pos)                         /*!< 0x000F0000 */
#define ADC_CTRL2_INJGEXTTRGSEL                                     ADC_CTRL2_INJGEXTTRGSEL_Msk                                    /*!<JEXTSEL[3:0] bits (External event select for injected group) */
#define ADC_CTRL2_INJGEXTTRGSEL_0                                   (0x1UL << ADC_CTRL2_INJGEXTTRGSEL_Pos)                         /*!< 0x00010000 */
#define ADC_CTRL2_INJGEXTTRGSEL_1                                   (0x2UL << ADC_CTRL2_INJGEXTTRGSEL_Pos)                         /*!< 0x00020000 */
#define ADC_CTRL2_INJGEXTTRGSEL_2                                   (0x4UL << ADC_CTRL2_INJGEXTTRGSEL_Pos)                         /*!< 0x00040000 */
#define ADC_CTRL2_INJGEXTTRGSEL_3                                   (0x8UL << ADC_CTRL2_INJGEXTTRGSEL_Pos)                         /*!< 0x00080000 */
#define ADC_CTRL2_INJEXTTRGEN_Pos                                   (20U)
#define ADC_CTRL2_INJEXTTRGEN_Msk                                   (0x3UL << ADC_CTRL2_INJEXTTRGEN_Pos)                           /*!< 0x00300000 */
#define ADC_CTRL2_INJEXTTRGEN                                       ADC_CTRL2_INJEXTTRGEN_Msk                                      /*!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) */
#define ADC_CTRL2_INJEXTTRGEN_0                                     (0x1UL << ADC_CTRL2_INJEXTTRGEN_Pos)                           /*!< 0x00100000 */
#define ADC_CTRL2_INJEXTTRGEN_1                                     (0x2UL << ADC_CTRL2_INJEXTTRGEN_Pos)                           /*!< 0x00200000 */
#define ADC_CTRL2_INJSWSC_Pos                                       (22U)
#define ADC_CTRL2_INJSWSC_Msk                                       (0x1UL << ADC_CTRL2_INJSWSC_Pos)                               /*!< 0x00400000 */
#define ADC_CTRL2_INJSWSC                                           ADC_CTRL2_INJSWSC_Msk                                          /*!<Start Conversion of injected channels */
#define ADC_CTRL2_REGEXTTRGSEL_Pos                                  (24U)
#define ADC_CTRL2_REGEXTTRGSEL_Msk                                  (0xFUL << ADC_CTRL2_REGEXTTRGSEL_Pos)                          /*!< 0x0F000000 */
#define ADC_CTRL2_REGEXTTRGSEL                                      ADC_CTRL2_REGEXTTRGSEL_Msk                                     /*!<EXTSEL[3:0] bits (External Event Select for regular group) */
#define ADC_CTRL2_REGEXTTRGSEL_0                                    (0x1UL << ADC_CTRL2_REGEXTTRGSEL_Pos)                          /*!< 0x01000000 */
#define ADC_CTRL2_REGEXTTRGSEL_1                                    (0x2UL << ADC_CTRL2_REGEXTTRGSEL_Pos)                          /*!< 0x02000000 */
#define ADC_CTRL2_REGEXTTRGSEL_2                                    (0x4UL << ADC_CTRL2_REGEXTTRGSEL_Pos)                          /*!< 0x04000000 */
#define ADC_CTRL2_REGEXTTRGSEL_3                                    (0x8UL << ADC_CTRL2_REGEXTTRGSEL_Pos)                          /*!< 0x08000000 */
#define ADC_CTRL2_REGEXTTRGEN_Pos                                   (28U)
#define ADC_CTRL2_REGEXTTRGEN_Msk                                   (0x3UL << ADC_CTRL2_REGEXTTRGEN_Pos)                           /*!< 0x30000000 */
#define ADC_CTRL2_REGEXTTRGEN                                       ADC_CTRL2_REGEXTTRGEN_Msk                                      /*!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) */
#define ADC_CTRL2_REGEXTTRGEN_0                                     (0x1UL << ADC_CTRL2_REGEXTTRGEN_Pos)                           /*!< 0x10000000 */
#define ADC_CTRL2_REGEXTTRGEN_1                                     (0x2UL << ADC_CTRL2_REGEXTTRGEN_Pos)                           /*!< 0x20000000 */
#define ADC_CTRL2_REGCHSC_Pos                                       (30U)
#define ADC_CTRL2_REGCHSC_Msk                                       (0x1UL << ADC_CTRL2_REGCHSC_Pos)                               /*!< 0x40000000 */
#define ADC_CTRL2_REGCHSC                                           ADC_CTRL2_REGCHSC_Msk                                          /*!<Start Conversion of regular channels */

/******************  Bit definition for ADC_SMPTIM1 register  *******************/
#define ADC_SMPTIM1_SMPCYCCFG10_Pos                                 (0U)
#define ADC_SMPTIM1_SMPCYCCFG10_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG10_Pos)                         /*!< 0x00000007 */
#define ADC_SMPTIM1_SMPCYCCFG10                                     ADC_SMPTIM1_SMPCYCCFG10_Msk                                    /*!<SMP10[2:0] bits (Channel 10 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG10_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG10_Pos)                         /*!< 0x00000001 */
#define ADC_SMPTIM1_SMPCYCCFG10_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG10_Pos)                         /*!< 0x00000002 */
#define ADC_SMPTIM1_SMPCYCCFG10_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG10_Pos)                         /*!< 0x00000004 */
#define ADC_SMPTIM1_SMPCYCCFG11_Pos                                 (3U)
#define ADC_SMPTIM1_SMPCYCCFG11_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG11_Pos)                         /*!< 0x00000038 */
#define ADC_SMPTIM1_SMPCYCCFG11                                     ADC_SMPTIM1_SMPCYCCFG11_Msk                                    /*!<SMP11[2:0] bits (Channel 11 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG11_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG11_Pos)                         /*!< 0x00000008 */
#define ADC_SMPTIM1_SMPCYCCFG11_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG11_Pos)                         /*!< 0x00000010 */
#define ADC_SMPTIM1_SMPCYCCFG11_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG11_Pos)                         /*!< 0x00000020 */
#define ADC_SMPTIM1_SMPCYCCFG12_Pos                                 (6U)
#define ADC_SMPTIM1_SMPCYCCFG12_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG12_Pos)                         /*!< 0x000001C0 */
#define ADC_SMPTIM1_SMPCYCCFG12                                     ADC_SMPTIM1_SMPCYCCFG12_Msk                                    /*!<SMP12[2:0] bits (Channel 12 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG12_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG12_Pos)                         /*!< 0x00000040 */
#define ADC_SMPTIM1_SMPCYCCFG12_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG12_Pos)                         /*!< 0x00000080 */
#define ADC_SMPTIM1_SMPCYCCFG12_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG12_Pos)                         /*!< 0x00000100 */
#define ADC_SMPTIM1_SMPCYCCFG13_Pos                                 (9U)
#define ADC_SMPTIM1_SMPCYCCFG13_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG13_Pos)                         /*!< 0x00000E00 */
#define ADC_SMPTIM1_SMPCYCCFG13                                     ADC_SMPTIM1_SMPCYCCFG13_Msk                                    /*!<SMP13[2:0] bits (Channel 13 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG13_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG13_Pos)                         /*!< 0x00000200 */
#define ADC_SMPTIM1_SMPCYCCFG13_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG13_Pos)                         /*!< 0x00000400 */
#define ADC_SMPTIM1_SMPCYCCFG13_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG13_Pos)                         /*!< 0x00000800 */
#define ADC_SMPTIM1_SMPCYCCFG14_Pos                                 (12U)
#define ADC_SMPTIM1_SMPCYCCFG14_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG14_Pos)                         /*!< 0x00007000 */
#define ADC_SMPTIM1_SMPCYCCFG14                                     ADC_SMPTIM1_SMPCYCCFG14_Msk                                    /*!<SMP14[2:0] bits (Channel 14 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG14_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG14_Pos)                         /*!< 0x00001000 */
#define ADC_SMPTIM1_SMPCYCCFG14_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG14_Pos)                         /*!< 0x00002000 */
#define ADC_SMPTIM1_SMPCYCCFG14_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG14_Pos)                         /*!< 0x00004000 */
#define ADC_SMPTIM1_SMPCYCCFG15_Pos                                 (15U)
#define ADC_SMPTIM1_SMPCYCCFG15_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG15_Pos)                         /*!< 0x00038000 */
#define ADC_SMPTIM1_SMPCYCCFG15                                     ADC_SMPTIM1_SMPCYCCFG15_Msk                                    /*!<SMP15[2:0] bits (Channel 15 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG15_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG15_Pos)                         /*!< 0x00008000 */
#define ADC_SMPTIM1_SMPCYCCFG15_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG15_Pos)                         /*!< 0x00010000 */
#define ADC_SMPTIM1_SMPCYCCFG15_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG15_Pos)                         /*!< 0x00020000 */
#define ADC_SMPTIM1_SMPCYCCFG16_Pos                                 (18U)
#define ADC_SMPTIM1_SMPCYCCFG16_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG16_Pos)                         /*!< 0x001C0000 */
#define ADC_SMPTIM1_SMPCYCCFG16                                     ADC_SMPTIM1_SMPCYCCFG16_Msk                                    /*!<SMP16[2:0] bits (Channel 16 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG16_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG16_Pos)                         /*!< 0x00040000 */
#define ADC_SMPTIM1_SMPCYCCFG16_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG16_Pos)                         /*!< 0x00080000 */
#define ADC_SMPTIM1_SMPCYCCFG16_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG16_Pos)                         /*!< 0x00100000 */
#define ADC_SMPTIM1_SMPCYCCFG17_Pos                                 (21U)
#define ADC_SMPTIM1_SMPCYCCFG17_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG17_Pos)                         /*!< 0x00E00000 */
#define ADC_SMPTIM1_SMPCYCCFG17                                     ADC_SMPTIM1_SMPCYCCFG17_Msk                                    /*!<SMP17[2:0] bits (Channel 17 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG17_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG17_Pos)                         /*!< 0x00200000 */
#define ADC_SMPTIM1_SMPCYCCFG17_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG17_Pos)                         /*!< 0x00400000 */
#define ADC_SMPTIM1_SMPCYCCFG17_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG17_Pos)                         /*!< 0x00800000 */
#define ADC_SMPTIM1_SMPCYCCFG18_Pos                                 (24U)
#define ADC_SMPTIM1_SMPCYCCFG18_Msk                                 (0x7UL << ADC_SMPTIM1_SMPCYCCFG18_Pos)                         /*!< 0x07000000 */
#define ADC_SMPTIM1_SMPCYCCFG18                                     ADC_SMPTIM1_SMPCYCCFG18_Msk                                    /*!<SMP18[2:0] bits (Channel 18 Sample time selection) */
#define ADC_SMPTIM1_SMPCYCCFG18_0                                   (0x1UL << ADC_SMPTIM1_SMPCYCCFG18_Pos)                         /*!< 0x01000000 */
#define ADC_SMPTIM1_SMPCYCCFG18_1                                   (0x2UL << ADC_SMPTIM1_SMPCYCCFG18_Pos)                         /*!< 0x02000000 */
#define ADC_SMPTIM1_SMPCYCCFG18_2                                   (0x4UL << ADC_SMPTIM1_SMPCYCCFG18_Pos)                         /*!< 0x04000000 */

/******************  Bit definition for ADC_SMPTIM2 register  *******************/
#define ADC_SMPTIM2_SMPCYCCFG0_Pos                                  (0U)
#define ADC_SMPTIM2_SMPCYCCFG0_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG0_Pos)                          /*!< 0x00000007 */
#define ADC_SMPTIM2_SMPCYCCFG0                                      ADC_SMPTIM2_SMPCYCCFG0_Msk                                     /*!<SMP0[2:0] bits (Channel 0 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG0_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG0_Pos)                          /*!< 0x00000001 */
#define ADC_SMPTIM2_SMPCYCCFG0_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG0_Pos)                          /*!< 0x00000002 */
#define ADC_SMPTIM2_SMPCYCCFG0_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG0_Pos)                          /*!< 0x00000004 */
#define ADC_SMPTIM2_SMPCYCCFG1_Pos                                  (3U)
#define ADC_SMPTIM2_SMPCYCCFG1_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG1_Pos)                          /*!< 0x00000038 */
#define ADC_SMPTIM2_SMPCYCCFG1                                      ADC_SMPTIM2_SMPCYCCFG1_Msk                                     /*!<SMP1[2:0] bits (Channel 1 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG1_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG1_Pos)                          /*!< 0x00000008 */
#define ADC_SMPTIM2_SMPCYCCFG1_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG1_Pos)                          /*!< 0x00000010 */
#define ADC_SMPTIM2_SMPCYCCFG1_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG1_Pos)                          /*!< 0x00000020 */
#define ADC_SMPTIM2_SMPCYCCFG2_Pos                                  (6U)
#define ADC_SMPTIM2_SMPCYCCFG2_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG2_Pos)                          /*!< 0x000001C0 */
#define ADC_SMPTIM2_SMPCYCCFG2                                      ADC_SMPTIM2_SMPCYCCFG2_Msk                                     /*!<SMP2[2:0] bits (Channel 2 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG2_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG2_Pos)                          /*!< 0x00000040 */
#define ADC_SMPTIM2_SMPCYCCFG2_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG2_Pos)                          /*!< 0x00000080 */
#define ADC_SMPTIM2_SMPCYCCFG2_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG2_Pos)                          /*!< 0x00000100 */
#define ADC_SMPTIM2_SMPCYCCFG3_Pos                                  (9U)
#define ADC_SMPTIM2_SMPCYCCFG3_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG3_Pos)                          /*!< 0x00000E00 */
#define ADC_SMPTIM2_SMPCYCCFG3                                      ADC_SMPTIM2_SMPCYCCFG3_Msk                                     /*!<SMP3[2:0] bits (Channel 3 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG3_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG3_Pos)                          /*!< 0x00000200 */
#define ADC_SMPTIM2_SMPCYCCFG3_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG3_Pos)                          /*!< 0x00000400 */
#define ADC_SMPTIM2_SMPCYCCFG3_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG3_Pos)                          /*!< 0x00000800 */
#define ADC_SMPTIM2_SMPCYCCFG4_Pos                                  (12U)
#define ADC_SMPTIM2_SMPCYCCFG4_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG4_Pos)                          /*!< 0x00007000 */
#define ADC_SMPTIM2_SMPCYCCFG4                                      ADC_SMPTIM2_SMPCYCCFG4_Msk                                     /*!<SMP4[2:0] bits (Channel 4 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG4_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG4_Pos)                          /*!< 0x00001000 */
#define ADC_SMPTIM2_SMPCYCCFG4_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG4_Pos)                          /*!< 0x00002000 */
#define ADC_SMPTIM2_SMPCYCCFG4_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG4_Pos)                          /*!< 0x00004000 */
#define ADC_SMPTIM2_SMPCYCCFG5_Pos                                  (15U)
#define ADC_SMPTIM2_SMPCYCCFG5_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG5_Pos)                          /*!< 0x00038000 */
#define ADC_SMPTIM2_SMPCYCCFG5                                      ADC_SMPTIM2_SMPCYCCFG5_Msk                                     /*!<SMP5[2:0] bits (Channel 5 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG5_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG5_Pos)                          /*!< 0x00008000 */
#define ADC_SMPTIM2_SMPCYCCFG5_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG5_Pos)                          /*!< 0x00010000 */
#define ADC_SMPTIM2_SMPCYCCFG5_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG5_Pos)                          /*!< 0x00020000 */
#define ADC_SMPTIM2_SMPCYCCFG6_Pos                                  (18U)
#define ADC_SMPTIM2_SMPCYCCFG6_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG6_Pos)                          /*!< 0x001C0000 */
#define ADC_SMPTIM2_SMPCYCCFG6                                      ADC_SMPTIM2_SMPCYCCFG6_Msk                                     /*!<SMP6[2:0] bits (Channel 6 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG6_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG6_Pos)                          /*!< 0x00040000 */
#define ADC_SMPTIM2_SMPCYCCFG6_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG6_Pos)                          /*!< 0x00080000 */
#define ADC_SMPTIM2_SMPCYCCFG6_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG6_Pos)                          /*!< 0x00100000 */
#define ADC_SMPTIM2_SMPCYCCFG7_Pos                                  (21U)
#define ADC_SMPTIM2_SMPCYCCFG7_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG7_Pos)                          /*!< 0x00E00000 */
#define ADC_SMPTIM2_SMPCYCCFG7                                      ADC_SMPTIM2_SMPCYCCFG7_Msk                                     /*!<SMP7[2:0] bits (Channel 7 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG7_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG7_Pos)                          /*!< 0x00200000 */
#define ADC_SMPTIM2_SMPCYCCFG7_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG7_Pos)                          /*!< 0x00400000 */
#define ADC_SMPTIM2_SMPCYCCFG7_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG7_Pos)                          /*!< 0x00800000 */
#define ADC_SMPTIM2_SMPCYCCFG8_Pos                                  (24U)
#define ADC_SMPTIM2_SMPCYCCFG8_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG8_Pos)                          /*!< 0x07000000 */
#define ADC_SMPTIM2_SMPCYCCFG8                                      ADC_SMPTIM2_SMPCYCCFG8_Msk                                     /*!<SMP8[2:0] bits (Channel 8 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG8_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG8_Pos)                          /*!< 0x01000000 */
#define ADC_SMPTIM2_SMPCYCCFG8_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG8_Pos)                          /*!< 0x02000000 */
#define ADC_SMPTIM2_SMPCYCCFG8_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG8_Pos)                          /*!< 0x04000000 */
#define ADC_SMPTIM2_SMPCYCCFG9_Pos                                  (27U)
#define ADC_SMPTIM2_SMPCYCCFG9_Msk                                  (0x7UL << ADC_SMPTIM2_SMPCYCCFG9_Pos)                          /*!< 0x38000000 */
#define ADC_SMPTIM2_SMPCYCCFG9                                      ADC_SMPTIM2_SMPCYCCFG9_Msk                                     /*!<SMP9[2:0] bits (Channel 9 Sample time selection) */
#define ADC_SMPTIM2_SMPCYCCFG9_0                                    (0x1UL << ADC_SMPTIM2_SMPCYCCFG9_Pos)                          /*!< 0x08000000 */
#define ADC_SMPTIM2_SMPCYCCFG9_1                                    (0x2UL << ADC_SMPTIM2_SMPCYCCFG9_Pos)                          /*!< 0x10000000 */
#define ADC_SMPTIM2_SMPCYCCFG9_2                                    (0x4UL << ADC_SMPTIM2_SMPCYCCFG9_Pos)                          /*!< 0x20000000 */

/******************  Bit definition for ADC_INJDOF1 register  *******************/
#define ADC_INJDOF1_INJDOF1_Pos                                     (0U)
#define ADC_INJDOF1_INJDOF1_Msk                                     (0xFFFUL << ADC_INJDOF1_INJDOF1_Pos)                           /*!< 0x00000FFF */
#define ADC_INJDOF1_INJDOF1                                         ADC_INJDOF1_INJDOF1_Msk                                        /*!<Data offset for injected channel 1 */

/******************  Bit definition for ADC_INJDOF2 register  *******************/
#define ADC_INJDOF2_INJDOF2_Pos                                     (0U)
#define ADC_INJDOF2_INJDOF2_Msk                                     (0xFFFUL << ADC_INJDOF2_INJDOF2_Pos)                           /*!< 0x00000FFF */
#define ADC_INJDOF2_INJDOF2                                         ADC_INJDOF2_INJDOF2_Msk                                        /*!<Data offset for injected channel 2 */

/******************  Bit definition for ADC_INJDOF3 register  *******************/
#define ADC_INJDOF3_INJDOF3_Pos                                     (0U)
#define ADC_INJDOF3_INJDOF3_Msk                                     (0xFFFUL << ADC_INJDOF3_INJDOF3_Pos)                           /*!< 0x00000FFF */
#define ADC_INJDOF3_INJDOF3                                         ADC_INJDOF3_INJDOF3_Msk                                        /*!<Data offset for injected channel 3 */

/******************  Bit definition for ADC_INJDOF4 register  *******************/
#define ADC_INJDOF4_INJDOF4_Pos                                     (0U)
#define ADC_INJDOF4_INJDOF4_Msk                                     (0xFFFUL << ADC_INJDOF4_INJDOF4_Pos)                           /*!< 0x00000FFF */
#define ADC_INJDOF4_INJDOF4                                         ADC_INJDOF4_INJDOF4_Msk                                        /*!<Data offset for injected channel 4 */

/*******************  Bit definition for ADC_AWDHT register  ********************/
#define ADC_AWDHT_AWDHT_Pos                                         (0U)
#define ADC_AWDHT_AWDHT_Msk                                         (0xFFFUL << ADC_AWDHT_AWDHT_Pos)                               /*!< 0x00000FFF */
#define ADC_AWDHT_AWDHT                                             ADC_AWDHT_AWDHT_Msk                                            /*!<Analog watchdog high threshold */

/*******************  Bit definition for ADC_AWDLT register  ********************/
#define ADC_AWDLT_AWDLT_Pos                                         (0U)
#define ADC_AWDLT_AWDLT_Msk                                         (0xFFFUL << ADC_AWDLT_AWDLT_Pos)                               /*!< 0x00000FFF */
#define ADC_AWDLT_AWDLT                                             ADC_AWDLT_AWDLT_Msk                                            /*!<Analog watchdog low threshold */

/*******************  Bit definition for ADC_REGSEQ1 register  *******************/
#define ADC_REGSEQ1_REGSEQC13_Pos                                   (0U)
#define ADC_REGSEQ1_REGSEQC13_Msk                                   (0x1FUL << ADC_REGSEQ1_REGSEQC13_Pos)                          /*!< 0x0000001F */
#define ADC_REGSEQ1_REGSEQC13                                       ADC_REGSEQ1_REGSEQC13_Msk                                      /*!<SQ13[4:0] bits (13th conversion in regular sequence) */
#define ADC_REGSEQ1_REGSEQC13_0                                     (0x01UL << ADC_REGSEQ1_REGSEQC13_Pos)                          /*!< 0x00000001 */
#define ADC_REGSEQ1_REGSEQC13_1                                     (0x02UL << ADC_REGSEQ1_REGSEQC13_Pos)                          /*!< 0x00000002 */
#define ADC_REGSEQ1_REGSEQC13_2                                     (0x04UL << ADC_REGSEQ1_REGSEQC13_Pos)                          /*!< 0x00000004 */
#define ADC_REGSEQ1_REGSEQC13_3                                     (0x08UL << ADC_REGSEQ1_REGSEQC13_Pos)                          /*!< 0x00000008 */
#define ADC_REGSEQ1_REGSEQC13_4                                     (0x10UL << ADC_REGSEQ1_REGSEQC13_Pos)                          /*!< 0x00000010 */
#define ADC_REGSEQ1_REGSEQC14_Pos                                   (5U)
#define ADC_REGSEQ1_REGSEQC14_Msk                                   (0x1FUL << ADC_REGSEQ1_REGSEQC14_Pos)                          /*!< 0x000003E0 */
#define ADC_REGSEQ1_REGSEQC14                                       ADC_REGSEQ1_REGSEQC14_Msk                                      /*!<SQ14[4:0] bits (14th conversion in regular sequence) */
#define ADC_REGSEQ1_REGSEQC14_0                                     (0x01UL << ADC_REGSEQ1_REGSEQC14_Pos)                          /*!< 0x00000020 */
#define ADC_REGSEQ1_REGSEQC14_1                                     (0x02UL << ADC_REGSEQ1_REGSEQC14_Pos)                          /*!< 0x00000040 */
#define ADC_REGSEQ1_REGSEQC14_2                                     (0x04UL << ADC_REGSEQ1_REGSEQC14_Pos)                          /*!< 0x00000080 */
#define ADC_REGSEQ1_REGSEQC14_3                                     (0x08UL << ADC_REGSEQ1_REGSEQC14_Pos)                          /*!< 0x00000100 */
#define ADC_REGSEQ1_REGSEQC14_4                                     (0x10UL << ADC_REGSEQ1_REGSEQC14_Pos)                          /*!< 0x00000200 */
#define ADC_REGSEQ1_REGSEQC15_Pos                                   (10U)
#define ADC_REGSEQ1_REGSEQC15_Msk                                   (0x1FUL << ADC_REGSEQ1_REGSEQC15_Pos)                          /*!< 0x00007C00 */
#define ADC_REGSEQ1_REGSEQC15                                       ADC_REGSEQ1_REGSEQC15_Msk                                      /*!<SQ15[4:0] bits (15th conversion in regular sequence) */
#define ADC_REGSEQ1_REGSEQC15_0                                     (0x01UL << ADC_REGSEQ1_REGSEQC15_Pos)                          /*!< 0x00000400 */
#define ADC_REGSEQ1_REGSEQC15_1                                     (0x02UL << ADC_REGSEQ1_REGSEQC15_Pos)                          /*!< 0x00000800 */
#define ADC_REGSEQ1_REGSEQC15_2                                     (0x04UL << ADC_REGSEQ1_REGSEQC15_Pos)                          /*!< 0x00001000 */
#define ADC_REGSEQ1_REGSEQC15_3                                     (0x08UL << ADC_REGSEQ1_REGSEQC15_Pos)                          /*!< 0x00002000 */
#define ADC_REGSEQ1_REGSEQC15_4                                     (0x10UL << ADC_REGSEQ1_REGSEQC15_Pos)                          /*!< 0x00004000 */
#define ADC_REGSEQ1_REGSEQC16_Pos                                   (15U)
#define ADC_REGSEQ1_REGSEQC16_Msk                                   (0x1FUL << ADC_REGSEQ1_REGSEQC16_Pos)                          /*!< 0x000F8000 */
#define ADC_REGSEQ1_REGSEQC16                                       ADC_REGSEQ1_REGSEQC16_Msk                                      /*!<SQ16[4:0] bits (16th conversion in regular sequence) */
#define ADC_REGSEQ1_REGSEQC16_0                                     (0x01UL << ADC_REGSEQ1_REGSEQC16_Pos)                          /*!< 0x00008000 */
#define ADC_REGSEQ1_REGSEQC16_1                                     (0x02UL << ADC_REGSEQ1_REGSEQC16_Pos)                          /*!< 0x00010000 */
#define ADC_REGSEQ1_REGSEQC16_2                                     (0x04UL << ADC_REGSEQ1_REGSEQC16_Pos)                          /*!< 0x00020000 */
#define ADC_REGSEQ1_REGSEQC16_3                                     (0x08UL << ADC_REGSEQ1_REGSEQC16_Pos)                          /*!< 0x00040000 */
#define ADC_REGSEQ1_REGSEQC16_4                                     (0x10UL << ADC_REGSEQ1_REGSEQC16_Pos)                          /*!< 0x00080000 */
#define ADC_REGSEQ1_REGSEQLEN_Pos                                   (20U)
#define ADC_REGSEQ1_REGSEQLEN_Msk                                   (0xFUL << ADC_REGSEQ1_REGSEQLEN_Pos)                           /*!< 0x00F00000 */
#define ADC_REGSEQ1_REGSEQLEN                                       ADC_REGSEQ1_REGSEQLEN_Msk                                      /*!<L[3:0] bits (Regular channel sequence length) */
#define ADC_REGSEQ1_REGSEQLEN_0                                     (0x1UL << ADC_REGSEQ1_REGSEQLEN_Pos)                           /*!< 0x00100000 */
#define ADC_REGSEQ1_REGSEQLEN_1                                     (0x2UL << ADC_REGSEQ1_REGSEQLEN_Pos)                           /*!< 0x00200000 */
#define ADC_REGSEQ1_REGSEQLEN_2                                     (0x4UL << ADC_REGSEQ1_REGSEQLEN_Pos)                           /*!< 0x00400000 */
#define ADC_REGSEQ1_REGSEQLEN_3                                     (0x8UL << ADC_REGSEQ1_REGSEQLEN_Pos)                           /*!< 0x00800000 */

/*******************  Bit definition for ADC_REGSEQ2 register  *******************/
#define ADC_REGSEQ2_REGSEQC7_Pos                                    (0U)
#define ADC_REGSEQ2_REGSEQC7_Msk                                    (0x1FUL << ADC_REGSEQ2_REGSEQC7_Pos)                           /*!< 0x0000001F */
#define ADC_REGSEQ2_REGSEQC7                                        ADC_REGSEQ2_REGSEQC7_Msk                                       /*!<SQ7[4:0] bits (7th conversion in regular sequence) */
#define ADC_REGSEQ2_REGSEQC7_0                                      (0x01UL << ADC_REGSEQ2_REGSEQC7_Pos)                           /*!< 0x00000001 */
#define ADC_REGSEQ2_REGSEQC7_1                                      (0x02UL << ADC_REGSEQ2_REGSEQC7_Pos)                           /*!< 0x00000002 */
#define ADC_REGSEQ2_REGSEQC7_2                                      (0x04UL << ADC_REGSEQ2_REGSEQC7_Pos)                           /*!< 0x00000004 */
#define ADC_REGSEQ2_REGSEQC7_3                                      (0x08UL << ADC_REGSEQ2_REGSEQC7_Pos)                           /*!< 0x00000008 */
#define ADC_REGSEQ2_REGSEQC7_4                                      (0x10UL << ADC_REGSEQ2_REGSEQC7_Pos)                           /*!< 0x00000010 */
#define ADC_REGSEQ2_REGSEQC8_Pos                                    (5U)
#define ADC_REGSEQ2_REGSEQC8_Msk                                    (0x1FUL << ADC_REGSEQ2_REGSEQC8_Pos)                           /*!< 0x000003E0 */
#define ADC_REGSEQ2_REGSEQC8                                        ADC_REGSEQ2_REGSEQC8_Msk                                       /*!<SQ8[4:0] bits (8th conversion in regular sequence) */
#define ADC_REGSEQ2_REGSEQC8_0                                      (0x01UL << ADC_REGSEQ2_REGSEQC8_Pos)                           /*!< 0x00000020 */
#define ADC_REGSEQ2_REGSEQC8_1                                      (0x02UL << ADC_REGSEQ2_REGSEQC8_Pos)                           /*!< 0x00000040 */
#define ADC_REGSEQ2_REGSEQC8_2                                      (0x04UL << ADC_REGSEQ2_REGSEQC8_Pos)                           /*!< 0x00000080 */
#define ADC_REGSEQ2_REGSEQC8_3                                      (0x08UL << ADC_REGSEQ2_REGSEQC8_Pos)                           /*!< 0x00000100 */
#define ADC_REGSEQ2_REGSEQC8_4                                      (0x10UL << ADC_REGSEQ2_REGSEQC8_Pos)                           /*!< 0x00000200 */
#define ADC_REGSEQ2_REGSEQC9_Pos                                    (10U)
#define ADC_REGSEQ2_REGSEQC9_Msk                                    (0x1FUL << ADC_REGSEQ2_REGSEQC9_Pos)                           /*!< 0x00007C00 */
#define ADC_REGSEQ2_REGSEQC9                                        ADC_REGSEQ2_REGSEQC9_Msk                                       /*!<SQ9[4:0] bits (9th conversion in regular sequence) */
#define ADC_REGSEQ2_REGSEQC9_0                                      (0x01UL << ADC_REGSEQ2_REGSEQC9_Pos)                           /*!< 0x00000400 */
#define ADC_REGSEQ2_REGSEQC9_1                                      (0x02UL << ADC_REGSEQ2_REGSEQC9_Pos)                           /*!< 0x00000800 */
#define ADC_REGSEQ2_REGSEQC9_2                                      (0x04UL << ADC_REGSEQ2_REGSEQC9_Pos)                           /*!< 0x00001000 */
#define ADC_REGSEQ2_REGSEQC9_3                                      (0x08UL << ADC_REGSEQ2_REGSEQC9_Pos)                           /*!< 0x00002000 */
#define ADC_REGSEQ2_REGSEQC9_4                                      (0x10UL << ADC_REGSEQ2_REGSEQC9_Pos)                           /*!< 0x00004000 */
#define ADC_REGSEQ2_REGSEQC10_Pos                                   (15U)
#define ADC_REGSEQ2_REGSEQC10_Msk                                   (0x1FUL << ADC_REGSEQ2_REGSEQC10_Pos)                          /*!< 0x000F8000 */
#define ADC_REGSEQ2_REGSEQC10                                       ADC_REGSEQ2_REGSEQC10_Msk                                      /*!<SQ10[4:0] bits (10th conversion in regular sequence) */
#define ADC_REGSEQ2_REGSEQC10_0                                     (0x01UL << ADC_REGSEQ2_REGSEQC10_Pos)                          /*!< 0x00008000 */
#define ADC_REGSEQ2_REGSEQC10_1                                     (0x02UL << ADC_REGSEQ2_REGSEQC10_Pos)                          /*!< 0x00010000 */
#define ADC_REGSEQ2_REGSEQC10_2                                     (0x04UL << ADC_REGSEQ2_REGSEQC10_Pos)                          /*!< 0x00020000 */
#define ADC_REGSEQ2_REGSEQC10_3                                     (0x08UL << ADC_REGSEQ2_REGSEQC10_Pos)                          /*!< 0x00040000 */
#define ADC_REGSEQ2_REGSEQC10_4                                     (0x10UL << ADC_REGSEQ2_REGSEQC10_Pos)                          /*!< 0x00080000 */
#define ADC_REGSEQ2_REGSEQC11_Pos                                   (20U)
#define ADC_REGSEQ2_REGSEQC11_Msk                                   (0x1FUL << ADC_REGSEQ2_REGSEQC11_Pos)                          /*!< 0x01F00000 */
#define ADC_REGSEQ2_REGSEQC11                                       ADC_REGSEQ2_REGSEQC11_Msk                                      /*!<SQ11[4:0] bits (11th conversion in regular sequence) */
#define ADC_REGSEQ2_REGSEQC11_0                                     (0x01UL << ADC_REGSEQ2_REGSEQC11_Pos)                          /*!< 0x00100000 */
#define ADC_REGSEQ2_REGSEQC11_1                                     (0x02UL << ADC_REGSEQ2_REGSEQC11_Pos)                          /*!< 0x00200000 */
#define ADC_REGSEQ2_REGSEQC11_2                                     (0x04UL << ADC_REGSEQ2_REGSEQC11_Pos)                          /*!< 0x00400000 */
#define ADC_REGSEQ2_REGSEQC11_3                                     (0x08UL << ADC_REGSEQ2_REGSEQC11_Pos)                          /*!< 0x00800000 */
#define ADC_REGSEQ2_REGSEQC11_4                                     (0x10UL << ADC_REGSEQ2_REGSEQC11_Pos)                          /*!< 0x01000000 */
#define ADC_REGSEQ2_REGSEQC12_Pos                                   (25U)
#define ADC_REGSEQ2_REGSEQC12_Msk                                   (0x1FUL << ADC_REGSEQ2_REGSEQC12_Pos)                          /*!< 0x3E000000 */
#define ADC_REGSEQ2_REGSEQC12                                       ADC_REGSEQ2_REGSEQC12_Msk                                      /*!<SQ12[4:0] bits (12th conversion in regular sequence) */
#define ADC_REGSEQ2_REGSEQC12_0                                     (0x01UL << ADC_REGSEQ2_REGSEQC12_Pos)                          /*!< 0x02000000 */
#define ADC_REGSEQ2_REGSEQC12_1                                     (0x02UL << ADC_REGSEQ2_REGSEQC12_Pos)                          /*!< 0x04000000 */
#define ADC_REGSEQ2_REGSEQC12_2                                     (0x04UL << ADC_REGSEQ2_REGSEQC12_Pos)                          /*!< 0x08000000 */
#define ADC_REGSEQ2_REGSEQC12_3                                     (0x08UL << ADC_REGSEQ2_REGSEQC12_Pos)                          /*!< 0x10000000 */
#define ADC_REGSEQ2_REGSEQC12_4                                     (0x10UL << ADC_REGSEQ2_REGSEQC12_Pos)                          /*!< 0x20000000 */

/*******************  Bit definition for ADC_REGSEQ3 register  *******************/
#define ADC_REGSEQ3_REGSEQC1_Pos                                    (0U)
#define ADC_REGSEQ3_REGSEQC1_Msk                                    (0x1FUL << ADC_REGSEQ3_REGSEQC1_Pos)                           /*!< 0x0000001F */
#define ADC_REGSEQ3_REGSEQC1                                        ADC_REGSEQ3_REGSEQC1_Msk                                       /*!<SQ1[4:0] bits (1st conversion in regular sequence) */
#define ADC_REGSEQ3_REGSEQC1_0                                      (0x01UL << ADC_REGSEQ3_REGSEQC1_Pos)                           /*!< 0x00000001 */
#define ADC_REGSEQ3_REGSEQC1_1                                      (0x02UL << ADC_REGSEQ3_REGSEQC1_Pos)                           /*!< 0x00000002 */
#define ADC_REGSEQ3_REGSEQC1_2                                      (0x04UL << ADC_REGSEQ3_REGSEQC1_Pos)                           /*!< 0x00000004 */
#define ADC_REGSEQ3_REGSEQC1_3                                      (0x08UL << ADC_REGSEQ3_REGSEQC1_Pos)                           /*!< 0x00000008 */
#define ADC_REGSEQ3_REGSEQC1_4                                      (0x10UL << ADC_REGSEQ3_REGSEQC1_Pos)                           /*!< 0x00000010 */
#define ADC_REGSEQ3_REGSEQC2_Pos                                    (5U)
#define ADC_REGSEQ3_REGSEQC2_Msk                                    (0x1FUL << ADC_REGSEQ3_REGSEQC2_Pos)                           /*!< 0x000003E0 */
#define ADC_REGSEQ3_REGSEQC2                                        ADC_REGSEQ3_REGSEQC2_Msk                                       /*!<SQ2[4:0] bits (2nd conversion in regular sequence) */
#define ADC_REGSEQ3_REGSEQC2_0                                      (0x01UL << ADC_REGSEQ3_REGSEQC2_Pos)                           /*!< 0x00000020 */
#define ADC_REGSEQ3_REGSEQC2_1                                      (0x02UL << ADC_REGSEQ3_REGSEQC2_Pos)                           /*!< 0x00000040 */
#define ADC_REGSEQ3_REGSEQC2_2                                      (0x04UL << ADC_REGSEQ3_REGSEQC2_Pos)                           /*!< 0x00000080 */
#define ADC_REGSEQ3_REGSEQC2_3                                      (0x08UL << ADC_REGSEQ3_REGSEQC2_Pos)                           /*!< 0x00000100 */
#define ADC_REGSEQ3_REGSEQC2_4                                      (0x10UL << ADC_REGSEQ3_REGSEQC2_Pos)                           /*!< 0x00000200 */
#define ADC_REGSEQ3_REGSEQC3_Pos                                    (10U)
#define ADC_REGSEQ3_REGSEQC3_Msk                                    (0x1FUL << ADC_REGSEQ3_REGSEQC3_Pos)                           /*!< 0x00007C00 */
#define ADC_REGSEQ3_REGSEQC3                                        ADC_REGSEQ3_REGSEQC3_Msk                                       /*!<SQ3[4:0] bits (3rd conversion in regular sequence) */
#define ADC_REGSEQ3_REGSEQC3_0                                      (0x01UL << ADC_REGSEQ3_REGSEQC3_Pos)                           /*!< 0x00000400 */
#define ADC_REGSEQ3_REGSEQC3_1                                      (0x02UL << ADC_REGSEQ3_REGSEQC3_Pos)                           /*!< 0x00000800 */
#define ADC_REGSEQ3_REGSEQC3_2                                      (0x04UL << ADC_REGSEQ3_REGSEQC3_Pos)                           /*!< 0x00001000 */
#define ADC_REGSEQ3_REGSEQC3_3                                      (0x08UL << ADC_REGSEQ3_REGSEQC3_Pos)                           /*!< 0x00002000 */
#define ADC_REGSEQ3_REGSEQC3_4                                      (0x10UL << ADC_REGSEQ3_REGSEQC3_Pos)                           /*!< 0x00004000 */
#define ADC_REGSEQ3_REGSEQC4_Pos                                    (15U)
#define ADC_REGSEQ3_REGSEQC4_Msk                                    (0x1FUL << ADC_REGSEQ3_REGSEQC4_Pos)                           /*!< 0x000F8000 */
#define ADC_REGSEQ3_REGSEQC4                                        ADC_REGSEQ3_REGSEQC4_Msk                                       /*!<SQ4[4:0] bits (4th conversion in regular sequence) */
#define ADC_REGSEQ3_REGSEQC4_0                                      (0x01UL << ADC_REGSEQ3_REGSEQC4_Pos)                           /*!< 0x00008000 */
#define ADC_REGSEQ3_REGSEQC4_1                                      (0x02UL << ADC_REGSEQ3_REGSEQC4_Pos)                           /*!< 0x00010000 */
#define ADC_REGSEQ3_REGSEQC4_2                                      (0x04UL << ADC_REGSEQ3_REGSEQC4_Pos)                           /*!< 0x00020000 */
#define ADC_REGSEQ3_REGSEQC4_3                                      (0x08UL << ADC_REGSEQ3_REGSEQC4_Pos)                           /*!< 0x00040000 */
#define ADC_REGSEQ3_REGSEQC4_4                                      (0x10UL << ADC_REGSEQ3_REGSEQC4_Pos)                           /*!< 0x00080000 */
#define ADC_REGSEQ3_REGSEQC5_Pos                                    (20U)
#define ADC_REGSEQ3_REGSEQC5_Msk                                    (0x1FUL << ADC_REGSEQ3_REGSEQC5_Pos)                           /*!< 0x01F00000 */
#define ADC_REGSEQ3_REGSEQC5                                        ADC_REGSEQ3_REGSEQC5_Msk                                       /*!<SQ5[4:0] bits (5th conversion in regular sequence) */
#define ADC_REGSEQ3_REGSEQC5_0                                      (0x01UL << ADC_REGSEQ3_REGSEQC5_Pos)                           /*!< 0x00100000 */
#define ADC_REGSEQ3_REGSEQC5_1                                      (0x02UL << ADC_REGSEQ3_REGSEQC5_Pos)                           /*!< 0x00200000 */
#define ADC_REGSEQ3_REGSEQC5_2                                      (0x04UL << ADC_REGSEQ3_REGSEQC5_Pos)                           /*!< 0x00400000 */
#define ADC_REGSEQ3_REGSEQC5_3                                      (0x08UL << ADC_REGSEQ3_REGSEQC5_Pos)                           /*!< 0x00800000 */
#define ADC_REGSEQ3_REGSEQC5_4                                      (0x10UL << ADC_REGSEQ3_REGSEQC5_Pos)                           /*!< 0x01000000 */
#define ADC_REGSEQ3_REGSEQC6_Pos                                    (25U)
#define ADC_REGSEQ3_REGSEQC6_Msk                                    (0x1FUL << ADC_REGSEQ3_REGSEQC6_Pos)                           /*!< 0x3E000000 */
#define ADC_REGSEQ3_REGSEQC6                                        ADC_REGSEQ3_REGSEQC6_Msk                                       /*!<SQ6[4:0] bits (6th conversion in regular sequence) */
#define ADC_REGSEQ3_REGSEQC6_0                                      (0x01UL << ADC_REGSEQ3_REGSEQC6_Pos)                           /*!< 0x02000000 */
#define ADC_REGSEQ3_REGSEQC6_1                                      (0x02UL << ADC_REGSEQ3_REGSEQC6_Pos)                           /*!< 0x04000000 */
#define ADC_REGSEQ3_REGSEQC6_2                                      (0x04UL << ADC_REGSEQ3_REGSEQC6_Pos)                           /*!< 0x08000000 */
#define ADC_REGSEQ3_REGSEQC6_3                                      (0x08UL << ADC_REGSEQ3_REGSEQC6_Pos)                           /*!< 0x10000000 */
#define ADC_REGSEQ3_REGSEQC6_4                                      (0x10UL << ADC_REGSEQ3_REGSEQC6_Pos)                           /*!< 0x20000000 */

/*******************  Bit definition for ADC_INJSEQ register  *******************/
#define ADC_INJSEQ_INJSEQC1_Pos                                     (0U)
#define ADC_INJSEQ_INJSEQC1_Msk                                     (0x1FUL << ADC_INJSEQ_INJSEQC1_Pos)                            /*!< 0x0000001F */
#define ADC_INJSEQ_INJSEQC1                                         ADC_INJSEQ_INJSEQC1_Msk                                        /*!<JSQ1[4:0] bits (1st conversion in injected sequence) */
#define ADC_INJSEQ_INJSEQC1_0                                       (0x01UL << ADC_INJSEQ_INJSEQC1_Pos)                            /*!< 0x00000001 */
#define ADC_INJSEQ_INJSEQC1_1                                       (0x02UL << ADC_INJSEQ_INJSEQC1_Pos)                            /*!< 0x00000002 */
#define ADC_INJSEQ_INJSEQC1_2                                       (0x04UL << ADC_INJSEQ_INJSEQC1_Pos)                            /*!< 0x00000004 */
#define ADC_INJSEQ_INJSEQC1_3                                       (0x08UL << ADC_INJSEQ_INJSEQC1_Pos)                            /*!< 0x00000008 */
#define ADC_INJSEQ_INJSEQC1_4                                       (0x10UL << ADC_INJSEQ_INJSEQC1_Pos)                            /*!< 0x00000010 */
#define ADC_INJSEQ_INJSEQC2_Pos                                     (5U)
#define ADC_INJSEQ_INJSEQC2_Msk                                     (0x1FUL << ADC_INJSEQ_INJSEQC2_Pos)                            /*!< 0x000003E0 */
#define ADC_INJSEQ_INJSEQC2                                         ADC_INJSEQ_INJSEQC2_Msk                                        /*!<JSQ2[4:0] bits (2nd conversion in injected sequence) */
#define ADC_INJSEQ_INJSEQC2_0                                       (0x01UL << ADC_INJSEQ_INJSEQC2_Pos)                            /*!< 0x00000020 */
#define ADC_INJSEQ_INJSEQC2_1                                       (0x02UL << ADC_INJSEQ_INJSEQC2_Pos)                            /*!< 0x00000040 */
#define ADC_INJSEQ_INJSEQC2_2                                       (0x04UL << ADC_INJSEQ_INJSEQC2_Pos)                            /*!< 0x00000080 */
#define ADC_INJSEQ_INJSEQC2_3                                       (0x08UL << ADC_INJSEQ_INJSEQC2_Pos)                            /*!< 0x00000100 */
#define ADC_INJSEQ_INJSEQC2_4                                       (0x10UL << ADC_INJSEQ_INJSEQC2_Pos)                            /*!< 0x00000200 */
#define ADC_INJSEQ_INJSEQC3_Pos                                     (10U)
#define ADC_INJSEQ_INJSEQC3_Msk                                     (0x1FUL << ADC_INJSEQ_INJSEQC3_Pos)                            /*!< 0x00007C00 */
#define ADC_INJSEQ_INJSEQC3                                         ADC_INJSEQ_INJSEQC3_Msk                                        /*!<JSQ3[4:0] bits (3rd conversion in injected sequence) */
#define ADC_INJSEQ_INJSEQC3_0                                       (0x01UL << ADC_INJSEQ_INJSEQC3_Pos)                            /*!< 0x00000400 */
#define ADC_INJSEQ_INJSEQC3_1                                       (0x02UL << ADC_INJSEQ_INJSEQC3_Pos)                            /*!< 0x00000800 */
#define ADC_INJSEQ_INJSEQC3_2                                       (0x04UL << ADC_INJSEQ_INJSEQC3_Pos)                            /*!< 0x00001000 */
#define ADC_INJSEQ_INJSEQC3_3                                       (0x08UL << ADC_INJSEQ_INJSEQC3_Pos)                            /*!< 0x00002000 */
#define ADC_INJSEQ_INJSEQC3_4                                       (0x10UL << ADC_INJSEQ_INJSEQC3_Pos)                            /*!< 0x00004000 */
#define ADC_INJSEQ_INJSEQC4_Pos                                     (15U)
#define ADC_INJSEQ_INJSEQC4_Msk                                     (0x1FUL << ADC_INJSEQ_INJSEQC4_Pos)                            /*!< 0x000F8000 */
#define ADC_INJSEQ_INJSEQC4                                         ADC_INJSEQ_INJSEQC4_Msk                                        /*!<JSQ4[4:0] bits (4th conversion in injected sequence) */
#define ADC_INJSEQ_INJSEQC4_0                                       (0x01UL << ADC_INJSEQ_INJSEQC4_Pos)                            /*!< 0x00008000 */
#define ADC_INJSEQ_INJSEQC4_1                                       (0x02UL << ADC_INJSEQ_INJSEQC4_Pos)                            /*!< 0x00010000 */
#define ADC_INJSEQ_INJSEQC4_2                                       (0x04UL << ADC_INJSEQ_INJSEQC4_Pos)                            /*!< 0x00020000 */
#define ADC_INJSEQ_INJSEQC4_3                                       (0x08UL << ADC_INJSEQ_INJSEQC4_Pos)                            /*!< 0x00040000 */
#define ADC_INJSEQ_INJSEQC4_4                                       (0x10UL << ADC_INJSEQ_INJSEQC4_Pos)                            /*!< 0x00080000 */
#define ADC_INJSEQ_INJSEQLEN_Pos                                    (20U)
#define ADC_INJSEQ_INJSEQLEN_Msk                                    (0x3UL << ADC_INJSEQ_INJSEQLEN_Pos)                            /*!< 0x00300000 */
#define ADC_INJSEQ_INJSEQLEN                                        ADC_INJSEQ_INJSEQLEN_Msk                                       /*!<JL[1:0] bits (Injected Sequence length) */
#define ADC_INJSEQ_INJSEQLEN_0                                      (0x1UL << ADC_INJSEQ_INJSEQLEN_Pos)                            /*!< 0x00100000 */
#define ADC_INJSEQ_INJSEQLEN_1                                      (0x2UL << ADC_INJSEQ_INJSEQLEN_Pos)                            /*!< 0x00200000 */

/*******************  Bit definition for ADC_INJDATA1 register  *******************/
#define ADC_INJDATA1_INJDATA_Pos                                    (0U)
#define ADC_INJDATA1_INJDATA_Msk                                    (0xFFFFUL << ADC_INJDATA1_INJDATA_Pos)                         /*!< 0x0000FFFF */
#define ADC_INJDATA1_INJDATA                                        ADC_INJDATA1_INJDATA_Msk                                       /*!<Injected data */

/*******************  Bit definition for ADC_INJDATA2 register  *******************/
#define ADC_INJDATA2_INJDATA_Pos                                    (0U)
#define ADC_INJDATA2_INJDATA_Msk                                    (0xFFFFUL << ADC_INJDATA2_INJDATA_Pos)                         /*!< 0x0000FFFF */
#define ADC_INJDATA2_INJDATA                                        ADC_INJDATA2_INJDATA_Msk                                       /*!<Injected data */

/*******************  Bit definition for ADC_INJDATA3 register  *******************/
#define ADC_INJDATA3_INJDATA_Pos                                    (0U)
#define ADC_INJDATA3_INJDATA_Msk                                    (0xFFFFUL << ADC_INJDATA3_INJDATA_Pos)                         /*!< 0x0000FFFF */
#define ADC_INJDATA3_INJDATA                                        ADC_INJDATA3_INJDATA_Msk                                       /*!<Injected data */

/*******************  Bit definition for ADC_INJDATA4 register  *******************/
#define ADC_INJDATA4_INJDATA_Pos                                    (0U)
#define ADC_INJDATA4_INJDATA_Msk                                    (0xFFFFUL << ADC_INJDATA4_INJDATA_Pos)                         /*!< 0x0000FFFF */
#define ADC_INJDATA4_INJDATA                                        ADC_INJDATA4_INJDATA_Msk                                       /*!<Injected data */

/********************  Bit definition for ADC_REGDATA register  ********************/
#define ADC_REGDATA_REGDATA_Pos                                     (0U)
#define ADC_REGDATA_REGDATA_Msk                                     (0xFFFFUL << ADC_REGDATA_REGDATA_Pos)                          /*!< 0x0000FFFF */
#define ADC_REGDATA_REGDATA                                         ADC_REGDATA_REGDATA_Msk                                        /*!<Regular data */
#define ADC_REGDATA_ADC2DATA_Pos                                    (16U)
#define ADC_REGDATA_ADC2DATA_Msk                                    (0xFFFFUL << ADC_REGDATA_ADC2DATA_Pos)                         /*!< 0xFFFF0000 */
#define ADC_REGDATA_ADC2DATA                                        ADC_REGDATA_ADC2DATA_Msk                                       /*!<ADC2 data */

/*******************  Bit definition for ADC_CSTS register  ********************/
#define ADC_CSTS_AWDFLG1_Pos                                        (0U)
#define ADC_CSTS_AWDFLG1_Msk                                        (0x1UL << ADC_CSTS_AWDFLG1_Pos)                                /*!< 0x00000001 */
#define ADC_CSTS_AWDFLG1                                            ADC_CSTS_AWDFLG1_Msk                                           /*!<ADC1 Analog watchdog flag */
#define ADC_CSTS_EOCFLG1_Pos                                        (1U)
#define ADC_CSTS_EOCFLG1_Msk                                        (0x1UL << ADC_CSTS_EOCFLG1_Pos)                                /*!< 0x00000002 */
#define ADC_CSTS_EOCFLG1                                            ADC_CSTS_EOCFLG1_Msk                                           /*!<ADC1 End of conversion */
#define ADC_CSTS_INJEOCFLG1_Pos                                     (2U)
#define ADC_CSTS_INJEOCFLG1_Msk                                     (0x1UL << ADC_CSTS_INJEOCFLG1_Pos)                             /*!< 0x00000004 */
#define ADC_CSTS_INJEOCFLG1                                         ADC_CSTS_INJEOCFLG1_Msk                                        /*!<ADC1 Injected channel end of conversion */
#define ADC_CSTS_INJCSFLG1_Pos                                      (3U)
#define ADC_CSTS_INJCSFLG1_Msk                                      (0x1UL << ADC_CSTS_INJCSFLG1_Pos)                              /*!< 0x00000008 */
#define ADC_CSTS_INJCSFLG1                                          ADC_CSTS_INJCSFLG1_Msk                                         /*!<ADC1 Injected channel Start flag */
#define ADC_CSTS_REGCSFLG1_Pos                                      (4U)
#define ADC_CSTS_REGCSFLG1_Msk                                      (0x1UL << ADC_CSTS_REGCSFLG1_Pos)                              /*!< 0x00000010 */
#define ADC_CSTS_REGCSFLG1                                          ADC_CSTS_REGCSFLG1_Msk                                         /*!<ADC1 Regular channel Start flag */
#define ADC_CSTS_OVRFLG1_Pos                                        (5U)
#define ADC_CSTS_OVRFLG1_Msk                                        (0x1UL << ADC_CSTS_OVRFLG1_Pos)                                /*!< 0x00000020 */
#define ADC_CSTS_OVRFLG1                                            ADC_CSTS_OVRFLG1_Msk                                           /*!<ADC1 DMA overrun  flag */
#define ADC_CSTS_AWDFLG2_Pos                                        (8U)
#define ADC_CSTS_AWDFLG2_Msk                                        (0x1UL << ADC_CSTS_AWDFLG2_Pos)                                /*!< 0x00000100 */
#define ADC_CSTS_AWDFLG2                                            ADC_CSTS_AWDFLG2_Msk                                           /*!<ADC2 Analog watchdog flag */
#define ADC_CSTS_EOCFLG2_Pos                                        (9U)
#define ADC_CSTS_EOCFLG2_Msk                                        (0x1UL << ADC_CSTS_EOCFLG2_Pos)                                /*!< 0x00000200 */
#define ADC_CSTS_EOCFLG2                                            ADC_CSTS_EOCFLG2_Msk                                           /*!<ADC2 End of conversion */
#define ADC_CSTS_INJEOCFLG2_Pos                                     (10U)
#define ADC_CSTS_INJEOCFLG2_Msk                                     (0x1UL << ADC_CSTS_INJEOCFLG2_Pos)                             /*!< 0x00000400 */
#define ADC_CSTS_INJEOCFLG2                                         ADC_CSTS_INJEOCFLG2_Msk                                        /*!<ADC2 Injected channel end of conversion */
#define ADC_CSTS_INJCSFLG2_Pos                                      (11U)
#define ADC_CSTS_INJCSFLG2_Msk                                      (0x1UL << ADC_CSTS_INJCSFLG2_Pos)                              /*!< 0x00000800 */
#define ADC_CSTS_INJCSFLG2                                          ADC_CSTS_INJCSFLG2_Msk                                         /*!<ADC2 Injected channel Start flag */
#define ADC_CSTS_REGCSFLG2_Pos                                      (12U)
#define ADC_CSTS_REGCSFLG2_Msk                                      (0x1UL << ADC_CSTS_REGCSFLG2_Pos)                              /*!< 0x00001000 */
#define ADC_CSTS_REGCSFLG2                                          ADC_CSTS_REGCSFLG2_Msk                                         /*!<ADC2 Regular channel Start flag */
#define ADC_CSTS_OVRFLG2_Pos                                        (13U)
#define ADC_CSTS_OVRFLG2_Msk                                        (0x1UL << ADC_CSTS_OVRFLG2_Pos)                                /*!< 0x00002000 */
#define ADC_CSTS_OVRFLG2                                            ADC_CSTS_OVRFLG2_Msk                                           /*!<ADC2 DMA overrun  flag */
#define ADC_CSTS_AWDFLG3_Pos                                        (16U)
#define ADC_CSTS_AWDFLG3_Msk                                        (0x1UL << ADC_CSTS_AWDFLG3_Pos)                                /*!< 0x00010000 */
#define ADC_CSTS_AWDFLG3                                            ADC_CSTS_AWDFLG3_Msk                                           /*!<ADC3 Analog watchdog flag */
#define ADC_CSTS_EOCFLG3_Pos                                        (17U)
#define ADC_CSTS_EOCFLG3_Msk                                        (0x1UL << ADC_CSTS_EOCFLG3_Pos)                                /*!< 0x00020000 */
#define ADC_CSTS_EOCFLG3                                            ADC_CSTS_EOCFLG3_Msk                                           /*!<ADC3 End of conversion */
#define ADC_CSTS_INJEOCFLG3_Pos                                     (18U)
#define ADC_CSTS_INJEOCFLG3_Msk                                     (0x1UL << ADC_CSTS_INJEOCFLG3_Pos)                             /*!< 0x00040000 */
#define ADC_CSTS_INJEOCFLG3                                         ADC_CSTS_INJEOCFLG3_Msk                                        /*!<ADC3 Injected channel end of conversion */
#define ADC_CSTS_INJCSFLG3_Pos                                      (19U)
#define ADC_CSTS_INJCSFLG3_Msk                                      (0x1UL << ADC_CSTS_INJCSFLG3_Pos)                              /*!< 0x00080000 */
#define ADC_CSTS_INJCSFLG3                                          ADC_CSTS_INJCSFLG3_Msk                                         /*!<ADC3 Injected channel Start flag */
#define ADC_CSTS_REGCSFLG3_Pos                                      (20U)
#define ADC_CSTS_REGCSFLG3_Msk                                      (0x1UL << ADC_CSTS_REGCSFLG3_Pos)                              /*!< 0x00100000 */
#define ADC_CSTS_REGCSFLG3                                          ADC_CSTS_REGCSFLG3_Msk                                         /*!<ADC3 Regular channel Start flag */
#define ADC_CSTS_OVRFLG3_Pos                                        (21U)
#define ADC_CSTS_OVRFLG3_Msk                                        (0x1UL << ADC_CSTS_OVRFLG3_Pos)                                /*!< 0x00200000 */
#define ADC_CSTS_OVRFLG3                                            ADC_CSTS_OVRFLG3_Msk                                           /*!<ADC3 DMA overrun  flag */

/* Legacy defines */
#define ADC_CSTS_DOVR1                                              ADC_CSTS_OVRFLG1
#define ADC_CSTS_DOVR2                                              ADC_CSTS_OVRFLG2
#define ADC_CSTS_DOVR3                                              ADC_CSTS_OVRFLG3

/*******************  Bit definition for ADC_CCTRL register  ********************/
#define ADC_CCTRL_ADCMSEL_Pos                                       (0U)
#define ADC_CCTRL_ADCMSEL_Msk                                       (0x1FUL << ADC_CCTRL_ADCMSEL_Pos)                              /*!< 0x0000001F */
#define ADC_CCTRL_ADCMSEL                                           ADC_CCTRL_ADCMSEL_Msk                                          /*!<MULTI[4:0] bits (Multi-ADC mode selection) */
#define ADC_CCTRL_ADCMSEL_0                                         (0x01UL << ADC_CCTRL_ADCMSEL_Pos)                              /*!< 0x00000001 */
#define ADC_CCTRL_ADCMSEL_1                                         (0x02UL << ADC_CCTRL_ADCMSEL_Pos)                              /*!< 0x00000002 */
#define ADC_CCTRL_ADCMSEL_2                                         (0x04UL << ADC_CCTRL_ADCMSEL_Pos)                              /*!< 0x00000004 */
#define ADC_CCTRL_ADCMSEL_3                                         (0x08UL << ADC_CCTRL_ADCMSEL_Pos)                              /*!< 0x00000008 */
#define ADC_CCTRL_ADCMSEL_4                                         (0x10UL << ADC_CCTRL_ADCMSEL_Pos)                              /*!< 0x00000010 */
#define ADC_CCTRL_SMPDEL2_Pos                                       (8U)
#define ADC_CCTRL_SMPDEL2_Msk                                       (0xFUL << ADC_CCTRL_SMPDEL2_Pos)                               /*!< 0x00000F00 */
#define ADC_CCTRL_SMPDEL2                                           ADC_CCTRL_SMPDEL2_Msk                                          /*!<DELAY[3:0] bits (Delay between 2 sampling phases) */
#define ADC_CCTRL_SMPDEL2_0                                         (0x1UL << ADC_CCTRL_SMPDEL2_Pos)                               /*!< 0x00000100 */
#define ADC_CCTRL_SMPDEL2_1                                         (0x2UL << ADC_CCTRL_SMPDEL2_Pos)                               /*!< 0x00000200 */
#define ADC_CCTRL_SMPDEL2_2                                         (0x4UL << ADC_CCTRL_SMPDEL2_Pos)                               /*!< 0x00000400 */
#define ADC_CCTRL_SMPDEL2_3                                         (0x8UL << ADC_CCTRL_SMPDEL2_Pos)                               /*!< 0x00000800 */
#define ADC_CCTRL_DMAMODEDISSEL_Pos                                 (13U)
#define ADC_CCTRL_DMAMODEDISSEL_Msk                                 (0x1UL << ADC_CCTRL_DMAMODEDISSEL_Pos)                         /*!< 0x00002000 */
#define ADC_CCTRL_DMAMODEDISSEL                                     ADC_CCTRL_DMAMODEDISSEL_Msk                                    /*!<DMA disable selection (Multi-ADC mode) */
#define ADC_CCTRL_DMAMODE_Pos                                       (14U)
#define ADC_CCTRL_DMAMODE_Msk                                       (0x3UL << ADC_CCTRL_DMAMODE_Pos)                               /*!< 0x0000C000 */
#define ADC_CCTRL_DMAMODE                                           ADC_CCTRL_DMAMODE_Msk                                          /*!<DMA[1:0] bits (Direct Memory Access mode for multimode) */
#define ADC_CCTRL_DMAMODE_0                                         (0x1UL << ADC_CCTRL_DMAMODE_Pos)                               /*!< 0x00004000 */
#define ADC_CCTRL_DMAMODE_1                                         (0x2UL << ADC_CCTRL_DMAMODE_Pos)                               /*!< 0x00008000 */
#define ADC_CCTRL_ADCPRE_Pos                                        (16U)
#define ADC_CCTRL_ADCPRE_Msk                                        (0x3UL << ADC_CCTRL_ADCPRE_Pos)                                /*!< 0x00030000 */
#define ADC_CCTRL_ADCPRE                                            ADC_CCTRL_ADCPRE_Msk                                           /*!<ADCPRE[1:0] bits (ADC prescaler) */
#define ADC_CCTRL_ADCPRE_0                                          (0x1UL << ADC_CCTRL_ADCPRE_Pos)                                /*!< 0x00010000 */
#define ADC_CCTRL_ADCPRE_1                                          (0x2UL << ADC_CCTRL_ADCPRE_Pos)                                /*!< 0x00020000 */
#define ADC_CCTRL_VBATEN_Pos                                        (22U)
#define ADC_CCTRL_VBATEN_Msk                                        (0x1UL << ADC_CCTRL_VBATEN_Pos)                                /*!< 0x00400000 */
#define ADC_CCTRL_VBATEN                                            ADC_CCTRL_VBATEN_Msk                                           /*!<VBAT Enable */
#define ADC_CCTRL_TSVREFEN_Pos                                      (23U)
#define ADC_CCTRL_TSVREFEN_Msk                                      (0x1UL << ADC_CCTRL_TSVREFEN_Pos)                              /*!< 0x00800000 */
#define ADC_CCTRL_TSVREFEN                                          ADC_CCTRL_TSVREFEN_Msk                                         /*!<Temperature Sensor and VREFINT Enable */

/*******************  Bit definition for ADC_CDATA register  ********************/
#define ADC_CDATA_DATA1_Pos                                         (0U)
#define ADC_CDATA_DATA1_Msk                                         (0xFFFFUL << ADC_CDATA_DATA1_Pos)                              /*!< 0x0000FFFF */
#define ADC_CDATA_DATA1                                             ADC_CDATA_DATA1_Msk                                            /*!<1st data of a pair of regular conversions */
#define ADC_CDATA_DATA2_Pos                                         (16U)
#define ADC_CDATA_DATA2_Msk                                         (0xFFFFUL << ADC_CDATA_DATA2_Pos)                              /*!< 0xFFFF0000 */
#define ADC_CDATA_DATA2                                             ADC_CDATA_DATA2_Msk                                            /*!<2nd data of a pair of regular conversions */

/* Legacy defines */
#define ADC_CDATA_RDATA_MST                                         ADC_CDATA_DATA1
#define ADC_CDATA_RDATA_SLV                                         ADC_CDATA_DATA2

/******************************************************************************/
/*                                                                            */
/*                         Controller Area Network                            */
/*                                                                            */
/******************************************************************************/
/*!<CAN control and status registers */
/*******************  Bit definition for CAN_MCTRL register  ********************/
#define CAN_MCTRL_INITREQ_Pos                                       (0U)
#define CAN_MCTRL_INITREQ_Msk                                       (0x1UL << CAN_MCTRL_INITREQ_Pos)                               /*!< 0x00000001 */
#define CAN_MCTRL_INITREQ                                           CAN_MCTRL_INITREQ_Msk                                          /*!<Initialization Request */
#define CAN_MCTRL_SLEEPREQ_Pos                                      (1U)
#define CAN_MCTRL_SLEEPREQ_Msk                                      (0x1UL << CAN_MCTRL_SLEEPREQ_Pos)                              /*!< 0x00000002 */
#define CAN_MCTRL_SLEEPREQ                                          CAN_MCTRL_SLEEPREQ_Msk                                         /*!<Sleep Mode Request */
#define CAN_MCTRL_TXFPCFG_Pos                                       (2U)
#define CAN_MCTRL_TXFPCFG_Msk                                       (0x1UL << CAN_MCTRL_TXFPCFG_Pos)                               /*!< 0x00000004 */
#define CAN_MCTRL_TXFPCFG                                           CAN_MCTRL_TXFPCFG_Msk                                          /*!<Transmit FIFO Priority */
#define CAN_MCTRL_RXFLOCK_Pos                                       (3U)
#define CAN_MCTRL_RXFLOCK_Msk                                       (0x1UL << CAN_MCTRL_RXFLOCK_Pos)                               /*!< 0x00000008 */
#define CAN_MCTRL_RXFLOCK                                           CAN_MCTRL_RXFLOCK_Msk                                          /*!<Receive FIFO Locked Mode */
#define CAN_MCTRL_ARTXMD_Pos                                        (4U)
#define CAN_MCTRL_ARTXMD_Msk                                        (0x1UL << CAN_MCTRL_ARTXMD_Pos)                                /*!< 0x00000010 */
#define CAN_MCTRL_ARTXMD                                            CAN_MCTRL_ARTXMD_Msk                                           /*!<No Automatic Retransmission */
#define CAN_MCTRL_AWUPCFG_Pos                                       (5U)
#define CAN_MCTRL_AWUPCFG_Msk                                       (0x1UL << CAN_MCTRL_AWUPCFG_Pos)                               /*!< 0x00000020 */
#define CAN_MCTRL_AWUPCFG                                           CAN_MCTRL_AWUPCFG_Msk                                          /*!<Automatic Wakeup Mode */
#define CAN_MCTRL_ALBOFFM_Pos                                       (6U)
#define CAN_MCTRL_ALBOFFM_Msk                                       (0x1UL << CAN_MCTRL_ALBOFFM_Pos)                               /*!< 0x00000040 */
#define CAN_MCTRL_ALBOFFM                                           CAN_MCTRL_ALBOFFM_Msk                                          /*!<Automatic Bus-Off Management */
#define CAN_MCTRL_TTCM_Pos                                          (7U)
#define CAN_MCTRL_TTCM_Msk                                          (0x1UL << CAN_MCTRL_TTCM_Pos)                                  /*!< 0x00000080 */
#define CAN_MCTRL_TTCM                                              CAN_MCTRL_TTCM_Msk                                             /*!<Time Triggered Communication Mode */
#define CAN_MCTRL_SWRST_Pos                                         (15U)
#define CAN_MCTRL_SWRST_Msk                                         (0x1UL << CAN_MCTRL_SWRST_Pos)                                 /*!< 0x00008000 */
#define CAN_MCTRL_SWRST                                             CAN_MCTRL_SWRST_Msk                                            /*!<bxCAN software master reset */
#define CAN_MCTRL_DBGFRZE_Pos                                       (16U)
#define CAN_MCTRL_DBGFRZE_Msk                                       (0x1UL << CAN_MCTRL_DBGFRZE_Pos)                               /*!< 0x00010000 */
#define CAN_MCTRL_DBGFRZE                                           CAN_MCTRL_DBGFRZE_Msk                                          /*!<bxCAN Debug freeze */
/*******************  Bit definition for CAN_MSTS register  ********************/
#define CAN_MSTS_INITFLG_Pos                                        (0U)
#define CAN_MSTS_INITFLG_Msk                                        (0x1UL << CAN_MSTS_INITFLG_Pos)                                /*!< 0x00000001 */
#define CAN_MSTS_INITFLG                                            CAN_MSTS_INITFLG_Msk                                           /*!<Initialization Acknowledge */
#define CAN_MSTS_SLEEPFLG_Pos                                       (1U)
#define CAN_MSTS_SLEEPFLG_Msk                                       (0x1UL << CAN_MSTS_SLEEPFLG_Pos)                               /*!< 0x00000002 */
#define CAN_MSTS_SLEEPFLG                                           CAN_MSTS_SLEEPFLG_Msk                                          /*!<Sleep Acknowledge */
#define CAN_MSTS_ERRIFLG_Pos                                        (2U)
#define CAN_MSTS_ERRIFLG_Msk                                        (0x1UL << CAN_MSTS_ERRIFLG_Pos)                                /*!< 0x00000004 */
#define CAN_MSTS_ERRIFLG                                            CAN_MSTS_ERRIFLG_Msk                                           /*!<Error Interrupt */
#define CAN_MSTS_WUPIFLG_Pos                                        (3U)
#define CAN_MSTS_WUPIFLG_Msk                                        (0x1UL << CAN_MSTS_WUPIFLG_Pos)                                /*!< 0x00000008 */
#define CAN_MSTS_WUPIFLG                                            CAN_MSTS_WUPIFLG_Msk                                           /*!<Wakeup Interrupt */
#define CAN_MSTS_SLEEPIFLG_Pos                                      (4U)
#define CAN_MSTS_SLEEPIFLG_Msk                                      (0x1UL << CAN_MSTS_SLEEPIFLG_Pos)                              /*!< 0x00000010 */
#define CAN_MSTS_SLEEPIFLG                                          CAN_MSTS_SLEEPIFLG_Msk                                         /*!<Sleep Acknowledge Interrupt */
#define CAN_MSTS_TXMFLG_Pos                                         (8U)
#define CAN_MSTS_TXMFLG_Msk                                         (0x1UL << CAN_MSTS_TXMFLG_Pos)                                 /*!< 0x00000100 */
#define CAN_MSTS_TXMFLG                                             CAN_MSTS_TXMFLG_Msk                                            /*!<Transmit Mode */
#define CAN_MSTS_RXSIGLMFLG_Pos                                     (9U)
#define CAN_MSTS_RXSIGLMFLG_Msk                                     (0x1UL << CAN_MSTS_RXSIGLMFLG_Pos)                             /*!< 0x00000200 */
#define CAN_MSTS_RXSIGLMFLG                                         CAN_MSTS_RXSIGLMFLG_Msk                                        /*!<Receive Mode */
#define CAN_MSTS_LSAMVALUE_Pos                                      (10U)
#define CAN_MSTS_LSAMVALUE_Msk                                      (0x1UL << CAN_MSTS_LSAMVALUE_Pos)                              /*!< 0x00000400 */
#define CAN_MSTS_LSAMVALUE                                          CAN_MSTS_LSAMVALUE_Msk                                         /*!<Last Sample Point */
#define CAN_MSTS_RXSIGL_Pos                                         (11U)
#define CAN_MSTS_RXSIGL_Msk                                         (0x1UL << CAN_MSTS_RXSIGL_Pos)                                 /*!< 0x00000800 */
#define CAN_MSTS_RXSIGL                                             CAN_MSTS_RXSIGL_Msk                                            /*!<CAN Rx Signal */

/*******************  Bit definition for CAN_TXSTS register  ********************/
#define CAN_TXSTS_REQCFLG0_Pos                                      (0U)
#define CAN_TXSTS_REQCFLG0_Msk                                      (0x1UL << CAN_TXSTS_REQCFLG0_Pos)                              /*!< 0x00000001 */
#define CAN_TXSTS_REQCFLG0                                          CAN_TXSTS_REQCFLG0_Msk                                         /*!<Request Completed Mailbox0 */
#define CAN_TXSTS_TXSUSFLG0_Pos                                     (1U)
#define CAN_TXSTS_TXSUSFLG0_Msk                                     (0x1UL << CAN_TXSTS_TXSUSFLG0_Pos)                             /*!< 0x00000002 */
#define CAN_TXSTS_TXSUSFLG0                                         CAN_TXSTS_TXSUSFLG0_Msk                                        /*!<Transmission OK of Mailbox0 */
#define CAN_TXSTS_ARBLSTFLG0_Pos                                    (2U)
#define CAN_TXSTS_ARBLSTFLG0_Msk                                    (0x1UL << CAN_TXSTS_ARBLSTFLG0_Pos)                            /*!< 0x00000004 */
#define CAN_TXSTS_ARBLSTFLG0                                        CAN_TXSTS_ARBLSTFLG0_Msk                                       /*!<Arbitration Lost for Mailbox0 */
#define CAN_TXSTS_TXERRFLG0_Pos                                     (3U)
#define CAN_TXSTS_TXERRFLG0_Msk                                     (0x1UL << CAN_TXSTS_TXERRFLG0_Pos)                             /*!< 0x00000008 */
#define CAN_TXSTS_TXERRFLG0                                         CAN_TXSTS_TXERRFLG0_Msk                                        /*!<Transmission Error of Mailbox0 */
#define CAN_TXSTS_ABREQFLG0_Pos                                     (7U)
#define CAN_TXSTS_ABREQFLG0_Msk                                     (0x1UL << CAN_TXSTS_ABREQFLG0_Pos)                             /*!< 0x00000080 */
#define CAN_TXSTS_ABREQFLG0                                         CAN_TXSTS_ABREQFLG0_Msk                                        /*!<Abort Request for Mailbox0 */
#define CAN_TXSTS_REQCFLG1_Pos                                      (8U)
#define CAN_TXSTS_REQCFLG1_Msk                                      (0x1UL << CAN_TXSTS_REQCFLG1_Pos)                              /*!< 0x00000100 */
#define CAN_TXSTS_REQCFLG1                                          CAN_TXSTS_REQCFLG1_Msk                                         /*!<Request Completed Mailbox1 */
#define CAN_TXSTS_TXSUSFLG1_Pos                                     (9U)
#define CAN_TXSTS_TXSUSFLG1_Msk                                     (0x1UL << CAN_TXSTS_TXSUSFLG1_Pos)                             /*!< 0x00000200 */
#define CAN_TXSTS_TXSUSFLG1                                         CAN_TXSTS_TXSUSFLG1_Msk                                        /*!<Transmission OK of Mailbox1 */
#define CAN_TXSTS_ARBLSTFLG1_Pos                                    (10U)
#define CAN_TXSTS_ARBLSTFLG1_Msk                                    (0x1UL << CAN_TXSTS_ARBLSTFLG1_Pos)                            /*!< 0x00000400 */
#define CAN_TXSTS_ARBLSTFLG1                                        CAN_TXSTS_ARBLSTFLG1_Msk                                       /*!<Arbitration Lost for Mailbox1 */
#define CAN_TXSTS_TXERRFLG1_Pos                                     (11U)
#define CAN_TXSTS_TXERRFLG1_Msk                                     (0x1UL << CAN_TXSTS_TXERRFLG1_Pos)                             /*!< 0x00000800 */
#define CAN_TXSTS_TXERRFLG1                                         CAN_TXSTS_TXERRFLG1_Msk                                        /*!<Transmission Error of Mailbox1 */
#define CAN_TXSTS_ABREQFLG1_Pos                                     (15U)
#define CAN_TXSTS_ABREQFLG1_Msk                                     (0x1UL << CAN_TXSTS_ABREQFLG1_Pos)                             /*!< 0x00008000 */
#define CAN_TXSTS_ABREQFLG1                                         CAN_TXSTS_ABREQFLG1_Msk                                        /*!<Abort Request for Mailbox 1 */
#define CAN_TXSTS_REQCFLG2_Pos                                      (16U)
#define CAN_TXSTS_REQCFLG2_Msk                                      (0x1UL << CAN_TXSTS_REQCFLG2_Pos)                              /*!< 0x00010000 */
#define CAN_TXSTS_REQCFLG2                                          CAN_TXSTS_REQCFLG2_Msk                                         /*!<Request Completed Mailbox2 */
#define CAN_TXSTS_TXSUSFLG2_Pos                                     (17U)
#define CAN_TXSTS_TXSUSFLG2_Msk                                     (0x1UL << CAN_TXSTS_TXSUSFLG2_Pos)                             /*!< 0x00020000 */
#define CAN_TXSTS_TXSUSFLG2                                         CAN_TXSTS_TXSUSFLG2_Msk                                        /*!<Transmission OK of Mailbox 2 */
#define CAN_TXSTS_ARBLSTFLG2_Pos                                    (18U)
#define CAN_TXSTS_ARBLSTFLG2_Msk                                    (0x1UL << CAN_TXSTS_ARBLSTFLG2_Pos)                            /*!< 0x00040000 */
#define CAN_TXSTS_ARBLSTFLG2                                        CAN_TXSTS_ARBLSTFLG2_Msk                                       /*!<Arbitration Lost for mailbox 2 */
#define CAN_TXSTS_TXERRFLG2_Pos                                     (19U)
#define CAN_TXSTS_TXERRFLG2_Msk                                     (0x1UL << CAN_TXSTS_TXERRFLG2_Pos)                             /*!< 0x00080000 */
#define CAN_TXSTS_TXERRFLG2                                         CAN_TXSTS_TXERRFLG2_Msk                                        /*!<Transmission Error of Mailbox 2 */
#define CAN_TXSTS_ABREQFLG2_Pos                                     (23U)
#define CAN_TXSTS_ABREQFLG2_Msk                                     (0x1UL << CAN_TXSTS_ABREQFLG2_Pos)                             /*!< 0x00800000 */
#define CAN_TXSTS_ABREQFLG2                                         CAN_TXSTS_ABREQFLG2_Msk                                        /*!<Abort Request for Mailbox 2 */
#define CAN_TXSTS_EMNUM_Pos                                         (24U)
#define CAN_TXSTS_EMNUM_Msk                                         (0x3UL << CAN_TXSTS_EMNUM_Pos)                                 /*!< 0x03000000 */
#define CAN_TXSTS_EMNUM                                             CAN_TXSTS_EMNUM_Msk                                            /*!<Mailbox Code */

#define CAN_TXSTS_TXMEFLG_Pos                                       (26U)
#define CAN_TXSTS_TXMEFLG_Msk                                       (0x7UL << CAN_TXSTS_TXMEFLG_Pos)                               /*!< 0x1C000000 */
#define CAN_TXSTS_TXMEFLG                                           CAN_TXSTS_TXMEFLG_Msk                                          /*!<TME[2:0] bits */
#define CAN_TXSTS_TXMEFLG0_Pos                                      (26U)
#define CAN_TXSTS_TXMEFLG0_Msk                                      (0x1UL << CAN_TXSTS_TXMEFLG0_Pos)                              /*!< 0x04000000 */
#define CAN_TXSTS_TXMEFLG0                                          CAN_TXSTS_TXMEFLG0_Msk                                         /*!<Transmit Mailbox 0 Empty */
#define CAN_TXSTS_TXMEFLG1_Pos                                      (27U)
#define CAN_TXSTS_TXMEFLG1_Msk                                      (0x1UL << CAN_TXSTS_TXMEFLG1_Pos)                              /*!< 0x08000000 */
#define CAN_TXSTS_TXMEFLG1                                          CAN_TXSTS_TXMEFLG1_Msk                                         /*!<Transmit Mailbox 1 Empty */
#define CAN_TXSTS_TXMEFLG2_Pos                                      (28U)
#define CAN_TXSTS_TXMEFLG2_Msk                                      (0x1UL << CAN_TXSTS_TXMEFLG2_Pos)                              /*!< 0x10000000 */
#define CAN_TXSTS_TXMEFLG2                                          CAN_TXSTS_TXMEFLG2_Msk                                         /*!<Transmit Mailbox 2 Empty */

#define CAN_TXSTS_LOWESTP_Pos                                       (29U)
#define CAN_TXSTS_LOWESTP_Msk                                       (0x7UL << CAN_TXSTS_LOWESTP_Pos)                               /*!< 0xE0000000 */
#define CAN_TXSTS_LOWESTP                                           CAN_TXSTS_LOWESTP_Msk                                          /*!<LOW[2:0] bits */
#define CAN_TXSTS_LOWESTP0_Pos                                      (29U)
#define CAN_TXSTS_LOWESTP0_Msk                                      (0x1UL << CAN_TXSTS_LOWESTP0_Pos)                              /*!< 0x20000000 */
#define CAN_TXSTS_LOWESTP0                                          CAN_TXSTS_LOWESTP0_Msk                                         /*!<Lowest Priority Flag for Mailbox 0 */
#define CAN_TXSTS_LOWESTP1_Pos                                      (30U)
#define CAN_TXSTS_LOWESTP1_Msk                                      (0x1UL << CAN_TXSTS_LOWESTP1_Pos)                              /*!< 0x40000000 */
#define CAN_TXSTS_LOWESTP1                                          CAN_TXSTS_LOWESTP1_Msk                                         /*!<Lowest Priority Flag for Mailbox 1 */
#define CAN_TXSTS_LOWESTP2_Pos                                      (31U)
#define CAN_TXSTS_LOWESTP2_Msk                                      (0x1UL << CAN_TXSTS_LOWESTP2_Pos)                              /*!< 0x80000000 */
#define CAN_TXSTS_LOWESTP2                                          CAN_TXSTS_LOWESTP2_Msk                                         /*!<Lowest Priority Flag for Mailbox 2 */

/*******************  Bit definition for CAN_RXF0 register  *******************/
#define CAN_RXF0_FMNUM0_Pos                                         (0U)
#define CAN_RXF0_FMNUM0_Msk                                         (0x3UL << CAN_RXF0_FMNUM0_Pos)                                 /*!< 0x00000003 */
#define CAN_RXF0_FMNUM0                                             CAN_RXF0_FMNUM0_Msk                                            /*!<FIFO 0 Message Pending */
#define CAN_RXF0_FFULLFLG0_Pos                                      (3U)
#define CAN_RXF0_FFULLFLG0_Msk                                      (0x1UL << CAN_RXF0_FFULLFLG0_Pos)                              /*!< 0x00000008 */
#define CAN_RXF0_FFULLFLG0                                          CAN_RXF0_FFULLFLG0_Msk                                         /*!<FIFO 0 Full */
#define CAN_RXF0_FOVRFLG0_Pos                                       (4U)
#define CAN_RXF0_FOVRFLG0_Msk                                       (0x1UL << CAN_RXF0_FOVRFLG0_Pos)                               /*!< 0x00000010 */
#define CAN_RXF0_FOVRFLG0                                           CAN_RXF0_FOVRFLG0_Msk                                          /*!<FIFO 0 Overrun */
#define CAN_RXF0_RFOM0_Pos                                          (5U)
#define CAN_RXF0_RFOM0_Msk                                          (0x1UL << CAN_RXF0_RFOM0_Pos)                                  /*!< 0x00000020 */
#define CAN_RXF0_RFOM0                                              CAN_RXF0_RFOM0_Msk                                             /*!<Release FIFO 0 Output Mailbox */

/*******************  Bit definition for CAN_RXF1 register  *******************/
#define CAN_RXF1_FMNUM1_Pos                                         (0U)
#define CAN_RXF1_FMNUM1_Msk                                         (0x3UL << CAN_RXF1_FMNUM1_Pos)                                 /*!< 0x00000003 */
#define CAN_RXF1_FMNUM1                                             CAN_RXF1_FMNUM1_Msk                                            /*!<FIFO 1 Message Pending */
#define CAN_RXF1_FFULLFLG1_Pos                                      (3U)
#define CAN_RXF1_FFULLFLG1_Msk                                      (0x1UL << CAN_RXF1_FFULLFLG1_Pos)                              /*!< 0x00000008 */
#define CAN_RXF1_FFULLFLG1                                          CAN_RXF1_FFULLFLG1_Msk                                         /*!<FIFO 1 Full */
#define CAN_RXF1_FOVRFLG1_Pos                                       (4U)
#define CAN_RXF1_FOVRFLG1_Msk                                       (0x1UL << CAN_RXF1_FOVRFLG1_Pos)                               /*!< 0x00000010 */
#define CAN_RXF1_FOVRFLG1                                           CAN_RXF1_FOVRFLG1_Msk                                          /*!<FIFO 1 Overrun */
#define CAN_RXF1_RFOM1_Pos                                          (5U)
#define CAN_RXF1_RFOM1_Msk                                          (0x1UL << CAN_RXF1_RFOM1_Pos)                                  /*!< 0x00000020 */
#define CAN_RXF1_RFOM1                                              CAN_RXF1_RFOM1_Msk                                             /*!<Release FIFO 1 Output Mailbox */

/********************  Bit definition for CAN_INTEN register  *******************/
#define CAN_INTEN_TXMEIEN_Pos                                       (0U)
#define CAN_INTEN_TXMEIEN_Msk                                       (0x1UL << CAN_INTEN_TXMEIEN_Pos)                               /*!< 0x00000001 */
#define CAN_INTEN_TXMEIEN                                           CAN_INTEN_TXMEIEN_Msk                                          /*!<Transmit Mailbox Empty Interrupt Enable */
#define CAN_INTEN_FMIEN0_Pos                                        (1U)
#define CAN_INTEN_FMIEN0_Msk                                        (0x1UL << CAN_INTEN_FMIEN0_Pos)                                /*!< 0x00000002 */
#define CAN_INTEN_FMIEN0                                            CAN_INTEN_FMIEN0_Msk                                           /*!<FIFO Message Pending Interrupt Enable */
#define CAN_INTEN_FFULLIEN0_Pos                                     (2U)
#define CAN_INTEN_FFULLIEN0_Msk                                     (0x1UL << CAN_INTEN_FFULLIEN0_Pos)                             /*!< 0x00000004 */
#define CAN_INTEN_FFULLIEN0                                         CAN_INTEN_FFULLIEN0_Msk                                        /*!<FIFO Full Interrupt Enable */
#define CAN_INTEN_FOVRIEN0_Pos                                      (3U)
#define CAN_INTEN_FOVRIEN0_Msk                                      (0x1UL << CAN_INTEN_FOVRIEN0_Pos)                              /*!< 0x00000008 */
#define CAN_INTEN_FOVRIEN0                                          CAN_INTEN_FOVRIEN0_Msk                                         /*!<FIFO Overrun Interrupt Enable */
#define CAN_INTEN_FMIEN1_Pos                                        (4U)
#define CAN_INTEN_FMIEN1_Msk                                        (0x1UL << CAN_INTEN_FMIEN1_Pos)                                /*!< 0x00000010 */
#define CAN_INTEN_FMIEN1                                            CAN_INTEN_FMIEN1_Msk                                           /*!<FIFO Message Pending Interrupt Enable */
#define CAN_INTEN_FFULLIEN1_Pos                                     (5U)
#define CAN_INTEN_FFULLIEN1_Msk                                     (0x1UL << CAN_INTEN_FFULLIEN1_Pos)                             /*!< 0x00000020 */
#define CAN_INTEN_FFULLIEN1                                         CAN_INTEN_FFULLIEN1_Msk                                        /*!<FIFO Full Interrupt Enable */
#define CAN_INTEN_FOVRIEN1_Pos                                      (6U)
#define CAN_INTEN_FOVRIEN1_Msk                                      (0x1UL << CAN_INTEN_FOVRIEN1_Pos)                              /*!< 0x00000040 */
#define CAN_INTEN_FOVRIEN1                                          CAN_INTEN_FOVRIEN1_Msk                                         /*!<FIFO Overrun Interrupt Enable */
#define CAN_INTEN_ERRWIEN_Pos                                       (8U)
#define CAN_INTEN_ERRWIEN_Msk                                       (0x1UL << CAN_INTEN_ERRWIEN_Pos)                               /*!< 0x00000100 */
#define CAN_INTEN_ERRWIEN                                           CAN_INTEN_ERRWIEN_Msk                                          /*!<Error Warning Interrupt Enable */
#define CAN_INTEN_ERRPIEN_Pos                                       (9U)
#define CAN_INTEN_ERRPIEN_Msk                                       (0x1UL << CAN_INTEN_ERRPIEN_Pos)                               /*!< 0x00000200 */
#define CAN_INTEN_ERRPIEN                                           CAN_INTEN_ERRPIEN_Msk                                          /*!<Error Passive Interrupt Enable */
#define CAN_INTEN_BOFFIEN_Pos                                       (10U)
#define CAN_INTEN_BOFFIEN_Msk                                       (0x1UL << CAN_INTEN_BOFFIEN_Pos)                               /*!< 0x00000400 */
#define CAN_INTEN_BOFFIEN                                           CAN_INTEN_BOFFIEN_Msk                                          /*!<Bus-Off Interrupt Enable */
#define CAN_INTEN_LECIEN_Pos                                        (11U)
#define CAN_INTEN_LECIEN_Msk                                        (0x1UL << CAN_INTEN_LECIEN_Pos)                                /*!< 0x00000800 */
#define CAN_INTEN_LECIEN                                            CAN_INTEN_LECIEN_Msk                                           /*!<Last Error Code Interrupt Enable */
#define CAN_INTEN_ERRIEN_Pos                                        (15U)
#define CAN_INTEN_ERRIEN_Msk                                        (0x1UL << CAN_INTEN_ERRIEN_Pos)                                /*!< 0x00008000 */
#define CAN_INTEN_ERRIEN                                            CAN_INTEN_ERRIEN_Msk                                           /*!<Error Interrupt Enable */
#define CAN_INTEN_WUPIEN_Pos                                        (16U)
#define CAN_INTEN_WUPIEN_Msk                                        (0x1UL << CAN_INTEN_WUPIEN_Pos)                                /*!< 0x00010000 */
#define CAN_INTEN_WUPIEN                                            CAN_INTEN_WUPIEN_Msk                                           /*!<Wakeup Interrupt Enable */
#define CAN_INTEN_SLEEPIEN_Pos                                      (17U)
#define CAN_INTEN_SLEEPIEN_Msk                                      (0x1UL << CAN_INTEN_SLEEPIEN_Pos)                              /*!< 0x00020000 */
#define CAN_INTEN_SLEEPIEN                                          CAN_INTEN_SLEEPIEN_Msk                                         /*!<Sleep Interrupt Enable */

/********************  Bit definition for CAN_ERRSTS register  *******************/
#define CAN_ERRSTS_ERRWFLG_Pos                                      (0U)
#define CAN_ERRSTS_ERRWFLG_Msk                                      (0x1UL << CAN_ERRSTS_ERRWFLG_Pos)                              /*!< 0x00000001 */
#define CAN_ERRSTS_ERRWFLG                                          CAN_ERRSTS_ERRWFLG_Msk                                         /*!<Error Warning Flag */
#define CAN_ERRSTS_ERRPFLG_Pos                                      (1U)
#define CAN_ERRSTS_ERRPFLG_Msk                                      (0x1UL << CAN_ERRSTS_ERRPFLG_Pos)                              /*!< 0x00000002 */
#define CAN_ERRSTS_ERRPFLG                                          CAN_ERRSTS_ERRPFLG_Msk                                         /*!<Error Passive Flag */
#define CAN_ERRSTS_BOFLG_Pos                                        (2U)
#define CAN_ERRSTS_BOFLG_Msk                                        (0x1UL << CAN_ERRSTS_BOFLG_Pos)                                /*!< 0x00000004 */
#define CAN_ERRSTS_BOFLG                                            CAN_ERRSTS_BOFLG_Msk                                           /*!<Bus-Off Flag */

#define CAN_ERRSTS_LERRC_Pos                                        (4U)
#define CAN_ERRSTS_LERRC_Msk                                        (0x7UL << CAN_ERRSTS_LERRC_Pos)                                /*!< 0x00000070 */
#define CAN_ERRSTS_LERRC                                            CAN_ERRSTS_LERRC_Msk                                           /*!<LEC[2:0] bits (Last Error Code) */
#define CAN_ERRSTS_LERRC_0                                          (0x1UL << CAN_ERRSTS_LERRC_Pos)                                /*!< 0x00000010 */
#define CAN_ERRSTS_LERRC_1                                          (0x2UL << CAN_ERRSTS_LERRC_Pos)                                /*!< 0x00000020 */
#define CAN_ERRSTS_LERRC_2                                          (0x4UL << CAN_ERRSTS_LERRC_Pos)                                /*!< 0x00000040 */

#define CAN_ERRSTS_TXERRCNT_Pos                                     (16U)
#define CAN_ERRSTS_TXERRCNT_Msk                                     (0xFFUL << CAN_ERRSTS_TXERRCNT_Pos)                            /*!< 0x00FF0000 */
#define CAN_ERRSTS_TXERRCNT                                         CAN_ERRSTS_TXERRCNT_Msk                                        /*!<Least significant byte of the 9-bit Transmit Error Counter */
#define CAN_ERRSTS_RXERRCNT_Pos                                     (24U)
#define CAN_ERRSTS_RXERRCNT_Msk                                     (0xFFUL << CAN_ERRSTS_RXERRCNT_Pos)                            /*!< 0xFF000000 */
#define CAN_ERRSTS_RXERRCNT                                         CAN_ERRSTS_RXERRCNT_Msk                                        /*!<Receive Error Counter */

/*******************  Bit definition for CAN_BITTIM register  ********************/
#define CAN_BITTIM_BRPSC_Pos                                        (0U)
#define CAN_BITTIM_BRPSC_Msk                                        (0x3FFUL << CAN_BITTIM_BRPSC_Pos)                              /*!< 0x000003FF */
#define CAN_BITTIM_BRPSC                                            CAN_BITTIM_BRPSC_Msk                                           /*!<Baud Rate Prescaler */
#define CAN_BITTIM_TIMSEG1_Pos                                      (16U)
#define CAN_BITTIM_TIMSEG1_Msk                                      (0xFUL << CAN_BITTIM_TIMSEG1_Pos)                              /*!< 0x000F0000 */
#define CAN_BITTIM_TIMSEG1                                          CAN_BITTIM_TIMSEG1_Msk                                         /*!<Time Segment 1 */
#define CAN_BITTIM_TIMSEG1_0                                        (0x1UL << CAN_BITTIM_TIMSEG1_Pos)                              /*!< 0x00010000 */
#define CAN_BITTIM_TIMSEG1_1                                        (0x2UL << CAN_BITTIM_TIMSEG1_Pos)                              /*!< 0x00020000 */
#define CAN_BITTIM_TIMSEG1_2                                        (0x4UL << CAN_BITTIM_TIMSEG1_Pos)                              /*!< 0x00040000 */
#define CAN_BITTIM_TIMSEG1_3                                        (0x8UL << CAN_BITTIM_TIMSEG1_Pos)                              /*!< 0x00080000 */
#define CAN_BITTIM_TIMSEG2_Pos                                      (20U)
#define CAN_BITTIM_TIMSEG2_Msk                                      (0x7UL << CAN_BITTIM_TIMSEG2_Pos)                              /*!< 0x00700000 */
#define CAN_BITTIM_TIMSEG2                                          CAN_BITTIM_TIMSEG2_Msk                                         /*!<Time Segment 2 */
#define CAN_BITTIM_TIMSEG2_0                                        (0x1UL << CAN_BITTIM_TIMSEG2_Pos)                              /*!< 0x00100000 */
#define CAN_BITTIM_TIMSEG2_1                                        (0x2UL << CAN_BITTIM_TIMSEG2_Pos)                              /*!< 0x00200000 */
#define CAN_BITTIM_TIMSEG2_2                                        (0x4UL << CAN_BITTIM_TIMSEG2_Pos)                              /*!< 0x00400000 */
#define CAN_BITTIM_RSYNJW_Pos                                       (24U)
#define CAN_BITTIM_RSYNJW_Msk                                       (0x3UL << CAN_BITTIM_RSYNJW_Pos)                               /*!< 0x03000000 */
#define CAN_BITTIM_RSYNJW                                           CAN_BITTIM_RSYNJW_Msk                                          /*!<Resynchronization Jump Width */
#define CAN_BITTIM_RSYNJW_0                                         (0x1UL << CAN_BITTIM_RSYNJW_Pos)                               /*!< 0x01000000 */
#define CAN_BITTIM_RSYNJW_1                                         (0x2UL << CAN_BITTIM_RSYNJW_Pos)                               /*!< 0x02000000 */
#define CAN_BITTIM_LBKMEN_Pos                                       (30U)
#define CAN_BITTIM_LBKMEN_Msk                                       (0x1UL << CAN_BITTIM_LBKMEN_Pos)                               /*!< 0x40000000 */
#define CAN_BITTIM_LBKMEN                                           CAN_BITTIM_LBKMEN_Msk                                          /*!<Loop Back Mode (Debug) */
#define CAN_BITTIM_SILMEN_Pos                                       (31U)
#define CAN_BITTIM_SILMEN_Msk                                       (0x1UL << CAN_BITTIM_SILMEN_Pos)                               /*!< 0x80000000 */
#define CAN_BITTIM_SILMEN                                           CAN_BITTIM_SILMEN_Msk                                          /*!<Silent Mode */


/*!<Mailbox registers */
/******************  Bit definition for CAN_TXMID0 register  ********************/
#define CAN_TXMID0_TXMREQ_Pos                                       (0U)
#define CAN_TXMID0_TXMREQ_Msk                                       (0x1UL << CAN_TXMID0_TXMREQ_Pos)                               /*!< 0x00000001 */
#define CAN_TXMID0_TXMREQ                                           CAN_TXMID0_TXMREQ_Msk                                          /*!<Transmit Mailbox Request */
#define CAN_TXMID0_TXRFREQ_Pos                                      (1U)
#define CAN_TXMID0_TXRFREQ_Msk                                      (0x1UL << CAN_TXMID0_TXRFREQ_Pos)                              /*!< 0x00000002 */
#define CAN_TXMID0_TXRFREQ                                          CAN_TXMID0_TXRFREQ_Msk                                         /*!<Remote Transmission Request */
#define CAN_TXMID0_IDTYPESEL_Pos                                    (2U)
#define CAN_TXMID0_IDTYPESEL_Msk                                    (0x1UL << CAN_TXMID0_IDTYPESEL_Pos)                            /*!< 0x00000004 */
#define CAN_TXMID0_IDTYPESEL                                        CAN_TXMID0_IDTYPESEL_Msk                                       /*!<Identifier Extension */
#define CAN_TXMID0_EXTID_Pos                                        (3U)
#define CAN_TXMID0_EXTID_Msk                                        (0x3FFFFUL << CAN_TXMID0_EXTID_Pos)                            /*!< 0x001FFFF8 */
#define CAN_TXMID0_EXTID                                            CAN_TXMID0_EXTID_Msk                                           /*!<Extended Identifier */
#define CAN_TXMID0_STDID_Pos                                        (21U)
#define CAN_TXMID0_STDID_Msk                                        (0x7FFUL << CAN_TXMID0_STDID_Pos)                              /*!< 0xFFE00000 */
#define CAN_TXMID0_STDID                                            CAN_TXMID0_STDID_Msk                                           /*!<Standard Identifier or Extended Identifier */

/******************  Bit definition for CAN_TXDLEN0 register  *******************/
#define CAN_TXDLEN0_DLCODE_Pos                                      (0U)
#define CAN_TXDLEN0_DLCODE_Msk                                      (0xFUL << CAN_TXDLEN0_DLCODE_Pos)                              /*!< 0x0000000F */
#define CAN_TXDLEN0_DLCODE                                          CAN_TXDLEN0_DLCODE_Msk                                         /*!<Data Length Code */
#define CAN_TXDLEN0_TXTS_Pos                                        (8U)
#define CAN_TXDLEN0_TXTS_Msk                                        (0x1UL << CAN_TXDLEN0_TXTS_Pos)                                /*!< 0x00000100 */
#define CAN_TXDLEN0_TXTS                                            CAN_TXDLEN0_TXTS_Msk                                           /*!<Transmit Global Time */
#define CAN_TXDLEN0_MTS_Pos                                         (16U)
#define CAN_TXDLEN0_MTS_Msk                                         (0xFFFFUL << CAN_TXDLEN0_MTS_Pos)                              /*!< 0xFFFF0000 */
#define CAN_TXDLEN0_MTS                                             CAN_TXDLEN0_MTS_Msk                                            /*!<Message Time Stamp */

/******************  Bit definition for CAN_TXMDL0 register  *******************/
#define CAN_TXMDL0_DATABYTE0_Pos                                    (0U)
#define CAN_TXMDL0_DATABYTE0_Msk                                    (0xFFUL << CAN_TXMDL0_DATABYTE0_Pos)                           /*!< 0x000000FF */
#define CAN_TXMDL0_DATABYTE0                                        CAN_TXMDL0_DATABYTE0_Msk                                       /*!<Data byte 0 */
#define CAN_TXMDL0_DATABYTE1_Pos                                    (8U)
#define CAN_TXMDL0_DATABYTE1_Msk                                    (0xFFUL << CAN_TXMDL0_DATABYTE1_Pos)                           /*!< 0x0000FF00 */
#define CAN_TXMDL0_DATABYTE1                                        CAN_TXMDL0_DATABYTE1_Msk                                       /*!<Data byte 1 */
#define CAN_TXMDL0_DATABYTE2_Pos                                    (16U)
#define CAN_TXMDL0_DATABYTE2_Msk                                    (0xFFUL << CAN_TXMDL0_DATABYTE2_Pos)                           /*!< 0x00FF0000 */
#define CAN_TXMDL0_DATABYTE2                                        CAN_TXMDL0_DATABYTE2_Msk                                       /*!<Data byte 2 */
#define CAN_TXMDL0_DATABYTE3_Pos                                    (24U)
#define CAN_TXMDL0_DATABYTE3_Msk                                    (0xFFUL << CAN_TXMDL0_DATABYTE3_Pos)                           /*!< 0xFF000000 */
#define CAN_TXMDL0_DATABYTE3                                        CAN_TXMDL0_DATABYTE3_Msk                                       /*!<Data byte 3 */

/******************  Bit definition for CAN_TXMDH0 register  *******************/
#define CAN_TXMDH0_DATABYTE4_Pos                                    (0U)
#define CAN_TXMDH0_DATABYTE4_Msk                                    (0xFFUL << CAN_TXMDH0_DATABYTE4_Pos)                           /*!< 0x000000FF */
#define CAN_TXMDH0_DATABYTE4                                        CAN_TXMDH0_DATABYTE4_Msk                                       /*!<Data byte 4 */
#define CAN_TXMDH0_DATABYTE5_Pos                                    (8U)
#define CAN_TXMDH0_DATABYTE5_Msk                                    (0xFFUL << CAN_TXMDH0_DATABYTE5_Pos)                           /*!< 0x0000FF00 */
#define CAN_TXMDH0_DATABYTE5                                        CAN_TXMDH0_DATABYTE5_Msk                                       /*!<Data byte 5 */
#define CAN_TXMDH0_DATABYTE6_Pos                                    (16U)
#define CAN_TXMDH0_DATABYTE6_Msk                                    (0xFFUL << CAN_TXMDH0_DATABYTE6_Pos)                           /*!< 0x00FF0000 */
#define CAN_TXMDH0_DATABYTE6                                        CAN_TXMDH0_DATABYTE6_Msk                                       /*!<Data byte 6 */
#define CAN_TXMDH0_DATABYTE7_Pos                                    (24U)
#define CAN_TXMDH0_DATABYTE7_Msk                                    (0xFFUL << CAN_TXMDH0_DATABYTE7_Pos)                           /*!< 0xFF000000 */
#define CAN_TXMDH0_DATABYTE7                                        CAN_TXMDH0_DATABYTE7_Msk                                       /*!<Data byte 7 */

/*******************  Bit definition for CAN_TXMID1 register  *******************/
#define CAN_TXMID1_TXMREQ_Pos                                       (0U)
#define CAN_TXMID1_TXMREQ_Msk                                       (0x1UL << CAN_TXMID1_TXMREQ_Pos)                               /*!< 0x00000001 */
#define CAN_TXMID1_TXMREQ                                           CAN_TXMID1_TXMREQ_Msk                                          /*!<Transmit Mailbox Request */
#define CAN_TXMID1_TXRFREQ_Pos                                      (1U)
#define CAN_TXMID1_TXRFREQ_Msk                                      (0x1UL << CAN_TXMID1_TXRFREQ_Pos)                              /*!< 0x00000002 */
#define CAN_TXMID1_TXRFREQ                                          CAN_TXMID1_TXRFREQ_Msk                                         /*!<Remote Transmission Request */
#define CAN_TXMID1_IDTYPESEL_Pos                                    (2U)
#define CAN_TXMID1_IDTYPESEL_Msk                                    (0x1UL << CAN_TXMID1_IDTYPESEL_Pos)                            /*!< 0x00000004 */
#define CAN_TXMID1_IDTYPESEL                                        CAN_TXMID1_IDTYPESEL_Msk                                       /*!<Identifier Extension */
#define CAN_TXMID1_EXTID_Pos                                        (3U)
#define CAN_TXMID1_EXTID_Msk                                        (0x3FFFFUL << CAN_TXMID1_EXTID_Pos)                            /*!< 0x001FFFF8 */
#define CAN_TXMID1_EXTID                                            CAN_TXMID1_EXTID_Msk                                           /*!<Extended Identifier */
#define CAN_TXMID1_STDID_Pos                                        (21U)
#define CAN_TXMID1_STDID_Msk                                        (0x7FFUL << CAN_TXMID1_STDID_Pos)                              /*!< 0xFFE00000 */
#define CAN_TXMID1_STDID                                            CAN_TXMID1_STDID_Msk                                           /*!<Standard Identifier or Extended Identifier */

/*******************  Bit definition for CAN_TXDLEN1 register  ******************/
#define CAN_TXDLEN1_DLCODE_Pos                                      (0U)
#define CAN_TXDLEN1_DLCODE_Msk                                      (0xFUL << CAN_TXDLEN1_DLCODE_Pos)                              /*!< 0x0000000F */
#define CAN_TXDLEN1_DLCODE                                          CAN_TXDLEN1_DLCODE_Msk                                         /*!<Data Length Code */
#define CAN_TXDLEN1_TXTS_Pos                                        (8U)
#define CAN_TXDLEN1_TXTS_Msk                                        (0x1UL << CAN_TXDLEN1_TXTS_Pos)                                /*!< 0x00000100 */
#define CAN_TXDLEN1_TXTS                                            CAN_TXDLEN1_TXTS_Msk                                           /*!<Transmit Global Time */
#define CAN_TXDLEN1_MTS_Pos                                         (16U)
#define CAN_TXDLEN1_MTS_Msk                                         (0xFFFFUL << CAN_TXDLEN1_MTS_Pos)                              /*!< 0xFFFF0000 */
#define CAN_TXDLEN1_MTS                                             CAN_TXDLEN1_MTS_Msk                                            /*!<Message Time Stamp */

/*******************  Bit definition for CAN_TXMDL1 register  ******************/
#define CAN_TXMDL1_DATABYTE0_Pos                                    (0U)
#define CAN_TXMDL1_DATABYTE0_Msk                                    (0xFFUL << CAN_TXMDL1_DATABYTE0_Pos)                           /*!< 0x000000FF */
#define CAN_TXMDL1_DATABYTE0                                        CAN_TXMDL1_DATABYTE0_Msk                                       /*!<Data byte 0 */
#define CAN_TXMDL1_DATABYTE1_Pos                                    (8U)
#define CAN_TXMDL1_DATABYTE1_Msk                                    (0xFFUL << CAN_TXMDL1_DATABYTE1_Pos)                           /*!< 0x0000FF00 */
#define CAN_TXMDL1_DATABYTE1                                        CAN_TXMDL1_DATABYTE1_Msk                                       /*!<Data byte 1 */
#define CAN_TXMDL1_DATABYTE2_Pos                                    (16U)
#define CAN_TXMDL1_DATABYTE2_Msk                                    (0xFFUL << CAN_TXMDL1_DATABYTE2_Pos)                           /*!< 0x00FF0000 */
#define CAN_TXMDL1_DATABYTE2                                        CAN_TXMDL1_DATABYTE2_Msk                                       /*!<Data byte 2 */
#define CAN_TXMDL1_DATABYTE3_Pos                                    (24U)
#define CAN_TXMDL1_DATABYTE3_Msk                                    (0xFFUL << CAN_TXMDL1_DATABYTE3_Pos)                           /*!< 0xFF000000 */
#define CAN_TXMDL1_DATABYTE3                                        CAN_TXMDL1_DATABYTE3_Msk                                       /*!<Data byte 3 */

/*******************  Bit definition for CAN_TXMDH1 register  ******************/
#define CAN_TXMDH1_DATABYTE4_Pos                                    (0U)
#define CAN_TXMDH1_DATABYTE4_Msk                                    (0xFFUL << CAN_TXMDH1_DATABYTE4_Pos)                           /*!< 0x000000FF */
#define CAN_TXMDH1_DATABYTE4                                        CAN_TXMDH1_DATABYTE4_Msk                                       /*!<Data byte 4 */
#define CAN_TXMDH1_DATABYTE5_Pos                                    (8U)
#define CAN_TXMDH1_DATABYTE5_Msk                                    (0xFFUL << CAN_TXMDH1_DATABYTE5_Pos)                           /*!< 0x0000FF00 */
#define CAN_TXMDH1_DATABYTE5                                        CAN_TXMDH1_DATABYTE5_Msk                                       /*!<Data byte 5 */
#define CAN_TXMDH1_DATABYTE6_Pos                                    (16U)
#define CAN_TXMDH1_DATABYTE6_Msk                                    (0xFFUL << CAN_TXMDH1_DATABYTE6_Pos)                           /*!< 0x00FF0000 */
#define CAN_TXMDH1_DATABYTE6                                        CAN_TXMDH1_DATABYTE6_Msk                                       /*!<Data byte 6 */
#define CAN_TXMDH1_DATABYTE7_Pos                                    (24U)
#define CAN_TXMDH1_DATABYTE7_Msk                                    (0xFFUL << CAN_TXMDH1_DATABYTE7_Pos)                           /*!< 0xFF000000 */
#define CAN_TXMDH1_DATABYTE7                                        CAN_TXMDH1_DATABYTE7_Msk                                       /*!<Data byte 7 */

/*******************  Bit definition for CAN_TXMID2 register  *******************/
#define CAN_TXMID2_TXMREQ_Pos                                       (0U)
#define CAN_TXMID2_TXMREQ_Msk                                       (0x1UL << CAN_TXMID2_TXMREQ_Pos)                               /*!< 0x00000001 */
#define CAN_TXMID2_TXMREQ                                           CAN_TXMID2_TXMREQ_Msk                                          /*!<Transmit Mailbox Request */
#define CAN_TXMID2_TXRFREQ_Pos                                      (1U)
#define CAN_TXMID2_TXRFREQ_Msk                                      (0x1UL << CAN_TXMID2_TXRFREQ_Pos)                              /*!< 0x00000002 */
#define CAN_TXMID2_TXRFREQ                                          CAN_TXMID2_TXRFREQ_Msk                                         /*!<Remote Transmission Request */
#define CAN_TXMID2_IDTYPESEL_Pos                                    (2U)
#define CAN_TXMID2_IDTYPESEL_Msk                                    (0x1UL << CAN_TXMID2_IDTYPESEL_Pos)                            /*!< 0x00000004 */
#define CAN_TXMID2_IDTYPESEL                                        CAN_TXMID2_IDTYPESEL_Msk                                       /*!<Identifier Extension */
#define CAN_TXMID2_EXTID_Pos                                        (3U)
#define CAN_TXMID2_EXTID_Msk                                        (0x3FFFFUL << CAN_TXMID2_EXTID_Pos)                            /*!< 0x001FFFF8 */
#define CAN_TXMID2_EXTID                                            CAN_TXMID2_EXTID_Msk                                           /*!<Extended identifier */
#define CAN_TXMID2_STDID_Pos                                        (21U)
#define CAN_TXMID2_STDID_Msk                                        (0x7FFUL << CAN_TXMID2_STDID_Pos)                              /*!< 0xFFE00000 */
#define CAN_TXMID2_STDID                                            CAN_TXMID2_STDID_Msk                                           /*!<Standard Identifier or Extended Identifier */

/*******************  Bit definition for CAN_TXDLEN2 register  ******************/  
#define CAN_TXDLEN2_DLCODE_Pos                                      (0U)
#define CAN_TXDLEN2_DLCODE_Msk                                      (0xFUL << CAN_TXDLEN2_DLCODE_Pos)                              /*!< 0x0000000F */
#define CAN_TXDLEN2_DLCODE                                          CAN_TXDLEN2_DLCODE_Msk                                         /*!<Data Length Code */
#define CAN_TXDLEN2_TXTS_Pos                                        (8U)
#define CAN_TXDLEN2_TXTS_Msk                                        (0x1UL << CAN_TXDLEN2_TXTS_Pos)                                /*!< 0x00000100 */
#define CAN_TXDLEN2_TXTS                                            CAN_TXDLEN2_TXTS_Msk                                           /*!<Transmit Global Time */
#define CAN_TXDLEN2_MTS_Pos                                         (16U)
#define CAN_TXDLEN2_MTS_Msk                                         (0xFFFFUL << CAN_TXDLEN2_MTS_Pos)                              /*!< 0xFFFF0000 */
#define CAN_TXDLEN2_MTS                                             CAN_TXDLEN2_MTS_Msk                                            /*!<Message Time Stamp */

/*******************  Bit definition for CAN_TXMDL2 register  ******************/
#define CAN_TXMDL2_DATABYTE0_Pos                                    (0U)
#define CAN_TXMDL2_DATABYTE0_Msk                                    (0xFFUL << CAN_TXMDL2_DATABYTE0_Pos)                           /*!< 0x000000FF */
#define CAN_TXMDL2_DATABYTE0                                        CAN_TXMDL2_DATABYTE0_Msk                                       /*!<Data byte 0 */
#define CAN_TXMDL2_DATABYTE1_Pos                                    (8U)
#define CAN_TXMDL2_DATABYTE1_Msk                                    (0xFFUL << CAN_TXMDL2_DATABYTE1_Pos)                           /*!< 0x0000FF00 */
#define CAN_TXMDL2_DATABYTE1                                        CAN_TXMDL2_DATABYTE1_Msk                                       /*!<Data byte 1 */
#define CAN_TXMDL2_DATABYTE2_Pos                                    (16U)
#define CAN_TXMDL2_DATABYTE2_Msk                                    (0xFFUL << CAN_TXMDL2_DATABYTE2_Pos)                           /*!< 0x00FF0000 */
#define CAN_TXMDL2_DATABYTE2                                        CAN_TXMDL2_DATABYTE2_Msk                                       /*!<Data byte 2 */
#define CAN_TXMDL2_DATABYTE3_Pos                                    (24U)
#define CAN_TXMDL2_DATABYTE3_Msk                                    (0xFFUL << CAN_TXMDL2_DATABYTE3_Pos)                           /*!< 0xFF000000 */
#define CAN_TXMDL2_DATABYTE3                                        CAN_TXMDL2_DATABYTE3_Msk                                       /*!<Data byte 3 */

/*******************  Bit definition for CAN_TXMDH2 register  ******************/
#define CAN_TXMDH2_DATABYTE4_Pos                                    (0U)
#define CAN_TXMDH2_DATABYTE4_Msk                                    (0xFFUL << CAN_TXMDH2_DATABYTE4_Pos)                           /*!< 0x000000FF */
#define CAN_TXMDH2_DATABYTE4                                        CAN_TXMDH2_DATABYTE4_Msk                                       /*!<Data byte 4 */
#define CAN_TXMDH2_DATABYTE5_Pos                                    (8U)
#define CAN_TXMDH2_DATABYTE5_Msk                                    (0xFFUL << CAN_TXMDH2_DATABYTE5_Pos)                           /*!< 0x0000FF00 */
#define CAN_TXMDH2_DATABYTE5                                        CAN_TXMDH2_DATABYTE5_Msk                                       /*!<Data byte 5 */
#define CAN_TXMDH2_DATABYTE6_Pos                                    (16U)
#define CAN_TXMDH2_DATABYTE6_Msk                                    (0xFFUL << CAN_TXMDH2_DATABYTE6_Pos)                           /*!< 0x00FF0000 */
#define CAN_TXMDH2_DATABYTE6                                        CAN_TXMDH2_DATABYTE6_Msk                                       /*!<Data byte 6 */
#define CAN_TXMDH2_DATABYTE7_Pos                                    (24U)
#define CAN_TXMDH2_DATABYTE7_Msk                                    (0xFFUL << CAN_TXMDH2_DATABYTE7_Pos)                           /*!< 0xFF000000 */
#define CAN_TXMDH2_DATABYTE7                                        CAN_TXMDH2_DATABYTE7_Msk                                       /*!<Data byte 7 */

/*******************  Bit definition for CAN_RXMID0 register  *******************/
#define CAN_RXMID0_RFTXREQ_Pos                                      (1U)
#define CAN_RXMID0_RFTXREQ_Msk                                      (0x1UL << CAN_RXMID0_RFTXREQ_Pos)                              /*!< 0x00000002 */
#define CAN_RXMID0_RFTXREQ                                          CAN_RXMID0_RFTXREQ_Msk                                         /*!<Remote Transmission Request */
#define CAN_RXMID0_IDTYPESEL_Pos                                    (2U)
#define CAN_RXMID0_IDTYPESEL_Msk                                    (0x1UL << CAN_RXMID0_IDTYPESEL_Pos)                            /*!< 0x00000004 */
#define CAN_RXMID0_IDTYPESEL                                        CAN_RXMID0_IDTYPESEL_Msk                                       /*!<Identifier Extension */
#define CAN_RXMID0_EXTID_Pos                                        (3U)
#define CAN_RXMID0_EXTID_Msk                                        (0x3FFFFUL << CAN_RXMID0_EXTID_Pos)                            /*!< 0x001FFFF8 */
#define CAN_RXMID0_EXTID                                            CAN_RXMID0_EXTID_Msk                                           /*!<Extended Identifier */
#define CAN_RXMID0_STDID_Pos                                        (21U)
#define CAN_RXMID0_STDID_Msk                                        (0x7FFUL << CAN_RXMID0_STDID_Pos)                              /*!< 0xFFE00000 */
#define CAN_RXMID0_STDID                                            CAN_RXMID0_STDID_Msk                                           /*!<Standard Identifier or Extended Identifier */

/*******************  Bit definition for CAN_RXDLEN0 register  ******************/
#define CAN_RXDLEN0_DLCODE_Pos                                      (0U)
#define CAN_RXDLEN0_DLCODE_Msk                                      (0xFUL << CAN_RXDLEN0_DLCODE_Pos)                              /*!< 0x0000000F */
#define CAN_RXDLEN0_DLCODE                                          CAN_RXDLEN0_DLCODE_Msk                                         /*!<Data Length Code */
#define CAN_RXDLEN0_FMIDX_Pos                                       (8U)
#define CAN_RXDLEN0_FMIDX_Msk                                       (0xFFUL << CAN_RXDLEN0_FMIDX_Pos)                              /*!< 0x0000FF00 */
#define CAN_RXDLEN0_FMIDX                                           CAN_RXDLEN0_FMIDX_Msk                                          /*!<Filter Match Index */
#define CAN_RXDLEN0_MTS_Pos                                         (16U)
#define CAN_RXDLEN0_MTS_Msk                                         (0xFFFFUL << CAN_RXDLEN0_MTS_Pos)                              /*!< 0xFFFF0000 */
#define CAN_RXDLEN0_MTS                                             CAN_RXDLEN0_MTS_Msk                                            /*!<Message Time Stamp */

/*******************  Bit definition for CAN_RXMDL0 register  ******************/
#define CAN_RXMDL0_DATABYTE0_Pos                                    (0U)
#define CAN_RXMDL0_DATABYTE0_Msk                                    (0xFFUL << CAN_RXMDL0_DATABYTE0_Pos)                           /*!< 0x000000FF */
#define CAN_RXMDL0_DATABYTE0                                        CAN_RXMDL0_DATABYTE0_Msk                                       /*!<Data byte 0 */
#define CAN_RXMDL0_DATABYTE1_Pos                                    (8U)
#define CAN_RXMDL0_DATABYTE1_Msk                                    (0xFFUL << CAN_RXMDL0_DATABYTE1_Pos)                           /*!< 0x0000FF00 */
#define CAN_RXMDL0_DATABYTE1                                        CAN_RXMDL0_DATABYTE1_Msk                                       /*!<Data byte 1 */
#define CAN_RXMDL0_DATABYTE2_Pos                                    (16U)
#define CAN_RXMDL0_DATABYTE2_Msk                                    (0xFFUL << CAN_RXMDL0_DATABYTE2_Pos)                           /*!< 0x00FF0000 */
#define CAN_RXMDL0_DATABYTE2                                        CAN_RXMDL0_DATABYTE2_Msk                                       /*!<Data byte 2 */
#define CAN_RXMDL0_DATABYTE3_Pos                                    (24U)
#define CAN_RXMDL0_DATABYTE3_Msk                                    (0xFFUL << CAN_RXMDL0_DATABYTE3_Pos)                           /*!< 0xFF000000 */
#define CAN_RXMDL0_DATABYTE3                                        CAN_RXMDL0_DATABYTE3_Msk                                       /*!<Data byte 3 */

/*******************  Bit definition for CAN_RXMDH0 register  ******************/
#define CAN_RXMDH0_DATABYTE4_Pos                                    (0U)
#define CAN_RXMDH0_DATABYTE4_Msk                                    (0xFFUL << CAN_RXMDH0_DATABYTE4_Pos)                           /*!< 0x000000FF */
#define CAN_RXMDH0_DATABYTE4                                        CAN_RXMDH0_DATABYTE4_Msk                                       /*!<Data byte 4 */
#define CAN_RXMDH0_DATABYTE5_Pos                                    (8U)
#define CAN_RXMDH0_DATABYTE5_Msk                                    (0xFFUL << CAN_RXMDH0_DATABYTE5_Pos)                           /*!< 0x0000FF00 */
#define CAN_RXMDH0_DATABYTE5                                        CAN_RXMDH0_DATABYTE5_Msk                                       /*!<Data byte 5 */
#define CAN_RXMDH0_DATABYTE6_Pos                                    (16U)
#define CAN_RXMDH0_DATABYTE6_Msk                                    (0xFFUL << CAN_RXMDH0_DATABYTE6_Pos)                           /*!< 0x00FF0000 */
#define CAN_RXMDH0_DATABYTE6                                        CAN_RXMDH0_DATABYTE6_Msk                                       /*!<Data byte 6 */
#define CAN_RXMDH0_DATABYTE7_Pos                                    (24U)
#define CAN_RXMDH0_DATABYTE7_Msk                                    (0xFFUL << CAN_RXMDH0_DATABYTE7_Pos)                           /*!< 0xFF000000 */
#define CAN_RXMDH0_DATABYTE7                                        CAN_RXMDH0_DATABYTE7_Msk                                       /*!<Data byte 7 */

/*******************  Bit definition for CAN_RXMID1 register  *******************/
#define CAN_RXMID1_RFTXREQ_Pos                                      (1U)
#define CAN_RXMID1_RFTXREQ_Msk                                      (0x1UL << CAN_RXMID1_RFTXREQ_Pos)                              /*!< 0x00000002 */
#define CAN_RXMID1_RFTXREQ                                          CAN_RXMID1_RFTXREQ_Msk                                         /*!<Remote Transmission Request */
#define CAN_RXMID1_IDTYPESEL_Pos                                    (2U)
#define CAN_RXMID1_IDTYPESEL_Msk                                    (0x1UL << CAN_RXMID1_IDTYPESEL_Pos)                            /*!< 0x00000004 */
#define CAN_RXMID1_IDTYPESEL                                        CAN_RXMID1_IDTYPESEL_Msk                                       /*!<Identifier Extension */
#define CAN_RXMID1_EXTID_Pos                                        (3U)
#define CAN_RXMID1_EXTID_Msk                                        (0x3FFFFUL << CAN_RXMID1_EXTID_Pos)                            /*!< 0x001FFFF8 */
#define CAN_RXMID1_EXTID                                            CAN_RXMID1_EXTID_Msk                                           /*!<Extended identifier */
#define CAN_RXMID1_STDID_Pos                                        (21U)
#define CAN_RXMID1_STDID_Msk                                        (0x7FFUL << CAN_RXMID1_STDID_Pos)                              /*!< 0xFFE00000 */
#define CAN_RXMID1_STDID                                            CAN_RXMID1_STDID_Msk                                           /*!<Standard Identifier or Extended Identifier */

/*******************  Bit definition for CAN_RXDLEN1 register  ******************/
#define CAN_RXDLEN1_DLCODE_Pos                                      (0U)
#define CAN_RXDLEN1_DLCODE_Msk                                      (0xFUL << CAN_RXDLEN1_DLCODE_Pos)                              /*!< 0x0000000F */
#define CAN_RXDLEN1_DLCODE                                          CAN_RXDLEN1_DLCODE_Msk                                         /*!<Data Length Code */
#define CAN_RXDLEN1_FMIDX_Pos                                       (8U)
#define CAN_RXDLEN1_FMIDX_Msk                                       (0xFFUL << CAN_RXDLEN1_FMIDX_Pos)                              /*!< 0x0000FF00 */
#define CAN_RXDLEN1_FMIDX                                           CAN_RXDLEN1_FMIDX_Msk                                          /*!<Filter Match Index */
#define CAN_RXDLEN1_MTS_Pos                                         (16U)
#define CAN_RXDLEN1_MTS_Msk                                         (0xFFFFUL << CAN_RXDLEN1_MTS_Pos)                              /*!< 0xFFFF0000 */
#define CAN_RXDLEN1_MTS                                             CAN_RXDLEN1_MTS_Msk                                            /*!<Message Time Stamp */

/*******************  Bit definition for CAN_RXMDL1 register  ******************/
#define CAN_RXMDL1_DATABYTE0_Pos                                    (0U)
#define CAN_RXMDL1_DATABYTE0_Msk                                    (0xFFUL << CAN_RXMDL1_DATABYTE0_Pos)                           /*!< 0x000000FF */
#define CAN_RXMDL1_DATABYTE0                                        CAN_RXMDL1_DATABYTE0_Msk                                       /*!<Data byte 0 */
#define CAN_RXMDL1_DATABYTE1_Pos                                    (8U)
#define CAN_RXMDL1_DATABYTE1_Msk                                    (0xFFUL << CAN_RXMDL1_DATABYTE1_Pos)                           /*!< 0x0000FF00 */
#define CAN_RXMDL1_DATABYTE1                                        CAN_RXMDL1_DATABYTE1_Msk                                       /*!<Data byte 1 */
#define CAN_RXMDL1_DATABYTE2_Pos                                    (16U)
#define CAN_RXMDL1_DATABYTE2_Msk                                    (0xFFUL << CAN_RXMDL1_DATABYTE2_Pos)                           /*!< 0x00FF0000 */
#define CAN_RXMDL1_DATABYTE2                                        CAN_RXMDL1_DATABYTE2_Msk                                       /*!<Data byte 2 */
#define CAN_RXMDL1_DATABYTE3_Pos                                    (24U)
#define CAN_RXMDL1_DATABYTE3_Msk                                    (0xFFUL << CAN_RXMDL1_DATABYTE3_Pos)                           /*!< 0xFF000000 */
#define CAN_RXMDL1_DATABYTE3                                        CAN_RXMDL1_DATABYTE3_Msk                                       /*!<Data byte 3 */

/*******************  Bit definition for CAN_RXMDH1 register  ******************/
#define CAN_RXMDH1_DATABYTE4_Pos                                    (0U)
#define CAN_RXMDH1_DATABYTE4_Msk                                    (0xFFUL << CAN_RXMDH1_DATABYTE4_Pos)                           /*!< 0x000000FF */
#define CAN_RXMDH1_DATABYTE4                                        CAN_RXMDH1_DATABYTE4_Msk                                       /*!<Data byte 4 */
#define CAN_RXMDH1_DATABYTE5_Pos                                    (8U)
#define CAN_RXMDH1_DATABYTE5_Msk                                    (0xFFUL << CAN_RXMDH1_DATABYTE5_Pos)                           /*!< 0x0000FF00 */
#define CAN_RXMDH1_DATABYTE5                                        CAN_RXMDH1_DATABYTE5_Msk                                       /*!<Data byte 5 */
#define CAN_RXMDH1_DATABYTE6_Pos                                    (16U)
#define CAN_RXMDH1_DATABYTE6_Msk                                    (0xFFUL << CAN_RXMDH1_DATABYTE6_Pos)                           /*!< 0x00FF0000 */
#define CAN_RXMDH1_DATABYTE6                                        CAN_RXMDH1_DATABYTE6_Msk                                       /*!<Data byte 6 */
#define CAN_RXMDH1_DATABYTE7_Pos                                    (24U)
#define CAN_RXMDH1_DATABYTE7_Msk                                    (0xFFUL << CAN_RXMDH1_DATABYTE7_Pos)                           /*!< 0xFF000000 */
#define CAN_RXMDH1_DATABYTE7                                        CAN_RXMDH1_DATABYTE7_Msk                                       /*!<Data byte 7 */

/*!<CAN filter registers */
/*******************  Bit definition for CAN_FCTRL register  ********************/
#define CAN_FCTRL_FINIT_Pos                                         (0U)
#define CAN_FCTRL_FINIT_Msk                                         (0x1UL << CAN_FCTRL_FINIT_Pos)                                 /*!< 0x00000001 */
#define CAN_FCTRL_FINIT                                             CAN_FCTRL_FINIT_Msk                                            /*!<Filter Init Mode */
#define CAN_FCTRL_CAN2SB_Pos                                        (8U)
#define CAN_FCTRL_CAN2SB_Msk                                        (0x3FUL << CAN_FCTRL_CAN2SB_Pos)                               /*!< 0x00003F00 */
#define CAN_FCTRL_CAN2SB                                            CAN_FCTRL_CAN2SB_Msk                                           /*!<CAN2 start bank */

/*******************  Bit definition for CAN_FMCFG register  *******************/
#define CAN_FMCFG_FBM_Pos                                           (0U)
#define CAN_FMCFG_FBM_Msk                                           (0xFFFFFFFUL << CAN_FMCFG_FBM_Pos)                             /*!< 0x0FFFFFFF */
#define CAN_FMCFG_FBM                                               CAN_FMCFG_FBM_Msk                                              /*!<Filter Mode */
#define CAN_FMCFG_FBM0_Pos                                          (0U)
#define CAN_FMCFG_FBM0_Msk                                          (0x1UL << CAN_FMCFG_FBM0_Pos)                                  /*!< 0x00000001 */
#define CAN_FMCFG_FBM0                                              CAN_FMCFG_FBM0_Msk                                             /*!<Filter Init Mode bit 0 */
#define CAN_FMCFG_FBM1_Pos                                          (1U)
#define CAN_FMCFG_FBM1_Msk                                          (0x1UL << CAN_FMCFG_FBM1_Pos)                                  /*!< 0x00000002 */
#define CAN_FMCFG_FBM1                                              CAN_FMCFG_FBM1_Msk                                             /*!<Filter Init Mode bit 1 */
#define CAN_FMCFG_FBM2_Pos                                          (2U)
#define CAN_FMCFG_FBM2_Msk                                          (0x1UL << CAN_FMCFG_FBM2_Pos)                                  /*!< 0x00000004 */
#define CAN_FMCFG_FBM2                                              CAN_FMCFG_FBM2_Msk                                             /*!<Filter Init Mode bit 2 */
#define CAN_FMCFG_FBM3_Pos                                          (3U)
#define CAN_FMCFG_FBM3_Msk                                          (0x1UL << CAN_FMCFG_FBM3_Pos)                                  /*!< 0x00000008 */
#define CAN_FMCFG_FBM3                                              CAN_FMCFG_FBM3_Msk                                             /*!<Filter Init Mode bit 3 */
#define CAN_FMCFG_FBM4_Pos                                          (4U)
#define CAN_FMCFG_FBM4_Msk                                          (0x1UL << CAN_FMCFG_FBM4_Pos)                                  /*!< 0x00000010 */
#define CAN_FMCFG_FBM4                                              CAN_FMCFG_FBM4_Msk                                             /*!<Filter Init Mode bit 4 */
#define CAN_FMCFG_FBM5_Pos                                          (5U)
#define CAN_FMCFG_FBM5_Msk                                          (0x1UL << CAN_FMCFG_FBM5_Pos)                                  /*!< 0x00000020 */
#define CAN_FMCFG_FBM5                                              CAN_FMCFG_FBM5_Msk                                             /*!<Filter Init Mode bit 5 */
#define CAN_FMCFG_FBM6_Pos                                          (6U)
#define CAN_FMCFG_FBM6_Msk                                          (0x1UL << CAN_FMCFG_FBM6_Pos)                                  /*!< 0x00000040 */
#define CAN_FMCFG_FBM6                                              CAN_FMCFG_FBM6_Msk                                             /*!<Filter Init Mode bit 6 */
#define CAN_FMCFG_FBM7_Pos                                          (7U)
#define CAN_FMCFG_FBM7_Msk                                          (0x1UL << CAN_FMCFG_FBM7_Pos)                                  /*!< 0x00000080 */
#define CAN_FMCFG_FBM7                                              CAN_FMCFG_FBM7_Msk                                             /*!<Filter Init Mode bit 7 */
#define CAN_FMCFG_FBM8_Pos                                          (8U)
#define CAN_FMCFG_FBM8_Msk                                          (0x1UL << CAN_FMCFG_FBM8_Pos)                                  /*!< 0x00000100 */
#define CAN_FMCFG_FBM8                                              CAN_FMCFG_FBM8_Msk                                             /*!<Filter Init Mode bit 8 */
#define CAN_FMCFG_FBM9_Pos                                          (9U)
#define CAN_FMCFG_FBM9_Msk                                          (0x1UL << CAN_FMCFG_FBM9_Pos)                                  /*!< 0x00000200 */
#define CAN_FMCFG_FBM9                                              CAN_FMCFG_FBM9_Msk                                             /*!<Filter Init Mode bit 9 */
#define CAN_FMCFG_FBM10_Pos                                         (10U)
#define CAN_FMCFG_FBM10_Msk                                         (0x1UL << CAN_FMCFG_FBM10_Pos)                                 /*!< 0x00000400 */
#define CAN_FMCFG_FBM10                                             CAN_FMCFG_FBM10_Msk                                            /*!<Filter Init Mode bit 10 */
#define CAN_FMCFG_FBM11_Pos                                         (11U)
#define CAN_FMCFG_FBM11_Msk                                         (0x1UL << CAN_FMCFG_FBM11_Pos)                                 /*!< 0x00000800 */
#define CAN_FMCFG_FBM11                                             CAN_FMCFG_FBM11_Msk                                            /*!<Filter Init Mode bit 11 */
#define CAN_FMCFG_FBM12_Pos                                         (12U)
#define CAN_FMCFG_FBM12_Msk                                         (0x1UL << CAN_FMCFG_FBM12_Pos)                                 /*!< 0x00001000 */
#define CAN_FMCFG_FBM12                                             CAN_FMCFG_FBM12_Msk                                            /*!<Filter Init Mode bit 12 */
#define CAN_FMCFG_FBM13_Pos                                         (13U)
#define CAN_FMCFG_FBM13_Msk                                         (0x1UL << CAN_FMCFG_FBM13_Pos)                                 /*!< 0x00002000 */
#define CAN_FMCFG_FBM13                                             CAN_FMCFG_FBM13_Msk                                            /*!<Filter Init Mode bit 13 */
#define CAN_FMCFG_FBM14_Pos                                         (14U)
#define CAN_FMCFG_FBM14_Msk                                         (0x1UL << CAN_FMCFG_FBM14_Pos)                                 /*!< 0x00004000 */
#define CAN_FMCFG_FBM14                                             CAN_FMCFG_FBM14_Msk                                            /*!<Filter Init Mode bit 14 */
#define CAN_FMCFG_FBM15_Pos                                         (15U)
#define CAN_FMCFG_FBM15_Msk                                         (0x1UL << CAN_FMCFG_FBM15_Pos)                                 /*!< 0x00008000 */
#define CAN_FMCFG_FBM15                                             CAN_FMCFG_FBM15_Msk                                            /*!<Filter Init Mode bit 15 */
#define CAN_FMCFG_FBM16_Pos                                         (16U)
#define CAN_FMCFG_FBM16_Msk                                         (0x1UL << CAN_FMCFG_FBM16_Pos)                                 /*!< 0x00010000 */
#define CAN_FMCFG_FBM16                                             CAN_FMCFG_FBM16_Msk                                            /*!<Filter Init Mode bit 16 */
#define CAN_FMCFG_FBM17_Pos                                         (17U)
#define CAN_FMCFG_FBM17_Msk                                         (0x1UL << CAN_FMCFG_FBM17_Pos)                                 /*!< 0x00020000 */
#define CAN_FMCFG_FBM17                                             CAN_FMCFG_FBM17_Msk                                            /*!<Filter Init Mode bit 17 */
#define CAN_FMCFG_FBM18_Pos                                         (18U)
#define CAN_FMCFG_FBM18_Msk                                         (0x1UL << CAN_FMCFG_FBM18_Pos)                                 /*!< 0x00040000 */
#define CAN_FMCFG_FBM18                                             CAN_FMCFG_FBM18_Msk                                            /*!<Filter Init Mode bit 18 */
#define CAN_FMCFG_FBM19_Pos                                         (19U)
#define CAN_FMCFG_FBM19_Msk                                         (0x1UL << CAN_FMCFG_FBM19_Pos)                                 /*!< 0x00080000 */
#define CAN_FMCFG_FBM19                                             CAN_FMCFG_FBM19_Msk                                            /*!<Filter Init Mode bit 19 */
#define CAN_FMCFG_FBM20_Pos                                         (20U)
#define CAN_FMCFG_FBM20_Msk                                         (0x1UL << CAN_FMCFG_FBM20_Pos)                                 /*!< 0x00100000 */
#define CAN_FMCFG_FBM20                                             CAN_FMCFG_FBM20_Msk                                            /*!<Filter Init Mode bit 20 */
#define CAN_FMCFG_FBM21_Pos                                         (21U)
#define CAN_FMCFG_FBM21_Msk                                         (0x1UL << CAN_FMCFG_FBM21_Pos)                                 /*!< 0x00200000 */
#define CAN_FMCFG_FBM21                                             CAN_FMCFG_FBM21_Msk                                            /*!<Filter Init Mode bit 21 */
#define CAN_FMCFG_FBM22_Pos                                         (22U)
#define CAN_FMCFG_FBM22_Msk                                         (0x1UL << CAN_FMCFG_FBM22_Pos)                                 /*!< 0x00400000 */
#define CAN_FMCFG_FBM22                                             CAN_FMCFG_FBM22_Msk                                            /*!<Filter Init Mode bit 22 */
#define CAN_FMCFG_FBM23_Pos                                         (23U)
#define CAN_FMCFG_FBM23_Msk                                         (0x1UL << CAN_FMCFG_FBM23_Pos)                                 /*!< 0x00800000 */
#define CAN_FMCFG_FBM23                                             CAN_FMCFG_FBM23_Msk                                            /*!<Filter Init Mode bit 23 */
#define CAN_FMCFG_FBM24_Pos                                         (24U)
#define CAN_FMCFG_FBM24_Msk                                         (0x1UL << CAN_FMCFG_FBM24_Pos)                                 /*!< 0x01000000 */
#define CAN_FMCFG_FBM24                                             CAN_FMCFG_FBM24_Msk                                            /*!<Filter Init Mode bit 24 */
#define CAN_FMCFG_FBM25_Pos                                         (25U)
#define CAN_FMCFG_FBM25_Msk                                         (0x1UL << CAN_FMCFG_FBM25_Pos)                                 /*!< 0x02000000 */
#define CAN_FMCFG_FBM25                                             CAN_FMCFG_FBM25_Msk                                            /*!<Filter Init Mode bit 25 */
#define CAN_FMCFG_FBM26_Pos                                         (26U)
#define CAN_FMCFG_FBM26_Msk                                         (0x1UL << CAN_FMCFG_FBM26_Pos)                                 /*!< 0x04000000 */
#define CAN_FMCFG_FBM26                                             CAN_FMCFG_FBM26_Msk                                            /*!<Filter Init Mode bit 26 */
#define CAN_FMCFG_FBM27_Pos                                         (27U)
#define CAN_FMCFG_FBM27_Msk                                         (0x1UL << CAN_FMCFG_FBM27_Pos)                                 /*!< 0x08000000 */
#define CAN_FMCFG_FBM27                                             CAN_FMCFG_FBM27_Msk                                            /*!<Filter Init Mode bit 27 */

/*******************  Bit definition for CAN_FSCFG register  *******************/
#define CAN_FSCFG_FSC_Pos                                           (0U)
#define CAN_FSCFG_FSC_Msk                                           (0xFFFFFFFUL << CAN_FSCFG_FSC_Pos)                             /*!< 0x0FFFFFFF */
#define CAN_FSCFG_FSC                                               CAN_FSCFG_FSC_Msk                                              /*!<Filter Scale Configuration */
#define CAN_FSCFG_FSC0_Pos                                          (0U)
#define CAN_FSCFG_FSC0_Msk                                          (0x1UL << CAN_FSCFG_FSC0_Pos)                                  /*!< 0x00000001 */
#define CAN_FSCFG_FSC0                                              CAN_FSCFG_FSC0_Msk                                             /*!<Filter Scale Configuration bit 0 */
#define CAN_FSCFG_FSC1_Pos                                          (1U)
#define CAN_FSCFG_FSC1_Msk                                          (0x1UL << CAN_FSCFG_FSC1_Pos)                                  /*!< 0x00000002 */
#define CAN_FSCFG_FSC1                                              CAN_FSCFG_FSC1_Msk                                             /*!<Filter Scale Configuration bit 1 */
#define CAN_FSCFG_FSC2_Pos                                          (2U)
#define CAN_FSCFG_FSC2_Msk                                          (0x1UL << CAN_FSCFG_FSC2_Pos)                                  /*!< 0x00000004 */
#define CAN_FSCFG_FSC2                                              CAN_FSCFG_FSC2_Msk                                             /*!<Filter Scale Configuration bit 2 */
#define CAN_FSCFG_FSC3_Pos                                          (3U)
#define CAN_FSCFG_FSC3_Msk                                          (0x1UL << CAN_FSCFG_FSC3_Pos)                                  /*!< 0x00000008 */
#define CAN_FSCFG_FSC3                                              CAN_FSCFG_FSC3_Msk                                             /*!<Filter Scale Configuration bit 3 */
#define CAN_FSCFG_FSC4_Pos                                          (4U)
#define CAN_FSCFG_FSC4_Msk                                          (0x1UL << CAN_FSCFG_FSC4_Pos)                                  /*!< 0x00000010 */
#define CAN_FSCFG_FSC4                                              CAN_FSCFG_FSC4_Msk                                             /*!<Filter Scale Configuration bit 4 */
#define CAN_FSCFG_FSC5_Pos                                          (5U)
#define CAN_FSCFG_FSC5_Msk                                          (0x1UL << CAN_FSCFG_FSC5_Pos)                                  /*!< 0x00000020 */
#define CAN_FSCFG_FSC5                                              CAN_FSCFG_FSC5_Msk                                             /*!<Filter Scale Configuration bit 5 */
#define CAN_FSCFG_FSC6_Pos                                          (6U)
#define CAN_FSCFG_FSC6_Msk                                          (0x1UL << CAN_FSCFG_FSC6_Pos)                                  /*!< 0x00000040 */
#define CAN_FSCFG_FSC6                                              CAN_FSCFG_FSC6_Msk                                             /*!<Filter Scale Configuration bit 6 */
#define CAN_FSCFG_FSC7_Pos                                          (7U)
#define CAN_FSCFG_FSC7_Msk                                          (0x1UL << CAN_FSCFG_FSC7_Pos)                                  /*!< 0x00000080 */
#define CAN_FSCFG_FSC7                                              CAN_FSCFG_FSC7_Msk                                             /*!<Filter Scale Configuration bit 7 */
#define CAN_FSCFG_FSC8_Pos                                          (8U)
#define CAN_FSCFG_FSC8_Msk                                          (0x1UL << CAN_FSCFG_FSC8_Pos)                                  /*!< 0x00000100 */
#define CAN_FSCFG_FSC8                                              CAN_FSCFG_FSC8_Msk                                             /*!<Filter Scale Configuration bit 8 */
#define CAN_FSCFG_FSC9_Pos                                          (9U)
#define CAN_FSCFG_FSC9_Msk                                          (0x1UL << CAN_FSCFG_FSC9_Pos)                                  /*!< 0x00000200 */
#define CAN_FSCFG_FSC9                                              CAN_FSCFG_FSC9_Msk                                             /*!<Filter Scale Configuration bit 9 */
#define CAN_FSCFG_FSC10_Pos                                         (10U)
#define CAN_FSCFG_FSC10_Msk                                         (0x1UL << CAN_FSCFG_FSC10_Pos)                                 /*!< 0x00000400 */
#define CAN_FSCFG_FSC10                                             CAN_FSCFG_FSC10_Msk                                            /*!<Filter Scale Configuration bit 10 */
#define CAN_FSCFG_FSC11_Pos                                         (11U)
#define CAN_FSCFG_FSC11_Msk                                         (0x1UL << CAN_FSCFG_FSC11_Pos)                                 /*!< 0x00000800 */
#define CAN_FSCFG_FSC11                                             CAN_FSCFG_FSC11_Msk                                            /*!<Filter Scale Configuration bit 11 */
#define CAN_FSCFG_FSC12_Pos                                         (12U)
#define CAN_FSCFG_FSC12_Msk                                         (0x1UL << CAN_FSCFG_FSC12_Pos)                                 /*!< 0x00001000 */
#define CAN_FSCFG_FSC12                                             CAN_FSCFG_FSC12_Msk                                            /*!<Filter Scale Configuration bit 12 */
#define CAN_FSCFG_FSC13_Pos                                         (13U)
#define CAN_FSCFG_FSC13_Msk                                         (0x1UL << CAN_FSCFG_FSC13_Pos)                                 /*!< 0x00002000 */
#define CAN_FSCFG_FSC13                                             CAN_FSCFG_FSC13_Msk                                            /*!<Filter Scale Configuration bit 13 */
#define CAN_FSCFG_FSC14_Pos                                         (14U)
#define CAN_FSCFG_FSC14_Msk                                         (0x1UL << CAN_FSCFG_FSC14_Pos)                                 /*!< 0x00004000 */
#define CAN_FSCFG_FSC14                                             CAN_FSCFG_FSC14_Msk                                            /*!<Filter Scale Configuration bit 14 */
#define CAN_FSCFG_FSC15_Pos                                         (15U)
#define CAN_FSCFG_FSC15_Msk                                         (0x1UL << CAN_FSCFG_FSC15_Pos)                                 /*!< 0x00008000 */
#define CAN_FSCFG_FSC15                                             CAN_FSCFG_FSC15_Msk                                            /*!<Filter Scale Configuration bit 15 */
#define CAN_FSCFG_FSC16_Pos                                         (16U)
#define CAN_FSCFG_FSC16_Msk                                         (0x1UL << CAN_FSCFG_FSC16_Pos)                                 /*!< 0x00010000 */
#define CAN_FSCFG_FSC16                                             CAN_FSCFG_FSC16_Msk                                            /*!<Filter Scale Configuration bit 16 */
#define CAN_FSCFG_FSC17_Pos                                         (17U)
#define CAN_FSCFG_FSC17_Msk                                         (0x1UL << CAN_FSCFG_FSC17_Pos)                                 /*!< 0x00020000 */
#define CAN_FSCFG_FSC17                                             CAN_FSCFG_FSC17_Msk                                            /*!<Filter Scale Configuration bit 17 */
#define CAN_FSCFG_FSC18_Pos                                         (18U)
#define CAN_FSCFG_FSC18_Msk                                         (0x1UL << CAN_FSCFG_FSC18_Pos)                                 /*!< 0x00040000 */
#define CAN_FSCFG_FSC18                                             CAN_FSCFG_FSC18_Msk                                            /*!<Filter Scale Configuration bit 18 */
#define CAN_FSCFG_FSC19_Pos                                         (19U)
#define CAN_FSCFG_FSC19_Msk                                         (0x1UL << CAN_FSCFG_FSC19_Pos)                                 /*!< 0x00080000 */
#define CAN_FSCFG_FSC19                                             CAN_FSCFG_FSC19_Msk                                            /*!<Filter Scale Configuration bit 19 */
#define CAN_FSCFG_FSC20_Pos                                         (20U)
#define CAN_FSCFG_FSC20_Msk                                         (0x1UL << CAN_FSCFG_FSC20_Pos)                                 /*!< 0x00100000 */
#define CAN_FSCFG_FSC20                                             CAN_FSCFG_FSC20_Msk                                            /*!<Filter Scale Configuration bit 20 */
#define CAN_FSCFG_FSC21_Pos                                         (21U)
#define CAN_FSCFG_FSC21_Msk                                         (0x1UL << CAN_FSCFG_FSC21_Pos)                                 /*!< 0x00200000 */
#define CAN_FSCFG_FSC21                                             CAN_FSCFG_FSC21_Msk                                            /*!<Filter Scale Configuration bit 21 */
#define CAN_FSCFG_FSC22_Pos                                         (22U)
#define CAN_FSCFG_FSC22_Msk                                         (0x1UL << CAN_FSCFG_FSC22_Pos)                                 /*!< 0x00400000 */
#define CAN_FSCFG_FSC22                                             CAN_FSCFG_FSC22_Msk                                            /*!<Filter Scale Configuration bit 22 */
#define CAN_FSCFG_FSC23_Pos                                         (23U)
#define CAN_FSCFG_FSC23_Msk                                         (0x1UL << CAN_FSCFG_FSC23_Pos)                                 /*!< 0x00800000 */
#define CAN_FSCFG_FSC23                                             CAN_FSCFG_FSC23_Msk                                            /*!<Filter Scale Configuration bit 23 */
#define CAN_FSCFG_FSC24_Pos                                         (24U)
#define CAN_FSCFG_FSC24_Msk                                         (0x1UL << CAN_FSCFG_FSC24_Pos)                                 /*!< 0x01000000 */
#define CAN_FSCFG_FSC24                                             CAN_FSCFG_FSC24_Msk                                            /*!<Filter Scale Configuration bit 24 */
#define CAN_FSCFG_FSC25_Pos                                         (25U)
#define CAN_FSCFG_FSC25_Msk                                         (0x1UL << CAN_FSCFG_FSC25_Pos)                                 /*!< 0x02000000 */
#define CAN_FSCFG_FSC25                                             CAN_FSCFG_FSC25_Msk                                            /*!<Filter Scale Configuration bit 25 */
#define CAN_FSCFG_FSC26_Pos                                         (26U)
#define CAN_FSCFG_FSC26_Msk                                         (0x1UL << CAN_FSCFG_FSC26_Pos)                                 /*!< 0x04000000 */
#define CAN_FSCFG_FSC26                                             CAN_FSCFG_FSC26_Msk                                            /*!<Filter Scale Configuration bit 26 */
#define CAN_FSCFG_FSC27_Pos                                         (27U)
#define CAN_FSCFG_FSC27_Msk                                         (0x1UL << CAN_FSCFG_FSC27_Pos)                                 /*!< 0x08000000 */
#define CAN_FSCFG_FSC27                                             CAN_FSCFG_FSC27_Msk                                            /*!<Filter Scale Configuration bit 27 */

/******************  Bit definition for CAN_FFASS register  *******************/
#define CAN_FFASS_FFA_Pos                                           (0U)
#define CAN_FFASS_FFA_Msk                                           (0xFFFFFFFUL << CAN_FFASS_FFA_Pos)                             /*!< 0x0FFFFFFF */
#define CAN_FFASS_FFA                                               CAN_FFASS_FFA_Msk                                              /*!<Filter FIFO Assignment */
#define CAN_FFASS_FFA0_Pos                                          (0U)
#define CAN_FFASS_FFA0_Msk                                          (0x1UL << CAN_FFASS_FFA0_Pos)                                  /*!< 0x00000001 */
#define CAN_FFASS_FFA0                                              CAN_FFASS_FFA0_Msk                                             /*!<Filter FIFO Assignment bit 0 */
#define CAN_FFASS_FFA1_Pos                                          (1U)
#define CAN_FFASS_FFA1_Msk                                          (0x1UL << CAN_FFASS_FFA1_Pos)                                  /*!< 0x00000002 */
#define CAN_FFASS_FFA1                                              CAN_FFASS_FFA1_Msk                                             /*!<Filter FIFO Assignment bit 1 */
#define CAN_FFASS_FFA2_Pos                                          (2U)
#define CAN_FFASS_FFA2_Msk                                          (0x1UL << CAN_FFASS_FFA2_Pos)                                  /*!< 0x00000004 */
#define CAN_FFASS_FFA2                                              CAN_FFASS_FFA2_Msk                                             /*!<Filter FIFO Assignment bit 2 */
#define CAN_FFASS_FFA3_Pos                                          (3U)
#define CAN_FFASS_FFA3_Msk                                          (0x1UL << CAN_FFASS_FFA3_Pos)                                  /*!< 0x00000008 */
#define CAN_FFASS_FFA3                                              CAN_FFASS_FFA3_Msk                                             /*!<Filter FIFO Assignment bit 3 */
#define CAN_FFASS_FFA4_Pos                                          (4U)
#define CAN_FFASS_FFA4_Msk                                          (0x1UL << CAN_FFASS_FFA4_Pos)                                  /*!< 0x00000010 */
#define CAN_FFASS_FFA4                                              CAN_FFASS_FFA4_Msk                                             /*!<Filter FIFO Assignment bit 4 */
#define CAN_FFASS_FFA5_Pos                                          (5U)
#define CAN_FFASS_FFA5_Msk                                          (0x1UL << CAN_FFASS_FFA5_Pos)                                  /*!< 0x00000020 */
#define CAN_FFASS_FFA5                                              CAN_FFASS_FFA5_Msk                                             /*!<Filter FIFO Assignment bit 5 */
#define CAN_FFASS_FFA6_Pos                                          (6U)
#define CAN_FFASS_FFA6_Msk                                          (0x1UL << CAN_FFASS_FFA6_Pos)                                  /*!< 0x00000040 */
#define CAN_FFASS_FFA6                                              CAN_FFASS_FFA6_Msk                                             /*!<Filter FIFO Assignment bit 6 */
#define CAN_FFASS_FFA7_Pos                                          (7U)
#define CAN_FFASS_FFA7_Msk                                          (0x1UL << CAN_FFASS_FFA7_Pos)                                  /*!< 0x00000080 */
#define CAN_FFASS_FFA7                                              CAN_FFASS_FFA7_Msk                                             /*!<Filter FIFO Assignment bit 7 */
#define CAN_FFASS_FFA8_Pos                                          (8U)
#define CAN_FFASS_FFA8_Msk                                          (0x1UL << CAN_FFASS_FFA8_Pos)                                  /*!< 0x00000100 */
#define CAN_FFASS_FFA8                                              CAN_FFASS_FFA8_Msk                                             /*!<Filter FIFO Assignment bit 8 */
#define CAN_FFASS_FFA9_Pos                                          (9U)
#define CAN_FFASS_FFA9_Msk                                          (0x1UL << CAN_FFASS_FFA9_Pos)                                  /*!< 0x00000200 */
#define CAN_FFASS_FFA9                                              CAN_FFASS_FFA9_Msk                                             /*!<Filter FIFO Assignment bit 9 */
#define CAN_FFASS_FFA10_Pos                                         (10U)
#define CAN_FFASS_FFA10_Msk                                         (0x1UL << CAN_FFASS_FFA10_Pos)                                 /*!< 0x00000400 */
#define CAN_FFASS_FFA10                                             CAN_FFASS_FFA10_Msk                                            /*!<Filter FIFO Assignment bit 10 */
#define CAN_FFASS_FFA11_Pos                                         (11U)
#define CAN_FFASS_FFA11_Msk                                         (0x1UL << CAN_FFASS_FFA11_Pos)                                 /*!< 0x00000800 */
#define CAN_FFASS_FFA11                                             CAN_FFASS_FFA11_Msk                                            /*!<Filter FIFO Assignment bit 11 */
#define CAN_FFASS_FFA12_Pos                                         (12U)
#define CAN_FFASS_FFA12_Msk                                         (0x1UL << CAN_FFASS_FFA12_Pos)                                 /*!< 0x00001000 */
#define CAN_FFASS_FFA12                                             CAN_FFASS_FFA12_Msk                                            /*!<Filter FIFO Assignment bit 12 */
#define CAN_FFASS_FFA13_Pos                                         (13U)
#define CAN_FFASS_FFA13_Msk                                         (0x1UL << CAN_FFASS_FFA13_Pos)                                 /*!< 0x00002000 */
#define CAN_FFASS_FFA13                                             CAN_FFASS_FFA13_Msk                                            /*!<Filter FIFO Assignment bit 13 */
#define CAN_FFASS_FFA14_Pos                                         (14U)
#define CAN_FFASS_FFA14_Msk                                         (0x1UL << CAN_FFASS_FFA14_Pos)                                 /*!< 0x00004000 */
#define CAN_FFASS_FFA14                                             CAN_FFASS_FFA14_Msk                                            /*!<Filter FIFO Assignment bit 14 */
#define CAN_FFASS_FFA15_Pos                                         (15U)
#define CAN_FFASS_FFA15_Msk                                         (0x1UL << CAN_FFASS_FFA15_Pos)                                 /*!< 0x00008000 */
#define CAN_FFASS_FFA15                                             CAN_FFASS_FFA15_Msk                                            /*!<Filter FIFO Assignment bit 15 */
#define CAN_FFASS_FFA16_Pos                                         (16U)
#define CAN_FFASS_FFA16_Msk                                         (0x1UL << CAN_FFASS_FFA16_Pos)                                 /*!< 0x00010000 */
#define CAN_FFASS_FFA16                                             CAN_FFASS_FFA16_Msk                                            /*!<Filter FIFO Assignment bit 16 */
#define CAN_FFASS_FFA17_Pos                                         (17U)
#define CAN_FFASS_FFA17_Msk                                         (0x1UL << CAN_FFASS_FFA17_Pos)                                 /*!< 0x00020000 */
#define CAN_FFASS_FFA17                                             CAN_FFASS_FFA17_Msk                                            /*!<Filter FIFO Assignment bit 17 */
#define CAN_FFASS_FFA18_Pos                                         (18U)
#define CAN_FFASS_FFA18_Msk                                         (0x1UL << CAN_FFASS_FFA18_Pos)                                 /*!< 0x00040000 */
#define CAN_FFASS_FFA18                                             CAN_FFASS_FFA18_Msk                                            /*!<Filter FIFO Assignment bit 18 */
#define CAN_FFASS_FFA19_Pos                                         (19U)
#define CAN_FFASS_FFA19_Msk                                         (0x1UL << CAN_FFASS_FFA19_Pos)                                 /*!< 0x00080000 */
#define CAN_FFASS_FFA19                                             CAN_FFASS_FFA19_Msk                                            /*!<Filter FIFO Assignment bit 19 */
#define CAN_FFASS_FFA20_Pos                                         (20U)
#define CAN_FFASS_FFA20_Msk                                         (0x1UL << CAN_FFASS_FFA20_Pos)                                 /*!< 0x00100000 */
#define CAN_FFASS_FFA20                                             CAN_FFASS_FFA20_Msk                                            /*!<Filter FIFO Assignment bit 20 */
#define CAN_FFASS_FFA21_Pos                                         (21U)
#define CAN_FFASS_FFA21_Msk                                         (0x1UL << CAN_FFASS_FFA21_Pos)                                 /*!< 0x00200000 */
#define CAN_FFASS_FFA21                                             CAN_FFASS_FFA21_Msk                                            /*!<Filter FIFO Assignment bit 21 */
#define CAN_FFASS_FFA22_Pos                                         (22U)
#define CAN_FFASS_FFA22_Msk                                         (0x1UL << CAN_FFASS_FFA22_Pos)                                 /*!< 0x00400000 */
#define CAN_FFASS_FFA22                                             CAN_FFASS_FFA22_Msk                                            /*!<Filter FIFO Assignment bit 22 */
#define CAN_FFASS_FFA23_Pos                                         (23U)
#define CAN_FFASS_FFA23_Msk                                         (0x1UL << CAN_FFASS_FFA23_Pos)                                 /*!< 0x00800000 */
#define CAN_FFASS_FFA23                                             CAN_FFASS_FFA23_Msk                                            /*!<Filter FIFO Assignment bit 23 */
#define CAN_FFASS_FFA24_Pos                                         (24U)
#define CAN_FFASS_FFA24_Msk                                         (0x1UL << CAN_FFASS_FFA24_Pos)                                 /*!< 0x01000000 */
#define CAN_FFASS_FFA24                                             CAN_FFASS_FFA24_Msk                                            /*!<Filter FIFO Assignment bit 24 */
#define CAN_FFASS_FFA25_Pos                                         (25U)
#define CAN_FFASS_FFA25_Msk                                         (0x1UL << CAN_FFASS_FFA25_Pos)                                 /*!< 0x02000000 */
#define CAN_FFASS_FFA25                                             CAN_FFASS_FFA25_Msk                                            /*!<Filter FIFO Assignment bit 25 */
#define CAN_FFASS_FFA26_Pos                                         (26U)
#define CAN_FFASS_FFA26_Msk                                         (0x1UL << CAN_FFASS_FFA26_Pos)                                 /*!< 0x04000000 */
#define CAN_FFASS_FFA26                                             CAN_FFASS_FFA26_Msk                                            /*!<Filter FIFO Assignment bit 26 */
#define CAN_FFASS_FFA27_Pos                                         (27U)
#define CAN_FFASS_FFA27_Msk                                         (0x1UL << CAN_FFASS_FFA27_Pos)                                 /*!< 0x08000000 */
#define CAN_FFASS_FFA27                                             CAN_FFASS_FFA27_Msk                                            /*!<Filter FIFO Assignment bit 27 */

/*******************  Bit definition for CAN_FACT register  *******************/
#define CAN_FACT_FACT_Pos                                           (0U)
#define CAN_FACT_FACT_Msk                                           (0xFFFFFFFUL << CAN_FACT_FACT_Pos)                             /*!< 0x0FFFFFFF */
#define CAN_FACT_FACT                                               CAN_FACT_FACT_Msk                                              /*!<Filter Active */
#define CAN_FACT_FACT0_Pos                                          (0U)
#define CAN_FACT_FACT0_Msk                                          (0x1UL << CAN_FACT_FACT0_Pos)                                  /*!< 0x00000001 */
#define CAN_FACT_FACT0                                              CAN_FACT_FACT0_Msk                                             /*!<Filter Active bit 0 */
#define CAN_FACT_FACT1_Pos                                          (1U)
#define CAN_FACT_FACT1_Msk                                          (0x1UL << CAN_FACT_FACT1_Pos)                                  /*!< 0x00000002 */
#define CAN_FACT_FACT1                                              CAN_FACT_FACT1_Msk                                             /*!<Filter Active bit 1 */
#define CAN_FACT_FACT2_Pos                                          (2U)
#define CAN_FACT_FACT2_Msk                                          (0x1UL << CAN_FACT_FACT2_Pos)                                  /*!< 0x00000004 */
#define CAN_FACT_FACT2                                              CAN_FACT_FACT2_Msk                                             /*!<Filter Active bit 2 */
#define CAN_FACT_FACT3_Pos                                          (3U)
#define CAN_FACT_FACT3_Msk                                          (0x1UL << CAN_FACT_FACT3_Pos)                                  /*!< 0x00000008 */
#define CAN_FACT_FACT3                                              CAN_FACT_FACT3_Msk                                             /*!<Filter Active bit 3 */
#define CAN_FACT_FACT4_Pos                                          (4U)
#define CAN_FACT_FACT4_Msk                                          (0x1UL << CAN_FACT_FACT4_Pos)                                  /*!< 0x00000010 */
#define CAN_FACT_FACT4                                              CAN_FACT_FACT4_Msk                                             /*!<Filter Active bit 4 */
#define CAN_FACT_FACT5_Pos                                          (5U)
#define CAN_FACT_FACT5_Msk                                          (0x1UL << CAN_FACT_FACT5_Pos)                                  /*!< 0x00000020 */
#define CAN_FACT_FACT5                                              CAN_FACT_FACT5_Msk                                             /*!<Filter Active bit 5 */
#define CAN_FACT_FACT6_Pos                                          (6U)
#define CAN_FACT_FACT6_Msk                                          (0x1UL << CAN_FACT_FACT6_Pos)                                  /*!< 0x00000040 */
#define CAN_FACT_FACT6                                              CAN_FACT_FACT6_Msk                                             /*!<Filter Active bit 6 */
#define CAN_FACT_FACT7_Pos                                          (7U)
#define CAN_FACT_FACT7_Msk                                          (0x1UL << CAN_FACT_FACT7_Pos)                                  /*!< 0x00000080 */
#define CAN_FACT_FACT7                                              CAN_FACT_FACT7_Msk                                             /*!<Filter Active bit 7 */
#define CAN_FACT_FACT8_Pos                                          (8U)
#define CAN_FACT_FACT8_Msk                                          (0x1UL << CAN_FACT_FACT8_Pos)                                  /*!< 0x00000100 */
#define CAN_FACT_FACT8                                              CAN_FACT_FACT8_Msk                                             /*!<Filter Active bit 8 */
#define CAN_FACT_FACT9_Pos                                          (9U)
#define CAN_FACT_FACT9_Msk                                          (0x1UL << CAN_FACT_FACT9_Pos)                                  /*!< 0x00000200 */
#define CAN_FACT_FACT9                                              CAN_FACT_FACT9_Msk                                             /*!<Filter Active bit 9 */
#define CAN_FACT_FACT10_Pos                                         (10U)
#define CAN_FACT_FACT10_Msk                                         (0x1UL << CAN_FACT_FACT10_Pos)                                 /*!< 0x00000400 */
#define CAN_FACT_FACT10                                             CAN_FACT_FACT10_Msk                                            /*!<Filter Active bit 10 */
#define CAN_FACT_FACT11_Pos                                         (11U)
#define CAN_FACT_FACT11_Msk                                         (0x1UL << CAN_FACT_FACT11_Pos)                                 /*!< 0x00000800 */
#define CAN_FACT_FACT11                                             CAN_FACT_FACT11_Msk                                            /*!<Filter Active bit 11 */
#define CAN_FACT_FACT12_Pos                                         (12U)
#define CAN_FACT_FACT12_Msk                                         (0x1UL << CAN_FACT_FACT12_Pos)                                 /*!< 0x00001000 */
#define CAN_FACT_FACT12                                             CAN_FACT_FACT12_Msk                                            /*!<Filter Active bit 12 */
#define CAN_FACT_FACT13_Pos                                         (13U)
#define CAN_FACT_FACT13_Msk                                         (0x1UL << CAN_FACT_FACT13_Pos)                                 /*!< 0x00002000 */
#define CAN_FACT_FACT13                                             CAN_FACT_FACT13_Msk                                            /*!<Filter Active bit 13 */
#define CAN_FACT_FACT14_Pos                                         (14U)
#define CAN_FACT_FACT14_Msk                                         (0x1UL << CAN_FACT_FACT14_Pos)                                 /*!< 0x00004000 */
#define CAN_FACT_FACT14                                             CAN_FACT_FACT14_Msk                                            /*!<Filter Active bit 14 */
#define CAN_FACT_FACT15_Pos                                         (15U)
#define CAN_FACT_FACT15_Msk                                         (0x1UL << CAN_FACT_FACT15_Pos)                                 /*!< 0x00008000 */
#define CAN_FACT_FACT15                                             CAN_FACT_FACT15_Msk                                            /*!<Filter Active bit 15 */
#define CAN_FACT_FACT16_Pos                                         (16U)
#define CAN_FACT_FACT16_Msk                                         (0x1UL << CAN_FACT_FACT16_Pos)                                 /*!< 0x00010000 */
#define CAN_FACT_FACT16                                             CAN_FACT_FACT16_Msk                                            /*!<Filter Active bit 16 */
#define CAN_FACT_FACT17_Pos                                         (17U)
#define CAN_FACT_FACT17_Msk                                         (0x1UL << CAN_FACT_FACT17_Pos)                                 /*!< 0x00020000 */
#define CAN_FACT_FACT17                                             CAN_FACT_FACT17_Msk                                            /*!<Filter Active bit 17 */
#define CAN_FACT_FACT18_Pos                                         (18U)
#define CAN_FACT_FACT18_Msk                                         (0x1UL << CAN_FACT_FACT18_Pos)                                 /*!< 0x00040000 */
#define CAN_FACT_FACT18                                             CAN_FACT_FACT18_Msk                                            /*!<Filter Active bit 18 */
#define CAN_FACT_FACT19_Pos                                         (19U)
#define CAN_FACT_FACT19_Msk                                         (0x1UL << CAN_FACT_FACT19_Pos)                                 /*!< 0x00080000 */
#define CAN_FACT_FACT19                                             CAN_FACT_FACT19_Msk                                            /*!<Filter Active bit 19 */
#define CAN_FACT_FACT20_Pos                                         (20U)
#define CAN_FACT_FACT20_Msk                                         (0x1UL << CAN_FACT_FACT20_Pos)                                 /*!< 0x00100000 */
#define CAN_FACT_FACT20                                             CAN_FACT_FACT20_Msk                                            /*!<Filter Active bit 20 */
#define CAN_FACT_FACT21_Pos                                         (21U)
#define CAN_FACT_FACT21_Msk                                         (0x1UL << CAN_FACT_FACT21_Pos)                                 /*!< 0x00200000 */
#define CAN_FACT_FACT21                                             CAN_FACT_FACT21_Msk                                            /*!<Filter Active bit 21 */
#define CAN_FACT_FACT22_Pos                                         (22U)
#define CAN_FACT_FACT22_Msk                                         (0x1UL << CAN_FACT_FACT22_Pos)                                 /*!< 0x00400000 */
#define CAN_FACT_FACT22                                             CAN_FACT_FACT22_Msk                                            /*!<Filter Active bit 22 */
#define CAN_FACT_FACT23_Pos                                         (23U)
#define CAN_FACT_FACT23_Msk                                         (0x1UL << CAN_FACT_FACT23_Pos)                                 /*!< 0x00800000 */
#define CAN_FACT_FACT23                                             CAN_FACT_FACT23_Msk                                            /*!<Filter Active bit 23 */
#define CAN_FACT_FACT24_Pos                                         (24U)
#define CAN_FACT_FACT24_Msk                                         (0x1UL << CAN_FACT_FACT24_Pos)                                 /*!< 0x01000000 */
#define CAN_FACT_FACT24                                             CAN_FACT_FACT24_Msk                                            /*!<Filter Active bit 24 */
#define CAN_FACT_FACT25_Pos                                         (25U)
#define CAN_FACT_FACT25_Msk                                         (0x1UL << CAN_FACT_FACT25_Pos)                                 /*!< 0x02000000 */
#define CAN_FACT_FACT25                                             CAN_FACT_FACT25_Msk                                            /*!<Filter Active bit 25 */
#define CAN_FACT_FACT26_Pos                                         (26U)
#define CAN_FACT_FACT26_Msk                                         (0x1UL << CAN_FACT_FACT26_Pos)                                 /*!< 0x04000000 */
#define CAN_FACT_FACT26                                             CAN_FACT_FACT26_Msk                                            /*!<Filter Active bit 26 */
#define CAN_FACT_FACT27_Pos                                         (27U)
#define CAN_FACT_FACT27_Msk                                         (0x1UL << CAN_FACT_FACT27_Pos)                                 /*!< 0x08000000 */
#define CAN_FACT_FACT27                                             CAN_FACT_FACT27_Msk                                            /*!<Filter Active bit 27 */


/*******************  Bit definition for CAN_F0R1 register  *******************/
#define CAN_F0R1_FB0_Pos                                            (0U)
#define CAN_F0R1_FB0_Msk                                            (0x1UL << CAN_F0R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F0R1_FB0                                                CAN_F0R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F0R1_FB1_Pos                                            (1U)
#define CAN_F0R1_FB1_Msk                                            (0x1UL << CAN_F0R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F0R1_FB1                                                CAN_F0R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F0R1_FB2_Pos                                            (2U)
#define CAN_F0R1_FB2_Msk                                            (0x1UL << CAN_F0R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F0R1_FB2                                                CAN_F0R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F0R1_FB3_Pos                                            (3U)
#define CAN_F0R1_FB3_Msk                                            (0x1UL << CAN_F0R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F0R1_FB3                                                CAN_F0R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F0R1_FB4_Pos                                            (4U)
#define CAN_F0R1_FB4_Msk                                            (0x1UL << CAN_F0R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F0R1_FB4                                                CAN_F0R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F0R1_FB5_Pos                                            (5U)
#define CAN_F0R1_FB5_Msk                                            (0x1UL << CAN_F0R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F0R1_FB5                                                CAN_F0R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F0R1_FB6_Pos                                            (6U)
#define CAN_F0R1_FB6_Msk                                            (0x1UL << CAN_F0R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F0R1_FB6                                                CAN_F0R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F0R1_FB7_Pos                                            (7U)
#define CAN_F0R1_FB7_Msk                                            (0x1UL << CAN_F0R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F0R1_FB7                                                CAN_F0R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F0R1_FB8_Pos                                            (8U)
#define CAN_F0R1_FB8_Msk                                            (0x1UL << CAN_F0R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F0R1_FB8                                                CAN_F0R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F0R1_FB9_Pos                                            (9U)
#define CAN_F0R1_FB9_Msk                                            (0x1UL << CAN_F0R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F0R1_FB9                                                CAN_F0R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F0R1_FB10_Pos                                           (10U)
#define CAN_F0R1_FB10_Msk                                           (0x1UL << CAN_F0R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F0R1_FB10                                               CAN_F0R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F0R1_FB11_Pos                                           (11U)
#define CAN_F0R1_FB11_Msk                                           (0x1UL << CAN_F0R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F0R1_FB11                                               CAN_F0R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F0R1_FB12_Pos                                           (12U)
#define CAN_F0R1_FB12_Msk                                           (0x1UL << CAN_F0R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F0R1_FB12                                               CAN_F0R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F0R1_FB13_Pos                                           (13U)
#define CAN_F0R1_FB13_Msk                                           (0x1UL << CAN_F0R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F0R1_FB13                                               CAN_F0R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F0R1_FB14_Pos                                           (14U)
#define CAN_F0R1_FB14_Msk                                           (0x1UL << CAN_F0R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F0R1_FB14                                               CAN_F0R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F0R1_FB15_Pos                                           (15U)
#define CAN_F0R1_FB15_Msk                                           (0x1UL << CAN_F0R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F0R1_FB15                                               CAN_F0R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F0R1_FB16_Pos                                           (16U)
#define CAN_F0R1_FB16_Msk                                           (0x1UL << CAN_F0R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F0R1_FB16                                               CAN_F0R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F0R1_FB17_Pos                                           (17U)
#define CAN_F0R1_FB17_Msk                                           (0x1UL << CAN_F0R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F0R1_FB17                                               CAN_F0R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F0R1_FB18_Pos                                           (18U)
#define CAN_F0R1_FB18_Msk                                           (0x1UL << CAN_F0R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F0R1_FB18                                               CAN_F0R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F0R1_FB19_Pos                                           (19U)
#define CAN_F0R1_FB19_Msk                                           (0x1UL << CAN_F0R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F0R1_FB19                                               CAN_F0R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F0R1_FB20_Pos                                           (20U)
#define CAN_F0R1_FB20_Msk                                           (0x1UL << CAN_F0R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F0R1_FB20                                               CAN_F0R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F0R1_FB21_Pos                                           (21U)
#define CAN_F0R1_FB21_Msk                                           (0x1UL << CAN_F0R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F0R1_FB21                                               CAN_F0R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F0R1_FB22_Pos                                           (22U)
#define CAN_F0R1_FB22_Msk                                           (0x1UL << CAN_F0R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F0R1_FB22                                               CAN_F0R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F0R1_FB23_Pos                                           (23U)
#define CAN_F0R1_FB23_Msk                                           (0x1UL << CAN_F0R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F0R1_FB23                                               CAN_F0R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F0R1_FB24_Pos                                           (24U)
#define CAN_F0R1_FB24_Msk                                           (0x1UL << CAN_F0R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F0R1_FB24                                               CAN_F0R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F0R1_FB25_Pos                                           (25U)
#define CAN_F0R1_FB25_Msk                                           (0x1UL << CAN_F0R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F0R1_FB25                                               CAN_F0R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F0R1_FB26_Pos                                           (26U)
#define CAN_F0R1_FB26_Msk                                           (0x1UL << CAN_F0R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F0R1_FB26                                               CAN_F0R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F0R1_FB27_Pos                                           (27U)
#define CAN_F0R1_FB27_Msk                                           (0x1UL << CAN_F0R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F0R1_FB27                                               CAN_F0R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F0R1_FB28_Pos                                           (28U)
#define CAN_F0R1_FB28_Msk                                           (0x1UL << CAN_F0R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F0R1_FB28                                               CAN_F0R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F0R1_FB29_Pos                                           (29U)
#define CAN_F0R1_FB29_Msk                                           (0x1UL << CAN_F0R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F0R1_FB29                                               CAN_F0R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F0R1_FB30_Pos                                           (30U)
#define CAN_F0R1_FB30_Msk                                           (0x1UL << CAN_F0R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F0R1_FB30                                               CAN_F0R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F0R1_FB31_Pos                                           (31U)
#define CAN_F0R1_FB31_Msk                                           (0x1UL << CAN_F0R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F0R1_FB31                                               CAN_F0R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F1R1 register  *******************/
#define CAN_F1R1_FB0_Pos                                            (0U)
#define CAN_F1R1_FB0_Msk                                            (0x1UL << CAN_F1R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F1R1_FB0                                                CAN_F1R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F1R1_FB1_Pos                                            (1U)
#define CAN_F1R1_FB1_Msk                                            (0x1UL << CAN_F1R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F1R1_FB1                                                CAN_F1R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F1R1_FB2_Pos                                            (2U)
#define CAN_F1R1_FB2_Msk                                            (0x1UL << CAN_F1R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F1R1_FB2                                                CAN_F1R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F1R1_FB3_Pos                                            (3U)
#define CAN_F1R1_FB3_Msk                                            (0x1UL << CAN_F1R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F1R1_FB3                                                CAN_F1R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F1R1_FB4_Pos                                            (4U)
#define CAN_F1R1_FB4_Msk                                            (0x1UL << CAN_F1R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F1R1_FB4                                                CAN_F1R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F1R1_FB5_Pos                                            (5U)
#define CAN_F1R1_FB5_Msk                                            (0x1UL << CAN_F1R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F1R1_FB5                                                CAN_F1R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F1R1_FB6_Pos                                            (6U)
#define CAN_F1R1_FB6_Msk                                            (0x1UL << CAN_F1R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F1R1_FB6                                                CAN_F1R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F1R1_FB7_Pos                                            (7U)
#define CAN_F1R1_FB7_Msk                                            (0x1UL << CAN_F1R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F1R1_FB7                                                CAN_F1R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F1R1_FB8_Pos                                            (8U)
#define CAN_F1R1_FB8_Msk                                            (0x1UL << CAN_F1R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F1R1_FB8                                                CAN_F1R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F1R1_FB9_Pos                                            (9U)
#define CAN_F1R1_FB9_Msk                                            (0x1UL << CAN_F1R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F1R1_FB9                                                CAN_F1R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F1R1_FB10_Pos                                           (10U)
#define CAN_F1R1_FB10_Msk                                           (0x1UL << CAN_F1R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F1R1_FB10                                               CAN_F1R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F1R1_FB11_Pos                                           (11U)
#define CAN_F1R1_FB11_Msk                                           (0x1UL << CAN_F1R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F1R1_FB11                                               CAN_F1R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F1R1_FB12_Pos                                           (12U)
#define CAN_F1R1_FB12_Msk                                           (0x1UL << CAN_F1R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F1R1_FB12                                               CAN_F1R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F1R1_FB13_Pos                                           (13U)
#define CAN_F1R1_FB13_Msk                                           (0x1UL << CAN_F1R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F1R1_FB13                                               CAN_F1R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F1R1_FB14_Pos                                           (14U)
#define CAN_F1R1_FB14_Msk                                           (0x1UL << CAN_F1R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F1R1_FB14                                               CAN_F1R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F1R1_FB15_Pos                                           (15U)
#define CAN_F1R1_FB15_Msk                                           (0x1UL << CAN_F1R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F1R1_FB15                                               CAN_F1R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F1R1_FB16_Pos                                           (16U)
#define CAN_F1R1_FB16_Msk                                           (0x1UL << CAN_F1R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F1R1_FB16                                               CAN_F1R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F1R1_FB17_Pos                                           (17U)
#define CAN_F1R1_FB17_Msk                                           (0x1UL << CAN_F1R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F1R1_FB17                                               CAN_F1R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F1R1_FB18_Pos                                           (18U)
#define CAN_F1R1_FB18_Msk                                           (0x1UL << CAN_F1R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F1R1_FB18                                               CAN_F1R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F1R1_FB19_Pos                                           (19U)
#define CAN_F1R1_FB19_Msk                                           (0x1UL << CAN_F1R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F1R1_FB19                                               CAN_F1R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F1R1_FB20_Pos                                           (20U)
#define CAN_F1R1_FB20_Msk                                           (0x1UL << CAN_F1R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F1R1_FB20                                               CAN_F1R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F1R1_FB21_Pos                                           (21U)
#define CAN_F1R1_FB21_Msk                                           (0x1UL << CAN_F1R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F1R1_FB21                                               CAN_F1R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F1R1_FB22_Pos                                           (22U)
#define CAN_F1R1_FB22_Msk                                           (0x1UL << CAN_F1R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F1R1_FB22                                               CAN_F1R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F1R1_FB23_Pos                                           (23U)
#define CAN_F1R1_FB23_Msk                                           (0x1UL << CAN_F1R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F1R1_FB23                                               CAN_F1R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F1R1_FB24_Pos                                           (24U)
#define CAN_F1R1_FB24_Msk                                           (0x1UL << CAN_F1R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F1R1_FB24                                               CAN_F1R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F1R1_FB25_Pos                                           (25U)
#define CAN_F1R1_FB25_Msk                                           (0x1UL << CAN_F1R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F1R1_FB25                                               CAN_F1R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F1R1_FB26_Pos                                           (26U)
#define CAN_F1R1_FB26_Msk                                           (0x1UL << CAN_F1R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F1R1_FB26                                               CAN_F1R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F1R1_FB27_Pos                                           (27U)
#define CAN_F1R1_FB27_Msk                                           (0x1UL << CAN_F1R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F1R1_FB27                                               CAN_F1R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F1R1_FB28_Pos                                           (28U)
#define CAN_F1R1_FB28_Msk                                           (0x1UL << CAN_F1R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F1R1_FB28                                               CAN_F1R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F1R1_FB29_Pos                                           (29U)
#define CAN_F1R1_FB29_Msk                                           (0x1UL << CAN_F1R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F1R1_FB29                                               CAN_F1R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F1R1_FB30_Pos                                           (30U)
#define CAN_F1R1_FB30_Msk                                           (0x1UL << CAN_F1R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F1R1_FB30                                               CAN_F1R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F1R1_FB31_Pos                                           (31U)
#define CAN_F1R1_FB31_Msk                                           (0x1UL << CAN_F1R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F1R1_FB31                                               CAN_F1R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F2R1 register  *******************/
#define CAN_F2R1_FB0_Pos                                            (0U)
#define CAN_F2R1_FB0_Msk                                            (0x1UL << CAN_F2R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F2R1_FB0                                                CAN_F2R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F2R1_FB1_Pos                                            (1U)
#define CAN_F2R1_FB1_Msk                                            (0x1UL << CAN_F2R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F2R1_FB1                                                CAN_F2R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F2R1_FB2_Pos                                            (2U)
#define CAN_F2R1_FB2_Msk                                            (0x1UL << CAN_F2R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F2R1_FB2                                                CAN_F2R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F2R1_FB3_Pos                                            (3U)
#define CAN_F2R1_FB3_Msk                                            (0x1UL << CAN_F2R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F2R1_FB3                                                CAN_F2R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F2R1_FB4_Pos                                            (4U)
#define CAN_F2R1_FB4_Msk                                            (0x1UL << CAN_F2R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F2R1_FB4                                                CAN_F2R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F2R1_FB5_Pos                                            (5U)
#define CAN_F2R1_FB5_Msk                                            (0x1UL << CAN_F2R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F2R1_FB5                                                CAN_F2R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F2R1_FB6_Pos                                            (6U)
#define CAN_F2R1_FB6_Msk                                            (0x1UL << CAN_F2R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F2R1_FB6                                                CAN_F2R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F2R1_FB7_Pos                                            (7U)
#define CAN_F2R1_FB7_Msk                                            (0x1UL << CAN_F2R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F2R1_FB7                                                CAN_F2R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F2R1_FB8_Pos                                            (8U)
#define CAN_F2R1_FB8_Msk                                            (0x1UL << CAN_F2R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F2R1_FB8                                                CAN_F2R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F2R1_FB9_Pos                                            (9U)
#define CAN_F2R1_FB9_Msk                                            (0x1UL << CAN_F2R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F2R1_FB9                                                CAN_F2R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F2R1_FB10_Pos                                           (10U)
#define CAN_F2R1_FB10_Msk                                           (0x1UL << CAN_F2R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F2R1_FB10                                               CAN_F2R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F2R1_FB11_Pos                                           (11U)
#define CAN_F2R1_FB11_Msk                                           (0x1UL << CAN_F2R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F2R1_FB11                                               CAN_F2R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F2R1_FB12_Pos                                           (12U)
#define CAN_F2R1_FB12_Msk                                           (0x1UL << CAN_F2R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F2R1_FB12                                               CAN_F2R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F2R1_FB13_Pos                                           (13U)
#define CAN_F2R1_FB13_Msk                                           (0x1UL << CAN_F2R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F2R1_FB13                                               CAN_F2R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F2R1_FB14_Pos                                           (14U)
#define CAN_F2R1_FB14_Msk                                           (0x1UL << CAN_F2R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F2R1_FB14                                               CAN_F2R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F2R1_FB15_Pos                                           (15U)
#define CAN_F2R1_FB15_Msk                                           (0x1UL << CAN_F2R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F2R1_FB15                                               CAN_F2R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F2R1_FB16_Pos                                           (16U)
#define CAN_F2R1_FB16_Msk                                           (0x1UL << CAN_F2R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F2R1_FB16                                               CAN_F2R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F2R1_FB17_Pos                                           (17U)
#define CAN_F2R1_FB17_Msk                                           (0x1UL << CAN_F2R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F2R1_FB17                                               CAN_F2R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F2R1_FB18_Pos                                           (18U)
#define CAN_F2R1_FB18_Msk                                           (0x1UL << CAN_F2R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F2R1_FB18                                               CAN_F2R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F2R1_FB19_Pos                                           (19U)
#define CAN_F2R1_FB19_Msk                                           (0x1UL << CAN_F2R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F2R1_FB19                                               CAN_F2R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F2R1_FB20_Pos                                           (20U)
#define CAN_F2R1_FB20_Msk                                           (0x1UL << CAN_F2R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F2R1_FB20                                               CAN_F2R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F2R1_FB21_Pos                                           (21U)
#define CAN_F2R1_FB21_Msk                                           (0x1UL << CAN_F2R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F2R1_FB21                                               CAN_F2R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F2R1_FB22_Pos                                           (22U)
#define CAN_F2R1_FB22_Msk                                           (0x1UL << CAN_F2R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F2R1_FB22                                               CAN_F2R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F2R1_FB23_Pos                                           (23U)
#define CAN_F2R1_FB23_Msk                                           (0x1UL << CAN_F2R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F2R1_FB23                                               CAN_F2R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F2R1_FB24_Pos                                           (24U)
#define CAN_F2R1_FB24_Msk                                           (0x1UL << CAN_F2R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F2R1_FB24                                               CAN_F2R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F2R1_FB25_Pos                                           (25U)
#define CAN_F2R1_FB25_Msk                                           (0x1UL << CAN_F2R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F2R1_FB25                                               CAN_F2R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F2R1_FB26_Pos                                           (26U)
#define CAN_F2R1_FB26_Msk                                           (0x1UL << CAN_F2R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F2R1_FB26                                               CAN_F2R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F2R1_FB27_Pos                                           (27U)
#define CAN_F2R1_FB27_Msk                                           (0x1UL << CAN_F2R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F2R1_FB27                                               CAN_F2R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F2R1_FB28_Pos                                           (28U)
#define CAN_F2R1_FB28_Msk                                           (0x1UL << CAN_F2R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F2R1_FB28                                               CAN_F2R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F2R1_FB29_Pos                                           (29U)
#define CAN_F2R1_FB29_Msk                                           (0x1UL << CAN_F2R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F2R1_FB29                                               CAN_F2R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F2R1_FB30_Pos                                           (30U)
#define CAN_F2R1_FB30_Msk                                           (0x1UL << CAN_F2R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F2R1_FB30                                               CAN_F2R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F2R1_FB31_Pos                                           (31U)
#define CAN_F2R1_FB31_Msk                                           (0x1UL << CAN_F2R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F2R1_FB31                                               CAN_F2R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F3R1 register  *******************/
#define CAN_F3R1_FB0_Pos                                            (0U)
#define CAN_F3R1_FB0_Msk                                            (0x1UL << CAN_F3R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F3R1_FB0                                                CAN_F3R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F3R1_FB1_Pos                                            (1U)
#define CAN_F3R1_FB1_Msk                                            (0x1UL << CAN_F3R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F3R1_FB1                                                CAN_F3R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F3R1_FB2_Pos                                            (2U)
#define CAN_F3R1_FB2_Msk                                            (0x1UL << CAN_F3R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F3R1_FB2                                                CAN_F3R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F3R1_FB3_Pos                                            (3U)
#define CAN_F3R1_FB3_Msk                                            (0x1UL << CAN_F3R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F3R1_FB3                                                CAN_F3R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F3R1_FB4_Pos                                            (4U)
#define CAN_F3R1_FB4_Msk                                            (0x1UL << CAN_F3R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F3R1_FB4                                                CAN_F3R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F3R1_FB5_Pos                                            (5U)
#define CAN_F3R1_FB5_Msk                                            (0x1UL << CAN_F3R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F3R1_FB5                                                CAN_F3R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F3R1_FB6_Pos                                            (6U)
#define CAN_F3R1_FB6_Msk                                            (0x1UL << CAN_F3R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F3R1_FB6                                                CAN_F3R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F3R1_FB7_Pos                                            (7U)
#define CAN_F3R1_FB7_Msk                                            (0x1UL << CAN_F3R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F3R1_FB7                                                CAN_F3R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F3R1_FB8_Pos                                            (8U)
#define CAN_F3R1_FB8_Msk                                            (0x1UL << CAN_F3R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F3R1_FB8                                                CAN_F3R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F3R1_FB9_Pos                                            (9U)
#define CAN_F3R1_FB9_Msk                                            (0x1UL << CAN_F3R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F3R1_FB9                                                CAN_F3R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F3R1_FB10_Pos                                           (10U)
#define CAN_F3R1_FB10_Msk                                           (0x1UL << CAN_F3R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F3R1_FB10                                               CAN_F3R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F3R1_FB11_Pos                                           (11U)
#define CAN_F3R1_FB11_Msk                                           (0x1UL << CAN_F3R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F3R1_FB11                                               CAN_F3R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F3R1_FB12_Pos                                           (12U)
#define CAN_F3R1_FB12_Msk                                           (0x1UL << CAN_F3R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F3R1_FB12                                               CAN_F3R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F3R1_FB13_Pos                                           (13U)
#define CAN_F3R1_FB13_Msk                                           (0x1UL << CAN_F3R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F3R1_FB13                                               CAN_F3R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F3R1_FB14_Pos                                           (14U)
#define CAN_F3R1_FB14_Msk                                           (0x1UL << CAN_F3R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F3R1_FB14                                               CAN_F3R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F3R1_FB15_Pos                                           (15U)
#define CAN_F3R1_FB15_Msk                                           (0x1UL << CAN_F3R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F3R1_FB15                                               CAN_F3R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F3R1_FB16_Pos                                           (16U)
#define CAN_F3R1_FB16_Msk                                           (0x1UL << CAN_F3R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F3R1_FB16                                               CAN_F3R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F3R1_FB17_Pos                                           (17U)
#define CAN_F3R1_FB17_Msk                                           (0x1UL << CAN_F3R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F3R1_FB17                                               CAN_F3R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F3R1_FB18_Pos                                           (18U)
#define CAN_F3R1_FB18_Msk                                           (0x1UL << CAN_F3R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F3R1_FB18                                               CAN_F3R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F3R1_FB19_Pos                                           (19U)
#define CAN_F3R1_FB19_Msk                                           (0x1UL << CAN_F3R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F3R1_FB19                                               CAN_F3R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F3R1_FB20_Pos                                           (20U)
#define CAN_F3R1_FB20_Msk                                           (0x1UL << CAN_F3R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F3R1_FB20                                               CAN_F3R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F3R1_FB21_Pos                                           (21U)
#define CAN_F3R1_FB21_Msk                                           (0x1UL << CAN_F3R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F3R1_FB21                                               CAN_F3R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F3R1_FB22_Pos                                           (22U)
#define CAN_F3R1_FB22_Msk                                           (0x1UL << CAN_F3R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F3R1_FB22                                               CAN_F3R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F3R1_FB23_Pos                                           (23U)
#define CAN_F3R1_FB23_Msk                                           (0x1UL << CAN_F3R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F3R1_FB23                                               CAN_F3R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F3R1_FB24_Pos                                           (24U)
#define CAN_F3R1_FB24_Msk                                           (0x1UL << CAN_F3R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F3R1_FB24                                               CAN_F3R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F3R1_FB25_Pos                                           (25U)
#define CAN_F3R1_FB25_Msk                                           (0x1UL << CAN_F3R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F3R1_FB25                                               CAN_F3R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F3R1_FB26_Pos                                           (26U)
#define CAN_F3R1_FB26_Msk                                           (0x1UL << CAN_F3R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F3R1_FB26                                               CAN_F3R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F3R1_FB27_Pos                                           (27U)
#define CAN_F3R1_FB27_Msk                                           (0x1UL << CAN_F3R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F3R1_FB27                                               CAN_F3R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F3R1_FB28_Pos                                           (28U)
#define CAN_F3R1_FB28_Msk                                           (0x1UL << CAN_F3R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F3R1_FB28                                               CAN_F3R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F3R1_FB29_Pos                                           (29U)
#define CAN_F3R1_FB29_Msk                                           (0x1UL << CAN_F3R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F3R1_FB29                                               CAN_F3R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F3R1_FB30_Pos                                           (30U)
#define CAN_F3R1_FB30_Msk                                           (0x1UL << CAN_F3R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F3R1_FB30                                               CAN_F3R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F3R1_FB31_Pos                                           (31U)
#define CAN_F3R1_FB31_Msk                                           (0x1UL << CAN_F3R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F3R1_FB31                                               CAN_F3R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F4R1 register  *******************/
#define CAN_F4R1_FB0_Pos                                            (0U)
#define CAN_F4R1_FB0_Msk                                            (0x1UL << CAN_F4R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F4R1_FB0                                                CAN_F4R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F4R1_FB1_Pos                                            (1U)
#define CAN_F4R1_FB1_Msk                                            (0x1UL << CAN_F4R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F4R1_FB1                                                CAN_F4R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F4R1_FB2_Pos                                            (2U)
#define CAN_F4R1_FB2_Msk                                            (0x1UL << CAN_F4R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F4R1_FB2                                                CAN_F4R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F4R1_FB3_Pos                                            (3U)
#define CAN_F4R1_FB3_Msk                                            (0x1UL << CAN_F4R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F4R1_FB3                                                CAN_F4R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F4R1_FB4_Pos                                            (4U)
#define CAN_F4R1_FB4_Msk                                            (0x1UL << CAN_F4R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F4R1_FB4                                                CAN_F4R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F4R1_FB5_Pos                                            (5U)
#define CAN_F4R1_FB5_Msk                                            (0x1UL << CAN_F4R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F4R1_FB5                                                CAN_F4R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F4R1_FB6_Pos                                            (6U)
#define CAN_F4R1_FB6_Msk                                            (0x1UL << CAN_F4R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F4R1_FB6                                                CAN_F4R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F4R1_FB7_Pos                                            (7U)
#define CAN_F4R1_FB7_Msk                                            (0x1UL << CAN_F4R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F4R1_FB7                                                CAN_F4R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F4R1_FB8_Pos                                            (8U)
#define CAN_F4R1_FB8_Msk                                            (0x1UL << CAN_F4R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F4R1_FB8                                                CAN_F4R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F4R1_FB9_Pos                                            (9U)
#define CAN_F4R1_FB9_Msk                                            (0x1UL << CAN_F4R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F4R1_FB9                                                CAN_F4R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F4R1_FB10_Pos                                           (10U)
#define CAN_F4R1_FB10_Msk                                           (0x1UL << CAN_F4R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F4R1_FB10                                               CAN_F4R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F4R1_FB11_Pos                                           (11U)
#define CAN_F4R1_FB11_Msk                                           (0x1UL << CAN_F4R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F4R1_FB11                                               CAN_F4R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F4R1_FB12_Pos                                           (12U)
#define CAN_F4R1_FB12_Msk                                           (0x1UL << CAN_F4R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F4R1_FB12                                               CAN_F4R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F4R1_FB13_Pos                                           (13U)
#define CAN_F4R1_FB13_Msk                                           (0x1UL << CAN_F4R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F4R1_FB13                                               CAN_F4R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F4R1_FB14_Pos                                           (14U)
#define CAN_F4R1_FB14_Msk                                           (0x1UL << CAN_F4R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F4R1_FB14                                               CAN_F4R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F4R1_FB15_Pos                                           (15U)
#define CAN_F4R1_FB15_Msk                                           (0x1UL << CAN_F4R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F4R1_FB15                                               CAN_F4R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F4R1_FB16_Pos                                           (16U)
#define CAN_F4R1_FB16_Msk                                           (0x1UL << CAN_F4R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F4R1_FB16                                               CAN_F4R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F4R1_FB17_Pos                                           (17U)
#define CAN_F4R1_FB17_Msk                                           (0x1UL << CAN_F4R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F4R1_FB17                                               CAN_F4R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F4R1_FB18_Pos                                           (18U)
#define CAN_F4R1_FB18_Msk                                           (0x1UL << CAN_F4R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F4R1_FB18                                               CAN_F4R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F4R1_FB19_Pos                                           (19U)
#define CAN_F4R1_FB19_Msk                                           (0x1UL << CAN_F4R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F4R1_FB19                                               CAN_F4R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F4R1_FB20_Pos                                           (20U)
#define CAN_F4R1_FB20_Msk                                           (0x1UL << CAN_F4R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F4R1_FB20                                               CAN_F4R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F4R1_FB21_Pos                                           (21U)
#define CAN_F4R1_FB21_Msk                                           (0x1UL << CAN_F4R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F4R1_FB21                                               CAN_F4R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F4R1_FB22_Pos                                           (22U)
#define CAN_F4R1_FB22_Msk                                           (0x1UL << CAN_F4R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F4R1_FB22                                               CAN_F4R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F4R1_FB23_Pos                                           (23U)
#define CAN_F4R1_FB23_Msk                                           (0x1UL << CAN_F4R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F4R1_FB23                                               CAN_F4R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F4R1_FB24_Pos                                           (24U)
#define CAN_F4R1_FB24_Msk                                           (0x1UL << CAN_F4R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F4R1_FB24                                               CAN_F4R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F4R1_FB25_Pos                                           (25U)
#define CAN_F4R1_FB25_Msk                                           (0x1UL << CAN_F4R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F4R1_FB25                                               CAN_F4R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F4R1_FB26_Pos                                           (26U)
#define CAN_F4R1_FB26_Msk                                           (0x1UL << CAN_F4R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F4R1_FB26                                               CAN_F4R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F4R1_FB27_Pos                                           (27U)
#define CAN_F4R1_FB27_Msk                                           (0x1UL << CAN_F4R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F4R1_FB27                                               CAN_F4R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F4R1_FB28_Pos                                           (28U)
#define CAN_F4R1_FB28_Msk                                           (0x1UL << CAN_F4R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F4R1_FB28                                               CAN_F4R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F4R1_FB29_Pos                                           (29U)
#define CAN_F4R1_FB29_Msk                                           (0x1UL << CAN_F4R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F4R1_FB29                                               CAN_F4R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F4R1_FB30_Pos                                           (30U)
#define CAN_F4R1_FB30_Msk                                           (0x1UL << CAN_F4R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F4R1_FB30                                               CAN_F4R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F4R1_FB31_Pos                                           (31U)
#define CAN_F4R1_FB31_Msk                                           (0x1UL << CAN_F4R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F4R1_FB31                                               CAN_F4R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F5R1 register  *******************/
#define CAN_F5R1_FB0_Pos                                            (0U)
#define CAN_F5R1_FB0_Msk                                            (0x1UL << CAN_F5R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F5R1_FB0                                                CAN_F5R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F5R1_FB1_Pos                                            (1U)
#define CAN_F5R1_FB1_Msk                                            (0x1UL << CAN_F5R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F5R1_FB1                                                CAN_F5R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F5R1_FB2_Pos                                            (2U)
#define CAN_F5R1_FB2_Msk                                            (0x1UL << CAN_F5R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F5R1_FB2                                                CAN_F5R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F5R1_FB3_Pos                                            (3U)
#define CAN_F5R1_FB3_Msk                                            (0x1UL << CAN_F5R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F5R1_FB3                                                CAN_F5R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F5R1_FB4_Pos                                            (4U)
#define CAN_F5R1_FB4_Msk                                            (0x1UL << CAN_F5R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F5R1_FB4                                                CAN_F5R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F5R1_FB5_Pos                                            (5U)
#define CAN_F5R1_FB5_Msk                                            (0x1UL << CAN_F5R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F5R1_FB5                                                CAN_F5R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F5R1_FB6_Pos                                            (6U)
#define CAN_F5R1_FB6_Msk                                            (0x1UL << CAN_F5R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F5R1_FB6                                                CAN_F5R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F5R1_FB7_Pos                                            (7U)
#define CAN_F5R1_FB7_Msk                                            (0x1UL << CAN_F5R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F5R1_FB7                                                CAN_F5R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F5R1_FB8_Pos                                            (8U)
#define CAN_F5R1_FB8_Msk                                            (0x1UL << CAN_F5R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F5R1_FB8                                                CAN_F5R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F5R1_FB9_Pos                                            (9U)
#define CAN_F5R1_FB9_Msk                                            (0x1UL << CAN_F5R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F5R1_FB9                                                CAN_F5R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F5R1_FB10_Pos                                           (10U)
#define CAN_F5R1_FB10_Msk                                           (0x1UL << CAN_F5R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F5R1_FB10                                               CAN_F5R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F5R1_FB11_Pos                                           (11U)
#define CAN_F5R1_FB11_Msk                                           (0x1UL << CAN_F5R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F5R1_FB11                                               CAN_F5R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F5R1_FB12_Pos                                           (12U)
#define CAN_F5R1_FB12_Msk                                           (0x1UL << CAN_F5R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F5R1_FB12                                               CAN_F5R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F5R1_FB13_Pos                                           (13U)
#define CAN_F5R1_FB13_Msk                                           (0x1UL << CAN_F5R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F5R1_FB13                                               CAN_F5R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F5R1_FB14_Pos                                           (14U)
#define CAN_F5R1_FB14_Msk                                           (0x1UL << CAN_F5R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F5R1_FB14                                               CAN_F5R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F5R1_FB15_Pos                                           (15U)
#define CAN_F5R1_FB15_Msk                                           (0x1UL << CAN_F5R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F5R1_FB15                                               CAN_F5R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F5R1_FB16_Pos                                           (16U)
#define CAN_F5R1_FB16_Msk                                           (0x1UL << CAN_F5R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F5R1_FB16                                               CAN_F5R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F5R1_FB17_Pos                                           (17U)
#define CAN_F5R1_FB17_Msk                                           (0x1UL << CAN_F5R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F5R1_FB17                                               CAN_F5R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F5R1_FB18_Pos                                           (18U)
#define CAN_F5R1_FB18_Msk                                           (0x1UL << CAN_F5R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F5R1_FB18                                               CAN_F5R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F5R1_FB19_Pos                                           (19U)
#define CAN_F5R1_FB19_Msk                                           (0x1UL << CAN_F5R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F5R1_FB19                                               CAN_F5R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F5R1_FB20_Pos                                           (20U)
#define CAN_F5R1_FB20_Msk                                           (0x1UL << CAN_F5R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F5R1_FB20                                               CAN_F5R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F5R1_FB21_Pos                                           (21U)
#define CAN_F5R1_FB21_Msk                                           (0x1UL << CAN_F5R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F5R1_FB21                                               CAN_F5R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F5R1_FB22_Pos                                           (22U)
#define CAN_F5R1_FB22_Msk                                           (0x1UL << CAN_F5R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F5R1_FB22                                               CAN_F5R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F5R1_FB23_Pos                                           (23U)
#define CAN_F5R1_FB23_Msk                                           (0x1UL << CAN_F5R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F5R1_FB23                                               CAN_F5R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F5R1_FB24_Pos                                           (24U)
#define CAN_F5R1_FB24_Msk                                           (0x1UL << CAN_F5R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F5R1_FB24                                               CAN_F5R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F5R1_FB25_Pos                                           (25U)
#define CAN_F5R1_FB25_Msk                                           (0x1UL << CAN_F5R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F5R1_FB25                                               CAN_F5R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F5R1_FB26_Pos                                           (26U)
#define CAN_F5R1_FB26_Msk                                           (0x1UL << CAN_F5R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F5R1_FB26                                               CAN_F5R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F5R1_FB27_Pos                                           (27U)
#define CAN_F5R1_FB27_Msk                                           (0x1UL << CAN_F5R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F5R1_FB27                                               CAN_F5R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F5R1_FB28_Pos                                           (28U)
#define CAN_F5R1_FB28_Msk                                           (0x1UL << CAN_F5R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F5R1_FB28                                               CAN_F5R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F5R1_FB29_Pos                                           (29U)
#define CAN_F5R1_FB29_Msk                                           (0x1UL << CAN_F5R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F5R1_FB29                                               CAN_F5R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F5R1_FB30_Pos                                           (30U)
#define CAN_F5R1_FB30_Msk                                           (0x1UL << CAN_F5R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F5R1_FB30                                               CAN_F5R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F5R1_FB31_Pos                                           (31U)
#define CAN_F5R1_FB31_Msk                                           (0x1UL << CAN_F5R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F5R1_FB31                                               CAN_F5R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F6R1 register  *******************/
#define CAN_F6R1_FB0_Pos                                            (0U)
#define CAN_F6R1_FB0_Msk                                            (0x1UL << CAN_F6R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F6R1_FB0                                                CAN_F6R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F6R1_FB1_Pos                                            (1U)
#define CAN_F6R1_FB1_Msk                                            (0x1UL << CAN_F6R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F6R1_FB1                                                CAN_F6R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F6R1_FB2_Pos                                            (2U)
#define CAN_F6R1_FB2_Msk                                            (0x1UL << CAN_F6R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F6R1_FB2                                                CAN_F6R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F6R1_FB3_Pos                                            (3U)
#define CAN_F6R1_FB3_Msk                                            (0x1UL << CAN_F6R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F6R1_FB3                                                CAN_F6R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F6R1_FB4_Pos                                            (4U)
#define CAN_F6R1_FB4_Msk                                            (0x1UL << CAN_F6R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F6R1_FB4                                                CAN_F6R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F6R1_FB5_Pos                                            (5U)
#define CAN_F6R1_FB5_Msk                                            (0x1UL << CAN_F6R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F6R1_FB5                                                CAN_F6R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F6R1_FB6_Pos                                            (6U)
#define CAN_F6R1_FB6_Msk                                            (0x1UL << CAN_F6R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F6R1_FB6                                                CAN_F6R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F6R1_FB7_Pos                                            (7U)
#define CAN_F6R1_FB7_Msk                                            (0x1UL << CAN_F6R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F6R1_FB7                                                CAN_F6R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F6R1_FB8_Pos                                            (8U)
#define CAN_F6R1_FB8_Msk                                            (0x1UL << CAN_F6R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F6R1_FB8                                                CAN_F6R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F6R1_FB9_Pos                                            (9U)
#define CAN_F6R1_FB9_Msk                                            (0x1UL << CAN_F6R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F6R1_FB9                                                CAN_F6R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F6R1_FB10_Pos                                           (10U)
#define CAN_F6R1_FB10_Msk                                           (0x1UL << CAN_F6R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F6R1_FB10                                               CAN_F6R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F6R1_FB11_Pos                                           (11U)
#define CAN_F6R1_FB11_Msk                                           (0x1UL << CAN_F6R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F6R1_FB11                                               CAN_F6R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F6R1_FB12_Pos                                           (12U)
#define CAN_F6R1_FB12_Msk                                           (0x1UL << CAN_F6R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F6R1_FB12                                               CAN_F6R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F6R1_FB13_Pos                                           (13U)
#define CAN_F6R1_FB13_Msk                                           (0x1UL << CAN_F6R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F6R1_FB13                                               CAN_F6R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F6R1_FB14_Pos                                           (14U)
#define CAN_F6R1_FB14_Msk                                           (0x1UL << CAN_F6R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F6R1_FB14                                               CAN_F6R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F6R1_FB15_Pos                                           (15U)
#define CAN_F6R1_FB15_Msk                                           (0x1UL << CAN_F6R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F6R1_FB15                                               CAN_F6R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F6R1_FB16_Pos                                           (16U)
#define CAN_F6R1_FB16_Msk                                           (0x1UL << CAN_F6R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F6R1_FB16                                               CAN_F6R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F6R1_FB17_Pos                                           (17U)
#define CAN_F6R1_FB17_Msk                                           (0x1UL << CAN_F6R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F6R1_FB17                                               CAN_F6R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F6R1_FB18_Pos                                           (18U)
#define CAN_F6R1_FB18_Msk                                           (0x1UL << CAN_F6R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F6R1_FB18                                               CAN_F6R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F6R1_FB19_Pos                                           (19U)
#define CAN_F6R1_FB19_Msk                                           (0x1UL << CAN_F6R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F6R1_FB19                                               CAN_F6R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F6R1_FB20_Pos                                           (20U)
#define CAN_F6R1_FB20_Msk                                           (0x1UL << CAN_F6R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F6R1_FB20                                               CAN_F6R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F6R1_FB21_Pos                                           (21U)
#define CAN_F6R1_FB21_Msk                                           (0x1UL << CAN_F6R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F6R1_FB21                                               CAN_F6R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F6R1_FB22_Pos                                           (22U)
#define CAN_F6R1_FB22_Msk                                           (0x1UL << CAN_F6R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F6R1_FB22                                               CAN_F6R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F6R1_FB23_Pos                                           (23U)
#define CAN_F6R1_FB23_Msk                                           (0x1UL << CAN_F6R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F6R1_FB23                                               CAN_F6R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F6R1_FB24_Pos                                           (24U)
#define CAN_F6R1_FB24_Msk                                           (0x1UL << CAN_F6R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F6R1_FB24                                               CAN_F6R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F6R1_FB25_Pos                                           (25U)
#define CAN_F6R1_FB25_Msk                                           (0x1UL << CAN_F6R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F6R1_FB25                                               CAN_F6R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F6R1_FB26_Pos                                           (26U)
#define CAN_F6R1_FB26_Msk                                           (0x1UL << CAN_F6R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F6R1_FB26                                               CAN_F6R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F6R1_FB27_Pos                                           (27U)
#define CAN_F6R1_FB27_Msk                                           (0x1UL << CAN_F6R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F6R1_FB27                                               CAN_F6R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F6R1_FB28_Pos                                           (28U)
#define CAN_F6R1_FB28_Msk                                           (0x1UL << CAN_F6R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F6R1_FB28                                               CAN_F6R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F6R1_FB29_Pos                                           (29U)
#define CAN_F6R1_FB29_Msk                                           (0x1UL << CAN_F6R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F6R1_FB29                                               CAN_F6R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F6R1_FB30_Pos                                           (30U)
#define CAN_F6R1_FB30_Msk                                           (0x1UL << CAN_F6R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F6R1_FB30                                               CAN_F6R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F6R1_FB31_Pos                                           (31U)
#define CAN_F6R1_FB31_Msk                                           (0x1UL << CAN_F6R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F6R1_FB31                                               CAN_F6R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F7R1 register  *******************/
#define CAN_F7R1_FB0_Pos                                            (0U)
#define CAN_F7R1_FB0_Msk                                            (0x1UL << CAN_F7R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F7R1_FB0                                                CAN_F7R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F7R1_FB1_Pos                                            (1U)
#define CAN_F7R1_FB1_Msk                                            (0x1UL << CAN_F7R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F7R1_FB1                                                CAN_F7R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F7R1_FB2_Pos                                            (2U)
#define CAN_F7R1_FB2_Msk                                            (0x1UL << CAN_F7R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F7R1_FB2                                                CAN_F7R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F7R1_FB3_Pos                                            (3U)
#define CAN_F7R1_FB3_Msk                                            (0x1UL << CAN_F7R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F7R1_FB3                                                CAN_F7R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F7R1_FB4_Pos                                            (4U)
#define CAN_F7R1_FB4_Msk                                            (0x1UL << CAN_F7R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F7R1_FB4                                                CAN_F7R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F7R1_FB5_Pos                                            (5U)
#define CAN_F7R1_FB5_Msk                                            (0x1UL << CAN_F7R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F7R1_FB5                                                CAN_F7R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F7R1_FB6_Pos                                            (6U)
#define CAN_F7R1_FB6_Msk                                            (0x1UL << CAN_F7R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F7R1_FB6                                                CAN_F7R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F7R1_FB7_Pos                                            (7U)
#define CAN_F7R1_FB7_Msk                                            (0x1UL << CAN_F7R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F7R1_FB7                                                CAN_F7R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F7R1_FB8_Pos                                            (8U)
#define CAN_F7R1_FB8_Msk                                            (0x1UL << CAN_F7R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F7R1_FB8                                                CAN_F7R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F7R1_FB9_Pos                                            (9U)
#define CAN_F7R1_FB9_Msk                                            (0x1UL << CAN_F7R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F7R1_FB9                                                CAN_F7R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F7R1_FB10_Pos                                           (10U)
#define CAN_F7R1_FB10_Msk                                           (0x1UL << CAN_F7R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F7R1_FB10                                               CAN_F7R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F7R1_FB11_Pos                                           (11U)
#define CAN_F7R1_FB11_Msk                                           (0x1UL << CAN_F7R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F7R1_FB11                                               CAN_F7R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F7R1_FB12_Pos                                           (12U)
#define CAN_F7R1_FB12_Msk                                           (0x1UL << CAN_F7R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F7R1_FB12                                               CAN_F7R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F7R1_FB13_Pos                                           (13U)
#define CAN_F7R1_FB13_Msk                                           (0x1UL << CAN_F7R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F7R1_FB13                                               CAN_F7R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F7R1_FB14_Pos                                           (14U)
#define CAN_F7R1_FB14_Msk                                           (0x1UL << CAN_F7R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F7R1_FB14                                               CAN_F7R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F7R1_FB15_Pos                                           (15U)
#define CAN_F7R1_FB15_Msk                                           (0x1UL << CAN_F7R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F7R1_FB15                                               CAN_F7R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F7R1_FB16_Pos                                           (16U)
#define CAN_F7R1_FB16_Msk                                           (0x1UL << CAN_F7R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F7R1_FB16                                               CAN_F7R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F7R1_FB17_Pos                                           (17U)
#define CAN_F7R1_FB17_Msk                                           (0x1UL << CAN_F7R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F7R1_FB17                                               CAN_F7R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F7R1_FB18_Pos                                           (18U)
#define CAN_F7R1_FB18_Msk                                           (0x1UL << CAN_F7R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F7R1_FB18                                               CAN_F7R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F7R1_FB19_Pos                                           (19U)
#define CAN_F7R1_FB19_Msk                                           (0x1UL << CAN_F7R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F7R1_FB19                                               CAN_F7R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F7R1_FB20_Pos                                           (20U)
#define CAN_F7R1_FB20_Msk                                           (0x1UL << CAN_F7R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F7R1_FB20                                               CAN_F7R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F7R1_FB21_Pos                                           (21U)
#define CAN_F7R1_FB21_Msk                                           (0x1UL << CAN_F7R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F7R1_FB21                                               CAN_F7R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F7R1_FB22_Pos                                           (22U)
#define CAN_F7R1_FB22_Msk                                           (0x1UL << CAN_F7R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F7R1_FB22                                               CAN_F7R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F7R1_FB23_Pos                                           (23U)
#define CAN_F7R1_FB23_Msk                                           (0x1UL << CAN_F7R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F7R1_FB23                                               CAN_F7R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F7R1_FB24_Pos                                           (24U)
#define CAN_F7R1_FB24_Msk                                           (0x1UL << CAN_F7R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F7R1_FB24                                               CAN_F7R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F7R1_FB25_Pos                                           (25U)
#define CAN_F7R1_FB25_Msk                                           (0x1UL << CAN_F7R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F7R1_FB25                                               CAN_F7R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F7R1_FB26_Pos                                           (26U)
#define CAN_F7R1_FB26_Msk                                           (0x1UL << CAN_F7R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F7R1_FB26                                               CAN_F7R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F7R1_FB27_Pos                                           (27U)
#define CAN_F7R1_FB27_Msk                                           (0x1UL << CAN_F7R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F7R1_FB27                                               CAN_F7R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F7R1_FB28_Pos                                           (28U)
#define CAN_F7R1_FB28_Msk                                           (0x1UL << CAN_F7R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F7R1_FB28                                               CAN_F7R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F7R1_FB29_Pos                                           (29U)
#define CAN_F7R1_FB29_Msk                                           (0x1UL << CAN_F7R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F7R1_FB29                                               CAN_F7R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F7R1_FB30_Pos                                           (30U)
#define CAN_F7R1_FB30_Msk                                           (0x1UL << CAN_F7R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F7R1_FB30                                               CAN_F7R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F7R1_FB31_Pos                                           (31U)
#define CAN_F7R1_FB31_Msk                                           (0x1UL << CAN_F7R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F7R1_FB31                                               CAN_F7R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F8R1 register  *******************/
#define CAN_F8R1_FB0_Pos                                            (0U)
#define CAN_F8R1_FB0_Msk                                            (0x1UL << CAN_F8R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F8R1_FB0                                                CAN_F8R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F8R1_FB1_Pos                                            (1U)
#define CAN_F8R1_FB1_Msk                                            (0x1UL << CAN_F8R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F8R1_FB1                                                CAN_F8R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F8R1_FB2_Pos                                            (2U)
#define CAN_F8R1_FB2_Msk                                            (0x1UL << CAN_F8R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F8R1_FB2                                                CAN_F8R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F8R1_FB3_Pos                                            (3U)
#define CAN_F8R1_FB3_Msk                                            (0x1UL << CAN_F8R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F8R1_FB3                                                CAN_F8R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F8R1_FB4_Pos                                            (4U)
#define CAN_F8R1_FB4_Msk                                            (0x1UL << CAN_F8R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F8R1_FB4                                                CAN_F8R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F8R1_FB5_Pos                                            (5U)
#define CAN_F8R1_FB5_Msk                                            (0x1UL << CAN_F8R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F8R1_FB5                                                CAN_F8R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F8R1_FB6_Pos                                            (6U)
#define CAN_F8R1_FB6_Msk                                            (0x1UL << CAN_F8R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F8R1_FB6                                                CAN_F8R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F8R1_FB7_Pos                                            (7U)
#define CAN_F8R1_FB7_Msk                                            (0x1UL << CAN_F8R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F8R1_FB7                                                CAN_F8R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F8R1_FB8_Pos                                            (8U)
#define CAN_F8R1_FB8_Msk                                            (0x1UL << CAN_F8R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F8R1_FB8                                                CAN_F8R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F8R1_FB9_Pos                                            (9U)
#define CAN_F8R1_FB9_Msk                                            (0x1UL << CAN_F8R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F8R1_FB9                                                CAN_F8R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F8R1_FB10_Pos                                           (10U)
#define CAN_F8R1_FB10_Msk                                           (0x1UL << CAN_F8R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F8R1_FB10                                               CAN_F8R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F8R1_FB11_Pos                                           (11U)
#define CAN_F8R1_FB11_Msk                                           (0x1UL << CAN_F8R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F8R1_FB11                                               CAN_F8R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F8R1_FB12_Pos                                           (12U)
#define CAN_F8R1_FB12_Msk                                           (0x1UL << CAN_F8R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F8R1_FB12                                               CAN_F8R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F8R1_FB13_Pos                                           (13U)
#define CAN_F8R1_FB13_Msk                                           (0x1UL << CAN_F8R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F8R1_FB13                                               CAN_F8R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F8R1_FB14_Pos                                           (14U)
#define CAN_F8R1_FB14_Msk                                           (0x1UL << CAN_F8R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F8R1_FB14                                               CAN_F8R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F8R1_FB15_Pos                                           (15U)
#define CAN_F8R1_FB15_Msk                                           (0x1UL << CAN_F8R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F8R1_FB15                                               CAN_F8R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F8R1_FB16_Pos                                           (16U)
#define CAN_F8R1_FB16_Msk                                           (0x1UL << CAN_F8R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F8R1_FB16                                               CAN_F8R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F8R1_FB17_Pos                                           (17U)
#define CAN_F8R1_FB17_Msk                                           (0x1UL << CAN_F8R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F8R1_FB17                                               CAN_F8R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F8R1_FB18_Pos                                           (18U)
#define CAN_F8R1_FB18_Msk                                           (0x1UL << CAN_F8R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F8R1_FB18                                               CAN_F8R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F8R1_FB19_Pos                                           (19U)
#define CAN_F8R1_FB19_Msk                                           (0x1UL << CAN_F8R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F8R1_FB19                                               CAN_F8R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F8R1_FB20_Pos                                           (20U)
#define CAN_F8R1_FB20_Msk                                           (0x1UL << CAN_F8R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F8R1_FB20                                               CAN_F8R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F8R1_FB21_Pos                                           (21U)
#define CAN_F8R1_FB21_Msk                                           (0x1UL << CAN_F8R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F8R1_FB21                                               CAN_F8R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F8R1_FB22_Pos                                           (22U)
#define CAN_F8R1_FB22_Msk                                           (0x1UL << CAN_F8R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F8R1_FB22                                               CAN_F8R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F8R1_FB23_Pos                                           (23U)
#define CAN_F8R1_FB23_Msk                                           (0x1UL << CAN_F8R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F8R1_FB23                                               CAN_F8R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F8R1_FB24_Pos                                           (24U)
#define CAN_F8R1_FB24_Msk                                           (0x1UL << CAN_F8R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F8R1_FB24                                               CAN_F8R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F8R1_FB25_Pos                                           (25U)
#define CAN_F8R1_FB25_Msk                                           (0x1UL << CAN_F8R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F8R1_FB25                                               CAN_F8R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F8R1_FB26_Pos                                           (26U)
#define CAN_F8R1_FB26_Msk                                           (0x1UL << CAN_F8R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F8R1_FB26                                               CAN_F8R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F8R1_FB27_Pos                                           (27U)
#define CAN_F8R1_FB27_Msk                                           (0x1UL << CAN_F8R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F8R1_FB27                                               CAN_F8R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F8R1_FB28_Pos                                           (28U)
#define CAN_F8R1_FB28_Msk                                           (0x1UL << CAN_F8R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F8R1_FB28                                               CAN_F8R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F8R1_FB29_Pos                                           (29U)
#define CAN_F8R1_FB29_Msk                                           (0x1UL << CAN_F8R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F8R1_FB29                                               CAN_F8R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F8R1_FB30_Pos                                           (30U)
#define CAN_F8R1_FB30_Msk                                           (0x1UL << CAN_F8R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F8R1_FB30                                               CAN_F8R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F8R1_FB31_Pos                                           (31U)
#define CAN_F8R1_FB31_Msk                                           (0x1UL << CAN_F8R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F8R1_FB31                                               CAN_F8R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F9R1 register  *******************/
#define CAN_F9R1_FB0_Pos                                            (0U)
#define CAN_F9R1_FB0_Msk                                            (0x1UL << CAN_F9R1_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F9R1_FB0                                                CAN_F9R1_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F9R1_FB1_Pos                                            (1U)
#define CAN_F9R1_FB1_Msk                                            (0x1UL << CAN_F9R1_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F9R1_FB1                                                CAN_F9R1_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F9R1_FB2_Pos                                            (2U)
#define CAN_F9R1_FB2_Msk                                            (0x1UL << CAN_F9R1_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F9R1_FB2                                                CAN_F9R1_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F9R1_FB3_Pos                                            (3U)
#define CAN_F9R1_FB3_Msk                                            (0x1UL << CAN_F9R1_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F9R1_FB3                                                CAN_F9R1_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F9R1_FB4_Pos                                            (4U)
#define CAN_F9R1_FB4_Msk                                            (0x1UL << CAN_F9R1_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F9R1_FB4                                                CAN_F9R1_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F9R1_FB5_Pos                                            (5U)
#define CAN_F9R1_FB5_Msk                                            (0x1UL << CAN_F9R1_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F9R1_FB5                                                CAN_F9R1_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F9R1_FB6_Pos                                            (6U)
#define CAN_F9R1_FB6_Msk                                            (0x1UL << CAN_F9R1_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F9R1_FB6                                                CAN_F9R1_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F9R1_FB7_Pos                                            (7U)
#define CAN_F9R1_FB7_Msk                                            (0x1UL << CAN_F9R1_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F9R1_FB7                                                CAN_F9R1_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F9R1_FB8_Pos                                            (8U)
#define CAN_F9R1_FB8_Msk                                            (0x1UL << CAN_F9R1_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F9R1_FB8                                                CAN_F9R1_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F9R1_FB9_Pos                                            (9U)
#define CAN_F9R1_FB9_Msk                                            (0x1UL << CAN_F9R1_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F9R1_FB9                                                CAN_F9R1_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F9R1_FB10_Pos                                           (10U)
#define CAN_F9R1_FB10_Msk                                           (0x1UL << CAN_F9R1_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F9R1_FB10                                               CAN_F9R1_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F9R1_FB11_Pos                                           (11U)
#define CAN_F9R1_FB11_Msk                                           (0x1UL << CAN_F9R1_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F9R1_FB11                                               CAN_F9R1_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F9R1_FB12_Pos                                           (12U)
#define CAN_F9R1_FB12_Msk                                           (0x1UL << CAN_F9R1_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F9R1_FB12                                               CAN_F9R1_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F9R1_FB13_Pos                                           (13U)
#define CAN_F9R1_FB13_Msk                                           (0x1UL << CAN_F9R1_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F9R1_FB13                                               CAN_F9R1_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F9R1_FB14_Pos                                           (14U)
#define CAN_F9R1_FB14_Msk                                           (0x1UL << CAN_F9R1_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F9R1_FB14                                               CAN_F9R1_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F9R1_FB15_Pos                                           (15U)
#define CAN_F9R1_FB15_Msk                                           (0x1UL << CAN_F9R1_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F9R1_FB15                                               CAN_F9R1_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F9R1_FB16_Pos                                           (16U)
#define CAN_F9R1_FB16_Msk                                           (0x1UL << CAN_F9R1_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F9R1_FB16                                               CAN_F9R1_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F9R1_FB17_Pos                                           (17U)
#define CAN_F9R1_FB17_Msk                                           (0x1UL << CAN_F9R1_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F9R1_FB17                                               CAN_F9R1_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F9R1_FB18_Pos                                           (18U)
#define CAN_F9R1_FB18_Msk                                           (0x1UL << CAN_F9R1_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F9R1_FB18                                               CAN_F9R1_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F9R1_FB19_Pos                                           (19U)
#define CAN_F9R1_FB19_Msk                                           (0x1UL << CAN_F9R1_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F9R1_FB19                                               CAN_F9R1_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F9R1_FB20_Pos                                           (20U)
#define CAN_F9R1_FB20_Msk                                           (0x1UL << CAN_F9R1_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F9R1_FB20                                               CAN_F9R1_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F9R1_FB21_Pos                                           (21U)
#define CAN_F9R1_FB21_Msk                                           (0x1UL << CAN_F9R1_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F9R1_FB21                                               CAN_F9R1_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F9R1_FB22_Pos                                           (22U)
#define CAN_F9R1_FB22_Msk                                           (0x1UL << CAN_F9R1_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F9R1_FB22                                               CAN_F9R1_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F9R1_FB23_Pos                                           (23U)
#define CAN_F9R1_FB23_Msk                                           (0x1UL << CAN_F9R1_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F9R1_FB23                                               CAN_F9R1_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F9R1_FB24_Pos                                           (24U)
#define CAN_F9R1_FB24_Msk                                           (0x1UL << CAN_F9R1_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F9R1_FB24                                               CAN_F9R1_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F9R1_FB25_Pos                                           (25U)
#define CAN_F9R1_FB25_Msk                                           (0x1UL << CAN_F9R1_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F9R1_FB25                                               CAN_F9R1_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F9R1_FB26_Pos                                           (26U)
#define CAN_F9R1_FB26_Msk                                           (0x1UL << CAN_F9R1_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F9R1_FB26                                               CAN_F9R1_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F9R1_FB27_Pos                                           (27U)
#define CAN_F9R1_FB27_Msk                                           (0x1UL << CAN_F9R1_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F9R1_FB27                                               CAN_F9R1_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F9R1_FB28_Pos                                           (28U)
#define CAN_F9R1_FB28_Msk                                           (0x1UL << CAN_F9R1_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F9R1_FB28                                               CAN_F9R1_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F9R1_FB29_Pos                                           (29U)
#define CAN_F9R1_FB29_Msk                                           (0x1UL << CAN_F9R1_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F9R1_FB29                                               CAN_F9R1_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F9R1_FB30_Pos                                           (30U)
#define CAN_F9R1_FB30_Msk                                           (0x1UL << CAN_F9R1_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F9R1_FB30                                               CAN_F9R1_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F9R1_FB31_Pos                                           (31U)
#define CAN_F9R1_FB31_Msk                                           (0x1UL << CAN_F9R1_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F9R1_FB31                                               CAN_F9R1_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F10R1 register  ******************/
#define CAN_F10R1_FB0_Pos                                           (0U)
#define CAN_F10R1_FB0_Msk                                           (0x1UL << CAN_F10R1_FB0_Pos)                                   /*!< 0x00000001 */
#define CAN_F10R1_FB0                                               CAN_F10R1_FB0_Msk                                              /*!<Filter bit 0 */
#define CAN_F10R1_FB1_Pos                                           (1U)
#define CAN_F10R1_FB1_Msk                                           (0x1UL << CAN_F10R1_FB1_Pos)                                   /*!< 0x00000002 */
#define CAN_F10R1_FB1                                               CAN_F10R1_FB1_Msk                                              /*!<Filter bit 1 */
#define CAN_F10R1_FB2_Pos                                           (2U)
#define CAN_F10R1_FB2_Msk                                           (0x1UL << CAN_F10R1_FB2_Pos)                                   /*!< 0x00000004 */
#define CAN_F10R1_FB2                                               CAN_F10R1_FB2_Msk                                              /*!<Filter bit 2 */
#define CAN_F10R1_FB3_Pos                                           (3U)
#define CAN_F10R1_FB3_Msk                                           (0x1UL << CAN_F10R1_FB3_Pos)                                   /*!< 0x00000008 */
#define CAN_F10R1_FB3                                               CAN_F10R1_FB3_Msk                                              /*!<Filter bit 3 */
#define CAN_F10R1_FB4_Pos                                           (4U)
#define CAN_F10R1_FB4_Msk                                           (0x1UL << CAN_F10R1_FB4_Pos)                                   /*!< 0x00000010 */
#define CAN_F10R1_FB4                                               CAN_F10R1_FB4_Msk                                              /*!<Filter bit 4 */
#define CAN_F10R1_FB5_Pos                                           (5U)
#define CAN_F10R1_FB5_Msk                                           (0x1UL << CAN_F10R1_FB5_Pos)                                   /*!< 0x00000020 */
#define CAN_F10R1_FB5                                               CAN_F10R1_FB5_Msk                                              /*!<Filter bit 5 */
#define CAN_F10R1_FB6_Pos                                           (6U)
#define CAN_F10R1_FB6_Msk                                           (0x1UL << CAN_F10R1_FB6_Pos)                                   /*!< 0x00000040 */
#define CAN_F10R1_FB6                                               CAN_F10R1_FB6_Msk                                              /*!<Filter bit 6 */
#define CAN_F10R1_FB7_Pos                                           (7U)
#define CAN_F10R1_FB7_Msk                                           (0x1UL << CAN_F10R1_FB7_Pos)                                   /*!< 0x00000080 */
#define CAN_F10R1_FB7                                               CAN_F10R1_FB7_Msk                                              /*!<Filter bit 7 */
#define CAN_F10R1_FB8_Pos                                           (8U)
#define CAN_F10R1_FB8_Msk                                           (0x1UL << CAN_F10R1_FB8_Pos)                                   /*!< 0x00000100 */
#define CAN_F10R1_FB8                                               CAN_F10R1_FB8_Msk                                              /*!<Filter bit 8 */
#define CAN_F10R1_FB9_Pos                                           (9U)
#define CAN_F10R1_FB9_Msk                                           (0x1UL << CAN_F10R1_FB9_Pos)                                   /*!< 0x00000200 */
#define CAN_F10R1_FB9                                               CAN_F10R1_FB9_Msk                                              /*!<Filter bit 9 */
#define CAN_F10R1_FB10_Pos                                          (10U)
#define CAN_F10R1_FB10_Msk                                          (0x1UL << CAN_F10R1_FB10_Pos)                                  /*!< 0x00000400 */
#define CAN_F10R1_FB10                                              CAN_F10R1_FB10_Msk                                             /*!<Filter bit 10 */
#define CAN_F10R1_FB11_Pos                                          (11U)
#define CAN_F10R1_FB11_Msk                                          (0x1UL << CAN_F10R1_FB11_Pos)                                  /*!< 0x00000800 */
#define CAN_F10R1_FB11                                              CAN_F10R1_FB11_Msk                                             /*!<Filter bit 11 */
#define CAN_F10R1_FB12_Pos                                          (12U)
#define CAN_F10R1_FB12_Msk                                          (0x1UL << CAN_F10R1_FB12_Pos)                                  /*!< 0x00001000 */
#define CAN_F10R1_FB12                                              CAN_F10R1_FB12_Msk                                             /*!<Filter bit 12 */
#define CAN_F10R1_FB13_Pos                                          (13U)
#define CAN_F10R1_FB13_Msk                                          (0x1UL << CAN_F10R1_FB13_Pos)                                  /*!< 0x00002000 */
#define CAN_F10R1_FB13                                              CAN_F10R1_FB13_Msk                                             /*!<Filter bit 13 */
#define CAN_F10R1_FB14_Pos                                          (14U)
#define CAN_F10R1_FB14_Msk                                          (0x1UL << CAN_F10R1_FB14_Pos)                                  /*!< 0x00004000 */
#define CAN_F10R1_FB14                                              CAN_F10R1_FB14_Msk                                             /*!<Filter bit 14 */
#define CAN_F10R1_FB15_Pos                                          (15U)
#define CAN_F10R1_FB15_Msk                                          (0x1UL << CAN_F10R1_FB15_Pos)                                  /*!< 0x00008000 */
#define CAN_F10R1_FB15                                              CAN_F10R1_FB15_Msk                                             /*!<Filter bit 15 */
#define CAN_F10R1_FB16_Pos                                          (16U)
#define CAN_F10R1_FB16_Msk                                          (0x1UL << CAN_F10R1_FB16_Pos)                                  /*!< 0x00010000 */
#define CAN_F10R1_FB16                                              CAN_F10R1_FB16_Msk                                             /*!<Filter bit 16 */
#define CAN_F10R1_FB17_Pos                                          (17U)
#define CAN_F10R1_FB17_Msk                                          (0x1UL << CAN_F10R1_FB17_Pos)                                  /*!< 0x00020000 */
#define CAN_F10R1_FB17                                              CAN_F10R1_FB17_Msk                                             /*!<Filter bit 17 */
#define CAN_F10R1_FB18_Pos                                          (18U)
#define CAN_F10R1_FB18_Msk                                          (0x1UL << CAN_F10R1_FB18_Pos)                                  /*!< 0x00040000 */
#define CAN_F10R1_FB18                                              CAN_F10R1_FB18_Msk                                             /*!<Filter bit 18 */
#define CAN_F10R1_FB19_Pos                                          (19U)
#define CAN_F10R1_FB19_Msk                                          (0x1UL << CAN_F10R1_FB19_Pos)                                  /*!< 0x00080000 */
#define CAN_F10R1_FB19                                              CAN_F10R1_FB19_Msk                                             /*!<Filter bit 19 */
#define CAN_F10R1_FB20_Pos                                          (20U)
#define CAN_F10R1_FB20_Msk                                          (0x1UL << CAN_F10R1_FB20_Pos)                                  /*!< 0x00100000 */
#define CAN_F10R1_FB20                                              CAN_F10R1_FB20_Msk                                             /*!<Filter bit 20 */
#define CAN_F10R1_FB21_Pos                                          (21U)
#define CAN_F10R1_FB21_Msk                                          (0x1UL << CAN_F10R1_FB21_Pos)                                  /*!< 0x00200000 */
#define CAN_F10R1_FB21                                              CAN_F10R1_FB21_Msk                                             /*!<Filter bit 21 */
#define CAN_F10R1_FB22_Pos                                          (22U)
#define CAN_F10R1_FB22_Msk                                          (0x1UL << CAN_F10R1_FB22_Pos)                                  /*!< 0x00400000 */
#define CAN_F10R1_FB22                                              CAN_F10R1_FB22_Msk                                             /*!<Filter bit 22 */
#define CAN_F10R1_FB23_Pos                                          (23U)
#define CAN_F10R1_FB23_Msk                                          (0x1UL << CAN_F10R1_FB23_Pos)                                  /*!< 0x00800000 */
#define CAN_F10R1_FB23                                              CAN_F10R1_FB23_Msk                                             /*!<Filter bit 23 */
#define CAN_F10R1_FB24_Pos                                          (24U)
#define CAN_F10R1_FB24_Msk                                          (0x1UL << CAN_F10R1_FB24_Pos)                                  /*!< 0x01000000 */
#define CAN_F10R1_FB24                                              CAN_F10R1_FB24_Msk                                             /*!<Filter bit 24 */
#define CAN_F10R1_FB25_Pos                                          (25U)
#define CAN_F10R1_FB25_Msk                                          (0x1UL << CAN_F10R1_FB25_Pos)                                  /*!< 0x02000000 */
#define CAN_F10R1_FB25                                              CAN_F10R1_FB25_Msk                                             /*!<Filter bit 25 */
#define CAN_F10R1_FB26_Pos                                          (26U)
#define CAN_F10R1_FB26_Msk                                          (0x1UL << CAN_F10R1_FB26_Pos)                                  /*!< 0x04000000 */
#define CAN_F10R1_FB26                                              CAN_F10R1_FB26_Msk                                             /*!<Filter bit 26 */
#define CAN_F10R1_FB27_Pos                                          (27U)
#define CAN_F10R1_FB27_Msk                                          (0x1UL << CAN_F10R1_FB27_Pos)                                  /*!< 0x08000000 */
#define CAN_F10R1_FB27                                              CAN_F10R1_FB27_Msk                                             /*!<Filter bit 27 */
#define CAN_F10R1_FB28_Pos                                          (28U)
#define CAN_F10R1_FB28_Msk                                          (0x1UL << CAN_F10R1_FB28_Pos)                                  /*!< 0x10000000 */
#define CAN_F10R1_FB28                                              CAN_F10R1_FB28_Msk                                             /*!<Filter bit 28 */
#define CAN_F10R1_FB29_Pos                                          (29U)
#define CAN_F10R1_FB29_Msk                                          (0x1UL << CAN_F10R1_FB29_Pos)                                  /*!< 0x20000000 */
#define CAN_F10R1_FB29                                              CAN_F10R1_FB29_Msk                                             /*!<Filter bit 29 */
#define CAN_F10R1_FB30_Pos                                          (30U)
#define CAN_F10R1_FB30_Msk                                          (0x1UL << CAN_F10R1_FB30_Pos)                                  /*!< 0x40000000 */
#define CAN_F10R1_FB30                                              CAN_F10R1_FB30_Msk                                             /*!<Filter bit 30 */
#define CAN_F10R1_FB31_Pos                                          (31U)
#define CAN_F10R1_FB31_Msk                                          (0x1UL << CAN_F10R1_FB31_Pos)                                  /*!< 0x80000000 */
#define CAN_F10R1_FB31                                              CAN_F10R1_FB31_Msk                                             /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F11R1 register  ******************/
#define CAN_F11R1_FB0_Pos                                           (0U)
#define CAN_F11R1_FB0_Msk                                           (0x1UL << CAN_F11R1_FB0_Pos)                                   /*!< 0x00000001 */
#define CAN_F11R1_FB0                                               CAN_F11R1_FB0_Msk                                              /*!<Filter bit 0 */
#define CAN_F11R1_FB1_Pos                                           (1U)
#define CAN_F11R1_FB1_Msk                                           (0x1UL << CAN_F11R1_FB1_Pos)                                   /*!< 0x00000002 */
#define CAN_F11R1_FB1                                               CAN_F11R1_FB1_Msk                                              /*!<Filter bit 1 */
#define CAN_F11R1_FB2_Pos                                           (2U)
#define CAN_F11R1_FB2_Msk                                           (0x1UL << CAN_F11R1_FB2_Pos)                                   /*!< 0x00000004 */
#define CAN_F11R1_FB2                                               CAN_F11R1_FB2_Msk                                              /*!<Filter bit 2 */
#define CAN_F11R1_FB3_Pos                                           (3U)
#define CAN_F11R1_FB3_Msk                                           (0x1UL << CAN_F11R1_FB3_Pos)                                   /*!< 0x00000008 */
#define CAN_F11R1_FB3                                               CAN_F11R1_FB3_Msk                                              /*!<Filter bit 3 */
#define CAN_F11R1_FB4_Pos                                           (4U)
#define CAN_F11R1_FB4_Msk                                           (0x1UL << CAN_F11R1_FB4_Pos)                                   /*!< 0x00000010 */
#define CAN_F11R1_FB4                                               CAN_F11R1_FB4_Msk                                              /*!<Filter bit 4 */
#define CAN_F11R1_FB5_Pos                                           (5U)
#define CAN_F11R1_FB5_Msk                                           (0x1UL << CAN_F11R1_FB5_Pos)                                   /*!< 0x00000020 */
#define CAN_F11R1_FB5                                               CAN_F11R1_FB5_Msk                                              /*!<Filter bit 5 */
#define CAN_F11R1_FB6_Pos                                           (6U)
#define CAN_F11R1_FB6_Msk                                           (0x1UL << CAN_F11R1_FB6_Pos)                                   /*!< 0x00000040 */
#define CAN_F11R1_FB6                                               CAN_F11R1_FB6_Msk                                              /*!<Filter bit 6 */
#define CAN_F11R1_FB7_Pos                                           (7U)
#define CAN_F11R1_FB7_Msk                                           (0x1UL << CAN_F11R1_FB7_Pos)                                   /*!< 0x00000080 */
#define CAN_F11R1_FB7                                               CAN_F11R1_FB7_Msk                                              /*!<Filter bit 7 */
#define CAN_F11R1_FB8_Pos                                           (8U)
#define CAN_F11R1_FB8_Msk                                           (0x1UL << CAN_F11R1_FB8_Pos)                                   /*!< 0x00000100 */
#define CAN_F11R1_FB8                                               CAN_F11R1_FB8_Msk                                              /*!<Filter bit 8 */
#define CAN_F11R1_FB9_Pos                                           (9U)
#define CAN_F11R1_FB9_Msk                                           (0x1UL << CAN_F11R1_FB9_Pos)                                   /*!< 0x00000200 */
#define CAN_F11R1_FB9                                               CAN_F11R1_FB9_Msk                                              /*!<Filter bit 9 */
#define CAN_F11R1_FB10_Pos                                          (10U)
#define CAN_F11R1_FB10_Msk                                          (0x1UL << CAN_F11R1_FB10_Pos)                                  /*!< 0x00000400 */
#define CAN_F11R1_FB10                                              CAN_F11R1_FB10_Msk                                             /*!<Filter bit 10 */
#define CAN_F11R1_FB11_Pos                                          (11U)
#define CAN_F11R1_FB11_Msk                                          (0x1UL << CAN_F11R1_FB11_Pos)                                  /*!< 0x00000800 */
#define CAN_F11R1_FB11                                              CAN_F11R1_FB11_Msk                                             /*!<Filter bit 11 */
#define CAN_F11R1_FB12_Pos                                          (12U)
#define CAN_F11R1_FB12_Msk                                          (0x1UL << CAN_F11R1_FB12_Pos)                                  /*!< 0x00001000 */
#define CAN_F11R1_FB12                                              CAN_F11R1_FB12_Msk                                             /*!<Filter bit 12 */
#define CAN_F11R1_FB13_Pos                                          (13U)
#define CAN_F11R1_FB13_Msk                                          (0x1UL << CAN_F11R1_FB13_Pos)                                  /*!< 0x00002000 */
#define CAN_F11R1_FB13                                              CAN_F11R1_FB13_Msk                                             /*!<Filter bit 13 */
#define CAN_F11R1_FB14_Pos                                          (14U)
#define CAN_F11R1_FB14_Msk                                          (0x1UL << CAN_F11R1_FB14_Pos)                                  /*!< 0x00004000 */
#define CAN_F11R1_FB14                                              CAN_F11R1_FB14_Msk                                             /*!<Filter bit 14 */
#define CAN_F11R1_FB15_Pos                                          (15U)
#define CAN_F11R1_FB15_Msk                                          (0x1UL << CAN_F11R1_FB15_Pos)                                  /*!< 0x00008000 */
#define CAN_F11R1_FB15                                              CAN_F11R1_FB15_Msk                                             /*!<Filter bit 15 */
#define CAN_F11R1_FB16_Pos                                          (16U)
#define CAN_F11R1_FB16_Msk                                          (0x1UL << CAN_F11R1_FB16_Pos)                                  /*!< 0x00010000 */
#define CAN_F11R1_FB16                                              CAN_F11R1_FB16_Msk                                             /*!<Filter bit 16 */
#define CAN_F11R1_FB17_Pos                                          (17U)
#define CAN_F11R1_FB17_Msk                                          (0x1UL << CAN_F11R1_FB17_Pos)                                  /*!< 0x00020000 */
#define CAN_F11R1_FB17                                              CAN_F11R1_FB17_Msk                                             /*!<Filter bit 17 */
#define CAN_F11R1_FB18_Pos                                          (18U)
#define CAN_F11R1_FB18_Msk                                          (0x1UL << CAN_F11R1_FB18_Pos)                                  /*!< 0x00040000 */
#define CAN_F11R1_FB18                                              CAN_F11R1_FB18_Msk                                             /*!<Filter bit 18 */
#define CAN_F11R1_FB19_Pos                                          (19U)
#define CAN_F11R1_FB19_Msk                                          (0x1UL << CAN_F11R1_FB19_Pos)                                  /*!< 0x00080000 */
#define CAN_F11R1_FB19                                              CAN_F11R1_FB19_Msk                                             /*!<Filter bit 19 */
#define CAN_F11R1_FB20_Pos                                          (20U)
#define CAN_F11R1_FB20_Msk                                          (0x1UL << CAN_F11R1_FB20_Pos)                                  /*!< 0x00100000 */
#define CAN_F11R1_FB20                                              CAN_F11R1_FB20_Msk                                             /*!<Filter bit 20 */
#define CAN_F11R1_FB21_Pos                                          (21U)
#define CAN_F11R1_FB21_Msk                                          (0x1UL << CAN_F11R1_FB21_Pos)                                  /*!< 0x00200000 */
#define CAN_F11R1_FB21                                              CAN_F11R1_FB21_Msk                                             /*!<Filter bit 21 */
#define CAN_F11R1_FB22_Pos                                          (22U)
#define CAN_F11R1_FB22_Msk                                          (0x1UL << CAN_F11R1_FB22_Pos)                                  /*!< 0x00400000 */
#define CAN_F11R1_FB22                                              CAN_F11R1_FB22_Msk                                             /*!<Filter bit 22 */
#define CAN_F11R1_FB23_Pos                                          (23U)
#define CAN_F11R1_FB23_Msk                                          (0x1UL << CAN_F11R1_FB23_Pos)                                  /*!< 0x00800000 */
#define CAN_F11R1_FB23                                              CAN_F11R1_FB23_Msk                                             /*!<Filter bit 23 */
#define CAN_F11R1_FB24_Pos                                          (24U)
#define CAN_F11R1_FB24_Msk                                          (0x1UL << CAN_F11R1_FB24_Pos)                                  /*!< 0x01000000 */
#define CAN_F11R1_FB24                                              CAN_F11R1_FB24_Msk                                             /*!<Filter bit 24 */
#define CAN_F11R1_FB25_Pos                                          (25U)
#define CAN_F11R1_FB25_Msk                                          (0x1UL << CAN_F11R1_FB25_Pos)                                  /*!< 0x02000000 */
#define CAN_F11R1_FB25                                              CAN_F11R1_FB25_Msk                                             /*!<Filter bit 25 */
#define CAN_F11R1_FB26_Pos                                          (26U)
#define CAN_F11R1_FB26_Msk                                          (0x1UL << CAN_F11R1_FB26_Pos)                                  /*!< 0x04000000 */
#define CAN_F11R1_FB26                                              CAN_F11R1_FB26_Msk                                             /*!<Filter bit 26 */
#define CAN_F11R1_FB27_Pos                                          (27U)
#define CAN_F11R1_FB27_Msk                                          (0x1UL << CAN_F11R1_FB27_Pos)                                  /*!< 0x08000000 */
#define CAN_F11R1_FB27                                              CAN_F11R1_FB27_Msk                                             /*!<Filter bit 27 */
#define CAN_F11R1_FB28_Pos                                          (28U)
#define CAN_F11R1_FB28_Msk                                          (0x1UL << CAN_F11R1_FB28_Pos)                                  /*!< 0x10000000 */
#define CAN_F11R1_FB28                                              CAN_F11R1_FB28_Msk                                             /*!<Filter bit 28 */
#define CAN_F11R1_FB29_Pos                                          (29U)
#define CAN_F11R1_FB29_Msk                                          (0x1UL << CAN_F11R1_FB29_Pos)                                  /*!< 0x20000000 */
#define CAN_F11R1_FB29                                              CAN_F11R1_FB29_Msk                                             /*!<Filter bit 29 */
#define CAN_F11R1_FB30_Pos                                          (30U)
#define CAN_F11R1_FB30_Msk                                          (0x1UL << CAN_F11R1_FB30_Pos)                                  /*!< 0x40000000 */
#define CAN_F11R1_FB30                                              CAN_F11R1_FB30_Msk                                             /*!<Filter bit 30 */
#define CAN_F11R1_FB31_Pos                                          (31U)
#define CAN_F11R1_FB31_Msk                                          (0x1UL << CAN_F11R1_FB31_Pos)                                  /*!< 0x80000000 */
#define CAN_F11R1_FB31                                              CAN_F11R1_FB31_Msk                                             /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F12R1 register  ******************/
#define CAN_F12R1_FB0_Pos                                           (0U)
#define CAN_F12R1_FB0_Msk                                           (0x1UL << CAN_F12R1_FB0_Pos)                                   /*!< 0x00000001 */
#define CAN_F12R1_FB0                                               CAN_F12R1_FB0_Msk                                              /*!<Filter bit 0 */
#define CAN_F12R1_FB1_Pos                                           (1U)
#define CAN_F12R1_FB1_Msk                                           (0x1UL << CAN_F12R1_FB1_Pos)                                   /*!< 0x00000002 */
#define CAN_F12R1_FB1                                               CAN_F12R1_FB1_Msk                                              /*!<Filter bit 1 */
#define CAN_F12R1_FB2_Pos                                           (2U)
#define CAN_F12R1_FB2_Msk                                           (0x1UL << CAN_F12R1_FB2_Pos)                                   /*!< 0x00000004 */
#define CAN_F12R1_FB2                                               CAN_F12R1_FB2_Msk                                              /*!<Filter bit 2 */
#define CAN_F12R1_FB3_Pos                                           (3U)
#define CAN_F12R1_FB3_Msk                                           (0x1UL << CAN_F12R1_FB3_Pos)                                   /*!< 0x00000008 */
#define CAN_F12R1_FB3                                               CAN_F12R1_FB3_Msk                                              /*!<Filter bit 3 */
#define CAN_F12R1_FB4_Pos                                           (4U)
#define CAN_F12R1_FB4_Msk                                           (0x1UL << CAN_F12R1_FB4_Pos)                                   /*!< 0x00000010 */
#define CAN_F12R1_FB4                                               CAN_F12R1_FB4_Msk                                              /*!<Filter bit 4 */
#define CAN_F12R1_FB5_Pos                                           (5U)
#define CAN_F12R1_FB5_Msk                                           (0x1UL << CAN_F12R1_FB5_Pos)                                   /*!< 0x00000020 */
#define CAN_F12R1_FB5                                               CAN_F12R1_FB5_Msk                                              /*!<Filter bit 5 */
#define CAN_F12R1_FB6_Pos                                           (6U)
#define CAN_F12R1_FB6_Msk                                           (0x1UL << CAN_F12R1_FB6_Pos)                                   /*!< 0x00000040 */
#define CAN_F12R1_FB6                                               CAN_F12R1_FB6_Msk                                              /*!<Filter bit 6 */
#define CAN_F12R1_FB7_Pos                                           (7U)
#define CAN_F12R1_FB7_Msk                                           (0x1UL << CAN_F12R1_FB7_Pos)                                   /*!< 0x00000080 */
#define CAN_F12R1_FB7                                               CAN_F12R1_FB7_Msk                                              /*!<Filter bit 7 */
#define CAN_F12R1_FB8_Pos                                           (8U)
#define CAN_F12R1_FB8_Msk                                           (0x1UL << CAN_F12R1_FB8_Pos)                                   /*!< 0x00000100 */
#define CAN_F12R1_FB8                                               CAN_F12R1_FB8_Msk                                              /*!<Filter bit 8 */
#define CAN_F12R1_FB9_Pos                                           (9U)
#define CAN_F12R1_FB9_Msk                                           (0x1UL << CAN_F12R1_FB9_Pos)                                   /*!< 0x00000200 */
#define CAN_F12R1_FB9                                               CAN_F12R1_FB9_Msk                                              /*!<Filter bit 9 */
#define CAN_F12R1_FB10_Pos                                          (10U)
#define CAN_F12R1_FB10_Msk                                          (0x1UL << CAN_F12R1_FB10_Pos)                                  /*!< 0x00000400 */
#define CAN_F12R1_FB10                                              CAN_F12R1_FB10_Msk                                             /*!<Filter bit 10 */
#define CAN_F12R1_FB11_Pos                                          (11U)
#define CAN_F12R1_FB11_Msk                                          (0x1UL << CAN_F12R1_FB11_Pos)                                  /*!< 0x00000800 */
#define CAN_F12R1_FB11                                              CAN_F12R1_FB11_Msk                                             /*!<Filter bit 11 */
#define CAN_F12R1_FB12_Pos                                          (12U)
#define CAN_F12R1_FB12_Msk                                          (0x1UL << CAN_F12R1_FB12_Pos)                                  /*!< 0x00001000 */
#define CAN_F12R1_FB12                                              CAN_F12R1_FB12_Msk                                             /*!<Filter bit 12 */
#define CAN_F12R1_FB13_Pos                                          (13U)
#define CAN_F12R1_FB13_Msk                                          (0x1UL << CAN_F12R1_FB13_Pos)                                  /*!< 0x00002000 */
#define CAN_F12R1_FB13                                              CAN_F12R1_FB13_Msk                                             /*!<Filter bit 13 */
#define CAN_F12R1_FB14_Pos                                          (14U)
#define CAN_F12R1_FB14_Msk                                          (0x1UL << CAN_F12R1_FB14_Pos)                                  /*!< 0x00004000 */
#define CAN_F12R1_FB14                                              CAN_F12R1_FB14_Msk                                             /*!<Filter bit 14 */
#define CAN_F12R1_FB15_Pos                                          (15U)
#define CAN_F12R1_FB15_Msk                                          (0x1UL << CAN_F12R1_FB15_Pos)                                  /*!< 0x00008000 */
#define CAN_F12R1_FB15                                              CAN_F12R1_FB15_Msk                                             /*!<Filter bit 15 */
#define CAN_F12R1_FB16_Pos                                          (16U)
#define CAN_F12R1_FB16_Msk                                          (0x1UL << CAN_F12R1_FB16_Pos)                                  /*!< 0x00010000 */
#define CAN_F12R1_FB16                                              CAN_F12R1_FB16_Msk                                             /*!<Filter bit 16 */
#define CAN_F12R1_FB17_Pos                                          (17U)
#define CAN_F12R1_FB17_Msk                                          (0x1UL << CAN_F12R1_FB17_Pos)                                  /*!< 0x00020000 */
#define CAN_F12R1_FB17                                              CAN_F12R1_FB17_Msk                                             /*!<Filter bit 17 */
#define CAN_F12R1_FB18_Pos                                          (18U)
#define CAN_F12R1_FB18_Msk                                          (0x1UL << CAN_F12R1_FB18_Pos)                                  /*!< 0x00040000 */
#define CAN_F12R1_FB18                                              CAN_F12R1_FB18_Msk                                             /*!<Filter bit 18 */
#define CAN_F12R1_FB19_Pos                                          (19U)
#define CAN_F12R1_FB19_Msk                                          (0x1UL << CAN_F12R1_FB19_Pos)                                  /*!< 0x00080000 */
#define CAN_F12R1_FB19                                              CAN_F12R1_FB19_Msk                                             /*!<Filter bit 19 */
#define CAN_F12R1_FB20_Pos                                          (20U)
#define CAN_F12R1_FB20_Msk                                          (0x1UL << CAN_F12R1_FB20_Pos)                                  /*!< 0x00100000 */
#define CAN_F12R1_FB20                                              CAN_F12R1_FB20_Msk                                             /*!<Filter bit 20 */
#define CAN_F12R1_FB21_Pos                                          (21U)
#define CAN_F12R1_FB21_Msk                                          (0x1UL << CAN_F12R1_FB21_Pos)                                  /*!< 0x00200000 */
#define CAN_F12R1_FB21                                              CAN_F12R1_FB21_Msk                                             /*!<Filter bit 21 */
#define CAN_F12R1_FB22_Pos                                          (22U)
#define CAN_F12R1_FB22_Msk                                          (0x1UL << CAN_F12R1_FB22_Pos)                                  /*!< 0x00400000 */
#define CAN_F12R1_FB22                                              CAN_F12R1_FB22_Msk                                             /*!<Filter bit 22 */
#define CAN_F12R1_FB23_Pos                                          (23U)
#define CAN_F12R1_FB23_Msk                                          (0x1UL << CAN_F12R1_FB23_Pos)                                  /*!< 0x00800000 */
#define CAN_F12R1_FB23                                              CAN_F12R1_FB23_Msk                                             /*!<Filter bit 23 */
#define CAN_F12R1_FB24_Pos                                          (24U)
#define CAN_F12R1_FB24_Msk                                          (0x1UL << CAN_F12R1_FB24_Pos)                                  /*!< 0x01000000 */
#define CAN_F12R1_FB24                                              CAN_F12R1_FB24_Msk                                             /*!<Filter bit 24 */
#define CAN_F12R1_FB25_Pos                                          (25U)
#define CAN_F12R1_FB25_Msk                                          (0x1UL << CAN_F12R1_FB25_Pos)                                  /*!< 0x02000000 */
#define CAN_F12R1_FB25                                              CAN_F12R1_FB25_Msk                                             /*!<Filter bit 25 */
#define CAN_F12R1_FB26_Pos                                          (26U)
#define CAN_F12R1_FB26_Msk                                          (0x1UL << CAN_F12R1_FB26_Pos)                                  /*!< 0x04000000 */
#define CAN_F12R1_FB26                                              CAN_F12R1_FB26_Msk                                             /*!<Filter bit 26 */
#define CAN_F12R1_FB27_Pos                                          (27U)
#define CAN_F12R1_FB27_Msk                                          (0x1UL << CAN_F12R1_FB27_Pos)                                  /*!< 0x08000000 */
#define CAN_F12R1_FB27                                              CAN_F12R1_FB27_Msk                                             /*!<Filter bit 27 */
#define CAN_F12R1_FB28_Pos                                          (28U)
#define CAN_F12R1_FB28_Msk                                          (0x1UL << CAN_F12R1_FB28_Pos)                                  /*!< 0x10000000 */
#define CAN_F12R1_FB28                                              CAN_F12R1_FB28_Msk                                             /*!<Filter bit 28 */
#define CAN_F12R1_FB29_Pos                                          (29U)
#define CAN_F12R1_FB29_Msk                                          (0x1UL << CAN_F12R1_FB29_Pos)                                  /*!< 0x20000000 */
#define CAN_F12R1_FB29                                              CAN_F12R1_FB29_Msk                                             /*!<Filter bit 29 */
#define CAN_F12R1_FB30_Pos                                          (30U)
#define CAN_F12R1_FB30_Msk                                          (0x1UL << CAN_F12R1_FB30_Pos)                                  /*!< 0x40000000 */
#define CAN_F12R1_FB30                                              CAN_F12R1_FB30_Msk                                             /*!<Filter bit 30 */
#define CAN_F12R1_FB31_Pos                                          (31U)
#define CAN_F12R1_FB31_Msk                                          (0x1UL << CAN_F12R1_FB31_Pos)                                  /*!< 0x80000000 */
#define CAN_F12R1_FB31                                              CAN_F12R1_FB31_Msk                                             /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F13R1 register  ******************/
#define CAN_F13R1_FB0_Pos                                           (0U)
#define CAN_F13R1_FB0_Msk                                           (0x1UL << CAN_F13R1_FB0_Pos)                                   /*!< 0x00000001 */
#define CAN_F13R1_FB0                                               CAN_F13R1_FB0_Msk                                              /*!<Filter bit 0 */
#define CAN_F13R1_FB1_Pos                                           (1U)
#define CAN_F13R1_FB1_Msk                                           (0x1UL << CAN_F13R1_FB1_Pos)                                   /*!< 0x00000002 */
#define CAN_F13R1_FB1                                               CAN_F13R1_FB1_Msk                                              /*!<Filter bit 1 */
#define CAN_F13R1_FB2_Pos                                           (2U)
#define CAN_F13R1_FB2_Msk                                           (0x1UL << CAN_F13R1_FB2_Pos)                                   /*!< 0x00000004 */
#define CAN_F13R1_FB2                                               CAN_F13R1_FB2_Msk                                              /*!<Filter bit 2 */
#define CAN_F13R1_FB3_Pos                                           (3U)
#define CAN_F13R1_FB3_Msk                                           (0x1UL << CAN_F13R1_FB3_Pos)                                   /*!< 0x00000008 */
#define CAN_F13R1_FB3                                               CAN_F13R1_FB3_Msk                                              /*!<Filter bit 3 */
#define CAN_F13R1_FB4_Pos                                           (4U)
#define CAN_F13R1_FB4_Msk                                           (0x1UL << CAN_F13R1_FB4_Pos)                                   /*!< 0x00000010 */
#define CAN_F13R1_FB4                                               CAN_F13R1_FB4_Msk                                              /*!<Filter bit 4 */
#define CAN_F13R1_FB5_Pos                                           (5U)
#define CAN_F13R1_FB5_Msk                                           (0x1UL << CAN_F13R1_FB5_Pos)                                   /*!< 0x00000020 */
#define CAN_F13R1_FB5                                               CAN_F13R1_FB5_Msk                                              /*!<Filter bit 5 */
#define CAN_F13R1_FB6_Pos                                           (6U)
#define CAN_F13R1_FB6_Msk                                           (0x1UL << CAN_F13R1_FB6_Pos)                                   /*!< 0x00000040 */
#define CAN_F13R1_FB6                                               CAN_F13R1_FB6_Msk                                              /*!<Filter bit 6 */
#define CAN_F13R1_FB7_Pos                                           (7U)
#define CAN_F13R1_FB7_Msk                                           (0x1UL << CAN_F13R1_FB7_Pos)                                   /*!< 0x00000080 */
#define CAN_F13R1_FB7                                               CAN_F13R1_FB7_Msk                                              /*!<Filter bit 7 */
#define CAN_F13R1_FB8_Pos                                           (8U)
#define CAN_F13R1_FB8_Msk                                           (0x1UL << CAN_F13R1_FB8_Pos)                                   /*!< 0x00000100 */
#define CAN_F13R1_FB8                                               CAN_F13R1_FB8_Msk                                              /*!<Filter bit 8 */
#define CAN_F13R1_FB9_Pos                                           (9U)
#define CAN_F13R1_FB9_Msk                                           (0x1UL << CAN_F13R1_FB9_Pos)                                   /*!< 0x00000200 */
#define CAN_F13R1_FB9                                               CAN_F13R1_FB9_Msk                                              /*!<Filter bit 9 */
#define CAN_F13R1_FB10_Pos                                          (10U)
#define CAN_F13R1_FB10_Msk                                          (0x1UL << CAN_F13R1_FB10_Pos)                                  /*!< 0x00000400 */
#define CAN_F13R1_FB10                                              CAN_F13R1_FB10_Msk                                             /*!<Filter bit 10 */
#define CAN_F13R1_FB11_Pos                                          (11U)
#define CAN_F13R1_FB11_Msk                                          (0x1UL << CAN_F13R1_FB11_Pos)                                  /*!< 0x00000800 */
#define CAN_F13R1_FB11                                              CAN_F13R1_FB11_Msk                                             /*!<Filter bit 11 */
#define CAN_F13R1_FB12_Pos                                          (12U)
#define CAN_F13R1_FB12_Msk                                          (0x1UL << CAN_F13R1_FB12_Pos)                                  /*!< 0x00001000 */
#define CAN_F13R1_FB12                                              CAN_F13R1_FB12_Msk                                             /*!<Filter bit 12 */
#define CAN_F13R1_FB13_Pos                                          (13U)
#define CAN_F13R1_FB13_Msk                                          (0x1UL << CAN_F13R1_FB13_Pos)                                  /*!< 0x00002000 */
#define CAN_F13R1_FB13                                              CAN_F13R1_FB13_Msk                                             /*!<Filter bit 13 */
#define CAN_F13R1_FB14_Pos                                          (14U)
#define CAN_F13R1_FB14_Msk                                          (0x1UL << CAN_F13R1_FB14_Pos)                                  /*!< 0x00004000 */
#define CAN_F13R1_FB14                                              CAN_F13R1_FB14_Msk                                             /*!<Filter bit 14 */
#define CAN_F13R1_FB15_Pos                                          (15U)
#define CAN_F13R1_FB15_Msk                                          (0x1UL << CAN_F13R1_FB15_Pos)                                  /*!< 0x00008000 */
#define CAN_F13R1_FB15                                              CAN_F13R1_FB15_Msk                                             /*!<Filter bit 15 */
#define CAN_F13R1_FB16_Pos                                          (16U)
#define CAN_F13R1_FB16_Msk                                          (0x1UL << CAN_F13R1_FB16_Pos)                                  /*!< 0x00010000 */
#define CAN_F13R1_FB16                                              CAN_F13R1_FB16_Msk                                             /*!<Filter bit 16 */
#define CAN_F13R1_FB17_Pos                                          (17U)
#define CAN_F13R1_FB17_Msk                                          (0x1UL << CAN_F13R1_FB17_Pos)                                  /*!< 0x00020000 */
#define CAN_F13R1_FB17                                              CAN_F13R1_FB17_Msk                                             /*!<Filter bit 17 */
#define CAN_F13R1_FB18_Pos                                          (18U)
#define CAN_F13R1_FB18_Msk                                          (0x1UL << CAN_F13R1_FB18_Pos)                                  /*!< 0x00040000 */
#define CAN_F13R1_FB18                                              CAN_F13R1_FB18_Msk                                             /*!<Filter bit 18 */
#define CAN_F13R1_FB19_Pos                                          (19U)
#define CAN_F13R1_FB19_Msk                                          (0x1UL << CAN_F13R1_FB19_Pos)                                  /*!< 0x00080000 */
#define CAN_F13R1_FB19                                              CAN_F13R1_FB19_Msk                                             /*!<Filter bit 19 */
#define CAN_F13R1_FB20_Pos                                          (20U)
#define CAN_F13R1_FB20_Msk                                          (0x1UL << CAN_F13R1_FB20_Pos)                                  /*!< 0x00100000 */
#define CAN_F13R1_FB20                                              CAN_F13R1_FB20_Msk                                             /*!<Filter bit 20 */
#define CAN_F13R1_FB21_Pos                                          (21U)
#define CAN_F13R1_FB21_Msk                                          (0x1UL << CAN_F13R1_FB21_Pos)                                  /*!< 0x00200000 */
#define CAN_F13R1_FB21                                              CAN_F13R1_FB21_Msk                                             /*!<Filter bit 21 */
#define CAN_F13R1_FB22_Pos                                          (22U)
#define CAN_F13R1_FB22_Msk                                          (0x1UL << CAN_F13R1_FB22_Pos)                                  /*!< 0x00400000 */
#define CAN_F13R1_FB22                                              CAN_F13R1_FB22_Msk                                             /*!<Filter bit 22 */
#define CAN_F13R1_FB23_Pos                                          (23U)
#define CAN_F13R1_FB23_Msk                                          (0x1UL << CAN_F13R1_FB23_Pos)                                  /*!< 0x00800000 */
#define CAN_F13R1_FB23                                              CAN_F13R1_FB23_Msk                                             /*!<Filter bit 23 */
#define CAN_F13R1_FB24_Pos                                          (24U)
#define CAN_F13R1_FB24_Msk                                          (0x1UL << CAN_F13R1_FB24_Pos)                                  /*!< 0x01000000 */
#define CAN_F13R1_FB24                                              CAN_F13R1_FB24_Msk                                             /*!<Filter bit 24 */
#define CAN_F13R1_FB25_Pos                                          (25U)
#define CAN_F13R1_FB25_Msk                                          (0x1UL << CAN_F13R1_FB25_Pos)                                  /*!< 0x02000000 */
#define CAN_F13R1_FB25                                              CAN_F13R1_FB25_Msk                                             /*!<Filter bit 25 */
#define CAN_F13R1_FB26_Pos                                          (26U)
#define CAN_F13R1_FB26_Msk                                          (0x1UL << CAN_F13R1_FB26_Pos)                                  /*!< 0x04000000 */
#define CAN_F13R1_FB26                                              CAN_F13R1_FB26_Msk                                             /*!<Filter bit 26 */
#define CAN_F13R1_FB27_Pos                                          (27U)
#define CAN_F13R1_FB27_Msk                                          (0x1UL << CAN_F13R1_FB27_Pos)                                  /*!< 0x08000000 */
#define CAN_F13R1_FB27                                              CAN_F13R1_FB27_Msk                                             /*!<Filter bit 27 */
#define CAN_F13R1_FB28_Pos                                          (28U)
#define CAN_F13R1_FB28_Msk                                          (0x1UL << CAN_F13R1_FB28_Pos)                                  /*!< 0x10000000 */
#define CAN_F13R1_FB28                                              CAN_F13R1_FB28_Msk                                             /*!<Filter bit 28 */
#define CAN_F13R1_FB29_Pos                                          (29U)
#define CAN_F13R1_FB29_Msk                                          (0x1UL << CAN_F13R1_FB29_Pos)                                  /*!< 0x20000000 */
#define CAN_F13R1_FB29                                              CAN_F13R1_FB29_Msk                                             /*!<Filter bit 29 */
#define CAN_F13R1_FB30_Pos                                          (30U)
#define CAN_F13R1_FB30_Msk                                          (0x1UL << CAN_F13R1_FB30_Pos)                                  /*!< 0x40000000 */
#define CAN_F13R1_FB30                                              CAN_F13R1_FB30_Msk                                             /*!<Filter bit 30 */
#define CAN_F13R1_FB31_Pos                                          (31U)
#define CAN_F13R1_FB31_Msk                                          (0x1UL << CAN_F13R1_FB31_Pos)                                  /*!< 0x80000000 */
#define CAN_F13R1_FB31                                              CAN_F13R1_FB31_Msk                                             /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F0R2 register  *******************/
#define CAN_F0R2_FB0_Pos                                            (0U)
#define CAN_F0R2_FB0_Msk                                            (0x1UL << CAN_F0R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F0R2_FB0                                                CAN_F0R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F0R2_FB1_Pos                                            (1U)
#define CAN_F0R2_FB1_Msk                                            (0x1UL << CAN_F0R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F0R2_FB1                                                CAN_F0R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F0R2_FB2_Pos                                            (2U)
#define CAN_F0R2_FB2_Msk                                            (0x1UL << CAN_F0R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F0R2_FB2                                                CAN_F0R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F0R2_FB3_Pos                                            (3U)
#define CAN_F0R2_FB3_Msk                                            (0x1UL << CAN_F0R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F0R2_FB3                                                CAN_F0R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F0R2_FB4_Pos                                            (4U)
#define CAN_F0R2_FB4_Msk                                            (0x1UL << CAN_F0R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F0R2_FB4                                                CAN_F0R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F0R2_FB5_Pos                                            (5U)
#define CAN_F0R2_FB5_Msk                                            (0x1UL << CAN_F0R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F0R2_FB5                                                CAN_F0R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F0R2_FB6_Pos                                            (6U)
#define CAN_F0R2_FB6_Msk                                            (0x1UL << CAN_F0R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F0R2_FB6                                                CAN_F0R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F0R2_FB7_Pos                                            (7U)
#define CAN_F0R2_FB7_Msk                                            (0x1UL << CAN_F0R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F0R2_FB7                                                CAN_F0R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F0R2_FB8_Pos                                            (8U)
#define CAN_F0R2_FB8_Msk                                            (0x1UL << CAN_F0R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F0R2_FB8                                                CAN_F0R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F0R2_FB9_Pos                                            (9U)
#define CAN_F0R2_FB9_Msk                                            (0x1UL << CAN_F0R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F0R2_FB9                                                CAN_F0R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F0R2_FB10_Pos                                           (10U)
#define CAN_F0R2_FB10_Msk                                           (0x1UL << CAN_F0R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F0R2_FB10                                               CAN_F0R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F0R2_FB11_Pos                                           (11U)
#define CAN_F0R2_FB11_Msk                                           (0x1UL << CAN_F0R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F0R2_FB11                                               CAN_F0R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F0R2_FB12_Pos                                           (12U)
#define CAN_F0R2_FB12_Msk                                           (0x1UL << CAN_F0R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F0R2_FB12                                               CAN_F0R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F0R2_FB13_Pos                                           (13U)
#define CAN_F0R2_FB13_Msk                                           (0x1UL << CAN_F0R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F0R2_FB13                                               CAN_F0R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F0R2_FB14_Pos                                           (14U)
#define CAN_F0R2_FB14_Msk                                           (0x1UL << CAN_F0R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F0R2_FB14                                               CAN_F0R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F0R2_FB15_Pos                                           (15U)
#define CAN_F0R2_FB15_Msk                                           (0x1UL << CAN_F0R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F0R2_FB15                                               CAN_F0R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F0R2_FB16_Pos                                           (16U)
#define CAN_F0R2_FB16_Msk                                           (0x1UL << CAN_F0R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F0R2_FB16                                               CAN_F0R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F0R2_FB17_Pos                                           (17U)
#define CAN_F0R2_FB17_Msk                                           (0x1UL << CAN_F0R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F0R2_FB17                                               CAN_F0R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F0R2_FB18_Pos                                           (18U)
#define CAN_F0R2_FB18_Msk                                           (0x1UL << CAN_F0R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F0R2_FB18                                               CAN_F0R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F0R2_FB19_Pos                                           (19U)
#define CAN_F0R2_FB19_Msk                                           (0x1UL << CAN_F0R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F0R2_FB19                                               CAN_F0R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F0R2_FB20_Pos                                           (20U)
#define CAN_F0R2_FB20_Msk                                           (0x1UL << CAN_F0R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F0R2_FB20                                               CAN_F0R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F0R2_FB21_Pos                                           (21U)
#define CAN_F0R2_FB21_Msk                                           (0x1UL << CAN_F0R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F0R2_FB21                                               CAN_F0R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F0R2_FB22_Pos                                           (22U)
#define CAN_F0R2_FB22_Msk                                           (0x1UL << CAN_F0R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F0R2_FB22                                               CAN_F0R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F0R2_FB23_Pos                                           (23U)
#define CAN_F0R2_FB23_Msk                                           (0x1UL << CAN_F0R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F0R2_FB23                                               CAN_F0R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F0R2_FB24_Pos                                           (24U)
#define CAN_F0R2_FB24_Msk                                           (0x1UL << CAN_F0R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F0R2_FB24                                               CAN_F0R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F0R2_FB25_Pos                                           (25U)
#define CAN_F0R2_FB25_Msk                                           (0x1UL << CAN_F0R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F0R2_FB25                                               CAN_F0R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F0R2_FB26_Pos                                           (26U)
#define CAN_F0R2_FB26_Msk                                           (0x1UL << CAN_F0R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F0R2_FB26                                               CAN_F0R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F0R2_FB27_Pos                                           (27U)
#define CAN_F0R2_FB27_Msk                                           (0x1UL << CAN_F0R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F0R2_FB27                                               CAN_F0R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F0R2_FB28_Pos                                           (28U)
#define CAN_F0R2_FB28_Msk                                           (0x1UL << CAN_F0R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F0R2_FB28                                               CAN_F0R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F0R2_FB29_Pos                                           (29U)
#define CAN_F0R2_FB29_Msk                                           (0x1UL << CAN_F0R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F0R2_FB29                                               CAN_F0R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F0R2_FB30_Pos                                           (30U)
#define CAN_F0R2_FB30_Msk                                           (0x1UL << CAN_F0R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F0R2_FB30                                               CAN_F0R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F0R2_FB31_Pos                                           (31U)
#define CAN_F0R2_FB31_Msk                                           (0x1UL << CAN_F0R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F0R2_FB31                                               CAN_F0R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F1R2 register  *******************/
#define CAN_F1R2_FB0_Pos                                            (0U)
#define CAN_F1R2_FB0_Msk                                            (0x1UL << CAN_F1R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F1R2_FB0                                                CAN_F1R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F1R2_FB1_Pos                                            (1U)
#define CAN_F1R2_FB1_Msk                                            (0x1UL << CAN_F1R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F1R2_FB1                                                CAN_F1R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F1R2_FB2_Pos                                            (2U)
#define CAN_F1R2_FB2_Msk                                            (0x1UL << CAN_F1R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F1R2_FB2                                                CAN_F1R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F1R2_FB3_Pos                                            (3U)
#define CAN_F1R2_FB3_Msk                                            (0x1UL << CAN_F1R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F1R2_FB3                                                CAN_F1R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F1R2_FB4_Pos                                            (4U)
#define CAN_F1R2_FB4_Msk                                            (0x1UL << CAN_F1R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F1R2_FB4                                                CAN_F1R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F1R2_FB5_Pos                                            (5U)
#define CAN_F1R2_FB5_Msk                                            (0x1UL << CAN_F1R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F1R2_FB5                                                CAN_F1R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F1R2_FB6_Pos                                            (6U)
#define CAN_F1R2_FB6_Msk                                            (0x1UL << CAN_F1R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F1R2_FB6                                                CAN_F1R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F1R2_FB7_Pos                                            (7U)
#define CAN_F1R2_FB7_Msk                                            (0x1UL << CAN_F1R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F1R2_FB7                                                CAN_F1R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F1R2_FB8_Pos                                            (8U)
#define CAN_F1R2_FB8_Msk                                            (0x1UL << CAN_F1R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F1R2_FB8                                                CAN_F1R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F1R2_FB9_Pos                                            (9U)
#define CAN_F1R2_FB9_Msk                                            (0x1UL << CAN_F1R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F1R2_FB9                                                CAN_F1R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F1R2_FB10_Pos                                           (10U)
#define CAN_F1R2_FB10_Msk                                           (0x1UL << CAN_F1R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F1R2_FB10                                               CAN_F1R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F1R2_FB11_Pos                                           (11U)
#define CAN_F1R2_FB11_Msk                                           (0x1UL << CAN_F1R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F1R2_FB11                                               CAN_F1R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F1R2_FB12_Pos                                           (12U)
#define CAN_F1R2_FB12_Msk                                           (0x1UL << CAN_F1R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F1R2_FB12                                               CAN_F1R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F1R2_FB13_Pos                                           (13U)
#define CAN_F1R2_FB13_Msk                                           (0x1UL << CAN_F1R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F1R2_FB13                                               CAN_F1R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F1R2_FB14_Pos                                           (14U)
#define CAN_F1R2_FB14_Msk                                           (0x1UL << CAN_F1R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F1R2_FB14                                               CAN_F1R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F1R2_FB15_Pos                                           (15U)
#define CAN_F1R2_FB15_Msk                                           (0x1UL << CAN_F1R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F1R2_FB15                                               CAN_F1R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F1R2_FB16_Pos                                           (16U)
#define CAN_F1R2_FB16_Msk                                           (0x1UL << CAN_F1R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F1R2_FB16                                               CAN_F1R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F1R2_FB17_Pos                                           (17U)
#define CAN_F1R2_FB17_Msk                                           (0x1UL << CAN_F1R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F1R2_FB17                                               CAN_F1R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F1R2_FB18_Pos                                           (18U)
#define CAN_F1R2_FB18_Msk                                           (0x1UL << CAN_F1R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F1R2_FB18                                               CAN_F1R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F1R2_FB19_Pos                                           (19U)
#define CAN_F1R2_FB19_Msk                                           (0x1UL << CAN_F1R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F1R2_FB19                                               CAN_F1R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F1R2_FB20_Pos                                           (20U)
#define CAN_F1R2_FB20_Msk                                           (0x1UL << CAN_F1R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F1R2_FB20                                               CAN_F1R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F1R2_FB21_Pos                                           (21U)
#define CAN_F1R2_FB21_Msk                                           (0x1UL << CAN_F1R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F1R2_FB21                                               CAN_F1R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F1R2_FB22_Pos                                           (22U)
#define CAN_F1R2_FB22_Msk                                           (0x1UL << CAN_F1R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F1R2_FB22                                               CAN_F1R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F1R2_FB23_Pos                                           (23U)
#define CAN_F1R2_FB23_Msk                                           (0x1UL << CAN_F1R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F1R2_FB23                                               CAN_F1R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F1R2_FB24_Pos                                           (24U)
#define CAN_F1R2_FB24_Msk                                           (0x1UL << CAN_F1R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F1R2_FB24                                               CAN_F1R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F1R2_FB25_Pos                                           (25U)
#define CAN_F1R2_FB25_Msk                                           (0x1UL << CAN_F1R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F1R2_FB25                                               CAN_F1R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F1R2_FB26_Pos                                           (26U)
#define CAN_F1R2_FB26_Msk                                           (0x1UL << CAN_F1R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F1R2_FB26                                               CAN_F1R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F1R2_FB27_Pos                                           (27U)
#define CAN_F1R2_FB27_Msk                                           (0x1UL << CAN_F1R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F1R2_FB27                                               CAN_F1R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F1R2_FB28_Pos                                           (28U)
#define CAN_F1R2_FB28_Msk                                           (0x1UL << CAN_F1R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F1R2_FB28                                               CAN_F1R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F1R2_FB29_Pos                                           (29U)
#define CAN_F1R2_FB29_Msk                                           (0x1UL << CAN_F1R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F1R2_FB29                                               CAN_F1R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F1R2_FB30_Pos                                           (30U)
#define CAN_F1R2_FB30_Msk                                           (0x1UL << CAN_F1R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F1R2_FB30                                               CAN_F1R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F1R2_FB31_Pos                                           (31U)
#define CAN_F1R2_FB31_Msk                                           (0x1UL << CAN_F1R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F1R2_FB31                                               CAN_F1R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F2R2 register  *******************/
#define CAN_F2R2_FB0_Pos                                            (0U)
#define CAN_F2R2_FB0_Msk                                            (0x1UL << CAN_F2R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F2R2_FB0                                                CAN_F2R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F2R2_FB1_Pos                                            (1U)
#define CAN_F2R2_FB1_Msk                                            (0x1UL << CAN_F2R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F2R2_FB1                                                CAN_F2R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F2R2_FB2_Pos                                            (2U)
#define CAN_F2R2_FB2_Msk                                            (0x1UL << CAN_F2R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F2R2_FB2                                                CAN_F2R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F2R2_FB3_Pos                                            (3U)
#define CAN_F2R2_FB3_Msk                                            (0x1UL << CAN_F2R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F2R2_FB3                                                CAN_F2R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F2R2_FB4_Pos                                            (4U)
#define CAN_F2R2_FB4_Msk                                            (0x1UL << CAN_F2R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F2R2_FB4                                                CAN_F2R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F2R2_FB5_Pos                                            (5U)
#define CAN_F2R2_FB5_Msk                                            (0x1UL << CAN_F2R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F2R2_FB5                                                CAN_F2R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F2R2_FB6_Pos                                            (6U)
#define CAN_F2R2_FB6_Msk                                            (0x1UL << CAN_F2R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F2R2_FB6                                                CAN_F2R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F2R2_FB7_Pos                                            (7U)
#define CAN_F2R2_FB7_Msk                                            (0x1UL << CAN_F2R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F2R2_FB7                                                CAN_F2R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F2R2_FB8_Pos                                            (8U)
#define CAN_F2R2_FB8_Msk                                            (0x1UL << CAN_F2R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F2R2_FB8                                                CAN_F2R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F2R2_FB9_Pos                                            (9U)
#define CAN_F2R2_FB9_Msk                                            (0x1UL << CAN_F2R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F2R2_FB9                                                CAN_F2R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F2R2_FB10_Pos                                           (10U)
#define CAN_F2R2_FB10_Msk                                           (0x1UL << CAN_F2R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F2R2_FB10                                               CAN_F2R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F2R2_FB11_Pos                                           (11U)
#define CAN_F2R2_FB11_Msk                                           (0x1UL << CAN_F2R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F2R2_FB11                                               CAN_F2R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F2R2_FB12_Pos                                           (12U)
#define CAN_F2R2_FB12_Msk                                           (0x1UL << CAN_F2R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F2R2_FB12                                               CAN_F2R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F2R2_FB13_Pos                                           (13U)
#define CAN_F2R2_FB13_Msk                                           (0x1UL << CAN_F2R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F2R2_FB13                                               CAN_F2R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F2R2_FB14_Pos                                           (14U)
#define CAN_F2R2_FB14_Msk                                           (0x1UL << CAN_F2R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F2R2_FB14                                               CAN_F2R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F2R2_FB15_Pos                                           (15U)
#define CAN_F2R2_FB15_Msk                                           (0x1UL << CAN_F2R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F2R2_FB15                                               CAN_F2R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F2R2_FB16_Pos                                           (16U)
#define CAN_F2R2_FB16_Msk                                           (0x1UL << CAN_F2R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F2R2_FB16                                               CAN_F2R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F2R2_FB17_Pos                                           (17U)
#define CAN_F2R2_FB17_Msk                                           (0x1UL << CAN_F2R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F2R2_FB17                                               CAN_F2R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F2R2_FB18_Pos                                           (18U)
#define CAN_F2R2_FB18_Msk                                           (0x1UL << CAN_F2R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F2R2_FB18                                               CAN_F2R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F2R2_FB19_Pos                                           (19U)
#define CAN_F2R2_FB19_Msk                                           (0x1UL << CAN_F2R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F2R2_FB19                                               CAN_F2R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F2R2_FB20_Pos                                           (20U)
#define CAN_F2R2_FB20_Msk                                           (0x1UL << CAN_F2R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F2R2_FB20                                               CAN_F2R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F2R2_FB21_Pos                                           (21U)
#define CAN_F2R2_FB21_Msk                                           (0x1UL << CAN_F2R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F2R2_FB21                                               CAN_F2R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F2R2_FB22_Pos                                           (22U)
#define CAN_F2R2_FB22_Msk                                           (0x1UL << CAN_F2R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F2R2_FB22                                               CAN_F2R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F2R2_FB23_Pos                                           (23U)
#define CAN_F2R2_FB23_Msk                                           (0x1UL << CAN_F2R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F2R2_FB23                                               CAN_F2R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F2R2_FB24_Pos                                           (24U)
#define CAN_F2R2_FB24_Msk                                           (0x1UL << CAN_F2R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F2R2_FB24                                               CAN_F2R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F2R2_FB25_Pos                                           (25U)
#define CAN_F2R2_FB25_Msk                                           (0x1UL << CAN_F2R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F2R2_FB25                                               CAN_F2R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F2R2_FB26_Pos                                           (26U)
#define CAN_F2R2_FB26_Msk                                           (0x1UL << CAN_F2R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F2R2_FB26                                               CAN_F2R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F2R2_FB27_Pos                                           (27U)
#define CAN_F2R2_FB27_Msk                                           (0x1UL << CAN_F2R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F2R2_FB27                                               CAN_F2R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F2R2_FB28_Pos                                           (28U)
#define CAN_F2R2_FB28_Msk                                           (0x1UL << CAN_F2R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F2R2_FB28                                               CAN_F2R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F2R2_FB29_Pos                                           (29U)
#define CAN_F2R2_FB29_Msk                                           (0x1UL << CAN_F2R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F2R2_FB29                                               CAN_F2R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F2R2_FB30_Pos                                           (30U)
#define CAN_F2R2_FB30_Msk                                           (0x1UL << CAN_F2R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F2R2_FB30                                               CAN_F2R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F2R2_FB31_Pos                                           (31U)
#define CAN_F2R2_FB31_Msk                                           (0x1UL << CAN_F2R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F2R2_FB31                                               CAN_F2R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F3R2 register  *******************/
#define CAN_F3R2_FB0_Pos                                            (0U)
#define CAN_F3R2_FB0_Msk                                            (0x1UL << CAN_F3R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F3R2_FB0                                                CAN_F3R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F3R2_FB1_Pos                                            (1U)
#define CAN_F3R2_FB1_Msk                                            (0x1UL << CAN_F3R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F3R2_FB1                                                CAN_F3R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F3R2_FB2_Pos                                            (2U)
#define CAN_F3R2_FB2_Msk                                            (0x1UL << CAN_F3R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F3R2_FB2                                                CAN_F3R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F3R2_FB3_Pos                                            (3U)
#define CAN_F3R2_FB3_Msk                                            (0x1UL << CAN_F3R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F3R2_FB3                                                CAN_F3R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F3R2_FB4_Pos                                            (4U)
#define CAN_F3R2_FB4_Msk                                            (0x1UL << CAN_F3R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F3R2_FB4                                                CAN_F3R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F3R2_FB5_Pos                                            (5U)
#define CAN_F3R2_FB5_Msk                                            (0x1UL << CAN_F3R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F3R2_FB5                                                CAN_F3R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F3R2_FB6_Pos                                            (6U)
#define CAN_F3R2_FB6_Msk                                            (0x1UL << CAN_F3R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F3R2_FB6                                                CAN_F3R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F3R2_FB7_Pos                                            (7U)
#define CAN_F3R2_FB7_Msk                                            (0x1UL << CAN_F3R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F3R2_FB7                                                CAN_F3R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F3R2_FB8_Pos                                            (8U)
#define CAN_F3R2_FB8_Msk                                            (0x1UL << CAN_F3R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F3R2_FB8                                                CAN_F3R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F3R2_FB9_Pos                                            (9U)
#define CAN_F3R2_FB9_Msk                                            (0x1UL << CAN_F3R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F3R2_FB9                                                CAN_F3R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F3R2_FB10_Pos                                           (10U)
#define CAN_F3R2_FB10_Msk                                           (0x1UL << CAN_F3R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F3R2_FB10                                               CAN_F3R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F3R2_FB11_Pos                                           (11U)
#define CAN_F3R2_FB11_Msk                                           (0x1UL << CAN_F3R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F3R2_FB11                                               CAN_F3R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F3R2_FB12_Pos                                           (12U)
#define CAN_F3R2_FB12_Msk                                           (0x1UL << CAN_F3R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F3R2_FB12                                               CAN_F3R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F3R2_FB13_Pos                                           (13U)
#define CAN_F3R2_FB13_Msk                                           (0x1UL << CAN_F3R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F3R2_FB13                                               CAN_F3R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F3R2_FB14_Pos                                           (14U)
#define CAN_F3R2_FB14_Msk                                           (0x1UL << CAN_F3R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F3R2_FB14                                               CAN_F3R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F3R2_FB15_Pos                                           (15U)
#define CAN_F3R2_FB15_Msk                                           (0x1UL << CAN_F3R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F3R2_FB15                                               CAN_F3R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F3R2_FB16_Pos                                           (16U)
#define CAN_F3R2_FB16_Msk                                           (0x1UL << CAN_F3R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F3R2_FB16                                               CAN_F3R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F3R2_FB17_Pos                                           (17U)
#define CAN_F3R2_FB17_Msk                                           (0x1UL << CAN_F3R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F3R2_FB17                                               CAN_F3R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F3R2_FB18_Pos                                           (18U)
#define CAN_F3R2_FB18_Msk                                           (0x1UL << CAN_F3R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F3R2_FB18                                               CAN_F3R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F3R2_FB19_Pos                                           (19U)
#define CAN_F3R2_FB19_Msk                                           (0x1UL << CAN_F3R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F3R2_FB19                                               CAN_F3R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F3R2_FB20_Pos                                           (20U)
#define CAN_F3R2_FB20_Msk                                           (0x1UL << CAN_F3R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F3R2_FB20                                               CAN_F3R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F3R2_FB21_Pos                                           (21U)
#define CAN_F3R2_FB21_Msk                                           (0x1UL << CAN_F3R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F3R2_FB21                                               CAN_F3R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F3R2_FB22_Pos                                           (22U)
#define CAN_F3R2_FB22_Msk                                           (0x1UL << CAN_F3R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F3R2_FB22                                               CAN_F3R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F3R2_FB23_Pos                                           (23U)
#define CAN_F3R2_FB23_Msk                                           (0x1UL << CAN_F3R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F3R2_FB23                                               CAN_F3R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F3R2_FB24_Pos                                           (24U)
#define CAN_F3R2_FB24_Msk                                           (0x1UL << CAN_F3R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F3R2_FB24                                               CAN_F3R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F3R2_FB25_Pos                                           (25U)
#define CAN_F3R2_FB25_Msk                                           (0x1UL << CAN_F3R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F3R2_FB25                                               CAN_F3R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F3R2_FB26_Pos                                           (26U)
#define CAN_F3R2_FB26_Msk                                           (0x1UL << CAN_F3R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F3R2_FB26                                               CAN_F3R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F3R2_FB27_Pos                                           (27U)
#define CAN_F3R2_FB27_Msk                                           (0x1UL << CAN_F3R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F3R2_FB27                                               CAN_F3R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F3R2_FB28_Pos                                           (28U)
#define CAN_F3R2_FB28_Msk                                           (0x1UL << CAN_F3R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F3R2_FB28                                               CAN_F3R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F3R2_FB29_Pos                                           (29U)
#define CAN_F3R2_FB29_Msk                                           (0x1UL << CAN_F3R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F3R2_FB29                                               CAN_F3R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F3R2_FB30_Pos                                           (30U)
#define CAN_F3R2_FB30_Msk                                           (0x1UL << CAN_F3R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F3R2_FB30                                               CAN_F3R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F3R2_FB31_Pos                                           (31U)
#define CAN_F3R2_FB31_Msk                                           (0x1UL << CAN_F3R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F3R2_FB31                                               CAN_F3R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F4R2 register  *******************/
#define CAN_F4R2_FB0_Pos                                            (0U)
#define CAN_F4R2_FB0_Msk                                            (0x1UL << CAN_F4R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F4R2_FB0                                                CAN_F4R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F4R2_FB1_Pos                                            (1U)
#define CAN_F4R2_FB1_Msk                                            (0x1UL << CAN_F4R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F4R2_FB1                                                CAN_F4R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F4R2_FB2_Pos                                            (2U)
#define CAN_F4R2_FB2_Msk                                            (0x1UL << CAN_F4R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F4R2_FB2                                                CAN_F4R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F4R2_FB3_Pos                                            (3U)
#define CAN_F4R2_FB3_Msk                                            (0x1UL << CAN_F4R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F4R2_FB3                                                CAN_F4R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F4R2_FB4_Pos                                            (4U)
#define CAN_F4R2_FB4_Msk                                            (0x1UL << CAN_F4R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F4R2_FB4                                                CAN_F4R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F4R2_FB5_Pos                                            (5U)
#define CAN_F4R2_FB5_Msk                                            (0x1UL << CAN_F4R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F4R2_FB5                                                CAN_F4R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F4R2_FB6_Pos                                            (6U)
#define CAN_F4R2_FB6_Msk                                            (0x1UL << CAN_F4R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F4R2_FB6                                                CAN_F4R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F4R2_FB7_Pos                                            (7U)
#define CAN_F4R2_FB7_Msk                                            (0x1UL << CAN_F4R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F4R2_FB7                                                CAN_F4R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F4R2_FB8_Pos                                            (8U)
#define CAN_F4R2_FB8_Msk                                            (0x1UL << CAN_F4R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F4R2_FB8                                                CAN_F4R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F4R2_FB9_Pos                                            (9U)
#define CAN_F4R2_FB9_Msk                                            (0x1UL << CAN_F4R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F4R2_FB9                                                CAN_F4R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F4R2_FB10_Pos                                           (10U)
#define CAN_F4R2_FB10_Msk                                           (0x1UL << CAN_F4R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F4R2_FB10                                               CAN_F4R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F4R2_FB11_Pos                                           (11U)
#define CAN_F4R2_FB11_Msk                                           (0x1UL << CAN_F4R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F4R2_FB11                                               CAN_F4R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F4R2_FB12_Pos                                           (12U)
#define CAN_F4R2_FB12_Msk                                           (0x1UL << CAN_F4R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F4R2_FB12                                               CAN_F4R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F4R2_FB13_Pos                                           (13U)
#define CAN_F4R2_FB13_Msk                                           (0x1UL << CAN_F4R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F4R2_FB13                                               CAN_F4R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F4R2_FB14_Pos                                           (14U)
#define CAN_F4R2_FB14_Msk                                           (0x1UL << CAN_F4R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F4R2_FB14                                               CAN_F4R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F4R2_FB15_Pos                                           (15U)
#define CAN_F4R2_FB15_Msk                                           (0x1UL << CAN_F4R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F4R2_FB15                                               CAN_F4R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F4R2_FB16_Pos                                           (16U)
#define CAN_F4R2_FB16_Msk                                           (0x1UL << CAN_F4R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F4R2_FB16                                               CAN_F4R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F4R2_FB17_Pos                                           (17U)
#define CAN_F4R2_FB17_Msk                                           (0x1UL << CAN_F4R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F4R2_FB17                                               CAN_F4R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F4R2_FB18_Pos                                           (18U)
#define CAN_F4R2_FB18_Msk                                           (0x1UL << CAN_F4R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F4R2_FB18                                               CAN_F4R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F4R2_FB19_Pos                                           (19U)
#define CAN_F4R2_FB19_Msk                                           (0x1UL << CAN_F4R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F4R2_FB19                                               CAN_F4R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F4R2_FB20_Pos                                           (20U)
#define CAN_F4R2_FB20_Msk                                           (0x1UL << CAN_F4R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F4R2_FB20                                               CAN_F4R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F4R2_FB21_Pos                                           (21U)
#define CAN_F4R2_FB21_Msk                                           (0x1UL << CAN_F4R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F4R2_FB21                                               CAN_F4R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F4R2_FB22_Pos                                           (22U)
#define CAN_F4R2_FB22_Msk                                           (0x1UL << CAN_F4R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F4R2_FB22                                               CAN_F4R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F4R2_FB23_Pos                                           (23U)
#define CAN_F4R2_FB23_Msk                                           (0x1UL << CAN_F4R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F4R2_FB23                                               CAN_F4R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F4R2_FB24_Pos                                           (24U)
#define CAN_F4R2_FB24_Msk                                           (0x1UL << CAN_F4R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F4R2_FB24                                               CAN_F4R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F4R2_FB25_Pos                                           (25U)
#define CAN_F4R2_FB25_Msk                                           (0x1UL << CAN_F4R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F4R2_FB25                                               CAN_F4R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F4R2_FB26_Pos                                           (26U)
#define CAN_F4R2_FB26_Msk                                           (0x1UL << CAN_F4R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F4R2_FB26                                               CAN_F4R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F4R2_FB27_Pos                                           (27U)
#define CAN_F4R2_FB27_Msk                                           (0x1UL << CAN_F4R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F4R2_FB27                                               CAN_F4R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F4R2_FB28_Pos                                           (28U)
#define CAN_F4R2_FB28_Msk                                           (0x1UL << CAN_F4R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F4R2_FB28                                               CAN_F4R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F4R2_FB29_Pos                                           (29U)
#define CAN_F4R2_FB29_Msk                                           (0x1UL << CAN_F4R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F4R2_FB29                                               CAN_F4R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F4R2_FB30_Pos                                           (30U)
#define CAN_F4R2_FB30_Msk                                           (0x1UL << CAN_F4R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F4R2_FB30                                               CAN_F4R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F4R2_FB31_Pos                                           (31U)
#define CAN_F4R2_FB31_Msk                                           (0x1UL << CAN_F4R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F4R2_FB31                                               CAN_F4R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F5R2 register  *******************/
#define CAN_F5R2_FB0_Pos                                            (0U)
#define CAN_F5R2_FB0_Msk                                            (0x1UL << CAN_F5R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F5R2_FB0                                                CAN_F5R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F5R2_FB1_Pos                                            (1U)
#define CAN_F5R2_FB1_Msk                                            (0x1UL << CAN_F5R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F5R2_FB1                                                CAN_F5R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F5R2_FB2_Pos                                            (2U)
#define CAN_F5R2_FB2_Msk                                            (0x1UL << CAN_F5R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F5R2_FB2                                                CAN_F5R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F5R2_FB3_Pos                                            (3U)
#define CAN_F5R2_FB3_Msk                                            (0x1UL << CAN_F5R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F5R2_FB3                                                CAN_F5R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F5R2_FB4_Pos                                            (4U)
#define CAN_F5R2_FB4_Msk                                            (0x1UL << CAN_F5R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F5R2_FB4                                                CAN_F5R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F5R2_FB5_Pos                                            (5U)
#define CAN_F5R2_FB5_Msk                                            (0x1UL << CAN_F5R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F5R2_FB5                                                CAN_F5R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F5R2_FB6_Pos                                            (6U)
#define CAN_F5R2_FB6_Msk                                            (0x1UL << CAN_F5R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F5R2_FB6                                                CAN_F5R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F5R2_FB7_Pos                                            (7U)
#define CAN_F5R2_FB7_Msk                                            (0x1UL << CAN_F5R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F5R2_FB7                                                CAN_F5R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F5R2_FB8_Pos                                            (8U)
#define CAN_F5R2_FB8_Msk                                            (0x1UL << CAN_F5R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F5R2_FB8                                                CAN_F5R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F5R2_FB9_Pos                                            (9U)
#define CAN_F5R2_FB9_Msk                                            (0x1UL << CAN_F5R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F5R2_FB9                                                CAN_F5R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F5R2_FB10_Pos                                           (10U)
#define CAN_F5R2_FB10_Msk                                           (0x1UL << CAN_F5R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F5R2_FB10                                               CAN_F5R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F5R2_FB11_Pos                                           (11U)
#define CAN_F5R2_FB11_Msk                                           (0x1UL << CAN_F5R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F5R2_FB11                                               CAN_F5R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F5R2_FB12_Pos                                           (12U)
#define CAN_F5R2_FB12_Msk                                           (0x1UL << CAN_F5R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F5R2_FB12                                               CAN_F5R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F5R2_FB13_Pos                                           (13U)
#define CAN_F5R2_FB13_Msk                                           (0x1UL << CAN_F5R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F5R2_FB13                                               CAN_F5R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F5R2_FB14_Pos                                           (14U)
#define CAN_F5R2_FB14_Msk                                           (0x1UL << CAN_F5R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F5R2_FB14                                               CAN_F5R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F5R2_FB15_Pos                                           (15U)
#define CAN_F5R2_FB15_Msk                                           (0x1UL << CAN_F5R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F5R2_FB15                                               CAN_F5R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F5R2_FB16_Pos                                           (16U)
#define CAN_F5R2_FB16_Msk                                           (0x1UL << CAN_F5R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F5R2_FB16                                               CAN_F5R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F5R2_FB17_Pos                                           (17U)
#define CAN_F5R2_FB17_Msk                                           (0x1UL << CAN_F5R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F5R2_FB17                                               CAN_F5R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F5R2_FB18_Pos                                           (18U)
#define CAN_F5R2_FB18_Msk                                           (0x1UL << CAN_F5R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F5R2_FB18                                               CAN_F5R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F5R2_FB19_Pos                                           (19U)
#define CAN_F5R2_FB19_Msk                                           (0x1UL << CAN_F5R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F5R2_FB19                                               CAN_F5R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F5R2_FB20_Pos                                           (20U)
#define CAN_F5R2_FB20_Msk                                           (0x1UL << CAN_F5R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F5R2_FB20                                               CAN_F5R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F5R2_FB21_Pos                                           (21U)
#define CAN_F5R2_FB21_Msk                                           (0x1UL << CAN_F5R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F5R2_FB21                                               CAN_F5R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F5R2_FB22_Pos                                           (22U)
#define CAN_F5R2_FB22_Msk                                           (0x1UL << CAN_F5R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F5R2_FB22                                               CAN_F5R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F5R2_FB23_Pos                                           (23U)
#define CAN_F5R2_FB23_Msk                                           (0x1UL << CAN_F5R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F5R2_FB23                                               CAN_F5R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F5R2_FB24_Pos                                           (24U)
#define CAN_F5R2_FB24_Msk                                           (0x1UL << CAN_F5R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F5R2_FB24                                               CAN_F5R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F5R2_FB25_Pos                                           (25U)
#define CAN_F5R2_FB25_Msk                                           (0x1UL << CAN_F5R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F5R2_FB25                                               CAN_F5R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F5R2_FB26_Pos                                           (26U)
#define CAN_F5R2_FB26_Msk                                           (0x1UL << CAN_F5R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F5R2_FB26                                               CAN_F5R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F5R2_FB27_Pos                                           (27U)
#define CAN_F5R2_FB27_Msk                                           (0x1UL << CAN_F5R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F5R2_FB27                                               CAN_F5R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F5R2_FB28_Pos                                           (28U)
#define CAN_F5R2_FB28_Msk                                           (0x1UL << CAN_F5R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F5R2_FB28                                               CAN_F5R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F5R2_FB29_Pos                                           (29U)
#define CAN_F5R2_FB29_Msk                                           (0x1UL << CAN_F5R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F5R2_FB29                                               CAN_F5R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F5R2_FB30_Pos                                           (30U)
#define CAN_F5R2_FB30_Msk                                           (0x1UL << CAN_F5R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F5R2_FB30                                               CAN_F5R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F5R2_FB31_Pos                                           (31U)
#define CAN_F5R2_FB31_Msk                                           (0x1UL << CAN_F5R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F5R2_FB31                                               CAN_F5R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F6R2 register  *******************/
#define CAN_F6R2_FB0_Pos                                            (0U)
#define CAN_F6R2_FB0_Msk                                            (0x1UL << CAN_F6R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F6R2_FB0                                                CAN_F6R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F6R2_FB1_Pos                                            (1U)
#define CAN_F6R2_FB1_Msk                                            (0x1UL << CAN_F6R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F6R2_FB1                                                CAN_F6R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F6R2_FB2_Pos                                            (2U)
#define CAN_F6R2_FB2_Msk                                            (0x1UL << CAN_F6R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F6R2_FB2                                                CAN_F6R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F6R2_FB3_Pos                                            (3U)
#define CAN_F6R2_FB3_Msk                                            (0x1UL << CAN_F6R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F6R2_FB3                                                CAN_F6R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F6R2_FB4_Pos                                            (4U)
#define CAN_F6R2_FB4_Msk                                            (0x1UL << CAN_F6R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F6R2_FB4                                                CAN_F6R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F6R2_FB5_Pos                                            (5U)
#define CAN_F6R2_FB5_Msk                                            (0x1UL << CAN_F6R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F6R2_FB5                                                CAN_F6R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F6R2_FB6_Pos                                            (6U)
#define CAN_F6R2_FB6_Msk                                            (0x1UL << CAN_F6R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F6R2_FB6                                                CAN_F6R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F6R2_FB7_Pos                                            (7U)
#define CAN_F6R2_FB7_Msk                                            (0x1UL << CAN_F6R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F6R2_FB7                                                CAN_F6R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F6R2_FB8_Pos                                            (8U)
#define CAN_F6R2_FB8_Msk                                            (0x1UL << CAN_F6R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F6R2_FB8                                                CAN_F6R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F6R2_FB9_Pos                                            (9U)
#define CAN_F6R2_FB9_Msk                                            (0x1UL << CAN_F6R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F6R2_FB9                                                CAN_F6R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F6R2_FB10_Pos                                           (10U)
#define CAN_F6R2_FB10_Msk                                           (0x1UL << CAN_F6R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F6R2_FB10                                               CAN_F6R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F6R2_FB11_Pos                                           (11U)
#define CAN_F6R2_FB11_Msk                                           (0x1UL << CAN_F6R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F6R2_FB11                                               CAN_F6R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F6R2_FB12_Pos                                           (12U)
#define CAN_F6R2_FB12_Msk                                           (0x1UL << CAN_F6R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F6R2_FB12                                               CAN_F6R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F6R2_FB13_Pos                                           (13U)
#define CAN_F6R2_FB13_Msk                                           (0x1UL << CAN_F6R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F6R2_FB13                                               CAN_F6R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F6R2_FB14_Pos                                           (14U)
#define CAN_F6R2_FB14_Msk                                           (0x1UL << CAN_F6R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F6R2_FB14                                               CAN_F6R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F6R2_FB15_Pos                                           (15U)
#define CAN_F6R2_FB15_Msk                                           (0x1UL << CAN_F6R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F6R2_FB15                                               CAN_F6R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F6R2_FB16_Pos                                           (16U)
#define CAN_F6R2_FB16_Msk                                           (0x1UL << CAN_F6R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F6R2_FB16                                               CAN_F6R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F6R2_FB17_Pos                                           (17U)
#define CAN_F6R2_FB17_Msk                                           (0x1UL << CAN_F6R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F6R2_FB17                                               CAN_F6R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F6R2_FB18_Pos                                           (18U)
#define CAN_F6R2_FB18_Msk                                           (0x1UL << CAN_F6R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F6R2_FB18                                               CAN_F6R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F6R2_FB19_Pos                                           (19U)
#define CAN_F6R2_FB19_Msk                                           (0x1UL << CAN_F6R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F6R2_FB19                                               CAN_F6R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F6R2_FB20_Pos                                           (20U)
#define CAN_F6R2_FB20_Msk                                           (0x1UL << CAN_F6R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F6R2_FB20                                               CAN_F6R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F6R2_FB21_Pos                                           (21U)
#define CAN_F6R2_FB21_Msk                                           (0x1UL << CAN_F6R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F6R2_FB21                                               CAN_F6R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F6R2_FB22_Pos                                           (22U)
#define CAN_F6R2_FB22_Msk                                           (0x1UL << CAN_F6R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F6R2_FB22                                               CAN_F6R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F6R2_FB23_Pos                                           (23U)
#define CAN_F6R2_FB23_Msk                                           (0x1UL << CAN_F6R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F6R2_FB23                                               CAN_F6R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F6R2_FB24_Pos                                           (24U)
#define CAN_F6R2_FB24_Msk                                           (0x1UL << CAN_F6R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F6R2_FB24                                               CAN_F6R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F6R2_FB25_Pos                                           (25U)
#define CAN_F6R2_FB25_Msk                                           (0x1UL << CAN_F6R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F6R2_FB25                                               CAN_F6R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F6R2_FB26_Pos                                           (26U)
#define CAN_F6R2_FB26_Msk                                           (0x1UL << CAN_F6R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F6R2_FB26                                               CAN_F6R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F6R2_FB27_Pos                                           (27U)
#define CAN_F6R2_FB27_Msk                                           (0x1UL << CAN_F6R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F6R2_FB27                                               CAN_F6R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F6R2_FB28_Pos                                           (28U)
#define CAN_F6R2_FB28_Msk                                           (0x1UL << CAN_F6R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F6R2_FB28                                               CAN_F6R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F6R2_FB29_Pos                                           (29U)
#define CAN_F6R2_FB29_Msk                                           (0x1UL << CAN_F6R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F6R2_FB29                                               CAN_F6R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F6R2_FB30_Pos                                           (30U)
#define CAN_F6R2_FB30_Msk                                           (0x1UL << CAN_F6R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F6R2_FB30                                               CAN_F6R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F6R2_FB31_Pos                                           (31U)
#define CAN_F6R2_FB31_Msk                                           (0x1UL << CAN_F6R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F6R2_FB31                                               CAN_F6R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F7R2 register  *******************/
#define CAN_F7R2_FB0_Pos                                            (0U)
#define CAN_F7R2_FB0_Msk                                            (0x1UL << CAN_F7R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F7R2_FB0                                                CAN_F7R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F7R2_FB1_Pos                                            (1U)
#define CAN_F7R2_FB1_Msk                                            (0x1UL << CAN_F7R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F7R2_FB1                                                CAN_F7R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F7R2_FB2_Pos                                            (2U)
#define CAN_F7R2_FB2_Msk                                            (0x1UL << CAN_F7R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F7R2_FB2                                                CAN_F7R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F7R2_FB3_Pos                                            (3U)
#define CAN_F7R2_FB3_Msk                                            (0x1UL << CAN_F7R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F7R2_FB3                                                CAN_F7R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F7R2_FB4_Pos                                            (4U)
#define CAN_F7R2_FB4_Msk                                            (0x1UL << CAN_F7R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F7R2_FB4                                                CAN_F7R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F7R2_FB5_Pos                                            (5U)
#define CAN_F7R2_FB5_Msk                                            (0x1UL << CAN_F7R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F7R2_FB5                                                CAN_F7R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F7R2_FB6_Pos                                            (6U)
#define CAN_F7R2_FB6_Msk                                            (0x1UL << CAN_F7R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F7R2_FB6                                                CAN_F7R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F7R2_FB7_Pos                                            (7U)
#define CAN_F7R2_FB7_Msk                                            (0x1UL << CAN_F7R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F7R2_FB7                                                CAN_F7R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F7R2_FB8_Pos                                            (8U)
#define CAN_F7R2_FB8_Msk                                            (0x1UL << CAN_F7R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F7R2_FB8                                                CAN_F7R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F7R2_FB9_Pos                                            (9U)
#define CAN_F7R2_FB9_Msk                                            (0x1UL << CAN_F7R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F7R2_FB9                                                CAN_F7R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F7R2_FB10_Pos                                           (10U)
#define CAN_F7R2_FB10_Msk                                           (0x1UL << CAN_F7R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F7R2_FB10                                               CAN_F7R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F7R2_FB11_Pos                                           (11U)
#define CAN_F7R2_FB11_Msk                                           (0x1UL << CAN_F7R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F7R2_FB11                                               CAN_F7R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F7R2_FB12_Pos                                           (12U)
#define CAN_F7R2_FB12_Msk                                           (0x1UL << CAN_F7R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F7R2_FB12                                               CAN_F7R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F7R2_FB13_Pos                                           (13U)
#define CAN_F7R2_FB13_Msk                                           (0x1UL << CAN_F7R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F7R2_FB13                                               CAN_F7R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F7R2_FB14_Pos                                           (14U)
#define CAN_F7R2_FB14_Msk                                           (0x1UL << CAN_F7R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F7R2_FB14                                               CAN_F7R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F7R2_FB15_Pos                                           (15U)
#define CAN_F7R2_FB15_Msk                                           (0x1UL << CAN_F7R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F7R2_FB15                                               CAN_F7R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F7R2_FB16_Pos                                           (16U)
#define CAN_F7R2_FB16_Msk                                           (0x1UL << CAN_F7R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F7R2_FB16                                               CAN_F7R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F7R2_FB17_Pos                                           (17U)
#define CAN_F7R2_FB17_Msk                                           (0x1UL << CAN_F7R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F7R2_FB17                                               CAN_F7R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F7R2_FB18_Pos                                           (18U)
#define CAN_F7R2_FB18_Msk                                           (0x1UL << CAN_F7R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F7R2_FB18                                               CAN_F7R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F7R2_FB19_Pos                                           (19U)
#define CAN_F7R2_FB19_Msk                                           (0x1UL << CAN_F7R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F7R2_FB19                                               CAN_F7R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F7R2_FB20_Pos                                           (20U)
#define CAN_F7R2_FB20_Msk                                           (0x1UL << CAN_F7R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F7R2_FB20                                               CAN_F7R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F7R2_FB21_Pos                                           (21U)
#define CAN_F7R2_FB21_Msk                                           (0x1UL << CAN_F7R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F7R2_FB21                                               CAN_F7R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F7R2_FB22_Pos                                           (22U)
#define CAN_F7R2_FB22_Msk                                           (0x1UL << CAN_F7R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F7R2_FB22                                               CAN_F7R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F7R2_FB23_Pos                                           (23U)
#define CAN_F7R2_FB23_Msk                                           (0x1UL << CAN_F7R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F7R2_FB23                                               CAN_F7R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F7R2_FB24_Pos                                           (24U)
#define CAN_F7R2_FB24_Msk                                           (0x1UL << CAN_F7R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F7R2_FB24                                               CAN_F7R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F7R2_FB25_Pos                                           (25U)
#define CAN_F7R2_FB25_Msk                                           (0x1UL << CAN_F7R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F7R2_FB25                                               CAN_F7R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F7R2_FB26_Pos                                           (26U)
#define CAN_F7R2_FB26_Msk                                           (0x1UL << CAN_F7R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F7R2_FB26                                               CAN_F7R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F7R2_FB27_Pos                                           (27U)
#define CAN_F7R2_FB27_Msk                                           (0x1UL << CAN_F7R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F7R2_FB27                                               CAN_F7R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F7R2_FB28_Pos                                           (28U)
#define CAN_F7R2_FB28_Msk                                           (0x1UL << CAN_F7R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F7R2_FB28                                               CAN_F7R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F7R2_FB29_Pos                                           (29U)
#define CAN_F7R2_FB29_Msk                                           (0x1UL << CAN_F7R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F7R2_FB29                                               CAN_F7R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F7R2_FB30_Pos                                           (30U)
#define CAN_F7R2_FB30_Msk                                           (0x1UL << CAN_F7R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F7R2_FB30                                               CAN_F7R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F7R2_FB31_Pos                                           (31U)
#define CAN_F7R2_FB31_Msk                                           (0x1UL << CAN_F7R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F7R2_FB31                                               CAN_F7R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F8R2 register  *******************/
#define CAN_F8R2_FB0_Pos                                            (0U)
#define CAN_F8R2_FB0_Msk                                            (0x1UL << CAN_F8R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F8R2_FB0                                                CAN_F8R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F8R2_FB1_Pos                                            (1U)
#define CAN_F8R2_FB1_Msk                                            (0x1UL << CAN_F8R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F8R2_FB1                                                CAN_F8R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F8R2_FB2_Pos                                            (2U)
#define CAN_F8R2_FB2_Msk                                            (0x1UL << CAN_F8R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F8R2_FB2                                                CAN_F8R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F8R2_FB3_Pos                                            (3U)
#define CAN_F8R2_FB3_Msk                                            (0x1UL << CAN_F8R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F8R2_FB3                                                CAN_F8R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F8R2_FB4_Pos                                            (4U)
#define CAN_F8R2_FB4_Msk                                            (0x1UL << CAN_F8R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F8R2_FB4                                                CAN_F8R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F8R2_FB5_Pos                                            (5U)
#define CAN_F8R2_FB5_Msk                                            (0x1UL << CAN_F8R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F8R2_FB5                                                CAN_F8R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F8R2_FB6_Pos                                            (6U)
#define CAN_F8R2_FB6_Msk                                            (0x1UL << CAN_F8R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F8R2_FB6                                                CAN_F8R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F8R2_FB7_Pos                                            (7U)
#define CAN_F8R2_FB7_Msk                                            (0x1UL << CAN_F8R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F8R2_FB7                                                CAN_F8R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F8R2_FB8_Pos                                            (8U)
#define CAN_F8R2_FB8_Msk                                            (0x1UL << CAN_F8R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F8R2_FB8                                                CAN_F8R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F8R2_FB9_Pos                                            (9U)
#define CAN_F8R2_FB9_Msk                                            (0x1UL << CAN_F8R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F8R2_FB9                                                CAN_F8R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F8R2_FB10_Pos                                           (10U)
#define CAN_F8R2_FB10_Msk                                           (0x1UL << CAN_F8R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F8R2_FB10                                               CAN_F8R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F8R2_FB11_Pos                                           (11U)
#define CAN_F8R2_FB11_Msk                                           (0x1UL << CAN_F8R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F8R2_FB11                                               CAN_F8R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F8R2_FB12_Pos                                           (12U)
#define CAN_F8R2_FB12_Msk                                           (0x1UL << CAN_F8R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F8R2_FB12                                               CAN_F8R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F8R2_FB13_Pos                                           (13U)
#define CAN_F8R2_FB13_Msk                                           (0x1UL << CAN_F8R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F8R2_FB13                                               CAN_F8R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F8R2_FB14_Pos                                           (14U)
#define CAN_F8R2_FB14_Msk                                           (0x1UL << CAN_F8R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F8R2_FB14                                               CAN_F8R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F8R2_FB15_Pos                                           (15U)
#define CAN_F8R2_FB15_Msk                                           (0x1UL << CAN_F8R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F8R2_FB15                                               CAN_F8R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F8R2_FB16_Pos                                           (16U)
#define CAN_F8R2_FB16_Msk                                           (0x1UL << CAN_F8R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F8R2_FB16                                               CAN_F8R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F8R2_FB17_Pos                                           (17U)
#define CAN_F8R2_FB17_Msk                                           (0x1UL << CAN_F8R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F8R2_FB17                                               CAN_F8R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F8R2_FB18_Pos                                           (18U)
#define CAN_F8R2_FB18_Msk                                           (0x1UL << CAN_F8R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F8R2_FB18                                               CAN_F8R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F8R2_FB19_Pos                                           (19U)
#define CAN_F8R2_FB19_Msk                                           (0x1UL << CAN_F8R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F8R2_FB19                                               CAN_F8R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F8R2_FB20_Pos                                           (20U)
#define CAN_F8R2_FB20_Msk                                           (0x1UL << CAN_F8R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F8R2_FB20                                               CAN_F8R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F8R2_FB21_Pos                                           (21U)
#define CAN_F8R2_FB21_Msk                                           (0x1UL << CAN_F8R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F8R2_FB21                                               CAN_F8R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F8R2_FB22_Pos                                           (22U)
#define CAN_F8R2_FB22_Msk                                           (0x1UL << CAN_F8R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F8R2_FB22                                               CAN_F8R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F8R2_FB23_Pos                                           (23U)
#define CAN_F8R2_FB23_Msk                                           (0x1UL << CAN_F8R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F8R2_FB23                                               CAN_F8R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F8R2_FB24_Pos                                           (24U)
#define CAN_F8R2_FB24_Msk                                           (0x1UL << CAN_F8R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F8R2_FB24                                               CAN_F8R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F8R2_FB25_Pos                                           (25U)
#define CAN_F8R2_FB25_Msk                                           (0x1UL << CAN_F8R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F8R2_FB25                                               CAN_F8R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F8R2_FB26_Pos                                           (26U)
#define CAN_F8R2_FB26_Msk                                           (0x1UL << CAN_F8R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F8R2_FB26                                               CAN_F8R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F8R2_FB27_Pos                                           (27U)
#define CAN_F8R2_FB27_Msk                                           (0x1UL << CAN_F8R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F8R2_FB27                                               CAN_F8R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F8R2_FB28_Pos                                           (28U)
#define CAN_F8R2_FB28_Msk                                           (0x1UL << CAN_F8R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F8R2_FB28                                               CAN_F8R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F8R2_FB29_Pos                                           (29U)
#define CAN_F8R2_FB29_Msk                                           (0x1UL << CAN_F8R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F8R2_FB29                                               CAN_F8R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F8R2_FB30_Pos                                           (30U)
#define CAN_F8R2_FB30_Msk                                           (0x1UL << CAN_F8R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F8R2_FB30                                               CAN_F8R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F8R2_FB31_Pos                                           (31U)
#define CAN_F8R2_FB31_Msk                                           (0x1UL << CAN_F8R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F8R2_FB31                                               CAN_F8R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F9R2 register  *******************/
#define CAN_F9R2_FB0_Pos                                            (0U)
#define CAN_F9R2_FB0_Msk                                            (0x1UL << CAN_F9R2_FB0_Pos)                                    /*!< 0x00000001 */
#define CAN_F9R2_FB0                                                CAN_F9R2_FB0_Msk                                               /*!<Filter bit 0 */
#define CAN_F9R2_FB1_Pos                                            (1U)
#define CAN_F9R2_FB1_Msk                                            (0x1UL << CAN_F9R2_FB1_Pos)                                    /*!< 0x00000002 */
#define CAN_F9R2_FB1                                                CAN_F9R2_FB1_Msk                                               /*!<Filter bit 1 */
#define CAN_F9R2_FB2_Pos                                            (2U)
#define CAN_F9R2_FB2_Msk                                            (0x1UL << CAN_F9R2_FB2_Pos)                                    /*!< 0x00000004 */
#define CAN_F9R2_FB2                                                CAN_F9R2_FB2_Msk                                               /*!<Filter bit 2 */
#define CAN_F9R2_FB3_Pos                                            (3U)
#define CAN_F9R2_FB3_Msk                                            (0x1UL << CAN_F9R2_FB3_Pos)                                    /*!< 0x00000008 */
#define CAN_F9R2_FB3                                                CAN_F9R2_FB3_Msk                                               /*!<Filter bit 3 */
#define CAN_F9R2_FB4_Pos                                            (4U)
#define CAN_F9R2_FB4_Msk                                            (0x1UL << CAN_F9R2_FB4_Pos)                                    /*!< 0x00000010 */
#define CAN_F9R2_FB4                                                CAN_F9R2_FB4_Msk                                               /*!<Filter bit 4 */
#define CAN_F9R2_FB5_Pos                                            (5U)
#define CAN_F9R2_FB5_Msk                                            (0x1UL << CAN_F9R2_FB5_Pos)                                    /*!< 0x00000020 */
#define CAN_F9R2_FB5                                                CAN_F9R2_FB5_Msk                                               /*!<Filter bit 5 */
#define CAN_F9R2_FB6_Pos                                            (6U)
#define CAN_F9R2_FB6_Msk                                            (0x1UL << CAN_F9R2_FB6_Pos)                                    /*!< 0x00000040 */
#define CAN_F9R2_FB6                                                CAN_F9R2_FB6_Msk                                               /*!<Filter bit 6 */
#define CAN_F9R2_FB7_Pos                                            (7U)
#define CAN_F9R2_FB7_Msk                                            (0x1UL << CAN_F9R2_FB7_Pos)                                    /*!< 0x00000080 */
#define CAN_F9R2_FB7                                                CAN_F9R2_FB7_Msk                                               /*!<Filter bit 7 */
#define CAN_F9R2_FB8_Pos                                            (8U)
#define CAN_F9R2_FB8_Msk                                            (0x1UL << CAN_F9R2_FB8_Pos)                                    /*!< 0x00000100 */
#define CAN_F9R2_FB8                                                CAN_F9R2_FB8_Msk                                               /*!<Filter bit 8 */
#define CAN_F9R2_FB9_Pos                                            (9U)
#define CAN_F9R2_FB9_Msk                                            (0x1UL << CAN_F9R2_FB9_Pos)                                    /*!< 0x00000200 */
#define CAN_F9R2_FB9                                                CAN_F9R2_FB9_Msk                                               /*!<Filter bit 9 */
#define CAN_F9R2_FB10_Pos                                           (10U)
#define CAN_F9R2_FB10_Msk                                           (0x1UL << CAN_F9R2_FB10_Pos)                                   /*!< 0x00000400 */
#define CAN_F9R2_FB10                                               CAN_F9R2_FB10_Msk                                              /*!<Filter bit 10 */
#define CAN_F9R2_FB11_Pos                                           (11U)
#define CAN_F9R2_FB11_Msk                                           (0x1UL << CAN_F9R2_FB11_Pos)                                   /*!< 0x00000800 */
#define CAN_F9R2_FB11                                               CAN_F9R2_FB11_Msk                                              /*!<Filter bit 11 */
#define CAN_F9R2_FB12_Pos                                           (12U)
#define CAN_F9R2_FB12_Msk                                           (0x1UL << CAN_F9R2_FB12_Pos)                                   /*!< 0x00001000 */
#define CAN_F9R2_FB12                                               CAN_F9R2_FB12_Msk                                              /*!<Filter bit 12 */
#define CAN_F9R2_FB13_Pos                                           (13U)
#define CAN_F9R2_FB13_Msk                                           (0x1UL << CAN_F9R2_FB13_Pos)                                   /*!< 0x00002000 */
#define CAN_F9R2_FB13                                               CAN_F9R2_FB13_Msk                                              /*!<Filter bit 13 */
#define CAN_F9R2_FB14_Pos                                           (14U)
#define CAN_F9R2_FB14_Msk                                           (0x1UL << CAN_F9R2_FB14_Pos)                                   /*!< 0x00004000 */
#define CAN_F9R2_FB14                                               CAN_F9R2_FB14_Msk                                              /*!<Filter bit 14 */
#define CAN_F9R2_FB15_Pos                                           (15U)
#define CAN_F9R2_FB15_Msk                                           (0x1UL << CAN_F9R2_FB15_Pos)                                   /*!< 0x00008000 */
#define CAN_F9R2_FB15                                               CAN_F9R2_FB15_Msk                                              /*!<Filter bit 15 */
#define CAN_F9R2_FB16_Pos                                           (16U)
#define CAN_F9R2_FB16_Msk                                           (0x1UL << CAN_F9R2_FB16_Pos)                                   /*!< 0x00010000 */
#define CAN_F9R2_FB16                                               CAN_F9R2_FB16_Msk                                              /*!<Filter bit 16 */
#define CAN_F9R2_FB17_Pos                                           (17U)
#define CAN_F9R2_FB17_Msk                                           (0x1UL << CAN_F9R2_FB17_Pos)                                   /*!< 0x00020000 */
#define CAN_F9R2_FB17                                               CAN_F9R2_FB17_Msk                                              /*!<Filter bit 17 */
#define CAN_F9R2_FB18_Pos                                           (18U)
#define CAN_F9R2_FB18_Msk                                           (0x1UL << CAN_F9R2_FB18_Pos)                                   /*!< 0x00040000 */
#define CAN_F9R2_FB18                                               CAN_F9R2_FB18_Msk                                              /*!<Filter bit 18 */
#define CAN_F9R2_FB19_Pos                                           (19U)
#define CAN_F9R2_FB19_Msk                                           (0x1UL << CAN_F9R2_FB19_Pos)                                   /*!< 0x00080000 */
#define CAN_F9R2_FB19                                               CAN_F9R2_FB19_Msk                                              /*!<Filter bit 19 */
#define CAN_F9R2_FB20_Pos                                           (20U)
#define CAN_F9R2_FB20_Msk                                           (0x1UL << CAN_F9R2_FB20_Pos)                                   /*!< 0x00100000 */
#define CAN_F9R2_FB20                                               CAN_F9R2_FB20_Msk                                              /*!<Filter bit 20 */
#define CAN_F9R2_FB21_Pos                                           (21U)
#define CAN_F9R2_FB21_Msk                                           (0x1UL << CAN_F9R2_FB21_Pos)                                   /*!< 0x00200000 */
#define CAN_F9R2_FB21                                               CAN_F9R2_FB21_Msk                                              /*!<Filter bit 21 */
#define CAN_F9R2_FB22_Pos                                           (22U)
#define CAN_F9R2_FB22_Msk                                           (0x1UL << CAN_F9R2_FB22_Pos)                                   /*!< 0x00400000 */
#define CAN_F9R2_FB22                                               CAN_F9R2_FB22_Msk                                              /*!<Filter bit 22 */
#define CAN_F9R2_FB23_Pos                                           (23U)
#define CAN_F9R2_FB23_Msk                                           (0x1UL << CAN_F9R2_FB23_Pos)                                   /*!< 0x00800000 */
#define CAN_F9R2_FB23                                               CAN_F9R2_FB23_Msk                                              /*!<Filter bit 23 */
#define CAN_F9R2_FB24_Pos                                           (24U)
#define CAN_F9R2_FB24_Msk                                           (0x1UL << CAN_F9R2_FB24_Pos)                                   /*!< 0x01000000 */
#define CAN_F9R2_FB24                                               CAN_F9R2_FB24_Msk                                              /*!<Filter bit 24 */
#define CAN_F9R2_FB25_Pos                                           (25U)
#define CAN_F9R2_FB25_Msk                                           (0x1UL << CAN_F9R2_FB25_Pos)                                   /*!< 0x02000000 */
#define CAN_F9R2_FB25                                               CAN_F9R2_FB25_Msk                                              /*!<Filter bit 25 */
#define CAN_F9R2_FB26_Pos                                           (26U)
#define CAN_F9R2_FB26_Msk                                           (0x1UL << CAN_F9R2_FB26_Pos)                                   /*!< 0x04000000 */
#define CAN_F9R2_FB26                                               CAN_F9R2_FB26_Msk                                              /*!<Filter bit 26 */
#define CAN_F9R2_FB27_Pos                                           (27U)
#define CAN_F9R2_FB27_Msk                                           (0x1UL << CAN_F9R2_FB27_Pos)                                   /*!< 0x08000000 */
#define CAN_F9R2_FB27                                               CAN_F9R2_FB27_Msk                                              /*!<Filter bit 27 */
#define CAN_F9R2_FB28_Pos                                           (28U)
#define CAN_F9R2_FB28_Msk                                           (0x1UL << CAN_F9R2_FB28_Pos)                                   /*!< 0x10000000 */
#define CAN_F9R2_FB28                                               CAN_F9R2_FB28_Msk                                              /*!<Filter bit 28 */
#define CAN_F9R2_FB29_Pos                                           (29U)
#define CAN_F9R2_FB29_Msk                                           (0x1UL << CAN_F9R2_FB29_Pos)                                   /*!< 0x20000000 */
#define CAN_F9R2_FB29                                               CAN_F9R2_FB29_Msk                                              /*!<Filter bit 29 */
#define CAN_F9R2_FB30_Pos                                           (30U)
#define CAN_F9R2_FB30_Msk                                           (0x1UL << CAN_F9R2_FB30_Pos)                                   /*!< 0x40000000 */
#define CAN_F9R2_FB30                                               CAN_F9R2_FB30_Msk                                              /*!<Filter bit 30 */
#define CAN_F9R2_FB31_Pos                                           (31U)
#define CAN_F9R2_FB31_Msk                                           (0x1UL << CAN_F9R2_FB31_Pos)                                   /*!< 0x80000000 */
#define CAN_F9R2_FB31                                               CAN_F9R2_FB31_Msk                                              /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F10R2 register  ******************/
#define CAN_F10R2_FB0_Pos                                           (0U)
#define CAN_F10R2_FB0_Msk                                           (0x1UL << CAN_F10R2_FB0_Pos)                                   /*!< 0x00000001 */
#define CAN_F10R2_FB0                                               CAN_F10R2_FB0_Msk                                              /*!<Filter bit 0 */
#define CAN_F10R2_FB1_Pos                                           (1U)
#define CAN_F10R2_FB1_Msk                                           (0x1UL << CAN_F10R2_FB1_Pos)                                   /*!< 0x00000002 */
#define CAN_F10R2_FB1                                               CAN_F10R2_FB1_Msk                                              /*!<Filter bit 1 */
#define CAN_F10R2_FB2_Pos                                           (2U)
#define CAN_F10R2_FB2_Msk                                           (0x1UL << CAN_F10R2_FB2_Pos)                                   /*!< 0x00000004 */
#define CAN_F10R2_FB2                                               CAN_F10R2_FB2_Msk                                              /*!<Filter bit 2 */
#define CAN_F10R2_FB3_Pos                                           (3U)
#define CAN_F10R2_FB3_Msk                                           (0x1UL << CAN_F10R2_FB3_Pos)                                   /*!< 0x00000008 */
#define CAN_F10R2_FB3                                               CAN_F10R2_FB3_Msk                                              /*!<Filter bit 3 */
#define CAN_F10R2_FB4_Pos                                           (4U)
#define CAN_F10R2_FB4_Msk                                           (0x1UL << CAN_F10R2_FB4_Pos)                                   /*!< 0x00000010 */
#define CAN_F10R2_FB4                                               CAN_F10R2_FB4_Msk                                              /*!<Filter bit 4 */
#define CAN_F10R2_FB5_Pos                                           (5U)
#define CAN_F10R2_FB5_Msk                                           (0x1UL << CAN_F10R2_FB5_Pos)                                   /*!< 0x00000020 */
#define CAN_F10R2_FB5                                               CAN_F10R2_FB5_Msk                                              /*!<Filter bit 5 */
#define CAN_F10R2_FB6_Pos                                           (6U)
#define CAN_F10R2_FB6_Msk                                           (0x1UL << CAN_F10R2_FB6_Pos)                                   /*!< 0x00000040 */
#define CAN_F10R2_FB6                                               CAN_F10R2_FB6_Msk                                              /*!<Filter bit 6 */
#define CAN_F10R2_FB7_Pos                                           (7U)
#define CAN_F10R2_FB7_Msk                                           (0x1UL << CAN_F10R2_FB7_Pos)                                   /*!< 0x00000080 */
#define CAN_F10R2_FB7                                               CAN_F10R2_FB7_Msk                                              /*!<Filter bit 7 */
#define CAN_F10R2_FB8_Pos                                           (8U)
#define CAN_F10R2_FB8_Msk                                           (0x1UL << CAN_F10R2_FB8_Pos)                                   /*!< 0x00000100 */
#define CAN_F10R2_FB8                                               CAN_F10R2_FB8_Msk                                              /*!<Filter bit 8 */
#define CAN_F10R2_FB9_Pos                                           (9U)
#define CAN_F10R2_FB9_Msk                                           (0x1UL << CAN_F10R2_FB9_Pos)                                   /*!< 0x00000200 */
#define CAN_F10R2_FB9                                               CAN_F10R2_FB9_Msk                                              /*!<Filter bit 9 */
#define CAN_F10R2_FB10_Pos                                          (10U)
#define CAN_F10R2_FB10_Msk                                          (0x1UL << CAN_F10R2_FB10_Pos)                                  /*!< 0x00000400 */
#define CAN_F10R2_FB10                                              CAN_F10R2_FB10_Msk                                             /*!<Filter bit 10 */
#define CAN_F10R2_FB11_Pos                                          (11U)
#define CAN_F10R2_FB11_Msk                                          (0x1UL << CAN_F10R2_FB11_Pos)                                  /*!< 0x00000800 */
#define CAN_F10R2_FB11                                              CAN_F10R2_FB11_Msk                                             /*!<Filter bit 11 */
#define CAN_F10R2_FB12_Pos                                          (12U)
#define CAN_F10R2_FB12_Msk                                          (0x1UL << CAN_F10R2_FB12_Pos)                                  /*!< 0x00001000 */
#define CAN_F10R2_FB12                                              CAN_F10R2_FB12_Msk                                             /*!<Filter bit 12 */
#define CAN_F10R2_FB13_Pos                                          (13U)
#define CAN_F10R2_FB13_Msk                                          (0x1UL << CAN_F10R2_FB13_Pos)                                  /*!< 0x00002000 */
#define CAN_F10R2_FB13                                              CAN_F10R2_FB13_Msk                                             /*!<Filter bit 13 */
#define CAN_F10R2_FB14_Pos                                          (14U)
#define CAN_F10R2_FB14_Msk                                          (0x1UL << CAN_F10R2_FB14_Pos)                                  /*!< 0x00004000 */
#define CAN_F10R2_FB14                                              CAN_F10R2_FB14_Msk                                             /*!<Filter bit 14 */
#define CAN_F10R2_FB15_Pos                                          (15U)
#define CAN_F10R2_FB15_Msk                                          (0x1UL << CAN_F10R2_FB15_Pos)                                  /*!< 0x00008000 */
#define CAN_F10R2_FB15                                              CAN_F10R2_FB15_Msk                                             /*!<Filter bit 15 */
#define CAN_F10R2_FB16_Pos                                          (16U)
#define CAN_F10R2_FB16_Msk                                          (0x1UL << CAN_F10R2_FB16_Pos)                                  /*!< 0x00010000 */
#define CAN_F10R2_FB16                                              CAN_F10R2_FB16_Msk                                             /*!<Filter bit 16 */
#define CAN_F10R2_FB17_Pos                                          (17U)
#define CAN_F10R2_FB17_Msk                                          (0x1UL << CAN_F10R2_FB17_Pos)                                  /*!< 0x00020000 */
#define CAN_F10R2_FB17                                              CAN_F10R2_FB17_Msk                                             /*!<Filter bit 17 */
#define CAN_F10R2_FB18_Pos                                          (18U)
#define CAN_F10R2_FB18_Msk                                          (0x1UL << CAN_F10R2_FB18_Pos)                                  /*!< 0x00040000 */
#define CAN_F10R2_FB18                                              CAN_F10R2_FB18_Msk                                             /*!<Filter bit 18 */
#define CAN_F10R2_FB19_Pos                                          (19U)
#define CAN_F10R2_FB19_Msk                                          (0x1UL << CAN_F10R2_FB19_Pos)                                  /*!< 0x00080000 */
#define CAN_F10R2_FB19                                              CAN_F10R2_FB19_Msk                                             /*!<Filter bit 19 */
#define CAN_F10R2_FB20_Pos                                          (20U)
#define CAN_F10R2_FB20_Msk                                          (0x1UL << CAN_F10R2_FB20_Pos)                                  /*!< 0x00100000 */
#define CAN_F10R2_FB20                                              CAN_F10R2_FB20_Msk                                             /*!<Filter bit 20 */
#define CAN_F10R2_FB21_Pos                                          (21U)
#define CAN_F10R2_FB21_Msk                                          (0x1UL << CAN_F10R2_FB21_Pos)                                  /*!< 0x00200000 */
#define CAN_F10R2_FB21                                              CAN_F10R2_FB21_Msk                                             /*!<Filter bit 21 */
#define CAN_F10R2_FB22_Pos                                          (22U)
#define CAN_F10R2_FB22_Msk                                          (0x1UL << CAN_F10R2_FB22_Pos)                                  /*!< 0x00400000 */
#define CAN_F10R2_FB22                                              CAN_F10R2_FB22_Msk                                             /*!<Filter bit 22 */
#define CAN_F10R2_FB23_Pos                                          (23U)
#define CAN_F10R2_FB23_Msk                                          (0x1UL << CAN_F10R2_FB23_Pos)                                  /*!< 0x00800000 */
#define CAN_F10R2_FB23                                              CAN_F10R2_FB23_Msk                                             /*!<Filter bit 23 */
#define CAN_F10R2_FB24_Pos                                          (24U)
#define CAN_F10R2_FB24_Msk                                          (0x1UL << CAN_F10R2_FB24_Pos)                                  /*!< 0x01000000 */
#define CAN_F10R2_FB24                                              CAN_F10R2_FB24_Msk                                             /*!<Filter bit 24 */
#define CAN_F10R2_FB25_Pos                                          (25U)
#define CAN_F10R2_FB25_Msk                                          (0x1UL << CAN_F10R2_FB25_Pos)                                  /*!< 0x02000000 */
#define CAN_F10R2_FB25                                              CAN_F10R2_FB25_Msk                                             /*!<Filter bit 25 */
#define CAN_F10R2_FB26_Pos                                          (26U)
#define CAN_F10R2_FB26_Msk                                          (0x1UL << CAN_F10R2_FB26_Pos)                                  /*!< 0x04000000 */
#define CAN_F10R2_FB26                                              CAN_F10R2_FB26_Msk                                             /*!<Filter bit 26 */
#define CAN_F10R2_FB27_Pos                                          (27U)
#define CAN_F10R2_FB27_Msk                                          (0x1UL << CAN_F10R2_FB27_Pos)                                  /*!< 0x08000000 */
#define CAN_F10R2_FB27                                              CAN_F10R2_FB27_Msk                                             /*!<Filter bit 27 */
#define CAN_F10R2_FB28_Pos                                          (28U)
#define CAN_F10R2_FB28_Msk                                          (0x1UL << CAN_F10R2_FB28_Pos)                                  /*!< 0x10000000 */
#define CAN_F10R2_FB28                                              CAN_F10R2_FB28_Msk                                             /*!<Filter bit 28 */
#define CAN_F10R2_FB29_Pos                                          (29U)
#define CAN_F10R2_FB29_Msk                                          (0x1UL << CAN_F10R2_FB29_Pos)                                  /*!< 0x20000000 */
#define CAN_F10R2_FB29                                              CAN_F10R2_FB29_Msk                                             /*!<Filter bit 29 */
#define CAN_F10R2_FB30_Pos                                          (30U)
#define CAN_F10R2_FB30_Msk                                          (0x1UL << CAN_F10R2_FB30_Pos)                                  /*!< 0x40000000 */
#define CAN_F10R2_FB30                                              CAN_F10R2_FB30_Msk                                             /*!<Filter bit 30 */
#define CAN_F10R2_FB31_Pos                                          (31U)
#define CAN_F10R2_FB31_Msk                                          (0x1UL << CAN_F10R2_FB31_Pos)                                  /*!< 0x80000000 */
#define CAN_F10R2_FB31                                              CAN_F10R2_FB31_Msk                                             /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F11R2 register  ******************/
#define CAN_F11R2_FB0_Pos                                           (0U)
#define CAN_F11R2_FB0_Msk                                           (0x1UL << CAN_F11R2_FB0_Pos)                                   /*!< 0x00000001 */
#define CAN_F11R2_FB0                                               CAN_F11R2_FB0_Msk                                              /*!<Filter bit 0 */
#define CAN_F11R2_FB1_Pos                                           (1U)
#define CAN_F11R2_FB1_Msk                                           (0x1UL << CAN_F11R2_FB1_Pos)                                   /*!< 0x00000002 */
#define CAN_F11R2_FB1                                               CAN_F11R2_FB1_Msk                                              /*!<Filter bit 1 */
#define CAN_F11R2_FB2_Pos                                           (2U)
#define CAN_F11R2_FB2_Msk                                           (0x1UL << CAN_F11R2_FB2_Pos)                                   /*!< 0x00000004 */
#define CAN_F11R2_FB2                                               CAN_F11R2_FB2_Msk                                              /*!<Filter bit 2 */
#define CAN_F11R2_FB3_Pos                                           (3U)
#define CAN_F11R2_FB3_Msk                                           (0x1UL << CAN_F11R2_FB3_Pos)                                   /*!< 0x00000008 */
#define CAN_F11R2_FB3                                               CAN_F11R2_FB3_Msk                                              /*!<Filter bit 3 */
#define CAN_F11R2_FB4_Pos                                           (4U)
#define CAN_F11R2_FB4_Msk                                           (0x1UL << CAN_F11R2_FB4_Pos)                                   /*!< 0x00000010 */
#define CAN_F11R2_FB4                                               CAN_F11R2_FB4_Msk                                              /*!<Filter bit 4 */
#define CAN_F11R2_FB5_Pos                                           (5U)
#define CAN_F11R2_FB5_Msk                                           (0x1UL << CAN_F11R2_FB5_Pos)                                   /*!< 0x00000020 */
#define CAN_F11R2_FB5                                               CAN_F11R2_FB5_Msk                                              /*!<Filter bit 5 */
#define CAN_F11R2_FB6_Pos                                           (6U)
#define CAN_F11R2_FB6_Msk                                           (0x1UL << CAN_F11R2_FB6_Pos)                                   /*!< 0x00000040 */
#define CAN_F11R2_FB6                                               CAN_F11R2_FB6_Msk                                              /*!<Filter bit 6 */
#define CAN_F11R2_FB7_Pos                                           (7U)
#define CAN_F11R2_FB7_Msk                                           (0x1UL << CAN_F11R2_FB7_Pos)                                   /*!< 0x00000080 */
#define CAN_F11R2_FB7                                               CAN_F11R2_FB7_Msk                                              /*!<Filter bit 7 */
#define CAN_F11R2_FB8_Pos                                           (8U)
#define CAN_F11R2_FB8_Msk                                           (0x1UL << CAN_F11R2_FB8_Pos)                                   /*!< 0x00000100 */
#define CAN_F11R2_FB8                                               CAN_F11R2_FB8_Msk                                              /*!<Filter bit 8 */
#define CAN_F11R2_FB9_Pos                                           (9U)
#define CAN_F11R2_FB9_Msk                                           (0x1UL << CAN_F11R2_FB9_Pos)                                   /*!< 0x00000200 */
#define CAN_F11R2_FB9                                               CAN_F11R2_FB9_Msk                                              /*!<Filter bit 9 */
#define CAN_F11R2_FB10_Pos                                          (10U)
#define CAN_F11R2_FB10_Msk                                          (0x1UL << CAN_F11R2_FB10_Pos)                                  /*!< 0x00000400 */
#define CAN_F11R2_FB10                                              CAN_F11R2_FB10_Msk                                             /*!<Filter bit 10 */
#define CAN_F11R2_FB11_Pos                                          (11U)
#define CAN_F11R2_FB11_Msk                                          (0x1UL << CAN_F11R2_FB11_Pos)                                  /*!< 0x00000800 */
#define CAN_F11R2_FB11                                              CAN_F11R2_FB11_Msk                                             /*!<Filter bit 11 */
#define CAN_F11R2_FB12_Pos                                          (12U)
#define CAN_F11R2_FB12_Msk                                          (0x1UL << CAN_F11R2_FB12_Pos)                                  /*!< 0x00001000 */
#define CAN_F11R2_FB12                                              CAN_F11R2_FB12_Msk                                             /*!<Filter bit 12 */
#define CAN_F11R2_FB13_Pos                                          (13U)
#define CAN_F11R2_FB13_Msk                                          (0x1UL << CAN_F11R2_FB13_Pos)                                  /*!< 0x00002000 */
#define CAN_F11R2_FB13                                              CAN_F11R2_FB13_Msk                                             /*!<Filter bit 13 */
#define CAN_F11R2_FB14_Pos                                          (14U)
#define CAN_F11R2_FB14_Msk                                          (0x1UL << CAN_F11R2_FB14_Pos)                                  /*!< 0x00004000 */
#define CAN_F11R2_FB14                                              CAN_F11R2_FB14_Msk                                             /*!<Filter bit 14 */
#define CAN_F11R2_FB15_Pos                                          (15U)
#define CAN_F11R2_FB15_Msk                                          (0x1UL << CAN_F11R2_FB15_Pos)                                  /*!< 0x00008000 */
#define CAN_F11R2_FB15                                              CAN_F11R2_FB15_Msk                                             /*!<Filter bit 15 */
#define CAN_F11R2_FB16_Pos                                          (16U)
#define CAN_F11R2_FB16_Msk                                          (0x1UL << CAN_F11R2_FB16_Pos)                                  /*!< 0x00010000 */
#define CAN_F11R2_FB16                                              CAN_F11R2_FB16_Msk                                             /*!<Filter bit 16 */
#define CAN_F11R2_FB17_Pos                                          (17U)
#define CAN_F11R2_FB17_Msk                                          (0x1UL << CAN_F11R2_FB17_Pos)                                  /*!< 0x00020000 */
#define CAN_F11R2_FB17                                              CAN_F11R2_FB17_Msk                                             /*!<Filter bit 17 */
#define CAN_F11R2_FB18_Pos                                          (18U)
#define CAN_F11R2_FB18_Msk                                          (0x1UL << CAN_F11R2_FB18_Pos)                                  /*!< 0x00040000 */
#define CAN_F11R2_FB18                                              CAN_F11R2_FB18_Msk                                             /*!<Filter bit 18 */
#define CAN_F11R2_FB19_Pos                                          (19U)
#define CAN_F11R2_FB19_Msk                                          (0x1UL << CAN_F11R2_FB19_Pos)                                  /*!< 0x00080000 */
#define CAN_F11R2_FB19                                              CAN_F11R2_FB19_Msk                                             /*!<Filter bit 19 */
#define CAN_F11R2_FB20_Pos                                          (20U)
#define CAN_F11R2_FB20_Msk                                          (0x1UL << CAN_F11R2_FB20_Pos)                                  /*!< 0x00100000 */
#define CAN_F11R2_FB20                                              CAN_F11R2_FB20_Msk                                             /*!<Filter bit 20 */
#define CAN_F11R2_FB21_Pos                                          (21U)
#define CAN_F11R2_FB21_Msk                                          (0x1UL << CAN_F11R2_FB21_Pos)                                  /*!< 0x00200000 */
#define CAN_F11R2_FB21                                              CAN_F11R2_FB21_Msk                                             /*!<Filter bit 21 */
#define CAN_F11R2_FB22_Pos                                          (22U)
#define CAN_F11R2_FB22_Msk                                          (0x1UL << CAN_F11R2_FB22_Pos)                                  /*!< 0x00400000 */
#define CAN_F11R2_FB22                                              CAN_F11R2_FB22_Msk                                             /*!<Filter bit 22 */
#define CAN_F11R2_FB23_Pos                                          (23U)
#define CAN_F11R2_FB23_Msk                                          (0x1UL << CAN_F11R2_FB23_Pos)                                  /*!< 0x00800000 */
#define CAN_F11R2_FB23                                              CAN_F11R2_FB23_Msk                                             /*!<Filter bit 23 */
#define CAN_F11R2_FB24_Pos                                          (24U)
#define CAN_F11R2_FB24_Msk                                          (0x1UL << CAN_F11R2_FB24_Pos)                                  /*!< 0x01000000 */
#define CAN_F11R2_FB24                                              CAN_F11R2_FB24_Msk                                             /*!<Filter bit 24 */
#define CAN_F11R2_FB25_Pos                                          (25U)
#define CAN_F11R2_FB25_Msk                                          (0x1UL << CAN_F11R2_FB25_Pos)                                  /*!< 0x02000000 */
#define CAN_F11R2_FB25                                              CAN_F11R2_FB25_Msk                                             /*!<Filter bit 25 */
#define CAN_F11R2_FB26_Pos                                          (26U)
#define CAN_F11R2_FB26_Msk                                          (0x1UL << CAN_F11R2_FB26_Pos)                                  /*!< 0x04000000 */
#define CAN_F11R2_FB26                                              CAN_F11R2_FB26_Msk                                             /*!<Filter bit 26 */
#define CAN_F11R2_FB27_Pos                                          (27U)
#define CAN_F11R2_FB27_Msk                                          (0x1UL << CAN_F11R2_FB27_Pos)                                  /*!< 0x08000000 */
#define CAN_F11R2_FB27                                              CAN_F11R2_FB27_Msk                                             /*!<Filter bit 27 */
#define CAN_F11R2_FB28_Pos                                          (28U)
#define CAN_F11R2_FB28_Msk                                          (0x1UL << CAN_F11R2_FB28_Pos)                                  /*!< 0x10000000 */
#define CAN_F11R2_FB28                                              CAN_F11R2_FB28_Msk                                             /*!<Filter bit 28 */
#define CAN_F11R2_FB29_Pos                                          (29U)
#define CAN_F11R2_FB29_Msk                                          (0x1UL << CAN_F11R2_FB29_Pos)                                  /*!< 0x20000000 */
#define CAN_F11R2_FB29                                              CAN_F11R2_FB29_Msk                                             /*!<Filter bit 29 */
#define CAN_F11R2_FB30_Pos                                          (30U)
#define CAN_F11R2_FB30_Msk                                          (0x1UL << CAN_F11R2_FB30_Pos)                                  /*!< 0x40000000 */
#define CAN_F11R2_FB30                                              CAN_F11R2_FB30_Msk                                             /*!<Filter bit 30 */
#define CAN_F11R2_FB31_Pos                                          (31U)
#define CAN_F11R2_FB31_Msk                                          (0x1UL << CAN_F11R2_FB31_Pos)                                  /*!< 0x80000000 */
#define CAN_F11R2_FB31                                              CAN_F11R2_FB31_Msk                                             /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F12R2 register  ******************/
#define CAN_F12R2_FB0_Pos                                           (0U)
#define CAN_F12R2_FB0_Msk                                           (0x1UL << CAN_F12R2_FB0_Pos)                                   /*!< 0x00000001 */
#define CAN_F12R2_FB0                                               CAN_F12R2_FB0_Msk                                              /*!<Filter bit 0 */
#define CAN_F12R2_FB1_Pos                                           (1U)
#define CAN_F12R2_FB1_Msk                                           (0x1UL << CAN_F12R2_FB1_Pos)                                   /*!< 0x00000002 */
#define CAN_F12R2_FB1                                               CAN_F12R2_FB1_Msk                                              /*!<Filter bit 1 */
#define CAN_F12R2_FB2_Pos                                           (2U)
#define CAN_F12R2_FB2_Msk                                           (0x1UL << CAN_F12R2_FB2_Pos)                                   /*!< 0x00000004 */
#define CAN_F12R2_FB2                                               CAN_F12R2_FB2_Msk                                              /*!<Filter bit 2 */
#define CAN_F12R2_FB3_Pos                                           (3U)
#define CAN_F12R2_FB3_Msk                                           (0x1UL << CAN_F12R2_FB3_Pos)                                   /*!< 0x00000008 */
#define CAN_F12R2_FB3                                               CAN_F12R2_FB3_Msk                                              /*!<Filter bit 3 */
#define CAN_F12R2_FB4_Pos                                           (4U)
#define CAN_F12R2_FB4_Msk                                           (0x1UL << CAN_F12R2_FB4_Pos)                                   /*!< 0x00000010 */
#define CAN_F12R2_FB4                                               CAN_F12R2_FB4_Msk                                              /*!<Filter bit 4 */
#define CAN_F12R2_FB5_Pos                                           (5U)
#define CAN_F12R2_FB5_Msk                                           (0x1UL << CAN_F12R2_FB5_Pos)                                   /*!< 0x00000020 */
#define CAN_F12R2_FB5                                               CAN_F12R2_FB5_Msk                                              /*!<Filter bit 5 */
#define CAN_F12R2_FB6_Pos                                           (6U)
#define CAN_F12R2_FB6_Msk                                           (0x1UL << CAN_F12R2_FB6_Pos)                                   /*!< 0x00000040 */
#define CAN_F12R2_FB6                                               CAN_F12R2_FB6_Msk                                              /*!<Filter bit 6 */
#define CAN_F12R2_FB7_Pos                                           (7U)
#define CAN_F12R2_FB7_Msk                                           (0x1UL << CAN_F12R2_FB7_Pos)                                   /*!< 0x00000080 */
#define CAN_F12R2_FB7                                               CAN_F12R2_FB7_Msk                                              /*!<Filter bit 7 */
#define CAN_F12R2_FB8_Pos                                           (8U)
#define CAN_F12R2_FB8_Msk                                           (0x1UL << CAN_F12R2_FB8_Pos)                                   /*!< 0x00000100 */
#define CAN_F12R2_FB8                                               CAN_F12R2_FB8_Msk                                              /*!<Filter bit 8 */
#define CAN_F12R2_FB9_Pos                                           (9U)
#define CAN_F12R2_FB9_Msk                                           (0x1UL << CAN_F12R2_FB9_Pos)                                   /*!< 0x00000200 */
#define CAN_F12R2_FB9                                               CAN_F12R2_FB9_Msk                                              /*!<Filter bit 9 */
#define CAN_F12R2_FB10_Pos                                          (10U)
#define CAN_F12R2_FB10_Msk                                          (0x1UL << CAN_F12R2_FB10_Pos)                                  /*!< 0x00000400 */
#define CAN_F12R2_FB10                                              CAN_F12R2_FB10_Msk                                             /*!<Filter bit 10 */
#define CAN_F12R2_FB11_Pos                                          (11U)
#define CAN_F12R2_FB11_Msk                                          (0x1UL << CAN_F12R2_FB11_Pos)                                  /*!< 0x00000800 */
#define CAN_F12R2_FB11                                              CAN_F12R2_FB11_Msk                                             /*!<Filter bit 11 */
#define CAN_F12R2_FB12_Pos                                          (12U)
#define CAN_F12R2_FB12_Msk                                          (0x1UL << CAN_F12R2_FB12_Pos)                                  /*!< 0x00001000 */
#define CAN_F12R2_FB12                                              CAN_F12R2_FB12_Msk                                             /*!<Filter bit 12 */
#define CAN_F12R2_FB13_Pos                                          (13U)
#define CAN_F12R2_FB13_Msk                                          (0x1UL << CAN_F12R2_FB13_Pos)                                  /*!< 0x00002000 */
#define CAN_F12R2_FB13                                              CAN_F12R2_FB13_Msk                                             /*!<Filter bit 13 */
#define CAN_F12R2_FB14_Pos                                          (14U)
#define CAN_F12R2_FB14_Msk                                          (0x1UL << CAN_F12R2_FB14_Pos)                                  /*!< 0x00004000 */
#define CAN_F12R2_FB14                                              CAN_F12R2_FB14_Msk                                             /*!<Filter bit 14 */
#define CAN_F12R2_FB15_Pos                                          (15U)
#define CAN_F12R2_FB15_Msk                                          (0x1UL << CAN_F12R2_FB15_Pos)                                  /*!< 0x00008000 */
#define CAN_F12R2_FB15                                              CAN_F12R2_FB15_Msk                                             /*!<Filter bit 15 */
#define CAN_F12R2_FB16_Pos                                          (16U)
#define CAN_F12R2_FB16_Msk                                          (0x1UL << CAN_F12R2_FB16_Pos)                                  /*!< 0x00010000 */
#define CAN_F12R2_FB16                                              CAN_F12R2_FB16_Msk                                             /*!<Filter bit 16 */
#define CAN_F12R2_FB17_Pos                                          (17U)
#define CAN_F12R2_FB17_Msk                                          (0x1UL << CAN_F12R2_FB17_Pos)                                  /*!< 0x00020000 */
#define CAN_F12R2_FB17                                              CAN_F12R2_FB17_Msk                                             /*!<Filter bit 17 */
#define CAN_F12R2_FB18_Pos                                          (18U)
#define CAN_F12R2_FB18_Msk                                          (0x1UL << CAN_F12R2_FB18_Pos)                                  /*!< 0x00040000 */
#define CAN_F12R2_FB18                                              CAN_F12R2_FB18_Msk                                             /*!<Filter bit 18 */
#define CAN_F12R2_FB19_Pos                                          (19U)
#define CAN_F12R2_FB19_Msk                                          (0x1UL << CAN_F12R2_FB19_Pos)                                  /*!< 0x00080000 */
#define CAN_F12R2_FB19                                              CAN_F12R2_FB19_Msk                                             /*!<Filter bit 19 */
#define CAN_F12R2_FB20_Pos                                          (20U)
#define CAN_F12R2_FB20_Msk                                          (0x1UL << CAN_F12R2_FB20_Pos)                                  /*!< 0x00100000 */
#define CAN_F12R2_FB20                                              CAN_F12R2_FB20_Msk                                             /*!<Filter bit 20 */
#define CAN_F12R2_FB21_Pos                                          (21U)
#define CAN_F12R2_FB21_Msk                                          (0x1UL << CAN_F12R2_FB21_Pos)                                  /*!< 0x00200000 */
#define CAN_F12R2_FB21                                              CAN_F12R2_FB21_Msk                                             /*!<Filter bit 21 */
#define CAN_F12R2_FB22_Pos                                          (22U)
#define CAN_F12R2_FB22_Msk                                          (0x1UL << CAN_F12R2_FB22_Pos)                                  /*!< 0x00400000 */
#define CAN_F12R2_FB22                                              CAN_F12R2_FB22_Msk                                             /*!<Filter bit 22 */
#define CAN_F12R2_FB23_Pos                                          (23U)
#define CAN_F12R2_FB23_Msk                                          (0x1UL << CAN_F12R2_FB23_Pos)                                  /*!< 0x00800000 */
#define CAN_F12R2_FB23                                              CAN_F12R2_FB23_Msk                                             /*!<Filter bit 23 */
#define CAN_F12R2_FB24_Pos                                          (24U)
#define CAN_F12R2_FB24_Msk                                          (0x1UL << CAN_F12R2_FB24_Pos)                                  /*!< 0x01000000 */
#define CAN_F12R2_FB24                                              CAN_F12R2_FB24_Msk                                             /*!<Filter bit 24 */
#define CAN_F12R2_FB25_Pos                                          (25U)
#define CAN_F12R2_FB25_Msk                                          (0x1UL << CAN_F12R2_FB25_Pos)                                  /*!< 0x02000000 */
#define CAN_F12R2_FB25                                              CAN_F12R2_FB25_Msk                                             /*!<Filter bit 25 */
#define CAN_F12R2_FB26_Pos                                          (26U)
#define CAN_F12R2_FB26_Msk                                          (0x1UL << CAN_F12R2_FB26_Pos)                                  /*!< 0x04000000 */
#define CAN_F12R2_FB26                                              CAN_F12R2_FB26_Msk                                             /*!<Filter bit 26 */
#define CAN_F12R2_FB27_Pos                                          (27U)
#define CAN_F12R2_FB27_Msk                                          (0x1UL << CAN_F12R2_FB27_Pos)                                  /*!< 0x08000000 */
#define CAN_F12R2_FB27                                              CAN_F12R2_FB27_Msk                                             /*!<Filter bit 27 */
#define CAN_F12R2_FB28_Pos                                          (28U)
#define CAN_F12R2_FB28_Msk                                          (0x1UL << CAN_F12R2_FB28_Pos)                                  /*!< 0x10000000 */
#define CAN_F12R2_FB28                                              CAN_F12R2_FB28_Msk                                             /*!<Filter bit 28 */
#define CAN_F12R2_FB29_Pos                                          (29U)
#define CAN_F12R2_FB29_Msk                                          (0x1UL << CAN_F12R2_FB29_Pos)                                  /*!< 0x20000000 */
#define CAN_F12R2_FB29                                              CAN_F12R2_FB29_Msk                                             /*!<Filter bit 29 */
#define CAN_F12R2_FB30_Pos                                          (30U)
#define CAN_F12R2_FB30_Msk                                          (0x1UL << CAN_F12R2_FB30_Pos)                                  /*!< 0x40000000 */
#define CAN_F12R2_FB30                                              CAN_F12R2_FB30_Msk                                             /*!<Filter bit 30 */
#define CAN_F12R2_FB31_Pos                                          (31U)
#define CAN_F12R2_FB31_Msk                                          (0x1UL << CAN_F12R2_FB31_Pos)                                  /*!< 0x80000000 */
#define CAN_F12R2_FB31                                              CAN_F12R2_FB31_Msk                                             /*!<Filter bit 31 */

/*******************  Bit definition for CAN_F13R2 register  ******************/
#define CAN_F13R2_FB0_Pos                                           (0U)
#define CAN_F13R2_FB0_Msk                                           (0x1UL << CAN_F13R2_FB0_Pos)                                   /*!< 0x00000001 */
#define CAN_F13R2_FB0                                               CAN_F13R2_FB0_Msk                                              /*!<Filter bit 0 */
#define CAN_F13R2_FB1_Pos                                           (1U)
#define CAN_F13R2_FB1_Msk                                           (0x1UL << CAN_F13R2_FB1_Pos)                                   /*!< 0x00000002 */
#define CAN_F13R2_FB1                                               CAN_F13R2_FB1_Msk                                              /*!<Filter bit 1 */
#define CAN_F13R2_FB2_Pos                                           (2U)
#define CAN_F13R2_FB2_Msk                                           (0x1UL << CAN_F13R2_FB2_Pos)                                   /*!< 0x00000004 */
#define CAN_F13R2_FB2                                               CAN_F13R2_FB2_Msk                                              /*!<Filter bit 2 */
#define CAN_F13R2_FB3_Pos                                           (3U)
#define CAN_F13R2_FB3_Msk                                           (0x1UL << CAN_F13R2_FB3_Pos)                                   /*!< 0x00000008 */
#define CAN_F13R2_FB3                                               CAN_F13R2_FB3_Msk                                              /*!<Filter bit 3 */
#define CAN_F13R2_FB4_Pos                                           (4U)
#define CAN_F13R2_FB4_Msk                                           (0x1UL << CAN_F13R2_FB4_Pos)                                   /*!< 0x00000010 */
#define CAN_F13R2_FB4                                               CAN_F13R2_FB4_Msk                                              /*!<Filter bit 4 */
#define CAN_F13R2_FB5_Pos                                           (5U)
#define CAN_F13R2_FB5_Msk                                           (0x1UL << CAN_F13R2_FB5_Pos)                                   /*!< 0x00000020 */
#define CAN_F13R2_FB5                                               CAN_F13R2_FB5_Msk                                              /*!<Filter bit 5 */
#define CAN_F13R2_FB6_Pos                                           (6U)
#define CAN_F13R2_FB6_Msk                                           (0x1UL << CAN_F13R2_FB6_Pos)                                   /*!< 0x00000040 */
#define CAN_F13R2_FB6                                               CAN_F13R2_FB6_Msk                                              /*!<Filter bit 6 */
#define CAN_F13R2_FB7_Pos                                           (7U)
#define CAN_F13R2_FB7_Msk                                           (0x1UL << CAN_F13R2_FB7_Pos)                                   /*!< 0x00000080 */
#define CAN_F13R2_FB7                                               CAN_F13R2_FB7_Msk                                              /*!<Filter bit 7 */
#define CAN_F13R2_FB8_Pos                                           (8U)
#define CAN_F13R2_FB8_Msk                                           (0x1UL << CAN_F13R2_FB8_Pos)                                   /*!< 0x00000100 */
#define CAN_F13R2_FB8                                               CAN_F13R2_FB8_Msk                                              /*!<Filter bit 8 */
#define CAN_F13R2_FB9_Pos                                           (9U)
#define CAN_F13R2_FB9_Msk                                           (0x1UL << CAN_F13R2_FB9_Pos)                                   /*!< 0x00000200 */
#define CAN_F13R2_FB9                                               CAN_F13R2_FB9_Msk                                              /*!<Filter bit 9 */
#define CAN_F13R2_FB10_Pos                                          (10U)
#define CAN_F13R2_FB10_Msk                                          (0x1UL << CAN_F13R2_FB10_Pos)                                  /*!< 0x00000400 */
#define CAN_F13R2_FB10                                              CAN_F13R2_FB10_Msk                                             /*!<Filter bit 10 */
#define CAN_F13R2_FB11_Pos                                          (11U)
#define CAN_F13R2_FB11_Msk                                          (0x1UL << CAN_F13R2_FB11_Pos)                                  /*!< 0x00000800 */
#define CAN_F13R2_FB11                                              CAN_F13R2_FB11_Msk                                             /*!<Filter bit 11 */
#define CAN_F13R2_FB12_Pos                                          (12U)
#define CAN_F13R2_FB12_Msk                                          (0x1UL << CAN_F13R2_FB12_Pos)                                  /*!< 0x00001000 */
#define CAN_F13R2_FB12                                              CAN_F13R2_FB12_Msk                                             /*!<Filter bit 12 */
#define CAN_F13R2_FB13_Pos                                          (13U)
#define CAN_F13R2_FB13_Msk                                          (0x1UL << CAN_F13R2_FB13_Pos)                                  /*!< 0x00002000 */
#define CAN_F13R2_FB13                                              CAN_F13R2_FB13_Msk                                             /*!<Filter bit 13 */
#define CAN_F13R2_FB14_Pos                                          (14U)
#define CAN_F13R2_FB14_Msk                                          (0x1UL << CAN_F13R2_FB14_Pos)                                  /*!< 0x00004000 */
#define CAN_F13R2_FB14                                              CAN_F13R2_FB14_Msk                                             /*!<Filter bit 14 */
#define CAN_F13R2_FB15_Pos                                          (15U)
#define CAN_F13R2_FB15_Msk                                          (0x1UL << CAN_F13R2_FB15_Pos)                                  /*!< 0x00008000 */
#define CAN_F13R2_FB15                                              CAN_F13R2_FB15_Msk                                             /*!<Filter bit 15 */
#define CAN_F13R2_FB16_Pos                                          (16U)
#define CAN_F13R2_FB16_Msk                                          (0x1UL << CAN_F13R2_FB16_Pos)                                  /*!< 0x00010000 */
#define CAN_F13R2_FB16                                              CAN_F13R2_FB16_Msk                                             /*!<Filter bit 16 */
#define CAN_F13R2_FB17_Pos                                          (17U)
#define CAN_F13R2_FB17_Msk                                          (0x1UL << CAN_F13R2_FB17_Pos)                                  /*!< 0x00020000 */
#define CAN_F13R2_FB17                                              CAN_F13R2_FB17_Msk                                             /*!<Filter bit 17 */
#define CAN_F13R2_FB18_Pos                                          (18U)
#define CAN_F13R2_FB18_Msk                                          (0x1UL << CAN_F13R2_FB18_Pos)                                  /*!< 0x00040000 */
#define CAN_F13R2_FB18                                              CAN_F13R2_FB18_Msk                                             /*!<Filter bit 18 */
#define CAN_F13R2_FB19_Pos                                          (19U)
#define CAN_F13R2_FB19_Msk                                          (0x1UL << CAN_F13R2_FB19_Pos)                                  /*!< 0x00080000 */
#define CAN_F13R2_FB19                                              CAN_F13R2_FB19_Msk                                             /*!<Filter bit 19 */
#define CAN_F13R2_FB20_Pos                                          (20U)
#define CAN_F13R2_FB20_Msk                                          (0x1UL << CAN_F13R2_FB20_Pos)                                  /*!< 0x00100000 */
#define CAN_F13R2_FB20                                              CAN_F13R2_FB20_Msk                                             /*!<Filter bit 20 */
#define CAN_F13R2_FB21_Pos                                          (21U)
#define CAN_F13R2_FB21_Msk                                          (0x1UL << CAN_F13R2_FB21_Pos)                                  /*!< 0x00200000 */
#define CAN_F13R2_FB21                                              CAN_F13R2_FB21_Msk                                             /*!<Filter bit 21 */
#define CAN_F13R2_FB22_Pos                                          (22U)
#define CAN_F13R2_FB22_Msk                                          (0x1UL << CAN_F13R2_FB22_Pos)                                  /*!< 0x00400000 */
#define CAN_F13R2_FB22                                              CAN_F13R2_FB22_Msk                                             /*!<Filter bit 22 */
#define CAN_F13R2_FB23_Pos                                          (23U)
#define CAN_F13R2_FB23_Msk                                          (0x1UL << CAN_F13R2_FB23_Pos)                                  /*!< 0x00800000 */
#define CAN_F13R2_FB23                                              CAN_F13R2_FB23_Msk                                             /*!<Filter bit 23 */
#define CAN_F13R2_FB24_Pos                                          (24U)
#define CAN_F13R2_FB24_Msk                                          (0x1UL << CAN_F13R2_FB24_Pos)                                  /*!< 0x01000000 */
#define CAN_F13R2_FB24                                              CAN_F13R2_FB24_Msk                                             /*!<Filter bit 24 */
#define CAN_F13R2_FB25_Pos                                          (25U)
#define CAN_F13R2_FB25_Msk                                          (0x1UL << CAN_F13R2_FB25_Pos)                                  /*!< 0x02000000 */
#define CAN_F13R2_FB25                                              CAN_F13R2_FB25_Msk                                             /*!<Filter bit 25 */
#define CAN_F13R2_FB26_Pos                                          (26U)
#define CAN_F13R2_FB26_Msk                                          (0x1UL << CAN_F13R2_FB26_Pos)                                  /*!< 0x04000000 */
#define CAN_F13R2_FB26                                              CAN_F13R2_FB26_Msk                                             /*!<Filter bit 26 */
#define CAN_F13R2_FB27_Pos                                          (27U)
#define CAN_F13R2_FB27_Msk                                          (0x1UL << CAN_F13R2_FB27_Pos)                                  /*!< 0x08000000 */
#define CAN_F13R2_FB27                                              CAN_F13R2_FB27_Msk                                             /*!<Filter bit 27 */
#define CAN_F13R2_FB28_Pos                                          (28U)
#define CAN_F13R2_FB28_Msk                                          (0x1UL << CAN_F13R2_FB28_Pos)                                  /*!< 0x10000000 */
#define CAN_F13R2_FB28                                              CAN_F13R2_FB28_Msk                                             /*!<Filter bit 28 */
#define CAN_F13R2_FB29_Pos                                          (29U)
#define CAN_F13R2_FB29_Msk                                          (0x1UL << CAN_F13R2_FB29_Pos)                                  /*!< 0x20000000 */
#define CAN_F13R2_FB29                                              CAN_F13R2_FB29_Msk                                             /*!<Filter bit 29 */
#define CAN_F13R2_FB30_Pos                                          (30U)
#define CAN_F13R2_FB30_Msk                                          (0x1UL << CAN_F13R2_FB30_Pos)                                  /*!< 0x40000000 */
#define CAN_F13R2_FB30                                              CAN_F13R2_FB30_Msk                                             /*!<Filter bit 30 */
#define CAN_F13R2_FB31_Pos                                          (31U)
#define CAN_F13R2_FB31_Msk                                          (0x1UL << CAN_F13R2_FB31_Pos)                                  /*!< 0x80000000 */
#define CAN_F13R2_FB31                                              CAN_F13R2_FB31_Msk                                             /*!<Filter bit 31 */

/******************************************************************************/
/*                                                                            */
/*                          CRC calculation unit                              */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for CRC_DATA register  *********************/
#define CRC_DATA_DATA_Pos                                           (0U)
#define CRC_DATA_DATA_Msk                                           (0xFFFFFFFFUL << CRC_DATA_DATA_Pos)                            /*!< 0xFFFFFFFF */
#define CRC_DATA_DATA                                               CRC_DATA_DATA_Msk                                              /*!< Data register bits */


/*******************  Bit definition for CRC_INDATA register  ********************/
#define CRC_INDATA_INDATA_Pos                                       (0U)
#define CRC_INDATA_INDATA_Msk                                       (0xFFUL << CRC_INDATA_INDATA_Pos)                              /*!< 0x000000FF */
#define CRC_INDATA_INDATA                                           CRC_INDATA_INDATA_Msk                                          /*!< General-purpose 8-bit data register bits */


/********************  Bit definition for CRC_CTRL register  ********************/
#define CRC_CTRL_RST_Pos                                            (0U)
#define CRC_CTRL_RST_Msk                                            (0x1UL << CRC_CTRL_RST_Pos)                                    /*!< 0x00000001 */
#define CRC_CTRL_RST                                                CRC_CTRL_RST_Msk                                               /*!< RESET bit */

/******************************************************************************/
/*                                                                            */
/*                      Digital to Analog Converter                           */
/*                                                                            */
/******************************************************************************/
/*
 * @brief Specific device feature definitions (not present on all devices in the APM32F4 serie)
 */
#define DAC_CHANNEL2_SUPPORT                                                                                                       /*!< DAC feature available only on specific devices: availability of DAC channel 2 */
/********************  Bit definition for DAC_CTRL register  ********************/
#define DAC_CTRL_ENCH1_Pos                                          (0U)
#define DAC_CTRL_ENCH1_Msk                                          (0x1UL << DAC_CTRL_ENCH1_Pos)                                  /*!< 0x00000001 */
#define DAC_CTRL_ENCH1                                              DAC_CTRL_ENCH1_Msk                                             /*!<DAC channel1 enable */
#define DAC_CTRL_BUFFDCH1_Pos                                       (1U)
#define DAC_CTRL_BUFFDCH1_Msk                                       (0x1UL << DAC_CTRL_BUFFDCH1_Pos)                               /*!< 0x00000002 */
#define DAC_CTRL_BUFFDCH1                                           DAC_CTRL_BUFFDCH1_Msk                                          /*!<DAC channel1 output buffer disable */
#define DAC_CTRL_TRGENCH1_Pos                                       (2U)
#define DAC_CTRL_TRGENCH1_Msk                                       (0x1UL << DAC_CTRL_TRGENCH1_Pos)                               /*!< 0x00000004 */
#define DAC_CTRL_TRGENCH1                                           DAC_CTRL_TRGENCH1_Msk                                          /*!<DAC channel1 Trigger enable */

#define DAC_CTRL_TRGSELCH1_Pos                                      (3U)
#define DAC_CTRL_TRGSELCH1_Msk                                      (0x7UL << DAC_CTRL_TRGSELCH1_Pos)                              /*!< 0x00000038 */
#define DAC_CTRL_TRGSELCH1                                          DAC_CTRL_TRGSELCH1_Msk                                         /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
#define DAC_CTRL_TRGSELCH1_0                                        (0x1UL << DAC_CTRL_TRGSELCH1_Pos)                              /*!< 0x00000008 */
#define DAC_CTRL_TRGSELCH1_1                                        (0x2UL << DAC_CTRL_TRGSELCH1_Pos)                              /*!< 0x00000010 */
#define DAC_CTRL_TRGSELCH1_2                                        (0x4UL << DAC_CTRL_TRGSELCH1_Pos)                              /*!< 0x00000020 */

#define DAC_CTRL_WAVENCH1_Pos                                       (6U)
#define DAC_CTRL_WAVENCH1_Msk                                       (0x3UL << DAC_CTRL_WAVENCH1_Pos)                               /*!< 0x000000C0 */
#define DAC_CTRL_WAVENCH1                                           DAC_CTRL_WAVENCH1_Msk                                          /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
#define DAC_CTRL_WAVENCH1_0                                         (0x1UL << DAC_CTRL_WAVENCH1_Pos)                               /*!< 0x00000040 */
#define DAC_CTRL_WAVENCH1_1                                         (0x2UL << DAC_CTRL_WAVENCH1_Pos)                               /*!< 0x00000080 */

#define DAC_CTRL_MAMPSELCH1_Pos                                     (8U)
#define DAC_CTRL_MAMPSELCH1_Msk                                     (0xFUL << DAC_CTRL_MAMPSELCH1_Pos)                             /*!< 0x00000F00 */
#define DAC_CTRL_MAMPSELCH1                                         DAC_CTRL_MAMPSELCH1_Msk                                        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
#define DAC_CTRL_MAMPSELCH1_0                                       (0x1UL << DAC_CTRL_MAMPSELCH1_Pos)                             /*!< 0x00000100 */
#define DAC_CTRL_MAMPSELCH1_1                                       (0x2UL << DAC_CTRL_MAMPSELCH1_Pos)                             /*!< 0x00000200 */
#define DAC_CTRL_MAMPSELCH1_2                                       (0x4UL << DAC_CTRL_MAMPSELCH1_Pos)                             /*!< 0x00000400 */
#define DAC_CTRL_MAMPSELCH1_3                                       (0x8UL << DAC_CTRL_MAMPSELCH1_Pos)                             /*!< 0x00000800 */

#define DAC_CTRL_DMAENCH1_Pos                                       (12U)
#define DAC_CTRL_DMAENCH1_Msk                                       (0x1UL << DAC_CTRL_DMAENCH1_Pos)                               /*!< 0x00001000 */
#define DAC_CTRL_DMAENCH1                                           DAC_CTRL_DMAENCH1_Msk                                          /*!<DAC channel1 DMA enable */
#define DAC_CTRL_DMAUDIEN1_Pos                                      (13U)
#define DAC_CTRL_DMAUDIEN1_Msk                                      (0x1UL << DAC_CTRL_DMAUDIEN1_Pos)                              /*!< 0x00002000 */
#define DAC_CTRL_DMAUDIEN1                                          DAC_CTRL_DMAUDIEN1_Msk                                         /*!<DAC channel1 DMA underrun interrupt enable*/
#define DAC_CTRL_ENCH2_Pos                                          (16U)
#define DAC_CTRL_ENCH2_Msk                                          (0x1UL << DAC_CTRL_ENCH2_Pos)                                  /*!< 0x00010000 */
#define DAC_CTRL_ENCH2                                              DAC_CTRL_ENCH2_Msk                                             /*!<DAC channel2 enable */
#define DAC_CTRL_BUFFDCH2_Pos                                       (17U)
#define DAC_CTRL_BUFFDCH2_Msk                                       (0x1UL << DAC_CTRL_BUFFDCH2_Pos)                               /*!< 0x00020000 */
#define DAC_CTRL_BUFFDCH2                                           DAC_CTRL_BUFFDCH2_Msk                                          /*!<DAC channel2 output buffer disable */
#define DAC_CTRL_TRGENCH2_Pos                                       (18U)
#define DAC_CTRL_TRGENCH2_Msk                                       (0x1UL << DAC_CTRL_TRGENCH2_Pos)                               /*!< 0x00040000 */
#define DAC_CTRL_TRGENCH2                                           DAC_CTRL_TRGENCH2_Msk                                          /*!<DAC channel2 Trigger enable */

#define DAC_CTRL_TRGSELCH2_Pos                                      (19U)
#define DAC_CTRL_TRGSELCH2_Msk                                      (0x7UL << DAC_CTRL_TRGSELCH2_Pos)                              /*!< 0x00380000 */
#define DAC_CTRL_TRGSELCH2                                          DAC_CTRL_TRGSELCH2_Msk                                         /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
#define DAC_CTRL_TRGSELCH2_0                                        (0x1UL << DAC_CTRL_TRGSELCH2_Pos)                              /*!< 0x00080000 */
#define DAC_CTRL_TRGSELCH2_1                                        (0x2UL << DAC_CTRL_TRGSELCH2_Pos)                              /*!< 0x00100000 */
#define DAC_CTRL_TRGSELCH2_2                                        (0x4UL << DAC_CTRL_TRGSELCH2_Pos)                              /*!< 0x00200000 */

#define DAC_CTRL_WAVENCH2_Pos                                       (22U)
#define DAC_CTRL_WAVENCH2_Msk                                       (0x3UL << DAC_CTRL_WAVENCH2_Pos)                               /*!< 0x00C00000 */
#define DAC_CTRL_WAVENCH2                                           DAC_CTRL_WAVENCH2_Msk                                          /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
#define DAC_CTRL_WAVENCH2_0                                         (0x1UL << DAC_CTRL_WAVENCH2_Pos)                               /*!< 0x00400000 */
#define DAC_CTRL_WAVENCH2_1                                         (0x2UL << DAC_CTRL_WAVENCH2_Pos)                               /*!< 0x00800000 */

#define DAC_CTRL_MAMPSELCH2_Pos                                     (24U)
#define DAC_CTRL_MAMPSELCH2_Msk                                     (0xFUL << DAC_CTRL_MAMPSELCH2_Pos)                             /*!< 0x0F000000 */
#define DAC_CTRL_MAMPSELCH2                                         DAC_CTRL_MAMPSELCH2_Msk                                        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
#define DAC_CTRL_MAMPSELCH2_0                                       (0x1UL << DAC_CTRL_MAMPSELCH2_Pos)                             /*!< 0x01000000 */
#define DAC_CTRL_MAMPSELCH2_1                                       (0x2UL << DAC_CTRL_MAMPSELCH2_Pos)                             /*!< 0x02000000 */
#define DAC_CTRL_MAMPSELCH2_2                                       (0x4UL << DAC_CTRL_MAMPSELCH2_Pos)                             /*!< 0x04000000 */
#define DAC_CTRL_MAMPSELCH2_3                                       (0x8UL << DAC_CTRL_MAMPSELCH2_Pos)                             /*!< 0x08000000 */

#define DAC_CTRL_DMAENCH2_Pos                                       (28U)
#define DAC_CTRL_DMAENCH2_Msk                                       (0x1UL << DAC_CTRL_DMAENCH2_Pos)                               /*!< 0x10000000 */
#define DAC_CTRL_DMAENCH2                                           DAC_CTRL_DMAENCH2_Msk                                          /*!<DAC channel2 DMA enabled */
#define DAC_CTRL_DMAUDIEN2_Pos                                      (29U)
#define DAC_CTRL_DMAUDIEN2_Msk                                      (0x1UL << DAC_CTRL_DMAUDIEN2_Pos)                              /*!< 0x20000000 */
#define DAC_CTRL_DMAUDIEN2                                          DAC_CTRL_DMAUDIEN2_Msk                                         /*!<DAC channel2 DMA underrun interrupt enable*/

/*****************  Bit definition for DAC_SWTRG register  ******************/
#define DAC_SWTRG_SWTRG1_Pos                                        (0U)
#define DAC_SWTRG_SWTRG1_Msk                                        (0x1UL << DAC_SWTRG_SWTRG1_Pos)                                /*!< 0x00000001 */
#define DAC_SWTRG_SWTRG1                                            DAC_SWTRG_SWTRG1_Msk                                           /*!<DAC channel1 software trigger */
#define DAC_SWTRG_SWTRG2_Pos                                        (1U)
#define DAC_SWTRG_SWTRG2_Msk                                        (0x1UL << DAC_SWTRG_SWTRG2_Pos)                                /*!< 0x00000002 */
#define DAC_SWTRG_SWTRG2                                            DAC_SWTRG_SWTRG2_Msk                                           /*!<DAC channel2 software trigger */

/*****************  Bit definition for DAC_DH12R1 register  ******************/
#define DAC_DH12R1_DATA_Pos                                         (0U)
#define DAC_DH12R1_DATA_Msk                                         (0xFFFUL << DAC_DH12R1_DATA_Pos)                               /*!< 0x00000FFF */
#define DAC_DH12R1_DATA                                             DAC_DH12R1_DATA_Msk                                            /*!<DAC channel1 12-bit Right aligned data */

/*****************  Bit definition for DAC_DH12L1 register  ******************/
#define DAC_DH12L1_DATA_Pos                                         (4U)
#define DAC_DH12L1_DATA_Msk                                         (0xFFFUL << DAC_DH12L1_DATA_Pos)                               /*!< 0x0000FFF0 */
#define DAC_DH12L1_DATA                                             DAC_DH12L1_DATA_Msk                                            /*!<DAC channel1 12-bit Left aligned data */

/******************  Bit definition for DAC_DH8R1 register  ******************/
#define DAC_DH8R1_DATA_Pos                                          (0U)
#define DAC_DH8R1_DATA_Msk                                          (0xFFUL << DAC_DH8R1_DATA_Pos)                                 /*!< 0x000000FF */
#define DAC_DH8R1_DATA                                              DAC_DH8R1_DATA_Msk                                             /*!<DAC channel1 8-bit Right aligned data */

/*****************  Bit definition for DAC_DH12R2 register  ******************/
#define DAC_DH12R2_DATA_Pos                                         (0U)
#define DAC_DH12R2_DATA_Msk                                         (0xFFFUL << DAC_DH12R2_DATA_Pos)                               /*!< 0x00000FFF */
#define DAC_DH12R2_DATA                                             DAC_DH12R2_DATA_Msk                                            /*!<DAC channel2 12-bit Right aligned data */

/*****************  Bit definition for DAC_DH12L2 register  ******************/
#define DAC_DH12L2_DATA_Pos                                         (4U)
#define DAC_DH12L2_DATA_Msk                                         (0xFFFUL << DAC_DH12L2_DATA_Pos)                               /*!< 0x0000FFF0 */
#define DAC_DH12L2_DATA                                             DAC_DH12L2_DATA_Msk                                            /*!<DAC channel2 12-bit Left aligned data */

/******************  Bit definition for DAC_DH8R2 register  ******************/
#define DAC_DH8R2_DATA_Pos                                          (0U)
#define DAC_DH8R2_DATA_Msk                                          (0xFFUL << DAC_DH8R2_DATA_Pos)                                 /*!< 0x000000FF */
#define DAC_DH8R2_DATA                                              DAC_DH8R2_DATA_Msk                                             /*!<DAC channel2 8-bit Right aligned data */

/*****************  Bit definition for DAC_DH12RDUAL register  ******************/
#define DAC_DH12RDUAL_DATACH1_Pos                                   (0U)
#define DAC_DH12RDUAL_DATACH1_Msk                                   (0xFFFUL << DAC_DH12RDUAL_DATACH1_Pos)                         /*!< 0x00000FFF */
#define DAC_DH12RDUAL_DATACH1                                       DAC_DH12RDUAL_DATACH1_Msk                                      /*!<DAC channel1 12-bit Right aligned data */
#define DAC_DH12RDUAL_DATACH2_Pos                                   (16U)
#define DAC_DH12RDUAL_DATACH2_Msk                                   (0xFFFUL << DAC_DH12RDUAL_DATACH2_Pos)                         /*!< 0x0FFF0000 */
#define DAC_DH12RDUAL_DATACH2                                       DAC_DH12RDUAL_DATACH2_Msk                                      /*!<DAC channel2 12-bit Right aligned data */

/*****************  Bit definition for DAC_DH12LDUAL register  ******************/
#define DAC_DH12LDUAL_DATACH1_Pos                                   (4U)
#define DAC_DH12LDUAL_DATACH1_Msk                                   (0xFFFUL << DAC_DH12LDUAL_DATACH1_Pos)                         /*!< 0x0000FFF0 */
#define DAC_DH12LDUAL_DATACH1                                       DAC_DH12LDUAL_DATACH1_Msk                                      /*!<DAC channel1 12-bit Left aligned data */
#define DAC_DH12LDUAL_DATACH2_Pos                                   (20U)
#define DAC_DH12LDUAL_DATACH2_Msk                                   (0xFFFUL << DAC_DH12LDUAL_DATACH2_Pos)                         /*!< 0xFFF00000 */
#define DAC_DH12LDUAL_DATACH2                                       DAC_DH12LDUAL_DATACH2_Msk                                      /*!<DAC channel2 12-bit Left aligned data */

/******************  Bit definition for DAC_DH8RDUAL register  ******************/
#define DAC_DH8RDUAL_DATACH1_Pos                                    (0U)
#define DAC_DH8RDUAL_DATACH1_Msk                                    (0xFFUL << DAC_DH8RDUAL_DATACH1_Pos)                           /*!< 0x000000FF */
#define DAC_DH8RDUAL_DATACH1                                        DAC_DH8RDUAL_DATACH1_Msk                                       /*!<DAC channel1 8-bit Right aligned data */
#define DAC_DH8RDUAL_DATACH2_Pos                                    (8U)
#define DAC_DH8RDUAL_DATACH2_Msk                                    (0xFFUL << DAC_DH8RDUAL_DATACH2_Pos)                           /*!< 0x0000FF00 */
#define DAC_DH8RDUAL_DATACH2                                        DAC_DH8RDUAL_DATACH2_Msk                                       /*!<DAC channel2 8-bit Right aligned data */

/*******************  Bit definition for DAC_DATAOCH1 register  *******************/
#define DAC_DATAOCH1_DATA_Pos                                       (0U)
#define DAC_DATAOCH1_DATA_Msk                                       (0xFFFUL << DAC_DATAOCH1_DATA_Pos)                             /*!< 0x00000FFF */
#define DAC_DATAOCH1_DATA                                           DAC_DATAOCH1_DATA_Msk                                          /*!<DAC channel1 data output */

/*******************  Bit definition for DAC_DATAOCH2 register  *******************/
#define DAC_DATAOCH2_DATA_Pos                                       (0U)
#define DAC_DATAOCH2_DATA_Msk                                       (0xFFFUL << DAC_DATAOCH2_DATA_Pos)                             /*!< 0x00000FFF */
#define DAC_DATAOCH2_DATA                                           DAC_DATAOCH2_DATA_Msk                                          /*!<DAC channel2 data output */

/********************  Bit definition for DAC_STS register  ********************/
#define DAC_STS_DMAUDFLG1_Pos                                       (13U)
#define DAC_STS_DMAUDFLG1_Msk                                       (0x1UL << DAC_STS_DMAUDFLG1_Pos)                               /*!< 0x00002000 */
#define DAC_STS_DMAUDFLG1                                           DAC_STS_DMAUDFLG1_Msk                                          /*!<DAC channel1 DMA underrun flag */
#define DAC_STS_DMAUDFLG2_Pos                                       (29U)
#define DAC_STS_DMAUDFLG2_Msk                                       (0x1UL << DAC_STS_DMAUDFLG2_Pos)                               /*!< 0x20000000 */
#define DAC_STS_DMAUDFLG2                                           DAC_STS_DMAUDFLG2_Msk                                          /*!<DAC channel2 DMA underrun flag */

/******************************************************************************/
/*                                                                            */
/*                                    DCI                                    */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for DCI_CTRL register  ******************/
#define DCI_CTRL_CEN_Pos                                            (0U)
#define DCI_CTRL_CEN_Msk                                            (0x1UL << DCI_CTRL_CEN_Pos)                                    /*!< 0x00000001 */
#define DCI_CTRL_CEN                                                DCI_CTRL_CEN_Msk
#define DCI_CTRL_CMODE_Pos                                          (1U)
#define DCI_CTRL_CMODE_Msk                                          (0x1UL << DCI_CTRL_CMODE_Pos)                                  /*!< 0x00000002 */
#define DCI_CTRL_CMODE                                              DCI_CTRL_CMODE_Msk
#define DCI_CTRL_CROPF_Pos                                          (2U)
#define DCI_CTRL_CROPF_Msk                                          (0x1UL << DCI_CTRL_CROPF_Pos)                                  /*!< 0x00000004 */
#define DCI_CTRL_CROPF                                              DCI_CTRL_CROPF_Msk
#define DCI_CTRL_JPGFM_Pos                                          (3U)
#define DCI_CTRL_JPGFM_Msk                                          (0x1UL << DCI_CTRL_JPGFM_Pos)                                  /*!< 0x00000008 */
#define DCI_CTRL_JPGFM                                              DCI_CTRL_JPGFM_Msk
#define DCI_CTRL_ESYNCSEL_Pos                                       (4U)
#define DCI_CTRL_ESYNCSEL_Msk                                       (0x1UL << DCI_CTRL_ESYNCSEL_Pos)                               /*!< 0x00000010 */
#define DCI_CTRL_ESYNCSEL                                           DCI_CTRL_ESYNCSEL_Msk
#define DCI_CTRL_PXCLKPOL_Pos                                       (5U)
#define DCI_CTRL_PXCLKPOL_Msk                                       (0x1UL << DCI_CTRL_PXCLKPOL_Pos)                               /*!< 0x00000020 */
#define DCI_CTRL_PXCLKPOL                                           DCI_CTRL_PXCLKPOL_Msk
#define DCI_CTRL_HSYNCPOL_Pos                                       (6U)
#define DCI_CTRL_HSYNCPOL_Msk                                       (0x1UL << DCI_CTRL_HSYNCPOL_Pos)                               /*!< 0x00000040 */
#define DCI_CTRL_HSYNCPOL                                           DCI_CTRL_HSYNCPOL_Msk
#define DCI_CTRL_VSYNCPOL_Pos                                       (7U)
#define DCI_CTRL_VSYNCPOL_Msk                                       (0x1UL << DCI_CTRL_VSYNCPOL_Pos)                               /*!< 0x00000080 */
#define DCI_CTRL_VSYNCPOL                                           DCI_CTRL_VSYNCPOL_Msk
#define DCI_CTRL_FCRCFG_0                                           0x00000100U
#define DCI_CTRL_FCRCFG_1                                           0x00000200U
#define DCI_CTRL_EXDMOD_0                                           0x00000400U
#define DCI_CTRL_EXDMOD_1                                           0x00000800U
#define DCI_CTRL_DCIEN_Pos                                          (14U)
#define DCI_CTRL_DCIEN_Msk                                          (0x1UL << DCI_CTRL_DCIEN_Pos)                                  /*!< 0x00004000 */
#define DCI_CTRL_DCIEN                                              DCI_CTRL_DCIEN_Msk

/********************  Bits definition for DCI_STS register  ******************/
#define DCI_STS_HSYNCSTS_Pos                                        (0U)
#define DCI_STS_HSYNCSTS_Msk                                        (0x1UL << DCI_STS_HSYNCSTS_Pos)                                /*!< 0x00000001 */
#define DCI_STS_HSYNCSTS                                            DCI_STS_HSYNCSTS_Msk
#define DCI_STS_VSYNCSTS_Pos                                        (1U)
#define DCI_STS_VSYNCSTS_Msk                                        (0x1UL << DCI_STS_VSYNCSTS_Pos)                                /*!< 0x00000002 */
#define DCI_STS_VSYNCSTS                                            DCI_STS_VSYNCSTS_Msk
#define DCI_STS_FIFONEMP_Pos                                        (2U)
#define DCI_STS_FIFONEMP_Msk                                        (0x1UL << DCI_STS_FIFONEMP_Pos)                                /*!< 0x00000004 */
#define DCI_STS_FIFONEMP                                            DCI_STS_FIFONEMP_Msk

/********************  Bits definition for DCI_RIS register  *****************/
#define DCI_RIS_FRAME_RIS_Pos                                       (0U)
#define DCI_RIS_FRAME_RIS_Msk                                       (0x1UL << DCI_RIS_FRAME_RIS_Pos)                               /*!< 0x00000001 */
#define DCI_RIS_FRAME_RIS                                           DCI_RIS_FRAME_RIS_Msk
#define DCI_RIS_OVR_RIS_Pos                                         (1U)
#define DCI_RIS_OVR_RIS_Msk                                         (0x1UL << DCI_RIS_OVR_RIS_Pos)                                 /*!< 0x00000002 */
#define DCI_RIS_OVR_RIS                                             DCI_RIS_OVR_RIS_Msk
#define DCI_RIS_ERR_RIS_Pos                                         (2U)
#define DCI_RIS_ERR_RIS_Msk                                         (0x1UL << DCI_RIS_ERR_RIS_Pos)                                 /*!< 0x00000004 */
#define DCI_RIS_ERR_RIS                                             DCI_RIS_ERR_RIS_Msk
#define DCI_RIS_VSYNC_RIS_Pos                                       (3U)
#define DCI_RIS_VSYNC_RIS_Msk                                       (0x1UL << DCI_RIS_VSYNC_RIS_Pos)                               /*!< 0x00000008 */
#define DCI_RIS_VSYNC_RIS                                           DCI_RIS_VSYNC_RIS_Msk
#define DCI_RIS_LINE_RIS_Pos                                        (4U)
#define DCI_RIS_LINE_RIS_Msk                                        (0x1UL << DCI_RIS_LINE_RIS_Pos)                                /*!< 0x00000010 */
#define DCI_RIS_LINE_RIS                                            DCI_RIS_LINE_RIS_Msk
/* Legacy defines */
#define DCI_RINTSTS_CC_RINT_RIS                                     DCI_RIS_FRAME_RIS
#define DCI_RINTSTS_OVR_RINT_RIS                                    DCI_RIS_OVR_RIS
#define DCI_RINTSTS_SYNCERR_RINT_RIS                                DCI_RIS_ERR_RIS
#define DCI_RINTSTS_VSYNC_RINT_RIS                                  DCI_RIS_VSYNC_RIS
#define DCI_RINTSTS_LINE_RINT_RIS                                   DCI_RIS_LINE_RIS
#define DCI_RINTSTS_OVF_RINT_RIS                                    DCI_RIS_OVR_RIS

/********************  Bits definition for DCI_INTEN register  *****************/
#define DCI_INTEN_CCINTEN_Pos                                       (0U)
#define DCI_INTEN_CCINTEN_Msk                                       (0x1UL << DCI_INTEN_CCINTEN_Pos)                               /*!< 0x00000001 */
#define DCI_INTEN_CCINTEN                                           DCI_INTEN_CCINTEN_Msk
#define DCI_INTEN_OVRINTEN_Pos                                      (1U)
#define DCI_INTEN_OVRINTEN_Msk                                      (0x1UL << DCI_INTEN_OVRINTEN_Pos)                              /*!< 0x00000002 */
#define DCI_INTEN_OVRINTEN                                          DCI_INTEN_OVRINTEN_Msk
#define DCI_INTEN_SYNCERRINTEN_Pos                                  (2U)
#define DCI_INTEN_SYNCERRINTEN_Msk                                  (0x1UL << DCI_INTEN_SYNCERRINTEN_Pos)                          /*!< 0x00000004 */
#define DCI_INTEN_SYNCERRINTEN                                      DCI_INTEN_SYNCERRINTEN_Msk
#define DCI_INTEN_VSYNCINTEN_Pos                                    (3U)
#define DCI_INTEN_VSYNCINTEN_Msk                                    (0x1UL << DCI_INTEN_VSYNCINTEN_Pos)                            /*!< 0x00000008 */
#define DCI_INTEN_VSYNCINTEN                                        DCI_INTEN_VSYNCINTEN_Msk
#define DCI_INTEN_LINEINTEN_Pos                                     (4U)
#define DCI_INTEN_LINEINTEN_Msk                                     (0x1UL << DCI_INTEN_LINEINTEN_Pos)                             /*!< 0x00000010 */
#define DCI_INTEN_LINEINTEN                                         DCI_INTEN_LINEINTEN_Msk
/* Legacy defines */
#define DCI_INTEN_OVF_IE                                            DCI_INTEN_OVRINTEN

/********************  Bits definition for DCI_MIS register  *****************/
#define DCI_MIS_FRAME_MIS_Pos                                       (0U)
#define DCI_MIS_FRAME_MIS_Msk                                       (0x1UL << DCI_MIS_FRAME_MIS_Pos)                               /*!< 0x00000001 */
#define DCI_MIS_FRAME_MIS                                           DCI_MIS_FRAME_MIS_Msk
#define DCI_MIS_OVR_MIS_Pos                                         (1U)
#define DCI_MIS_OVR_MIS_Msk                                         (0x1UL << DCI_MIS_OVR_MIS_Pos)                                 /*!< 0x00000002 */
#define DCI_MIS_OVR_MIS                                             DCI_MIS_OVR_MIS_Msk
#define DCI_MIS_ERR_MIS_Pos                                         (2U)
#define DCI_MIS_ERR_MIS_Msk                                         (0x1UL << DCI_MIS_ERR_MIS_Pos)                                 /*!< 0x00000004 */
#define DCI_MIS_ERR_MIS                                             DCI_MIS_ERR_MIS_Msk
#define DCI_MIS_VSYNC_MIS_Pos                                       (3U)
#define DCI_MIS_VSYNC_MIS_Msk                                       (0x1UL << DCI_MIS_VSYNC_MIS_Pos)                               /*!< 0x00000008 */
#define DCI_MIS_VSYNC_MIS                                           DCI_MIS_VSYNC_MIS_Msk
#define DCI_MIS_LINE_MIS_Pos                                        (4U)
#define DCI_MIS_LINE_MIS_Msk                                        (0x1UL << DCI_MIS_LINE_MIS_Pos)                                /*!< 0x00000010 */
#define DCI_MIS_LINE_MIS                                            DCI_MIS_LINE_MIS_Msk

/* Legacy defines */
#define DCI_MINTSTS_CC_MINT_MIS                                     DCI_MIS_FRAME_MIS
#define DCI_MINTSTS_OVR_MINT_MIS                                    DCI_MIS_OVR_MIS
#define DCI_MINTSTS_SYNCERR_MINT_MIS                                DCI_MIS_ERR_MIS
#define DCI_MINTSTS_VSYNC_MINT_MIS                                  DCI_MIS_VSYNC_MIS
#define DCI_MINTSTS_LINE_MINT_MIS                                   DCI_MIS_LINE_MIS

/********************  Bits definition for DCI_INTCLR register  *****************/
#define DCI_INTCLR_CC_INTCLR_Pos                                    (0U)
#define DCI_INTCLR_CC_INTCLR_Msk                                    (0x1UL << DCI_INTCLR_CC_INTCLR_Pos)                            /*!< 0x00000001 */
#define DCI_INTCLR_CC_INTCLR                                        DCI_INTCLR_CC_INTCLR_Msk
#define DCI_INTCLR_OVR_INTCLR_Pos                                   (1U)
#define DCI_INTCLR_OVR_INTCLR_Msk                                   (0x1UL << DCI_INTCLR_OVR_INTCLR_Pos)                           /*!< 0x00000002 */
#define DCI_INTCLR_OVR_INTCLR                                       DCI_INTCLR_OVR_INTCLR_Msk
#define DCI_INTCLR_SYNCERR_INTCLR_Pos                               (2U)
#define DCI_INTCLR_SYNCERR_INTCLR_Msk                               (0x1UL << DCI_INTCLR_SYNCERR_INTCLR_Pos)                       /*!< 0x00000004 */
#define DCI_INTCLR_SYNCERR_INTCLR                                   DCI_INTCLR_SYNCERR_INTCLR_Msk
#define DCI_INTCLR_VSYNC_INTCLR_Pos                                 (3U)
#define DCI_INTCLR_VSYNC_INTCLR_Msk                                 (0x1UL << DCI_INTCLR_VSYNC_INTCLR_Pos)                         /*!< 0x00000008 */
#define DCI_INTCLR_VSYNC_INTCLR                                     DCI_INTCLR_VSYNC_INTCLR_Msk
#define DCI_INTCLR_LINE_INTCLR_Pos                                  (4U)
#define DCI_INTCLR_LINE_INTCLR_Msk                                  (0x1UL << DCI_INTCLR_LINE_INTCLR_Pos)                          /*!< 0x00000010 */
#define DCI_INTCLR_LINE_INTCLR                                      DCI_INTCLR_LINE_INTCLR_Msk

/* Legacy defines */
#define DCI_INTCLR_OVF_INTCLR                                       DCI_INTCLR_OVR_INTCLR

/********************  Bits definition for DCI_ESYNCC register  ******************/
#define DCI_ESYNCC_FSDC_Pos                                         (0U)
#define DCI_ESYNCC_FSDC_Msk                                         (0xFFUL << DCI_ESYNCC_FSDC_Pos)                                /*!< 0x000000FF */
#define DCI_ESYNCC_FSDC                                             DCI_ESYNCC_FSDC_Msk
#define DCI_ESYNCC_LSDC_Pos                                         (8U)
#define DCI_ESYNCC_LSDC_Msk                                         (0xFFUL << DCI_ESYNCC_LSDC_Pos)                                /*!< 0x0000FF00 */
#define DCI_ESYNCC_LSDC                                             DCI_ESYNCC_LSDC_Msk
#define DCI_ESYNCC_LEDC_Pos                                         (16U)
#define DCI_ESYNCC_LEDC_Msk                                         (0xFFUL << DCI_ESYNCC_LEDC_Pos)                                /*!< 0x00FF0000 */
#define DCI_ESYNCC_LEDC                                             DCI_ESYNCC_LEDC_Msk
#define DCI_ESYNCC_FEDC_Pos                                         (24U)
#define DCI_ESYNCC_FEDC_Msk                                         (0xFFUL << DCI_ESYNCC_FEDC_Pos)                                /*!< 0xFF000000 */
#define DCI_ESYNCC_FEDC                                             DCI_ESYNCC_FEDC_Msk

/********************  Bits definition for DCI_ESYNCUM register  ******************/
#define DCI_ESYNCUM_FSDUM_Pos                                       (0U)
#define DCI_ESYNCUM_FSDUM_Msk                                       (0xFFUL << DCI_ESYNCUM_FSDUM_Pos)                              /*!< 0x000000FF */
#define DCI_ESYNCUM_FSDUM                                           DCI_ESYNCUM_FSDUM_Msk
#define DCI_ESYNCUM_LSDUM_Pos                                       (8U)
#define DCI_ESYNCUM_LSDUM_Msk                                       (0xFFUL << DCI_ESYNCUM_LSDUM_Pos)                              /*!< 0x0000FF00 */
#define DCI_ESYNCUM_LSDUM                                           DCI_ESYNCUM_LSDUM_Msk
#define DCI_ESYNCUM_LEDUM_Pos                                       (16U)
#define DCI_ESYNCUM_LEDUM_Msk                                       (0xFFUL << DCI_ESYNCUM_LEDUM_Pos)                              /*!< 0x00FF0000 */
#define DCI_ESYNCUM_LEDUM                                           DCI_ESYNCUM_LEDUM_Msk
#define DCI_ESYNCUM_FEDUM_Pos                                       (24U)
#define DCI_ESYNCUM_FEDUM_Msk                                       (0xFFUL << DCI_ESYNCUM_FEDUM_Pos)                              /*!< 0xFF000000 */
#define DCI_ESYNCUM_FEDUM                                           DCI_ESYNCUM_FEDUM_Msk

/********************  Bits definition for DCI_CROPWSTAT register  ******************/
#define DCI_CROPWSTAT_HOFSCNT_Pos                                   (0U)
#define DCI_CROPWSTAT_HOFSCNT_Msk                                   (0x3FFFUL << DCI_CROPWSTAT_HOFSCNT_Pos)                        /*!< 0x00003FFF */
#define DCI_CROPWSTAT_HOFSCNT                                       DCI_CROPWSTAT_HOFSCNT_Msk
#define DCI_CROPWSTAT_VSLINECNT_Pos                                 (16U)
#define DCI_CROPWSTAT_VSLINECNT_Msk                                 (0x1FFFUL << DCI_CROPWSTAT_VSLINECNT_Pos)                      /*!< 0x1FFF0000 */
#define DCI_CROPWSTAT_VSLINECNT                                     DCI_CROPWSTAT_VSLINECNT_Msk

/********************  Bits definition for DCI_CROPWSIZE register  ******************/
#define DCI_CROPWSIZE_CCNT_Pos                                      (0U)
#define DCI_CROPWSIZE_CCNT_Msk                                      (0x3FFFUL << DCI_CROPWSIZE_CCNT_Pos)                           /*!< 0x00003FFF */
#define DCI_CROPWSIZE_CCNT                                          DCI_CROPWSIZE_CCNT_Msk
#define DCI_CROPWSIZE_VLINECNT_Pos                                  (16U)
#define DCI_CROPWSIZE_VLINECNT_Msk                                  (0x3FFFUL << DCI_CROPWSIZE_VLINECNT_Pos)                       /*!< 0x3FFF0000 */
#define DCI_CROPWSIZE_VLINECNT                                      DCI_CROPWSIZE_VLINECNT_Msk

/********************  Bits definition for DCI_DATA register  *********************/
#define DCI_DATA_DATA0_Pos                                          (0U)
#define DCI_DATA_DATA0_Msk                                          (0xFFUL << DCI_DATA_DATA0_Pos)                                 /*!< 0x000000FF */
#define DCI_DATA_DATA0                                              DCI_DATA_DATA0_Msk
#define DCI_DATA_DATA1_Pos                                          (8U)
#define DCI_DATA_DATA1_Msk                                          (0xFFUL << DCI_DATA_DATA1_Pos)                                 /*!< 0x0000FF00 */
#define DCI_DATA_DATA1                                              DCI_DATA_DATA1_Msk
#define DCI_DATA_DATA2_Pos                                          (16U)
#define DCI_DATA_DATA2_Msk                                          (0xFFUL << DCI_DATA_DATA2_Pos)                                 /*!< 0x00FF0000 */
#define DCI_DATA_DATA2                                              DCI_DATA_DATA2_Msk
#define DCI_DATA_DATA3_Pos                                          (24U)
#define DCI_DATA_DATA3_Msk                                          (0xFFUL << DCI_DATA_DATA3_Pos)                                 /*!< 0xFF000000 */
#define DCI_DATA_DATA3                                              DCI_DATA_DATA3_Msk

/******************************************************************************/
/*                                                                            */
/*                             DMA Controller                                 */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for DMA_SCFGx register  *****************/
#define DMA_SCFGx_CHSEL_Pos                                         (25U)
#define DMA_SCFGx_CHSEL_Msk                                         (0x7UL << DMA_SCFGx_CHSEL_Pos)                                 /*!< 0x0E000000 */
#define DMA_SCFGx_CHSEL                                             DMA_SCFGx_CHSEL_Msk
#define DMA_SCFGx_CHSEL_0                                           0x02000000U
#define DMA_SCFGx_CHSEL_1                                           0x04000000U
#define DMA_SCFGx_CHSEL_2                                           0x08000000U
#define DMA_SCFGx_MBCFG_Pos                                         (23U)
#define DMA_SCFGx_MBCFG_Msk                                         (0x3UL << DMA_SCFGx_MBCFG_Pos)                                 /*!< 0x01800000 */
#define DMA_SCFGx_MBCFG                                             DMA_SCFGx_MBCFG_Msk
#define DMA_SCFGx_MBCFG_0                                           (0x1UL << DMA_SCFGx_MBCFG_Pos)                                 /*!< 0x00800000 */
#define DMA_SCFGx_MBCFG_1                                           (0x2UL << DMA_SCFGx_MBCFG_Pos)                                 /*!< 0x01000000 */
#define DMA_SCFGx_PBCFG_Pos                                         (21U)
#define DMA_SCFGx_PBCFG_Msk                                         (0x3UL << DMA_SCFGx_PBCFG_Pos)                                 /*!< 0x00600000 */
#define DMA_SCFGx_PBCFG                                             DMA_SCFGx_PBCFG_Msk
#define DMA_SCFGx_PBCFG_0                                           (0x1UL << DMA_SCFGx_PBCFG_Pos)                                 /*!< 0x00200000 */
#define DMA_SCFGx_PBCFG_1                                           (0x2UL << DMA_SCFGx_PBCFG_Pos)                                 /*!< 0x00400000 */
#define DMA_SCFGx_CTARG_Pos                                         (19U)
#define DMA_SCFGx_CTARG_Msk                                         (0x1UL << DMA_SCFGx_CTARG_Pos)                                 /*!< 0x00080000 */
#define DMA_SCFGx_CTARG                                             DMA_SCFGx_CTARG_Msk
#define DMA_SCFGx_DBM_Pos                                           (18U)
#define DMA_SCFGx_DBM_Msk                                           (0x1UL << DMA_SCFGx_DBM_Pos)                                   /*!< 0x00040000 */
#define DMA_SCFGx_DBM                                               DMA_SCFGx_DBM_Msk
#define DMA_SCFGx_PRILCFG_Pos                                       (16U)
#define DMA_SCFGx_PRILCFG_Msk                                       (0x3UL << DMA_SCFGx_PRILCFG_Pos)                               /*!< 0x00030000 */
#define DMA_SCFGx_PRILCFG                                           DMA_SCFGx_PRILCFG_Msk
#define DMA_SCFGx_PRILCFG_0                                         (0x1UL << DMA_SCFGx_PRILCFG_Pos)                               /*!< 0x00010000 */
#define DMA_SCFGx_PRILCFG_1                                         (0x2UL << DMA_SCFGx_PRILCFG_Pos)                               /*!< 0x00020000 */
#define DMA_SCFGx_PERIOSIZE_Pos                                     (15U)
#define DMA_SCFGx_PERIOSIZE_Msk                                     (0x1UL << DMA_SCFGx_PERIOSIZE_Pos)                             /*!< 0x00008000 */
#define DMA_SCFGx_PERIOSIZE                                         DMA_SCFGx_PERIOSIZE_Msk
#define DMA_SCFGx_MEMSIZECFG_Pos                                    (13U)
#define DMA_SCFGx_MEMSIZECFG_Msk                                    (0x3UL << DMA_SCFGx_MEMSIZECFG_Pos)                            /*!< 0x00006000 */
#define DMA_SCFGx_MEMSIZECFG                                        DMA_SCFGx_MEMSIZECFG_Msk
#define DMA_SCFGx_MEMSIZECFG_0                                      (0x1UL << DMA_SCFGx_MEMSIZECFG_Pos)                            /*!< 0x00002000 */
#define DMA_SCFGx_MEMSIZECFG_1                                      (0x2UL << DMA_SCFGx_MEMSIZECFG_Pos)                            /*!< 0x00004000 */
#define DMA_SCFGx_PERSIZECFG_Pos                                    (11U)
#define DMA_SCFGx_PERSIZECFG_Msk                                    (0x3UL << DMA_SCFGx_PERSIZECFG_Pos)                            /*!< 0x00001800 */
#define DMA_SCFGx_PERSIZECFG                                        DMA_SCFGx_PERSIZECFG_Msk
#define DMA_SCFGx_PERSIZECFG_0                                      (0x1UL << DMA_SCFGx_PERSIZECFG_Pos)                            /*!< 0x00000800 */
#define DMA_SCFGx_PERSIZECFG_1                                      (0x2UL << DMA_SCFGx_PERSIZECFG_Pos)                            /*!< 0x00001000 */
#define DMA_SCFGx_MEMIM_Pos                                         (10U)
#define DMA_SCFGx_MEMIM_Msk                                         (0x1UL << DMA_SCFGx_MEMIM_Pos)                                 /*!< 0x00000400 */
#define DMA_SCFGx_MEMIM                                             DMA_SCFGx_MEMIM_Msk
#define DMA_SCFGx_PERIM_Pos                                         (9U)
#define DMA_SCFGx_PERIM_Msk                                         (0x1UL << DMA_SCFGx_PERIM_Pos)                                 /*!< 0x00000200 */
#define DMA_SCFGx_PERIM                                             DMA_SCFGx_PERIM_Msk
#define DMA_SCFGx_CIRCMEN_Pos                                       (8U)
#define DMA_SCFGx_CIRCMEN_Msk                                       (0x1UL << DMA_SCFGx_CIRCMEN_Pos)                               /*!< 0x00000100 */
#define DMA_SCFGx_CIRCMEN                                           DMA_SCFGx_CIRCMEN_Msk
#define DMA_SCFGx_DIRCFG_Pos                                        (6U)
#define DMA_SCFGx_DIRCFG_Msk                                        (0x3UL << DMA_SCFGx_DIRCFG_Pos)                                /*!< 0x000000C0 */
#define DMA_SCFGx_DIRCFG                                            DMA_SCFGx_DIRCFG_Msk
#define DMA_SCFGx_DIRCFG_0                                          (0x1UL << DMA_SCFGx_DIRCFG_Pos)                                /*!< 0x00000040 */
#define DMA_SCFGx_DIRCFG_1                                          (0x2UL << DMA_SCFGx_DIRCFG_Pos)                                /*!< 0x00000080 */
#define DMA_SCFGx_PERFC_Pos                                         (5U)
#define DMA_SCFGx_PERFC_Msk                                         (0x1UL << DMA_SCFGx_PERFC_Pos)                                 /*!< 0x00000020 */
#define DMA_SCFGx_PERFC                                             DMA_SCFGx_PERFC_Msk
#define DMA_SCFGx_TXCIEN_Pos                                        (4U)
#define DMA_SCFGx_TXCIEN_Msk                                        (0x1UL << DMA_SCFGx_TXCIEN_Pos)                                /*!< 0x00000010 */
#define DMA_SCFGx_TXCIEN                                            DMA_SCFGx_TXCIEN_Msk
#define DMA_SCFGx_HTXIEN_Pos                                        (3U)
#define DMA_SCFGx_HTXIEN_Msk                                        (0x1UL << DMA_SCFGx_HTXIEN_Pos)                                /*!< 0x00000008 */
#define DMA_SCFGx_HTXIEN                                            DMA_SCFGx_HTXIEN_Msk
#define DMA_SCFGx_TXEIEN_Pos                                        (2U)
#define DMA_SCFGx_TXEIEN_Msk                                        (0x1UL << DMA_SCFGx_TXEIEN_Pos)                                /*!< 0x00000004 */
#define DMA_SCFGx_TXEIEN                                            DMA_SCFGx_TXEIEN_Msk
#define DMA_SCFGx_DMEIEN_Pos                                        (1U)
#define DMA_SCFGx_DMEIEN_Msk                                        (0x1UL << DMA_SCFGx_DMEIEN_Pos)                                /*!< 0x00000002 */
#define DMA_SCFGx_DMEIEN                                            DMA_SCFGx_DMEIEN_Msk
#define DMA_SCFGx_EN_Pos                                            (0U)
#define DMA_SCFGx_EN_Msk                                            (0x1UL << DMA_SCFGx_EN_Pos)                                    /*!< 0x00000001 */
#define DMA_SCFGx_EN                                                DMA_SCFGx_EN_Msk

/* Legacy defines */
#define DMA_SCFGx_ACK_Pos                                           (20U)
#define DMA_SCFGx_ACK_Msk                                           (0x1UL << DMA_SCFGx_ACK_Pos)                                   /*!< 0x00100000 */
#define DMA_SCFGx_ACK                                               DMA_SCFGx_ACK_Msk

/********************  Bits definition for DMA_NDATAx register  **************/
#define DMA_NDATAx_Pos                                              (0U)
#define DMA_NDATAx_Msk                                              (0xFFFFUL << DMA_NDATAx_Pos)                                   /*!< 0x0000FFFF */
#define DMA_NDATAx                                                  DMA_NDATAx_Msk
#define DMA_NDATAx_0                                                (0x0001UL << DMA_NDATAx_Pos)                                   /*!< 0x00000001 */
#define DMA_NDATAx_1                                                (0x0002UL << DMA_NDATAx_Pos)                                   /*!< 0x00000002 */
#define DMA_NDATAx_2                                                (0x0004UL << DMA_NDATAx_Pos)                                   /*!< 0x00000004 */
#define DMA_NDATAx_3                                                (0x0008UL << DMA_NDATAx_Pos)                                   /*!< 0x00000008 */
#define DMA_NDATAx_4                                                (0x0010UL << DMA_NDATAx_Pos)                                   /*!< 0x00000010 */
#define DMA_NDATAx_5                                                (0x0020UL << DMA_NDATAx_Pos)                                   /*!< 0x00000020 */
#define DMA_NDATAx_6                                                (0x0040UL << DMA_NDATAx_Pos)                                   /*!< 0x00000040 */
#define DMA_NDATAx_7                                                (0x0080UL << DMA_NDATAx_Pos)                                   /*!< 0x00000080 */
#define DMA_NDATAx_8                                                (0x0100UL << DMA_NDATAx_Pos)                                   /*!< 0x00000100 */
#define DMA_NDATAx_9                                                (0x0200UL << DMA_NDATAx_Pos)                                   /*!< 0x00000200 */
#define DMA_NDATAx_10                                               (0x0400UL << DMA_NDATAx_Pos)                                   /*!< 0x00000400 */
#define DMA_NDATAx_11                                               (0x0800UL << DMA_NDATAx_Pos)                                   /*!< 0x00000800 */
#define DMA_NDATAx_12                                               (0x1000UL << DMA_NDATAx_Pos)                                   /*!< 0x00001000 */
#define DMA_NDATAx_13                                               (0x2000UL << DMA_NDATAx_Pos)                                   /*!< 0x00002000 */
#define DMA_NDATAx_14                                               (0x4000UL << DMA_NDATAx_Pos)                                   /*!< 0x00004000 */
#define DMA_NDATAx_15                                               (0x8000UL << DMA_NDATAx_Pos)                                   /*!< 0x00008000 */

/********************  Bits definition for DMA_FCTRLx register  ****************/ 
#define DMA_FCTRLx_FEIEN_Pos                                        (7U)
#define DMA_FCTRLx_FEIEN_Msk                                        (0x1UL << DMA_FCTRLx_FEIEN_Pos)                                /*!< 0x00000080 */
#define DMA_FCTRLx_FEIEN                                            DMA_FCTRLx_FEIEN_Msk
#define DMA_FCTRLx_FSTS_Pos                                         (3U)
#define DMA_FCTRLx_FSTS_Msk                                         (0x7UL << DMA_FCTRLx_FSTS_Pos)                                 /*!< 0x00000038 */
#define DMA_FCTRLx_FSTS                                             DMA_FCTRLx_FSTS_Msk
#define DMA_FCTRLx_FSTS_0                                           (0x1UL << DMA_FCTRLx_FSTS_Pos)                                 /*!< 0x00000008 */
#define DMA_FCTRLx_FSTS_1                                           (0x2UL << DMA_FCTRLx_FSTS_Pos)                                 /*!< 0x00000010 */
#define DMA_FCTRLx_FSTS_2                                           (0x4UL << DMA_FCTRLx_FSTS_Pos)                                 /*!< 0x00000020 */
#define DMA_FCTRLx_DMDEN_Pos                                        (2U)
#define DMA_FCTRLx_DMDEN_Msk                                        (0x1UL << DMA_FCTRLx_DMDEN_Pos)                                /*!< 0x00000004 */
#define DMA_FCTRLx_DMDEN                                            DMA_FCTRLx_DMDEN_Msk
#define DMA_FCTRLx_FTHSEL_Pos                                       (0U)
#define DMA_FCTRLx_FTHSEL_Msk                                       (0x3UL << DMA_FCTRLx_FTHSEL_Pos)                               /*!< 0x00000003 */
#define DMA_FCTRLx_FTHSEL                                           DMA_FCTRLx_FTHSEL_Msk
#define DMA_FCTRLx_FTHSEL_0                                         (0x1UL << DMA_FCTRLx_FTHSEL_Pos)                               /*!< 0x00000001 */
#define DMA_FCTRLx_FTHSEL_1                                         (0x2UL << DMA_FCTRLx_FTHSEL_Pos)                               /*!< 0x00000002 */

/********************  Bits definition for DMA_LINTSTS register  *****************/ 
#define DMA_LINTSTS_TXCIFLG3_Pos                                    (27U)
#define DMA_LINTSTS_TXCIFLG3_Msk                                    (0x1UL << DMA_LINTSTS_TXCIFLG3_Pos)                            /*!< 0x08000000 */
#define DMA_LINTSTS_TXCIFLG3                                        DMA_LINTSTS_TXCIFLG3_Msk
#define DMA_LINTSTS_HTXIFLG3_Pos                                    (26U)
#define DMA_LINTSTS_HTXIFLG3_Msk                                    (0x1UL << DMA_LINTSTS_HTXIFLG3_Pos)                            /*!< 0x04000000 */
#define DMA_LINTSTS_HTXIFLG3                                        DMA_LINTSTS_HTXIFLG3_Msk
#define DMA_LINTSTS_TXEIFLG3_Pos                                    (25U)
#define DMA_LINTSTS_TXEIFLG3_Msk                                    (0x1UL << DMA_LINTSTS_TXEIFLG3_Pos)                            /*!< 0x02000000 */
#define DMA_LINTSTS_TXEIFLG3                                        DMA_LINTSTS_TXEIFLG3_Msk
#define DMA_LINTSTS_DMEIFLG3_Pos                                    (24U)
#define DMA_LINTSTS_DMEIFLG3_Msk                                    (0x1UL << DMA_LINTSTS_DMEIFLG3_Pos)                            /*!< 0x01000000 */
#define DMA_LINTSTS_DMEIFLG3                                        DMA_LINTSTS_DMEIFLG3_Msk
#define DMA_LINTSTS_FEIFLG3_Pos                                     (22U)
#define DMA_LINTSTS_FEIFLG3_Msk                                     (0x1UL << DMA_LINTSTS_FEIFLG3_Pos)                             /*!< 0x00400000 */
#define DMA_LINTSTS_FEIFLG3                                         DMA_LINTSTS_FEIFLG3_Msk
#define DMA_LINTSTS_TXCIFLG2_Pos                                    (21U)
#define DMA_LINTSTS_TXCIFLG2_Msk                                    (0x1UL << DMA_LINTSTS_TXCIFLG2_Pos)                            /*!< 0x00200000 */
#define DMA_LINTSTS_TXCIFLG2                                        DMA_LINTSTS_TXCIFLG2_Msk
#define DMA_LINTSTS_HTXIFLG2_Pos                                    (20U)
#define DMA_LINTSTS_HTXIFLG2_Msk                                    (0x1UL << DMA_LINTSTS_HTXIFLG2_Pos)                            /*!< 0x00100000 */
#define DMA_LINTSTS_HTXIFLG2                                        DMA_LINTSTS_HTXIFLG2_Msk
#define DMA_LINTSTS_TXEIFLG2_Pos                                    (19U)
#define DMA_LINTSTS_TXEIFLG2_Msk                                    (0x1UL << DMA_LINTSTS_TXEIFLG2_Pos)                            /*!< 0x00080000 */
#define DMA_LINTSTS_TXEIFLG2                                        DMA_LINTSTS_TXEIFLG2_Msk
#define DMA_LINTSTS_DMEIFLG2_Pos                                    (18U)
#define DMA_LINTSTS_DMEIFLG2_Msk                                    (0x1UL << DMA_LINTSTS_DMEIFLG2_Pos)                            /*!< 0x00040000 */
#define DMA_LINTSTS_DMEIFLG2                                        DMA_LINTSTS_DMEIFLG2_Msk
#define DMA_LINTSTS_FEIFLG2_Pos                                     (16U)
#define DMA_LINTSTS_FEIFLG2_Msk                                     (0x1UL << DMA_LINTSTS_FEIFLG2_Pos)                             /*!< 0x00010000 */
#define DMA_LINTSTS_FEIFLG2                                         DMA_LINTSTS_FEIFLG2_Msk
#define DMA_LINTSTS_TXCIFLG1_Pos                                    (11U)
#define DMA_LINTSTS_TXCIFLG1_Msk                                    (0x1UL << DMA_LINTSTS_TXCIFLG1_Pos)                            /*!< 0x00000800 */
#define DMA_LINTSTS_TXCIFLG1                                        DMA_LINTSTS_TXCIFLG1_Msk
#define DMA_LINTSTS_HTXIFLG1_Pos                                    (10U)
#define DMA_LINTSTS_HTXIFLG1_Msk                                    (0x1UL << DMA_LINTSTS_HTXIFLG1_Pos)                            /*!< 0x00000400 */
#define DMA_LINTSTS_HTXIFLG1                                        DMA_LINTSTS_HTXIFLG1_Msk
#define DMA_LINTSTS_TXEIFLG1_Pos                                    (9U)
#define DMA_LINTSTS_TXEIFLG1_Msk                                    (0x1UL << DMA_LINTSTS_TXEIFLG1_Pos)                            /*!< 0x00000200 */
#define DMA_LINTSTS_TXEIFLG1                                        DMA_LINTSTS_TXEIFLG1_Msk
#define DMA_LINTSTS_DMEIFLG1_Pos                                    (8U)
#define DMA_LINTSTS_DMEIFLG1_Msk                                    (0x1UL << DMA_LINTSTS_DMEIFLG1_Pos)                            /*!< 0x00000100 */
#define DMA_LINTSTS_DMEIFLG1                                        DMA_LINTSTS_DMEIFLG1_Msk
#define DMA_LINTSTS_FEIFLG1_Pos                                     (6U)
#define DMA_LINTSTS_FEIFLG1_Msk                                     (0x1UL << DMA_LINTSTS_FEIFLG1_Pos)                             /*!< 0x00000040 */
#define DMA_LINTSTS_FEIFLG1                                         DMA_LINTSTS_FEIFLG1_Msk
#define DMA_LINTSTS_TXCIFLG0_Pos                                    (5U)
#define DMA_LINTSTS_TXCIFLG0_Msk                                    (0x1UL << DMA_LINTSTS_TXCIFLG0_Pos)                            /*!< 0x00000020 */
#define DMA_LINTSTS_TXCIFLG0                                        DMA_LINTSTS_TXCIFLG0_Msk
#define DMA_LINTSTS_HTXIFLG0_Pos                                    (4U)
#define DMA_LINTSTS_HTXIFLG0_Msk                                    (0x1UL << DMA_LINTSTS_HTXIFLG0_Pos)                            /*!< 0x00000010 */
#define DMA_LINTSTS_HTXIFLG0                                        DMA_LINTSTS_HTXIFLG0_Msk
#define DMA_LINTSTS_TXEIFLG0_Pos                                    (3U)
#define DMA_LINTSTS_TXEIFLG0_Msk                                    (0x1UL << DMA_LINTSTS_TXEIFLG0_Pos)                            /*!< 0x00000008 */
#define DMA_LINTSTS_TXEIFLG0                                        DMA_LINTSTS_TXEIFLG0_Msk
#define DMA_LINTSTS_DMEIFLG0_Pos                                    (2U)
#define DMA_LINTSTS_DMEIFLG0_Msk                                    (0x1UL << DMA_LINTSTS_DMEIFLG0_Pos)                            /*!< 0x00000004 */
#define DMA_LINTSTS_DMEIFLG0                                        DMA_LINTSTS_DMEIFLG0_Msk
#define DMA_LINTSTS_FEIFLG0_Pos                                     (0U)
#define DMA_LINTSTS_FEIFLG0_Msk                                     (0x1UL << DMA_LINTSTS_FEIFLG0_Pos)                             /*!< 0x00000001 */
#define DMA_LINTSTS_FEIFLG0                                         DMA_LINTSTS_FEIFLG0_Msk

/********************  Bits definition for DMA_HINTSTS register  *****************/ 
#define DMA_HINTSTS_TXCIFLG7_Pos                                    (27U)
#define DMA_HINTSTS_TXCIFLG7_Msk                                    (0x1UL << DMA_HINTSTS_TXCIFLG7_Pos)                            /*!< 0x08000000 */
#define DMA_HINTSTS_TXCIFLG7                                        DMA_HINTSTS_TXCIFLG7_Msk
#define DMA_HINTSTS_HTXIFLG7_Pos                                    (26U)
#define DMA_HINTSTS_HTXIFLG7_Msk                                    (0x1UL << DMA_HINTSTS_HTXIFLG7_Pos)                            /*!< 0x04000000 */
#define DMA_HINTSTS_HTXIFLG7                                        DMA_HINTSTS_HTXIFLG7_Msk
#define DMA_HINTSTS_TXEIFLG7_Pos                                    (25U)
#define DMA_HINTSTS_TXEIFLG7_Msk                                    (0x1UL << DMA_HINTSTS_TXEIFLG7_Pos)                            /*!< 0x02000000 */
#define DMA_HINTSTS_TXEIFLG7                                        DMA_HINTSTS_TXEIFLG7_Msk
#define DMA_HINTSTS_DMEIFLG7_Pos                                    (24U)
#define DMA_HINTSTS_DMEIFLG7_Msk                                    (0x1UL << DMA_HINTSTS_DMEIFLG7_Pos)                            /*!< 0x01000000 */
#define DMA_HINTSTS_DMEIFLG7                                        DMA_HINTSTS_DMEIFLG7_Msk
#define DMA_HINTSTS_FEIFLG7_Pos                                     (22U)
#define DMA_HINTSTS_FEIFLG7_Msk                                     (0x1UL << DMA_HINTSTS_FEIFLG7_Pos)                             /*!< 0x00400000 */
#define DMA_HINTSTS_FEIFLG7                                         DMA_HINTSTS_FEIFLG7_Msk
#define DMA_HINTSTS_TXCIFLG6_Pos                                    (21U)
#define DMA_HINTSTS_TXCIFLG6_Msk                                    (0x1UL << DMA_HINTSTS_TXCIFLG6_Pos)                            /*!< 0x00200000 */
#define DMA_HINTSTS_TXCIFLG6                                        DMA_HINTSTS_TXCIFLG6_Msk
#define DMA_HINTSTS_HTXIFLG6_Pos                                    (20U)
#define DMA_HINTSTS_HTXIFLG6_Msk                                    (0x1UL << DMA_HINTSTS_HTXIFLG6_Pos)                            /*!< 0x00100000 */
#define DMA_HINTSTS_HTXIFLG6                                        DMA_HINTSTS_HTXIFLG6_Msk
#define DMA_HINTSTS_TXEIFLG6_Pos                                    (19U)
#define DMA_HINTSTS_TXEIFLG6_Msk                                    (0x1UL << DMA_HINTSTS_TXEIFLG6_Pos)                            /*!< 0x00080000 */
#define DMA_HINTSTS_TXEIFLG6                                        DMA_HINTSTS_TXEIFLG6_Msk
#define DMA_HINTSTS_DMEIFLG6_Pos                                    (18U)
#define DMA_HINTSTS_DMEIFLG6_Msk                                    (0x1UL << DMA_HINTSTS_DMEIFLG6_Pos)                            /*!< 0x00040000 */
#define DMA_HINTSTS_DMEIFLG6                                        DMA_HINTSTS_DMEIFLG6_Msk
#define DMA_HINTSTS_FEIFLG6_Pos                                     (16U)
#define DMA_HINTSTS_FEIFLG6_Msk                                     (0x1UL << DMA_HINTSTS_FEIFLG6_Pos)                             /*!< 0x00010000 */
#define DMA_HINTSTS_FEIFLG6                                         DMA_HINTSTS_FEIFLG6_Msk
#define DMA_HINTSTS_TXCIFLG5_Pos                                    (11U)
#define DMA_HINTSTS_TXCIFLG5_Msk                                    (0x1UL << DMA_HINTSTS_TXCIFLG5_Pos)                            /*!< 0x00000800 */
#define DMA_HINTSTS_TXCIFLG5                                        DMA_HINTSTS_TXCIFLG5_Msk
#define DMA_HINTSTS_HTXIFLG5_Pos                                    (10U)
#define DMA_HINTSTS_HTXIFLG5_Msk                                    (0x1UL << DMA_HINTSTS_HTXIFLG5_Pos)                            /*!< 0x00000400 */
#define DMA_HINTSTS_HTXIFLG5                                        DMA_HINTSTS_HTXIFLG5_Msk
#define DMA_HINTSTS_TXEIFLG5_Pos                                    (9U)
#define DMA_HINTSTS_TXEIFLG5_Msk                                    (0x1UL << DMA_HINTSTS_TXEIFLG5_Pos)                            /*!< 0x00000200 */
#define DMA_HINTSTS_TXEIFLG5                                        DMA_HINTSTS_TXEIFLG5_Msk
#define DMA_HINTSTS_DMEIFLG5_Pos                                    (8U)
#define DMA_HINTSTS_DMEIFLG5_Msk                                    (0x1UL << DMA_HINTSTS_DMEIFLG5_Pos)                            /*!< 0x00000100 */
#define DMA_HINTSTS_DMEIFLG5                                        DMA_HINTSTS_DMEIFLG5_Msk
#define DMA_HINTSTS_FEIFLG5_Pos                                     (6U)
#define DMA_HINTSTS_FEIFLG5_Msk                                     (0x1UL << DMA_HINTSTS_FEIFLG5_Pos)                             /*!< 0x00000040 */
#define DMA_HINTSTS_FEIFLG5                                         DMA_HINTSTS_FEIFLG5_Msk
#define DMA_HINTSTS_TXCIFLG4_Pos                                    (5U)
#define DMA_HINTSTS_TXCIFLG4_Msk                                    (0x1UL << DMA_HINTSTS_TXCIFLG4_Pos)                            /*!< 0x00000020 */
#define DMA_HINTSTS_TXCIFLG4                                        DMA_HINTSTS_TXCIFLG4_Msk
#define DMA_HINTSTS_HTXIFLG4_Pos                                    (4U)
#define DMA_HINTSTS_HTXIFLG4_Msk                                    (0x1UL << DMA_HINTSTS_HTXIFLG4_Pos)                            /*!< 0x00000010 */
#define DMA_HINTSTS_HTXIFLG4                                        DMA_HINTSTS_HTXIFLG4_Msk
#define DMA_HINTSTS_TXEIFLG4_Pos                                    (3U)
#define DMA_HINTSTS_TXEIFLG4_Msk                                    (0x1UL << DMA_HINTSTS_TXEIFLG4_Pos)                            /*!< 0x00000008 */
#define DMA_HINTSTS_TXEIFLG4                                        DMA_HINTSTS_TXEIFLG4_Msk
#define DMA_HINTSTS_DMEIFLG4_Pos                                    (2U)
#define DMA_HINTSTS_DMEIFLG4_Msk                                    (0x1UL << DMA_HINTSTS_DMEIFLG4_Pos)                            /*!< 0x00000004 */
#define DMA_HINTSTS_DMEIFLG4                                        DMA_HINTSTS_DMEIFLG4_Msk
#define DMA_HINTSTS_FEIFLG4_Pos                                     (0U)
#define DMA_HINTSTS_FEIFLG4_Msk                                     (0x1UL << DMA_HINTSTS_FEIFLG4_Pos)                             /*!< 0x00000001 */
#define DMA_HINTSTS_FEIFLG4                                         DMA_HINTSTS_FEIFLG4_Msk

/********************  Bits definition for DMA_LIFCLR register  ****************/ 
#define DMA_LIFCLR_CTXCIFLG3_Pos                                    (27U)
#define DMA_LIFCLR_CTXCIFLG3_Msk                                    (0x1UL << DMA_LIFCLR_CTXCIFLG3_Pos)                            /*!< 0x08000000 */
#define DMA_LIFCLR_CTXCIFLG3                                        DMA_LIFCLR_CTXCIFLG3_Msk
#define DMA_LIFCLR_CHTXIFLG3_Pos                                    (26U)
#define DMA_LIFCLR_CHTXIFLG3_Msk                                    (0x1UL << DMA_LIFCLR_CHTXIFLG3_Pos)                            /*!< 0x04000000 */
#define DMA_LIFCLR_CHTXIFLG3                                        DMA_LIFCLR_CHTXIFLG3_Msk
#define DMA_LIFCLR_CTXEIFLG3_Pos                                    (25U)
#define DMA_LIFCLR_CTXEIFLG3_Msk                                    (0x1UL << DMA_LIFCLR_CTXEIFLG3_Pos)                            /*!< 0x02000000 */
#define DMA_LIFCLR_CTXEIFLG3                                        DMA_LIFCLR_CTXEIFLG3_Msk
#define DMA_LIFCLR_CDMEIFLG3_Pos                                    (24U)
#define DMA_LIFCLR_CDMEIFLG3_Msk                                    (0x1UL << DMA_LIFCLR_CDMEIFLG3_Pos)                            /*!< 0x01000000 */
#define DMA_LIFCLR_CDMEIFLG3                                        DMA_LIFCLR_CDMEIFLG3_Msk
#define DMA_LIFCLR_CFEIFLG3_Pos                                     (22U)
#define DMA_LIFCLR_CFEIFLG3_Msk                                     (0x1UL << DMA_LIFCLR_CFEIFLG3_Pos)                             /*!< 0x00400000 */
#define DMA_LIFCLR_CFEIFLG3                                         DMA_LIFCLR_CFEIFLG3_Msk
#define DMA_LIFCLR_CTXCIFLG2_Pos                                    (21U)
#define DMA_LIFCLR_CTXCIFLG2_Msk                                    (0x1UL << DMA_LIFCLR_CTXCIFLG2_Pos)                            /*!< 0x00200000 */
#define DMA_LIFCLR_CTXCIFLG2                                        DMA_LIFCLR_CTXCIFLG2_Msk
#define DMA_LIFCLR_CHTXIFLG2_Pos                                    (20U)
#define DMA_LIFCLR_CHTXIFLG2_Msk                                    (0x1UL << DMA_LIFCLR_CHTXIFLG2_Pos)                            /*!< 0x00100000 */
#define DMA_LIFCLR_CHTXIFLG2                                        DMA_LIFCLR_CHTXIFLG2_Msk
#define DMA_LIFCLR_CTXEIFLG2_Pos                                    (19U)
#define DMA_LIFCLR_CTXEIFLG2_Msk                                    (0x1UL << DMA_LIFCLR_CTXEIFLG2_Pos)                            /*!< 0x00080000 */
#define DMA_LIFCLR_CTXEIFLG2                                        DMA_LIFCLR_CTXEIFLG2_Msk
#define DMA_LIFCLR_CDMEIFLG2_Pos                                    (18U)
#define DMA_LIFCLR_CDMEIFLG2_Msk                                    (0x1UL << DMA_LIFCLR_CDMEIFLG2_Pos)                            /*!< 0x00040000 */
#define DMA_LIFCLR_CDMEIFLG2                                        DMA_LIFCLR_CDMEIFLG2_Msk
#define DMA_LIFCLR_CFEIFLG2_Pos                                     (16U)
#define DMA_LIFCLR_CFEIFLG2_Msk                                     (0x1UL << DMA_LIFCLR_CFEIFLG2_Pos)                             /*!< 0x00010000 */
#define DMA_LIFCLR_CFEIFLG2                                         DMA_LIFCLR_CFEIFLG2_Msk
#define DMA_LIFCLR_CTXCIFLG1_Pos                                    (11U)
#define DMA_LIFCLR_CTXCIFLG1_Msk                                    (0x1UL << DMA_LIFCLR_CTXCIFLG1_Pos)                            /*!< 0x00000800 */
#define DMA_LIFCLR_CTXCIFLG1                                        DMA_LIFCLR_CTXCIFLG1_Msk
#define DMA_LIFCLR_CHTXIFLG1_Pos                                    (10U)
#define DMA_LIFCLR_CHTXIFLG1_Msk                                    (0x1UL << DMA_LIFCLR_CHTXIFLG1_Pos)                            /*!< 0x00000400 */
#define DMA_LIFCLR_CHTXIFLG1                                        DMA_LIFCLR_CHTXIFLG1_Msk
#define DMA_LIFCLR_CTXEIFLG1_Pos                                    (9U)
#define DMA_LIFCLR_CTXEIFLG1_Msk                                    (0x1UL << DMA_LIFCLR_CTXEIFLG1_Pos)                            /*!< 0x00000200 */
#define DMA_LIFCLR_CTXEIFLG1                                        DMA_LIFCLR_CTXEIFLG1_Msk
#define DMA_LIFCLR_CDMEIFLG1_Pos                                    (8U)
#define DMA_LIFCLR_CDMEIFLG1_Msk                                    (0x1UL << DMA_LIFCLR_CDMEIFLG1_Pos)                            /*!< 0x00000100 */
#define DMA_LIFCLR_CDMEIFLG1                                        DMA_LIFCLR_CDMEIFLG1_Msk
#define DMA_LIFCLR_CFEIFLG1_Pos                                     (6U)
#define DMA_LIFCLR_CFEIFLG1_Msk                                     (0x1UL << DMA_LIFCLR_CFEIFLG1_Pos)                             /*!< 0x00000040 */
#define DMA_LIFCLR_CFEIFLG1                                         DMA_LIFCLR_CFEIFLG1_Msk
#define DMA_LIFCLR_CTXCIFLG0_Pos                                    (5U)
#define DMA_LIFCLR_CTXCIFLG0_Msk                                    (0x1UL << DMA_LIFCLR_CTXCIFLG0_Pos)                            /*!< 0x00000020 */
#define DMA_LIFCLR_CTXCIFLG0                                        DMA_LIFCLR_CTXCIFLG0_Msk
#define DMA_LIFCLR_CHTXIFLG0_Pos                                    (4U)
#define DMA_LIFCLR_CHTXIFLG0_Msk                                    (0x1UL << DMA_LIFCLR_CHTXIFLG0_Pos)                            /*!< 0x00000010 */
#define DMA_LIFCLR_CHTXIFLG0                                        DMA_LIFCLR_CHTXIFLG0_Msk
#define DMA_LIFCLR_CTXEIFLG0_Pos                                    (3U)
#define DMA_LIFCLR_CTXEIFLG0_Msk                                    (0x1UL << DMA_LIFCLR_CTXEIFLG0_Pos)                            /*!< 0x00000008 */
#define DMA_LIFCLR_CTXEIFLG0                                        DMA_LIFCLR_CTXEIFLG0_Msk
#define DMA_LIFCLR_CDMEIFLG0_Pos                                    (2U)
#define DMA_LIFCLR_CDMEIFLG0_Msk                                    (0x1UL << DMA_LIFCLR_CDMEIFLG0_Pos)                            /*!< 0x00000004 */
#define DMA_LIFCLR_CDMEIFLG0                                        DMA_LIFCLR_CDMEIFLG0_Msk
#define DMA_LIFCLR_CFEIFLG0_Pos                                     (0U)
#define DMA_LIFCLR_CFEIFLG0_Msk                                     (0x1UL << DMA_LIFCLR_CFEIFLG0_Pos)                             /*!< 0x00000001 */
#define DMA_LIFCLR_CFEIFLG0                                         DMA_LIFCLR_CFEIFLG0_Msk

/********************  Bits definition for DMA_HIFCLR  register  ****************/ 
#define DMA_HIFCLR_CTXCIFLG7_Pos                                    (27U)
#define DMA_HIFCLR_CTXCIFLG7_Msk                                    (0x1UL << DMA_HIFCLR_CTXCIFLG7_Pos)                            /*!< 0x08000000 */
#define DMA_HIFCLR_CTXCIFLG7                                        DMA_HIFCLR_CTXCIFLG7_Msk
#define DMA_HIFCLR_CHTXIFLG7_Pos                                    (26U)
#define DMA_HIFCLR_CHTXIFLG7_Msk                                    (0x1UL << DMA_HIFCLR_CHTXIFLG7_Pos)                            /*!< 0x04000000 */
#define DMA_HIFCLR_CHTXIFLG7                                        DMA_HIFCLR_CHTXIFLG7_Msk
#define DMA_HIFCLR_CTXEIFLG7_Pos                                    (25U)
#define DMA_HIFCLR_CTXEIFLG7_Msk                                    (0x1UL << DMA_HIFCLR_CTXEIFLG7_Pos)                            /*!< 0x02000000 */
#define DMA_HIFCLR_CTXEIFLG7                                        DMA_HIFCLR_CTXEIFLG7_Msk
#define DMA_HIFCLR_CDMEIFLG7_Pos                                    (24U)
#define DMA_HIFCLR_CDMEIFLG7_Msk                                    (0x1UL << DMA_HIFCLR_CDMEIFLG7_Pos)                            /*!< 0x01000000 */
#define DMA_HIFCLR_CDMEIFLG7                                        DMA_HIFCLR_CDMEIFLG7_Msk
#define DMA_HIFCLR_CFEIFLG7_Pos                                     (22U)
#define DMA_HIFCLR_CFEIFLG7_Msk                                     (0x1UL << DMA_HIFCLR_CFEIFLG7_Pos)                             /*!< 0x00400000 */
#define DMA_HIFCLR_CFEIFLG7                                         DMA_HIFCLR_CFEIFLG7_Msk
#define DMA_HIFCLR_CTXCIFLG6_Pos                                    (21U)
#define DMA_HIFCLR_CTXCIFLG6_Msk                                    (0x1UL << DMA_HIFCLR_CTXCIFLG6_Pos)                            /*!< 0x00200000 */
#define DMA_HIFCLR_CTXCIFLG6                                        DMA_HIFCLR_CTXCIFLG6_Msk
#define DMA_HIFCLR_CHTXIFLG6_Pos                                    (20U)
#define DMA_HIFCLR_CHTXIFLG6_Msk                                    (0x1UL << DMA_HIFCLR_CHTXIFLG6_Pos)                            /*!< 0x00100000 */
#define DMA_HIFCLR_CHTXIFLG6                                        DMA_HIFCLR_CHTXIFLG6_Msk
#define DMA_HIFCLR_CTXEIFLG6_Pos                                    (19U)
#define DMA_HIFCLR_CTXEIFLG6_Msk                                    (0x1UL << DMA_HIFCLR_CTXEIFLG6_Pos)                            /*!< 0x00080000 */
#define DMA_HIFCLR_CTXEIFLG6                                        DMA_HIFCLR_CTXEIFLG6_Msk
#define DMA_HIFCLR_CDMEIFLG6_Pos                                    (18U)
#define DMA_HIFCLR_CDMEIFLG6_Msk                                    (0x1UL << DMA_HIFCLR_CDMEIFLG6_Pos)                            /*!< 0x00040000 */
#define DMA_HIFCLR_CDMEIFLG6                                        DMA_HIFCLR_CDMEIFLG6_Msk
#define DMA_HIFCLR_CFEIFLG6_Pos                                     (16U)
#define DMA_HIFCLR_CFEIFLG6_Msk                                     (0x1UL << DMA_HIFCLR_CFEIFLG6_Pos)                             /*!< 0x00010000 */
#define DMA_HIFCLR_CFEIFLG6                                         DMA_HIFCLR_CFEIFLG6_Msk
#define DMA_HIFCLR_CTXCIFLG5_Pos                                    (11U)
#define DMA_HIFCLR_CTXCIFLG5_Msk                                    (0x1UL << DMA_HIFCLR_CTXCIFLG5_Pos)                            /*!< 0x00000800 */
#define DMA_HIFCLR_CTXCIFLG5                                        DMA_HIFCLR_CTXCIFLG5_Msk
#define DMA_HIFCLR_CHTXIFLG5_Pos                                    (10U)
#define DMA_HIFCLR_CHTXIFLG5_Msk                                    (0x1UL << DMA_HIFCLR_CHTXIFLG5_Pos)                            /*!< 0x00000400 */
#define DMA_HIFCLR_CHTXIFLG5                                        DMA_HIFCLR_CHTXIFLG5_Msk
#define DMA_HIFCLR_CTXEIFLG5_Pos                                    (9U)
#define DMA_HIFCLR_CTXEIFLG5_Msk                                    (0x1UL << DMA_HIFCLR_CTXEIFLG5_Pos)                            /*!< 0x00000200 */
#define DMA_HIFCLR_CTXEIFLG5                                        DMA_HIFCLR_CTXEIFLG5_Msk
#define DMA_HIFCLR_CDMEIFLG5_Pos                                    (8U)
#define DMA_HIFCLR_CDMEIFLG5_Msk                                    (0x1UL << DMA_HIFCLR_CDMEIFLG5_Pos)                            /*!< 0x00000100 */
#define DMA_HIFCLR_CDMEIFLG5                                        DMA_HIFCLR_CDMEIFLG5_Msk
#define DMA_HIFCLR_CFEIFLG5_Pos                                     (6U)
#define DMA_HIFCLR_CFEIFLG5_Msk                                     (0x1UL << DMA_HIFCLR_CFEIFLG5_Pos)                             /*!< 0x00000040 */
#define DMA_HIFCLR_CFEIFLG5                                         DMA_HIFCLR_CFEIFLG5_Msk
#define DMA_HIFCLR_CTXCIFLG4_Pos                                    (5U)
#define DMA_HIFCLR_CTXCIFLG4_Msk                                    (0x1UL << DMA_HIFCLR_CTXCIFLG4_Pos)                            /*!< 0x00000020 */
#define DMA_HIFCLR_CTXCIFLG4                                        DMA_HIFCLR_CTXCIFLG4_Msk
#define DMA_HIFCLR_CHTXIFLG4_Pos                                    (4U)
#define DMA_HIFCLR_CHTXIFLG4_Msk                                    (0x1UL << DMA_HIFCLR_CHTXIFLG4_Pos)                            /*!< 0x00000010 */
#define DMA_HIFCLR_CHTXIFLG4                                        DMA_HIFCLR_CHTXIFLG4_Msk
#define DMA_HIFCLR_CTXEIFLG4_Pos                                    (3U)
#define DMA_HIFCLR_CTXEIFLG4_Msk                                    (0x1UL << DMA_HIFCLR_CTXEIFLG4_Pos)                            /*!< 0x00000008 */
#define DMA_HIFCLR_CTXEIFLG4                                        DMA_HIFCLR_CTXEIFLG4_Msk
#define DMA_HIFCLR_CDMEIFLG4_Pos                                    (2U)
#define DMA_HIFCLR_CDMEIFLG4_Msk                                    (0x1UL << DMA_HIFCLR_CDMEIFLG4_Pos)                            /*!< 0x00000004 */
#define DMA_HIFCLR_CDMEIFLG4                                        DMA_HIFCLR_CDMEIFLG4_Msk
#define DMA_HIFCLR_CFEIFLG4_Pos                                     (0U)
#define DMA_HIFCLR_CFEIFLG4_Msk                                     (0x1UL << DMA_HIFCLR_CFEIFLG4_Pos)                             /*!< 0x00000001 */
#define DMA_HIFCLR_CFEIFLG4                                         DMA_HIFCLR_CFEIFLG4_Msk

/******************  Bit definition for DMA_SxPAR register  ********************/
#define DMA_PADDRx_PADDR_Pos                                        (0U)
#define DMA_PADDRx_PADDR_Msk                                        (0xFFFFFFFFUL << DMA_PADDRx_PADDR_Pos)                         /*!< 0xFFFFFFFF */
#define DMA_PADDRx_PADDR                                            DMA_PADDRx_PADDR_Msk                                           /*!< Peripheral Address */

/******************  Bit definition for DMA_SxM0AR register  ********************/
#define DMA_M0ADDRx_M0ADDR_Pos                                      (0U)
#define DMA_M0ADDRx_M0ADDR_Msk                                      (0xFFFFFFFFUL << DMA_M0ADDRx_M0ADDR_Pos)                       /*!< 0xFFFFFFFF */
#define DMA_M0ADDRx_M0ADDR                                          DMA_M0ADDRx_M0ADDR_Msk                                         /*!< Memory Address */

/******************  Bit definition for DMA_SxM1AR register  ********************/
#define DMA_M1ADDRx_M1ADDR_Pos                                      (0U)
#define DMA_M1ADDRx_M1ADDR_Msk                                      (0xFFFFFFFFUL << DMA_M1ADDRx_M1ADDR_Pos)                       /*!< 0xFFFFFFFF */
#define DMA_M1ADDRx_M1ADDR                                          DMA_M1ADDRx_M1ADDR_Msk                                         /*!< Memory Address */


/******************************************************************************/
/*                                                                            */
/*                    External Interrupt/Event Controller                     */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for EINT_IMASK register  *******************/
#define EINT_IMASK_IMASK0_Pos                                       (0U)
#define EINT_IMASK_IMASK0_Msk                                       (0x1UL << EINT_IMASK_IMASK0_Pos)                               /*!< 0x00000001 */
#define EINT_IMASK_IMASK0                                           EINT_IMASK_IMASK0_Msk                                          /*!< Interrupt Mask on line 0 */
#define EINT_IMASK_IMASK1_Pos                                       (1U)
#define EINT_IMASK_IMASK1_Msk                                       (0x1UL << EINT_IMASK_IMASK1_Pos)                               /*!< 0x00000002 */
#define EINT_IMASK_IMASK1                                           EINT_IMASK_IMASK1_Msk                                          /*!< Interrupt Mask on line 1 */
#define EINT_IMASK_IMASK2_Pos                                       (2U)
#define EINT_IMASK_IMASK2_Msk                                       (0x1UL << EINT_IMASK_IMASK2_Pos)                               /*!< 0x00000004 */
#define EINT_IMASK_IMASK2                                           EINT_IMASK_IMASK2_Msk                                          /*!< Interrupt Mask on line 2 */
#define EINT_IMASK_IMASK3_Pos                                       (3U)
#define EINT_IMASK_IMASK3_Msk                                       (0x1UL << EINT_IMASK_IMASK3_Pos)                               /*!< 0x00000008 */
#define EINT_IMASK_IMASK3                                           EINT_IMASK_IMASK3_Msk                                          /*!< Interrupt Mask on line 3 */
#define EINT_IMASK_IMASK4_Pos                                       (4U)
#define EINT_IMASK_IMASK4_Msk                                       (0x1UL << EINT_IMASK_IMASK4_Pos)                               /*!< 0x00000010 */
#define EINT_IMASK_IMASK4                                           EINT_IMASK_IMASK4_Msk                                          /*!< Interrupt Mask on line 4 */
#define EINT_IMASK_IMASK5_Pos                                       (5U)
#define EINT_IMASK_IMASK5_Msk                                       (0x1UL << EINT_IMASK_IMASK5_Pos)                               /*!< 0x00000020 */
#define EINT_IMASK_IMASK5                                           EINT_IMASK_IMASK5_Msk                                          /*!< Interrupt Mask on line 5 */
#define EINT_IMASK_IMASK6_Pos                                       (6U)
#define EINT_IMASK_IMASK6_Msk                                       (0x1UL << EINT_IMASK_IMASK6_Pos)                               /*!< 0x00000040 */
#define EINT_IMASK_IMASK6                                           EINT_IMASK_IMASK6_Msk                                          /*!< Interrupt Mask on line 6 */
#define EINT_IMASK_IMASK7_Pos                                       (7U)
#define EINT_IMASK_IMASK7_Msk                                       (0x1UL << EINT_IMASK_IMASK7_Pos)                               /*!< 0x00000080 */
#define EINT_IMASK_IMASK7                                           EINT_IMASK_IMASK7_Msk                                          /*!< Interrupt Mask on line 7 */
#define EINT_IMASK_IMASK8_Pos                                       (8U)
#define EINT_IMASK_IMASK8_Msk                                       (0x1UL << EINT_IMASK_IMASK8_Pos)                               /*!< 0x00000100 */
#define EINT_IMASK_IMASK8                                           EINT_IMASK_IMASK8_Msk                                          /*!< Interrupt Mask on line 8 */
#define EINT_IMASK_IMASK9_Pos                                       (9U)
#define EINT_IMASK_IMASK9_Msk                                       (0x1UL << EINT_IMASK_IMASK9_Pos)                               /*!< 0x00000200 */
#define EINT_IMASK_IMASK9                                           EINT_IMASK_IMASK9_Msk                                          /*!< Interrupt Mask on line 9 */
#define EINT_IMASK_IMASK10_Pos                                      (10U)
#define EINT_IMASK_IMASK10_Msk                                      (0x1UL << EINT_IMASK_IMASK10_Pos)                              /*!< 0x00000400 */
#define EINT_IMASK_IMASK10                                          EINT_IMASK_IMASK10_Msk                                         /*!< Interrupt Mask on line 10 */
#define EINT_IMASK_IMASK11_Pos                                      (11U)
#define EINT_IMASK_IMASK11_Msk                                      (0x1UL << EINT_IMASK_IMASK11_Pos)                              /*!< 0x00000800 */
#define EINT_IMASK_IMASK11                                          EINT_IMASK_IMASK11_Msk                                         /*!< Interrupt Mask on line 11 */
#define EINT_IMASK_IMASK12_Pos                                      (12U)
#define EINT_IMASK_IMASK12_Msk                                      (0x1UL << EINT_IMASK_IMASK12_Pos)                              /*!< 0x00001000 */
#define EINT_IMASK_IMASK12                                          EINT_IMASK_IMASK12_Msk                                         /*!< Interrupt Mask on line 12 */
#define EINT_IMASK_IMASK13_Pos                                      (13U)
#define EINT_IMASK_IMASK13_Msk                                      (0x1UL << EINT_IMASK_IMASK13_Pos)                              /*!< 0x00002000 */
#define EINT_IMASK_IMASK13                                          EINT_IMASK_IMASK13_Msk                                         /*!< Interrupt Mask on line 13 */
#define EINT_IMASK_IMASK14_Pos                                      (14U)
#define EINT_IMASK_IMASK14_Msk                                      (0x1UL << EINT_IMASK_IMASK14_Pos)                              /*!< 0x00004000 */
#define EINT_IMASK_IMASK14                                          EINT_IMASK_IMASK14_Msk                                         /*!< Interrupt Mask on line 14 */
#define EINT_IMASK_IMASK15_Pos                                      (15U)
#define EINT_IMASK_IMASK15_Msk                                      (0x1UL << EINT_IMASK_IMASK15_Pos)                              /*!< 0x00008000 */
#define EINT_IMASK_IMASK15                                          EINT_IMASK_IMASK15_Msk                                         /*!< Interrupt Mask on line 15 */
#define EINT_IMASK_IMASK16_Pos                                      (16U)
#define EINT_IMASK_IMASK16_Msk                                      (0x1UL << EINT_IMASK_IMASK16_Pos)                              /*!< 0x00010000 */
#define EINT_IMASK_IMASK16                                          EINT_IMASK_IMASK16_Msk                                         /*!< Interrupt Mask on line 16 */
#define EINT_IMASK_IMASK17_Pos                                      (17U)
#define EINT_IMASK_IMASK17_Msk                                      (0x1UL << EINT_IMASK_IMASK17_Pos)                              /*!< 0x00020000 */
#define EINT_IMASK_IMASK17                                          EINT_IMASK_IMASK17_Msk                                         /*!< Interrupt Mask on line 17 */
#define EINT_IMASK_IMASK18_Pos                                      (18U)
#define EINT_IMASK_IMASK18_Msk                                      (0x1UL << EINT_IMASK_IMASK18_Pos)                              /*!< 0x00040000 */
#define EINT_IMASK_IMASK18                                          EINT_IMASK_IMASK18_Msk                                         /*!< Interrupt Mask on line 18 */
#define EINT_IMASK_IMASK19_Pos                                      (19U)
#define EINT_IMASK_IMASK19_Msk                                      (0x1UL << EINT_IMASK_IMASK19_Pos)                              /*!< 0x00080000 */
#define EINT_IMASK_IMASK19                                          EINT_IMASK_IMASK19_Msk                                         /*!< Interrupt Mask on line 19 */
#define EINT_IMASK_IMASK20_Pos                                      (20U)
#define EINT_IMASK_IMASK20_Msk                                      (0x1UL << EINT_IMASK_IMASK20_Pos)                              /*!< 0x00100000 */
#define EINT_IMASK_IMASK20                                          EINT_IMASK_IMASK20_Msk                                         /*!< Interrupt Mask on line 20 */
#define EINT_IMASK_IMASK21_Pos                                      (21U)
#define EINT_IMASK_IMASK21_Msk                                      (0x1UL << EINT_IMASK_IMASK21_Pos)                              /*!< 0x00200000 */
#define EINT_IMASK_IMASK21                                          EINT_IMASK_IMASK21_Msk                                         /*!< Interrupt Mask on line 21 */
#define EINT_IMASK_IMASK22_Pos                                      (22U)
#define EINT_IMASK_IMASK22_Msk                                      (0x1UL << EINT_IMASK_IMASK22_Pos)                              /*!< 0x00400000 */
#define EINT_IMASK_IMASK22                                          EINT_IMASK_IMASK22_Msk                                         /*!< Interrupt Mask on line 22 */

/* Reference Defines */
#define EINT_IMASK_IM0                                              EINT_IMASK_IMASK0
#define EINT_IMASK_IM1                                              EINT_IMASK_IMASK1
#define EINT_IMASK_IM2                                              EINT_IMASK_IMASK2
#define EINT_IMASK_IM3                                              EINT_IMASK_IMASK3
#define EINT_IMASK_IM4                                              EINT_IMASK_IMASK4
#define EINT_IMASK_IM5                                              EINT_IMASK_IMASK5
#define EINT_IMASK_IM6                                              EINT_IMASK_IMASK6
#define EINT_IMASK_IM7                                              EINT_IMASK_IMASK7
#define EINT_IMASK_IM8                                              EINT_IMASK_IMASK8
#define EINT_IMASK_IM9                                              EINT_IMASK_IMASK9
#define EINT_IMASK_IM10                                             EINT_IMASK_IMASK10
#define EINT_IMASK_IM11                                             EINT_IMASK_IMASK11
#define EINT_IMASK_IM12                                             EINT_IMASK_IMASK12
#define EINT_IMASK_IM13                                             EINT_IMASK_IMASK13
#define EINT_IMASK_IM14                                             EINT_IMASK_IMASK14
#define EINT_IMASK_IM15                                             EINT_IMASK_IMASK15
#define EINT_IMASK_IM16                                             EINT_IMASK_IMASK16
#define EINT_IMASK_IM17                                             EINT_IMASK_IMASK17
#define EINT_IMASK_IM18                                             EINT_IMASK_IMASK18
#define EINT_IMASK_IM19                                             EINT_IMASK_IMASK19
#define EINT_IMASK_IM20                                             EINT_IMASK_IMASK20
#define EINT_IMASK_IM21                                             EINT_IMASK_IMASK21
#define EINT_IMASK_IM22                                             EINT_IMASK_IMASK22
#define EINT_IMASK_IM_Pos                                           (0U)
#define EINT_IMASK_IM_Msk                                           (0x7FFFFFUL << EINT_IMASK_IM_Pos)                              /*!< 0x007FFFFF */
#define EINT_IMASK_IM                                               EINT_IMASK_IM_Msk                                              /*!< Interrupt Mask All */

/*******************  Bit definition for EINT_EMASK register  *******************/
#define EINT_EMASK_EMASK0_Pos                                       (0U)
#define EINT_EMASK_EMASK0_Msk                                       (0x1UL << EINT_EMASK_EMASK0_Pos)                               /*!< 0x00000001 */
#define EINT_EMASK_EMASK0                                           EINT_EMASK_EMASK0_Msk                                          /*!< Event Mask on line 0 */
#define EINT_EMASK_EMASK1_Pos                                       (1U)
#define EINT_EMASK_EMASK1_Msk                                       (0x1UL << EINT_EMASK_EMASK1_Pos)                               /*!< 0x00000002 */
#define EINT_EMASK_EMASK1                                           EINT_EMASK_EMASK1_Msk                                          /*!< Event Mask on line 1 */
#define EINT_EMASK_EMASK2_Pos                                       (2U)
#define EINT_EMASK_EMASK2_Msk                                       (0x1UL << EINT_EMASK_EMASK2_Pos)                               /*!< 0x00000004 */
#define EINT_EMASK_EMASK2                                           EINT_EMASK_EMASK2_Msk                                          /*!< Event Mask on line 2 */
#define EINT_EMASK_EMASK3_Pos                                       (3U)
#define EINT_EMASK_EMASK3_Msk                                       (0x1UL << EINT_EMASK_EMASK3_Pos)                               /*!< 0x00000008 */
#define EINT_EMASK_EMASK3                                           EINT_EMASK_EMASK3_Msk                                          /*!< Event Mask on line 3 */
#define EINT_EMASK_EMASK4_Pos                                       (4U)
#define EINT_EMASK_EMASK4_Msk                                       (0x1UL << EINT_EMASK_EMASK4_Pos)                               /*!< 0x00000010 */
#define EINT_EMASK_EMASK4                                           EINT_EMASK_EMASK4_Msk                                          /*!< Event Mask on line 4 */
#define EINT_EMASK_EMASK5_Pos                                       (5U)
#define EINT_EMASK_EMASK5_Msk                                       (0x1UL << EINT_EMASK_EMASK5_Pos)                               /*!< 0x00000020 */
#define EINT_EMASK_EMASK5                                           EINT_EMASK_EMASK5_Msk                                          /*!< Event Mask on line 5 */
#define EINT_EMASK_EMASK6_Pos                                       (6U)
#define EINT_EMASK_EMASK6_Msk                                       (0x1UL << EINT_EMASK_EMASK6_Pos)                               /*!< 0x00000040 */
#define EINT_EMASK_EMASK6                                           EINT_EMASK_EMASK6_Msk                                          /*!< Event Mask on line 6 */
#define EINT_EMASK_EMASK7_Pos                                       (7U)
#define EINT_EMASK_EMASK7_Msk                                       (0x1UL << EINT_EMASK_EMASK7_Pos)                               /*!< 0x00000080 */
#define EINT_EMASK_EMASK7                                           EINT_EMASK_EMASK7_Msk                                          /*!< Event Mask on line 7 */
#define EINT_EMASK_EMASK8_Pos                                       (8U)
#define EINT_EMASK_EMASK8_Msk                                       (0x1UL << EINT_EMASK_EMASK8_Pos)                               /*!< 0x00000100 */
#define EINT_EMASK_EMASK8                                           EINT_EMASK_EMASK8_Msk                                          /*!< Event Mask on line 8 */
#define EINT_EMASK_EMASK9_Pos                                       (9U)
#define EINT_EMASK_EMASK9_Msk                                       (0x1UL << EINT_EMASK_EMASK9_Pos)                               /*!< 0x00000200 */
#define EINT_EMASK_EMASK9                                           EINT_EMASK_EMASK9_Msk                                          /*!< Event Mask on line 9 */
#define EINT_EMASK_EMASK10_Pos                                      (10U)
#define EINT_EMASK_EMASK10_Msk                                      (0x1UL << EINT_EMASK_EMASK10_Pos)                              /*!< 0x00000400 */
#define EINT_EMASK_EMASK10                                          EINT_EMASK_EMASK10_Msk                                         /*!< Event Mask on line 10 */
#define EINT_EMASK_EMASK11_Pos                                      (11U)
#define EINT_EMASK_EMASK11_Msk                                      (0x1UL << EINT_EMASK_EMASK11_Pos)                              /*!< 0x00000800 */
#define EINT_EMASK_EMASK11                                          EINT_EMASK_EMASK11_Msk                                         /*!< Event Mask on line 11 */
#define EINT_EMASK_EMASK12_Pos                                      (12U)
#define EINT_EMASK_EMASK12_Msk                                      (0x1UL << EINT_EMASK_EMASK12_Pos)                              /*!< 0x00001000 */
#define EINT_EMASK_EMASK12                                          EINT_EMASK_EMASK12_Msk                                         /*!< Event Mask on line 12 */
#define EINT_EMASK_EMASK13_Pos                                      (13U)
#define EINT_EMASK_EMASK13_Msk                                      (0x1UL << EINT_EMASK_EMASK13_Pos)                              /*!< 0x00002000 */
#define EINT_EMASK_EMASK13                                          EINT_EMASK_EMASK13_Msk                                         /*!< Event Mask on line 13 */
#define EINT_EMASK_EMASK14_Pos                                      (14U)
#define EINT_EMASK_EMASK14_Msk                                      (0x1UL << EINT_EMASK_EMASK14_Pos)                              /*!< 0x00004000 */
#define EINT_EMASK_EMASK14                                          EINT_EMASK_EMASK14_Msk                                         /*!< Event Mask on line 14 */
#define EINT_EMASK_EMASK15_Pos                                      (15U)
#define EINT_EMASK_EMASK15_Msk                                      (0x1UL << EINT_EMASK_EMASK15_Pos)                              /*!< 0x00008000 */
#define EINT_EMASK_EMASK15                                          EINT_EMASK_EMASK15_Msk                                         /*!< Event Mask on line 15 */
#define EINT_EMASK_EMASK16_Pos                                      (16U)
#define EINT_EMASK_EMASK16_Msk                                      (0x1UL << EINT_EMASK_EMASK16_Pos)                              /*!< 0x00010000 */
#define EINT_EMASK_EMASK16                                          EINT_EMASK_EMASK16_Msk                                         /*!< Event Mask on line 16 */
#define EINT_EMASK_EMASK17_Pos                                      (17U)
#define EINT_EMASK_EMASK17_Msk                                      (0x1UL << EINT_EMASK_EMASK17_Pos)                              /*!< 0x00020000 */
#define EINT_EMASK_EMASK17                                          EINT_EMASK_EMASK17_Msk                                         /*!< Event Mask on line 17 */
#define EINT_EMASK_EMASK18_Pos                                      (18U)
#define EINT_EMASK_EMASK18_Msk                                      (0x1UL << EINT_EMASK_EMASK18_Pos)                              /*!< 0x00040000 */
#define EINT_EMASK_EMASK18                                          EINT_EMASK_EMASK18_Msk                                         /*!< Event Mask on line 18 */
#define EINT_EMASK_EMASK19_Pos                                      (19U)
#define EINT_EMASK_EMASK19_Msk                                      (0x1UL << EINT_EMASK_EMASK19_Pos)                              /*!< 0x00080000 */
#define EINT_EMASK_EMASK19                                          EINT_EMASK_EMASK19_Msk                                         /*!< Event Mask on line 19 */
#define EINT_EMASK_EMASK20_Pos                                      (20U)
#define EINT_EMASK_EMASK20_Msk                                      (0x1UL << EINT_EMASK_EMASK20_Pos)                              /*!< 0x00100000 */
#define EINT_EMASK_EMASK20                                          EINT_EMASK_EMASK20_Msk                                         /*!< Event Mask on line 20 */
#define EINT_EMASK_EMASK21_Pos                                      (21U)
#define EINT_EMASK_EMASK21_Msk                                      (0x1UL << EINT_EMASK_EMASK21_Pos)                              /*!< 0x00200000 */
#define EINT_EMASK_EMASK21                                          EINT_EMASK_EMASK21_Msk                                         /*!< Event Mask on line 21 */
#define EINT_EMASK_EMASK22_Pos                                      (22U)
#define EINT_EMASK_EMASK22_Msk                                      (0x1UL << EINT_EMASK_EMASK22_Pos)                              /*!< 0x00400000 */
#define EINT_EMASK_EMASK22                                          EINT_EMASK_EMASK22_Msk                                         /*!< Event Mask on line 22 */

/* Reference Defines */
#define EINT_EMASK_EM0                                              EINT_EMASK_EMASK0
#define EINT_EMASK_EM1                                              EINT_EMASK_EMASK1
#define EINT_EMASK_EM2                                              EINT_EMASK_EMASK2
#define EINT_EMASK_EM3                                              EINT_EMASK_EMASK3
#define EINT_EMASK_EM4                                              EINT_EMASK_EMASK4
#define EINT_EMASK_EM5                                              EINT_EMASK_EMASK5
#define EINT_EMASK_EM6                                              EINT_EMASK_EMASK6
#define EINT_EMASK_EM7                                              EINT_EMASK_EMASK7
#define EINT_EMASK_EM8                                              EINT_EMASK_EMASK8
#define EINT_EMASK_EM9                                              EINT_EMASK_EMASK9
#define EINT_EMASK_EM10                                             EINT_EMASK_EMASK10
#define EINT_EMASK_EM11                                             EINT_EMASK_EMASK11
#define EINT_EMASK_EM12                                             EINT_EMASK_EMASK12
#define EINT_EMASK_EM13                                             EINT_EMASK_EMASK13
#define EINT_EMASK_EM14                                             EINT_EMASK_EMASK14
#define EINT_EMASK_EM15                                             EINT_EMASK_EMASK15
#define EINT_EMASK_EM16                                             EINT_EMASK_EMASK16
#define EINT_EMASK_EM17                                             EINT_EMASK_EMASK17
#define EINT_EMASK_EM18                                             EINT_EMASK_EMASK18
#define EINT_EMASK_EM19                                             EINT_EMASK_EMASK19
#define EINT_EMASK_EM20                                             EINT_EMASK_EMASK20
#define EINT_EMASK_EM21                                             EINT_EMASK_EMASK21
#define EINT_EMASK_EM22                                             EINT_EMASK_EMASK22

/******************  Bit definition for EINT_RTEN register  *******************/
#define EINT_RTEN_RTEN0_Pos                                         (0U)
#define EINT_RTEN_RTEN0_Msk                                         (0x1UL << EINT_RTEN_RTEN0_Pos)                                 /*!< 0x00000001 */
#define EINT_RTEN_RTEN0                                             EINT_RTEN_RTEN0_Msk                                            /*!< Rising trigger event configuration bit of line 0 */
#define EINT_RTEN_RTEN1_Pos                                         (1U)
#define EINT_RTEN_RTEN1_Msk                                         (0x1UL << EINT_RTEN_RTEN1_Pos)                                 /*!< 0x00000002 */
#define EINT_RTEN_RTEN1                                             EINT_RTEN_RTEN1_Msk                                            /*!< Rising trigger event configuration bit of line 1 */
#define EINT_RTEN_RTEN2_Pos                                         (2U)
#define EINT_RTEN_RTEN2_Msk                                         (0x1UL << EINT_RTEN_RTEN2_Pos)                                 /*!< 0x00000004 */
#define EINT_RTEN_RTEN2                                             EINT_RTEN_RTEN2_Msk                                            /*!< Rising trigger event configuration bit of line 2 */
#define EINT_RTEN_RTEN3_Pos                                         (3U)
#define EINT_RTEN_RTEN3_Msk                                         (0x1UL << EINT_RTEN_RTEN3_Pos)                                 /*!< 0x00000008 */
#define EINT_RTEN_RTEN3                                             EINT_RTEN_RTEN3_Msk                                            /*!< Rising trigger event configuration bit of line 3 */
#define EINT_RTEN_RTEN4_Pos                                         (4U)
#define EINT_RTEN_RTEN4_Msk                                         (0x1UL << EINT_RTEN_RTEN4_Pos)                                 /*!< 0x00000010 */
#define EINT_RTEN_RTEN4                                             EINT_RTEN_RTEN4_Msk                                            /*!< Rising trigger event configuration bit of line 4 */
#define EINT_RTEN_RTEN5_Pos                                         (5U)
#define EINT_RTEN_RTEN5_Msk                                         (0x1UL << EINT_RTEN_RTEN5_Pos)                                 /*!< 0x00000020 */
#define EINT_RTEN_RTEN5                                             EINT_RTEN_RTEN5_Msk                                            /*!< Rising trigger event configuration bit of line 5 */
#define EINT_RTEN_RTEN6_Pos                                         (6U)
#define EINT_RTEN_RTEN6_Msk                                         (0x1UL << EINT_RTEN_RTEN6_Pos)                                 /*!< 0x00000040 */
#define EINT_RTEN_RTEN6                                             EINT_RTEN_RTEN6_Msk                                            /*!< Rising trigger event configuration bit of line 6 */
#define EINT_RTEN_RTEN7_Pos                                         (7U)
#define EINT_RTEN_RTEN7_Msk                                         (0x1UL << EINT_RTEN_RTEN7_Pos)                                 /*!< 0x00000080 */
#define EINT_RTEN_RTEN7                                             EINT_RTEN_RTEN7_Msk                                            /*!< Rising trigger event configuration bit of line 7 */
#define EINT_RTEN_RTEN8_Pos                                         (8U)
#define EINT_RTEN_RTEN8_Msk                                         (0x1UL << EINT_RTEN_RTEN8_Pos)                                 /*!< 0x00000100 */
#define EINT_RTEN_RTEN8                                             EINT_RTEN_RTEN8_Msk                                            /*!< Rising trigger event configuration bit of line 8 */
#define EINT_RTEN_RTEN9_Pos                                         (9U)
#define EINT_RTEN_RTEN9_Msk                                         (0x1UL << EINT_RTEN_RTEN9_Pos)                                 /*!< 0x00000200 */
#define EINT_RTEN_RTEN9                                             EINT_RTEN_RTEN9_Msk                                            /*!< Rising trigger event configuration bit of line 9 */
#define EINT_RTEN_RTEN10_Pos                                        (10U)
#define EINT_RTEN_RTEN10_Msk                                        (0x1UL << EINT_RTEN_RTEN10_Pos)                                /*!< 0x00000400 */
#define EINT_RTEN_RTEN10                                            EINT_RTEN_RTEN10_Msk                                           /*!< Rising trigger event configuration bit of line 10 */
#define EINT_RTEN_RTEN11_Pos                                        (11U)
#define EINT_RTEN_RTEN11_Msk                                        (0x1UL << EINT_RTEN_RTEN11_Pos)                                /*!< 0x00000800 */
#define EINT_RTEN_RTEN11                                            EINT_RTEN_RTEN11_Msk                                           /*!< Rising trigger event configuration bit of line 11 */
#define EINT_RTEN_RTEN12_Pos                                        (12U)
#define EINT_RTEN_RTEN12_Msk                                        (0x1UL << EINT_RTEN_RTEN12_Pos)                                /*!< 0x00001000 */
#define EINT_RTEN_RTEN12                                            EINT_RTEN_RTEN12_Msk                                           /*!< Rising trigger event configuration bit of line 12 */
#define EINT_RTEN_RTEN13_Pos                                        (13U)
#define EINT_RTEN_RTEN13_Msk                                        (0x1UL << EINT_RTEN_RTEN13_Pos)                                /*!< 0x00002000 */
#define EINT_RTEN_RTEN13                                            EINT_RTEN_RTEN13_Msk                                           /*!< Rising trigger event configuration bit of line 13 */
#define EINT_RTEN_RTEN14_Pos                                        (14U)
#define EINT_RTEN_RTEN14_Msk                                        (0x1UL << EINT_RTEN_RTEN14_Pos)                                /*!< 0x00004000 */
#define EINT_RTEN_RTEN14                                            EINT_RTEN_RTEN14_Msk                                           /*!< Rising trigger event configuration bit of line 14 */
#define EINT_RTEN_RTEN15_Pos                                        (15U)
#define EINT_RTEN_RTEN15_Msk                                        (0x1UL << EINT_RTEN_RTEN15_Pos)                                /*!< 0x00008000 */
#define EINT_RTEN_RTEN15                                            EINT_RTEN_RTEN15_Msk                                           /*!< Rising trigger event configuration bit of line 15 */
#define EINT_RTEN_RTEN16_Pos                                        (16U)
#define EINT_RTEN_RTEN16_Msk                                        (0x1UL << EINT_RTEN_RTEN16_Pos)                                /*!< 0x00010000 */
#define EINT_RTEN_RTEN16                                            EINT_RTEN_RTEN16_Msk                                           /*!< Rising trigger event configuration bit of line 16 */
#define EINT_RTEN_RTEN17_Pos                                        (17U)
#define EINT_RTEN_RTEN17_Msk                                        (0x1UL << EINT_RTEN_RTEN17_Pos)                                /*!< 0x00020000 */
#define EINT_RTEN_RTEN17                                            EINT_RTEN_RTEN17_Msk                                           /*!< Rising trigger event configuration bit of line 17 */
#define EINT_RTEN_RTEN18_Pos                                        (18U)
#define EINT_RTEN_RTEN18_Msk                                        (0x1UL << EINT_RTEN_RTEN18_Pos)                                /*!< 0x00040000 */
#define EINT_RTEN_RTEN18                                            EINT_RTEN_RTEN18_Msk                                           /*!< Rising trigger event configuration bit of line 18 */
#define EINT_RTEN_RTEN19_Pos                                        (19U)
#define EINT_RTEN_RTEN19_Msk                                        (0x1UL << EINT_RTEN_RTEN19_Pos)                                /*!< 0x00080000 */
#define EINT_RTEN_RTEN19                                            EINT_RTEN_RTEN19_Msk                                           /*!< Rising trigger event configuration bit of line 19 */
#define EINT_RTEN_RTEN20_Pos                                        (20U)
#define EINT_RTEN_RTEN20_Msk                                        (0x1UL << EINT_RTEN_RTEN20_Pos)                                /*!< 0x00100000 */
#define EINT_RTEN_RTEN20                                            EINT_RTEN_RTEN20_Msk                                           /*!< Rising trigger event configuration bit of line 20 */
#define EINT_RTEN_RTEN21_Pos                                        (21U)
#define EINT_RTEN_RTEN21_Msk                                        (0x1UL << EINT_RTEN_RTEN21_Pos)                                /*!< 0x00200000 */
#define EINT_RTEN_RTEN21                                            EINT_RTEN_RTEN21_Msk                                           /*!< Rising trigger event configuration bit of line 21 */
#define EINT_RTEN_RTEN22_Pos                                        (22U)
#define EINT_RTEN_RTEN22_Msk                                        (0x1UL << EINT_RTEN_RTEN22_Pos)                                /*!< 0x00400000 */
#define EINT_RTEN_RTEN22                                            EINT_RTEN_RTEN22_Msk                                           /*!< Rising trigger event configuration bit of line 22 */

/******************  Bit definition for EINT_FTEN register  *******************/
#define EINT_FTEN_FTEN0_Pos                                         (0U)
#define EINT_FTEN_FTEN0_Msk                                         (0x1UL << EINT_FTEN_FTEN0_Pos)                                 /*!< 0x00000001 */
#define EINT_FTEN_FTEN0                                             EINT_FTEN_FTEN0_Msk                                            /*!< Falling trigger event configuration bit of line 0 */
#define EINT_FTEN_FTEN1_Pos                                         (1U)
#define EINT_FTEN_FTEN1_Msk                                         (0x1UL << EINT_FTEN_FTEN1_Pos)                                 /*!< 0x00000002 */
#define EINT_FTEN_FTEN1                                             EINT_FTEN_FTEN1_Msk                                            /*!< Falling trigger event configuration bit of line 1 */
#define EINT_FTEN_FTEN2_Pos                                         (2U)
#define EINT_FTEN_FTEN2_Msk                                         (0x1UL << EINT_FTEN_FTEN2_Pos)                                 /*!< 0x00000004 */
#define EINT_FTEN_FTEN2                                             EINT_FTEN_FTEN2_Msk                                            /*!< Falling trigger event configuration bit of line 2 */
#define EINT_FTEN_FTEN3_Pos                                         (3U)
#define EINT_FTEN_FTEN3_Msk                                         (0x1UL << EINT_FTEN_FTEN3_Pos)                                 /*!< 0x00000008 */
#define EINT_FTEN_FTEN3                                             EINT_FTEN_FTEN3_Msk                                            /*!< Falling trigger event configuration bit of line 3 */
#define EINT_FTEN_FTEN4_Pos                                         (4U)
#define EINT_FTEN_FTEN4_Msk                                         (0x1UL << EINT_FTEN_FTEN4_Pos)                                 /*!< 0x00000010 */
#define EINT_FTEN_FTEN4                                             EINT_FTEN_FTEN4_Msk                                            /*!< Falling trigger event configuration bit of line 4 */
#define EINT_FTEN_FTEN5_Pos                                         (5U)
#define EINT_FTEN_FTEN5_Msk                                         (0x1UL << EINT_FTEN_FTEN5_Pos)                                 /*!< 0x00000020 */
#define EINT_FTEN_FTEN5                                             EINT_FTEN_FTEN5_Msk                                            /*!< Falling trigger event configuration bit of line 5 */
#define EINT_FTEN_FTEN6_Pos                                         (6U)
#define EINT_FTEN_FTEN6_Msk                                         (0x1UL << EINT_FTEN_FTEN6_Pos)                                 /*!< 0x00000040 */
#define EINT_FTEN_FTEN6                                             EINT_FTEN_FTEN6_Msk                                            /*!< Falling trigger event configuration bit of line 6 */
#define EINT_FTEN_FTEN7_Pos                                         (7U)
#define EINT_FTEN_FTEN7_Msk                                         (0x1UL << EINT_FTEN_FTEN7_Pos)                                 /*!< 0x00000080 */
#define EINT_FTEN_FTEN7                                             EINT_FTEN_FTEN7_Msk                                            /*!< Falling trigger event configuration bit of line 7 */
#define EINT_FTEN_FTEN8_Pos                                         (8U)
#define EINT_FTEN_FTEN8_Msk                                         (0x1UL << EINT_FTEN_FTEN8_Pos)                                 /*!< 0x00000100 */
#define EINT_FTEN_FTEN8                                             EINT_FTEN_FTEN8_Msk                                            /*!< Falling trigger event configuration bit of line 8 */
#define EINT_FTEN_FTEN9_Pos                                         (9U)
#define EINT_FTEN_FTEN9_Msk                                         (0x1UL << EINT_FTEN_FTEN9_Pos)                                 /*!< 0x00000200 */
#define EINT_FTEN_FTEN9                                             EINT_FTEN_FTEN9_Msk                                            /*!< Falling trigger event configuration bit of line 9 */
#define EINT_FTEN_FTEN10_Pos                                        (10U)
#define EINT_FTEN_FTEN10_Msk                                        (0x1UL << EINT_FTEN_FTEN10_Pos)                                /*!< 0x00000400 */
#define EINT_FTEN_FTEN10                                            EINT_FTEN_FTEN10_Msk                                           /*!< Falling trigger event configuration bit of line 10 */
#define EINT_FTEN_FTEN11_Pos                                        (11U)
#define EINT_FTEN_FTEN11_Msk                                        (0x1UL << EINT_FTEN_FTEN11_Pos)                                /*!< 0x00000800 */
#define EINT_FTEN_FTEN11                                            EINT_FTEN_FTEN11_Msk                                           /*!< Falling trigger event configuration bit of line 11 */
#define EINT_FTEN_FTEN12_Pos                                        (12U)
#define EINT_FTEN_FTEN12_Msk                                        (0x1UL << EINT_FTEN_FTEN12_Pos)                                /*!< 0x00001000 */
#define EINT_FTEN_FTEN12                                            EINT_FTEN_FTEN12_Msk                                           /*!< Falling trigger event configuration bit of line 12 */
#define EINT_FTEN_FTEN13_Pos                                        (13U)
#define EINT_FTEN_FTEN13_Msk                                        (0x1UL << EINT_FTEN_FTEN13_Pos)                                /*!< 0x00002000 */
#define EINT_FTEN_FTEN13                                            EINT_FTEN_FTEN13_Msk                                           /*!< Falling trigger event configuration bit of line 13 */
#define EINT_FTEN_FTEN14_Pos                                        (14U)
#define EINT_FTEN_FTEN14_Msk                                        (0x1UL << EINT_FTEN_FTEN14_Pos)                                /*!< 0x00004000 */
#define EINT_FTEN_FTEN14                                            EINT_FTEN_FTEN14_Msk                                           /*!< Falling trigger event configuration bit of line 14 */
#define EINT_FTEN_FTEN15_Pos                                        (15U)
#define EINT_FTEN_FTEN15_Msk                                        (0x1UL << EINT_FTEN_FTEN15_Pos)                                /*!< 0x00008000 */
#define EINT_FTEN_FTEN15                                            EINT_FTEN_FTEN15_Msk                                           /*!< Falling trigger event configuration bit of line 15 */
#define EINT_FTEN_FTEN16_Pos                                        (16U)
#define EINT_FTEN_FTEN16_Msk                                        (0x1UL << EINT_FTEN_FTEN16_Pos)                                /*!< 0x00010000 */
#define EINT_FTEN_FTEN16                                            EINT_FTEN_FTEN16_Msk                                           /*!< Falling trigger event configuration bit of line 16 */
#define EINT_FTEN_FTEN17_Pos                                        (17U)
#define EINT_FTEN_FTEN17_Msk                                        (0x1UL << EINT_FTEN_FTEN17_Pos)                                /*!< 0x00020000 */
#define EINT_FTEN_FTEN17                                            EINT_FTEN_FTEN17_Msk                                           /*!< Falling trigger event configuration bit of line 17 */
#define EINT_FTEN_FTEN18_Pos                                        (18U)
#define EINT_FTEN_FTEN18_Msk                                        (0x1UL << EINT_FTEN_FTEN18_Pos)                                /*!< 0x00040000 */
#define EINT_FTEN_FTEN18                                            EINT_FTEN_FTEN18_Msk                                           /*!< Falling trigger event configuration bit of line 18 */
#define EINT_FTEN_FTEN19_Pos                                        (19U)
#define EINT_FTEN_FTEN19_Msk                                        (0x1UL << EINT_FTEN_FTEN19_Pos)                                /*!< 0x00080000 */
#define EINT_FTEN_FTEN19                                            EINT_FTEN_FTEN19_Msk                                           /*!< Falling trigger event configuration bit of line 19 */
#define EINT_FTEN_FTEN20_Pos                                        (20U)
#define EINT_FTEN_FTEN20_Msk                                        (0x1UL << EINT_FTEN_FTEN20_Pos)                                /*!< 0x00100000 */
#define EINT_FTEN_FTEN20                                            EINT_FTEN_FTEN20_Msk                                           /*!< Falling trigger event configuration bit of line 20 */
#define EINT_FTEN_FTEN21_Pos                                        (21U)
#define EINT_FTEN_FTEN21_Msk                                        (0x1UL << EINT_FTEN_FTEN21_Pos)                                /*!< 0x00200000 */
#define EINT_FTEN_FTEN21                                            EINT_FTEN_FTEN21_Msk                                           /*!< Falling trigger event configuration bit of line 21 */
#define EINT_FTEN_FTEN22_Pos                                        (22U)
#define EINT_FTEN_FTEN22_Msk                                        (0x1UL << EINT_FTEN_FTEN22_Pos)                                /*!< 0x00400000 */
#define EINT_FTEN_FTEN22                                            EINT_FTEN_FTEN22_Msk                                           /*!< Falling trigger event configuration bit of line 22 */

/******************  Bit definition for EINT_SWINTE register  ******************/
#define EINT_SWINTE_SWINTE0_Pos                                     (0U)
#define EINT_SWINTE_SWINTE0_Msk                                     (0x1UL << EINT_SWINTE_SWINTE0_Pos)                             /*!< 0x00000001 */
#define EINT_SWINTE_SWINTE0                                         EINT_SWINTE_SWINTE0_Msk                                        /*!< Software Interrupt on line 0 */
#define EINT_SWINTE_SWINTE1_Pos                                     (1U)
#define EINT_SWINTE_SWINTE1_Msk                                     (0x1UL << EINT_SWINTE_SWINTE1_Pos)                             /*!< 0x00000002 */
#define EINT_SWINTE_SWINTE1                                         EINT_SWINTE_SWINTE1_Msk                                        /*!< Software Interrupt on line 1 */
#define EINT_SWINTE_SWINTE2_Pos                                     (2U)
#define EINT_SWINTE_SWINTE2_Msk                                     (0x1UL << EINT_SWINTE_SWINTE2_Pos)                             /*!< 0x00000004 */
#define EINT_SWINTE_SWINTE2                                         EINT_SWINTE_SWINTE2_Msk                                        /*!< Software Interrupt on line 2 */
#define EINT_SWINTE_SWINTE3_Pos                                     (3U)
#define EINT_SWINTE_SWINTE3_Msk                                     (0x1UL << EINT_SWINTE_SWINTE3_Pos)                             /*!< 0x00000008 */
#define EINT_SWINTE_SWINTE3                                         EINT_SWINTE_SWINTE3_Msk                                        /*!< Software Interrupt on line 3 */
#define EINT_SWINTE_SWINTE4_Pos                                     (4U)
#define EINT_SWINTE_SWINTE4_Msk                                     (0x1UL << EINT_SWINTE_SWINTE4_Pos)                             /*!< 0x00000010 */
#define EINT_SWINTE_SWINTE4                                         EINT_SWINTE_SWINTE4_Msk                                        /*!< Software Interrupt on line 4 */
#define EINT_SWINTE_SWINTE5_Pos                                     (5U)
#define EINT_SWINTE_SWINTE5_Msk                                     (0x1UL << EINT_SWINTE_SWINTE5_Pos)                             /*!< 0x00000020 */
#define EINT_SWINTE_SWINTE5                                         EINT_SWINTE_SWINTE5_Msk                                        /*!< Software Interrupt on line 5 */
#define EINT_SWINTE_SWINTE6_Pos                                     (6U)
#define EINT_SWINTE_SWINTE6_Msk                                     (0x1UL << EINT_SWINTE_SWINTE6_Pos)                             /*!< 0x00000040 */
#define EINT_SWINTE_SWINTE6                                         EINT_SWINTE_SWINTE6_Msk                                        /*!< Software Interrupt on line 6 */
#define EINT_SWINTE_SWINTE7_Pos                                     (7U)
#define EINT_SWINTE_SWINTE7_Msk                                     (0x1UL << EINT_SWINTE_SWINTE7_Pos)                             /*!< 0x00000080 */
#define EINT_SWINTE_SWINTE7                                         EINT_SWINTE_SWINTE7_Msk                                        /*!< Software Interrupt on line 7 */
#define EINT_SWINTE_SWINTE8_Pos                                     (8U)
#define EINT_SWINTE_SWINTE8_Msk                                     (0x1UL << EINT_SWINTE_SWINTE8_Pos)                             /*!< 0x00000100 */
#define EINT_SWINTE_SWINTE8                                         EINT_SWINTE_SWINTE8_Msk                                        /*!< Software Interrupt on line 8 */
#define EINT_SWINTE_SWINTE9_Pos                                     (9U)
#define EINT_SWINTE_SWINTE9_Msk                                     (0x1UL << EINT_SWINTE_SWINTE9_Pos)                             /*!< 0x00000200 */
#define EINT_SWINTE_SWINTE9                                         EINT_SWINTE_SWINTE9_Msk                                        /*!< Software Interrupt on line 9 */
#define EINT_SWINTE_SWINTE10_Pos                                    (10U)
#define EINT_SWINTE_SWINTE10_Msk                                    (0x1UL << EINT_SWINTE_SWINTE10_Pos)                            /*!< 0x00000400 */
#define EINT_SWINTE_SWINTE10                                        EINT_SWINTE_SWINTE10_Msk                                       /*!< Software Interrupt on line 10 */
#define EINT_SWINTE_SWINTE11_Pos                                    (11U)
#define EINT_SWINTE_SWINTE11_Msk                                    (0x1UL << EINT_SWINTE_SWINTE11_Pos)                            /*!< 0x00000800 */
#define EINT_SWINTE_SWINTE11                                        EINT_SWINTE_SWINTE11_Msk                                       /*!< Software Interrupt on line 11 */
#define EINT_SWINTE_SWINTE12_Pos                                    (12U)
#define EINT_SWINTE_SWINTE12_Msk                                    (0x1UL << EINT_SWINTE_SWINTE12_Pos)                            /*!< 0x00001000 */
#define EINT_SWINTE_SWINTE12                                        EINT_SWINTE_SWINTE12_Msk                                       /*!< Software Interrupt on line 12 */
#define EINT_SWINTE_SWINTE13_Pos                                    (13U)
#define EINT_SWINTE_SWINTE13_Msk                                    (0x1UL << EINT_SWINTE_SWINTE13_Pos)                            /*!< 0x00002000 */
#define EINT_SWINTE_SWINTE13                                        EINT_SWINTE_SWINTE13_Msk                                       /*!< Software Interrupt on line 13 */
#define EINT_SWINTE_SWINTE14_Pos                                    (14U)
#define EINT_SWINTE_SWINTE14_Msk                                    (0x1UL << EINT_SWINTE_SWINTE14_Pos)                            /*!< 0x00004000 */
#define EINT_SWINTE_SWINTE14                                        EINT_SWINTE_SWINTE14_Msk                                       /*!< Software Interrupt on line 14 */
#define EINT_SWINTE_SWINTE15_Pos                                    (15U)
#define EINT_SWINTE_SWINTE15_Msk                                    (0x1UL << EINT_SWINTE_SWINTE15_Pos)                            /*!< 0x00008000 */
#define EINT_SWINTE_SWINTE15                                        EINT_SWINTE_SWINTE15_Msk                                       /*!< Software Interrupt on line 15 */
#define EINT_SWINTE_SWINTE16_Pos                                    (16U)
#define EINT_SWINTE_SWINTE16_Msk                                    (0x1UL << EINT_SWINTE_SWINTE16_Pos)                            /*!< 0x00010000 */
#define EINT_SWINTE_SWINTE16                                        EINT_SWINTE_SWINTE16_Msk                                       /*!< Software Interrupt on line 16 */
#define EINT_SWINTE_SWINTE17_Pos                                    (17U)
#define EINT_SWINTE_SWINTE17_Msk                                    (0x1UL << EINT_SWINTE_SWINTE17_Pos)                            /*!< 0x00020000 */
#define EINT_SWINTE_SWINTE17                                        EINT_SWINTE_SWINTE17_Msk                                       /*!< Software Interrupt on line 17 */
#define EINT_SWINTE_SWINTE18_Pos                                    (18U)
#define EINT_SWINTE_SWINTE18_Msk                                    (0x1UL << EINT_SWINTE_SWINTE18_Pos)                            /*!< 0x00040000 */
#define EINT_SWINTE_SWINTE18                                        EINT_SWINTE_SWINTE18_Msk                                       /*!< Software Interrupt on line 18 */
#define EINT_SWINTE_SWINTE19_Pos                                    (19U)
#define EINT_SWINTE_SWINTE19_Msk                                    (0x1UL << EINT_SWINTE_SWINTE19_Pos)                            /*!< 0x00080000 */
#define EINT_SWINTE_SWINTE19                                        EINT_SWINTE_SWINTE19_Msk                                       /*!< Software Interrupt on line 19 */
#define EINT_SWINTE_SWINTE20_Pos                                    (20U)
#define EINT_SWINTE_SWINTE20_Msk                                    (0x1UL << EINT_SWINTE_SWINTE20_Pos)                            /*!< 0x00100000 */
#define EINT_SWINTE_SWINTE20                                        EINT_SWINTE_SWINTE20_Msk                                       /*!< Software Interrupt on line 20 */
#define EINT_SWINTE_SWINTE21_Pos                                    (21U)
#define EINT_SWINTE_SWINTE21_Msk                                    (0x1UL << EINT_SWINTE_SWINTE21_Pos)                            /*!< 0x00200000 */
#define EINT_SWINTE_SWINTE21                                        EINT_SWINTE_SWINTE21_Msk                                       /*!< Software Interrupt on line 21 */
#define EINT_SWINTE_SWINTE22_Pos                                    (22U)
#define EINT_SWINTE_SWINTE22_Msk                                    (0x1UL << EINT_SWINTE_SWINTE22_Pos)                            /*!< 0x00400000 */
#define EINT_SWINTE_SWINTE22                                        EINT_SWINTE_SWINTE22_Msk                                       /*!< Software Interrupt on line 22 */

/*******************  Bit definition for EINT_IPEND register  ********************/
#define EINT_IPEND_IPEND0_Pos                                       (0U)
#define EINT_IPEND_IPEND0_Msk                                       (0x1UL << EINT_IPEND_IPEND0_Pos)                               /*!< 0x00000001 */
#define EINT_IPEND_IPEND0                                           EINT_IPEND_IPEND0_Msk                                          /*!< Pending bit for line 0 */
#define EINT_IPEND_IPEND1_Pos                                       (1U)
#define EINT_IPEND_IPEND1_Msk                                       (0x1UL << EINT_IPEND_IPEND1_Pos)                               /*!< 0x00000002 */
#define EINT_IPEND_IPEND1                                           EINT_IPEND_IPEND1_Msk                                          /*!< Pending bit for line 1 */
#define EINT_IPEND_IPEND2_Pos                                       (2U)
#define EINT_IPEND_IPEND2_Msk                                       (0x1UL << EINT_IPEND_IPEND2_Pos)                               /*!< 0x00000004 */
#define EINT_IPEND_IPEND2                                           EINT_IPEND_IPEND2_Msk                                          /*!< Pending bit for line 2 */
#define EINT_IPEND_IPEND3_Pos                                       (3U)
#define EINT_IPEND_IPEND3_Msk                                       (0x1UL << EINT_IPEND_IPEND3_Pos)                               /*!< 0x00000008 */
#define EINT_IPEND_IPEND3                                           EINT_IPEND_IPEND3_Msk                                          /*!< Pending bit for line 3 */
#define EINT_IPEND_IPEND4_Pos                                       (4U)
#define EINT_IPEND_IPEND4_Msk                                       (0x1UL << EINT_IPEND_IPEND4_Pos)                               /*!< 0x00000010 */
#define EINT_IPEND_IPEND4                                           EINT_IPEND_IPEND4_Msk                                          /*!< Pending bit for line 4 */
#define EINT_IPEND_IPEND5_Pos                                       (5U)
#define EINT_IPEND_IPEND5_Msk                                       (0x1UL << EINT_IPEND_IPEND5_Pos)                               /*!< 0x00000020 */
#define EINT_IPEND_IPEND5                                           EINT_IPEND_IPEND5_Msk                                          /*!< Pending bit for line 5 */
#define EINT_IPEND_IPEND6_Pos                                       (6U)
#define EINT_IPEND_IPEND6_Msk                                       (0x1UL << EINT_IPEND_IPEND6_Pos)                               /*!< 0x00000040 */
#define EINT_IPEND_IPEND6                                           EINT_IPEND_IPEND6_Msk                                          /*!< Pending bit for line 6 */
#define EINT_IPEND_IPEND7_Pos                                       (7U)
#define EINT_IPEND_IPEND7_Msk                                       (0x1UL << EINT_IPEND_IPEND7_Pos)                               /*!< 0x00000080 */
#define EINT_IPEND_IPEND7                                           EINT_IPEND_IPEND7_Msk                                          /*!< Pending bit for line 7 */
#define EINT_IPEND_IPEND8_Pos                                       (8U)
#define EINT_IPEND_IPEND8_Msk                                       (0x1UL << EINT_IPEND_IPEND8_Pos)                               /*!< 0x00000100 */
#define EINT_IPEND_IPEND8                                           EINT_IPEND_IPEND8_Msk                                          /*!< Pending bit for line 8 */
#define EINT_IPEND_IPEND9_Pos                                       (9U)
#define EINT_IPEND_IPEND9_Msk                                       (0x1UL << EINT_IPEND_IPEND9_Pos)                               /*!< 0x00000200 */
#define EINT_IPEND_IPEND9                                           EINT_IPEND_IPEND9_Msk                                          /*!< Pending bit for line 9 */
#define EINT_IPEND_IPEND10_Pos                                      (10U)
#define EINT_IPEND_IPEND10_Msk                                      (0x1UL << EINT_IPEND_IPEND10_Pos)                              /*!< 0x00000400 */
#define EINT_IPEND_IPEND10                                          EINT_IPEND_IPEND10_Msk                                         /*!< Pending bit for line 10 */
#define EINT_IPEND_IPEND11_Pos                                      (11U)
#define EINT_IPEND_IPEND11_Msk                                      (0x1UL << EINT_IPEND_IPEND11_Pos)                              /*!< 0x00000800 */
#define EINT_IPEND_IPEND11                                          EINT_IPEND_IPEND11_Msk                                         /*!< Pending bit for line 11 */
#define EINT_IPEND_IPEND12_Pos                                      (12U)
#define EINT_IPEND_IPEND12_Msk                                      (0x1UL << EINT_IPEND_IPEND12_Pos)                              /*!< 0x00001000 */
#define EINT_IPEND_IPEND12                                          EINT_IPEND_IPEND12_Msk                                         /*!< Pending bit for line 12 */
#define EINT_IPEND_IPEND13_Pos                                      (13U)
#define EINT_IPEND_IPEND13_Msk                                      (0x1UL << EINT_IPEND_IPEND13_Pos)                              /*!< 0x00002000 */
#define EINT_IPEND_IPEND13                                          EINT_IPEND_IPEND13_Msk                                         /*!< Pending bit for line 13 */
#define EINT_IPEND_IPEND14_Pos                                      (14U)
#define EINT_IPEND_IPEND14_Msk                                      (0x1UL << EINT_IPEND_IPEND14_Pos)                              /*!< 0x00004000 */
#define EINT_IPEND_IPEND14                                          EINT_IPEND_IPEND14_Msk                                         /*!< Pending bit for line 14 */
#define EINT_IPEND_IPEND15_Pos                                      (15U)
#define EINT_IPEND_IPEND15_Msk                                      (0x1UL << EINT_IPEND_IPEND15_Pos)                              /*!< 0x00008000 */
#define EINT_IPEND_IPEND15                                          EINT_IPEND_IPEND15_Msk                                         /*!< Pending bit for line 15 */
#define EINT_IPEND_IPEND16_Pos                                      (16U)
#define EINT_IPEND_IPEND16_Msk                                      (0x1UL << EINT_IPEND_IPEND16_Pos)                              /*!< 0x00010000 */
#define EINT_IPEND_IPEND16                                          EINT_IPEND_IPEND16_Msk                                         /*!< Pending bit for line 16 */
#define EINT_IPEND_IPEND17_Pos                                      (17U)
#define EINT_IPEND_IPEND17_Msk                                      (0x1UL << EINT_IPEND_IPEND17_Pos)                              /*!< 0x00020000 */
#define EINT_IPEND_IPEND17                                          EINT_IPEND_IPEND17_Msk                                         /*!< Pending bit for line 17 */
#define EINT_IPEND_IPEND18_Pos                                      (18U)
#define EINT_IPEND_IPEND18_Msk                                      (0x1UL << EINT_IPEND_IPEND18_Pos)                              /*!< 0x00040000 */
#define EINT_IPEND_IPEND18                                          EINT_IPEND_IPEND18_Msk                                         /*!< Pending bit for line 18 */
#define EINT_IPEND_IPEND19_Pos                                      (19U)
#define EINT_IPEND_IPEND19_Msk                                      (0x1UL << EINT_IPEND_IPEND19_Pos)                              /*!< 0x00080000 */
#define EINT_IPEND_IPEND19                                          EINT_IPEND_IPEND19_Msk                                         /*!< Pending bit for line 19 */
#define EINT_IPEND_IPEND20_Pos                                      (20U)
#define EINT_IPEND_IPEND20_Msk                                      (0x1UL << EINT_IPEND_IPEND20_Pos)                              /*!< 0x00100000 */
#define EINT_IPEND_IPEND20                                          EINT_IPEND_IPEND20_Msk                                         /*!< Pending bit for line 20 */
#define EINT_IPEND_IPEND21_Pos                                      (21U)
#define EINT_IPEND_IPEND21_Msk                                      (0x1UL << EINT_IPEND_IPEND21_Pos)                              /*!< 0x00200000 */
#define EINT_IPEND_IPEND21                                          EINT_IPEND_IPEND21_Msk                                         /*!< Pending bit for line 21 */
#define EINT_IPEND_IPEND22_Pos                                      (22U)
#define EINT_IPEND_IPEND22_Msk                                      (0x1UL << EINT_IPEND_IPEND22_Pos)                              /*!< 0x00400000 */
#define EINT_IPEND_IPEND22                                          EINT_IPEND_IPEND22_Msk                                         /*!< Pending bit for line 22 */

/******************************************************************************/
/*                                                                            */
/*                                    FLASH                                   */
/*                                                                            */
/******************************************************************************/
/*******************  Bits definition for FLASH_ACCTRL register  *****************/
#define FLASH_ACCTRL_WAITP_Pos                                      (0U)
#define FLASH_ACCTRL_WAITP_Msk                                      (0x7UL << FLASH_ACCTRL_WAITP_Pos)                              /*!< 0x00000007 */
#define FLASH_ACCTRL_WAITP                                          FLASH_ACCTRL_WAITP_Msk
#define FLASH_ACCTRL_WAITP_0WS                                      0x00000000U
#define FLASH_ACCTRL_WAITP_1WS                                      0x00000001U
#define FLASH_ACCTRL_WAITP_2WS                                      0x00000002U
#define FLASH_ACCTRL_WAITP_3WS                                      0x00000003U
#define FLASH_ACCTRL_WAITP_4WS                                      0x00000004U
#define FLASH_ACCTRL_WAITP_5WS                                      0x00000005U
#define FLASH_ACCTRL_WAITP_6WS                                      0x00000006U
#define FLASH_ACCTRL_WAITP_7WS                                      0x00000007U


#define FLASH_ACCTRL_PREFEN_Pos                                     (8U)
#define FLASH_ACCTRL_PREFEN_Msk                                     (0x1UL << FLASH_ACCTRL_PREFEN_Pos)                             /*!< 0x00000100 */
#define FLASH_ACCTRL_PREFEN                                         FLASH_ACCTRL_PREFEN_Msk
#define FLASH_ACCTRL_ICACHEEN_Pos                                   (9U)
#define FLASH_ACCTRL_ICACHEEN_Msk                                   (0x1UL << FLASH_ACCTRL_ICACHEEN_Pos)                           /*!< 0x00000200 */
#define FLASH_ACCTRL_ICACHEEN                                       FLASH_ACCTRL_ICACHEEN_Msk
#define FLASH_ACCTRL_DCACHEEN_Pos                                   (10U)
#define FLASH_ACCTRL_DCACHEEN_Msk                                   (0x1UL << FLASH_ACCTRL_DCACHEEN_Pos)                           /*!< 0x00000400 */
#define FLASH_ACCTRL_DCACHEEN                                       FLASH_ACCTRL_DCACHEEN_Msk
#define FLASH_ACCTRL_ICACHERST_Pos                                  (11U)
#define FLASH_ACCTRL_ICACHERST_Msk                                  (0x1UL << FLASH_ACCTRL_ICACHERST_Pos)                          /*!< 0x00000800 */
#define FLASH_ACCTRL_ICACHERST                                      FLASH_ACCTRL_ICACHERST_Msk
#define FLASH_ACCTRL_DCACHERST_Pos                                  (12U)
#define FLASH_ACCTRL_DCACHERST_Msk                                  (0x1UL << FLASH_ACCTRL_DCACHERST_Pos)                          /*!< 0x00001000 */
#define FLASH_ACCTRL_DCACHERST                                      FLASH_ACCTRL_DCACHERST_Msk
#define FLASH_ACCTRL_BYTE0_ADDRESS_Pos                              (10U)
#define FLASH_ACCTRL_BYTE0_ADDRESS_Msk                              (0x10008FUL << FLASH_ACCTRL_BYTE0_ADDRESS_Pos)                 /*!< 0x40023C00 */
#define FLASH_ACCTRL_BYTE0_ADDRESS                                  FLASH_ACCTRL_BYTE0_ADDRESS_Msk
#define FLASH_ACCTRL_BYTE2_ADDRESS_Pos                              (0U)
#define FLASH_ACCTRL_BYTE2_ADDRESS_Msk                              (0x40023C03UL << FLASH_ACCTRL_BYTE2_ADDRESS_Pos)               /*!< 0x40023C03 */
#define FLASH_ACCTRL_BYTE2_ADDRESS                                  FLASH_ACCTRL_BYTE2_ADDRESS_Msk

/*******************  Bits definition for FLASH_STS register  ******************/
#define FLASH_STS_OPRCMP_Pos                                        (0U)
#define FLASH_STS_OPRCMP_Msk                                        (0x1UL << FLASH_STS_OPRCMP_Pos)                                /*!< 0x00000001 */
#define FLASH_STS_OPRCMP                                            FLASH_STS_OPRCMP_Msk
#define FLASH_STS_OPRERR_Pos                                        (1U)
#define FLASH_STS_OPRERR_Msk                                        (0x1UL << FLASH_STS_OPRERR_Pos)                                /*!< 0x00000002 */
#define FLASH_STS_OPRERR                                            FLASH_STS_OPRERR_Msk
#define FLASH_STS_WPROTERR_Pos                                      (4U)
#define FLASH_STS_WPROTERR_Msk                                      (0x1UL << FLASH_STS_WPROTERR_Pos)                              /*!< 0x00000010 */
#define FLASH_STS_WPROTERR                                          FLASH_STS_WPROTERR_Msk
#define FLASH_STS_PGALGERR_Pos                                      (5U)
#define FLASH_STS_PGALGERR_Msk                                      (0x1UL << FLASH_STS_PGALGERR_Pos)                              /*!< 0x00000020 */
#define FLASH_STS_PGALGERR                                          FLASH_STS_PGALGERR_Msk
#define FLASH_STS_PGPRLERR_Pos                                      (6U)
#define FLASH_STS_PGPRLERR_Msk                                      (0x1UL << FLASH_STS_PGPRLERR_Pos)                              /*!< 0x00000040 */
#define FLASH_STS_PGPRLERR                                          FLASH_STS_PGPRLERR_Msk
#define FLASH_STS_PGSEQERR_Pos                                      (7U)
#define FLASH_STS_PGSEQERR_Msk                                      (0x1UL << FLASH_STS_PGSEQERR_Pos)                              /*!< 0x00000080 */
#define FLASH_STS_PGSEQERR                                          FLASH_STS_PGSEQERR_Msk
#define FLASH_STS_BUSY_Pos                                          (16U)
#define FLASH_STS_BUSY_Msk                                          (0x1UL << FLASH_STS_BUSY_Pos)                                  /*!< 0x00010000 */
#define FLASH_STS_BUSY                                              FLASH_STS_BUSY_Msk

/*******************  Bits definition for FLASH_CTRL register  ******************/
#define FLASH_CTRL_PG_Pos                                           (0U)
#define FLASH_CTRL_PG_Msk                                           (0x1UL << FLASH_CTRL_PG_Pos)                                   /*!< 0x00000001 */
#define FLASH_CTRL_PG                                               FLASH_CTRL_PG_Msk
#define FLASH_CTRL_SERS_Pos                                         (1U)
#define FLASH_CTRL_SERS_Msk                                         (0x1UL << FLASH_CTRL_SERS_Pos)                                 /*!< 0x00000002 */
#define FLASH_CTRL_SERS                                             FLASH_CTRL_SERS_Msk
#define FLASH_CTRL_MERS_Pos                                         (2U)
#define FLASH_CTRL_MERS_Msk                                         (0x1UL << FLASH_CTRL_MERS_Pos)                                 /*!< 0x00000004 */
#define FLASH_CTRL_MERS                                             FLASH_CTRL_MERS_Msk
#define FLASH_CTRL_SNUM_Pos                                         (3U)
#define FLASH_CTRL_SNUM_Msk                                         (0x1FUL << FLASH_CTRL_SNUM_Pos)                                /*!< 0x000000F8 */
#define FLASH_CTRL_SNUM                                             FLASH_CTRL_SNUM_Msk
#define FLASH_CTRL_SNUM_0                                           (0x01UL << FLASH_CTRL_SNUM_Pos)                                /*!< 0x00000008 */
#define FLASH_CTRL_SNUM_1                                           (0x02UL << FLASH_CTRL_SNUM_Pos)                                /*!< 0x00000010 */
#define FLASH_CTRL_SNUM_2                                           (0x04UL << FLASH_CTRL_SNUM_Pos)                                /*!< 0x00000020 */
#define FLASH_CTRL_SNUM_3                                           (0x08UL << FLASH_CTRL_SNUM_Pos)                                /*!< 0x00000040 */
#define FLASH_CTRL_SNUM_4                                           (0x10UL << FLASH_CTRL_SNUM_Pos)                                /*!< 0x00000080 */
#define FLASH_CTRL_PGSIZE_Pos                                       (8U)
#define FLASH_CTRL_PGSIZE_Msk                                       (0x3UL << FLASH_CTRL_PGSIZE_Pos)                               /*!< 0x00000300 */
#define FLASH_CTRL_PGSIZE                                           FLASH_CTRL_PGSIZE_Msk
#define FLASH_CTRL_PGSIZE_0                                         (0x1UL << FLASH_CTRL_PGSIZE_Pos)                               /*!< 0x00000100 */
#define FLASH_CTRL_PGSIZE_1                                         (0x2UL << FLASH_CTRL_PGSIZE_Pos)                               /*!< 0x00000200 */
#define FLASH_CTRL_START_Pos                                        (16U)
#define FLASH_CTRL_START_Msk                                        (0x1UL << FLASH_CTRL_START_Pos)                                /*!< 0x00010000 */
#define FLASH_CTRL_START                                            FLASH_CTRL_START_Msk
#define FLASH_CTRL_OPCINTEN_Pos                                     (24U)
#define FLASH_CTRL_OPCINTEN_Msk                                     (0x1UL << FLASH_CTRL_OPCINTEN_Pos)                             /*!< 0x01000000 */
#define FLASH_CTRL_OPCINTEN                                         FLASH_CTRL_OPCINTEN_Msk
#define FLASH_CTRL_ERRINTEN_Pos                                     (25U)
#define FLASH_CTRL_ERRINTEN_Msk                                     (0x1UL << FLASH_CTRL_ERRINTEN_Pos)
#define FLASH_CTRL_ERRINTEN                                         FLASH_CTRL_ERRINTEN_Msk
#define FLASH_CTRL_LOCK_Pos                                         (31U)
#define FLASH_CTRL_LOCK_Msk                                         (0x1UL << FLASH_CTRL_LOCK_Pos)                                 /*!< 0x80000000 */
#define FLASH_CTRL_LOCK                                             FLASH_CTRL_LOCK_Msk

/*******************  Bits definition for FLASH_OPTCTRL register  ***************/
#define FLASH_OPTCTRL_OPTLOCK_Pos                                   (0U)
#define FLASH_OPTCTRL_OPTLOCK_Msk                                   (0x1UL << FLASH_OPTCTRL_OPTLOCK_Pos)                           /*!< 0x00000001 */
#define FLASH_OPTCTRL_OPTLOCK                                       FLASH_OPTCTRL_OPTLOCK_Msk
#define FLASH_OPTCTRL_OPTSTART_Pos                                  (1U)
#define FLASH_OPTCTRL_OPTSTART_Msk                                  (0x1UL << FLASH_OPTCTRL_OPTSTART_Pos)                          /*!< 0x00000002 */
#define FLASH_OPTCTRL_OPTSTART                                      FLASH_OPTCTRL_OPTSTART_Msk

#define FLASH_OPTCTRL_BORLVL_0                                      0x00000004U
#define FLASH_OPTCTRL_BORLVL_1                                      0x00000008U
#define FLASH_OPTCTRL_BORLVL_Pos                                    (2U)
#define FLASH_OPTCTRL_BORLVL_Msk                                    (0x3UL << FLASH_OPTCTRL_BORLVL_Pos)                            /*!< 0x0000000C */
#define FLASH_OPTCTRL_BORLVL                                        FLASH_OPTCTRL_BORLVL_Msk
#define FLASH_OPTCTRL_WDTSEL_Pos                                    (5U)
#define FLASH_OPTCTRL_WDTSEL_Msk                                    (0x1UL << FLASH_OPTCTRL_WDTSEL_Pos)                            /*!< 0x00000020 */
#define FLASH_OPTCTRL_WDTSEL                                        FLASH_OPTCTRL_WDTSEL_Msk
#define FLASH_OPTCTRL_RSTSTOP_Pos                                   (6U)
#define FLASH_OPTCTRL_RSTSTOP_Msk                                   (0x1UL << FLASH_OPTCTRL_RSTSTOP_Pos)                           /*!< 0x00000040 */
#define FLASH_OPTCTRL_RSTSTOP                                       FLASH_OPTCTRL_RSTSTOP_Msk
#define FLASH_OPTCTRL_RSTSTDB_Pos                                   (7U)
#define FLASH_OPTCTRL_RSTSTDB_Msk                                   (0x1UL << FLASH_OPTCTRL_RSTSTDB_Pos)                           /*!< 0x00000080 */
#define FLASH_OPTCTRL_RSTSTDB                                       FLASH_OPTCTRL_RSTSTDB_Msk
#define FLASH_OPTCTRL_RPROT_Pos                                     (8U)
#define FLASH_OPTCTRL_RPROT_Msk                                     (0xFFUL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x0000FF00 */
#define FLASH_OPTCTRL_RPROT                                         FLASH_OPTCTRL_RPROT_Msk
#define FLASH_OPTCTRL_RPROT_0                                       (0x01UL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x00000100 */
#define FLASH_OPTCTRL_RPROT_1                                       (0x02UL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x00000200 */
#define FLASH_OPTCTRL_RPROT_2                                       (0x04UL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x00000400 */
#define FLASH_OPTCTRL_RPROT_3                                       (0x08UL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x00000800 */
#define FLASH_OPTCTRL_RPROT_4                                       (0x10UL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x00001000 */
#define FLASH_OPTCTRL_RPROT_5                                       (0x20UL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x00002000 */
#define FLASH_OPTCTRL_RPROT_6                                       (0x40UL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x00004000 */
#define FLASH_OPTCTRL_RPROT_7                                       (0x80UL << FLASH_OPTCTRL_RPROT_Pos)                            /*!< 0x00008000 */
#define FLASH_OPTCTRL_NWPROT_Pos                                    (16U)
#define FLASH_OPTCTRL_NWPROT_Msk                                    (0xFFFUL << FLASH_OPTCTRL_NWPROT_Pos)                          /*!< 0x0FFF0000 */
#define FLASH_OPTCTRL_NWPROT                                        FLASH_OPTCTRL_NWPROT_Msk
#define FLASH_OPTCTRL_NWPROT_0                                      0x00010000U
#define FLASH_OPTCTRL_NWPROT_1                                      0x00020000U
#define FLASH_OPTCTRL_NWPROT_2                                      0x00040000U
#define FLASH_OPTCTRL_NWPROT_3                                      0x00080000U
#define FLASH_OPTCTRL_NWPROT_4                                      0x00100000U
#define FLASH_OPTCTRL_NWPROT_5                                      0x00200000U
#define FLASH_OPTCTRL_NWPROT_6                                      0x00400000U
#define FLASH_OPTCTRL_NWPROT_7                                      0x00800000U
#define FLASH_OPTCTRL_NWPROT_8                                      0x01000000U
#define FLASH_OPTCTRL_NWPROT_9                                      0x02000000U
#define FLASH_OPTCTRL_NWPROT_10                                     0x04000000U
#define FLASH_OPTCTRL_NWPROT_11                                     0x08000000U
                                             
/******************  Bits definition for FLASH_OPTCTRL1 register  ***************/
#define FLASH_OPTCTRL1_NWPROT_Pos                                   (16U)
#define FLASH_OPTCTRL1_NWPROT_Msk                                   (0xFFFUL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x0FFF0000 */
#define FLASH_OPTCTRL1_NWPROT                                       FLASH_OPTCTRL1_NWPROT_Msk
#define FLASH_OPTCTRL1_NWPROT_0                                     (0x001UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x00010000 */
#define FLASH_OPTCTRL1_NWPROT_1                                     (0x002UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x00020000 */
#define FLASH_OPTCTRL1_NWPROT_2                                     (0x004UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x00040000 */
#define FLASH_OPTCTRL1_NWPROT_3                                     (0x008UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x00080000 */
#define FLASH_OPTCTRL1_NWPROT_4                                     (0x010UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x00100000 */
#define FLASH_OPTCTRL1_NWPROT_5                                     (0x020UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x00200000 */
#define FLASH_OPTCTRL1_NWPROT_6                                     (0x040UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x00400000 */
#define FLASH_OPTCTRL1_NWPROT_7                                     (0x080UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x00800000 */
#define FLASH_OPTCTRL1_NWPROT_8                                     (0x100UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x01000000 */
#define FLASH_OPTCTRL1_NWPROT_9                                     (0x200UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x02000000 */
#define FLASH_OPTCTRL1_NWPROT_10                                    (0x400UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x04000000 */
#define FLASH_OPTCTRL1_NWPROT_11                                    (0x800UL << FLASH_OPTCTRL1_NWPROT_Pos)                         /*!< 0x08000000 */

/******************************************************************************/
/*                                                                            */
/*                   Flexible Static Memory Controller                        */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for SMC_CSCTRL1 register  *******************/
#define SMC_CSCTRL1_MBKEN_Pos                                       (0U)
#define SMC_CSCTRL1_MBKEN_Msk                                       (0x1UL << SMC_CSCTRL1_MBKEN_Pos)                               /*!< 0x00000001 */
#define SMC_CSCTRL1_MBKEN                                           SMC_CSCTRL1_MBKEN_Msk                                          /*!<Memory bank enable bit                 */
#define SMC_CSCTRL1_ADMUXEN_Pos                                     (1U)
#define SMC_CSCTRL1_ADMUXEN_Msk                                     (0x1UL << SMC_CSCTRL1_ADMUXEN_Pos)                             /*!< 0x00000002 */
#define SMC_CSCTRL1_ADMUXEN                                         SMC_CSCTRL1_ADMUXEN_Msk                                        /*!<Address/data multiplexing enable bit   */

#define SMC_CSCTRL1_MTYPECFG_Pos                                    (2U)
#define SMC_CSCTRL1_MTYPECFG_Msk                                    (0x3UL << SMC_CSCTRL1_MTYPECFG_Pos)                            /*!< 0x0000000C */
#define SMC_CSCTRL1_MTYPECFG                                        SMC_CSCTRL1_MTYPECFG_Msk                                       /*!<MTYP[1:0] bits (Memory type)           */
#define SMC_CSCTRL1_MTYPECFG_0                                      (0x1UL << SMC_CSCTRL1_MTYPECFG_Pos)                            /*!< 0x00000004 */
#define SMC_CSCTRL1_MTYPECFG_1                                      (0x2UL << SMC_CSCTRL1_MTYPECFG_Pos)                            /*!< 0x00000008 */

#define SMC_CSCTRL1_MDBWIDCFG_Pos                                   (4U)
#define SMC_CSCTRL1_MDBWIDCFG_Msk                                   (0x3UL << SMC_CSCTRL1_MDBWIDCFG_Pos)                           /*!< 0x00000030 */
#define SMC_CSCTRL1_MDBWIDCFG                                       SMC_CSCTRL1_MDBWIDCFG_Msk                                      /*!<MWID[1:0] bits (Memory data bus width) */
#define SMC_CSCTRL1_MDBWIDCFG_0                                     (0x1UL << SMC_CSCTRL1_MDBWIDCFG_Pos)                           /*!< 0x00000010 */
#define SMC_CSCTRL1_MDBWIDCFG_1                                     (0x2UL << SMC_CSCTRL1_MDBWIDCFG_Pos)                           /*!< 0x00000020 */

#define SMC_CSCTRL1_NORFMACCEN_Pos                                  (6U)
#define SMC_CSCTRL1_NORFMACCEN_Msk                                  (0x1UL << SMC_CSCTRL1_NORFMACCEN_Pos)                          /*!< 0x00000040 */
#define SMC_CSCTRL1_NORFMACCEN                                      SMC_CSCTRL1_NORFMACCEN_Msk                                     /*!<Flash access enable                    */
#define SMC_CSCTRL1_BURSTEN_Pos                                     (8U)
#define SMC_CSCTRL1_BURSTEN_Msk                                     (0x1UL << SMC_CSCTRL1_BURSTEN_Pos)                             /*!< 0x00000100 */
#define SMC_CSCTRL1_BURSTEN                                         SMC_CSCTRL1_BURSTEN_Msk                                        /*!<Burst enable bit                       */
#define SMC_CSCTRL1_WSPOLCFG_Pos                                    (9U)
#define SMC_CSCTRL1_WSPOLCFG_Msk                                    (0x1UL << SMC_CSCTRL1_WSPOLCFG_Pos)                            /*!< 0x00000200 */
#define SMC_CSCTRL1_WSPOLCFG                                        SMC_CSCTRL1_WSPOLCFG_Msk                                       /*!<Wait signal polarity bit               */
#define SMC_CSCTRL1_WRAPBEN_Pos                                     (10U)
#define SMC_CSCTRL1_WRAPBEN_Msk                                     (0x1UL << SMC_CSCTRL1_WRAPBEN_Pos)                             /*!< 0x00000400 */
#define SMC_CSCTRL1_WRAPBEN                                         SMC_CSCTRL1_WRAPBEN_Msk                                        /*!<Wrapped burst mode support             */
#define SMC_CSCTRL1_WTIMCFG_Pos                                     (11U)
#define SMC_CSCTRL1_WTIMCFG_Msk                                     (0x1UL << SMC_CSCTRL1_WTIMCFG_Pos)                             /*!< 0x00000800 */
#define SMC_CSCTRL1_WTIMCFG                                         SMC_CSCTRL1_WTIMCFG_Msk                                        /*!<Wait timing configuration              */
#define SMC_CSCTRL1_WREN_Pos                                        (12U)
#define SMC_CSCTRL1_WREN_Msk                                        (0x1UL << SMC_CSCTRL1_WREN_Pos)                                /*!< 0x00001000 */
#define SMC_CSCTRL1_WREN                                            SMC_CSCTRL1_WREN_Msk                                           /*!<Write enable bit                       */
#define SMC_CSCTRL1_WAITEN_Pos                                      (13U)
#define SMC_CSCTRL1_WAITEN_Msk                                      (0x1UL << SMC_CSCTRL1_WAITEN_Pos)                              /*!< 0x00002000 */
#define SMC_CSCTRL1_WAITEN                                          SMC_CSCTRL1_WAITEN_Msk                                         /*!<Wait enable bit                        */
#define SMC_CSCTRL1_EXTMODEEN_Pos                                   (14U)
#define SMC_CSCTRL1_EXTMODEEN_Msk                                   (0x1UL << SMC_CSCTRL1_EXTMODEEN_Pos)                           /*!< 0x00004000 */
#define SMC_CSCTRL1_EXTMODEEN                                       SMC_CSCTRL1_EXTMODEEN_Msk                                      /*!<Extended mode enable                   */
#define SMC_CSCTRL1_WSASYNCEN_Pos                                   (15U)
#define SMC_CSCTRL1_WSASYNCEN_Msk                                   (0x1UL << SMC_CSCTRL1_WSASYNCEN_Pos)                           /*!< 0x00008000 */
#define SMC_CSCTRL1_WSASYNCEN                                       SMC_CSCTRL1_WSASYNCEN_Msk                                      /*!<Asynchronous wait                      */
#define SMC_CSCTRL1_CRAMPSIZECFG_Pos                                (16U)
#define SMC_CSCTRL1_CRAMPSIZECFG_Msk                                (0x7UL << SMC_CSCTRL1_CRAMPSIZECFG_Pos)                        /*!< 0x00070000 */
#define SMC_CSCTRL1_CRAMPSIZECFG                                    SMC_CSCTRL1_CRAMPSIZECFG_Msk                                   /*!<CRAM page size */
#define SMC_CSCTRL1_CRAMPSIZECFG_0                                  (0x1UL << SMC_CSCTRL1_CRAMPSIZECFG_Pos)                        /*!< 0x00010000 */
#define SMC_CSCTRL1_CRAMPSIZECFG_1                                  (0x2UL << SMC_CSCTRL1_CRAMPSIZECFG_Pos)                        /*!< 0x00020000 */
#define SMC_CSCTRL1_CRAMPSIZECFG_2                                  (0x4UL << SMC_CSCTRL1_CRAMPSIZECFG_Pos)                        /*!< 0x00040000 */
#define SMC_CSCTRL1_WRBURSTEN_Pos                                   (19U)
#define SMC_CSCTRL1_WRBURSTEN_Msk                                   (0x1UL << SMC_CSCTRL1_WRBURSTEN_Pos)                           /*!< 0x00080000 */
#define SMC_CSCTRL1_WRBURSTEN                                       SMC_CSCTRL1_WRBURSTEN_Msk                                      /*!<Write burst enable                     */

/******************  Bit definition for SMC_CSCTRL2 register  *******************/
#define SMC_CSCTRL2_MBKEN_Pos                                       (0U)
#define SMC_CSCTRL2_MBKEN_Msk                                       (0x1UL << SMC_CSCTRL2_MBKEN_Pos)                               /*!< 0x00000001 */
#define SMC_CSCTRL2_MBKEN                                           SMC_CSCTRL2_MBKEN_Msk                                          /*!<Memory bank enable bit                */
#define SMC_CSCTRL2_ADMUXEN_Pos                                     (1U)
#define SMC_CSCTRL2_ADMUXEN_Msk                                     (0x1UL << SMC_CSCTRL2_ADMUXEN_Pos)                             /*!< 0x00000002 */
#define SMC_CSCTRL2_ADMUXEN                                         SMC_CSCTRL2_ADMUXEN_Msk                                        /*!<Address/data multiplexing enable bit   */

#define SMC_CSCTRL2_MTYPECFG_Pos                                    (2U)
#define SMC_CSCTRL2_MTYPECFG_Msk                                    (0x3UL << SMC_CSCTRL2_MTYPECFG_Pos)                            /*!< 0x0000000C */
#define SMC_CSCTRL2_MTYPECFG                                        SMC_CSCTRL2_MTYPECFG_Msk                                       /*!<MTYP[1:0] bits (Memory type)           */
#define SMC_CSCTRL2_MTYPECFG_0                                      (0x1UL << SMC_CSCTRL2_MTYPECFG_Pos)                            /*!< 0x00000004 */
#define SMC_CSCTRL2_MTYPECFG_1                                      (0x2UL << SMC_CSCTRL2_MTYPECFG_Pos)                            /*!< 0x00000008 */

#define SMC_CSCTRL2_MDBWIDCFG_Pos                                   (4U)
#define SMC_CSCTRL2_MDBWIDCFG_Msk                                   (0x3UL << SMC_CSCTRL2_MDBWIDCFG_Pos)                           /*!< 0x00000030 */
#define SMC_CSCTRL2_MDBWIDCFG                                       SMC_CSCTRL2_MDBWIDCFG_Msk                                      /*!<MWID[1:0] bits (Memory data bus width) */
#define SMC_CSCTRL2_MDBWIDCFG_0                                     (0x1UL << SMC_CSCTRL2_MDBWIDCFG_Pos)                           /*!< 0x00000010 */
#define SMC_CSCTRL2_MDBWIDCFG_1                                     (0x2UL << SMC_CSCTRL2_MDBWIDCFG_Pos)                           /*!< 0x00000020 */

#define SMC_CSCTRL2_NORFMACCEN_Pos                                  (6U)
#define SMC_CSCTRL2_NORFMACCEN_Msk                                  (0x1UL << SMC_CSCTRL2_NORFMACCEN_Pos)                          /*!< 0x00000040 */
#define SMC_CSCTRL2_NORFMACCEN                                      SMC_CSCTRL2_NORFMACCEN_Msk                                     /*!<Flash access enable                    */
#define SMC_CSCTRL2_BURSTEN_Pos                                     (8U)
#define SMC_CSCTRL2_BURSTEN_Msk                                     (0x1UL << SMC_CSCTRL2_BURSTEN_Pos)                             /*!< 0x00000100 */
#define SMC_CSCTRL2_BURSTEN                                         SMC_CSCTRL2_BURSTEN_Msk                                        /*!<Burst enable bit                       */
#define SMC_CSCTRL2_WSPOLCFG_Pos                                    (9U)
#define SMC_CSCTRL2_WSPOLCFG_Msk                                    (0x1UL << SMC_CSCTRL2_WSPOLCFG_Pos)                            /*!< 0x00000200 */
#define SMC_CSCTRL2_WSPOLCFG                                        SMC_CSCTRL2_WSPOLCFG_Msk                                       /*!<Wait signal polarity bit               */
#define SMC_CSCTRL2_WRAPBEN_Pos                                     (10U)
#define SMC_CSCTRL2_WRAPBEN_Msk                                     (0x1UL << SMC_CSCTRL2_WRAPBEN_Pos)                             /*!< 0x00000400 */
#define SMC_CSCTRL2_WRAPBEN                                         SMC_CSCTRL2_WRAPBEN_Msk                                        /*!<Wrapped burst mode support             */
#define SMC_CSCTRL2_WTIMCFG_Pos                                     (11U)
#define SMC_CSCTRL2_WTIMCFG_Msk                                     (0x1UL << SMC_CSCTRL2_WTIMCFG_Pos)                             /*!< 0x00000800 */
#define SMC_CSCTRL2_WTIMCFG                                         SMC_CSCTRL2_WTIMCFG_Msk                                        /*!<Wait timing configuration              */
#define SMC_CSCTRL2_WREN_Pos                                        (12U)
#define SMC_CSCTRL2_WREN_Msk                                        (0x1UL << SMC_CSCTRL2_WREN_Pos)                                /*!< 0x00001000 */
#define SMC_CSCTRL2_WREN                                            SMC_CSCTRL2_WREN_Msk                                           /*!<Write enable bit                       */
#define SMC_CSCTRL2_WAITEN_Pos                                      (13U)
#define SMC_CSCTRL2_WAITEN_Msk                                      (0x1UL << SMC_CSCTRL2_WAITEN_Pos)                              /*!< 0x00002000 */
#define SMC_CSCTRL2_WAITEN                                          SMC_CSCTRL2_WAITEN_Msk                                         /*!<Wait enable bit                        */
#define SMC_CSCTRL2_EXTMODEEN_Pos                                   (14U)
#define SMC_CSCTRL2_EXTMODEEN_Msk                                   (0x1UL << SMC_CSCTRL2_EXTMODEEN_Pos)                           /*!< 0x00004000 */
#define SMC_CSCTRL2_EXTMODEEN                                       SMC_CSCTRL2_EXTMODEEN_Msk                                      /*!<Extended mode enable                   */
#define SMC_CSCTRL2_WSASYNCEN_Pos                                   (15U)
#define SMC_CSCTRL2_WSASYNCEN_Msk                                   (0x1UL << SMC_CSCTRL2_WSASYNCEN_Pos)                           /*!< 0x00008000 */
#define SMC_CSCTRL2_WSASYNCEN                                       SMC_CSCTRL2_WSASYNCEN_Msk                                      /*!<Asynchronous wait                      */
#define SMC_CSCTRL2_CRAMPSIZECFG_Pos                                (16U)
#define SMC_CSCTRL2_CRAMPSIZECFG_Msk                                (0x7UL << SMC_CSCTRL2_CRAMPSIZECFG_Pos)                        /*!< 0x00070000 */
#define SMC_CSCTRL2_CRAMPSIZECFG                                    SMC_CSCTRL2_CRAMPSIZECFG_Msk                                   /*!<CRAM page size */
#define SMC_CSCTRL2_CRAMPSIZECFG_0                                  (0x1UL << SMC_CSCTRL2_CRAMPSIZECFG_Pos)                        /*!< 0x00010000 */
#define SMC_CSCTRL2_CRAMPSIZECFG_1                                  (0x2UL << SMC_CSCTRL2_CRAMPSIZECFG_Pos)                        /*!< 0x00020000 */
#define SMC_CSCTRL2_CRAMPSIZECFG_2                                  (0x4UL << SMC_CSCTRL2_CRAMPSIZECFG_Pos)                        /*!< 0x00040000 */
#define SMC_CSCTRL2_WRBURSTEN_Pos                                   (19U)
#define SMC_CSCTRL2_WRBURSTEN_Msk                                   (0x1UL << SMC_CSCTRL2_WRBURSTEN_Pos)                           /*!< 0x00080000 */
#define SMC_CSCTRL2_WRBURSTEN                                       SMC_CSCTRL2_WRBURSTEN_Msk                                      /*!<Write burst enable                     */

/******************  Bit definition for SMC_CSCTRL3 register  *******************/
#define SMC_CSCTRL3_MBKEN_Pos                                       (0U)
#define SMC_CSCTRL3_MBKEN_Msk                                       (0x1UL << SMC_CSCTRL3_MBKEN_Pos)                               /*!< 0x00000001 */
#define SMC_CSCTRL3_MBKEN                                           SMC_CSCTRL3_MBKEN_Msk                                          /*!<Memory bank enable bit                 */
#define SMC_CSCTRL3_ADMUXEN_Pos                                     (1U)
#define SMC_CSCTRL3_ADMUXEN_Msk                                     (0x1UL << SMC_CSCTRL3_ADMUXEN_Pos)                             /*!< 0x00000002 */
#define SMC_CSCTRL3_ADMUXEN                                         SMC_CSCTRL3_ADMUXEN_Msk                                        /*!<Address/data multiplexing enable bit   */

#define SMC_CSCTRL3_MTYPECFG_Pos                                    (2U)
#define SMC_CSCTRL3_MTYPECFG_Msk                                    (0x3UL << SMC_CSCTRL3_MTYPECFG_Pos)                            /*!< 0x0000000C */
#define SMC_CSCTRL3_MTYPECFG                                        SMC_CSCTRL3_MTYPECFG_Msk                                       /*!<MTYP[1:0] bits (Memory type)           */
#define SMC_CSCTRL3_MTYPECFG_0                                      (0x1UL << SMC_CSCTRL3_MTYPECFG_Pos)                            /*!< 0x00000004 */
#define SMC_CSCTRL3_MTYPECFG_1                                      (0x2UL << SMC_CSCTRL3_MTYPECFG_Pos)                            /*!< 0x00000008 */

#define SMC_CSCTRL3_MDBWIDCFG_Pos                                   (4U)
#define SMC_CSCTRL3_MDBWIDCFG_Msk                                   (0x3UL << SMC_CSCTRL3_MDBWIDCFG_Pos)                           /*!< 0x00000030 */
#define SMC_CSCTRL3_MDBWIDCFG                                       SMC_CSCTRL3_MDBWIDCFG_Msk                                      /*!<MWID[1:0] bits (Memory data bus width) */
#define SMC_CSCTRL3_MDBWIDCFG_0                                     (0x1UL << SMC_CSCTRL3_MDBWIDCFG_Pos)                           /*!< 0x00000010 */
#define SMC_CSCTRL3_MDBWIDCFG_1                                     (0x2UL << SMC_CSCTRL3_MDBWIDCFG_Pos)                           /*!< 0x00000020 */

#define SMC_CSCTRL3_NORFMACCEN_Pos                                  (6U)
#define SMC_CSCTRL3_NORFMACCEN_Msk                                  (0x1UL << SMC_CSCTRL3_NORFMACCEN_Pos)                          /*!< 0x00000040 */
#define SMC_CSCTRL3_NORFMACCEN                                      SMC_CSCTRL3_NORFMACCEN_Msk                                     /*!<Flash access enable                    */
#define SMC_CSCTRL3_BURSTEN_Pos                                     (8U)
#define SMC_CSCTRL3_BURSTEN_Msk                                     (0x1UL << SMC_CSCTRL3_BURSTEN_Pos)                             /*!< 0x00000100 */
#define SMC_CSCTRL3_BURSTEN                                         SMC_CSCTRL3_BURSTEN_Msk                                        /*!<Burst enable bit                       */
#define SMC_CSCTRL3_WSPOLCFG_Pos                                    (9U)
#define SMC_CSCTRL3_WSPOLCFG_Msk                                    (0x1UL << SMC_CSCTRL3_WSPOLCFG_Pos)                            /*!< 0x00000200 */
#define SMC_CSCTRL3_WSPOLCFG                                        SMC_CSCTRL3_WSPOLCFG_Msk                                       /*!<Wait signal polarity bit               */
#define SMC_CSCTRL3_WRAPBEN_Pos                                     (10U)
#define SMC_CSCTRL3_WRAPBEN_Msk                                     (0x1UL << SMC_CSCTRL3_WRAPBEN_Pos)                             /*!< 0x00000400 */
#define SMC_CSCTRL3_WRAPBEN                                         SMC_CSCTRL3_WRAPBEN_Msk                                        /*!<Wrapped burst mode support             */
#define SMC_CSCTRL3_WTIMCFG_Pos                                     (11U)
#define SMC_CSCTRL3_WTIMCFG_Msk                                     (0x1UL << SMC_CSCTRL3_WTIMCFG_Pos)                             /*!< 0x00000800 */
#define SMC_CSCTRL3_WTIMCFG                                         SMC_CSCTRL3_WTIMCFG_Msk                                        /*!<Wait timing configuration              */
#define SMC_CSCTRL3_WREN_Pos                                        (12U)
#define SMC_CSCTRL3_WREN_Msk                                        (0x1UL << SMC_CSCTRL3_WREN_Pos)                                /*!< 0x00001000 */
#define SMC_CSCTRL3_WREN                                            SMC_CSCTRL3_WREN_Msk                                           /*!<Write enable bit                       */
#define SMC_CSCTRL3_WAITEN_Pos                                      (13U)
#define SMC_CSCTRL3_WAITEN_Msk                                      (0x1UL << SMC_CSCTRL3_WAITEN_Pos)                              /*!< 0x00002000 */
#define SMC_CSCTRL3_WAITEN                                          SMC_CSCTRL3_WAITEN_Msk                                         /*!<Wait enable bit                        */
#define SMC_CSCTRL3_EXTMODEEN_Pos                                   (14U)
#define SMC_CSCTRL3_EXTMODEEN_Msk                                   (0x1UL << SMC_CSCTRL3_EXTMODEEN_Pos)                           /*!< 0x00004000 */
#define SMC_CSCTRL3_EXTMODEEN                                       SMC_CSCTRL3_EXTMODEEN_Msk                                      /*!<Extended mode enable                   */
#define SMC_CSCTRL3_WSASYNCEN_Pos                                   (15U)
#define SMC_CSCTRL3_WSASYNCEN_Msk                                   (0x1UL << SMC_CSCTRL3_WSASYNCEN_Pos)                           /*!< 0x00008000 */
#define SMC_CSCTRL3_WSASYNCEN                                       SMC_CSCTRL3_WSASYNCEN_Msk                                      /*!<Asynchronous wait                      */
#define SMC_CSCTRL3_CRAMPSIZECFG_Pos                                (16U)
#define SMC_CSCTRL3_CRAMPSIZECFG_Msk                                (0x7UL << SMC_CSCTRL3_CRAMPSIZECFG_Pos)                        /*!< 0x00070000 */
#define SMC_CSCTRL3_CRAMPSIZECFG                                    SMC_CSCTRL3_CRAMPSIZECFG_Msk                                   /*!<CRAM page size */
#define SMC_CSCTRL3_CRAMPSIZECFG_0                                  (0x1UL << SMC_CSCTRL3_CRAMPSIZECFG_Pos)                        /*!< 0x00010000 */
#define SMC_CSCTRL3_CRAMPSIZECFG_1                                  (0x2UL << SMC_CSCTRL3_CRAMPSIZECFG_Pos)                        /*!< 0x00020000 */
#define SMC_CSCTRL3_CRAMPSIZECFG_2                                  (0x4UL << SMC_CSCTRL3_CRAMPSIZECFG_Pos)                        /*!< 0x00040000 */
#define SMC_CSCTRL3_WRBURSTEN_Pos                                   (19U)
#define SMC_CSCTRL3_WRBURSTEN_Msk                                   (0x1UL << SMC_CSCTRL3_WRBURSTEN_Pos)                           /*!< 0x00080000 */
#define SMC_CSCTRL3_WRBURSTEN                                       SMC_CSCTRL3_WRBURSTEN_Msk                                      /*!<Write burst enable                     */

/******************  Bit definition for SMC_CSCTRL4 register  *******************/
#define SMC_CSCTRL4_MBKEN_Pos                                       (0U)
#define SMC_CSCTRL4_MBKEN_Msk                                       (0x1UL << SMC_CSCTRL4_MBKEN_Pos)                               /*!< 0x00000001 */
#define SMC_CSCTRL4_MBKEN                                           SMC_CSCTRL4_MBKEN_Msk                                          /*!<Memory bank enable bit */
#define SMC_CSCTRL4_ADMUXEN_Pos                                     (1U)
#define SMC_CSCTRL4_ADMUXEN_Msk                                     (0x1UL << SMC_CSCTRL4_ADMUXEN_Pos)                             /*!< 0x00000002 */
#define SMC_CSCTRL4_ADMUXEN                                         SMC_CSCTRL4_ADMUXEN_Msk                                        /*!<Address/data multiplexing enable bit   */

#define SMC_CSCTRL4_MTYPECFG_Pos                                    (2U)
#define SMC_CSCTRL4_MTYPECFG_Msk                                    (0x3UL << SMC_CSCTRL4_MTYPECFG_Pos)                            /*!< 0x0000000C */
#define SMC_CSCTRL4_MTYPECFG                                        SMC_CSCTRL4_MTYPECFG_Msk                                       /*!<MTYP[1:0] bits (Memory type)           */
#define SMC_CSCTRL4_MTYPECFG_0                                      (0x1UL << SMC_CSCTRL4_MTYPECFG_Pos)                            /*!< 0x00000004 */
#define SMC_CSCTRL4_MTYPECFG_1                                      (0x2UL << SMC_CSCTRL4_MTYPECFG_Pos)                            /*!< 0x00000008 */

#define SMC_CSCTRL4_MDBWIDCFG_Pos                                   (4U)
#define SMC_CSCTRL4_MDBWIDCFG_Msk                                   (0x3UL << SMC_CSCTRL4_MDBWIDCFG_Pos)                           /*!< 0x00000030 */
#define SMC_CSCTRL4_MDBWIDCFG                                       SMC_CSCTRL4_MDBWIDCFG_Msk                                      /*!<MWID[1:0] bits (Memory data bus width) */
#define SMC_CSCTRL4_MDBWIDCFG_0                                     (0x1UL << SMC_CSCTRL4_MDBWIDCFG_Pos)                           /*!< 0x00000010 */
#define SMC_CSCTRL4_MDBWIDCFG_1                                     (0x2UL << SMC_CSCTRL4_MDBWIDCFG_Pos)                           /*!< 0x00000020 */

#define SMC_CSCTRL4_NORFMACCEN_Pos                                  (6U)
#define SMC_CSCTRL4_NORFMACCEN_Msk                                  (0x1UL << SMC_CSCTRL4_NORFMACCEN_Pos)                          /*!< 0x00000040 */
#define SMC_CSCTRL4_NORFMACCEN                                      SMC_CSCTRL4_NORFMACCEN_Msk                                     /*!<Flash access enable                    */
#define SMC_CSCTRL4_BURSTEN_Pos                                     (8U)
#define SMC_CSCTRL4_BURSTEN_Msk                                     (0x1UL << SMC_CSCTRL4_BURSTEN_Pos)                             /*!< 0x00000100 */
#define SMC_CSCTRL4_BURSTEN                                         SMC_CSCTRL4_BURSTEN_Msk                                        /*!<Burst enable bit                       */
#define SMC_CSCTRL4_WSPOLCFG_Pos                                    (9U)
#define SMC_CSCTRL4_WSPOLCFG_Msk                                    (0x1UL << SMC_CSCTRL4_WSPOLCFG_Pos)                            /*!< 0x00000200 */
#define SMC_CSCTRL4_WSPOLCFG                                        SMC_CSCTRL4_WSPOLCFG_Msk                                       /*!<Wait signal polarity bit               */
#define SMC_CSCTRL4_WRAPBEN_Pos                                     (10U)
#define SMC_CSCTRL4_WRAPBEN_Msk                                     (0x1UL << SMC_CSCTRL4_WRAPBEN_Pos)                             /*!< 0x00000400 */
#define SMC_CSCTRL4_WRAPBEN                                         SMC_CSCTRL4_WRAPBEN_Msk                                        /*!<Wrapped burst mode support             */
#define SMC_CSCTRL4_WTIMCFG_Pos                                     (11U)
#define SMC_CSCTRL4_WTIMCFG_Msk                                     (0x1UL << SMC_CSCTRL4_WTIMCFG_Pos)                             /*!< 0x00000800 */
#define SMC_CSCTRL4_WTIMCFG                                         SMC_CSCTRL4_WTIMCFG_Msk                                        /*!<Wait timing configuration              */
#define SMC_CSCTRL4_WREN_Pos                                        (12U)
#define SMC_CSCTRL4_WREN_Msk                                        (0x1UL << SMC_CSCTRL4_WREN_Pos)                                /*!< 0x00001000 */
#define SMC_CSCTRL4_WREN                                            SMC_CSCTRL4_WREN_Msk                                           /*!<Write enable bit                       */
#define SMC_CSCTRL4_WAITEN_Pos                                      (13U)
#define SMC_CSCTRL4_WAITEN_Msk                                      (0x1UL << SMC_CSCTRL4_WAITEN_Pos)                              /*!< 0x00002000 */
#define SMC_CSCTRL4_WAITEN                                          SMC_CSCTRL4_WAITEN_Msk                                         /*!<Wait enable bit                        */
#define SMC_CSCTRL4_EXTMODEEN_Pos                                   (14U)
#define SMC_CSCTRL4_EXTMODEEN_Msk                                   (0x1UL << SMC_CSCTRL4_EXTMODEEN_Pos)                           /*!< 0x00004000 */
#define SMC_CSCTRL4_EXTMODEEN                                       SMC_CSCTRL4_EXTMODEEN_Msk                                      /*!<Extended mode enable                   */
#define SMC_CSCTRL4_WSASYNCEN_Pos                                   (15U)
#define SMC_CSCTRL4_WSASYNCEN_Msk                                   (0x1UL << SMC_CSCTRL4_WSASYNCEN_Pos)                           /*!< 0x00008000 */
#define SMC_CSCTRL4_WSASYNCEN                                       SMC_CSCTRL4_WSASYNCEN_Msk                                      /*!<Asynchronous wait                      */
#define SMC_CSCTRL4_CRAMPSIZECFG_Pos                                (16U)
#define SMC_CSCTRL4_CRAMPSIZECFG_Msk                                (0x7UL << SMC_CSCTRL4_CRAMPSIZECFG_Pos)                        /*!< 0x00070000 */
#define SMC_CSCTRL4_CRAMPSIZECFG                                    SMC_CSCTRL4_CRAMPSIZECFG_Msk                                   /*!<CRAM page size */
#define SMC_CSCTRL4_CRAMPSIZECFG_0                                  (0x1UL << SMC_CSCTRL4_CRAMPSIZECFG_Pos)                        /*!< 0x00010000 */
#define SMC_CSCTRL4_CRAMPSIZECFG_1                                  (0x2UL << SMC_CSCTRL4_CRAMPSIZECFG_Pos)                        /*!< 0x00020000 */
#define SMC_CSCTRL4_CRAMPSIZECFG_2                                  (0x4UL << SMC_CSCTRL4_CRAMPSIZECFG_Pos)                        /*!< 0x00040000 */
#define SMC_CSCTRL4_WRBURSTEN_Pos                                   (19U)
#define SMC_CSCTRL4_WRBURSTEN_Msk                                   (0x1UL << SMC_CSCTRL4_WRBURSTEN_Pos)                           /*!< 0x00080000 */
#define SMC_CSCTRL4_WRBURSTEN                                       SMC_CSCTRL4_WRBURSTEN_Msk                                      /*!<Write burst enable                     */

/******************  Bit definition for SMC_CSTIM1 register  ******************/
#define SMC_CSTIM1_ADDRSETCFG_Pos                                   (0U)
#define SMC_CSTIM1_ADDRSETCFG_Msk                                   (0xFUL << SMC_CSTIM1_ADDRSETCFG_Pos)                           /*!< 0x0000000F */
#define SMC_CSTIM1_ADDRSETCFG                                       SMC_CSTIM1_ADDRSETCFG_Msk                                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define SMC_CSTIM1_ADDRSETCFG_0                                     (0x1UL << SMC_CSTIM1_ADDRSETCFG_Pos)                           /*!< 0x00000001 */
#define SMC_CSTIM1_ADDRSETCFG_1                                     (0x2UL << SMC_CSTIM1_ADDRSETCFG_Pos)                           /*!< 0x00000002 */
#define SMC_CSTIM1_ADDRSETCFG_2                                     (0x4UL << SMC_CSTIM1_ADDRSETCFG_Pos)                           /*!< 0x00000004 */
#define SMC_CSTIM1_ADDRSETCFG_3                                     (0x8UL << SMC_CSTIM1_ADDRSETCFG_Pos)                           /*!< 0x00000008 */

#define SMC_CSTIM1_ADDRHLDCFG_Pos                                   (4U)
#define SMC_CSTIM1_ADDRHLDCFG_Msk                                   (0xFUL << SMC_CSTIM1_ADDRHLDCFG_Pos)                           /*!< 0x000000F0 */
#define SMC_CSTIM1_ADDRHLDCFG                                       SMC_CSTIM1_ADDRHLDCFG_Msk                                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define SMC_CSTIM1_ADDRHLDCFG_0                                     (0x1UL << SMC_CSTIM1_ADDRHLDCFG_Pos)                           /*!< 0x00000010 */
#define SMC_CSTIM1_ADDRHLDCFG_1                                     (0x2UL << SMC_CSTIM1_ADDRHLDCFG_Pos)                           /*!< 0x00000020 */
#define SMC_CSTIM1_ADDRHLDCFG_2                                     (0x4UL << SMC_CSTIM1_ADDRHLDCFG_Pos)                           /*!< 0x00000040 */
#define SMC_CSTIM1_ADDRHLDCFG_3                                     (0x8UL << SMC_CSTIM1_ADDRHLDCFG_Pos)                           /*!< 0x00000080 */

#define SMC_CSTIM1_DATASETCFG_Pos                                   (8U)
#define SMC_CSTIM1_DATASETCFG_Msk                                   (0xFFUL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x0000FF00 */
#define SMC_CSTIM1_DATASETCFG                                       SMC_CSTIM1_DATASETCFG_Msk                                      /*!<DATAST [7:0] bits (Data-phase duration) */
#define SMC_CSTIM1_DATASETCFG_0                                     (0x01UL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x00000100 */
#define SMC_CSTIM1_DATASETCFG_1                                     (0x02UL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x00000200 */
#define SMC_CSTIM1_DATASETCFG_2                                     (0x04UL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x00000400 */
#define SMC_CSTIM1_DATASETCFG_3                                     (0x08UL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x00000800 */
#define SMC_CSTIM1_DATASETCFG_4                                     (0x10UL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x00001000 */
#define SMC_CSTIM1_DATASETCFG_5                                     (0x20UL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x00002000 */
#define SMC_CSTIM1_DATASETCFG_6                                     (0x40UL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x00004000 */
#define SMC_CSTIM1_DATASETCFG_7                                     (0x80UL << SMC_CSTIM1_DATASETCFG_Pos)                          /*!< 0x00008000 */

#define SMC_CSTIM1_BUSTURNCFG_Pos                                   (16U)
#define SMC_CSTIM1_BUSTURNCFG_Msk                                   (0xFUL << SMC_CSTIM1_BUSTURNCFG_Pos)                           /*!< 0x000F0000 */
#define SMC_CSTIM1_BUSTURNCFG                                       SMC_CSTIM1_BUSTURNCFG_Msk                                      /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define SMC_CSTIM1_BUSTURNCFG_0                                     (0x1UL << SMC_CSTIM1_BUSTURNCFG_Pos)                           /*!< 0x00010000 */
#define SMC_CSTIM1_BUSTURNCFG_1                                     (0x2UL << SMC_CSTIM1_BUSTURNCFG_Pos)                           /*!< 0x00020000 */
#define SMC_CSTIM1_BUSTURNCFG_2                                     (0x4UL << SMC_CSTIM1_BUSTURNCFG_Pos)                           /*!< 0x00040000 */
#define SMC_CSTIM1_BUSTURNCFG_3                                     (0x8UL << SMC_CSTIM1_BUSTURNCFG_Pos)                           /*!< 0x00080000 */

#define SMC_CSTIM1_CLKDIVCFG_Pos                                    (20U)
#define SMC_CSTIM1_CLKDIVCFG_Msk                                    (0xFUL << SMC_CSTIM1_CLKDIVCFG_Pos)                            /*!< 0x00F00000 */
#define SMC_CSTIM1_CLKDIVCFG                                        SMC_CSTIM1_CLKDIVCFG_Msk                                       /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define SMC_CSTIM1_CLKDIVCFG_0                                      (0x1UL << SMC_CSTIM1_CLKDIVCFG_Pos)                            /*!< 0x00100000 */
#define SMC_CSTIM1_CLKDIVCFG_1                                      (0x2UL << SMC_CSTIM1_CLKDIVCFG_Pos)                            /*!< 0x00200000 */
#define SMC_CSTIM1_CLKDIVCFG_2                                      (0x4UL << SMC_CSTIM1_CLKDIVCFG_Pos)                            /*!< 0x00400000 */
#define SMC_CSTIM1_CLKDIVCFG_3                                      (0x8UL << SMC_CSTIM1_CLKDIVCFG_Pos)                            /*!< 0x00800000 */

#define SMC_CSTIM1_DATALATCFG_Pos                                   (24U)
#define SMC_CSTIM1_DATALATCFG_Msk                                   (0xFUL << SMC_CSTIM1_DATALATCFG_Pos)                           /*!< 0x0F000000 */
#define SMC_CSTIM1_DATALATCFG                                       SMC_CSTIM1_DATALATCFG_Msk                                      /*!<DATLA[3:0] bits (Data latency) */
#define SMC_CSTIM1_DATALATCFG_0                                     (0x1UL << SMC_CSTIM1_DATALATCFG_Pos)                           /*!< 0x01000000 */
#define SMC_CSTIM1_DATALATCFG_1                                     (0x2UL << SMC_CSTIM1_DATALATCFG_Pos)                           /*!< 0x02000000 */
#define SMC_CSTIM1_DATALATCFG_2                                     (0x4UL << SMC_CSTIM1_DATALATCFG_Pos)                           /*!< 0x04000000 */
#define SMC_CSTIM1_DATALATCFG_3                                     (0x8UL << SMC_CSTIM1_DATALATCFG_Pos)                           /*!< 0x08000000 */

#define SMC_CSTIM1_ASYNCACCCFG_Pos                                  (28U)
#define SMC_CSTIM1_ASYNCACCCFG_Msk                                  (0x3UL << SMC_CSTIM1_ASYNCACCCFG_Pos)                          /*!< 0x30000000 */
#define SMC_CSTIM1_ASYNCACCCFG                                      SMC_CSTIM1_ASYNCACCCFG_Msk                                     /*!<ACCMOD[1:0] bits (Access mode) */
#define SMC_CSTIM1_ASYNCACCCFG_0                                    (0x1UL << SMC_CSTIM1_ASYNCACCCFG_Pos)                          /*!< 0x10000000 */
#define SMC_CSTIM1_ASYNCACCCFG_1                                    (0x2UL << SMC_CSTIM1_ASYNCACCCFG_Pos)                          /*!< 0x20000000 */

/******************  Bit definition for SMC_CSTIM2 register  *******************/
#define SMC_CSTIM2_ADDRSETCFG_Pos                                   (0U)
#define SMC_CSTIM2_ADDRSETCFG_Msk                                   (0xFUL << SMC_CSTIM2_ADDRSETCFG_Pos)                           /*!< 0x0000000F */
#define SMC_CSTIM2_ADDRSETCFG                                       SMC_CSTIM2_ADDRSETCFG_Msk                                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define SMC_CSTIM2_ADDRSETCFG_0                                     (0x1UL << SMC_CSTIM2_ADDRSETCFG_Pos)                           /*!< 0x00000001 */
#define SMC_CSTIM2_ADDRSETCFG_1                                     (0x2UL << SMC_CSTIM2_ADDRSETCFG_Pos)                           /*!< 0x00000002 */
#define SMC_CSTIM2_ADDRSETCFG_2                                     (0x4UL << SMC_CSTIM2_ADDRSETCFG_Pos)                           /*!< 0x00000004 */
#define SMC_CSTIM2_ADDRSETCFG_3                                     (0x8UL << SMC_CSTIM2_ADDRSETCFG_Pos)                           /*!< 0x00000008 */

#define SMC_CSTIM2_ADDRHLDCFG_Pos                                   (4U)
#define SMC_CSTIM2_ADDRHLDCFG_Msk                                   (0xFUL << SMC_CSTIM2_ADDRHLDCFG_Pos)                           /*!< 0x000000F0 */
#define SMC_CSTIM2_ADDRHLDCFG                                       SMC_CSTIM2_ADDRHLDCFG_Msk                                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define SMC_CSTIM2_ADDRHLDCFG_0                                     (0x1UL << SMC_CSTIM2_ADDRHLDCFG_Pos)                           /*!< 0x00000010 */
#define SMC_CSTIM2_ADDRHLDCFG_1                                     (0x2UL << SMC_CSTIM2_ADDRHLDCFG_Pos)                           /*!< 0x00000020 */
#define SMC_CSTIM2_ADDRHLDCFG_2                                     (0x4UL << SMC_CSTIM2_ADDRHLDCFG_Pos)                           /*!< 0x00000040 */
#define SMC_CSTIM2_ADDRHLDCFG_3                                     (0x8UL << SMC_CSTIM2_ADDRHLDCFG_Pos)                           /*!< 0x00000080 */

#define SMC_CSTIM2_DATASETCFG_Pos                                   (8U)
#define SMC_CSTIM2_DATASETCFG_Msk                                   (0xFFUL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x0000FF00 */
#define SMC_CSTIM2_DATASETCFG                                       SMC_CSTIM2_DATASETCFG_Msk                                      /*!<DATAST [7:0] bits (Data-phase duration) */
#define SMC_CSTIM2_DATASETCFG_0                                     (0x01UL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x00000100 */
#define SMC_CSTIM2_DATASETCFG_1                                     (0x02UL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x00000200 */
#define SMC_CSTIM2_DATASETCFG_2                                     (0x04UL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x00000400 */
#define SMC_CSTIM2_DATASETCFG_3                                     (0x08UL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x00000800 */
#define SMC_CSTIM2_DATASETCFG_4                                     (0x10UL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x00001000 */
#define SMC_CSTIM2_DATASETCFG_5                                     (0x20UL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x00002000 */
#define SMC_CSTIM2_DATASETCFG_6                                     (0x40UL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x00004000 */
#define SMC_CSTIM2_DATASETCFG_7                                     (0x80UL << SMC_CSTIM2_DATASETCFG_Pos)                          /*!< 0x00008000 */

#define SMC_CSTIM2_BUSTURNCFG_Pos                                   (16U)
#define SMC_CSTIM2_BUSTURNCFG_Msk                                   (0xFUL << SMC_CSTIM2_BUSTURNCFG_Pos)                           /*!< 0x000F0000 */
#define SMC_CSTIM2_BUSTURNCFG                                       SMC_CSTIM2_BUSTURNCFG_Msk                                      /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define SMC_CSTIM2_BUSTURNCFG_0                                     (0x1UL << SMC_CSTIM2_BUSTURNCFG_Pos)                           /*!< 0x00010000 */
#define SMC_CSTIM2_BUSTURNCFG_1                                     (0x2UL << SMC_CSTIM2_BUSTURNCFG_Pos)                           /*!< 0x00020000 */
#define SMC_CSTIM2_BUSTURNCFG_2                                     (0x4UL << SMC_CSTIM2_BUSTURNCFG_Pos)                           /*!< 0x00040000 */
#define SMC_CSTIM2_BUSTURNCFG_3                                     (0x8UL << SMC_CSTIM2_BUSTURNCFG_Pos)                           /*!< 0x00080000 */

#define SMC_CSTIM2_CLKDIVCFG_Pos                                    (20U)
#define SMC_CSTIM2_CLKDIVCFG_Msk                                    (0xFUL << SMC_CSTIM2_CLKDIVCFG_Pos)                            /*!< 0x00F00000 */
#define SMC_CSTIM2_CLKDIVCFG                                        SMC_CSTIM2_CLKDIVCFG_Msk                                       /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define SMC_CSTIM2_CLKDIVCFG_0                                      (0x1UL << SMC_CSTIM2_CLKDIVCFG_Pos)                            /*!< 0x00100000 */
#define SMC_CSTIM2_CLKDIVCFG_1                                      (0x2UL << SMC_CSTIM2_CLKDIVCFG_Pos)                            /*!< 0x00200000 */
#define SMC_CSTIM2_CLKDIVCFG_2                                      (0x4UL << SMC_CSTIM2_CLKDIVCFG_Pos)                            /*!< 0x00400000 */
#define SMC_CSTIM2_CLKDIVCFG_3                                      (0x8UL << SMC_CSTIM2_CLKDIVCFG_Pos)                            /*!< 0x00800000 */

#define SMC_CSTIM2_DATALATCFG_Pos                                   (24U)
#define SMC_CSTIM2_DATALATCFG_Msk                                   (0xFUL << SMC_CSTIM2_DATALATCFG_Pos)                           /*!< 0x0F000000 */
#define SMC_CSTIM2_DATALATCFG                                       SMC_CSTIM2_DATALATCFG_Msk                                      /*!<DATLA[3:0] bits (Data latency) */
#define SMC_CSTIM2_DATALATCFG_0                                     (0x1UL << SMC_CSTIM2_DATALATCFG_Pos)                           /*!< 0x01000000 */
#define SMC_CSTIM2_DATALATCFG_1                                     (0x2UL << SMC_CSTIM2_DATALATCFG_Pos)                           /*!< 0x02000000 */
#define SMC_CSTIM2_DATALATCFG_2                                     (0x4UL << SMC_CSTIM2_DATALATCFG_Pos)                           /*!< 0x04000000 */
#define SMC_CSTIM2_DATALATCFG_3                                     (0x8UL << SMC_CSTIM2_DATALATCFG_Pos)                           /*!< 0x08000000 */

#define SMC_CSTIM2_ASYNCACCCFG_Pos                                  (28U)
#define SMC_CSTIM2_ASYNCACCCFG_Msk                                  (0x3UL << SMC_CSTIM2_ASYNCACCCFG_Pos)                          /*!< 0x30000000 */
#define SMC_CSTIM2_ASYNCACCCFG                                      SMC_CSTIM2_ASYNCACCCFG_Msk                                     /*!<ACCMOD[1:0] bits (Access mode) */
#define SMC_CSTIM2_ASYNCACCCFG_0                                    (0x1UL << SMC_CSTIM2_ASYNCACCCFG_Pos)                          /*!< 0x10000000 */
#define SMC_CSTIM2_ASYNCACCCFG_1                                    (0x2UL << SMC_CSTIM2_ASYNCACCCFG_Pos)                          /*!< 0x20000000 */

/*******************  Bit definition for SMC_CSTIM3 register  *******************/
#define SMC_CSTIM3_ADDRSETCFG_Pos                                   (0U)
#define SMC_CSTIM3_ADDRSETCFG_Msk                                   (0xFUL << SMC_CSTIM3_ADDRSETCFG_Pos)                           /*!< 0x0000000F */
#define SMC_CSTIM3_ADDRSETCFG                                       SMC_CSTIM3_ADDRSETCFG_Msk                                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define SMC_CSTIM3_ADDRSETCFG_0                                     (0x1UL << SMC_CSTIM3_ADDRSETCFG_Pos)                           /*!< 0x00000001 */
#define SMC_CSTIM3_ADDRSETCFG_1                                     (0x2UL << SMC_CSTIM3_ADDRSETCFG_Pos)                           /*!< 0x00000002 */
#define SMC_CSTIM3_ADDRSETCFG_2                                     (0x4UL << SMC_CSTIM3_ADDRSETCFG_Pos)                           /*!< 0x00000004 */
#define SMC_CSTIM3_ADDRSETCFG_3                                     (0x8UL << SMC_CSTIM3_ADDRSETCFG_Pos)                           /*!< 0x00000008 */

#define SMC_CSTIM3_ADDRHLDCFG_Pos                                   (4U)
#define SMC_CSTIM3_ADDRHLDCFG_Msk                                   (0xFUL << SMC_CSTIM3_ADDRHLDCFG_Pos)                           /*!< 0x000000F0 */
#define SMC_CSTIM3_ADDRHLDCFG                                       SMC_CSTIM3_ADDRHLDCFG_Msk                                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define SMC_CSTIM3_ADDRHLDCFG_0                                     (0x1UL << SMC_CSTIM3_ADDRHLDCFG_Pos)                           /*!< 0x00000010 */
#define SMC_CSTIM3_ADDRHLDCFG_1                                     (0x2UL << SMC_CSTIM3_ADDRHLDCFG_Pos)                           /*!< 0x00000020 */
#define SMC_CSTIM3_ADDRHLDCFG_2                                     (0x4UL << SMC_CSTIM3_ADDRHLDCFG_Pos)                           /*!< 0x00000040 */
#define SMC_CSTIM3_ADDRHLDCFG_3                                     (0x8UL << SMC_CSTIM3_ADDRHLDCFG_Pos)                           /*!< 0x00000080 */

#define SMC_CSTIM3_DATASETCFG_Pos                                   (8U)
#define SMC_CSTIM3_DATASETCFG_Msk                                   (0xFFUL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x0000FF00 */
#define SMC_CSTIM3_DATASETCFG                                       SMC_CSTIM3_DATASETCFG_Msk                                      /*!<DATAST [7:0] bits (Data-phase duration) */
#define SMC_CSTIM3_DATASETCFG_0                                     (0x01UL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x00000100 */
#define SMC_CSTIM3_DATASETCFG_1                                     (0x02UL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x00000200 */
#define SMC_CSTIM3_DATASETCFG_2                                     (0x04UL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x00000400 */
#define SMC_CSTIM3_DATASETCFG_3                                     (0x08UL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x00000800 */
#define SMC_CSTIM3_DATASETCFG_4                                     (0x10UL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x00001000 */
#define SMC_CSTIM3_DATASETCFG_5                                     (0x20UL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x00002000 */
#define SMC_CSTIM3_DATASETCFG_6                                     (0x40UL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x00004000 */
#define SMC_CSTIM3_DATASETCFG_7                                     (0x80UL << SMC_CSTIM3_DATASETCFG_Pos)                          /*!< 0x00008000 */

#define SMC_CSTIM3_BUSTURNCFG_Pos                                   (16U)
#define SMC_CSTIM3_BUSTURNCFG_Msk                                   (0xFUL << SMC_CSTIM3_BUSTURNCFG_Pos)                           /*!< 0x000F0000 */
#define SMC_CSTIM3_BUSTURNCFG                                       SMC_CSTIM3_BUSTURNCFG_Msk                                      /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define SMC_CSTIM3_BUSTURNCFG_0                                     (0x1UL << SMC_CSTIM3_BUSTURNCFG_Pos)                           /*!< 0x00010000 */
#define SMC_CSTIM3_BUSTURNCFG_1                                     (0x2UL << SMC_CSTIM3_BUSTURNCFG_Pos)                           /*!< 0x00020000 */
#define SMC_CSTIM3_BUSTURNCFG_2                                     (0x4UL << SMC_CSTIM3_BUSTURNCFG_Pos)                           /*!< 0x00040000 */
#define SMC_CSTIM3_BUSTURNCFG_3                                     (0x8UL << SMC_CSTIM3_BUSTURNCFG_Pos)                           /*!< 0x00080000 */

#define SMC_CSTIM3_CLKDIVCFG_Pos                                    (20U)
#define SMC_CSTIM3_CLKDIVCFG_Msk                                    (0xFUL << SMC_CSTIM3_CLKDIVCFG_Pos)                            /*!< 0x00F00000 */
#define SMC_CSTIM3_CLKDIVCFG                                        SMC_CSTIM3_CLKDIVCFG_Msk                                       /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define SMC_CSTIM3_CLKDIVCFG_0                                      (0x1UL << SMC_CSTIM3_CLKDIVCFG_Pos)                            /*!< 0x00100000 */
#define SMC_CSTIM3_CLKDIVCFG_1                                      (0x2UL << SMC_CSTIM3_CLKDIVCFG_Pos)                            /*!< 0x00200000 */
#define SMC_CSTIM3_CLKDIVCFG_2                                      (0x4UL << SMC_CSTIM3_CLKDIVCFG_Pos)                            /*!< 0x00400000 */
#define SMC_CSTIM3_CLKDIVCFG_3                                      (0x8UL << SMC_CSTIM3_CLKDIVCFG_Pos)                            /*!< 0x00800000 */

#define SMC_CSTIM3_DATALATCFG_Pos                                   (24U)
#define SMC_CSTIM3_DATALATCFG_Msk                                   (0xFUL << SMC_CSTIM3_DATALATCFG_Pos)                           /*!< 0x0F000000 */
#define SMC_CSTIM3_DATALATCFG                                       SMC_CSTIM3_DATALATCFG_Msk                                      /*!<DATLA[3:0] bits (Data latency) */
#define SMC_CSTIM3_DATALATCFG_0                                     (0x1UL << SMC_CSTIM3_DATALATCFG_Pos)                           /*!< 0x01000000 */
#define SMC_CSTIM3_DATALATCFG_1                                     (0x2UL << SMC_CSTIM3_DATALATCFG_Pos)                           /*!< 0x02000000 */
#define SMC_CSTIM3_DATALATCFG_2                                     (0x4UL << SMC_CSTIM3_DATALATCFG_Pos)                           /*!< 0x04000000 */
#define SMC_CSTIM3_DATALATCFG_3                                     (0x8UL << SMC_CSTIM3_DATALATCFG_Pos)                           /*!< 0x08000000 */

#define SMC_CSTIM3_ASYNCACCCFG_Pos                                  (28U)
#define SMC_CSTIM3_ASYNCACCCFG_Msk                                  (0x3UL << SMC_CSTIM3_ASYNCACCCFG_Pos)                          /*!< 0x30000000 */
#define SMC_CSTIM3_ASYNCACCCFG                                      SMC_CSTIM3_ASYNCACCCFG_Msk                                     /*!<ACCMOD[1:0] bits (Access mode) */
#define SMC_CSTIM3_ASYNCACCCFG_0                                    (0x1UL << SMC_CSTIM3_ASYNCACCCFG_Pos)                          /*!< 0x10000000 */
#define SMC_CSTIM3_ASYNCACCCFG_1                                    (0x2UL << SMC_CSTIM3_ASYNCACCCFG_Pos)                          /*!< 0x20000000 */

/******************  Bit definition for SMC_CSTIM4 register  *******************/
#define SMC_CSTIM4_ADDRSETCFG_Pos                                   (0U)
#define SMC_CSTIM4_ADDRSETCFG_Msk                                   (0xFUL << SMC_CSTIM4_ADDRSETCFG_Pos)                           /*!< 0x0000000F */
#define SMC_CSTIM4_ADDRSETCFG                                       SMC_CSTIM4_ADDRSETCFG_Msk                                      /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define SMC_CSTIM4_ADDRSETCFG_0                                     (0x1UL << SMC_CSTIM4_ADDRSETCFG_Pos)                           /*!< 0x00000001 */
#define SMC_CSTIM4_ADDRSETCFG_1                                     (0x2UL << SMC_CSTIM4_ADDRSETCFG_Pos)                           /*!< 0x00000002 */
#define SMC_CSTIM4_ADDRSETCFG_2                                     (0x4UL << SMC_CSTIM4_ADDRSETCFG_Pos)                           /*!< 0x00000004 */
#define SMC_CSTIM4_ADDRSETCFG_3                                     (0x8UL << SMC_CSTIM4_ADDRSETCFG_Pos)                           /*!< 0x00000008 */

#define SMC_CSTIM4_ADDRHLDCFG_Pos                                   (4U)
#define SMC_CSTIM4_ADDRHLDCFG_Msk                                   (0xFUL << SMC_CSTIM4_ADDRHLDCFG_Pos)                           /*!< 0x000000F0 */
#define SMC_CSTIM4_ADDRHLDCFG                                       SMC_CSTIM4_ADDRHLDCFG_Msk                                      /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define SMC_CSTIM4_ADDRHLDCFG_0                                     (0x1UL << SMC_CSTIM4_ADDRHLDCFG_Pos)                           /*!< 0x00000010 */
#define SMC_CSTIM4_ADDRHLDCFG_1                                     (0x2UL << SMC_CSTIM4_ADDRHLDCFG_Pos)                           /*!< 0x00000020 */
#define SMC_CSTIM4_ADDRHLDCFG_2                                     (0x4UL << SMC_CSTIM4_ADDRHLDCFG_Pos)                           /*!< 0x00000040 */
#define SMC_CSTIM4_ADDRHLDCFG_3                                     (0x8UL << SMC_CSTIM4_ADDRHLDCFG_Pos)                           /*!< 0x00000080 */

#define SMC_CSTIM4_DATASETCFG_Pos                                   (8U)
#define SMC_CSTIM4_DATASETCFG_Msk                                   (0xFFUL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x0000FF00 */
#define SMC_CSTIM4_DATASETCFG                                       SMC_CSTIM4_DATASETCFG_Msk                                      /*!<DATAST [7:0] bits (Data-phase duration) */
#define SMC_CSTIM4_DATASETCFG_0                                     (0x01UL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x00000100 */
#define SMC_CSTIM4_DATASETCFG_1                                     (0x02UL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x00000200 */
#define SMC_CSTIM4_DATASETCFG_2                                     (0x04UL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x00000400 */
#define SMC_CSTIM4_DATASETCFG_3                                     (0x08UL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x00000800 */
#define SMC_CSTIM4_DATASETCFG_4                                     (0x10UL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x00001000 */
#define SMC_CSTIM4_DATASETCFG_5                                     (0x20UL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x00002000 */
#define SMC_CSTIM4_DATASETCFG_6                                     (0x40UL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x00004000 */
#define SMC_CSTIM4_DATASETCFG_7                                     (0x80UL << SMC_CSTIM4_DATASETCFG_Pos)                          /*!< 0x00008000 */

#define SMC_CSTIM4_BUSTURNCFG_Pos                                   (16U)
#define SMC_CSTIM4_BUSTURNCFG_Msk                                   (0xFUL << SMC_CSTIM4_BUSTURNCFG_Pos)                           /*!< 0x000F0000 */
#define SMC_CSTIM4_BUSTURNCFG                                       SMC_CSTIM4_BUSTURNCFG_Msk                                      /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
#define SMC_CSTIM4_BUSTURNCFG_0                                     (0x1UL << SMC_CSTIM4_BUSTURNCFG_Pos)                           /*!< 0x00010000 */
#define SMC_CSTIM4_BUSTURNCFG_1                                     (0x2UL << SMC_CSTIM4_BUSTURNCFG_Pos)                           /*!< 0x00020000 */
#define SMC_CSTIM4_BUSTURNCFG_2                                     (0x4UL << SMC_CSTIM4_BUSTURNCFG_Pos)                           /*!< 0x00040000 */
#define SMC_CSTIM4_BUSTURNCFG_3                                     (0x8UL << SMC_CSTIM4_BUSTURNCFG_Pos)                           /*!< 0x00080000 */

#define SMC_CSTIM4_CLKDIVCFG_Pos                                    (20U)
#define SMC_CSTIM4_CLKDIVCFG_Msk                                    (0xFUL << SMC_CSTIM4_CLKDIVCFG_Pos)                            /*!< 0x00F00000 */
#define SMC_CSTIM4_CLKDIVCFG                                        SMC_CSTIM4_CLKDIVCFG_Msk                                       /*!<CLKDIV[3:0] bits (Clock divide ratio) */
#define SMC_CSTIM4_CLKDIVCFG_0                                      (0x1UL << SMC_CSTIM4_CLKDIVCFG_Pos)                            /*!< 0x00100000 */
#define SMC_CSTIM4_CLKDIVCFG_1                                      (0x2UL << SMC_CSTIM4_CLKDIVCFG_Pos)                            /*!< 0x00200000 */
#define SMC_CSTIM4_CLKDIVCFG_2                                      (0x4UL << SMC_CSTIM4_CLKDIVCFG_Pos)                            /*!< 0x00400000 */
#define SMC_CSTIM4_CLKDIVCFG_3                                      (0x8UL << SMC_CSTIM4_CLKDIVCFG_Pos)                            /*!< 0x00800000 */

#define SMC_CSTIM4_DATALATCFG_Pos                                   (24U)
#define SMC_CSTIM4_DATALATCFG_Msk                                   (0xFUL << SMC_CSTIM4_DATALATCFG_Pos)                           /*!< 0x0F000000 */
#define SMC_CSTIM4_DATALATCFG                                       SMC_CSTIM4_DATALATCFG_Msk                                      /*!<DATLA[3:0] bits (Data latency) */
#define SMC_CSTIM4_DATALATCFG_0                                     (0x1UL << SMC_CSTIM4_DATALATCFG_Pos)                           /*!< 0x01000000 */
#define SMC_CSTIM4_DATALATCFG_1                                     (0x2UL << SMC_CSTIM4_DATALATCFG_Pos)                           /*!< 0x02000000 */
#define SMC_CSTIM4_DATALATCFG_2                                     (0x4UL << SMC_CSTIM4_DATALATCFG_Pos)                           /*!< 0x04000000 */
#define SMC_CSTIM4_DATALATCFG_3                                     (0x8UL << SMC_CSTIM4_DATALATCFG_Pos)                           /*!< 0x08000000 */

#define SMC_CSTIM4_ASYNCACCCFG_Pos                                  (28U)
#define SMC_CSTIM4_ASYNCACCCFG_Msk                                  (0x3UL << SMC_CSTIM4_ASYNCACCCFG_Pos)                          /*!< 0x30000000 */
#define SMC_CSTIM4_ASYNCACCCFG                                      SMC_CSTIM4_ASYNCACCCFG_Msk                                     /*!<ACCMOD[1:0] bits (Access mode) */
#define SMC_CSTIM4_ASYNCACCCFG_0                                    (0x1UL << SMC_CSTIM4_ASYNCACCCFG_Pos)                          /*!< 0x10000000 */
#define SMC_CSTIM4_ASYNCACCCFG_1                                    (0x2UL << SMC_CSTIM4_ASYNCACCCFG_Pos)                          /*!< 0x20000000 */

/******************  Bit definition for SMC_WRTTIM1 register  ******************/
#define SMC_WRTTIM1_ADDRSETCFG_Pos                                  (0U)
#define SMC_WRTTIM1_ADDRSETCFG_Msk                                  (0xFUL << SMC_WRTTIM1_ADDRSETCFG_Pos)                          /*!< 0x0000000F */
#define SMC_WRTTIM1_ADDRSETCFG                                      SMC_WRTTIM1_ADDRSETCFG_Msk                                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define SMC_WRTTIM1_ADDRSETCFG_0                                    (0x1UL << SMC_WRTTIM1_ADDRSETCFG_Pos)                          /*!< 0x00000001 */
#define SMC_WRTTIM1_ADDRSETCFG_1                                    (0x2UL << SMC_WRTTIM1_ADDRSETCFG_Pos)                          /*!< 0x00000002 */
#define SMC_WRTTIM1_ADDRSETCFG_2                                    (0x4UL << SMC_WRTTIM1_ADDRSETCFG_Pos)                          /*!< 0x00000004 */
#define SMC_WRTTIM1_ADDRSETCFG_3                                    (0x8UL << SMC_WRTTIM1_ADDRSETCFG_Pos)                          /*!< 0x00000008 */

#define SMC_WRTTIM1_ADDRHLDCFG_Pos                                  (4U)
#define SMC_WRTTIM1_ADDRHLDCFG_Msk                                  (0xFUL << SMC_WRTTIM1_ADDRHLDCFG_Pos)                          /*!< 0x000000F0 */
#define SMC_WRTTIM1_ADDRHLDCFG                                      SMC_WRTTIM1_ADDRHLDCFG_Msk                                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define SMC_WRTTIM1_ADDRHLDCFG_0                                    (0x1UL << SMC_WRTTIM1_ADDRHLDCFG_Pos)                          /*!< 0x00000010 */
#define SMC_WRTTIM1_ADDRHLDCFG_1                                    (0x2UL << SMC_WRTTIM1_ADDRHLDCFG_Pos)                          /*!< 0x00000020 */
#define SMC_WRTTIM1_ADDRHLDCFG_2                                    (0x4UL << SMC_WRTTIM1_ADDRHLDCFG_Pos)                          /*!< 0x00000040 */
#define SMC_WRTTIM1_ADDRHLDCFG_3                                    (0x8UL << SMC_WRTTIM1_ADDRHLDCFG_Pos)                          /*!< 0x00000080 */

#define SMC_WRTTIM1_DATASETCFG_Pos                                  (8U)
#define SMC_WRTTIM1_DATASETCFG_Msk                                  (0xFFUL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x0000FF00 */
#define SMC_WRTTIM1_DATASETCFG                                      SMC_WRTTIM1_DATASETCFG_Msk                                     /*!<DATAST [7:0] bits (Data-phase duration) */
#define SMC_WRTTIM1_DATASETCFG_0                                    (0x01UL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x00000100 */
#define SMC_WRTTIM1_DATASETCFG_1                                    (0x02UL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x00000200 */
#define SMC_WRTTIM1_DATASETCFG_2                                    (0x04UL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x00000400 */
#define SMC_WRTTIM1_DATASETCFG_3                                    (0x08UL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x00000800 */
#define SMC_WRTTIM1_DATASETCFG_4                                    (0x10UL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x00001000 */
#define SMC_WRTTIM1_DATASETCFG_5                                    (0x20UL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x00002000 */
#define SMC_WRTTIM1_DATASETCFG_6                                    (0x40UL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x00004000 */
#define SMC_WRTTIM1_DATASETCFG_7                                    (0x80UL << SMC_WRTTIM1_DATASETCFG_Pos)                         /*!< 0x00008000 */

#define SMC_WRTTIM1_BUSTURNCFG_Pos                                  (16U)
#define SMC_WRTTIM1_BUSTURNCFG_Msk                                  (0xFUL << SMC_WRTTIM1_BUSTURNCFG_Pos)                          /*!< 0x000F0000 */
#define SMC_WRTTIM1_BUSTURNCFG                                      SMC_WRTTIM1_BUSTURNCFG_Msk                                     /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define SMC_WRTTIM1_BUSTURNCFG_0                                    (0x1UL << SMC_WRTTIM1_BUSTURNCFG_Pos)                          /*!< 0x00010000 */
#define SMC_WRTTIM1_BUSTURNCFG_1                                    (0x2UL << SMC_WRTTIM1_BUSTURNCFG_Pos)                          /*!< 0x00020000 */
#define SMC_WRTTIM1_BUSTURNCFG_2                                    (0x4UL << SMC_WRTTIM1_BUSTURNCFG_Pos)                          /*!< 0x00040000 */
#define SMC_WRTTIM1_BUSTURNCFG_3                                    (0x8UL << SMC_WRTTIM1_BUSTURNCFG_Pos)                          /*!< 0x00080000 */

#define SMC_WRTTIM1_ASYNCACCCFG_Pos                                 (28U)
#define SMC_WRTTIM1_ASYNCACCCFG_Msk                                 (0x3UL << SMC_WRTTIM1_ASYNCACCCFG_Pos)                         /*!< 0x30000000 */
#define SMC_WRTTIM1_ASYNCACCCFG                                     SMC_WRTTIM1_ASYNCACCCFG_Msk                                    /*!<ACCMOD[1:0] bits (Access mode) */
#define SMC_WRTTIM1_ASYNCACCCFG_0                                   (0x1UL << SMC_WRTTIM1_ASYNCACCCFG_Pos)                         /*!< 0x10000000 */
#define SMC_WRTTIM1_ASYNCACCCFG_1                                   (0x2UL << SMC_WRTTIM1_ASYNCACCCFG_Pos)                         /*!< 0x20000000 */

/******************  Bit definition for SMC_WRTTIM2 register  ******************/
#define SMC_WRTTIM2_ADDRSETCFG_Pos                                  (0U)
#define SMC_WRTTIM2_ADDRSETCFG_Msk                                  (0xFUL << SMC_WRTTIM2_ADDRSETCFG_Pos)                          /*!< 0x0000000F */
#define SMC_WRTTIM2_ADDRSETCFG                                      SMC_WRTTIM2_ADDRSETCFG_Msk                                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define SMC_WRTTIM2_ADDRSETCFG_0                                    (0x1UL << SMC_WRTTIM2_ADDRSETCFG_Pos)                          /*!< 0x00000001 */
#define SMC_WRTTIM2_ADDRSETCFG_1                                    (0x2UL << SMC_WRTTIM2_ADDRSETCFG_Pos)                          /*!< 0x00000002 */
#define SMC_WRTTIM2_ADDRSETCFG_2                                    (0x4UL << SMC_WRTTIM2_ADDRSETCFG_Pos)                          /*!< 0x00000004 */
#define SMC_WRTTIM2_ADDRSETCFG_3                                    (0x8UL << SMC_WRTTIM2_ADDRSETCFG_Pos)                          /*!< 0x00000008 */

#define SMC_WRTTIM2_ADDRHLDCFG_Pos                                  (4U)
#define SMC_WRTTIM2_ADDRHLDCFG_Msk                                  (0xFUL << SMC_WRTTIM2_ADDRHLDCFG_Pos)                          /*!< 0x000000F0 */
#define SMC_WRTTIM2_ADDRHLDCFG                                      SMC_WRTTIM2_ADDRHLDCFG_Msk                                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define SMC_WRTTIM2_ADDRHLDCFG_0                                    (0x1UL << SMC_WRTTIM2_ADDRHLDCFG_Pos)                          /*!< 0x00000010 */
#define SMC_WRTTIM2_ADDRHLDCFG_1                                    (0x2UL << SMC_WRTTIM2_ADDRHLDCFG_Pos)                          /*!< 0x00000020 */
#define SMC_WRTTIM2_ADDRHLDCFG_2                                    (0x4UL << SMC_WRTTIM2_ADDRHLDCFG_Pos)                          /*!< 0x00000040 */
#define SMC_WRTTIM2_ADDRHLDCFG_3                                    (0x8UL << SMC_WRTTIM2_ADDRHLDCFG_Pos)                          /*!< 0x00000080 */

#define SMC_WRTTIM2_DATASETCFG_Pos                                  (8U)
#define SMC_WRTTIM2_DATASETCFG_Msk                                  (0xFFUL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x0000FF00 */
#define SMC_WRTTIM2_DATASETCFG                                      SMC_WRTTIM2_DATASETCFG_Msk                                     /*!<DATAST [7:0] bits (Data-phase duration) */
#define SMC_WRTTIM2_DATASETCFG_0                                    (0x01UL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x00000100 */
#define SMC_WRTTIM2_DATASETCFG_1                                    (0x02UL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x00000200 */
#define SMC_WRTTIM2_DATASETCFG_2                                    (0x04UL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x00000400 */
#define SMC_WRTTIM2_DATASETCFG_3                                    (0x08UL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x00000800 */
#define SMC_WRTTIM2_DATASETCFG_4                                    (0x10UL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x00001000 */
#define SMC_WRTTIM2_DATASETCFG_5                                    (0x20UL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x00002000 */
#define SMC_WRTTIM2_DATASETCFG_6                                    (0x40UL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x00004000 */
#define SMC_WRTTIM2_DATASETCFG_7                                    (0x80UL << SMC_WRTTIM2_DATASETCFG_Pos)                         /*!< 0x00008000 */

#define SMC_WRTTIM2_BUSTURNCFG_Pos                                  (16U)
#define SMC_WRTTIM2_BUSTURNCFG_Msk                                  (0xFUL << SMC_WRTTIM2_BUSTURNCFG_Pos)                          /*!< 0x000F0000 */
#define SMC_WRTTIM2_BUSTURNCFG                                      SMC_WRTTIM2_BUSTURNCFG_Msk                                     /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define SMC_WRTTIM2_BUSTURNCFG_0                                    (0x1UL << SMC_WRTTIM2_BUSTURNCFG_Pos)                          /*!< 0x00010000 */
#define SMC_WRTTIM2_BUSTURNCFG_1                                    (0x2UL << SMC_WRTTIM2_BUSTURNCFG_Pos)                          /*!< 0x00020000 */
#define SMC_WRTTIM2_BUSTURNCFG_2                                    (0x4UL << SMC_WRTTIM2_BUSTURNCFG_Pos)                          /*!< 0x00040000 */
#define SMC_WRTTIM2_BUSTURNCFG_3                                    (0x8UL << SMC_WRTTIM2_BUSTURNCFG_Pos)                          /*!< 0x00080000 */

#define SMC_WRTTIM2_ASYNCACCCFG_Pos                                 (28U)
#define SMC_WRTTIM2_ASYNCACCCFG_Msk                                 (0x3UL << SMC_WRTTIM2_ASYNCACCCFG_Pos)                         /*!< 0x30000000 */
#define SMC_WRTTIM2_ASYNCACCCFG                                     SMC_WRTTIM2_ASYNCACCCFG_Msk                                    /*!<ACCMOD[1:0] bits (Access mode) */
#define SMC_WRTTIM2_ASYNCACCCFG_0                                   (0x1UL << SMC_WRTTIM2_ASYNCACCCFG_Pos)                         /*!< 0x10000000 */
#define SMC_WRTTIM2_ASYNCACCCFG_1                                   (0x2UL << SMC_WRTTIM2_ASYNCACCCFG_Pos)                         /*!< 0x20000000 */

/******************  Bit definition for SMC_WRTTIM3 register  ******************/
#define SMC_WRTTIM3_ADDRSETCFG_Pos                                  (0U)
#define SMC_WRTTIM3_ADDRSETCFG_Msk                                  (0xFUL << SMC_WRTTIM3_ADDRSETCFG_Pos)                          /*!< 0x0000000F */
#define SMC_WRTTIM3_ADDRSETCFG                                      SMC_WRTTIM3_ADDRSETCFG_Msk                                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define SMC_WRTTIM3_ADDRSETCFG_0                                    (0x1UL << SMC_WRTTIM3_ADDRSETCFG_Pos)                          /*!< 0x00000001 */
#define SMC_WRTTIM3_ADDRSETCFG_1                                    (0x2UL << SMC_WRTTIM3_ADDRSETCFG_Pos)                          /*!< 0x00000002 */
#define SMC_WRTTIM3_ADDRSETCFG_2                                    (0x4UL << SMC_WRTTIM3_ADDRSETCFG_Pos)                          /*!< 0x00000004 */
#define SMC_WRTTIM3_ADDRSETCFG_3                                    (0x8UL << SMC_WRTTIM3_ADDRSETCFG_Pos)                          /*!< 0x00000008 */

#define SMC_WRTTIM3_ADDRHLDCFG_Pos                                  (4U)
#define SMC_WRTTIM3_ADDRHLDCFG_Msk                                  (0xFUL << SMC_WRTTIM3_ADDRHLDCFG_Pos)                          /*!< 0x000000F0 */
#define SMC_WRTTIM3_ADDRHLDCFG                                      SMC_WRTTIM3_ADDRHLDCFG_Msk                                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define SMC_WRTTIM3_ADDRHLDCFG_0                                    (0x1UL << SMC_WRTTIM3_ADDRHLDCFG_Pos)                          /*!< 0x00000010 */
#define SMC_WRTTIM3_ADDRHLDCFG_1                                    (0x2UL << SMC_WRTTIM3_ADDRHLDCFG_Pos)                          /*!< 0x00000020 */
#define SMC_WRTTIM3_ADDRHLDCFG_2                                    (0x4UL << SMC_WRTTIM3_ADDRHLDCFG_Pos)                          /*!< 0x00000040 */
#define SMC_WRTTIM3_ADDRHLDCFG_3                                    (0x8UL << SMC_WRTTIM3_ADDRHLDCFG_Pos)                          /*!< 0x00000080 */

#define SMC_WRTTIM3_DATASETCFG_Pos                                  (8U)
#define SMC_WRTTIM3_DATASETCFG_Msk                                  (0xFFUL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x0000FF00 */
#define SMC_WRTTIM3_DATASETCFG                                      SMC_WRTTIM3_DATASETCFG_Msk                                     /*!<DATAST [7:0] bits (Data-phase duration) */
#define SMC_WRTTIM3_DATASETCFG_0                                    (0x01UL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x00000100 */
#define SMC_WRTTIM3_DATASETCFG_1                                    (0x02UL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x00000200 */
#define SMC_WRTTIM3_DATASETCFG_2                                    (0x04UL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x00000400 */
#define SMC_WRTTIM3_DATASETCFG_3                                    (0x08UL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x00000800 */
#define SMC_WRTTIM3_DATASETCFG_4                                    (0x10UL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x00001000 */
#define SMC_WRTTIM3_DATASETCFG_5                                    (0x20UL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x00002000 */
#define SMC_WRTTIM3_DATASETCFG_6                                    (0x40UL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x00004000 */
#define SMC_WRTTIM3_DATASETCFG_7                                    (0x80UL << SMC_WRTTIM3_DATASETCFG_Pos)                         /*!< 0x00008000 */

#define SMC_WRTTIM3_BUSTURNCFG_Pos                                  (16U)
#define SMC_WRTTIM3_BUSTURNCFG_Msk                                  (0xFUL << SMC_WRTTIM3_BUSTURNCFG_Pos)                          /*!< 0x000F0000 */
#define SMC_WRTTIM3_BUSTURNCFG                                      SMC_WRTTIM3_BUSTURNCFG_Msk                                     /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define SMC_WRTTIM3_BUSTURNCFG_0                                    (0x1UL << SMC_WRTTIM3_BUSTURNCFG_Pos)                          /*!< 0x00010000 */
#define SMC_WRTTIM3_BUSTURNCFG_1                                    (0x2UL << SMC_WRTTIM3_BUSTURNCFG_Pos)                          /*!< 0x00020000 */
#define SMC_WRTTIM3_BUSTURNCFG_2                                    (0x4UL << SMC_WRTTIM3_BUSTURNCFG_Pos)                          /*!< 0x00040000 */
#define SMC_WRTTIM3_BUSTURNCFG_3                                    (0x8UL << SMC_WRTTIM3_BUSTURNCFG_Pos)                          /*!< 0x00080000 */

#define SMC_WRTTIM3_ASYNCACCCFG_Pos                                 (28U)
#define SMC_WRTTIM3_ASYNCACCCFG_Msk                                 (0x3UL << SMC_WRTTIM3_ASYNCACCCFG_Pos)                         /*!< 0x30000000 */
#define SMC_WRTTIM3_ASYNCACCCFG                                     SMC_WRTTIM3_ASYNCACCCFG_Msk                                    /*!<ACCMOD[1:0] bits (Access mode) */
#define SMC_WRTTIM3_ASYNCACCCFG_0                                   (0x1UL << SMC_WRTTIM3_ASYNCACCCFG_Pos)                         /*!< 0x10000000 */
#define SMC_WRTTIM3_ASYNCACCCFG_1                                   (0x2UL << SMC_WRTTIM3_ASYNCACCCFG_Pos)                         /*!< 0x20000000 */

/******************  Bit definition for SMC_WRTTIM4 register  ******************/
#define SMC_WRTTIM4_ADDRSETCFG_Pos                                  (0U)
#define SMC_WRTTIM4_ADDRSETCFG_Msk                                  (0xFUL << SMC_WRTTIM4_ADDRSETCFG_Pos)                          /*!< 0x0000000F */
#define SMC_WRTTIM4_ADDRSETCFG                                      SMC_WRTTIM4_ADDRSETCFG_Msk                                     /*!<ADDSET[3:0] bits (Address setup phase duration) */
#define SMC_WRTTIM4_ADDRSETCFG_0                                    (0x1UL << SMC_WRTTIM4_ADDRSETCFG_Pos)                          /*!< 0x00000001 */
#define SMC_WRTTIM4_ADDRSETCFG_1                                    (0x2UL << SMC_WRTTIM4_ADDRSETCFG_Pos)                          /*!< 0x00000002 */
#define SMC_WRTTIM4_ADDRSETCFG_2                                    (0x4UL << SMC_WRTTIM4_ADDRSETCFG_Pos)                          /*!< 0x00000004 */
#define SMC_WRTTIM4_ADDRSETCFG_3                                    (0x8UL << SMC_WRTTIM4_ADDRSETCFG_Pos)                          /*!< 0x00000008 */

#define SMC_WRTTIM4_ADDRHLDCFG_Pos                                  (4U)
#define SMC_WRTTIM4_ADDRHLDCFG_Msk                                  (0xFUL << SMC_WRTTIM4_ADDRHLDCFG_Pos)                          /*!< 0x000000F0 */
#define SMC_WRTTIM4_ADDRHLDCFG                                      SMC_WRTTIM4_ADDRHLDCFG_Msk                                     /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
#define SMC_WRTTIM4_ADDRHLDCFG_0                                    (0x1UL << SMC_WRTTIM4_ADDRHLDCFG_Pos)                          /*!< 0x00000010 */
#define SMC_WRTTIM4_ADDRHLDCFG_1                                    (0x2UL << SMC_WRTTIM4_ADDRHLDCFG_Pos)                          /*!< 0x00000020 */
#define SMC_WRTTIM4_ADDRHLDCFG_2                                    (0x4UL << SMC_WRTTIM4_ADDRHLDCFG_Pos)                          /*!< 0x00000040 */
#define SMC_WRTTIM4_ADDRHLDCFG_3                                    (0x8UL << SMC_WRTTIM4_ADDRHLDCFG_Pos)                          /*!< 0x00000080 */

#define SMC_WRTTIM4_DATASETCFG_Pos                                  (8U)
#define SMC_WRTTIM4_DATASETCFG_Msk                                  (0xFFUL << SMC_WRTTIM4_DATASETCFG_Pos)                         /*!< 0x0000FF00 */
#define SMC_WRTTIM4_DATASETCFG                                      SMC_WRTTIM4_DATASETCFG_Msk                                     /*!<DATAST [3:0] bits (Data-phase duration) */
#define SMC_WRTTIM4_DATASETCFG_0                                    0x00000100U                                                    /*!<Bit 0 */
#define SMC_WRTTIM4_DATASETCFG_1                                    0x00000200U                                                    /*!<Bit 1 */
#define SMC_WRTTIM4_DATASETCFG_2                                    0x00000400U                                                    /*!<Bit 2 */
#define SMC_WRTTIM4_DATASETCFG_3                                    0x00000800U                                                    /*!<Bit 3 */
#define SMC_WRTTIM4_DATASETCFG_4                                    0x00001000U                                                    /*!<Bit 4 */
#define SMC_WRTTIM4_DATASETCFG_5                                    0x00002000U                                                    /*!<Bit 5 */
#define SMC_WRTTIM4_DATASETCFG_6                                    0x00004000U                                                    /*!<Bit 6 */
#define SMC_WRTTIM4_DATASETCFG_7                                    0x00008000U                                                    /*!<Bit 7 */

#define SMC_WRTTIM4_BUSTURNCFG_Pos                                  (16U)
#define SMC_WRTTIM4_BUSTURNCFG_Msk                                  (0xFUL << SMC_WRTTIM4_BUSTURNCFG_Pos)                          /*!< 0x000F0000 */
#define SMC_WRTTIM4_BUSTURNCFG                                      SMC_WRTTIM4_BUSTURNCFG_Msk                                     /*!<BUSTURN[3:0] bits (Bus turnaround duration) */
#define SMC_WRTTIM4_BUSTURNCFG_0                                    (0x1UL << SMC_WRTTIM4_BUSTURNCFG_Pos)                          /*!< 0x00010000 */
#define SMC_WRTTIM4_BUSTURNCFG_1                                    (0x2UL << SMC_WRTTIM4_BUSTURNCFG_Pos)                          /*!< 0x00020000 */
#define SMC_WRTTIM4_BUSTURNCFG_2                                    (0x4UL << SMC_WRTTIM4_BUSTURNCFG_Pos)                          /*!< 0x00040000 */
#define SMC_WRTTIM4_BUSTURNCFG_3                                    (0x8UL << SMC_WRTTIM4_BUSTURNCFG_Pos)                          /*!< 0x00080000 */

#define SMC_WRTTIM4_ASYNCACCCFG_Pos                                 (28U)
#define SMC_WRTTIM4_ASYNCACCCFG_Msk                                 (0x3UL << SMC_WRTTIM4_ASYNCACCCFG_Pos)                         /*!< 0x30000000 */
#define SMC_WRTTIM4_ASYNCACCCFG                                     SMC_WRTTIM4_ASYNCACCCFG_Msk                                    /*!<ACCMOD[1:0] bits (Access mode) */
#define SMC_WRTTIM4_ASYNCACCCFG_0                                   (0x1UL << SMC_WRTTIM4_ASYNCACCCFG_Pos)                         /*!< 0x10000000 */
#define SMC_WRTTIM4_ASYNCACCCFG_1                                   (0x2UL << SMC_WRTTIM4_ASYNCACCCFG_Pos)                         /*!< 0x20000000 */

/******************  Bit definition for SMC_CTRL2 register  *******************/
#define SMC_CTRL2_WAITFEN_Pos                                       (1U)
#define SMC_CTRL2_WAITFEN_Msk                                       (0x1UL << SMC_CTRL2_WAITFEN_Pos)                               /*!< 0x00000002 */
#define SMC_CTRL2_WAITFEN                                           SMC_CTRL2_WAITFEN_Msk                                          /*!<Wait feature enable bit */
#define SMC_CTRL2_MBKEN_Pos                                         (2U)
#define SMC_CTRL2_MBKEN_Msk                                         (0x1UL << SMC_CTRL2_MBKEN_Pos)                                 /*!< 0x00000004 */
#define SMC_CTRL2_MBKEN                                             SMC_CTRL2_MBKEN_Msk                                            /*!<PC Card/NAND Flash memory bank enable bit */
#define SMC_CTRL2_MTYPECFG_Pos                                      (3U)
#define SMC_CTRL2_MTYPECFG_Msk                                      (0x1UL << SMC_CTRL2_MTYPECFG_Pos)                              /*!< 0x00000008 */
#define SMC_CTRL2_MTYPECFG                                          SMC_CTRL2_MTYPECFG_Msk                                         /*!<Memory type */

#define SMC_CTRL2_DBWIDCFG_Pos                                      (4U)
#define SMC_CTRL2_DBWIDCFG_Msk                                      (0x3UL << SMC_CTRL2_DBWIDCFG_Pos)                              /*!< 0x00000030 */
#define SMC_CTRL2_DBWIDCFG                                          SMC_CTRL2_DBWIDCFG_Msk                                         /*!<PWID[1:0] bits (NAND Flash databus width) */
#define SMC_CTRL2_DBWIDCFG_0                                        (0x1UL << SMC_CTRL2_DBWIDCFG_Pos)                              /*!< 0x00000010 */
#define SMC_CTRL2_DBWIDCFG_1                                        (0x2UL << SMC_CTRL2_DBWIDCFG_Pos)                              /*!< 0x00000020 */

#define SMC_CTRL2_ECCEN_Pos                                         (6U)
#define SMC_CTRL2_ECCEN_Msk                                         (0x1UL << SMC_CTRL2_ECCEN_Pos)                                 /*!< 0x00000040 */
#define SMC_CTRL2_ECCEN                                             SMC_CTRL2_ECCEN_Msk                                            /*!<ECC computation logic enable bit */

#define SMC_CTRL2_C2RDCFG_Pos                                       (9U)
#define SMC_CTRL2_C2RDCFG_Msk                                       (0xFUL << SMC_CTRL2_C2RDCFG_Pos)                               /*!< 0x00001E00 */
#define SMC_CTRL2_C2RDCFG                                           SMC_CTRL2_C2RDCFG_Msk                                          /*!<TCLR[3:0] bits (CLE to RE delay) */
#define SMC_CTRL2_C2RDCFG_0                                         (0x1UL << SMC_CTRL2_C2RDCFG_Pos)                               /*!< 0x00000200 */
#define SMC_CTRL2_C2RDCFG_1                                         (0x2UL << SMC_CTRL2_C2RDCFG_Pos)                               /*!< 0x00000400 */
#define SMC_CTRL2_C2RDCFG_2                                         (0x4UL << SMC_CTRL2_C2RDCFG_Pos)                               /*!< 0x00000800 */
#define SMC_CTRL2_C2RDCFG_3                                         (0x8UL << SMC_CTRL2_C2RDCFG_Pos)                               /*!< 0x00001000 */

#define SMC_CTRL2_A2RDCFG_Pos                                       (13U)
#define SMC_CTRL2_A2RDCFG_Msk                                       (0xFUL << SMC_CTRL2_A2RDCFG_Pos)                               /*!< 0x0001E000 */
#define SMC_CTRL2_A2RDCFG                                           SMC_CTRL2_A2RDCFG_Msk                                          /*!<TAR[3:0] bits (ALE to RE delay) */
#define SMC_CTRL2_A2RDCFG_0                                         (0x1UL << SMC_CTRL2_A2RDCFG_Pos)                               /*!< 0x00002000 */
#define SMC_CTRL2_A2RDCFG_1                                         (0x2UL << SMC_CTRL2_A2RDCFG_Pos)                               /*!< 0x00004000 */
#define SMC_CTRL2_A2RDCFG_2                                         (0x4UL << SMC_CTRL2_A2RDCFG_Pos)                               /*!< 0x00008000 */
#define SMC_CTRL2_A2RDCFG_3                                         (0x8UL << SMC_CTRL2_A2RDCFG_Pos)                               /*!< 0x00010000 */

#define SMC_CTRL2_ECCPSCFG_Pos                                      (17U)
#define SMC_CTRL2_ECCPSCFG_Msk                                      (0x7UL << SMC_CTRL2_ECCPSCFG_Pos)                              /*!< 0x000E0000 */
#define SMC_CTRL2_ECCPSCFG                                          SMC_CTRL2_ECCPSCFG_Msk                                         /*!<ECCPS[1:0] bits (ECC page size) */
#define SMC_CTRL2_ECCPSCFG_0                                        (0x1UL << SMC_CTRL2_ECCPSCFG_Pos)                              /*!< 0x00020000 */
#define SMC_CTRL2_ECCPSCFG_1                                        (0x2UL << SMC_CTRL2_ECCPSCFG_Pos)                              /*!< 0x00040000 */
#define SMC_CTRL2_ECCPSCFG_2                                        (0x4UL << SMC_CTRL2_ECCPSCFG_Pos)                              /*!< 0x00080000 */

/******************  Bit definition for SMC_CTRL3 register  *******************/
#define SMC_CTRL3_WAITFEN_Pos                                       (1U)
#define SMC_CTRL3_WAITFEN_Msk                                       (0x1UL << SMC_CTRL3_WAITFEN_Pos)                               /*!< 0x00000002 */
#define SMC_CTRL3_WAITFEN                                           SMC_CTRL3_WAITFEN_Msk                                          /*!<Wait feature enable bit */
#define SMC_CTRL3_MBKEN_Pos                                         (2U)
#define SMC_CTRL3_MBKEN_Msk                                         (0x1UL << SMC_CTRL3_MBKEN_Pos)                                 /*!< 0x00000004 */
#define SMC_CTRL3_MBKEN                                             SMC_CTRL3_MBKEN_Msk                                            /*!<PC Card/NAND Flash memory bank enable bit */
#define SMC_CTRL3_MTYPECFG_Pos                                      (3U)
#define SMC_CTRL3_MTYPECFG_Msk                                      (0x1UL << SMC_CTRL3_MTYPECFG_Pos)                              /*!< 0x00000008 */
#define SMC_CTRL3_MTYPECFG                                          SMC_CTRL3_MTYPECFG_Msk                                         /*!<Memory type */

#define SMC_CTRL3_DBWIDCFG_Pos                                      (4U)
#define SMC_CTRL3_DBWIDCFG_Msk                                      (0x3UL << SMC_CTRL3_DBWIDCFG_Pos)                              /*!< 0x00000030 */
#define SMC_CTRL3_DBWIDCFG                                          SMC_CTRL3_DBWIDCFG_Msk                                         /*!<PWID[1:0] bits (NAND Flash databus width) */
#define SMC_CTRL3_DBWIDCFG_0                                        (0x1UL << SMC_CTRL3_DBWIDCFG_Pos)                              /*!< 0x00000010 */
#define SMC_CTRL3_DBWIDCFG_1                                        (0x2UL << SMC_CTRL3_DBWIDCFG_Pos)                              /*!< 0x00000020 */

#define SMC_CTRL3_ECCEN_Pos                                         (6U)
#define SMC_CTRL3_ECCEN_Msk                                         (0x1UL << SMC_CTRL3_ECCEN_Pos)                                 /*!< 0x00000040 */
#define SMC_CTRL3_ECCEN                                             SMC_CTRL3_ECCEN_Msk                                            /*!<ECC computation logic enable bit */

#define SMC_CTRL3_C2RDCFG_Pos                                       (9U)
#define SMC_CTRL3_C2RDCFG_Msk                                       (0xFUL << SMC_CTRL3_C2RDCFG_Pos)                               /*!< 0x00001E00 */
#define SMC_CTRL3_C2RDCFG                                           SMC_CTRL3_C2RDCFG_Msk                                          /*!<TCLR[3:0] bits (CLE to RE delay) */
#define SMC_CTRL3_C2RDCFG_0                                         (0x1UL << SMC_CTRL3_C2RDCFG_Pos)                               /*!< 0x00000200 */
#define SMC_CTRL3_C2RDCFG_1                                         (0x2UL << SMC_CTRL3_C2RDCFG_Pos)                               /*!< 0x00000400 */
#define SMC_CTRL3_C2RDCFG_2                                         (0x4UL << SMC_CTRL3_C2RDCFG_Pos)                               /*!< 0x00000800 */
#define SMC_CTRL3_C2RDCFG_3                                         (0x8UL << SMC_CTRL3_C2RDCFG_Pos)                               /*!< 0x00001000 */

#define SMC_CTRL3_A2RDCFG_Pos                                       (13U)
#define SMC_CTRL3_A2RDCFG_Msk                                       (0xFUL << SMC_CTRL3_A2RDCFG_Pos)                               /*!< 0x0001E000 */
#define SMC_CTRL3_A2RDCFG                                           SMC_CTRL3_A2RDCFG_Msk                                          /*!<TAR[3:0] bits (ALE to RE delay) */
#define SMC_CTRL3_A2RDCFG_0                                         (0x1UL << SMC_CTRL3_A2RDCFG_Pos)                               /*!< 0x00002000 */
#define SMC_CTRL3_A2RDCFG_1                                         (0x2UL << SMC_CTRL3_A2RDCFG_Pos)                               /*!< 0x00004000 */
#define SMC_CTRL3_A2RDCFG_2                                         (0x4UL << SMC_CTRL3_A2RDCFG_Pos)                               /*!< 0x00008000 */
#define SMC_CTRL3_A2RDCFG_3                                         (0x8UL << SMC_CTRL3_A2RDCFG_Pos)                               /*!< 0x00010000 */

#define SMC_CTRL3_ECCPSCFG_Pos                                      (17U)
#define SMC_CTRL3_ECCPSCFG_Msk                                      (0x7UL << SMC_CTRL3_ECCPSCFG_Pos)                              /*!< 0x000E0000 */
#define SMC_CTRL3_ECCPSCFG                                          SMC_CTRL3_ECCPSCFG_Msk                                         /*!<ECCPS[2:0] bits (ECC page size) */
#define SMC_CTRL3_ECCPSCFG_0                                        (0x1UL << SMC_CTRL3_ECCPSCFG_Pos)                              /*!< 0x00020000 */
#define SMC_CTRL3_ECCPSCFG_1                                        (0x2UL << SMC_CTRL3_ECCPSCFG_Pos)                              /*!< 0x00040000 */
#define SMC_CTRL3_ECCPSCFG_2                                        (0x4UL << SMC_CTRL3_ECCPSCFG_Pos)                              /*!< 0x00080000 */

/******************  Bit definition for SMC_CTRL4 register  *******************/
#define SMC_CTRL4_WAITFEN_Pos                                       (1U)
#define SMC_CTRL4_WAITFEN_Msk                                       (0x1UL << SMC_CTRL4_WAITFEN_Pos)                               /*!< 0x00000002 */
#define SMC_CTRL4_WAITFEN                                           SMC_CTRL4_WAITFEN_Msk                                          /*!<Wait feature enable bit */
#define SMC_CTRL4_MBKEN_Pos                                         (2U)
#define SMC_CTRL4_MBKEN_Msk                                         (0x1UL << SMC_CTRL4_MBKEN_Pos)                                 /*!< 0x00000004 */
#define SMC_CTRL4_MBKEN                                             SMC_CTRL4_MBKEN_Msk                                            /*!<PC Card/NAND Flash memory bank enable bit */
#define SMC_CTRL4_MTYPECFG_Pos                                      (3U)
#define SMC_CTRL4_MTYPECFG_Msk                                      (0x1UL << SMC_CTRL4_MTYPECFG_Pos)                              /*!< 0x00000008 */
#define SMC_CTRL4_MTYPECFG                                          SMC_CTRL4_MTYPECFG_Msk                                         /*!<Memory type */

#define SMC_CTRL4_DBWIDCFG_Pos                                      (4U)
#define SMC_CTRL4_DBWIDCFG_Msk                                      (0x3UL << SMC_CTRL4_DBWIDCFG_Pos)                              /*!< 0x00000030 */
#define SMC_CTRL4_DBWIDCFG                                          SMC_CTRL4_DBWIDCFG_Msk                                         /*!<PWID[1:0] bits (NAND Flash databus width) */
#define SMC_CTRL4_DBWIDCFG_0                                        (0x1UL << SMC_CTRL4_DBWIDCFG_Pos)                              /*!< 0x00000010 */
#define SMC_CTRL4_DBWIDCFG_1                                        (0x2UL << SMC_CTRL4_DBWIDCFG_Pos)                              /*!< 0x00000020 */

#define SMC_CTRL4_ECCEN_Pos                                         (6U)
#define SMC_CTRL4_ECCEN_Msk                                         (0x1UL << SMC_CTRL4_ECCEN_Pos)                                 /*!< 0x00000040 */
#define SMC_CTRL4_ECCEN                                             SMC_CTRL4_ECCEN_Msk                                            /*!<ECC computation logic enable bit */

#define SMC_CTRL4_C2RDCFG_Pos                                       (9U)
#define SMC_CTRL4_C2RDCFG_Msk                                       (0xFUL << SMC_CTRL4_C2RDCFG_Pos)                               /*!< 0x00001E00 */
#define SMC_CTRL4_C2RDCFG                                           SMC_CTRL4_C2RDCFG_Msk                                          /*!<TCLR[3:0] bits (CLE to RE delay) */
#define SMC_CTRL4_C2RDCFG_0                                         (0x1UL << SMC_CTRL4_C2RDCFG_Pos)                               /*!< 0x00000200 */
#define SMC_CTRL4_C2RDCFG_1                                         (0x2UL << SMC_CTRL4_C2RDCFG_Pos)                               /*!< 0x00000400 */
#define SMC_CTRL4_C2RDCFG_2                                         (0x4UL << SMC_CTRL4_C2RDCFG_Pos)                               /*!< 0x00000800 */
#define SMC_CTRL4_C2RDCFG_3                                         (0x8UL << SMC_CTRL4_C2RDCFG_Pos)                               /*!< 0x00001000 */

#define SMC_CTRL4_A2RDCFG_Pos                                       (13U)
#define SMC_CTRL4_A2RDCFG_Msk                                       (0xFUL << SMC_CTRL4_A2RDCFG_Pos)                               /*!< 0x0001E000 */
#define SMC_CTRL4_A2RDCFG                                           SMC_CTRL4_A2RDCFG_Msk                                          /*!<TAR[3:0] bits (ALE to RE delay) */
#define SMC_CTRL4_A2RDCFG_0                                         (0x1UL << SMC_CTRL4_A2RDCFG_Pos)                               /*!< 0x00002000 */
#define SMC_CTRL4_A2RDCFG_1                                         (0x2UL << SMC_CTRL4_A2RDCFG_Pos)                               /*!< 0x00004000 */
#define SMC_CTRL4_A2RDCFG_2                                         (0x4UL << SMC_CTRL4_A2RDCFG_Pos)                               /*!< 0x00008000 */
#define SMC_CTRL4_A2RDCFG_3                                         (0x8UL << SMC_CTRL4_A2RDCFG_Pos)                               /*!< 0x00010000 */

#define SMC_CTRL4_ECCPSCFG_Pos                                      (17U)
#define SMC_CTRL4_ECCPSCFG_Msk                                      (0x7UL << SMC_CTRL4_ECCPSCFG_Pos)                              /*!< 0x000E0000 */
#define SMC_CTRL4_ECCPSCFG                                          SMC_CTRL4_ECCPSCFG_Msk                                         /*!<ECCPS[2:0] bits (ECC page size) */
#define SMC_CTRL4_ECCPSCFG_0                                        (0x1UL << SMC_CTRL4_ECCPSCFG_Pos)                              /*!< 0x00020000 */
#define SMC_CTRL4_ECCPSCFG_1                                        (0x2UL << SMC_CTRL4_ECCPSCFG_Pos)                              /*!< 0x00040000 */
#define SMC_CTRL4_ECCPSCFG_2                                        (0x4UL << SMC_CTRL4_ECCPSCFG_Pos)                              /*!< 0x00080000 */

/*******************  Bit definition for SMC_STSINT2 register  *******************/
#define SMC_STSINT2_IREFLG_Pos                                      (0U)
#define SMC_STSINT2_IREFLG_Msk                                      (0x1UL << SMC_STSINT2_IREFLG_Pos)                              /*!< 0x00000001 */
#define SMC_STSINT2_IREFLG                                          SMC_STSINT2_IREFLG_Msk                                         /*!<Interrupt Rising Edge status                */
#define SMC_STSINT2_IHLFLG_Pos                                      (1U)
#define SMC_STSINT2_IHLFLG_Msk                                      (0x1UL << SMC_STSINT2_IHLFLG_Pos)                              /*!< 0x00000002 */
#define SMC_STSINT2_IHLFLG                                          SMC_STSINT2_IHLFLG_Msk                                         /*!<Interrupt Level status                      */
#define SMC_STSINT2_IFEFLG_Pos                                      (2U)
#define SMC_STSINT2_IFEFLG_Msk                                      (0x1UL << SMC_STSINT2_IFEFLG_Pos)                              /*!< 0x00000004 */
#define SMC_STSINT2_IFEFLG                                          SMC_STSINT2_IFEFLG_Msk                                         /*!<Interrupt Falling Edge status               */
#define SMC_STSINT2_IREDEN_Pos                                      (3U)
#define SMC_STSINT2_IREDEN_Msk                                      (0x1UL << SMC_STSINT2_IREDEN_Pos)                              /*!< 0x00000008 */
#define SMC_STSINT2_IREDEN                                          SMC_STSINT2_IREDEN_Msk                                         /*!<Interrupt Rising Edge detection Enable bit  */
#define SMC_STSINT2_IHLDEN_Pos                                      (4U)
#define SMC_STSINT2_IHLDEN_Msk                                      (0x1UL << SMC_STSINT2_IHLDEN_Pos)                              /*!< 0x00000010 */
#define SMC_STSINT2_IHLDEN                                          SMC_STSINT2_IHLDEN_Msk                                         /*!<Interrupt Level detection Enable bit        */
#define SMC_STSINT2_IFEDEN_Pos                                      (5U)
#define SMC_STSINT2_IFEDEN_Msk                                      (0x1UL << SMC_STSINT2_IFEDEN_Pos)                              /*!< 0x00000020 */
#define SMC_STSINT2_IFEDEN                                          SMC_STSINT2_IFEDEN_Msk                                         /*!<Interrupt Falling Edge detection Enable bit */
#define SMC_STSINT2_FEFLG_Pos                                       (6U)
#define SMC_STSINT2_FEFLG_Msk                                       (0x1UL << SMC_STSINT2_FEFLG_Pos)                               /*!< 0x00000040 */
#define SMC_STSINT2_FEFLG                                           SMC_STSINT2_FEFLG_Msk                                          /*!<FIFO empty */

/*******************  Bit definition for SMC_STSINT3 register  *******************/
#define SMC_STSINT3_IREFLG_Pos                                      (0U)
#define SMC_STSINT3_IREFLG_Msk                                      (0x1UL << SMC_STSINT3_IREFLG_Pos)                              /*!< 0x00000001 */
#define SMC_STSINT3_IREFLG                                          SMC_STSINT3_IREFLG_Msk                                         /*!<Interrupt Rising Edge status                */
#define SMC_STSINT3_IHLFLG_Pos                                      (1U)
#define SMC_STSINT3_IHLFLG_Msk                                      (0x1UL << SMC_STSINT3_IHLFLG_Pos)                              /*!< 0x00000002 */
#define SMC_STSINT3_IHLFLG                                          SMC_STSINT3_IHLFLG_Msk                                         /*!<Interrupt Level status                      */
#define SMC_STSINT3_IFEFLG_Pos                                      (2U)
#define SMC_STSINT3_IFEFLG_Msk                                      (0x1UL << SMC_STSINT3_IFEFLG_Pos)                              /*!< 0x00000004 */
#define SMC_STSINT3_IFEFLG                                          SMC_STSINT3_IFEFLG_Msk                                         /*!<Interrupt Falling Edge status               */
#define SMC_STSINT3_IREDEN_Pos                                      (3U)
#define SMC_STSINT3_IREDEN_Msk                                      (0x1UL << SMC_STSINT3_IREDEN_Pos)                              /*!< 0x00000008 */
#define SMC_STSINT3_IREDEN                                          SMC_STSINT3_IREDEN_Msk                                         /*!<Interrupt Rising Edge detection Enable bit  */
#define SMC_STSINT3_IHLDEN_Pos                                      (4U)
#define SMC_STSINT3_IHLDEN_Msk                                      (0x1UL << SMC_STSINT3_IHLDEN_Pos)                              /*!< 0x00000010 */
#define SMC_STSINT3_IHLDEN                                          SMC_STSINT3_IHLDEN_Msk                                         /*!<Interrupt Level detection Enable bit        */
#define SMC_STSINT3_IFEDEN_Pos                                      (5U)
#define SMC_STSINT3_IFEDEN_Msk                                      (0x1UL << SMC_STSINT3_IFEDEN_Pos)                              /*!< 0x00000020 */
#define SMC_STSINT3_IFEDEN                                          SMC_STSINT3_IFEDEN_Msk                                         /*!<Interrupt Falling Edge detection Enable bit */
#define SMC_STSINT3_FEFLG_Pos                                       (6U)
#define SMC_STSINT3_FEFLG_Msk                                       (0x1UL << SMC_STSINT3_FEFLG_Pos)                               /*!< 0x00000040 */
#define SMC_STSINT3_FEFLG                                           SMC_STSINT3_FEFLG_Msk                                          /*!<FIFO empty */

/*******************  Bit definition for SMC_STSINT4 register  *******************/
#define SMC_STSINT4_IREFLG_Pos                                      (0U)
#define SMC_STSINT4_IREFLG_Msk                                      (0x1UL << SMC_STSINT4_IREFLG_Pos)                              /*!< 0x00000001 */
#define SMC_STSINT4_IREFLG                                          SMC_STSINT4_IREFLG_Msk                                         /*!<Interrupt Rising Edge status                 */
#define SMC_STSINT4_IHLFLG_Pos                                      (1U)
#define SMC_STSINT4_IHLFLG_Msk                                      (0x1UL << SMC_STSINT4_IHLFLG_Pos)                              /*!< 0x00000002 */
#define SMC_STSINT4_IHLFLG                                          SMC_STSINT4_IHLFLG_Msk                                         /*!<Interrupt Level status                       */
#define SMC_STSINT4_IFEFLG_Pos                                      (2U)
#define SMC_STSINT4_IFEFLG_Msk                                      (0x1UL << SMC_STSINT4_IFEFLG_Pos)                              /*!< 0x00000004 */
#define SMC_STSINT4_IFEFLG                                          SMC_STSINT4_IFEFLG_Msk                                         /*!<Interrupt Falling Edge status                */
#define SMC_STSINT4_IREDEN_Pos                                      (3U)
#define SMC_STSINT4_IREDEN_Msk                                      (0x1UL << SMC_STSINT4_IREDEN_Pos)                              /*!< 0x00000008 */
#define SMC_STSINT4_IREDEN                                          SMC_STSINT4_IREDEN_Msk                                         /*!<Interrupt Rising Edge detection Enable bit   */
#define SMC_STSINT4_IHLDEN_Pos                                      (4U)
#define SMC_STSINT4_IHLDEN_Msk                                      (0x1UL << SMC_STSINT4_IHLDEN_Pos)                              /*!< 0x00000010 */
#define SMC_STSINT4_IHLDEN                                          SMC_STSINT4_IHLDEN_Msk                                         /*!<Interrupt Level detection Enable bit         */
#define SMC_STSINT4_IFEDEN_Pos                                      (5U)
#define SMC_STSINT4_IFEDEN_Msk                                      (0x1UL << SMC_STSINT4_IFEDEN_Pos)                              /*!< 0x00000020 */
#define SMC_STSINT4_IFEDEN                                          SMC_STSINT4_IFEDEN_Msk                                         /*!<Interrupt Falling Edge detection Enable bit  */
#define SMC_STSINT4_FEFLG_Pos                                       (6U)
#define SMC_STSINT4_FEFLG_Msk                                       (0x1UL << SMC_STSINT4_FEFLG_Pos)                               /*!< 0x00000040 */
#define SMC_STSINT4_FEFLG                                           SMC_STSINT4_FEFLG_Msk                                          /*!<FIFO empty */

/******************  Bit definition for SMC_CMSTIM2 register  ******************/
#define SMC_CMSTIM2_SET2_Pos                                        (0U)
#define SMC_CMSTIM2_SET2_Msk                                        (0xFFUL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x000000FF */
#define SMC_CMSTIM2_SET2                                            SMC_CMSTIM2_SET2_Msk                                           /*!<MEMSET2[7:0] bits (Common memory 2 setup time) */
#define SMC_CMSTIM2_SET2_0                                          (0x01UL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x00000001 */
#define SMC_CMSTIM2_SET2_1                                          (0x02UL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x00000002 */
#define SMC_CMSTIM2_SET2_2                                          (0x04UL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x00000004 */
#define SMC_CMSTIM2_SET2_3                                          (0x08UL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x00000008 */
#define SMC_CMSTIM2_SET2_4                                          (0x10UL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x00000010 */
#define SMC_CMSTIM2_SET2_5                                          (0x20UL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x00000020 */
#define SMC_CMSTIM2_SET2_6                                          (0x40UL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x00000040 */
#define SMC_CMSTIM2_SET2_7                                          (0x80UL << SMC_CMSTIM2_SET2_Pos)                               /*!< 0x00000080 */

#define SMC_CMSTIM2_WAIT2_Pos                                       (8U)
#define SMC_CMSTIM2_WAIT2_Msk                                       (0xFFUL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x0000FF00 */
#define SMC_CMSTIM2_WAIT2                                           SMC_CMSTIM2_WAIT2_Msk                                          /*!<MEMWAIT2[7:0] bits (Common memory 2 wait time) */
#define SMC_CMSTIM2_WAIT2_0                                         (0x01UL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x00000100 */
#define SMC_CMSTIM2_WAIT2_1                                         (0x02UL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x00000200 */
#define SMC_CMSTIM2_WAIT2_2                                         (0x04UL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x00000400 */
#define SMC_CMSTIM2_WAIT2_3                                         (0x08UL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x00000800 */
#define SMC_CMSTIM2_WAIT2_4                                         (0x10UL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x00001000 */
#define SMC_CMSTIM2_WAIT2_5                                         (0x20UL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x00002000 */
#define SMC_CMSTIM2_WAIT2_6                                         (0x40UL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x00004000 */
#define SMC_CMSTIM2_WAIT2_7                                         (0x80UL << SMC_CMSTIM2_WAIT2_Pos)                              /*!< 0x00008000 */

#define SMC_CMSTIM2_HLD2_Pos                                        (16U)
#define SMC_CMSTIM2_HLD2_Msk                                        (0xFFUL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00FF0000 */
#define SMC_CMSTIM2_HLD2                                            SMC_CMSTIM2_HLD2_Msk                                           /*!<MEMHOLD2[7:0] bits (Common memory 2 hold time) */
#define SMC_CMSTIM2_HLD2_0                                          (0x01UL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00010000 */
#define SMC_CMSTIM2_HLD2_1                                          (0x02UL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00020000 */
#define SMC_CMSTIM2_HLD2_2                                          (0x04UL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00040000 */
#define SMC_CMSTIM2_HLD2_3                                          (0x08UL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00080000 */
#define SMC_CMSTIM2_HLD2_4                                          (0x10UL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00100000 */
#define SMC_CMSTIM2_HLD2_5                                          (0x20UL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00200000 */
#define SMC_CMSTIM2_HLD2_6                                          (0x40UL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00400000 */
#define SMC_CMSTIM2_HLD2_7                                          (0x80UL << SMC_CMSTIM2_HLD2_Pos)                               /*!< 0x00800000 */

#define SMC_CMSTIM2_HIZ2_Pos                                        (24U)
#define SMC_CMSTIM2_HIZ2_Msk                                        (0xFFUL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0xFF000000 */
#define SMC_CMSTIM2_HIZ2                                            SMC_CMSTIM2_HIZ2_Msk                                           /*!<MEMHIZ2[7:0] bits (Common memory 2 databus HiZ time) */
#define SMC_CMSTIM2_HIZ2_0                                          (0x01UL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0x01000000 */
#define SMC_CMSTIM2_HIZ2_1                                          (0x02UL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0x02000000 */
#define SMC_CMSTIM2_HIZ2_2                                          (0x04UL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0x04000000 */
#define SMC_CMSTIM2_HIZ2_3                                          (0x08UL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0x08000000 */
#define SMC_CMSTIM2_HIZ2_4                                          (0x10UL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0x10000000 */
#define SMC_CMSTIM2_HIZ2_5                                          (0x20UL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0x20000000 */
#define SMC_CMSTIM2_HIZ2_6                                          (0x40UL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0x40000000 */
#define SMC_CMSTIM2_HIZ2_7                                          (0x80UL << SMC_CMSTIM2_HIZ2_Pos)                               /*!< 0x80000000 */

/******************  Bit definition for SMC_CMSTIM3 register  ******************/
#define SMC_CMSTIM3_SET3_Pos                                        (0U)
#define SMC_CMSTIM3_SET3_Msk                                        (0xFFUL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x000000FF */
#define SMC_CMSTIM3_SET3                                            SMC_CMSTIM3_SET3_Msk                                           /*!<MEMSET3[7:0] bits (Common memory 3 setup time) */
#define SMC_CMSTIM3_SET3_0                                          (0x01UL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x00000001 */
#define SMC_CMSTIM3_SET3_1                                          (0x02UL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x00000002 */
#define SMC_CMSTIM3_SET3_2                                          (0x04UL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x00000004 */
#define SMC_CMSTIM3_SET3_3                                          (0x08UL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x00000008 */
#define SMC_CMSTIM3_SET3_4                                          (0x10UL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x00000010 */
#define SMC_CMSTIM3_SET3_5                                          (0x20UL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x00000020 */
#define SMC_CMSTIM3_SET3_6                                          (0x40UL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x00000040 */
#define SMC_CMSTIM3_SET3_7                                          (0x80UL << SMC_CMSTIM3_SET3_Pos)                               /*!< 0x00000080 */

#define SMC_CMSTIM3_WAIT3_Pos                                       (8U)
#define SMC_CMSTIM3_WAIT3_Msk                                       (0xFFUL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x0000FF00 */
#define SMC_CMSTIM3_WAIT3                                           SMC_CMSTIM3_WAIT3_Msk                                          /*!<MEMWAIT3[7:0] bits (Common memory 3 wait time) */
#define SMC_CMSTIM3_WAIT3_0                                         (0x01UL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x00000100 */
#define SMC_CMSTIM3_WAIT3_1                                         (0x02UL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x00000200 */
#define SMC_CMSTIM3_WAIT3_2                                         (0x04UL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x00000400 */
#define SMC_CMSTIM3_WAIT3_3                                         (0x08UL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x00000800 */
#define SMC_CMSTIM3_WAIT3_4                                         (0x10UL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x00001000 */
#define SMC_CMSTIM3_WAIT3_5                                         (0x20UL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x00002000 */
#define SMC_CMSTIM3_WAIT3_6                                         (0x40UL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x00004000 */
#define SMC_CMSTIM3_WAIT3_7                                         (0x80UL << SMC_CMSTIM3_WAIT3_Pos)                              /*!< 0x00008000 */

#define SMC_CMSTIM3_HLD3_Pos                                        (16U)
#define SMC_CMSTIM3_HLD3_Msk                                        (0xFFUL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00FF0000 */
#define SMC_CMSTIM3_HLD3                                            SMC_CMSTIM3_HLD3_Msk                                           /*!<MEMHOLD3[7:0] bits (Common memory 3 hold time) */
#define SMC_CMSTIM3_HLD3_0                                          (0x01UL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00010000 */
#define SMC_CMSTIM3_HLD3_1                                          (0x02UL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00020000 */
#define SMC_CMSTIM3_HLD3_2                                          (0x04UL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00040000 */
#define SMC_CMSTIM3_HLD3_3                                          (0x08UL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00080000 */
#define SMC_CMSTIM3_HLD3_4                                          (0x10UL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00100000 */
#define SMC_CMSTIM3_HLD3_5                                          (0x20UL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00200000 */
#define SMC_CMSTIM3_HLD3_6                                          (0x40UL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00400000 */
#define SMC_CMSTIM3_HLD3_7                                          (0x80UL << SMC_CMSTIM3_HLD3_Pos)                               /*!< 0x00800000 */

#define SMC_CMSTIM3_HIZ3_Pos                                        (24U)
#define SMC_CMSTIM3_HIZ3_Msk                                        (0xFFUL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0xFF000000 */
#define SMC_CMSTIM3_HIZ3                                            SMC_CMSTIM3_HIZ3_Msk                                           /*!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) */
#define SMC_CMSTIM3_HIZ3_0                                          (0x01UL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0x01000000 */
#define SMC_CMSTIM3_HIZ3_1                                          (0x02UL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0x02000000 */
#define SMC_CMSTIM3_HIZ3_2                                          (0x04UL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0x04000000 */
#define SMC_CMSTIM3_HIZ3_3                                          (0x08UL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0x08000000 */
#define SMC_CMSTIM3_HIZ3_4                                          (0x10UL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0x10000000 */
#define SMC_CMSTIM3_HIZ3_5                                          (0x20UL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0x20000000 */
#define SMC_CMSTIM3_HIZ3_6                                          (0x40UL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0x40000000 */
#define SMC_CMSTIM3_HIZ3_7                                          (0x80UL << SMC_CMSTIM3_HIZ3_Pos)                               /*!< 0x80000000 */

/******************  Bit definition for SMC_CMSTIM4 register  ******************/
#define SMC_CMSTIM4_SET4_Pos                                        (0U)
#define SMC_CMSTIM4_SET4_Msk                                        (0xFFUL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x000000FF */
#define SMC_CMSTIM4_SET4                                            SMC_CMSTIM4_SET4_Msk                                           /*!<MEMSET4[7:0] bits (Common memory 4 setup time) */
#define SMC_CMSTIM4_SET4_0                                          (0x01UL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x00000001 */
#define SMC_CMSTIM4_SET4_1                                          (0x02UL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x00000002 */
#define SMC_CMSTIM4_SET4_2                                          (0x04UL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x00000004 */
#define SMC_CMSTIM4_SET4_3                                          (0x08UL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x00000008 */
#define SMC_CMSTIM4_SET4_4                                          (0x10UL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x00000010 */
#define SMC_CMSTIM4_SET4_5                                          (0x20UL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x00000020 */
#define SMC_CMSTIM4_SET4_6                                          (0x40UL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x00000040 */
#define SMC_CMSTIM4_SET4_7                                          (0x80UL << SMC_CMSTIM4_SET4_Pos)                               /*!< 0x00000080 */

#define SMC_CMSTIM4_WAIT4_Pos                                       (8U)
#define SMC_CMSTIM4_WAIT4_Msk                                       (0xFFUL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x0000FF00 */
#define SMC_CMSTIM4_WAIT4                                           SMC_CMSTIM4_WAIT4_Msk                                          /*!<MEMWAIT4[7:0] bits (Common memory 4 wait time) */
#define SMC_CMSTIM4_WAIT4_0                                         (0x01UL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x00000100 */
#define SMC_CMSTIM4_WAIT4_1                                         (0x02UL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x00000200 */
#define SMC_CMSTIM4_WAIT4_2                                         (0x04UL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x00000400 */
#define SMC_CMSTIM4_WAIT4_3                                         (0x08UL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x00000800 */
#define SMC_CMSTIM4_WAIT4_4                                         (0x10UL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x00001000 */
#define SMC_CMSTIM4_WAIT4_5                                         (0x20UL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x00002000 */
#define SMC_CMSTIM4_WAIT4_6                                         (0x40UL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x00004000 */
#define SMC_CMSTIM4_WAIT4_7                                         (0x80UL << SMC_CMSTIM4_WAIT4_Pos)                              /*!< 0x00008000 */

#define SMC_CMSTIM4_HLD4_Pos                                        (16U)
#define SMC_CMSTIM4_HLD4_Msk                                        (0xFFUL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00FF0000 */
#define SMC_CMSTIM4_HLD4                                            SMC_CMSTIM4_HLD4_Msk                                           /*!<MEMHOLD4[7:0] bits (Common memory 4 hold time) */
#define SMC_CMSTIM4_HLD4_0                                          (0x01UL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00010000 */
#define SMC_CMSTIM4_HLD4_1                                          (0x02UL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00020000 */
#define SMC_CMSTIM4_HLD4_2                                          (0x04UL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00040000 */
#define SMC_CMSTIM4_HLD4_3                                          (0x08UL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00080000 */
#define SMC_CMSTIM4_HLD4_4                                          (0x10UL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00100000 */
#define SMC_CMSTIM4_HLD4_5                                          (0x20UL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00200000 */
#define SMC_CMSTIM4_HLD4_6                                          (0x40UL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00400000 */
#define SMC_CMSTIM4_HLD4_7                                          (0x80UL << SMC_CMSTIM4_HLD4_Pos)                               /*!< 0x00800000 */

#define SMC_CMSTIM4_HIZ4_Pos                                        (24U)
#define SMC_CMSTIM4_HIZ4_Msk                                        (0xFFUL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0xFF000000 */
#define SMC_CMSTIM4_HIZ4                                            SMC_CMSTIM4_HIZ4_Msk                                           /*!<MEMHIZ4[7:0] bits (Common memory 4 databus HiZ time) */
#define SMC_CMSTIM4_HIZ4_0                                          (0x01UL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0x01000000 */
#define SMC_CMSTIM4_HIZ4_1                                          (0x02UL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0x02000000 */
#define SMC_CMSTIM4_HIZ4_2                                          (0x04UL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0x04000000 */
#define SMC_CMSTIM4_HIZ4_3                                          (0x08UL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0x08000000 */
#define SMC_CMSTIM4_HIZ4_4                                          (0x10UL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0x10000000 */
#define SMC_CMSTIM4_HIZ4_5                                          (0x20UL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0x20000000 */
#define SMC_CMSTIM4_HIZ4_6                                          (0x40UL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0x40000000 */
#define SMC_CMSTIM4_HIZ4_7                                          (0x80UL << SMC_CMSTIM4_HIZ4_Pos)                               /*!< 0x80000000 */

/******************  Bit definition for SMC_AMSTIM2 register  ******************/
#define SMC_AMSTIM2_SET2_Pos                                        (0U)
#define SMC_AMSTIM2_SET2_Msk                                        (0xFFUL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x000000FF */
#define SMC_AMSTIM2_SET2                                            SMC_AMSTIM2_SET2_Msk                                           /*!<ATTSET2[7:0] bits (Attribute memory 2 setup time) */
#define SMC_AMSTIM2_SET2_0                                          (0x01UL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x00000001 */
#define SMC_AMSTIM2_SET2_1                                          (0x02UL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x00000002 */
#define SMC_AMSTIM2_SET2_2                                          (0x04UL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x00000004 */
#define SMC_AMSTIM2_SET2_3                                          (0x08UL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x00000008 */
#define SMC_AMSTIM2_SET2_4                                          (0x10UL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x00000010 */
#define SMC_AMSTIM2_SET2_5                                          (0x20UL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x00000020 */
#define SMC_AMSTIM2_SET2_6                                          (0x40UL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x00000040 */
#define SMC_AMSTIM2_SET2_7                                          (0x80UL << SMC_AMSTIM2_SET2_Pos)                               /*!< 0x00000080 */

#define SMC_AMSTIM2_WAIT2_Pos                                       (8U)
#define SMC_AMSTIM2_WAIT2_Msk                                       (0xFFUL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x0000FF00 */
#define SMC_AMSTIM2_WAIT2                                           SMC_AMSTIM2_WAIT2_Msk                                          /*!<ATTWAIT2[7:0] bits (Attribute memory 2 wait time) */
#define SMC_AMSTIM2_WAIT2_0                                         (0x01UL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x00000100 */
#define SMC_AMSTIM2_WAIT2_1                                         (0x02UL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x00000200 */
#define SMC_AMSTIM2_WAIT2_2                                         (0x04UL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x00000400 */
#define SMC_AMSTIM2_WAIT2_3                                         (0x08UL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x00000800 */
#define SMC_AMSTIM2_WAIT2_4                                         (0x10UL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x00001000 */
#define SMC_AMSTIM2_WAIT2_5                                         (0x20UL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x00002000 */
#define SMC_AMSTIM2_WAIT2_6                                         (0x40UL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x00004000 */
#define SMC_AMSTIM2_WAIT2_7                                         (0x80UL << SMC_AMSTIM2_WAIT2_Pos)                              /*!< 0x00008000 */

#define SMC_AMSTIM2_HLD2_Pos                                        (16U)
#define SMC_AMSTIM2_HLD2_Msk                                        (0xFFUL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00FF0000 */
#define SMC_AMSTIM2_HLD2                                            SMC_AMSTIM2_HLD2_Msk                                           /*!<ATTHOLD2[7:0] bits (Attribute memory 2 hold time) */
#define SMC_AMSTIM2_HLD2_0                                          (0x01UL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00010000 */
#define SMC_AMSTIM2_HLD2_1                                          (0x02UL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00020000 */
#define SMC_AMSTIM2_HLD2_2                                          (0x04UL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00040000 */
#define SMC_AMSTIM2_HLD2_3                                          (0x08UL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00080000 */
#define SMC_AMSTIM2_HLD2_4                                          (0x10UL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00100000 */
#define SMC_AMSTIM2_HLD2_5                                          (0x20UL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00200000 */
#define SMC_AMSTIM2_HLD2_6                                          (0x40UL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00400000 */
#define SMC_AMSTIM2_HLD2_7                                          (0x80UL << SMC_AMSTIM2_HLD2_Pos)                               /*!< 0x00800000 */

#define SMC_AMSTIM2_HIZ2_Pos                                        (24U)
#define SMC_AMSTIM2_HIZ2_Msk                                        (0xFFUL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0xFF000000 */
#define SMC_AMSTIM2_HIZ2                                            SMC_AMSTIM2_HIZ2_Msk                                           /*!<ATTHIZ2[7:0] bits (Attribute memory 2 databus HiZ time) */
#define SMC_AMSTIM2_HIZ2_0                                          (0x01UL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0x01000000 */
#define SMC_AMSTIM2_HIZ2_1                                          (0x02UL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0x02000000 */
#define SMC_AMSTIM2_HIZ2_2                                          (0x04UL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0x04000000 */
#define SMC_AMSTIM2_HIZ2_3                                          (0x08UL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0x08000000 */
#define SMC_AMSTIM2_HIZ2_4                                          (0x10UL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0x10000000 */
#define SMC_AMSTIM2_HIZ2_5                                          (0x20UL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0x20000000 */
#define SMC_AMSTIM2_HIZ2_6                                          (0x40UL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0x40000000 */
#define SMC_AMSTIM2_HIZ2_7                                          (0x80UL << SMC_AMSTIM2_HIZ2_Pos)                               /*!< 0x80000000 */

/******************  Bit definition for SMC_AMSTIM3 register  ******************/
#define SMC_AMSTIM3_SET3_Pos                                        (0U)
#define SMC_AMSTIM3_SET3_Msk                                        (0xFFUL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x000000FF */
#define SMC_AMSTIM3_SET3                                            SMC_AMSTIM3_SET3_Msk                                           /*!<ATTSET3[7:0] bits (Attribute memory 3 setup time) */
#define SMC_AMSTIM3_SET3_0                                          (0x01UL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x00000001 */
#define SMC_AMSTIM3_SET3_1                                          (0x02UL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x00000002 */
#define SMC_AMSTIM3_SET3_2                                          (0x04UL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x00000004 */
#define SMC_AMSTIM3_SET3_3                                          (0x08UL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x00000008 */
#define SMC_AMSTIM3_SET3_4                                          (0x10UL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x00000010 */
#define SMC_AMSTIM3_SET3_5                                          (0x20UL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x00000020 */
#define SMC_AMSTIM3_SET3_6                                          (0x40UL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x00000040 */
#define SMC_AMSTIM3_SET3_7                                          (0x80UL << SMC_AMSTIM3_SET3_Pos)                               /*!< 0x00000080 */

#define SMC_AMSTIM3_WAIT3_Pos                                       (8U)
#define SMC_AMSTIM3_WAIT3_Msk                                       (0xFFUL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x0000FF00 */
#define SMC_AMSTIM3_WAIT3                                           SMC_AMSTIM3_WAIT3_Msk                                          /*!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) */
#define SMC_AMSTIM3_WAIT3_0                                         (0x01UL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x00000100 */
#define SMC_AMSTIM3_WAIT3_1                                         (0x02UL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x00000200 */
#define SMC_AMSTIM3_WAIT3_2                                         (0x04UL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x00000400 */
#define SMC_AMSTIM3_WAIT3_3                                         (0x08UL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x00000800 */
#define SMC_AMSTIM3_WAIT3_4                                         (0x10UL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x00001000 */
#define SMC_AMSTIM3_WAIT3_5                                         (0x20UL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x00002000 */
#define SMC_AMSTIM3_WAIT3_6                                         (0x40UL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x00004000 */
#define SMC_AMSTIM3_WAIT3_7                                         (0x80UL << SMC_AMSTIM3_WAIT3_Pos)                              /*!< 0x00008000 */

#define SMC_AMSTIM3_HLD3_Pos                                        (16U)
#define SMC_AMSTIM3_HLD3_Msk                                        (0xFFUL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00FF0000 */
#define SMC_AMSTIM3_HLD3                                            SMC_AMSTIM3_HLD3_Msk                                           /*!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) */
#define SMC_AMSTIM3_HLD3_0                                          (0x01UL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00010000 */
#define SMC_AMSTIM3_HLD3_1                                          (0x02UL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00020000 */
#define SMC_AMSTIM3_HLD3_2                                          (0x04UL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00040000 */
#define SMC_AMSTIM3_HLD3_3                                          (0x08UL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00080000 */
#define SMC_AMSTIM3_HLD3_4                                          (0x10UL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00100000 */
#define SMC_AMSTIM3_HLD3_5                                          (0x20UL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00200000 */
#define SMC_AMSTIM3_HLD3_6                                          (0x40UL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00400000 */
#define SMC_AMSTIM3_HLD3_7                                          (0x80UL << SMC_AMSTIM3_HLD3_Pos)                               /*!< 0x00800000 */

#define SMC_AMSTIM3_HIZ3_Pos                                        (24U)
#define SMC_AMSTIM3_HIZ3_Msk                                        (0xFFUL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0xFF000000 */
#define SMC_AMSTIM3_HIZ3                                            SMC_AMSTIM3_HIZ3_Msk                                           /*!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) */
#define SMC_AMSTIM3_HIZ3_0                                          (0x01UL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0x01000000 */
#define SMC_AMSTIM3_HIZ3_1                                          (0x02UL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0x02000000 */
#define SMC_AMSTIM3_HIZ3_2                                          (0x04UL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0x04000000 */
#define SMC_AMSTIM3_HIZ3_3                                          (0x08UL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0x08000000 */
#define SMC_AMSTIM3_HIZ3_4                                          (0x10UL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0x10000000 */
#define SMC_AMSTIM3_HIZ3_5                                          (0x20UL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0x20000000 */
#define SMC_AMSTIM3_HIZ3_6                                          (0x40UL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0x40000000 */
#define SMC_AMSTIM3_HIZ3_7                                          (0x80UL << SMC_AMSTIM3_HIZ3_Pos)                               /*!< 0x80000000 */

/******************  Bit definition for SMC_AMSTIM4 register  ******************/
#define SMC_AMSTIM4_SET4_Pos                                        (0U)
#define SMC_AMSTIM4_SET4_Msk                                        (0xFFUL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x000000FF */
#define SMC_AMSTIM4_SET4                                            SMC_AMSTIM4_SET4_Msk                                           /*!<ATTSET4[7:0] bits (Attribute memory 4 setup time) */
#define SMC_AMSTIM4_SET4_0                                          (0x01UL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x00000001 */
#define SMC_AMSTIM4_SET4_1                                          (0x02UL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x00000002 */
#define SMC_AMSTIM4_SET4_2                                          (0x04UL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x00000004 */
#define SMC_AMSTIM4_SET4_3                                          (0x08UL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x00000008 */
#define SMC_AMSTIM4_SET4_4                                          (0x10UL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x00000010 */
#define SMC_AMSTIM4_SET4_5                                          (0x20UL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x00000020 */
#define SMC_AMSTIM4_SET4_6                                          (0x40UL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x00000040 */
#define SMC_AMSTIM4_SET4_7                                          (0x80UL << SMC_AMSTIM4_SET4_Pos)                               /*!< 0x00000080 */

#define SMC_AMSTIM4_WAIT4_Pos                                       (8U)
#define SMC_AMSTIM4_WAIT4_Msk                                       (0xFFUL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x0000FF00 */
#define SMC_AMSTIM4_WAIT4                                           SMC_AMSTIM4_WAIT4_Msk                                          /*!<ATTWAIT4[7:0] bits (Attribute memory 4 wait time) */
#define SMC_AMSTIM4_WAIT4_0                                         (0x01UL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x00000100 */
#define SMC_AMSTIM4_WAIT4_1                                         (0x02UL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x00000200 */
#define SMC_AMSTIM4_WAIT4_2                                         (0x04UL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x00000400 */
#define SMC_AMSTIM4_WAIT4_3                                         (0x08UL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x00000800 */
#define SMC_AMSTIM4_WAIT4_4                                         (0x10UL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x00001000 */
#define SMC_AMSTIM4_WAIT4_5                                         (0x20UL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x00002000 */
#define SMC_AMSTIM4_WAIT4_6                                         (0x40UL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x00004000 */
#define SMC_AMSTIM4_WAIT4_7                                         (0x80UL << SMC_AMSTIM4_WAIT4_Pos)                              /*!< 0x00008000 */

#define SMC_AMSTIM4_HLD4_Pos                                        (16U)
#define SMC_AMSTIM4_HLD4_Msk                                        (0xFFUL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00FF0000 */
#define SMC_AMSTIM4_HLD4                                            SMC_AMSTIM4_HLD4_Msk                                           /*!<ATTHOLD4[7:0] bits (Attribute memory 4 hold time) */
#define SMC_AMSTIM4_HLD4_0                                          (0x01UL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00010000 */
#define SMC_AMSTIM4_HLD4_1                                          (0x02UL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00020000 */
#define SMC_AMSTIM4_HLD4_2                                          (0x04UL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00040000 */
#define SMC_AMSTIM4_HLD4_3                                          (0x08UL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00080000 */
#define SMC_AMSTIM4_HLD4_4                                          (0x10UL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00100000 */
#define SMC_AMSTIM4_HLD4_5                                          (0x20UL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00200000 */
#define SMC_AMSTIM4_HLD4_6                                          (0x40UL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00400000 */
#define SMC_AMSTIM4_HLD4_7                                          (0x80UL << SMC_AMSTIM4_HLD4_Pos)                               /*!< 0x00800000 */

#define SMC_AMSTIM4_HIZ4_Pos                                        (24U)
#define SMC_AMSTIM4_HIZ4_Msk                                        (0xFFUL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0xFF000000 */
#define SMC_AMSTIM4_HIZ4                                            SMC_AMSTIM4_HIZ4_Msk                                           /*!<ATTHIZ4[7:0] bits (Attribute memory 4 databus HiZ time) */
#define SMC_AMSTIM4_HIZ4_0                                          (0x01UL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0x01000000 */
#define SMC_AMSTIM4_HIZ4_1                                          (0x02UL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0x02000000 */
#define SMC_AMSTIM4_HIZ4_2                                          (0x04UL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0x04000000 */
#define SMC_AMSTIM4_HIZ4_3                                          (0x08UL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0x08000000 */
#define SMC_AMSTIM4_HIZ4_4                                          (0x10UL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0x10000000 */
#define SMC_AMSTIM4_HIZ4_5                                          (0x20UL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0x20000000 */
#define SMC_AMSTIM4_HIZ4_6                                          (0x40UL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0x40000000 */
#define SMC_AMSTIM4_HIZ4_7                                          (0x80UL << SMC_AMSTIM4_HIZ4_Pos)                               /*!< 0x80000000 */

/******************  Bit definition for SMC_IOSTIM4 register  *******************/
#define SMC_IOSTIM4_SET4_Pos                                        (0U)
#define SMC_IOSTIM4_SET4_Msk                                        (0xFFUL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x000000FF */
#define SMC_IOSTIM4_SET4                                            SMC_IOSTIM4_SET4_Msk                                           /*!<IOSET4[7:0] bits (I/O 4 setup time) */
#define SMC_IOSTIM4_SET4_0                                          (0x01UL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x00000001 */
#define SMC_IOSTIM4_SET4_1                                          (0x02UL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x00000002 */
#define SMC_IOSTIM4_SET4_2                                          (0x04UL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x00000004 */
#define SMC_IOSTIM4_SET4_3                                          (0x08UL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x00000008 */
#define SMC_IOSTIM4_SET4_4                                          (0x10UL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x00000010 */
#define SMC_IOSTIM4_SET4_5                                          (0x20UL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x00000020 */
#define SMC_IOSTIM4_SET4_6                                          (0x40UL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x00000040 */
#define SMC_IOSTIM4_SET4_7                                          (0x80UL << SMC_IOSTIM4_SET4_Pos)                               /*!< 0x00000080 */

#define SMC_IOSTIM4_WAIT4_Pos                                       (8U)
#define SMC_IOSTIM4_WAIT4_Msk                                       (0xFFUL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x0000FF00 */
#define SMC_IOSTIM4_WAIT4                                           SMC_IOSTIM4_WAIT4_Msk                                          /*!<IOWAIT4[7:0] bits (I/O 4 wait time) */
#define SMC_IOSTIM4_WAIT4_0                                         (0x01UL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x00000100 */
#define SMC_IOSTIM4_WAIT4_1                                         (0x02UL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x00000200 */
#define SMC_IOSTIM4_WAIT4_2                                         (0x04UL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x00000400 */
#define SMC_IOSTIM4_WAIT4_3                                         (0x08UL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x00000800 */
#define SMC_IOSTIM4_WAIT4_4                                         (0x10UL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x00001000 */
#define SMC_IOSTIM4_WAIT4_5                                         (0x20UL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x00002000 */
#define SMC_IOSTIM4_WAIT4_6                                         (0x40UL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x00004000 */
#define SMC_IOSTIM4_WAIT4_7                                         (0x80UL << SMC_IOSTIM4_WAIT4_Pos)                              /*!< 0x00008000 */

#define SMC_IOSTIM4_HLD4_Pos                                        (16U)
#define SMC_IOSTIM4_HLD4_Msk                                        (0xFFUL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00FF0000 */
#define SMC_IOSTIM4_HLD4                                            SMC_IOSTIM4_HLD4_Msk                                           /*!<IOHOLD4[7:0] bits (I/O 4 hold time) */
#define SMC_IOSTIM4_HLD4_0                                          (0x01UL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00010000 */
#define SMC_IOSTIM4_HLD4_1                                          (0x02UL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00020000 */
#define SMC_IOSTIM4_HLD4_2                                          (0x04UL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00040000 */
#define SMC_IOSTIM4_HLD4_3                                          (0x08UL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00080000 */
#define SMC_IOSTIM4_HLD4_4                                          (0x10UL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00100000 */
#define SMC_IOSTIM4_HLD4_5                                          (0x20UL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00200000 */
#define SMC_IOSTIM4_HLD4_6                                          (0x40UL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00400000 */
#define SMC_IOSTIM4_HLD4_7                                          (0x80UL << SMC_IOSTIM4_HLD4_Pos)                               /*!< 0x00800000 */

#define SMC_IOSTIM4_HIZ4_Pos                                        (24U)
#define SMC_IOSTIM4_HIZ4_Msk                                        (0xFFUL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0xFF000000 */
#define SMC_IOSTIM4_HIZ4                                            SMC_IOSTIM4_HIZ4_Msk                                           /*!<IOHIZ4[7:0] bits (I/O 4 databus HiZ time) */
#define SMC_IOSTIM4_HIZ4_0                                          (0x01UL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0x01000000 */
#define SMC_IOSTIM4_HIZ4_1                                          (0x02UL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0x02000000 */
#define SMC_IOSTIM4_HIZ4_2                                          (0x04UL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0x04000000 */
#define SMC_IOSTIM4_HIZ4_3                                          (0x08UL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0x08000000 */
#define SMC_IOSTIM4_HIZ4_4                                          (0x10UL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0x10000000 */
#define SMC_IOSTIM4_HIZ4_5                                          (0x20UL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0x20000000 */
#define SMC_IOSTIM4_HIZ4_6                                          (0x40UL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0x40000000 */
#define SMC_IOSTIM4_HIZ4_7                                          (0x80UL << SMC_IOSTIM4_HIZ4_Pos)                               /*!< 0x80000000 */

/******************  Bit definition for SMC_ECCRS2 register  ******************/
#define SMC_ECCRS2_ECCRS2_Pos                                       (0U)
#define SMC_ECCRS2_ECCRS2_Msk                                       (0xFFFFFFFFUL << SMC_ECCRS2_ECCRS2_Pos)                        /*!< 0xFFFFFFFF */
#define SMC_ECCRS2_ECCRS2                                           SMC_ECCRS2_ECCRS2_Msk                                          /*!<ECC result */

/******************  Bit definition for SMC_ECCRS3 register  ******************/
#define SMC_ECCRS3_ECCRS3_Pos                                       (0U)
#define SMC_ECCRS3_ECCRS3_Msk                                       (0xFFFFFFFFUL << SMC_ECCRS3_ECCRS3_Pos)                        /*!< 0xFFFFFFFF */
#define SMC_ECCRS3_ECCRS3                                           SMC_ECCRS3_ECCRS3_Msk                                          /*!<ECC result */

/******************************************************************************/
/*                                                                            */
/*                           Dynamic Memory Controller                        */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for DMC_CFG register  ********************/
#define DMC_CFG_BAWCFG_Pos                                          (3U)
#define DMC_CFG_BAWCFG_Msk                                          (0x3UL << DMC_CFG_BAWCFG_Pos)                                  /*!< 0x00000018 */
#define DMC_CFG_BAWCFG                                              DMC_CFG_BAWCFG_Msk
#define DMC_CFG_BAWCFG_0                                            (0x00UL << DMC_CFG_BAWCFG_Pos)                                 /*!< 0x00000000 */
#define DMC_CFG_BAWCFG_1                                            (0x01UL << DMC_CFG_BAWCFG_Pos)                                 /*!< 0x00000008 */
#define DMC_CFG_RAWCFG_Pos                                          (5U)
#define DMC_CFG_RAWCFG_Msk                                          (0xFUL << DMC_CFG_RAWCFG_Pos)                                  /*!< 0x000001E0 */
#define DMC_CFG_RAWCFG                                              DMC_CFG_RAWCFG_Msk
#define DMC_CFG_CAWCFG_Pos                                          (9U)
#define DMC_CFG_CAWCFG_Msk                                          (0xFUL << DMC_CFG_CAWCFG_Pos)                                  /*!< 0x00001E00 */
#define DMC_CFG_CAWCFG                                              DMC_CFG_CAWCFG_Msk
#define DMC_CFG_DWCFG_Pos                                           (13U)
#define DMC_CFG_DWCFG_Msk                                           (0x3UL << DMC_CFG_DWCFG_Pos)                                   /*!< 0x00006000 */
#define DMC_CFG_DWCFG                                               DMC_CFG_DWCFG_Msk

/******************  Bit definition for DMC_TIM0 register  ********************/
#define DMC_TIM0_CASLSEL0_Pos                                       (0U)
#define DMC_TIM0_CASLSEL0_Msk                                       (0x3UL << DMC_TIM0_CASLSEL0_Pos)                               /*!< 0x00000003 */
#define DMC_TIM0_CASLSEL0                                           DMC_TIM0_CASLSEL0_Msk
#define DMC_TIM0_RASMINTSEL_Pos                                     (2U)
#define DMC_TIM0_RASMINTSEL_Msk                                     (0xFUL << DMC_TIM0_RASMINTSEL_Pos)                             /*!< 0x0000003C */
#define DMC_TIM0_RASMINTSEL                                         DMC_TIM0_RASMINTSEL_Msk
#define DMC_TIM0_DTIMSEL_Pos                                        (6U)
#define DMC_TIM0_DTIMSEL_Msk                                        (0x7UL << DMC_TIM0_DTIMSEL_Pos)                                /*!< 0x000001C0 */
#define DMC_TIM0_DTIMSEL                                            DMC_TIM0_DTIMSEL_Msk
#define DMC_TIM0_PCPSEL_Pos                                         (9U)
#define DMC_TIM0_PCPSEL_Msk                                         (0x7UL << DMC_TIM0_PCPSEL_Pos)                                 /*!< 0x00000E00 */
#define DMC_TIM0_PCPSEL                                             DMC_TIM0_PCPSEL_Msk
#define DMC_TIM0_WRTIMSEL_Pos                                       (12U)
#define DMC_TIM0_WRTIMSEL_Msk                                       (0x3UL << DMC_TIM0_WRTIMSEL_Pos)                               /*!< 0x00003000 */
#define DMC_TIM0_WRTIMSEL                                           DMC_TIM0_WRTIMSEL_Msk
#define DMC_TIM0_ARPSEL_Pos                                         (14U)
#define DMC_TIM0_ARPSEL_Msk                                         (0xFUL << DMC_TIM0_ARPSEL_Pos)                                 /*!< 0x0003C000 */
#define DMC_TIM0_ARPSEL                                             DMC_TIM0_ARPSEL_Msk
#define DMC_TIM0_XSR0_Pos                                           (18U)
#define DMC_TIM0_XSR0_Msk                                           (0xFUL << DMC_TIM0_XSR0_Pos)                                   /*!< 0x003C0000 */
#define DMC_TIM0_XSR0                                               DMC_TIM0_XSR0_Msk
#define DMC_TIM0_ATACP_Pos                                          (22U)
#define DMC_TIM0_ATACP_Msk                                          (0xFUL << DMC_TIM0_ATACP_Pos)                                  /*!< 0x03C00000 */
#define DMC_TIM0_ATACP                                              DMC_TIM0_ATACP_Msk
#define DMC_TIM0_ECASLSEL1_Pos                                      (26U)
#define DMC_TIM0_ECASLSEL1_Msk                                      (0x1UL << DMC_TIM0_ECASLSEL1_Pos)                              /*!< 0x04000000 */
#define DMC_TIM0_ECASLSEL1                                          DMC_TIM0_ECASLSEL1_Msk
#define DMC_TIM0_EXSR1_Pos                                          (27U)
#define DMC_TIM0_EXSR1_Msk                                          (0x1FUL << DMC_TIM0_EXSR1_Pos)                                 /*!< 0xF8000000 */
#define DMC_TIM0_EXSR1                                              DMC_TIM0_EXSR1_Msk

/******************  Bit definition for DMC_TIM1 register  ********************/
#define DMC_TIM1_STBTIM_Pos                                         (0U)
#define DMC_TIM1_STBTIM_Msk                                         (0xFFFFUL << DMC_TIM1_STBTIM_Pos)                              /*!< 0x0000FFFF */
#define DMC_TIM1_STBTIM                                             DMC_TIM1_STBTIM_Msk
#define DMC_TIM1_ARNUMCFG_Pos                                       (16U)
#define DMC_TIM1_ARNUMCFG_Msk                                       (0xFUL << DMC_TIM1_ARNUMCFG_Pos)                               /*!< 0x000F0000 */
#define DMC_TIM1_ARNUMCFG                                           DMC_TIM1_ARNUMCFG_Msk

/******************  Bit definition for DMC_CTRL1 register  ********************/
#define DMC_CTRL1_INIT_Pos                                          (0U)
#define DMC_CTRL1_INIT_Msk                                          (0x1UL << DMC_CTRL1_INIT_Pos)                                  /*!< 0x00000001 */
#define DMC_CTRL1_INIT                                              DMC_CTRL1_INIT_Msk
#define DMC_CTRL1_SRMEN_Pos                                         (1U)
#define DMC_CTRL1_SRMEN_Msk                                         (0x1UL << DMC_CTRL1_SRMEN_Pos)                                 /*!< 0x00000002 */
#define DMC_CTRL1_SRMEN                                             DMC_CTRL1_SRMEN_Msk
#define DMC_CTRL1_PDMEN_Pos                                         (2U)
#define DMC_CTRL1_PDMEN_Msk                                         (0x1UL << DMC_CTRL1_PDMEN_Pos)                                 /*!< 0x00000004 */
#define DMC_CTRL1_PDMEN                                             DMC_CTRL1_PDMEN_Msk
#define DMC_CTRL1_PCACFG_Pos                                        (3U)
#define DMC_CTRL1_PCACFG_Msk                                        (0x1UL << DMC_CTRL1_PCACFG_Pos)                                /*!< 0x00000008 */
#define DMC_CTRL1_PCACFG                                            DMC_CTRL1_PCACFG_Msk
#define DMC_CTRL1_FRBSREN_Pos                                       (4U)
#define DMC_CTRL1_FRBSREN_Msk                                       (0x1UL << DMC_CTRL1_FRBSREN_Pos)                               /*!< 0x00000010 */
#define DMC_CTRL1_FRBSREN                                           DMC_CTRL1_FRBSREN_Msk
#define DMC_CTRL1_FRASREN_Pos                                       (5U)
#define DMC_CTRL1_FRASREN_Msk                                       (0x1UL << DMC_CTRL1_FRASREN_Pos)                               /*!< 0x00000020 */
#define DMC_CTRL1_FRASREN                                           DMC_CTRL1_FRASREN_Msk
#define DMC_CTRL1_RDNUMMCFG_Pos                                     (6U)
#define DMC_CTRL1_RDNUMMCFG_Msk                                     (0x7UL << DMC_CTRL1_RDNUMMCFG_Pos)                             /*!< 0x000001C0 */
#define DMC_CTRL1_RDNUMMCFG                                         DMC_CTRL1_RDNUMMCFG_Msk
#define DMC_CTRL1_MODESET_Pos                                       (9U)
#define DMC_CTRL1_MODESET_Msk                                       (0x1UL << DMC_CTRL1_MODESET_Pos)                               /*!< 0x00000200 */
#define DMC_CTRL1_MODESET                                           DMC_CTRL1_MODESET_Msk
#define DMC_CTRL1_SRMFLG_Pos                                        (11U)
#define DMC_CTRL1_SRMFLG_Msk                                        (0x1UL << DMC_CTRL1_SRMFLG_Pos)                                /*!< 0x00000800 */
#define DMC_CTRL1_SRMFLG                                            DMC_CTRL1_SRMFLG_Msk
#define DMC_CTRL1_BANKNUMCFG_Pos                                    (12U)
#define DMC_CTRL1_BANKNUMCFG_Msk                                    (0xFUL << DMC_CTRL1_BANKNUMCFG_Pos)                            /*!< 0x0000F000 */
#define DMC_CTRL1_BANKNUMCFG                                        DMC_CTRL1_BANKNUMCFG_Msk

/******************  Bit definition for DMC_REF register  ********************/
#define DMC_REF_RCYCCFG_Pos                                         (0U)
#define DMC_REF_RCYCCFG_Msk                                         (0xFFFFUL << DMC_REF_RCYCCFG_Pos)                              /*!< 0x0000FFFF */
#define DMC_REF_RCYCCFG                                             DMC_REF_RCYCCFG_Msk

/******************  Bit definition for DMC_REF register  ********************/
#define DMC_SW_MCSW_Pos                                             (0U)
#define DMC_SW_MCSW_Msk                                             (0x1UL << DMC_SW_MCSW_Pos)                                     /*!< 0x00000001 */
#define DMC_SW_MCSW                                                 DMC_SW_MCSW_Msk

/******************  Bit definition for DMC_CTRL2 register  ********************/
#define DMC_CTRL2_CPHACFG_Pos                                       (0U)
#define DMC_CTRL2_CPHACFG_Msk                                       (0x1UL << DMC_CTRL2_CPHACFG_Pos)                               /*!< 0x00000001 */
#define DMC_CTRL2_CPHACFG                                           DMC_CTRL2_CPHACFG_Msk
#define DMC_CTRL2_RDDEN_Pos                                         (1U)
#define DMC_CTRL2_RDDEN_Msk                                         (0x1UL << DMC_CTRL2_RDDEN_Pos)                                 /*!< 0x00000002 */
#define DMC_CTRL2_RDDEN                                             DMC_CTRL2_RDDEN_Msk
#define DMC_CTRL2_RDDCFG_Pos                                        (2U)
#define DMC_CTRL2_RDDCFG_Msk                                        (0x7UL << DMC_CTRL2_RDDCFG_Pos)                                /*!< 0x0000001C */
#define DMC_CTRL2_RDDCFG                                            DMC_CTRL2_RDDCFG_Msk
#define DMC_CTRL2_WPEN_Pos                                          (5U)
#define DMC_CTRL2_WPEN_Msk                                          (0x1UL << DMC_CTRL2_WPEN_Pos)                                  /*!< 0x00000020 */
#define DMC_CTRL2_WPEN                                              DMC_CTRL2_WPEN_Msk
#define DMC_CTRL2_BUFFEN_Pos                                        (6U)
#define DMC_CTRL2_BUFFEN_Msk                                        (0x1UL << DMC_CTRL2_BUFFEN_Pos)                                /*!< 0x00000040 */
#define DMC_CTRL2_BUFFEN                                            DMC_CTRL2_BUFFEN_Msk
#define DMC_CTRL2_WRPBSEL_Pos                                       (7U)
#define DMC_CTRL2_WRPBSEL_Msk                                       (0x1UL << DMC_CTRL2_WRPBSEL_Pos)                               /*!< 0x00000080 */
#define DMC_CTRL2_WRPBSEL                                           DMC_CTRL2_WRPBSEL_Msk

/******************************************************************************/
/*                                                                            */
/*                            General Purpose I/O                             */
/*                                                                            */
/******************************************************************************/
/******************  Bits definition for GPIO_MODE register  *****************/
#define GPIO_MODE_MODE0_Pos                                         (0U)
#define GPIO_MODE_MODE0_Msk                                         (0x3UL << GPIO_MODE_MODE0_Pos)                                 /*!< 0x00000003 */
#define GPIO_MODE_MODE0                                             GPIO_MODE_MODE0_Msk
#define GPIO_MODE_MODE0_0                                           (0x1UL << GPIO_MODE_MODE0_Pos)                                 /*!< 0x00000001 */
#define GPIO_MODE_MODE0_1                                           (0x2UL << GPIO_MODE_MODE0_Pos)                                 /*!< 0x00000002 */
#define GPIO_MODE_MODE1_Pos                                         (2U)
#define GPIO_MODE_MODE1_Msk                                         (0x3UL << GPIO_MODE_MODE1_Pos)                                 /*!< 0x0000000C */
#define GPIO_MODE_MODE1                                             GPIO_MODE_MODE1_Msk
#define GPIO_MODE_MODE1_0                                           (0x1UL << GPIO_MODE_MODE1_Pos)                                 /*!< 0x00000004 */
#define GPIO_MODE_MODE1_1                                           (0x2UL << GPIO_MODE_MODE1_Pos)                                 /*!< 0x00000008 */
#define GPIO_MODE_MODE2_Pos                                         (4U)
#define GPIO_MODE_MODE2_Msk                                         (0x3UL << GPIO_MODE_MODE2_Pos)                                 /*!< 0x00000030 */
#define GPIO_MODE_MODE2                                             GPIO_MODE_MODE2_Msk
#define GPIO_MODE_MODE2_0                                           (0x1UL << GPIO_MODE_MODE2_Pos)                                 /*!< 0x00000010 */
#define GPIO_MODE_MODE2_1                                           (0x2UL << GPIO_MODE_MODE2_Pos)                                 /*!< 0x00000020 */
#define GPIO_MODE_MODE3_Pos                                         (6U)
#define GPIO_MODE_MODE3_Msk                                         (0x3UL << GPIO_MODE_MODE3_Pos)                                 /*!< 0x000000C0 */
#define GPIO_MODE_MODE3                                             GPIO_MODE_MODE3_Msk
#define GPIO_MODE_MODE3_0                                           (0x1UL << GPIO_MODE_MODE3_Pos)                                 /*!< 0x00000040 */
#define GPIO_MODE_MODE3_1                                           (0x2UL << GPIO_MODE_MODE3_Pos)                                 /*!< 0x00000080 */
#define GPIO_MODE_MODE4_Pos                                         (8U)
#define GPIO_MODE_MODE4_Msk                                         (0x3UL << GPIO_MODE_MODE4_Pos)                                 /*!< 0x00000300 */
#define GPIO_MODE_MODE4                                             GPIO_MODE_MODE4_Msk
#define GPIO_MODE_MODE4_0                                           (0x1UL << GPIO_MODE_MODE4_Pos)                                 /*!< 0x00000100 */
#define GPIO_MODE_MODE4_1                                           (0x2UL << GPIO_MODE_MODE4_Pos)                                 /*!< 0x00000200 */
#define GPIO_MODE_MODE5_Pos                                         (10U)
#define GPIO_MODE_MODE5_Msk                                         (0x3UL << GPIO_MODE_MODE5_Pos)                                 /*!< 0x00000C00 */
#define GPIO_MODE_MODE5                                             GPIO_MODE_MODE5_Msk
#define GPIO_MODE_MODE5_0                                           (0x1UL << GPIO_MODE_MODE5_Pos)                                 /*!< 0x00000400 */
#define GPIO_MODE_MODE5_1                                           (0x2UL << GPIO_MODE_MODE5_Pos)                                 /*!< 0x00000800 */
#define GPIO_MODE_MODE6_Pos                                         (12U)
#define GPIO_MODE_MODE6_Msk                                         (0x3UL << GPIO_MODE_MODE6_Pos)                                 /*!< 0x00003000 */
#define GPIO_MODE_MODE6                                             GPIO_MODE_MODE6_Msk
#define GPIO_MODE_MODE6_0                                           (0x1UL << GPIO_MODE_MODE6_Pos)                                 /*!< 0x00001000 */
#define GPIO_MODE_MODE6_1                                           (0x2UL << GPIO_MODE_MODE6_Pos)                                 /*!< 0x00002000 */
#define GPIO_MODE_MODE7_Pos                                         (14U)
#define GPIO_MODE_MODE7_Msk                                         (0x3UL << GPIO_MODE_MODE7_Pos)                                 /*!< 0x0000C000 */
#define GPIO_MODE_MODE7                                             GPIO_MODE_MODE7_Msk
#define GPIO_MODE_MODE7_0                                           (0x1UL << GPIO_MODE_MODE7_Pos)                                 /*!< 0x00004000 */
#define GPIO_MODE_MODE7_1                                           (0x2UL << GPIO_MODE_MODE7_Pos)                                 /*!< 0x00008000 */
#define GPIO_MODE_MODE8_Pos                                         (16U)
#define GPIO_MODE_MODE8_Msk                                         (0x3UL << GPIO_MODE_MODE8_Pos)                                 /*!< 0x00030000 */
#define GPIO_MODE_MODE8                                             GPIO_MODE_MODE8_Msk
#define GPIO_MODE_MODE8_0                                           (0x1UL << GPIO_MODE_MODE8_Pos)                                 /*!< 0x00010000 */
#define GPIO_MODE_MODE8_1                                           (0x2UL << GPIO_MODE_MODE8_Pos)                                 /*!< 0x00020000 */
#define GPIO_MODE_MODE9_Pos                                         (18U)
#define GPIO_MODE_MODE9_Msk                                         (0x3UL << GPIO_MODE_MODE9_Pos)                                 /*!< 0x000C0000 */
#define GPIO_MODE_MODE9                                             GPIO_MODE_MODE9_Msk
#define GPIO_MODE_MODE9_0                                           (0x1UL << GPIO_MODE_MODE9_Pos)                                 /*!< 0x00040000 */
#define GPIO_MODE_MODE9_1                                           (0x2UL << GPIO_MODE_MODE9_Pos)                                 /*!< 0x00080000 */
#define GPIO_MODE_MODE10_Pos                                        (20U)
#define GPIO_MODE_MODE10_Msk                                        (0x3UL << GPIO_MODE_MODE10_Pos)                                /*!< 0x00300000 */
#define GPIO_MODE_MODE10                                            GPIO_MODE_MODE10_Msk
#define GPIO_MODE_MODE10_0                                          (0x1UL << GPIO_MODE_MODE10_Pos)                                /*!< 0x00100000 */
#define GPIO_MODE_MODE10_1                                          (0x2UL << GPIO_MODE_MODE10_Pos)                                /*!< 0x00200000 */
#define GPIO_MODE_MODE11_Pos                                        (22U)
#define GPIO_MODE_MODE11_Msk                                        (0x3UL << GPIO_MODE_MODE11_Pos)                                /*!< 0x00C00000 */
#define GPIO_MODE_MODE11                                            GPIO_MODE_MODE11_Msk
#define GPIO_MODE_MODE11_0                                          (0x1UL << GPIO_MODE_MODE11_Pos)                                /*!< 0x00400000 */
#define GPIO_MODE_MODE11_1                                          (0x2UL << GPIO_MODE_MODE11_Pos)                                /*!< 0x00800000 */
#define GPIO_MODE_MODE12_Pos                                        (24U)
#define GPIO_MODE_MODE12_Msk                                        (0x3UL << GPIO_MODE_MODE12_Pos)                                /*!< 0x03000000 */
#define GPIO_MODE_MODE12                                            GPIO_MODE_MODE12_Msk
#define GPIO_MODE_MODE12_0                                          (0x1UL << GPIO_MODE_MODE12_Pos)                                /*!< 0x01000000 */
#define GPIO_MODE_MODE12_1                                          (0x2UL << GPIO_MODE_MODE12_Pos)                                /*!< 0x02000000 */
#define GPIO_MODE_MODE13_Pos                                        (26U)
#define GPIO_MODE_MODE13_Msk                                        (0x3UL << GPIO_MODE_MODE13_Pos)                                /*!< 0x0C000000 */
#define GPIO_MODE_MODE13                                            GPIO_MODE_MODE13_Msk
#define GPIO_MODE_MODE13_0                                          (0x1UL << GPIO_MODE_MODE13_Pos)                                /*!< 0x04000000 */
#define GPIO_MODE_MODE13_1                                          (0x2UL << GPIO_MODE_MODE13_Pos)                                /*!< 0x08000000 */
#define GPIO_MODE_MODE14_Pos                                        (28U)
#define GPIO_MODE_MODE14_Msk                                        (0x3UL << GPIO_MODE_MODE14_Pos)                                /*!< 0x30000000 */
#define GPIO_MODE_MODE14                                            GPIO_MODE_MODE14_Msk
#define GPIO_MODE_MODE14_0                                          (0x1UL << GPIO_MODE_MODE14_Pos)                                /*!< 0x10000000 */
#define GPIO_MODE_MODE14_1                                          (0x2UL << GPIO_MODE_MODE14_Pos)                                /*!< 0x20000000 */
#define GPIO_MODE_MODE15_Pos                                        (30U)
#define GPIO_MODE_MODE15_Msk                                        (0x3UL << GPIO_MODE_MODE15_Pos)                                /*!< 0xC0000000 */
#define GPIO_MODE_MODE15                                            GPIO_MODE_MODE15_Msk
#define GPIO_MODE_MODE15_0                                          (0x1UL << GPIO_MODE_MODE15_Pos)                                /*!< 0x40000000 */
#define GPIO_MODE_MODE15_1                                          (0x2UL << GPIO_MODE_MODE15_Pos)                                /*!< 0x80000000 */

/******************  Bits definition for GPIO_OMODE register  ****************/
#define GPIO_OMODE_OMODE0_Pos                                       (0U)
#define GPIO_OMODE_OMODE0_Msk                                       (0x1UL << GPIO_OMODE_OMODE0_Pos)                               /*!< 0x00000001 */
#define GPIO_OMODE_OMODE0                                           GPIO_OMODE_OMODE0_Msk
#define GPIO_OMODE_OMODE1_Pos                                       (1U)
#define GPIO_OMODE_OMODE1_Msk                                       (0x1UL << GPIO_OMODE_OMODE1_Pos)                               /*!< 0x00000002 */
#define GPIO_OMODE_OMODE1                                           GPIO_OMODE_OMODE1_Msk
#define GPIO_OMODE_OMODE2_Pos                                       (2U)
#define GPIO_OMODE_OMODE2_Msk                                       (0x1UL << GPIO_OMODE_OMODE2_Pos)                               /*!< 0x00000004 */
#define GPIO_OMODE_OMODE2                                           GPIO_OMODE_OMODE2_Msk
#define GPIO_OMODE_OMODE3_Pos                                       (3U)
#define GPIO_OMODE_OMODE3_Msk                                       (0x1UL << GPIO_OMODE_OMODE3_Pos)                               /*!< 0x00000008 */
#define GPIO_OMODE_OMODE3                                           GPIO_OMODE_OMODE3_Msk
#define GPIO_OMODE_OMODE4_Pos                                       (4U)
#define GPIO_OMODE_OMODE4_Msk                                       (0x1UL << GPIO_OMODE_OMODE4_Pos)                               /*!< 0x00000010 */
#define GPIO_OMODE_OMODE4                                           GPIO_OMODE_OMODE4_Msk
#define GPIO_OMODE_OMODE5_Pos                                       (5U)
#define GPIO_OMODE_OMODE5_Msk                                       (0x1UL << GPIO_OMODE_OMODE5_Pos)                               /*!< 0x00000020 */
#define GPIO_OMODE_OMODE5                                           GPIO_OMODE_OMODE5_Msk
#define GPIO_OMODE_OMODE6_Pos                                       (6U)
#define GPIO_OMODE_OMODE6_Msk                                       (0x1UL << GPIO_OMODE_OMODE6_Pos)                               /*!< 0x00000040 */
#define GPIO_OMODE_OMODE6                                           GPIO_OMODE_OMODE6_Msk
#define GPIO_OMODE_OMODE7_Pos                                       (7U)
#define GPIO_OMODE_OMODE7_Msk                                       (0x1UL << GPIO_OMODE_OMODE7_Pos)                               /*!< 0x00000080 */
#define GPIO_OMODE_OMODE7                                           GPIO_OMODE_OMODE7_Msk
#define GPIO_OMODE_OMODE8_Pos                                       (8U)
#define GPIO_OMODE_OMODE8_Msk                                       (0x1UL << GPIO_OMODE_OMODE8_Pos)                               /*!< 0x00000100 */
#define GPIO_OMODE_OMODE8                                           GPIO_OMODE_OMODE8_Msk
#define GPIO_OMODE_OMODE9_Pos                                       (9U)
#define GPIO_OMODE_OMODE9_Msk                                       (0x1UL << GPIO_OMODE_OMODE9_Pos)                               /*!< 0x00000200 */
#define GPIO_OMODE_OMODE9                                           GPIO_OMODE_OMODE9_Msk
#define GPIO_OMODE_OMODE10_Pos                                      (10U)
#define GPIO_OMODE_OMODE10_Msk                                      (0x1UL << GPIO_OMODE_OMODE10_Pos)                              /*!< 0x00000400 */
#define GPIO_OMODE_OMODE10                                          GPIO_OMODE_OMODE10_Msk
#define GPIO_OMODE_OMODE11_Pos                                      (11U)
#define GPIO_OMODE_OMODE11_Msk                                      (0x1UL << GPIO_OMODE_OMODE11_Pos)                              /*!< 0x00000800 */
#define GPIO_OMODE_OMODE11                                          GPIO_OMODE_OMODE11_Msk
#define GPIO_OMODE_OMODE12_Pos                                      (12U)
#define GPIO_OMODE_OMODE12_Msk                                      (0x1UL << GPIO_OMODE_OMODE12_Pos)                              /*!< 0x00001000 */
#define GPIO_OMODE_OMODE12                                          GPIO_OMODE_OMODE12_Msk
#define GPIO_OMODE_OMODE13_Pos                                      (13U)
#define GPIO_OMODE_OMODE13_Msk                                      (0x1UL << GPIO_OMODE_OMODE13_Pos)                              /*!< 0x00002000 */
#define GPIO_OMODE_OMODE13                                          GPIO_OMODE_OMODE13_Msk
#define GPIO_OMODE_OMODE14_Pos                                      (14U)
#define GPIO_OMODE_OMODE14_Msk                                      (0x1UL << GPIO_OMODE_OMODE14_Pos)                              /*!< 0x00004000 */
#define GPIO_OMODE_OMODE14                                          GPIO_OMODE_OMODE14_Msk
#define GPIO_OMODE_OMODE15_Pos                                      (15U)
#define GPIO_OMODE_OMODE15_Msk                                      (0x1UL << GPIO_OMODE_OMODE15_Pos)                              /*!< 0x00008000 */
#define GPIO_OMODE_OMODE15                                          GPIO_OMODE_OMODE15_Msk

/* Legacy defines */
#define GPIO_OMODE_OT_0                                             GPIO_OMODE_OMODE0
#define GPIO_OMODE_OT_1                                             GPIO_OMODE_OMODE1
#define GPIO_OMODE_OT_2                                             GPIO_OMODE_OMODE2
#define GPIO_OMODE_OT_3                                             GPIO_OMODE_OMODE3
#define GPIO_OMODE_OT_4                                             GPIO_OMODE_OMODE4
#define GPIO_OMODE_OT_5                                             GPIO_OMODE_OMODE5
#define GPIO_OMODE_OT_6                                             GPIO_OMODE_OMODE6
#define GPIO_OMODE_OT_7                                             GPIO_OMODE_OMODE7
#define GPIO_OMODE_OT_8                                             GPIO_OMODE_OMODE8
#define GPIO_OMODE_OT_9                                             GPIO_OMODE_OMODE9
#define GPIO_OMODE_OT_10                                            GPIO_OMODE_OMODE10
#define GPIO_OMODE_OT_11                                            GPIO_OMODE_OMODE11
#define GPIO_OMODE_OT_12                                            GPIO_OMODE_OMODE12
#define GPIO_OMODE_OT_13                                            GPIO_OMODE_OMODE13
#define GPIO_OMODE_OT_14                                            GPIO_OMODE_OMODE14
#define GPIO_OMODE_OT_15                                            GPIO_OMODE_OMODE15

/******************  Bits definition for GPIO_OSSEL register  ***************/
#define GPIO_OSSEL_OSSEL0_Pos                                       (0U)
#define GPIO_OSSEL_OSSEL0_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL0_Pos)                               /*!< 0x00000003 */
#define GPIO_OSSEL_OSSEL0                                           GPIO_OSSEL_OSSEL0_Msk
#define GPIO_OSSEL_OSSEL0_0                                         (0x1UL << GPIO_OSSEL_OSSEL0_Pos)                               /*!< 0x00000001 */
#define GPIO_OSSEL_OSSEL0_1                                         (0x2UL << GPIO_OSSEL_OSSEL0_Pos)                               /*!< 0x00000002 */
#define GPIO_OSSEL_OSSEL1_Pos                                       (2U)
#define GPIO_OSSEL_OSSEL1_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL1_Pos)                               /*!< 0x0000000C */
#define GPIO_OSSEL_OSSEL1                                           GPIO_OSSEL_OSSEL1_Msk
#define GPIO_OSSEL_OSSEL1_0                                         (0x1UL << GPIO_OSSEL_OSSEL1_Pos)                               /*!< 0x00000004 */
#define GPIO_OSSEL_OSSEL1_1                                         (0x2UL << GPIO_OSSEL_OSSEL1_Pos)                               /*!< 0x00000008 */
#define GPIO_OSSEL_OSSEL2_Pos                                       (4U)
#define GPIO_OSSEL_OSSEL2_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL2_Pos)                               /*!< 0x00000030 */
#define GPIO_OSSEL_OSSEL2                                           GPIO_OSSEL_OSSEL2_Msk
#define GPIO_OSSEL_OSSEL2_0                                         (0x1UL << GPIO_OSSEL_OSSEL2_Pos)                               /*!< 0x00000010 */
#define GPIO_OSSEL_OSSEL2_1                                         (0x2UL << GPIO_OSSEL_OSSEL2_Pos)                               /*!< 0x00000020 */
#define GPIO_OSSEL_OSSEL3_Pos                                       (6U)
#define GPIO_OSSEL_OSSEL3_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL3_Pos)                               /*!< 0x000000C0 */
#define GPIO_OSSEL_OSSEL3                                           GPIO_OSSEL_OSSEL3_Msk
#define GPIO_OSSEL_OSSEL3_0                                         (0x1UL << GPIO_OSSEL_OSSEL3_Pos)                               /*!< 0x00000040 */
#define GPIO_OSSEL_OSSEL3_1                                         (0x2UL << GPIO_OSSEL_OSSEL3_Pos)                               /*!< 0x00000080 */
#define GPIO_OSSEL_OSSEL4_Pos                                       (8U)
#define GPIO_OSSEL_OSSEL4_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL4_Pos)                               /*!< 0x00000300 */
#define GPIO_OSSEL_OSSEL4                                           GPIO_OSSEL_OSSEL4_Msk
#define GPIO_OSSEL_OSSEL4_0                                         (0x1UL << GPIO_OSSEL_OSSEL4_Pos)                               /*!< 0x00000100 */
#define GPIO_OSSEL_OSSEL4_1                                         (0x2UL << GPIO_OSSEL_OSSEL4_Pos)                               /*!< 0x00000200 */
#define GPIO_OSSEL_OSSEL5_Pos                                       (10U)
#define GPIO_OSSEL_OSSEL5_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL5_Pos)                               /*!< 0x00000C00 */
#define GPIO_OSSEL_OSSEL5                                           GPIO_OSSEL_OSSEL5_Msk
#define GPIO_OSSEL_OSSEL5_0                                         (0x1UL << GPIO_OSSEL_OSSEL5_Pos)                               /*!< 0x00000400 */
#define GPIO_OSSEL_OSSEL5_1                                         (0x2UL << GPIO_OSSEL_OSSEL5_Pos)                               /*!< 0x00000800 */
#define GPIO_OSSEL_OSSEL6_Pos                                       (12U)
#define GPIO_OSSEL_OSSEL6_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL6_Pos)                               /*!< 0x00003000 */
#define GPIO_OSSEL_OSSEL6                                           GPIO_OSSEL_OSSEL6_Msk
#define GPIO_OSSEL_OSSEL6_0                                         (0x1UL << GPIO_OSSEL_OSSEL6_Pos)                               /*!< 0x00001000 */
#define GPIO_OSSEL_OSSEL6_1                                         (0x2UL << GPIO_OSSEL_OSSEL6_Pos)                               /*!< 0x00002000 */
#define GPIO_OSSEL_OSSEL7_Pos                                       (14U)
#define GPIO_OSSEL_OSSEL7_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL7_Pos)                               /*!< 0x0000C000 */
#define GPIO_OSSEL_OSSEL7                                           GPIO_OSSEL_OSSEL7_Msk
#define GPIO_OSSEL_OSSEL7_0                                         (0x1UL << GPIO_OSSEL_OSSEL7_Pos)                               /*!< 0x00004000 */
#define GPIO_OSSEL_OSSEL7_1                                         (0x2UL << GPIO_OSSEL_OSSEL7_Pos)                               /*!< 0x00008000 */
#define GPIO_OSSEL_OSSEL8_Pos                                       (16U)
#define GPIO_OSSEL_OSSEL8_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL8_Pos)                               /*!< 0x00030000 */
#define GPIO_OSSEL_OSSEL8                                           GPIO_OSSEL_OSSEL8_Msk
#define GPIO_OSSEL_OSSEL8_0                                         (0x1UL << GPIO_OSSEL_OSSEL8_Pos)                               /*!< 0x00010000 */
#define GPIO_OSSEL_OSSEL8_1                                         (0x2UL << GPIO_OSSEL_OSSEL8_Pos)                               /*!< 0x00020000 */
#define GPIO_OSSEL_OSSEL9_Pos                                       (18U)
#define GPIO_OSSEL_OSSEL9_Msk                                       (0x3UL << GPIO_OSSEL_OSSEL9_Pos)                               /*!< 0x000C0000 */
#define GPIO_OSSEL_OSSEL9                                           GPIO_OSSEL_OSSEL9_Msk
#define GPIO_OSSEL_OSSEL9_0                                         (0x1UL << GPIO_OSSEL_OSSEL9_Pos)                               /*!< 0x00040000 */
#define GPIO_OSSEL_OSSEL9_1                                         (0x2UL << GPIO_OSSEL_OSSEL9_Pos)                               /*!< 0x00080000 */
#define GPIO_OSSEL_OSSEL10_Pos                                      (20U)
#define GPIO_OSSEL_OSSEL10_Msk                                      (0x3UL << GPIO_OSSEL_OSSEL10_Pos)                              /*!< 0x00300000 */
#define GPIO_OSSEL_OSSEL10                                          GPIO_OSSEL_OSSEL10_Msk
#define GPIO_OSSEL_OSSEL10_0                                        (0x1UL << GPIO_OSSEL_OSSEL10_Pos)                              /*!< 0x00100000 */
#define GPIO_OSSEL_OSSEL10_1                                        (0x2UL << GPIO_OSSEL_OSSEL10_Pos)                              /*!< 0x00200000 */
#define GPIO_OSSEL_OSSEL11_Pos                                      (22U)
#define GPIO_OSSEL_OSSEL11_Msk                                      (0x3UL << GPIO_OSSEL_OSSEL11_Pos)                              /*!< 0x00C00000 */
#define GPIO_OSSEL_OSSEL11                                          GPIO_OSSEL_OSSEL11_Msk
#define GPIO_OSSEL_OSSEL11_0                                        (0x1UL << GPIO_OSSEL_OSSEL11_Pos)                              /*!< 0x00400000 */
#define GPIO_OSSEL_OSSEL11_1                                        (0x2UL << GPIO_OSSEL_OSSEL11_Pos)                              /*!< 0x00800000 */
#define GPIO_OSSEL_OSSEL12_Pos                                      (24U)
#define GPIO_OSSEL_OSSEL12_Msk                                      (0x3UL << GPIO_OSSEL_OSSEL12_Pos)                              /*!< 0x03000000 */
#define GPIO_OSSEL_OSSEL12                                          GPIO_OSSEL_OSSEL12_Msk
#define GPIO_OSSEL_OSSEL12_0                                        (0x1UL << GPIO_OSSEL_OSSEL12_Pos)                              /*!< 0x01000000 */
#define GPIO_OSSEL_OSSEL12_1                                        (0x2UL << GPIO_OSSEL_OSSEL12_Pos)                              /*!< 0x02000000 */
#define GPIO_OSSEL_OSSEL13_Pos                                      (26U)
#define GPIO_OSSEL_OSSEL13_Msk                                      (0x3UL << GPIO_OSSEL_OSSEL13_Pos)                              /*!< 0x0C000000 */
#define GPIO_OSSEL_OSSEL13                                          GPIO_OSSEL_OSSEL13_Msk
#define GPIO_OSSEL_OSSEL13_0                                        (0x1UL << GPIO_OSSEL_OSSEL13_Pos)                              /*!< 0x04000000 */
#define GPIO_OSSEL_OSSEL13_1                                        (0x2UL << GPIO_OSSEL_OSSEL13_Pos)                              /*!< 0x08000000 */
#define GPIO_OSSEL_OSSEL14_Pos                                      (28U)
#define GPIO_OSSEL_OSSEL14_Msk                                      (0x3UL << GPIO_OSSEL_OSSEL14_Pos)                              /*!< 0x30000000 */
#define GPIO_OSSEL_OSSEL14                                          GPIO_OSSEL_OSSEL14_Msk
#define GPIO_OSSEL_OSSEL14_0                                        (0x1UL << GPIO_OSSEL_OSSEL14_Pos)                              /*!< 0x10000000 */
#define GPIO_OSSEL_OSSEL14_1                                        (0x2UL << GPIO_OSSEL_OSSEL14_Pos)                              /*!< 0x20000000 */
#define GPIO_OSSEL_OSSEL15_Pos                                      (30U)
#define GPIO_OSSEL_OSSEL15_Msk                                      (0x3UL << GPIO_OSSEL_OSSEL15_Pos)                              /*!< 0xC0000000 */
#define GPIO_OSSEL_OSSEL15                                          GPIO_OSSEL_OSSEL15_Msk
#define GPIO_OSSEL_OSSEL15_0                                        (0x1UL << GPIO_OSSEL_OSSEL15_Pos)                              /*!< 0x40000000 */
#define GPIO_OSSEL_OSSEL15_1                                        (0x2UL << GPIO_OSSEL_OSSEL15_Pos)                              /*!< 0x80000000 */

/* Legacy defines */
#define GPIO_OSPEEDER_OSPEEDR0                                      GPIO_OSSEL_OSSEL0
#define GPIO_OSPEEDER_OSPEEDR0_0                                    GPIO_OSSEL_OSSEL0_0
#define GPIO_OSPEEDER_OSPEEDR0_1                                    GPIO_OSSEL_OSSEL0_1
#define GPIO_OSPEEDER_OSPEEDR1                                      GPIO_OSSEL_OSSEL1
#define GPIO_OSPEEDER_OSPEEDR1_0                                    GPIO_OSSEL_OSSEL1_0
#define GPIO_OSPEEDER_OSPEEDR1_1                                    GPIO_OSSEL_OSSEL1_1
#define GPIO_OSPEEDER_OSPEEDR2                                      GPIO_OSSEL_OSSEL2
#define GPIO_OSPEEDER_OSPEEDR2_0                                    GPIO_OSSEL_OSSEL2_0
#define GPIO_OSPEEDER_OSPEEDR2_1                                    GPIO_OSSEL_OSSEL2_1
#define GPIO_OSPEEDER_OSPEEDR3                                      GPIO_OSSEL_OSSEL3
#define GPIO_OSPEEDER_OSPEEDR3_0                                    GPIO_OSSEL_OSSEL3_0
#define GPIO_OSPEEDER_OSPEEDR3_1                                    GPIO_OSSEL_OSSEL3_1
#define GPIO_OSPEEDER_OSPEEDR4                                      GPIO_OSSEL_OSSEL4
#define GPIO_OSPEEDER_OSPEEDR4_0                                    GPIO_OSSEL_OSSEL4_0
#define GPIO_OSPEEDER_OSPEEDR4_1                                    GPIO_OSSEL_OSSEL4_1
#define GPIO_OSPEEDER_OSPEEDR5                                      GPIO_OSSEL_OSSEL5
#define GPIO_OSPEEDER_OSPEEDR5_0                                    GPIO_OSSEL_OSSEL5_0
#define GPIO_OSPEEDER_OSPEEDR5_1                                    GPIO_OSSEL_OSSEL5_1
#define GPIO_OSPEEDER_OSPEEDR6                                      GPIO_OSSEL_OSSEL6
#define GPIO_OSPEEDER_OSPEEDR6_0                                    GPIO_OSSEL_OSSEL6_0
#define GPIO_OSPEEDER_OSPEEDR6_1                                    GPIO_OSSEL_OSSEL6_1
#define GPIO_OSPEEDER_OSPEEDR7                                      GPIO_OSSEL_OSSEL7
#define GPIO_OSPEEDER_OSPEEDR7_0                                    GPIO_OSSEL_OSSEL7_0
#define GPIO_OSPEEDER_OSPEEDR7_1                                    GPIO_OSSEL_OSSEL7_1
#define GPIO_OSPEEDER_OSPEEDR8                                      GPIO_OSSEL_OSSEL8
#define GPIO_OSPEEDER_OSPEEDR8_0                                    GPIO_OSSEL_OSSEL8_0
#define GPIO_OSPEEDER_OSPEEDR8_1                                    GPIO_OSSEL_OSSEL8_1
#define GPIO_OSPEEDER_OSPEEDR9                                      GPIO_OSSEL_OSSEL9
#define GPIO_OSPEEDER_OSPEEDR9_0                                    GPIO_OSSEL_OSSEL9_0
#define GPIO_OSPEEDER_OSPEEDR9_1                                    GPIO_OSSEL_OSSEL9_1
#define GPIO_OSPEEDER_OSPEEDR10                                     GPIO_OSSEL_OSSEL10
#define GPIO_OSPEEDER_OSPEEDR10_0                                   GPIO_OSSEL_OSSEL10_0
#define GPIO_OSPEEDER_OSPEEDR10_1                                   GPIO_OSSEL_OSSEL10_1
#define GPIO_OSPEEDER_OSPEEDR11                                     GPIO_OSSEL_OSSEL11
#define GPIO_OSPEEDER_OSPEEDR11_0                                   GPIO_OSSEL_OSSEL11_0
#define GPIO_OSPEEDER_OSPEEDR11_1                                   GPIO_OSSEL_OSSEL11_1
#define GPIO_OSPEEDER_OSPEEDR12                                     GPIO_OSSEL_OSSEL12
#define GPIO_OSPEEDER_OSPEEDR12_0                                   GPIO_OSSEL_OSSEL12_0
#define GPIO_OSPEEDER_OSPEEDR12_1                                   GPIO_OSSEL_OSSEL12_1
#define GPIO_OSPEEDER_OSPEEDR13                                     GPIO_OSSEL_OSSEL13
#define GPIO_OSPEEDER_OSPEEDR13_0                                   GPIO_OSSEL_OSSEL13_0
#define GPIO_OSPEEDER_OSPEEDR13_1                                   GPIO_OSSEL_OSSEL13_1
#define GPIO_OSPEEDER_OSPEEDR14                                     GPIO_OSSEL_OSSEL14
#define GPIO_OSPEEDER_OSPEEDR14_0                                   GPIO_OSSEL_OSSEL14_0
#define GPIO_OSPEEDER_OSPEEDR14_1                                   GPIO_OSSEL_OSSEL14_1
#define GPIO_OSPEEDER_OSPEEDR15                                     GPIO_OSSEL_OSSEL15
#define GPIO_OSPEEDER_OSPEEDR15_0                                   GPIO_OSSEL_OSSEL15_0
#define GPIO_OSPEEDER_OSPEEDR15_1                                   GPIO_OSSEL_OSSEL15_1

/******************  Bits definition for GPIO_PUPD register  *****************/
#define GPIO_PUPD_PUPD0_Pos                                         (0U)
#define GPIO_PUPD_PUPD0_Msk                                         (0x3UL << GPIO_PUPD_PUPD0_Pos)                                 /*!< 0x00000003 */
#define GPIO_PUPD_PUPD0                                             GPIO_PUPD_PUPD0_Msk
#define GPIO_PUPD_PUPD0_0                                           (0x1UL << GPIO_PUPD_PUPD0_Pos)                                 /*!< 0x00000001 */
#define GPIO_PUPD_PUPD0_1                                           (0x2UL << GPIO_PUPD_PUPD0_Pos)                                 /*!< 0x00000002 */
#define GPIO_PUPD_PUPD1_Pos                                         (2U)
#define GPIO_PUPD_PUPD1_Msk                                         (0x3UL << GPIO_PUPD_PUPD1_Pos)                                 /*!< 0x0000000C */
#define GPIO_PUPD_PUPD1                                             GPIO_PUPD_PUPD1_Msk
#define GPIO_PUPD_PUPD1_0                                           (0x1UL << GPIO_PUPD_PUPD1_Pos)                                 /*!< 0x00000004 */
#define GPIO_PUPD_PUPD1_1                                           (0x2UL << GPIO_PUPD_PUPD1_Pos)                                 /*!< 0x00000008 */
#define GPIO_PUPD_PUPD2_Pos                                         (4U)
#define GPIO_PUPD_PUPD2_Msk                                         (0x3UL << GPIO_PUPD_PUPD2_Pos)                                 /*!< 0x00000030 */
#define GPIO_PUPD_PUPD2                                             GPIO_PUPD_PUPD2_Msk
#define GPIO_PUPD_PUPD2_0                                           (0x1UL << GPIO_PUPD_PUPD2_Pos)                                 /*!< 0x00000010 */
#define GPIO_PUPD_PUPD2_1                                           (0x2UL << GPIO_PUPD_PUPD2_Pos)                                 /*!< 0x00000020 */
#define GPIO_PUPD_PUPD3_Pos                                         (6U)
#define GPIO_PUPD_PUPD3_Msk                                         (0x3UL << GPIO_PUPD_PUPD3_Pos)                                 /*!< 0x000000C0 */
#define GPIO_PUPD_PUPD3                                             GPIO_PUPD_PUPD3_Msk
#define GPIO_PUPD_PUPD3_0                                           (0x1UL << GPIO_PUPD_PUPD3_Pos)                                 /*!< 0x00000040 */
#define GPIO_PUPD_PUPD3_1                                           (0x2UL << GPIO_PUPD_PUPD3_Pos)                                 /*!< 0x00000080 */
#define GPIO_PUPD_PUPD4_Pos                                         (8U)
#define GPIO_PUPD_PUPD4_Msk                                         (0x3UL << GPIO_PUPD_PUPD4_Pos)                                 /*!< 0x00000300 */
#define GPIO_PUPD_PUPD4                                             GPIO_PUPD_PUPD4_Msk
#define GPIO_PUPD_PUPD4_0                                           (0x1UL << GPIO_PUPD_PUPD4_Pos)                                 /*!< 0x00000100 */
#define GPIO_PUPD_PUPD4_1                                           (0x2UL << GPIO_PUPD_PUPD4_Pos)                                 /*!< 0x00000200 */
#define GPIO_PUPD_PUPD5_Pos                                         (10U)
#define GPIO_PUPD_PUPD5_Msk                                         (0x3UL << GPIO_PUPD_PUPD5_Pos)                                 /*!< 0x00000C00 */
#define GPIO_PUPD_PUPD5                                             GPIO_PUPD_PUPD5_Msk
#define GPIO_PUPD_PUPD5_0                                           (0x1UL << GPIO_PUPD_PUPD5_Pos)                                 /*!< 0x00000400 */
#define GPIO_PUPD_PUPD5_1                                           (0x2UL << GPIO_PUPD_PUPD5_Pos)                                 /*!< 0x00000800 */
#define GPIO_PUPD_PUPD6_Pos                                         (12U)
#define GPIO_PUPD_PUPD6_Msk                                         (0x3UL << GPIO_PUPD_PUPD6_Pos)                                 /*!< 0x00003000 */
#define GPIO_PUPD_PUPD6                                             GPIO_PUPD_PUPD6_Msk
#define GPIO_PUPD_PUPD6_0                                           (0x1UL << GPIO_PUPD_PUPD6_Pos)                                 /*!< 0x00001000 */
#define GPIO_PUPD_PUPD6_1                                           (0x2UL << GPIO_PUPD_PUPD6_Pos)                                 /*!< 0x00002000 */
#define GPIO_PUPD_PUPD7_Pos                                         (14U)
#define GPIO_PUPD_PUPD7_Msk                                         (0x3UL << GPIO_PUPD_PUPD7_Pos)                                 /*!< 0x0000C000 */
#define GPIO_PUPD_PUPD7                                             GPIO_PUPD_PUPD7_Msk
#define GPIO_PUPD_PUPD7_0                                           (0x1UL << GPIO_PUPD_PUPD7_Pos)                                 /*!< 0x00004000 */
#define GPIO_PUPD_PUPD7_1                                           (0x2UL << GPIO_PUPD_PUPD7_Pos)                                 /*!< 0x00008000 */
#define GPIO_PUPD_PUPD8_Pos                                         (16U)
#define GPIO_PUPD_PUPD8_Msk                                         (0x3UL << GPIO_PUPD_PUPD8_Pos)                                 /*!< 0x00030000 */
#define GPIO_PUPD_PUPD8                                             GPIO_PUPD_PUPD8_Msk
#define GPIO_PUPD_PUPD8_0                                           (0x1UL << GPIO_PUPD_PUPD8_Pos)                                 /*!< 0x00010000 */
#define GPIO_PUPD_PUPD8_1                                           (0x2UL << GPIO_PUPD_PUPD8_Pos)                                 /*!< 0x00020000 */
#define GPIO_PUPD_PUPD9_Pos                                         (18U)
#define GPIO_PUPD_PUPD9_Msk                                         (0x3UL << GPIO_PUPD_PUPD9_Pos)                                 /*!< 0x000C0000 */
#define GPIO_PUPD_PUPD9                                             GPIO_PUPD_PUPD9_Msk
#define GPIO_PUPD_PUPD9_0                                           (0x1UL << GPIO_PUPD_PUPD9_Pos)                                 /*!< 0x00040000 */
#define GPIO_PUPD_PUPD9_1                                           (0x2UL << GPIO_PUPD_PUPD9_Pos)                                 /*!< 0x00080000 */
#define GPIO_PUPD_PUPD10_Pos                                        (20U)
#define GPIO_PUPD_PUPD10_Msk                                        (0x3UL << GPIO_PUPD_PUPD10_Pos)                                /*!< 0x00300000 */
#define GPIO_PUPD_PUPD10                                            GPIO_PUPD_PUPD10_Msk
#define GPIO_PUPD_PUPD10_0                                          (0x1UL << GPIO_PUPD_PUPD10_Pos)                                /*!< 0x00100000 */
#define GPIO_PUPD_PUPD10_1                                          (0x2UL << GPIO_PUPD_PUPD10_Pos)                                /*!< 0x00200000 */
#define GPIO_PUPD_PUPD11_Pos                                        (22U)
#define GPIO_PUPD_PUPD11_Msk                                        (0x3UL << GPIO_PUPD_PUPD11_Pos)                                /*!< 0x00C00000 */
#define GPIO_PUPD_PUPD11                                            GPIO_PUPD_PUPD11_Msk
#define GPIO_PUPD_PUPD11_0                                          (0x1UL << GPIO_PUPD_PUPD11_Pos)                                /*!< 0x00400000 */
#define GPIO_PUPD_PUPD11_1                                          (0x2UL << GPIO_PUPD_PUPD11_Pos)                                /*!< 0x00800000 */
#define GPIO_PUPD_PUPD12_Pos                                        (24U)
#define GPIO_PUPD_PUPD12_Msk                                        (0x3UL << GPIO_PUPD_PUPD12_Pos)                                /*!< 0x03000000 */
#define GPIO_PUPD_PUPD12                                            GPIO_PUPD_PUPD12_Msk
#define GPIO_PUPD_PUPD12_0                                          (0x1UL << GPIO_PUPD_PUPD12_Pos)                                /*!< 0x01000000 */
#define GPIO_PUPD_PUPD12_1                                          (0x2UL << GPIO_PUPD_PUPD12_Pos)                                /*!< 0x02000000 */
#define GPIO_PUPD_PUPD13_Pos                                        (26U)
#define GPIO_PUPD_PUPD13_Msk                                        (0x3UL << GPIO_PUPD_PUPD13_Pos)                                /*!< 0x0C000000 */
#define GPIO_PUPD_PUPD13                                            GPIO_PUPD_PUPD13_Msk
#define GPIO_PUPD_PUPD13_0                                          (0x1UL << GPIO_PUPD_PUPD13_Pos)                                /*!< 0x04000000 */
#define GPIO_PUPD_PUPD13_1                                          (0x2UL << GPIO_PUPD_PUPD13_Pos)                                /*!< 0x08000000 */
#define GPIO_PUPD_PUPD14_Pos                                        (28U)
#define GPIO_PUPD_PUPD14_Msk                                        (0x3UL << GPIO_PUPD_PUPD14_Pos)                                /*!< 0x30000000 */
#define GPIO_PUPD_PUPD14                                            GPIO_PUPD_PUPD14_Msk
#define GPIO_PUPD_PUPD14_0                                          (0x1UL << GPIO_PUPD_PUPD14_Pos)                                /*!< 0x10000000 */
#define GPIO_PUPD_PUPD14_1                                          (0x2UL << GPIO_PUPD_PUPD14_Pos)                                /*!< 0x20000000 */
#define GPIO_PUPD_PUPD15_Pos                                        (30U)
#define GPIO_PUPD_PUPD15_Msk                                        (0x3UL << GPIO_PUPD_PUPD15_Pos)                                /*!< 0xC0000000 */
#define GPIO_PUPD_PUPD15                                            GPIO_PUPD_PUPD15_Msk
#define GPIO_PUPD_PUPD15_0                                          (0x1UL << GPIO_PUPD_PUPD15_Pos)                                /*!< 0x40000000 */
#define GPIO_PUPD_PUPD15_1                                          (0x2UL << GPIO_PUPD_PUPD15_Pos)                                /*!< 0x80000000 */

/* Legacy defines */
#define GPIO_PUPD_PUPDR0                                            GPIO_PUPD_PUPD0
#define GPIO_PUPD_PUPDR0_0                                          GPIO_PUPD_PUPD0_0
#define GPIO_PUPD_PUPDR0_1                                          GPIO_PUPD_PUPD0_1
#define GPIO_PUPD_PUPDR1                                            GPIO_PUPD_PUPD1
#define GPIO_PUPD_PUPDR1_0                                          GPIO_PUPD_PUPD1_0
#define GPIO_PUPD_PUPDR1_1                                          GPIO_PUPD_PUPD1_1
#define GPIO_PUPD_PUPDR2                                            GPIO_PUPD_PUPD2
#define GPIO_PUPD_PUPDR2_0                                          GPIO_PUPD_PUPD2_0
#define GPIO_PUPD_PUPDR2_1                                          GPIO_PUPD_PUPD2_1
#define GPIO_PUPD_PUPDR3                                            GPIO_PUPD_PUPD3
#define GPIO_PUPD_PUPDR3_0                                          GPIO_PUPD_PUPD3_0
#define GPIO_PUPD_PUPDR3_1                                          GPIO_PUPD_PUPD3_1
#define GPIO_PUPD_PUPDR4                                            GPIO_PUPD_PUPD4
#define GPIO_PUPD_PUPDR4_0                                          GPIO_PUPD_PUPD4_0
#define GPIO_PUPD_PUPDR4_1                                          GPIO_PUPD_PUPD4_1
#define GPIO_PUPD_PUPDR5                                            GPIO_PUPD_PUPD5
#define GPIO_PUPD_PUPDR5_0                                          GPIO_PUPD_PUPD5_0
#define GPIO_PUPD_PUPDR5_1                                          GPIO_PUPD_PUPD5_1
#define GPIO_PUPD_PUPDR6                                            GPIO_PUPD_PUPD6
#define GPIO_PUPD_PUPDR6_0                                          GPIO_PUPD_PUPD6_0
#define GPIO_PUPD_PUPDR6_1                                          GPIO_PUPD_PUPD6_1
#define GPIO_PUPD_PUPDR7                                            GPIO_PUPD_PUPD7
#define GPIO_PUPD_PUPDR7_0                                          GPIO_PUPD_PUPD7_0
#define GPIO_PUPD_PUPDR7_1                                          GPIO_PUPD_PUPD7_1
#define GPIO_PUPD_PUPDR8                                            GPIO_PUPD_PUPD8
#define GPIO_PUPD_PUPDR8_0                                          GPIO_PUPD_PUPD8_0
#define GPIO_PUPD_PUPDR8_1                                          GPIO_PUPD_PUPD8_1
#define GPIO_PUPD_PUPDR9                                            GPIO_PUPD_PUPD9
#define GPIO_PUPD_PUPDR9_0                                          GPIO_PUPD_PUPD9_0
#define GPIO_PUPD_PUPDR9_1                                          GPIO_PUPD_PUPD9_1
#define GPIO_PUPD_PUPDR10                                           GPIO_PUPD_PUPD10
#define GPIO_PUPD_PUPDR10_0                                         GPIO_PUPD_PUPD10_0
#define GPIO_PUPD_PUPDR10_1                                         GPIO_PUPD_PUPD10_1
#define GPIO_PUPD_PUPDR11                                           GPIO_PUPD_PUPD11
#define GPIO_PUPD_PUPDR11_0                                         GPIO_PUPD_PUPD11_0
#define GPIO_PUPD_PUPDR11_1                                         GPIO_PUPD_PUPD11_1
#define GPIO_PUPD_PUPDR12                                           GPIO_PUPD_PUPD12
#define GPIO_PUPD_PUPDR12_0                                         GPIO_PUPD_PUPD12_0
#define GPIO_PUPD_PUPDR12_1                                         GPIO_PUPD_PUPD12_1
#define GPIO_PUPD_PUPDR13                                           GPIO_PUPD_PUPD13
#define GPIO_PUPD_PUPDR13_0                                         GPIO_PUPD_PUPD13_0
#define GPIO_PUPD_PUPDR13_1                                         GPIO_PUPD_PUPD13_1
#define GPIO_PUPD_PUPDR14                                           GPIO_PUPD_PUPD14
#define GPIO_PUPD_PUPDR14_0                                         GPIO_PUPD_PUPD14_0
#define GPIO_PUPD_PUPDR14_1                                         GPIO_PUPD_PUPD14_1
#define GPIO_PUPD_PUPDR15                                           GPIO_PUPD_PUPD15
#define GPIO_PUPD_PUPDR15_0                                         GPIO_PUPD_PUPD15_0
#define GPIO_PUPD_PUPDR15_1                                         GPIO_PUPD_PUPD15_1

/******************  Bits definition for GPIO_IDATA register  *******************/
#define GPIO_IDATA_IDATA0_Pos                                       (0U)
#define GPIO_IDATA_IDATA0_Msk                                       (0x1UL << GPIO_IDATA_IDATA0_Pos)                               /*!< 0x00000001 */
#define GPIO_IDATA_IDATA0                                           GPIO_IDATA_IDATA0_Msk
#define GPIO_IDATA_IDATA1_Pos                                       (1U)
#define GPIO_IDATA_IDATA1_Msk                                       (0x1UL << GPIO_IDATA_IDATA1_Pos)                               /*!< 0x00000002 */
#define GPIO_IDATA_IDATA1                                           GPIO_IDATA_IDATA1_Msk
#define GPIO_IDATA_IDATA2_Pos                                       (2U)
#define GPIO_IDATA_IDATA2_Msk                                       (0x1UL << GPIO_IDATA_IDATA2_Pos)                               /*!< 0x00000004 */
#define GPIO_IDATA_IDATA2                                           GPIO_IDATA_IDATA2_Msk
#define GPIO_IDATA_IDATA3_Pos                                       (3U)
#define GPIO_IDATA_IDATA3_Msk                                       (0x1UL << GPIO_IDATA_IDATA3_Pos)                               /*!< 0x00000008 */
#define GPIO_IDATA_IDATA3                                           GPIO_IDATA_IDATA3_Msk
#define GPIO_IDATA_IDATA4_Pos                                       (4U)
#define GPIO_IDATA_IDATA4_Msk                                       (0x1UL << GPIO_IDATA_IDATA4_Pos)                               /*!< 0x00000010 */
#define GPIO_IDATA_IDATA4                                           GPIO_IDATA_IDATA4_Msk
#define GPIO_IDATA_IDATA5_Pos                                       (5U)
#define GPIO_IDATA_IDATA5_Msk                                       (0x1UL << GPIO_IDATA_IDATA5_Pos)                               /*!< 0x00000020 */
#define GPIO_IDATA_IDATA5                                           GPIO_IDATA_IDATA5_Msk
#define GPIO_IDATA_IDATA6_Pos                                       (6U)
#define GPIO_IDATA_IDATA6_Msk                                       (0x1UL << GPIO_IDATA_IDATA6_Pos)                               /*!< 0x00000040 */
#define GPIO_IDATA_IDATA6                                           GPIO_IDATA_IDATA6_Msk
#define GPIO_IDATA_IDATA7_Pos                                       (7U)
#define GPIO_IDATA_IDATA7_Msk                                       (0x1UL << GPIO_IDATA_IDATA7_Pos)                               /*!< 0x00000080 */
#define GPIO_IDATA_IDATA7                                           GPIO_IDATA_IDATA7_Msk
#define GPIO_IDATA_IDATA8_Pos                                       (8U)
#define GPIO_IDATA_IDATA8_Msk                                       (0x1UL << GPIO_IDATA_IDATA8_Pos)                               /*!< 0x00000100 */
#define GPIO_IDATA_IDATA8                                           GPIO_IDATA_IDATA8_Msk
#define GPIO_IDATA_IDATA9_Pos                                       (9U)
#define GPIO_IDATA_IDATA9_Msk                                       (0x1UL << GPIO_IDATA_IDATA9_Pos)                               /*!< 0x00000200 */
#define GPIO_IDATA_IDATA9                                           GPIO_IDATA_IDATA9_Msk
#define GPIO_IDATA_IDATA10_Pos                                      (10U)
#define GPIO_IDATA_IDATA10_Msk                                      (0x1UL << GPIO_IDATA_IDATA10_Pos)                              /*!< 0x00000400 */
#define GPIO_IDATA_IDATA10                                          GPIO_IDATA_IDATA10_Msk
#define GPIO_IDATA_IDATA11_Pos                                      (11U)
#define GPIO_IDATA_IDATA11_Msk                                      (0x1UL << GPIO_IDATA_IDATA11_Pos)                              /*!< 0x00000800 */
#define GPIO_IDATA_IDATA11                                          GPIO_IDATA_IDATA11_Msk
#define GPIO_IDATA_IDATA12_Pos                                      (12U)
#define GPIO_IDATA_IDATA12_Msk                                      (0x1UL << GPIO_IDATA_IDATA12_Pos)                              /*!< 0x00001000 */
#define GPIO_IDATA_IDATA12                                          GPIO_IDATA_IDATA12_Msk
#define GPIO_IDATA_IDATA13_Pos                                      (13U)
#define GPIO_IDATA_IDATA13_Msk                                      (0x1UL << GPIO_IDATA_IDATA13_Pos)                              /*!< 0x00002000 */
#define GPIO_IDATA_IDATA13                                          GPIO_IDATA_IDATA13_Msk
#define GPIO_IDATA_IDATA14_Pos                                      (14U)
#define GPIO_IDATA_IDATA14_Msk                                      (0x1UL << GPIO_IDATA_IDATA14_Pos)                              /*!< 0x00004000 */
#define GPIO_IDATA_IDATA14                                          GPIO_IDATA_IDATA14_Msk
#define GPIO_IDATA_IDATA15_Pos                                      (15U)
#define GPIO_IDATA_IDATA15_Msk                                      (0x1UL << GPIO_IDATA_IDATA15_Pos)                              /*!< 0x00008000 */
#define GPIO_IDATA_IDATA15                                          GPIO_IDATA_IDATA15_Msk

/* Legacy defines */
#define GPIO_IDATA_IDR_0                                            GPIO_IDATA_IDATA0
#define GPIO_IDATA_IDR_1                                            GPIO_IDATA_IDATA1
#define GPIO_IDATA_IDR_2                                            GPIO_IDATA_IDATA2
#define GPIO_IDATA_IDR_3                                            GPIO_IDATA_IDATA3
#define GPIO_IDATA_IDR_4                                            GPIO_IDATA_IDATA4
#define GPIO_IDATA_IDR_5                                            GPIO_IDATA_IDATA5
#define GPIO_IDATA_IDR_6                                            GPIO_IDATA_IDATA6
#define GPIO_IDATA_IDR_7                                            GPIO_IDATA_IDATA7
#define GPIO_IDATA_IDR_8                                            GPIO_IDATA_IDATA8
#define GPIO_IDATA_IDR_9                                            GPIO_IDATA_IDATA9
#define GPIO_IDATA_IDR_10                                           GPIO_IDATA_IDATA10
#define GPIO_IDATA_IDR_11                                           GPIO_IDATA_IDATA11
#define GPIO_IDATA_IDR_12                                           GPIO_IDATA_IDATA12
#define GPIO_IDATA_IDR_13                                           GPIO_IDATA_IDATA13
#define GPIO_IDATA_IDR_14                                           GPIO_IDATA_IDATA14
#define GPIO_IDATA_IDR_15                                           GPIO_IDATA_IDATA15

/******************  Bits definition for GPIO_ODATA register  *******************/
#define GPIO_ODATA_ODATA0_Pos                                       (0U)
#define GPIO_ODATA_ODATA0_Msk                                       (0x1UL << GPIO_ODATA_ODATA0_Pos)                               /*!< 0x00000001 */
#define GPIO_ODATA_ODATA0                                           GPIO_ODATA_ODATA0_Msk
#define GPIO_ODATA_ODATA1_Pos                                       (1U)
#define GPIO_ODATA_ODATA1_Msk                                       (0x1UL << GPIO_ODATA_ODATA1_Pos)                               /*!< 0x00000002 */
#define GPIO_ODATA_ODATA1                                           GPIO_ODATA_ODATA1_Msk
#define GPIO_ODATA_ODATA2_Pos                                       (2U)
#define GPIO_ODATA_ODATA2_Msk                                       (0x1UL << GPIO_ODATA_ODATA2_Pos)                               /*!< 0x00000004 */
#define GPIO_ODATA_ODATA2                                           GPIO_ODATA_ODATA2_Msk
#define GPIO_ODATA_ODATA3_Pos                                       (3U)
#define GPIO_ODATA_ODATA3_Msk                                       (0x1UL << GPIO_ODATA_ODATA3_Pos)                               /*!< 0x00000008 */
#define GPIO_ODATA_ODATA3                                           GPIO_ODATA_ODATA3_Msk
#define GPIO_ODATA_ODATA4_Pos                                       (4U)
#define GPIO_ODATA_ODATA4_Msk                                       (0x1UL << GPIO_ODATA_ODATA4_Pos)                               /*!< 0x00000010 */
#define GPIO_ODATA_ODATA4                                           GPIO_ODATA_ODATA4_Msk
#define GPIO_ODATA_ODATA5_Pos                                       (5U)
#define GPIO_ODATA_ODATA5_Msk                                       (0x1UL << GPIO_ODATA_ODATA5_Pos)                               /*!< 0x00000020 */
#define GPIO_ODATA_ODATA5                                           GPIO_ODATA_ODATA5_Msk
#define GPIO_ODATA_ODATA6_Pos                                       (6U)
#define GPIO_ODATA_ODATA6_Msk                                       (0x1UL << GPIO_ODATA_ODATA6_Pos)                               /*!< 0x00000040 */
#define GPIO_ODATA_ODATA6                                           GPIO_ODATA_ODATA6_Msk
#define GPIO_ODATA_ODATA7_Pos                                       (7U)
#define GPIO_ODATA_ODATA7_Msk                                       (0x1UL << GPIO_ODATA_ODATA7_Pos)                               /*!< 0x00000080 */
#define GPIO_ODATA_ODATA7                                           GPIO_ODATA_ODATA7_Msk
#define GPIO_ODATA_ODATA8_Pos                                       (8U)
#define GPIO_ODATA_ODATA8_Msk                                       (0x1UL << GPIO_ODATA_ODATA8_Pos)                               /*!< 0x00000100 */
#define GPIO_ODATA_ODATA8                                           GPIO_ODATA_ODATA8_Msk
#define GPIO_ODATA_ODATA9_Pos                                       (9U)
#define GPIO_ODATA_ODATA9_Msk                                       (0x1UL << GPIO_ODATA_ODATA9_Pos)                               /*!< 0x00000200 */
#define GPIO_ODATA_ODATA9                                           GPIO_ODATA_ODATA9_Msk
#define GPIO_ODATA_ODATA10_Pos                                      (10U)
#define GPIO_ODATA_ODATA10_Msk                                      (0x1UL << GPIO_ODATA_ODATA10_Pos)                              /*!< 0x00000400 */
#define GPIO_ODATA_ODATA10                                          GPIO_ODATA_ODATA10_Msk
#define GPIO_ODATA_ODATA11_Pos                                      (11U)
#define GPIO_ODATA_ODATA11_Msk                                      (0x1UL << GPIO_ODATA_ODATA11_Pos)                              /*!< 0x00000800 */
#define GPIO_ODATA_ODATA11                                          GPIO_ODATA_ODATA11_Msk
#define GPIO_ODATA_ODATA12_Pos                                      (12U)
#define GPIO_ODATA_ODATA12_Msk                                      (0x1UL << GPIO_ODATA_ODATA12_Pos)                              /*!< 0x00001000 */
#define GPIO_ODATA_ODATA12                                          GPIO_ODATA_ODATA12_Msk
#define GPIO_ODATA_ODATA13_Pos                                      (13U)
#define GPIO_ODATA_ODATA13_Msk                                      (0x1UL << GPIO_ODATA_ODATA13_Pos)                              /*!< 0x00002000 */
#define GPIO_ODATA_ODATA13                                          GPIO_ODATA_ODATA13_Msk
#define GPIO_ODATA_ODATA14_Pos                                      (14U)
#define GPIO_ODATA_ODATA14_Msk                                      (0x1UL << GPIO_ODATA_ODATA14_Pos)                              /*!< 0x00004000 */
#define GPIO_ODATA_ODATA14                                          GPIO_ODATA_ODATA14_Msk
#define GPIO_ODATA_ODATA15_Pos                                      (15U)
#define GPIO_ODATA_ODATA15_Msk                                      (0x1UL << GPIO_ODATA_ODATA15_Pos)                              /*!< 0x00008000 */
#define GPIO_ODATA_ODATA15                                          GPIO_ODATA_ODATA15_Msk
/* Legacy defines */
#define GPIO_ODATA_ODR_0                                            GPIO_ODATA_ODATA0
#define GPIO_ODATA_ODR_1                                            GPIO_ODATA_ODATA1
#define GPIO_ODATA_ODR_2                                            GPIO_ODATA_ODATA2
#define GPIO_ODATA_ODR_3                                            GPIO_ODATA_ODATA3
#define GPIO_ODATA_ODR_4                                            GPIO_ODATA_ODATA4
#define GPIO_ODATA_ODR_5                                            GPIO_ODATA_ODATA5
#define GPIO_ODATA_ODR_6                                            GPIO_ODATA_ODATA6
#define GPIO_ODATA_ODR_7                                            GPIO_ODATA_ODATA7
#define GPIO_ODATA_ODR_8                                            GPIO_ODATA_ODATA8
#define GPIO_ODATA_ODR_9                                            GPIO_ODATA_ODATA9
#define GPIO_ODATA_ODR_10                                           GPIO_ODATA_ODATA10
#define GPIO_ODATA_ODR_11                                           GPIO_ODATA_ODATA11
#define GPIO_ODATA_ODR_12                                           GPIO_ODATA_ODATA12
#define GPIO_ODATA_ODR_13                                           GPIO_ODATA_ODATA13
#define GPIO_ODATA_ODR_14                                           GPIO_ODATA_ODATA14
#define GPIO_ODATA_ODR_15                                           GPIO_ODATA_ODATA15

/******************  Bits definition for GPIO_BSC register  ******************/
#define GPIO_BSC_BS0_Pos                                            (0U)
#define GPIO_BSC_BS0_Msk                                            (0x1UL << GPIO_BSC_BS0_Pos)                                    /*!< 0x00000001 */
#define GPIO_BSC_BS0                                                GPIO_BSC_BS0_Msk
#define GPIO_BSC_BS1_Pos                                            (1U)
#define GPIO_BSC_BS1_Msk                                            (0x1UL << GPIO_BSC_BS1_Pos)                                    /*!< 0x00000002 */
#define GPIO_BSC_BS1                                                GPIO_BSC_BS1_Msk
#define GPIO_BSC_BS2_Pos                                            (2U)
#define GPIO_BSC_BS2_Msk                                            (0x1UL << GPIO_BSC_BS2_Pos)                                    /*!< 0x00000004 */
#define GPIO_BSC_BS2                                                GPIO_BSC_BS2_Msk
#define GPIO_BSC_BS3_Pos                                            (3U)
#define GPIO_BSC_BS3_Msk                                            (0x1UL << GPIO_BSC_BS3_Pos)                                    /*!< 0x00000008 */
#define GPIO_BSC_BS3                                                GPIO_BSC_BS3_Msk
#define GPIO_BSC_BS4_Pos                                            (4U)
#define GPIO_BSC_BS4_Msk                                            (0x1UL << GPIO_BSC_BS4_Pos)                                    /*!< 0x00000010 */
#define GPIO_BSC_BS4                                                GPIO_BSC_BS4_Msk
#define GPIO_BSC_BS5_Pos                                            (5U)
#define GPIO_BSC_BS5_Msk                                            (0x1UL << GPIO_BSC_BS5_Pos)                                    /*!< 0x00000020 */
#define GPIO_BSC_BS5                                                GPIO_BSC_BS5_Msk
#define GPIO_BSC_BS6_Pos                                            (6U)
#define GPIO_BSC_BS6_Msk                                            (0x1UL << GPIO_BSC_BS6_Pos)                                    /*!< 0x00000040 */
#define GPIO_BSC_BS6                                                GPIO_BSC_BS6_Msk
#define GPIO_BSC_BS7_Pos                                            (7U)
#define GPIO_BSC_BS7_Msk                                            (0x1UL << GPIO_BSC_BS7_Pos)                                    /*!< 0x00000080 */
#define GPIO_BSC_BS7                                                GPIO_BSC_BS7_Msk
#define GPIO_BSC_BS8_Pos                                            (8U)
#define GPIO_BSC_BS8_Msk                                            (0x1UL << GPIO_BSC_BS8_Pos)                                    /*!< 0x00000100 */
#define GPIO_BSC_BS8                                                GPIO_BSC_BS8_Msk
#define GPIO_BSC_BS9_Pos                                            (9U)
#define GPIO_BSC_BS9_Msk                                            (0x1UL << GPIO_BSC_BS9_Pos)                                    /*!< 0x00000200 */
#define GPIO_BSC_BS9                                                GPIO_BSC_BS9_Msk
#define GPIO_BSC_BS10_Pos                                           (10U)
#define GPIO_BSC_BS10_Msk                                           (0x1UL << GPIO_BSC_BS10_Pos)                                   /*!< 0x00000400 */
#define GPIO_BSC_BS10                                               GPIO_BSC_BS10_Msk
#define GPIO_BSC_BS11_Pos                                           (11U)
#define GPIO_BSC_BS11_Msk                                           (0x1UL << GPIO_BSC_BS11_Pos)                                   /*!< 0x00000800 */
#define GPIO_BSC_BS11                                               GPIO_BSC_BS11_Msk
#define GPIO_BSC_BS12_Pos                                           (12U)
#define GPIO_BSC_BS12_Msk                                           (0x1UL << GPIO_BSC_BS12_Pos)                                   /*!< 0x00001000 */
#define GPIO_BSC_BS12                                               GPIO_BSC_BS12_Msk
#define GPIO_BSC_BS13_Pos                                           (13U)
#define GPIO_BSC_BS13_Msk                                           (0x1UL << GPIO_BSC_BS13_Pos)                                   /*!< 0x00002000 */
#define GPIO_BSC_BS13                                               GPIO_BSC_BS13_Msk
#define GPIO_BSC_BS14_Pos                                           (14U)
#define GPIO_BSC_BS14_Msk                                           (0x1UL << GPIO_BSC_BS14_Pos)                                   /*!< 0x00004000 */
#define GPIO_BSC_BS14                                               GPIO_BSC_BS14_Msk
#define GPIO_BSC_BS15_Pos                                           (15U)
#define GPIO_BSC_BS15_Msk                                           (0x1UL << GPIO_BSC_BS15_Pos)                                   /*!< 0x00008000 */
#define GPIO_BSC_BS15                                               GPIO_BSC_BS15_Msk
#define GPIO_BSC_BC0_Pos                                            (16U)
#define GPIO_BSC_BC0_Msk                                            (0x1UL << GPIO_BSC_BC0_Pos)                                    /*!< 0x00010000 */
#define GPIO_BSC_BC0                                                GPIO_BSC_BC0_Msk
#define GPIO_BSC_BC1_Pos                                            (17U)
#define GPIO_BSC_BC1_Msk                                            (0x1UL << GPIO_BSC_BC1_Pos)                                    /*!< 0x00020000 */
#define GPIO_BSC_BC1                                                GPIO_BSC_BC1_Msk
#define GPIO_BSC_BC2_Pos                                            (18U)
#define GPIO_BSC_BC2_Msk                                            (0x1UL << GPIO_BSC_BC2_Pos)                                    /*!< 0x00040000 */
#define GPIO_BSC_BC2                                                GPIO_BSC_BC2_Msk
#define GPIO_BSC_BC3_Pos                                            (19U)
#define GPIO_BSC_BC3_Msk                                            (0x1UL << GPIO_BSC_BC3_Pos)                                    /*!< 0x00080000 */
#define GPIO_BSC_BC3                                                GPIO_BSC_BC3_Msk
#define GPIO_BSC_BC4_Pos                                            (20U)
#define GPIO_BSC_BC4_Msk                                            (0x1UL << GPIO_BSC_BC4_Pos)                                    /*!< 0x00100000 */
#define GPIO_BSC_BC4                                                GPIO_BSC_BC4_Msk
#define GPIO_BSC_BC5_Pos                                            (21U)
#define GPIO_BSC_BC5_Msk                                            (0x1UL << GPIO_BSC_BC5_Pos)                                    /*!< 0x00200000 */
#define GPIO_BSC_BC5                                                GPIO_BSC_BC5_Msk
#define GPIO_BSC_BC6_Pos                                            (22U)
#define GPIO_BSC_BC6_Msk                                            (0x1UL << GPIO_BSC_BC6_Pos)                                    /*!< 0x00400000 */
#define GPIO_BSC_BC6                                                GPIO_BSC_BC6_Msk
#define GPIO_BSC_BC7_Pos                                            (23U)
#define GPIO_BSC_BC7_Msk                                            (0x1UL << GPIO_BSC_BC7_Pos)                                    /*!< 0x00800000 */
#define GPIO_BSC_BC7                                                GPIO_BSC_BC7_Msk
#define GPIO_BSC_BC8_Pos                                            (24U)
#define GPIO_BSC_BC8_Msk                                            (0x1UL << GPIO_BSC_BC8_Pos)                                    /*!< 0x01000000 */
#define GPIO_BSC_BC8                                                GPIO_BSC_BC8_Msk
#define GPIO_BSC_BC9_Pos                                            (25U)
#define GPIO_BSC_BC9_Msk                                            (0x1UL << GPIO_BSC_BC9_Pos)                                    /*!< 0x02000000 */
#define GPIO_BSC_BC9                                                GPIO_BSC_BC9_Msk
#define GPIO_BSC_BC10_Pos                                           (26U)
#define GPIO_BSC_BC10_Msk                                           (0x1UL << GPIO_BSC_BC10_Pos)                                   /*!< 0x04000000 */
#define GPIO_BSC_BC10                                               GPIO_BSC_BC10_Msk
#define GPIO_BSC_BC11_Pos                                           (27U)
#define GPIO_BSC_BC11_Msk                                           (0x1UL << GPIO_BSC_BC11_Pos)                                   /*!< 0x08000000 */
#define GPIO_BSC_BC11                                               GPIO_BSC_BC11_Msk
#define GPIO_BSC_BC12_Pos                                           (28U)
#define GPIO_BSC_BC12_Msk                                           (0x1UL << GPIO_BSC_BC12_Pos)                                   /*!< 0x10000000 */
#define GPIO_BSC_BC12                                               GPIO_BSC_BC12_Msk
#define GPIO_BSC_BC13_Pos                                           (29U)
#define GPIO_BSC_BC13_Msk                                           (0x1UL << GPIO_BSC_BC13_Pos)                                   /*!< 0x20000000 */
#define GPIO_BSC_BC13                                               GPIO_BSC_BC13_Msk
#define GPIO_BSC_BC14_Pos                                           (30U)
#define GPIO_BSC_BC14_Msk                                           (0x1UL << GPIO_BSC_BC14_Pos)                                   /*!< 0x40000000 */
#define GPIO_BSC_BC14                                               GPIO_BSC_BC14_Msk
#define GPIO_BSC_BC15_Pos                                           (31U)
#define GPIO_BSC_BC15_Msk                                           (0x1UL << GPIO_BSC_BC15_Pos)                                   /*!< 0x80000000 */
#define GPIO_BSC_BC15                                               GPIO_BSC_BC15_Msk

/* Legacy defines */
#define GPIO_BSC_BS_0                                               GPIO_BSC_BS0
#define GPIO_BSC_BS_1                                               GPIO_BSC_BS1
#define GPIO_BSC_BS_2                                               GPIO_BSC_BS2
#define GPIO_BSC_BS_3                                               GPIO_BSC_BS3
#define GPIO_BSC_BS_4                                               GPIO_BSC_BS4
#define GPIO_BSC_BS_5                                               GPIO_BSC_BS5
#define GPIO_BSC_BS_6                                               GPIO_BSC_BS6
#define GPIO_BSC_BS_7                                               GPIO_BSC_BS7
#define GPIO_BSC_BS_8                                               GPIO_BSC_BS8
#define GPIO_BSC_BS_9                                               GPIO_BSC_BS9
#define GPIO_BSC_BS_10                                              GPIO_BSC_BS10
#define GPIO_BSC_BS_11                                              GPIO_BSC_BS11
#define GPIO_BSC_BS_12                                              GPIO_BSC_BS12
#define GPIO_BSC_BS_13                                              GPIO_BSC_BS13
#define GPIO_BSC_BS_14                                              GPIO_BSC_BS14
#define GPIO_BSC_BS_15                                              GPIO_BSC_BS15
#define GPIO_BSC_BR_0                                               GPIO_BSC_BC0
#define GPIO_BSC_BR_1                                               GPIO_BSC_BC1
#define GPIO_BSC_BR_2                                               GPIO_BSC_BC2
#define GPIO_BSC_BR_3                                               GPIO_BSC_BC3
#define GPIO_BSC_BR_4                                               GPIO_BSC_BC4
#define GPIO_BSC_BR_5                                               GPIO_BSC_BC5
#define GPIO_BSC_BR_6                                               GPIO_BSC_BC6
#define GPIO_BSC_BR_7                                               GPIO_BSC_BC7
#define GPIO_BSC_BR_8                                               GPIO_BSC_BC8
#define GPIO_BSC_BR_9                                               GPIO_BSC_BC9
#define GPIO_BSC_BR_10                                              GPIO_BSC_BC10
#define GPIO_BSC_BR_11                                              GPIO_BSC_BC11
#define GPIO_BSC_BR_12                                              GPIO_BSC_BC12
#define GPIO_BSC_BR_13                                              GPIO_BSC_BC13
#define GPIO_BSC_BR_14                                              GPIO_BSC_BC14
#define GPIO_BSC_BR_15                                              GPIO_BSC_BC15
#define GPIO_BRR_BR0                                                GPIO_BSC_BC0
#define GPIO_BRR_BR0_Pos                                            GPIO_BSC_BC0_Pos
#define GPIO_BRR_BR0_Msk                                            GPIO_BSC_BC0_Msk
#define GPIO_BRR_BR1                                                GPIO_BSC_BC1
#define GPIO_BRR_BR1_Pos                                            GPIO_BSC_BC1_Pos
#define GPIO_BRR_BR1_Msk                                            GPIO_BSC_BC1_Msk
#define GPIO_BRR_BR2                                                GPIO_BSC_BC2
#define GPIO_BRR_BR2_Pos                                            GPIO_BSC_BC2_Pos
#define GPIO_BRR_BR2_Msk                                            GPIO_BSC_BC2_Msk
#define GPIO_BRR_BR3                                                GPIO_BSC_BC3
#define GPIO_BRR_BR3_Pos                                            GPIO_BSC_BC3_Pos
#define GPIO_BRR_BR3_Msk                                            GPIO_BSC_BC3_Msk
#define GPIO_BRR_BR4                                                GPIO_BSC_BC4
#define GPIO_BRR_BR4_Pos                                            GPIO_BSC_BC4_Pos
#define GPIO_BRR_BR4_Msk                                            GPIO_BSC_BC4_Msk
#define GPIO_BRR_BR5                                                GPIO_BSC_BC5
#define GPIO_BRR_BR5_Pos                                            GPIO_BSC_BC5_Pos
#define GPIO_BRR_BR5_Msk                                            GPIO_BSC_BC5_Msk
#define GPIO_BRR_BR6                                                GPIO_BSC_BC6
#define GPIO_BRR_BR6_Pos                                            GPIO_BSC_BC6_Pos
#define GPIO_BRR_BR6_Msk                                            GPIO_BSC_BC6_Msk
#define GPIO_BRR_BR7                                                GPIO_BSC_BC7
#define GPIO_BRR_BR7_Pos                                            GPIO_BSC_BC7_Pos
#define GPIO_BRR_BR7_Msk                                            GPIO_BSC_BC7_Msk
#define GPIO_BRR_BR8                                                GPIO_BSC_BC8
#define GPIO_BRR_BR8_Pos                                            GPIO_BSC_BC8_Pos
#define GPIO_BRR_BR8_Msk                                            GPIO_BSC_BC8_Msk
#define GPIO_BRR_BR9                                                GPIO_BSC_BC9
#define GPIO_BRR_BR9_Pos                                            GPIO_BSC_BC9_Pos
#define GPIO_BRR_BR9_Msk                                            GPIO_BSC_BC9_Msk
#define GPIO_BRR_BR10                                               GPIO_BSC_BC10
#define GPIO_BRR_BR10_Pos                                           GPIO_BSC_BC10_Pos
#define GPIO_BRR_BR10_Msk                                           GPIO_BSC_BC10_Msk
#define GPIO_BRR_BR11                                               GPIO_BSC_BC11
#define GPIO_BRR_BR11_Pos                                           GPIO_BSC_BC11_Pos
#define GPIO_BRR_BR11_Msk                                           GPIO_BSC_BC11_Msk
#define GPIO_BRR_BR12                                               GPIO_BSC_BC12
#define GPIO_BRR_BR12_Pos                                           GPIO_BSC_BC12_Pos
#define GPIO_BRR_BR12_Msk                                           GPIO_BSC_BC12_Msk
#define GPIO_BRR_BR13                                               GPIO_BSC_BC13
#define GPIO_BRR_BR13_Pos                                           GPIO_BSC_BC13_Pos
#define GPIO_BRR_BR13_Msk                                           GPIO_BSC_BC13_Msk
#define GPIO_BRR_BR14                                               GPIO_BSC_BC14
#define GPIO_BRR_BR14_Pos                                           GPIO_BSC_BC14_Pos
#define GPIO_BRR_BR14_Msk                                           GPIO_BSC_BC14_Msk
#define GPIO_BRR_BR15                                               GPIO_BSC_BC15
#define GPIO_BRR_BR15_Pos                                           GPIO_BSC_BC15_Pos
#define GPIO_BRR_BR15_Msk                                           GPIO_BSC_BC15_Msk
/****************** Bit definition for GPIO_LOCK register *********************/
#define GPIO_LOCK_LOCK0_Pos                                         (0U)
#define GPIO_LOCK_LOCK0_Msk                                         (0x1UL << GPIO_LOCK_LOCK0_Pos)                                 /*!< 0x00000001 */
#define GPIO_LOCK_LOCK0                                             GPIO_LOCK_LOCK0_Msk
#define GPIO_LOCK_LOCK1_Pos                                         (1U)
#define GPIO_LOCK_LOCK1_Msk                                         (0x1UL << GPIO_LOCK_LOCK1_Pos)                                 /*!< 0x00000002 */
#define GPIO_LOCK_LOCK1                                             GPIO_LOCK_LOCK1_Msk
#define GPIO_LOCK_LOCK2_Pos                                         (2U)
#define GPIO_LOCK_LOCK2_Msk                                         (0x1UL << GPIO_LOCK_LOCK2_Pos)                                 /*!< 0x00000004 */
#define GPIO_LOCK_LOCK2                                             GPIO_LOCK_LOCK2_Msk
#define GPIO_LOCK_LOCK3_Pos                                         (3U)
#define GPIO_LOCK_LOCK3_Msk                                         (0x1UL << GPIO_LOCK_LOCK3_Pos)                                 /*!< 0x00000008 */
#define GPIO_LOCK_LOCK3                                             GPIO_LOCK_LOCK3_Msk
#define GPIO_LOCK_LOCK4_Pos                                         (4U)
#define GPIO_LOCK_LOCK4_Msk                                         (0x1UL << GPIO_LOCK_LOCK4_Pos)                                 /*!< 0x00000010 */
#define GPIO_LOCK_LOCK4                                             GPIO_LOCK_LOCK4_Msk
#define GPIO_LOCK_LOCK5_Pos                                         (5U)
#define GPIO_LOCK_LOCK5_Msk                                         (0x1UL << GPIO_LOCK_LOCK5_Pos)                                 /*!< 0x00000020 */
#define GPIO_LOCK_LOCK5                                             GPIO_LOCK_LOCK5_Msk
#define GPIO_LOCK_LOCK6_Pos                                         (6U)
#define GPIO_LOCK_LOCK6_Msk                                         (0x1UL << GPIO_LOCK_LOCK6_Pos)                                 /*!< 0x00000040 */
#define GPIO_LOCK_LOCK6                                             GPIO_LOCK_LOCK6_Msk
#define GPIO_LOCK_LOCK7_Pos                                         (7U)
#define GPIO_LOCK_LOCK7_Msk                                         (0x1UL << GPIO_LOCK_LOCK7_Pos)                                 /*!< 0x00000080 */
#define GPIO_LOCK_LOCK7                                             GPIO_LOCK_LOCK7_Msk
#define GPIO_LOCK_LOCK8_Pos                                         (8U)
#define GPIO_LOCK_LOCK8_Msk                                         (0x1UL << GPIO_LOCK_LOCK8_Pos)                                 /*!< 0x00000100 */
#define GPIO_LOCK_LOCK8                                             GPIO_LOCK_LOCK8_Msk
#define GPIO_LOCK_LOCK9_Pos                                         (9U)
#define GPIO_LOCK_LOCK9_Msk                                         (0x1UL << GPIO_LOCK_LOCK9_Pos)                                 /*!< 0x00000200 */
#define GPIO_LOCK_LOCK9                                             GPIO_LOCK_LOCK9_Msk
#define GPIO_LOCK_LOCK10_Pos                                        (10U)
#define GPIO_LOCK_LOCK10_Msk                                        (0x1UL << GPIO_LOCK_LOCK10_Pos)                                /*!< 0x00000400 */
#define GPIO_LOCK_LOCK10                                            GPIO_LOCK_LOCK10_Msk
#define GPIO_LOCK_LOCK11_Pos                                        (11U)
#define GPIO_LOCK_LOCK11_Msk                                        (0x1UL << GPIO_LOCK_LOCK11_Pos)                                /*!< 0x00000800 */
#define GPIO_LOCK_LOCK11                                            GPIO_LOCK_LOCK11_Msk
#define GPIO_LOCK_LOCK12_Pos                                        (12U)
#define GPIO_LOCK_LOCK12_Msk                                        (0x1UL << GPIO_LOCK_LOCK12_Pos)                                /*!< 0x00001000 */
#define GPIO_LOCK_LOCK12                                            GPIO_LOCK_LOCK12_Msk
#define GPIO_LOCK_LOCK13_Pos                                        (13U)
#define GPIO_LOCK_LOCK13_Msk                                        (0x1UL << GPIO_LOCK_LOCK13_Pos)                                /*!< 0x00002000 */
#define GPIO_LOCK_LOCK13                                            GPIO_LOCK_LOCK13_Msk
#define GPIO_LOCK_LOCK14_Pos                                        (14U)
#define GPIO_LOCK_LOCK14_Msk                                        (0x1UL << GPIO_LOCK_LOCK14_Pos)                                /*!< 0x00004000 */
#define GPIO_LOCK_LOCK14                                            GPIO_LOCK_LOCK14_Msk
#define GPIO_LOCK_LOCK15_Pos                                        (15U)
#define GPIO_LOCK_LOCK15_Msk                                        (0x1UL << GPIO_LOCK_LOCK15_Pos)                                /*!< 0x00008000 */
#define GPIO_LOCK_LOCK15                                            GPIO_LOCK_LOCK15_Msk
#define GPIO_LOCK_LOCKKEY_Pos                                       (16U)
#define GPIO_LOCK_LOCKKEY_Msk                                       (0x1UL << GPIO_LOCK_LOCKKEY_Pos)                               /*!< 0x00010000 */
#define GPIO_LOCK_LOCKKEY                                           GPIO_LOCK_LOCKKEY_Msk
/****************** Bit definition for GPIO_ALFL register *********************/
#define GPIO_ALFL_ALFSEL0_Pos                                       (0U)
#define GPIO_ALFL_ALFSEL0_Msk                                       (0xFUL << GPIO_ALFL_ALFSEL0_Pos)                               /*!< 0x0000000F */
#define GPIO_ALFL_ALFSEL0                                           GPIO_ALFL_ALFSEL0_Msk
#define GPIO_ALFL_ALFSEL0_0                                         (0x1UL << GPIO_ALFL_ALFSEL0_Pos)                               /*!< 0x00000001 */
#define GPIO_ALFL_ALFSEL0_1                                         (0x2UL << GPIO_ALFL_ALFSEL0_Pos)                               /*!< 0x00000002 */
#define GPIO_ALFL_ALFSEL0_2                                         (0x4UL << GPIO_ALFL_ALFSEL0_Pos)                               /*!< 0x00000004 */
#define GPIO_ALFL_ALFSEL0_3                                         (0x8UL << GPIO_ALFL_ALFSEL0_Pos)                               /*!< 0x00000008 */
#define GPIO_ALFL_ALFSEL1_Pos                                       (4U)
#define GPIO_ALFL_ALFSEL1_Msk                                       (0xFUL << GPIO_ALFL_ALFSEL1_Pos)                               /*!< 0x000000F0 */
#define GPIO_ALFL_ALFSEL1                                           GPIO_ALFL_ALFSEL1_Msk
#define GPIO_ALFL_ALFSEL1_0                                         (0x1UL << GPIO_ALFL_ALFSEL1_Pos)                               /*!< 0x00000010 */
#define GPIO_ALFL_ALFSEL1_1                                         (0x2UL << GPIO_ALFL_ALFSEL1_Pos)                               /*!< 0x00000020 */
#define GPIO_ALFL_ALFSEL1_2                                         (0x4UL << GPIO_ALFL_ALFSEL1_Pos)                               /*!< 0x00000040 */
#define GPIO_ALFL_ALFSEL1_3                                         (0x8UL << GPIO_ALFL_ALFSEL1_Pos)                               /*!< 0x00000080 */
#define GPIO_ALFL_ALFSEL2_Pos                                       (8U)
#define GPIO_ALFL_ALFSEL2_Msk                                       (0xFUL << GPIO_ALFL_ALFSEL2_Pos)                               /*!< 0x00000F00 */
#define GPIO_ALFL_ALFSEL2                                           GPIO_ALFL_ALFSEL2_Msk
#define GPIO_ALFL_ALFSEL2_0                                         (0x1UL << GPIO_ALFL_ALFSEL2_Pos)                               /*!< 0x00000100 */
#define GPIO_ALFL_ALFSEL2_1                                         (0x2UL << GPIO_ALFL_ALFSEL2_Pos)                               /*!< 0x00000200 */
#define GPIO_ALFL_ALFSEL2_2                                         (0x4UL << GPIO_ALFL_ALFSEL2_Pos)                               /*!< 0x00000400 */
#define GPIO_ALFL_ALFSEL2_3                                         (0x8UL << GPIO_ALFL_ALFSEL2_Pos)                               /*!< 0x00000800 */
#define GPIO_ALFL_ALFSEL3_Pos                                       (12U)
#define GPIO_ALFL_ALFSEL3_Msk                                       (0xFUL << GPIO_ALFL_ALFSEL3_Pos)                               /*!< 0x0000F000 */
#define GPIO_ALFL_ALFSEL3                                           GPIO_ALFL_ALFSEL3_Msk
#define GPIO_ALFL_ALFSEL3_0                                         (0x1UL << GPIO_ALFL_ALFSEL3_Pos)                               /*!< 0x00001000 */
#define GPIO_ALFL_ALFSEL3_1                                         (0x2UL << GPIO_ALFL_ALFSEL3_Pos)                               /*!< 0x00002000 */
#define GPIO_ALFL_ALFSEL3_2                                         (0x4UL << GPIO_ALFL_ALFSEL3_Pos)                               /*!< 0x00004000 */
#define GPIO_ALFL_ALFSEL3_3                                         (0x8UL << GPIO_ALFL_ALFSEL3_Pos)                               /*!< 0x00008000 */
#define GPIO_ALFL_ALFSEL4_Pos                                       (16U)
#define GPIO_ALFL_ALFSEL4_Msk                                       (0xFUL << GPIO_ALFL_ALFSEL4_Pos)                               /*!< 0x000F0000 */
#define GPIO_ALFL_ALFSEL4                                           GPIO_ALFL_ALFSEL4_Msk
#define GPIO_ALFL_ALFSEL4_0                                         (0x1UL << GPIO_ALFL_ALFSEL4_Pos)                               /*!< 0x00010000 */
#define GPIO_ALFL_ALFSEL4_1                                         (0x2UL << GPIO_ALFL_ALFSEL4_Pos)                               /*!< 0x00020000 */
#define GPIO_ALFL_ALFSEL4_2                                         (0x4UL << GPIO_ALFL_ALFSEL4_Pos)                               /*!< 0x00040000 */
#define GPIO_ALFL_ALFSEL4_3                                         (0x8UL << GPIO_ALFL_ALFSEL4_Pos)                               /*!< 0x00080000 */
#define GPIO_ALFL_ALFSEL5_Pos                                       (20U)
#define GPIO_ALFL_ALFSEL5_Msk                                       (0xFUL << GPIO_ALFL_ALFSEL5_Pos)                               /*!< 0x00F00000 */
#define GPIO_ALFL_ALFSEL5                                           GPIO_ALFL_ALFSEL5_Msk
#define GPIO_ALFL_ALFSEL5_0                                         (0x1UL << GPIO_ALFL_ALFSEL5_Pos)                               /*!< 0x00100000 */
#define GPIO_ALFL_ALFSEL5_1                                         (0x2UL << GPIO_ALFL_ALFSEL5_Pos)                               /*!< 0x00200000 */
#define GPIO_ALFL_ALFSEL5_2                                         (0x4UL << GPIO_ALFL_ALFSEL5_Pos)                               /*!< 0x00400000 */
#define GPIO_ALFL_ALFSEL5_3                                         (0x8UL << GPIO_ALFL_ALFSEL5_Pos)                               /*!< 0x00800000 */
#define GPIO_ALFL_ALFSEL6_Pos                                       (24U)
#define GPIO_ALFL_ALFSEL6_Msk                                       (0xFUL << GPIO_ALFL_ALFSEL6_Pos)                               /*!< 0x0F000000 */
#define GPIO_ALFL_ALFSEL6                                           GPIO_ALFL_ALFSEL6_Msk
#define GPIO_ALFL_ALFSEL6_0                                         (0x1UL << GPIO_ALFL_ALFSEL6_Pos)                               /*!< 0x01000000 */
#define GPIO_ALFL_ALFSEL6_1                                         (0x2UL << GPIO_ALFL_ALFSEL6_Pos)                               /*!< 0x02000000 */
#define GPIO_ALFL_ALFSEL6_2                                         (0x4UL << GPIO_ALFL_ALFSEL6_Pos)                               /*!< 0x04000000 */
#define GPIO_ALFL_ALFSEL6_3                                         (0x8UL << GPIO_ALFL_ALFSEL6_Pos)                               /*!< 0x08000000 */
#define GPIO_ALFL_ALFSEL7_Pos                                       (28U)
#define GPIO_ALFL_ALFSEL7_Msk                                       (0xFUL << GPIO_ALFL_ALFSEL7_Pos)                               /*!< 0xF0000000 */
#define GPIO_ALFL_ALFSEL7                                           GPIO_ALFL_ALFSEL7_Msk
#define GPIO_ALFL_ALFSEL7_0                                         (0x1UL << GPIO_ALFL_ALFSEL7_Pos)                               /*!< 0x10000000 */
#define GPIO_ALFL_ALFSEL7_1                                         (0x2UL << GPIO_ALFL_ALFSEL7_Pos)                               /*!< 0x20000000 */
#define GPIO_ALFL_ALFSEL7_2                                         (0x4UL << GPIO_ALFL_ALFSEL7_Pos)                               /*!< 0x40000000 */
#define GPIO_ALFL_ALFSEL7_3                                         (0x8UL << GPIO_ALFL_ALFSEL7_Pos)                               /*!< 0x80000000 */

/* Legacy defines */
#define GPIO_ALFL_AFRL0                                             GPIO_ALFL_ALFSEL0
#define GPIO_ALFL_AFRL0_0                                           GPIO_ALFL_ALFSEL0_0
#define GPIO_ALFL_AFRL0_1                                           GPIO_ALFL_ALFSEL0_1
#define GPIO_ALFL_AFRL0_2                                           GPIO_ALFL_ALFSEL0_2
#define GPIO_ALFL_AFRL0_3                                           GPIO_ALFL_ALFSEL0_3
#define GPIO_ALFL_AFRL1                                             GPIO_ALFL_ALFSEL1
#define GPIO_ALFL_AFRL1_0                                           GPIO_ALFL_ALFSEL1_0
#define GPIO_ALFL_AFRL1_1                                           GPIO_ALFL_ALFSEL1_1
#define GPIO_ALFL_AFRL1_2                                           GPIO_ALFL_ALFSEL1_2
#define GPIO_ALFL_AFRL1_3                                           GPIO_ALFL_ALFSEL1_3
#define GPIO_ALFL_AFRL2                                             GPIO_ALFL_ALFSEL2
#define GPIO_ALFL_AFRL2_0                                           GPIO_ALFL_ALFSEL2_0
#define GPIO_ALFL_AFRL2_1                                           GPIO_ALFL_ALFSEL2_1
#define GPIO_ALFL_AFRL2_2                                           GPIO_ALFL_ALFSEL2_2
#define GPIO_ALFL_AFRL2_3                                           GPIO_ALFL_ALFSEL2_3
#define GPIO_ALFL_AFRL3                                             GPIO_ALFL_ALFSEL3
#define GPIO_ALFL_AFRL3_0                                           GPIO_ALFL_ALFSEL3_0
#define GPIO_ALFL_AFRL3_1                                           GPIO_ALFL_ALFSEL3_1
#define GPIO_ALFL_AFRL3_2                                           GPIO_ALFL_ALFSEL3_2
#define GPIO_ALFL_AFRL3_3                                           GPIO_ALFL_ALFSEL3_3
#define GPIO_ALFL_AFRL4                                             GPIO_ALFL_ALFSEL4
#define GPIO_ALFL_AFRL4_0                                           GPIO_ALFL_ALFSEL4_0
#define GPIO_ALFL_AFRL4_1                                           GPIO_ALFL_ALFSEL4_1
#define GPIO_ALFL_AFRL4_2                                           GPIO_ALFL_ALFSEL4_2
#define GPIO_ALFL_AFRL4_3                                           GPIO_ALFL_ALFSEL4_3
#define GPIO_ALFL_AFRL5                                             GPIO_ALFL_ALFSEL5
#define GPIO_ALFL_AFRL5_0                                           GPIO_ALFL_ALFSEL5_0
#define GPIO_ALFL_AFRL5_1                                           GPIO_ALFL_ALFSEL5_1
#define GPIO_ALFL_AFRL5_2                                           GPIO_ALFL_ALFSEL5_2
#define GPIO_ALFL_AFRL5_3                                           GPIO_ALFL_ALFSEL5_3
#define GPIO_ALFL_AFRL6                                             GPIO_ALFL_ALFSEL6
#define GPIO_ALFL_AFRL6_0                                           GPIO_ALFL_ALFSEL6_0
#define GPIO_ALFL_AFRL6_1                                           GPIO_ALFL_ALFSEL6_1
#define GPIO_ALFL_AFRL6_2                                           GPIO_ALFL_ALFSEL6_2
#define GPIO_ALFL_AFRL6_3                                           GPIO_ALFL_ALFSEL6_3
#define GPIO_ALFL_AFRL7                                             GPIO_ALFL_ALFSEL7
#define GPIO_ALFL_AFRL7_0                                           GPIO_ALFL_ALFSEL7_0
#define GPIO_ALFL_AFRL7_1                                           GPIO_ALFL_ALFSEL7_1
#define GPIO_ALFL_AFRL7_2                                           GPIO_ALFL_ALFSEL7_2
#define GPIO_ALFL_AFRL7_3                                           GPIO_ALFL_ALFSEL7_3

/****************** Bit definition for GPIO_ALFH register *********************/
#define GPIO_ALFH_ALFSEL8_Pos                                       (0U)
#define GPIO_ALFH_ALFSEL8_Msk                                       (0xFUL << GPIO_ALFH_ALFSEL8_Pos)                               /*!< 0x0000000F */
#define GPIO_ALFH_ALFSEL8                                           GPIO_ALFH_ALFSEL8_Msk
#define GPIO_ALFH_ALFSEL8_0                                         (0x1UL << GPIO_ALFH_ALFSEL8_Pos)                               /*!< 0x00000001 */
#define GPIO_ALFH_ALFSEL8_1                                         (0x2UL << GPIO_ALFH_ALFSEL8_Pos)                               /*!< 0x00000002 */
#define GPIO_ALFH_ALFSEL8_2                                         (0x4UL << GPIO_ALFH_ALFSEL8_Pos)                               /*!< 0x00000004 */
#define GPIO_ALFH_ALFSEL8_3                                         (0x8UL << GPIO_ALFH_ALFSEL8_Pos)                               /*!< 0x00000008 */
#define GPIO_ALFH_ALFSEL9_Pos                                       (4U)
#define GPIO_ALFH_ALFSEL9_Msk                                       (0xFUL << GPIO_ALFH_ALFSEL9_Pos)                               /*!< 0x000000F0 */
#define GPIO_ALFH_ALFSEL9                                           GPIO_ALFH_ALFSEL9_Msk
#define GPIO_ALFH_ALFSEL9_0                                         (0x1UL << GPIO_ALFH_ALFSEL9_Pos)                               /*!< 0x00000010 */
#define GPIO_ALFH_ALFSEL9_1                                         (0x2UL << GPIO_ALFH_ALFSEL9_Pos)                               /*!< 0x00000020 */
#define GPIO_ALFH_ALFSEL9_2                                         (0x4UL << GPIO_ALFH_ALFSEL9_Pos)                               /*!< 0x00000040 */
#define GPIO_ALFH_ALFSEL9_3                                         (0x8UL << GPIO_ALFH_ALFSEL9_Pos)                               /*!< 0x00000080 */
#define GPIO_ALFH_ALFSEL10_Pos                                      (8U)
#define GPIO_ALFH_ALFSEL10_Msk                                      (0xFUL << GPIO_ALFH_ALFSEL10_Pos)                              /*!< 0x00000F00 */
#define GPIO_ALFH_ALFSEL10                                          GPIO_ALFH_ALFSEL10_Msk
#define GPIO_ALFH_ALFSEL10_0                                        (0x1UL << GPIO_ALFH_ALFSEL10_Pos)                              /*!< 0x00000100 */
#define GPIO_ALFH_ALFSEL10_1                                        (0x2UL << GPIO_ALFH_ALFSEL10_Pos)                              /*!< 0x00000200 */
#define GPIO_ALFH_ALFSEL10_2                                        (0x4UL << GPIO_ALFH_ALFSEL10_Pos)                              /*!< 0x00000400 */
#define GPIO_ALFH_ALFSEL10_3                                        (0x8UL << GPIO_ALFH_ALFSEL10_Pos)                              /*!< 0x00000800 */
#define GPIO_ALFH_ALFSEL11_Pos                                      (12U)
#define GPIO_ALFH_ALFSEL11_Msk                                      (0xFUL << GPIO_ALFH_ALFSEL11_Pos)                              /*!< 0x0000F000 */
#define GPIO_ALFH_ALFSEL11                                          GPIO_ALFH_ALFSEL11_Msk
#define GPIO_ALFH_ALFSEL11_0                                        (0x1UL << GPIO_ALFH_ALFSEL11_Pos)                              /*!< 0x00001000 */
#define GPIO_ALFH_ALFSEL11_1                                        (0x2UL << GPIO_ALFH_ALFSEL11_Pos)                              /*!< 0x00002000 */
#define GPIO_ALFH_ALFSEL11_2                                        (0x4UL << GPIO_ALFH_ALFSEL11_Pos)                              /*!< 0x00004000 */
#define GPIO_ALFH_ALFSEL11_3                                        (0x8UL << GPIO_ALFH_ALFSEL11_Pos)                              /*!< 0x00008000 */
#define GPIO_ALFH_ALFSEL12_Pos                                      (16U)
#define GPIO_ALFH_ALFSEL12_Msk                                      (0xFUL << GPIO_ALFH_ALFSEL12_Pos)                              /*!< 0x000F0000 */
#define GPIO_ALFH_ALFSEL12                                          GPIO_ALFH_ALFSEL12_Msk
#define GPIO_ALFH_ALFSEL12_0                                        (0x1UL << GPIO_ALFH_ALFSEL12_Pos)                              /*!< 0x00010000 */
#define GPIO_ALFH_ALFSEL12_1                                        (0x2UL << GPIO_ALFH_ALFSEL12_Pos)                              /*!< 0x00020000 */
#define GPIO_ALFH_ALFSEL12_2                                        (0x4UL << GPIO_ALFH_ALFSEL12_Pos)                              /*!< 0x00040000 */
#define GPIO_ALFH_ALFSEL12_3                                        (0x8UL << GPIO_ALFH_ALFSEL12_Pos)                              /*!< 0x00080000 */
#define GPIO_ALFH_ALFSEL13_Pos                                      (20U)
#define GPIO_ALFH_ALFSEL13_Msk                                      (0xFUL << GPIO_ALFH_ALFSEL13_Pos)                              /*!< 0x00F00000 */
#define GPIO_ALFH_ALFSEL13                                          GPIO_ALFH_ALFSEL13_Msk
#define GPIO_ALFH_ALFSEL13_0                                        (0x1UL << GPIO_ALFH_ALFSEL13_Pos)                              /*!< 0x00100000 */
#define GPIO_ALFH_ALFSEL13_1                                        (0x2UL << GPIO_ALFH_ALFSEL13_Pos)                              /*!< 0x00200000 */
#define GPIO_ALFH_ALFSEL13_2                                        (0x4UL << GPIO_ALFH_ALFSEL13_Pos)                              /*!< 0x00400000 */
#define GPIO_ALFH_ALFSEL13_3                                        (0x8UL << GPIO_ALFH_ALFSEL13_Pos)                              /*!< 0x00800000 */
#define GPIO_ALFH_ALFSEL14_Pos                                      (24U)
#define GPIO_ALFH_ALFSEL14_Msk                                      (0xFUL << GPIO_ALFH_ALFSEL14_Pos)                              /*!< 0x0F000000 */
#define GPIO_ALFH_ALFSEL14                                          GPIO_ALFH_ALFSEL14_Msk
#define GPIO_ALFH_ALFSEL14_0                                        (0x1UL << GPIO_ALFH_ALFSEL14_Pos)                              /*!< 0x01000000 */
#define GPIO_ALFH_ALFSEL14_1                                        (0x2UL << GPIO_ALFH_ALFSEL14_Pos)                              /*!< 0x02000000 */
#define GPIO_ALFH_ALFSEL14_2                                        (0x4UL << GPIO_ALFH_ALFSEL14_Pos)                              /*!< 0x04000000 */
#define GPIO_ALFH_ALFSEL14_3                                        (0x8UL << GPIO_ALFH_ALFSEL14_Pos)                              /*!< 0x08000000 */
#define GPIO_ALFH_ALFSEL15_Pos                                      (28U)
#define GPIO_ALFH_ALFSEL15_Msk                                      (0xFUL << GPIO_ALFH_ALFSEL15_Pos)                              /*!< 0xF0000000 */
#define GPIO_ALFH_ALFSEL15                                          GPIO_ALFH_ALFSEL15_Msk
#define GPIO_ALFH_ALFSEL15_0                                        (0x1UL << GPIO_ALFH_ALFSEL15_Pos)                              /*!< 0x10000000 */
#define GPIO_ALFH_ALFSEL15_1                                        (0x2UL << GPIO_ALFH_ALFSEL15_Pos)                              /*!< 0x20000000 */
#define GPIO_ALFH_ALFSEL15_2                                        (0x4UL << GPIO_ALFH_ALFSEL15_Pos)                              /*!< 0x40000000 */
#define GPIO_ALFH_ALFSEL15_3                                        (0x8UL << GPIO_ALFH_ALFSEL15_Pos)                              /*!< 0x80000000 */

/* Legacy defines */
#define GPIO_ALFH_AFRH0                                             GPIO_ALFH_ALFSEL8
#define GPIO_ALFH_AFRH0_0                                           GPIO_ALFH_ALFSEL8_0
#define GPIO_ALFH_AFRH0_1                                           GPIO_ALFH_ALFSEL8_1
#define GPIO_ALFH_AFRH0_2                                           GPIO_ALFH_ALFSEL8_2
#define GPIO_ALFH_AFRH0_3                                           GPIO_ALFH_ALFSEL8_3
#define GPIO_ALFH_AFRH1                                             GPIO_ALFH_ALFSEL9
#define GPIO_ALFH_AFRH1_0                                           GPIO_ALFH_ALFSEL9_0
#define GPIO_ALFH_AFRH1_1                                           GPIO_ALFH_ALFSEL9_1
#define GPIO_ALFH_AFRH1_2                                           GPIO_ALFH_ALFSEL9_2
#define GPIO_ALFH_AFRH1_3                                           GPIO_ALFH_ALFSEL9_3
#define GPIO_ALFH_AFRH2                                             GPIO_ALFH_ALFSEL10
#define GPIO_ALFH_AFRH2_0                                           GPIO_ALFH_ALFSEL10_0
#define GPIO_ALFH_AFRH2_1                                           GPIO_ALFH_ALFSEL10_1
#define GPIO_ALFH_AFRH2_2                                           GPIO_ALFH_ALFSEL10_2
#define GPIO_ALFH_AFRH2_3                                           GPIO_ALFH_ALFSEL10_3
#define GPIO_ALFH_AFRH3                                             GPIO_ALFH_ALFSEL11
#define GPIO_ALFH_AFRH3_0                                           GPIO_ALFH_ALFSEL11_0
#define GPIO_ALFH_AFRH3_1                                           GPIO_ALFH_ALFSEL11_1
#define GPIO_ALFH_AFRH3_2                                           GPIO_ALFH_ALFSEL11_2
#define GPIO_ALFH_AFRH3_3                                           GPIO_ALFH_ALFSEL11_3
#define GPIO_ALFH_AFRH4                                             GPIO_ALFH_ALFSEL12
#define GPIO_ALFH_AFRH4_0                                           GPIO_ALFH_ALFSEL12_0
#define GPIO_ALFH_AFRH4_1                                           GPIO_ALFH_ALFSEL12_1
#define GPIO_ALFH_AFRH4_2                                           GPIO_ALFH_ALFSEL12_2
#define GPIO_ALFH_AFRH4_3                                           GPIO_ALFH_ALFSEL12_3
#define GPIO_ALFH_AFRH5                                             GPIO_ALFH_ALFSEL13
#define GPIO_ALFH_AFRH5_0                                           GPIO_ALFH_ALFSEL13_0
#define GPIO_ALFH_AFRH5_1                                           GPIO_ALFH_ALFSEL13_1
#define GPIO_ALFH_AFRH5_2                                           GPIO_ALFH_ALFSEL13_2
#define GPIO_ALFH_AFRH5_3                                           GPIO_ALFH_ALFSEL13_3
#define GPIO_ALFH_AFRH6                                             GPIO_ALFH_ALFSEL14
#define GPIO_ALFH_AFRH6_0                                           GPIO_ALFH_ALFSEL14_0
#define GPIO_ALFH_AFRH6_1                                           GPIO_ALFH_ALFSEL14_1
#define GPIO_ALFH_AFRH6_2                                           GPIO_ALFH_ALFSEL14_2
#define GPIO_ALFH_AFRH6_3                                           GPIO_ALFH_ALFSEL14_3
#define GPIO_ALFH_AFRH7                                             GPIO_ALFH_ALFSEL15
#define GPIO_ALFH_AFRH7_0                                           GPIO_ALFH_ALFSEL15_0
#define GPIO_ALFH_AFRH7_1                                           GPIO_ALFH_ALFSEL15_1
#define GPIO_ALFH_AFRH7_2                                           GPIO_ALFH_ALFSEL15_2
#define GPIO_ALFH_AFRH7_3                                           GPIO_ALFH_ALFSEL15_3


/******************************************************************************/
/*                                                                            */
/*                      Inter-integrated Circuit Interface                    */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for I2C_CTRL1 register  ********************/
#define I2C_CTRL1_I2CEN_Pos                                         (0U)
#define I2C_CTRL1_I2CEN_Msk                                         (0x1UL << I2C_CTRL1_I2CEN_Pos)                                 /*!< 0x00000001 */
#define I2C_CTRL1_I2CEN                                             I2C_CTRL1_I2CEN_Msk                                            /*!<Peripheral Enable                             */
#define I2C_CTRL1_SMBEN_Pos                                         (1U)
#define I2C_CTRL1_SMBEN_Msk                                         (0x1UL << I2C_CTRL1_SMBEN_Pos)                                 /*!< 0x00000002 */
#define I2C_CTRL1_SMBEN                                             I2C_CTRL1_SMBEN_Msk                                            /*!<SMBus Mode                                    */
#define I2C_CTRL1_SMBTCFG_Pos                                       (3U)
#define I2C_CTRL1_SMBTCFG_Msk                                       (0x1UL << I2C_CTRL1_SMBTCFG_Pos)                               /*!< 0x00000008 */
#define I2C_CTRL1_SMBTCFG                                           I2C_CTRL1_SMBTCFG_Msk                                          /*!<SMBus Type                                    */
#define I2C_CTRL1_ARPEN_Pos                                         (4U)
#define I2C_CTRL1_ARPEN_Msk                                         (0x1UL << I2C_CTRL1_ARPEN_Pos)                                 /*!< 0x00000010 */
#define I2C_CTRL1_ARPEN                                             I2C_CTRL1_ARPEN_Msk                                            /*!<ARP Enable                                    */
#define I2C_CTRL1_PECEN_Pos                                         (5U)
#define I2C_CTRL1_PECEN_Msk                                         (0x1UL << I2C_CTRL1_PECEN_Pos)                                 /*!< 0x00000020 */
#define I2C_CTRL1_PECEN                                             I2C_CTRL1_PECEN_Msk                                            /*!<PEC Enable                                    */
#define I2C_CTRL1_SRBEN_Pos                                         (6U)
#define I2C_CTRL1_SRBEN_Msk                                         (0x1UL << I2C_CTRL1_SRBEN_Pos)                                 /*!< 0x00000040 */
#define I2C_CTRL1_SRBEN                                             I2C_CTRL1_SRBEN_Msk                                            /*!<General Call Enable                           */
#define I2C_CTRL1_CLKSTRETCHD_Pos                                   (7U)
#define I2C_CTRL1_CLKSTRETCHD_Msk                                   (0x1UL << I2C_CTRL1_CLKSTRETCHD_Pos)                           /*!< 0x00000080 */
#define I2C_CTRL1_CLKSTRETCHD                                       I2C_CTRL1_CLKSTRETCHD_Msk                                      /*!<Clock Stretching Disable (Slave mode)         */
#define I2C_CTRL1_START_Pos                                         (8U)
#define I2C_CTRL1_START_Msk                                         (0x1UL << I2C_CTRL1_START_Pos)                                 /*!< 0x00000100 */
#define I2C_CTRL1_START                                             I2C_CTRL1_START_Msk                                            /*!<Start Generation                              */
#define I2C_CTRL1_STOP_Pos                                          (9U)
#define I2C_CTRL1_STOP_Msk                                          (0x1UL << I2C_CTRL1_STOP_Pos)                                  /*!< 0x00000200 */
#define I2C_CTRL1_STOP                                              I2C_CTRL1_STOP_Msk                                             /*!<Stop Generation                               */
#define I2C_CTRL1_ACKEN_Pos                                         (10U)
#define I2C_CTRL1_ACKEN_Msk                                         (0x1UL << I2C_CTRL1_ACKEN_Pos)                                 /*!< 0x00000400 */
#define I2C_CTRL1_ACKEN                                             I2C_CTRL1_ACKEN_Msk                                            /*!<Acknowledge Enable                            */
#define I2C_CTRL1_ACKPOS_Pos                                        (11U)
#define I2C_CTRL1_ACKPOS_Msk                                        (0x1UL << I2C_CTRL1_ACKPOS_Pos)                                /*!< 0x00000800 */
#define I2C_CTRL1_ACKPOS                                            I2C_CTRL1_ACKPOS_Msk                                           /*!<Acknowledge/PEC Position (for data reception) */
#define I2C_CTRL1_PEC_Pos                                           (12U)
#define I2C_CTRL1_PEC_Msk                                           (0x1UL << I2C_CTRL1_PEC_Pos)                                   /*!< 0x00001000 */
#define I2C_CTRL1_PEC                                               I2C_CTRL1_PEC_Msk                                              /*!<Packet Error Checking                         */
#define I2C_CTRL1_ALERTEN_Pos                                       (13U)
#define I2C_CTRL1_ALERTEN_Msk                                       (0x1UL << I2C_CTRL1_ALERTEN_Pos)                               /*!< 0x00002000 */
#define I2C_CTRL1_ALERTEN                                           I2C_CTRL1_ALERTEN_Msk                                          /*!<SMBus Alert                                   */
#define I2C_CTRL1_SWRST_Pos                                         (15U)
#define I2C_CTRL1_SWRST_Msk                                         (0x1UL << I2C_CTRL1_SWRST_Pos)                                 /*!< 0x00008000 */
#define I2C_CTRL1_SWRST                                             I2C_CTRL1_SWRST_Msk                                            /*!<Software Reset                                */

/*******************  Bit definition for I2C_CTRL2 register  ********************/
#define I2C_CTRL2_CLKFCFG_Pos                                       (0U)
#define I2C_CTRL2_CLKFCFG_Msk                                       (0x3FUL << I2C_CTRL2_CLKFCFG_Pos)                              /*!< 0x0000003F */
#define I2C_CTRL2_CLKFCFG                                           I2C_CTRL2_CLKFCFG_Msk                                          /*!<FREQ[5:0] bits (Peripheral Clock Frequency)   */
#define I2C_CTRL2_CLKFCFG_0                                         (0x01UL << I2C_CTRL2_CLKFCFG_Pos)                              /*!< 0x00000001 */
#define I2C_CTRL2_CLKFCFG_1                                         (0x02UL << I2C_CTRL2_CLKFCFG_Pos)                              /*!< 0x00000002 */
#define I2C_CTRL2_CLKFCFG_2                                         (0x04UL << I2C_CTRL2_CLKFCFG_Pos)                              /*!< 0x00000004 */
#define I2C_CTRL2_CLKFCFG_3                                         (0x08UL << I2C_CTRL2_CLKFCFG_Pos)                              /*!< 0x00000008 */
#define I2C_CTRL2_CLKFCFG_4                                         (0x10UL << I2C_CTRL2_CLKFCFG_Pos)                              /*!< 0x00000010 */
#define I2C_CTRL2_CLKFCFG_5                                         (0x20UL << I2C_CTRL2_CLKFCFG_Pos)                              /*!< 0x00000020 */

#define I2C_CTRL2_ERRIEN_Pos                                        (8U)
#define I2C_CTRL2_ERRIEN_Msk                                        (0x1UL << I2C_CTRL2_ERRIEN_Pos)                                /*!< 0x00000100 */
#define I2C_CTRL2_ERRIEN                                            I2C_CTRL2_ERRIEN_Msk                                           /*!<Error Interrupt Enable  */
#define I2C_CTRL2_EVIEN_Pos                                         (9U)
#define I2C_CTRL2_EVIEN_Msk                                         (0x1UL << I2C_CTRL2_EVIEN_Pos)                                 /*!< 0x00000200 */
#define I2C_CTRL2_EVIEN                                             I2C_CTRL2_EVIEN_Msk                                            /*!<Event Interrupt Enable  */
#define I2C_CTRL2_BUFIEN_Pos                                        (10U)
#define I2C_CTRL2_BUFIEN_Msk                                        (0x1UL << I2C_CTRL2_BUFIEN_Pos)                                /*!< 0x00000400 */
#define I2C_CTRL2_BUFIEN                                            I2C_CTRL2_BUFIEN_Msk                                           /*!<Buffer Interrupt Enable */
#define I2C_CTRL2_DMAEN_Pos                                         (11U)
#define I2C_CTRL2_DMAEN_Msk                                         (0x1UL << I2C_CTRL2_DMAEN_Pos)                                 /*!< 0x00000800 */
#define I2C_CTRL2_DMAEN                                             I2C_CTRL2_DMAEN_Msk                                            /*!<DMA Requests Enable     */
#define I2C_CTRL2_LTCFG_Pos                                         (12U)
#define I2C_CTRL2_LTCFG_Msk                                         (0x1UL << I2C_CTRL2_LTCFG_Pos)                                 /*!< 0x00001000 */
#define I2C_CTRL2_LTCFG                                             I2C_CTRL2_LTCFG_Msk                                            /*!<DMA Last Transfer       */

/*******************  Bit definition for I2C_SADDR1 register  *******************/
#define I2C_SADDR1_ADDR1_7                                          0x000000FEU                                                    /*!<Interface Address */
#define I2C_SADDR1_ADDR8_9                                          0x00000300U                                                    /*!<Interface Address */

#define I2C_SADDR1_ADDR0_Pos                                        (0U)
#define I2C_SADDR1_ADDR0_Msk                                        (0x1UL << I2C_SADDR1_ADDR0_Pos)                                /*!< 0x00000001 */
#define I2C_SADDR1_ADDR0                                            I2C_SADDR1_ADDR0_Msk                                           /*!<Bit 0 */
#define I2C_SADDR1_ADDR1_Pos                                        (1U)
#define I2C_SADDR1_ADDR1_Msk                                        (0x1UL << I2C_SADDR1_ADDR1_Pos)                                /*!< 0x00000002 */
#define I2C_SADDR1_ADDR1                                            I2C_SADDR1_ADDR1_Msk                                           /*!<Bit 1 */
#define I2C_SADDR1_ADDR2_Pos                                        (2U)
#define I2C_SADDR1_ADDR2_Msk                                        (0x1UL << I2C_SADDR1_ADDR2_Pos)                                /*!< 0x00000004 */
#define I2C_SADDR1_ADDR2                                            I2C_SADDR1_ADDR2_Msk                                           /*!<Bit 2 */
#define I2C_SADDR1_ADDR3_Pos                                        (3U)
#define I2C_SADDR1_ADDR3_Msk                                        (0x1UL << I2C_SADDR1_ADDR3_Pos)                                /*!< 0x00000008 */
#define I2C_SADDR1_ADDR3                                            I2C_SADDR1_ADDR3_Msk                                           /*!<Bit 3 */
#define I2C_SADDR1_ADDR4_Pos                                        (4U)
#define I2C_SADDR1_ADDR4_Msk                                        (0x1UL << I2C_SADDR1_ADDR4_Pos)                                /*!< 0x00000010 */
#define I2C_SADDR1_ADDR4                                            I2C_SADDR1_ADDR4_Msk                                           /*!<Bit 4 */
#define I2C_SADDR1_ADDR5_Pos                                        (5U)
#define I2C_SADDR1_ADDR5_Msk                                        (0x1UL << I2C_SADDR1_ADDR5_Pos)                                /*!< 0x00000020 */
#define I2C_SADDR1_ADDR5                                            I2C_SADDR1_ADDR5_Msk                                           /*!<Bit 5 */
#define I2C_SADDR1_ADDR6_Pos                                        (6U)
#define I2C_SADDR1_ADDR6_Msk                                        (0x1UL << I2C_SADDR1_ADDR6_Pos)                                /*!< 0x00000040 */
#define I2C_SADDR1_ADDR6                                            I2C_SADDR1_ADDR6_Msk                                           /*!<Bit 6 */
#define I2C_SADDR1_ADDR7_Pos                                        (7U)
#define I2C_SADDR1_ADDR7_Msk                                        (0x1UL << I2C_SADDR1_ADDR7_Pos)                                /*!< 0x00000080 */
#define I2C_SADDR1_ADDR7                                            I2C_SADDR1_ADDR7_Msk                                           /*!<Bit 7 */
#define I2C_SADDR1_ADDR8_Pos                                        (8U)
#define I2C_SADDR1_ADDR8_Msk                                        (0x1UL << I2C_SADDR1_ADDR8_Pos)                                /*!< 0x00000100 */
#define I2C_SADDR1_ADDR8                                            I2C_SADDR1_ADDR8_Msk                                           /*!<Bit 8 */
#define I2C_SADDR1_ADDR9_Pos                                        (9U)
#define I2C_SADDR1_ADDR9_Msk                                        (0x1UL << I2C_SADDR1_ADDR9_Pos)                                /*!< 0x00000200 */
#define I2C_SADDR1_ADDR9                                            I2C_SADDR1_ADDR9_Msk                                           /*!<Bit 9 */

#define I2C_SADDR1_ADDRLEN_Pos                                      (15U)
#define I2C_SADDR1_ADDRLEN_Msk                                      (0x1UL << I2C_SADDR1_ADDRLEN_Pos)                              /*!< 0x00008000 */
#define I2C_SADDR1_ADDRLEN                                          I2C_SADDR1_ADDRLEN_Msk                                         /*!<Addressing Mode (Slave mode) */

/*******************  Bit definition for I2C_SADDR2 register  *******************/
#define I2C_SADDR2_ADDRNUM_Pos                                      (0U)
#define I2C_SADDR2_ADDRNUM_Msk                                      (0x1UL << I2C_SADDR2_ADDRNUM_Pos)                              /*!< 0x00000001 */
#define I2C_SADDR2_ADDRNUM                                          I2C_SADDR2_ADDRNUM_Msk                                         /*!<Dual addressing mode enable */
#define I2C_SADDR2_ADDR2_Pos                                        (1U)
#define I2C_SADDR2_ADDR2_Msk                                        (0x7FUL << I2C_SADDR2_ADDR2_Pos)                               /*!< 0x000000FE */
#define I2C_SADDR2_ADDR2                                            I2C_SADDR2_ADDR2_Msk                                           /*!<Interface address           */

/********************  Bit definition for I2C_DATA register  ********************/
#define I2C_DATA_DATA_Pos                                           (0U)
#define I2C_DATA_DATA_Msk                                           (0xFFUL << I2C_DATA_DATA_Pos)                                  /*!< 0x000000FF */
#define I2C_DATA_DATA                                               I2C_DATA_DATA_Msk                                              /*!<8-bit Data Register         */

/*******************  Bit definition for I2C_STS1 register  ********************/
#define I2C_STS1_STARTFLG_Pos                                       (0U)
#define I2C_STS1_STARTFLG_Msk                                       (0x1UL << I2C_STS1_STARTFLG_Pos)                               /*!< 0x00000001 */
#define I2C_STS1_STARTFLG                                           I2C_STS1_STARTFLG_Msk                                          /*!<Start Bit (Master mode)                         */
#define I2C_STS1_ADDRFLG_Pos                                        (1U)
#define I2C_STS1_ADDRFLG_Msk                                        (0x1UL << I2C_STS1_ADDRFLG_Pos)                                /*!< 0x00000002 */
#define I2C_STS1_ADDRFLG                                            I2C_STS1_ADDRFLG_Msk                                           /*!<Address sent (master mode)/matched (slave mode) */
#define I2C_STS1_BTCFLG_Pos                                         (2U)
#define I2C_STS1_BTCFLG_Msk                                         (0x1UL << I2C_STS1_BTCFLG_Pos)                                 /*!< 0x00000004 */
#define I2C_STS1_BTCFLG                                             I2C_STS1_BTCFLG_Msk                                            /*!<Byte Transfer Finished                          */
#define I2C_STS1_ADDR10FLG_Pos                                      (3U)
#define I2C_STS1_ADDR10FLG_Msk                                      (0x1UL << I2C_STS1_ADDR10FLG_Pos)                              /*!< 0x00000008 */
#define I2C_STS1_ADDR10FLG                                          I2C_STS1_ADDR10FLG_Msk                                         /*!<10-bit header sent (Master mode)                */
#define I2C_STS1_STOPFLG_Pos                                        (4U)
#define I2C_STS1_STOPFLG_Msk                                        (0x1UL << I2C_STS1_STOPFLG_Pos)                                /*!< 0x00000010 */
#define I2C_STS1_STOPFLG                                            I2C_STS1_STOPFLG_Msk                                           /*!<Stop detection (Slave mode)                     */
#define I2C_STS1_RXBNEFLG_Pos                                       (6U)
#define I2C_STS1_RXBNEFLG_Msk                                       (0x1UL << I2C_STS1_RXBNEFLG_Pos)                               /*!< 0x00000040 */
#define I2C_STS1_RXBNEFLG                                           I2C_STS1_RXBNEFLG_Msk                                          /*!<Data Register not Empty (receivers)             */
#define I2C_STS1_TXBEFLG_Pos                                        (7U)
#define I2C_STS1_TXBEFLG_Msk                                        (0x1UL << I2C_STS1_TXBEFLG_Pos)                                /*!< 0x00000080 */
#define I2C_STS1_TXBEFLG                                            I2C_STS1_TXBEFLG_Msk                                           /*!<Data Register Empty (transmitters)              */
#define I2C_STS1_BERRFLG_Pos                                        (8U)
#define I2C_STS1_BERRFLG_Msk                                        (0x1UL << I2C_STS1_BERRFLG_Pos)                                /*!< 0x00000100 */
#define I2C_STS1_BERRFLG                                            I2C_STS1_BERRFLG_Msk                                           /*!<Bus Error                                       */
#define I2C_STS1_ALFLG_Pos                                          (9U)
#define I2C_STS1_ALFLG_Msk                                          (0x1UL << I2C_STS1_ALFLG_Pos)                                  /*!< 0x00000200 */
#define I2C_STS1_ALFLG                                              I2C_STS1_ALFLG_Msk                                             /*!<Arbitration Lost (master mode)                  */
#define I2C_STS1_AEFLG_Pos                                          (10U)
#define I2C_STS1_AEFLG_Msk                                          (0x1UL << I2C_STS1_AEFLG_Pos)                                  /*!< 0x00000400 */
#define I2C_STS1_AEFLG                                              I2C_STS1_AEFLG_Msk                                             /*!<Acknowledge Failure                             */
#define I2C_STS1_OVRURFLG_Pos                                       (11U)
#define I2C_STS1_OVRURFLG_Msk                                       (0x1UL << I2C_STS1_OVRURFLG_Pos)                               /*!< 0x00000800 */
#define I2C_STS1_OVRURFLG                                           I2C_STS1_OVRURFLG_Msk                                          /*!<Overrun/Underrun                                */
#define I2C_STS1_PECEFLG_Pos                                        (12U)
#define I2C_STS1_PECEFLG_Msk                                        (0x1UL << I2C_STS1_PECEFLG_Pos)                                /*!< 0x00001000 */
#define I2C_STS1_PECEFLG                                            I2C_STS1_PECEFLG_Msk                                           /*!<PEC Error in reception                          */
#define I2C_STS1_TTEFLG_Pos                                         (14U)
#define I2C_STS1_TTEFLG_Msk                                         (0x1UL << I2C_STS1_TTEFLG_Pos)                                 /*!< 0x00004000 */
#define I2C_STS1_TTEFLG                                             I2C_STS1_TTEFLG_Msk                                            /*!<Timeout or Tlow Error                           */
#define I2C_STS1_SMBALTFLG_Pos                                      (15U)
#define I2C_STS1_SMBALTFLG_Msk                                      (0x1UL << I2C_STS1_SMBALTFLG_Pos)                              /*!< 0x00008000 */
#define I2C_STS1_SMBALTFLG                                          I2C_STS1_SMBALTFLG_Msk                                         /*!<SMBus Alert                                     */

/*******************  Bit definition for I2C_STS2 register  ********************/
#define I2C_STS2_MSFLG_Pos                                          (0U)
#define I2C_STS2_MSFLG_Msk                                          (0x1UL << I2C_STS2_MSFLG_Pos)                                  /*!< 0x00000001 */
#define I2C_STS2_MSFLG                                              I2C_STS2_MSFLG_Msk                                             /*!<Master/Slave                                    */
#define I2C_STS2_BUSBSYFLG_Pos                                      (1U)
#define I2C_STS2_BUSBSYFLG_Msk                                      (0x1UL << I2C_STS2_BUSBSYFLG_Pos)                              /*!< 0x00000002 */
#define I2C_STS2_BUSBSYFLG                                          I2C_STS2_BUSBSYFLG_Msk                                         /*!<Bus Busy                                        */
#define I2C_STS2_TRFLG_Pos                                          (2U)
#define I2C_STS2_TRFLG_Msk                                          (0x1UL << I2C_STS2_TRFLG_Pos)                                  /*!< 0x00000004 */
#define I2C_STS2_TRFLG                                              I2C_STS2_TRFLG_Msk                                             /*!<Transmitter/Receiver                            */
#define I2C_STS2_GENCALLFLG_Pos                                     (4U)
#define I2C_STS2_GENCALLFLG_Msk                                     (0x1UL << I2C_STS2_GENCALLFLG_Pos)                             /*!< 0x00000010 */
#define I2C_STS2_GENCALLFLG                                         I2C_STS2_GENCALLFLG_Msk                                        /*!<General Call Address (Slave mode)               */
#define I2C_STS2_SMBDADDRFLG_Pos                                    (5U)
#define I2C_STS2_SMBDADDRFLG_Msk                                    (0x1UL << I2C_STS2_SMBDADDRFLG_Pos)                            /*!< 0x00000020 */
#define I2C_STS2_SMBDADDRFLG                                        I2C_STS2_SMBDADDRFLG_Msk                                       /*!<SMBus Device Default Address (Slave mode)       */
#define I2C_STS2_SMMHADDR_Pos                                       (6U)
#define I2C_STS2_SMMHADDR_Msk                                       (0x1UL << I2C_STS2_SMMHADDR_Pos)                               /*!< 0x00000040 */
#define I2C_STS2_SMMHADDR                                           I2C_STS2_SMMHADDR_Msk                                          /*!<SMBus Host Header (Slave mode)                  */
#define I2C_STS2_DUALADDRFLG_Pos                                    (7U)
#define I2C_STS2_DUALADDRFLG_Msk                                    (0x1UL << I2C_STS2_DUALADDRFLG_Pos)                            /*!< 0x00000080 */
#define I2C_STS2_DUALADDRFLG                                        I2C_STS2_DUALADDRFLG_Msk                                       /*!<Dual Flag (Slave mode)                          */
#define I2C_STS2_PECVALUE_Pos                                       (8U)
#define I2C_STS2_PECVALUE_Msk                                       (0xFFUL << I2C_STS2_PECVALUE_Pos)                              /*!< 0x0000FF00 */
#define I2C_STS2_PECVALUE                                           I2C_STS2_PECVALUE_Msk                                          /*!<Packet Error Checking Register                  */

/*******************  Bit definition for I2C_CLKCTRL register  ********************/
#define I2C_CLKCTRL_CLKS_Pos                                        (0U)
#define I2C_CLKCTRL_CLKS_Msk                                        (0xFFFUL << I2C_CLKCTRL_CLKS_Pos)                              /*!< 0x00000FFF */
#define I2C_CLKCTRL_CLKS                                            I2C_CLKCTRL_CLKS_Msk                                           /*!<Clock Control Register in Fast/Standard mode (Master mode) */
#define I2C_CLKCTRL_FDUTYCFG_Pos                                    (14U)
#define I2C_CLKCTRL_FDUTYCFG_Msk                                    (0x1UL << I2C_CLKCTRL_FDUTYCFG_Pos)                            /*!< 0x00004000 */
#define I2C_CLKCTRL_FDUTYCFG                                        I2C_CLKCTRL_FDUTYCFG_Msk                                       /*!<Fast Mode Duty Cycle                                       */
#define I2C_CLKCTRL_SPEEDCFG_Pos                                    (15U)
#define I2C_CLKCTRL_SPEEDCFG_Msk                                    (0x1UL << I2C_CLKCTRL_SPEEDCFG_Pos)                            /*!< 0x00008000 */
#define I2C_CLKCTRL_SPEEDCFG                                        I2C_CLKCTRL_SPEEDCFG_Msk                                       /*!<I2C Master Mode Selection                                  */

/******************  Bit definition for I2C_RISETMAX register  *******************/
#define I2C_RISETMAX_RISETMAX_Pos                                   (0U)
#define I2C_RISETMAX_RISETMAX_Msk                                   (0x3FUL << I2C_RISETMAX_RISETMAX_Pos)                          /*!< 0x0000003F */
#define I2C_RISETMAX_RISETMAX                                       I2C_RISETMAX_RISETMAX_Msk                                      /*!<Maximum Rise Time in Fast/Standard mode (Master mode) */


/******************************************************************************/
/*                                                                            */
/*                           Independent WATCHDOG                             */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for IWDT_KEY register  ********************/
#define IWDT_KEY_KEY_Pos                                            (0U)
#define IWDT_KEY_KEY_Msk                                            (0xFFFFUL << IWDT_KEY_KEY_Pos)                                 /*!< 0x0000FFFF */
#define IWDT_KEY_KEY                                                IWDT_KEY_KEY_Msk                                               /*!<Key value (write only, read 0000h)  */

/*******************  Bit definition for IWDT_PSC register  ********************/
#define IWDT_PSC_PSC_Pos                                            (0U)
#define IWDT_PSC_PSC_Msk                                            (0x7UL << IWDT_PSC_PSC_Pos)                                    /*!< 0x00000007 */
#define IWDT_PSC_PSC                                                IWDT_PSC_PSC_Msk                                               /*!<PR[2:0] (Prescaler divider)         */
#define IWDT_PSC_PSC_0                                              (0x1UL << IWDT_PSC_PSC_Pos)                                    /*!< 0x01 */
#define IWDT_PSC_PSC_1                                              (0x2UL << IWDT_PSC_PSC_Pos)                                    /*!< 0x02 */
#define IWDT_PSC_PSC_2                                              (0x4UL << IWDT_PSC_PSC_Pos)                                    /*!< 0x04 */

/*******************  Bit definition for IWDT_CNTRLD register  *******************/
#define IWDT_CNTRLD_CNTRLD_Pos                                      (0U)
#define IWDT_CNTRLD_CNTRLD_Msk                                      (0xFFFUL << IWDT_CNTRLD_CNTRLD_Pos)                            /*!< 0x00000FFF */
#define IWDT_CNTRLD_CNTRLD                                          IWDT_CNTRLD_CNTRLD_Msk                                         /*!<Watchdog counter reload value        */

/*******************  Bit definition for IWDT_STS register  ********************/
#define IWDT_STS_PSCUFLG_Pos                                        (0U)
#define IWDT_STS_PSCUFLG_Msk                                        (0x1UL << IWDT_STS_PSCUFLG_Pos)                                /*!< 0x00000001 */
#define IWDT_STS_PSCUFLG                                            IWDT_STS_PSCUFLG_Msk                                           /*!<Watchdog prescaler value update      */
#define IWDT_STS_CNTUFLG_Pos                                        (1U)
#define IWDT_STS_CNTUFLG_Msk                                        (0x1UL << IWDT_STS_CNTUFLG_Pos)                                /*!< 0x00000002 */
#define IWDT_STS_CNTUFLG                                            IWDT_STS_CNTUFLG_Msk                                           /*!<Watchdog counter reload value update */



/******************************************************************************/
/*                                                                            */
/*                             Power Control                                  */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for PMU_CTRL register  ********************/
#define PMU_CTRL_LPDSCFG_Pos                                        (0U)
#define PMU_CTRL_LPDSCFG_Msk                                        (0x1UL << PMU_CTRL_LPDSCFG_Pos)                                /*!< 0x00000001 */
#define PMU_CTRL_LPDSCFG                                            PMU_CTRL_LPDSCFG_Msk                                           /*!< Low-Power Deepsleep                 */
#define PMU_CTRL_PDDSCFG_Pos                                        (1U)
#define PMU_CTRL_PDDSCFG_Msk                                        (0x1UL << PMU_CTRL_PDDSCFG_Pos)                                /*!< 0x00000002 */
#define PMU_CTRL_PDDSCFG                                            PMU_CTRL_PDDSCFG_Msk                                           /*!< Power Down Deepsleep                */
#define PMU_CTRL_WUFLGCLR_Pos                                       (2U)
#define PMU_CTRL_WUFLGCLR_Msk                                       (0x1UL << PMU_CTRL_WUFLGCLR_Pos)                               /*!< 0x00000004 */
#define PMU_CTRL_WUFLGCLR                                           PMU_CTRL_WUFLGCLR_Msk                                          /*!< Clear Wakeup Flag                   */
#define PMU_CTRL_SBFLGCLR_Pos                                       (3U)
#define PMU_CTRL_SBFLGCLR_Msk                                       (0x1UL << PMU_CTRL_SBFLGCLR_Pos)                               /*!< 0x00000008 */
#define PMU_CTRL_SBFLGCLR                                           PMU_CTRL_SBFLGCLR_Msk                                          /*!< Clear Standby Flag                  */
#define PMU_CTRL_PVDEN_Pos                                          (4U)
#define PMU_CTRL_PVDEN_Msk                                          (0x1UL << PMU_CTRL_PVDEN_Pos)                                  /*!< 0x00000010 */
#define PMU_CTRL_PVDEN                                              PMU_CTRL_PVDEN_Msk                                             /*!< Power Voltage Detector Enable       */

#define PMU_CTRL_PLSEL_Pos                                          (5U)
#define PMU_CTRL_PLSEL_Msk                                          (0x7UL << PMU_CTRL_PLSEL_Pos)                                  /*!< 0x000000E0 */
#define PMU_CTRL_PLSEL                                              PMU_CTRL_PLSEL_Msk                                             /*!< PLS[2:0] bits (PVD Level Selection) */
#define PMU_CTRL_PLSEL_0                                            (0x1UL << PMU_CTRL_PLSEL_Pos)                                  /*!< 0x00000020 */
#define PMU_CTRL_PLSEL_1                                            (0x2UL << PMU_CTRL_PLSEL_Pos)                                  /*!< 0x00000040 */
#define PMU_CTRL_PLSEL_2                                            (0x4UL << PMU_CTRL_PLSEL_Pos)                                  /*!< 0x00000080 */

/*!< PVD level configuration */
#define PMU_CTRL_PLSEL_LEV0                                         0x00000000U                                                    /*!< PVD level 0 */
#define PMU_CTRL_PLSEL_LEV1                                         0x00000020U                                                    /*!< PVD level 1 */
#define PMU_CTRL_PLSEL_LEV2                                         0x00000040U                                                    /*!< PVD level 2 */
#define PMU_CTRL_PLSEL_LEV3                                         0x00000060U                                                    /*!< PVD level 3 */
#define PMU_CTRL_PLSEL_LEV4                                         0x00000080U                                                    /*!< PVD level 4 */
#define PMU_CTRL_PLSEL_LEV5                                         0x000000A0U                                                    /*!< PVD level 5 */
#define PMU_CTRL_PLSEL_LEV6                                         0x000000C0U                                                    /*!< PVD level 6 */
#define PMU_CTRL_PLSEL_LEV7                                         0x000000E0U                                                    /*!< PVD level 7 */
#define PMU_CTRL_BPWEN_Pos                                          (8U)
#define PMU_CTRL_BPWEN_Msk                                          (0x1UL << PMU_CTRL_BPWEN_Pos)                                  /*!< 0x00000100 */
#define PMU_CTRL_BPWEN                                              PMU_CTRL_BPWEN_Msk                                             /*!< Disable Backup Domain write protection                     */
#define PMU_CTRL_FPDSM_Pos                                          (9U)
#define PMU_CTRL_FPDSM_Msk                                          (0x1UL << PMU_CTRL_FPDSM_Pos)                                  /*!< 0x00000200 */
#define PMU_CTRL_FPDSM                                              PMU_CTRL_FPDSM_Msk                                             /*!< Flash power down in Stop mode                              */
#define PMU_CTRL_VOSSEL_Pos                                         (14U)
#define PMU_CTRL_VOSSEL_Msk                                         (0x1UL << PMU_CTRL_VOSSEL_Pos)                                 /*!< 0x00004000 */
#define PMU_CTRL_VOSSEL                                             PMU_CTRL_VOSSEL_Msk                                            /*!< VOS bit (Regulator voltage scaling output selection) */

/* Legacy define */
#define PMU_CTRL_PMODE                                              PMU_CTRL_VOSSEL

/*******************  Bit definition for PMU_CSTS register  ********************/
#define PMU_CSTS_WUEFLG_Pos                                         (0U)
#define PMU_CSTS_WUEFLG_Msk                                         (0x1UL << PMU_CSTS_WUEFLG_Pos)                                 /*!< 0x00000001 */
#define PMU_CSTS_WUEFLG                                             PMU_CSTS_WUEFLG_Msk                                            /*!< Wakeup Flag                                      */
#define PMU_CSTS_SBFLG_Pos                                          (1U)
#define PMU_CSTS_SBFLG_Msk                                          (0x1UL << PMU_CSTS_SBFLG_Pos)                                  /*!< 0x00000002 */
#define PMU_CSTS_SBFLG                                              PMU_CSTS_SBFLG_Msk                                             /*!< Standby Flag                                     */
#define PMU_CSTS_PVDOFLG_Pos                                        (2U)
#define PMU_CSTS_PVDOFLG_Msk                                        (0x1UL << PMU_CSTS_PVDOFLG_Pos)                                /*!< 0x00000004 */
#define PMU_CSTS_PVDOFLG                                            PMU_CSTS_PVDOFLG_Msk                                           /*!< PVD Output                                       */
#define PMU_CSTS_BKPRFLG_Pos                                        (3U)
#define PMU_CSTS_BKPRFLG_Msk                                        (0x1UL << PMU_CSTS_BKPRFLG_Pos)                                /*!< 0x00000008 */
#define PMU_CSTS_BKPRFLG                                            PMU_CSTS_BKPRFLG_Msk                                           /*!< Backup regulator ready                           */
#define PMU_CSTS_WKUPCFG_Pos                                        (8U)
#define PMU_CSTS_WKUPCFG_Msk                                        (0x1UL << PMU_CSTS_WKUPCFG_Pos)                                /*!< 0x00000100 */
#define PMU_CSTS_WKUPCFG                                            PMU_CSTS_WKUPCFG_Msk                                           /*!< Enable WKUP pin                                  */
#define PMU_CSTS_BKPREN_Pos                                         (9U)
#define PMU_CSTS_BKPREN_Msk                                         (0x1UL << PMU_CSTS_BKPREN_Pos)                                 /*!< 0x00000200 */
#define PMU_CSTS_BKPREN                                             PMU_CSTS_BKPREN_Msk                                            /*!< Backup regulator enable                          */
#define PMU_CSTS_VOSRFLG_Pos                                        (14U)
#define PMU_CSTS_VOSRFLG_Msk                                        (0x1UL << PMU_CSTS_VOSRFLG_Pos)                                /*!< 0x00004000 */
#define PMU_CSTS_VOSRFLG                                            PMU_CSTS_VOSRFLG_Msk                                           /*!< Regulator voltage scaling output selection ready */

/* Legacy define */
#define PMU_CSTS_REGRDY                                             PMU_CSTS_VOSRFLG

/******************************************************************************/
/*                                                                            */
/*                         Reset and Clock Control                            */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for RCM_CTRL register  ********************/
#define RCM_CTRL_HSIEN_Pos                                          (0U)
#define RCM_CTRL_HSIEN_Msk                                          (0x1UL << RCM_CTRL_HSIEN_Pos)                                  /*!< 0x00000001 */
#define RCM_CTRL_HSIEN                                              RCM_CTRL_HSIEN_Msk
#define RCM_CTRL_HSIRDYFLG_Pos                                      (1U)
#define RCM_CTRL_HSIRDYFLG_Msk                                      (0x1UL << RCM_CTRL_HSIRDYFLG_Pos)                              /*!< 0x00000002 */
#define RCM_CTRL_HSIRDYFLG                                          RCM_CTRL_HSIRDYFLG_Msk

#define RCM_CTRL_HSITRM_Pos                                         (3U)
#define RCM_CTRL_HSITRM_Msk                                         (0x1FUL << RCM_CTRL_HSITRM_Pos)                                /*!< 0x000000F8 */
#define RCM_CTRL_HSITRM                                             RCM_CTRL_HSITRM_Msk
#define RCM_CTRL_HSITRM_0                                           (0x01UL << RCM_CTRL_HSITRM_Pos)                                /*!< 0x00000008 */
#define RCM_CTRL_HSITRM_1                                           (0x02UL << RCM_CTRL_HSITRM_Pos)                                /*!< 0x00000010 */
#define RCM_CTRL_HSITRM_2                                           (0x04UL << RCM_CTRL_HSITRM_Pos)                                /*!< 0x00000020 */
#define RCM_CTRL_HSITRM_3                                           (0x08UL << RCM_CTRL_HSITRM_Pos)                                /*!< 0x00000040 */
#define RCM_CTRL_HSITRM_4                                           (0x10UL << RCM_CTRL_HSITRM_Pos)                                /*!< 0x00000080 */

#define RCM_CTRL_HSICAL_Pos                                         (8U)
#define RCM_CTRL_HSICAL_Msk                                         (0xFFUL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x0000FF00 */
#define RCM_CTRL_HSICAL                                             RCM_CTRL_HSICAL_Msk
#define RCM_CTRL_HSICAL_0                                           (0x01UL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x00000100 */
#define RCM_CTRL_HSICAL_1                                           (0x02UL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x00000200 */
#define RCM_CTRL_HSICAL_2                                           (0x04UL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x00000400 */
#define RCM_CTRL_HSICAL_3                                           (0x08UL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x00000800 */
#define RCM_CTRL_HSICAL_4                                           (0x10UL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x00001000 */
#define RCM_CTRL_HSICAL_5                                           (0x20UL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x00002000 */
#define RCM_CTRL_HSICAL_6                                           (0x40UL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x00004000 */
#define RCM_CTRL_HSICAL_7                                           (0x80UL << RCM_CTRL_HSICAL_Pos)                                /*!< 0x00008000 */

#define RCM_CTRL_HSEEN_Pos                                          (16U)
#define RCM_CTRL_HSEEN_Msk                                          (0x1UL << RCM_CTRL_HSEEN_Pos)                                  /*!< 0x00010000 */
#define RCM_CTRL_HSEEN                                              RCM_CTRL_HSEEN_Msk
#define RCM_CTRL_HSERDYFLG_Pos                                      (17U)
#define RCM_CTRL_HSERDYFLG_Msk                                      (0x1UL << RCM_CTRL_HSERDYFLG_Pos)                              /*!< 0x00020000 */
#define RCM_CTRL_HSERDYFLG                                          RCM_CTRL_HSERDYFLG_Msk
#define RCM_CTRL_HSEBCFG_Pos                                        (18U)
#define RCM_CTRL_HSEBCFG_Msk                                        (0x1UL << RCM_CTRL_HSEBCFG_Pos)                                /*!< 0x00040000 */
#define RCM_CTRL_HSEBCFG                                            RCM_CTRL_HSEBCFG_Msk
#define RCM_CTRL_CSSEN_Pos                                          (19U)
#define RCM_CTRL_CSSEN_Msk                                          (0x1UL << RCM_CTRL_CSSEN_Pos)                                  /*!< 0x00080000 */
#define RCM_CTRL_CSSEN                                              RCM_CTRL_CSSEN_Msk
#define RCM_CTRL_PLL1EN_Pos                                         (24U)
#define RCM_CTRL_PLL1EN_Msk                                         (0x1UL << RCM_CTRL_PLL1EN_Pos)                                 /*!< 0x01000000 */
#define RCM_CTRL_PLL1EN                                             RCM_CTRL_PLL1EN_Msk
#define RCM_CTRL_PLL1RDYFLG_Pos                                     (25U)
#define RCM_CTRL_PLL1RDYFLG_Msk                                     (0x1UL << RCM_CTRL_PLL1RDYFLG_Pos)                             /*!< 0x02000000 */
#define RCM_CTRL_PLL1RDYFLG                                         RCM_CTRL_PLL1RDYFLG_Msk
/*
 * @brief Specific device feature definitions (not present on all devices in the APM32F4 serie)
 */
#define RCM_PLLI2S_SUPPORT                                                                                                         /*!< Support PLLI2S oscillator */

#define RCM_CTRL_PLL2EN_Pos                                         (26U)
#define RCM_CTRL_PLL2EN_Msk                                         (0x1UL << RCM_CTRL_PLL2EN_Pos)                                 /*!< 0x04000000 */
#define RCM_CTRL_PLL2EN                                             RCM_CTRL_PLL2EN_Msk
#define RCM_CTRL_PLL2RDYFLG_Pos                                     (27U)
#define RCM_CTRL_PLL2RDYFLG_Msk                                     (0x1UL << RCM_CTRL_PLL2RDYFLG_Pos)                             /*!< 0x08000000 */
#define RCM_CTRL_PLL2RDYFLG                                         RCM_CTRL_PLL2RDYFLG_Msk

/********************  Bit definition for RCM_PLL1CFG register  ***************/
#define RCM_PLL1CFG_PLLB_Pos                                        (0U)
#define RCM_PLL1CFG_PLLB_Msk                                        (0x3FUL << RCM_PLL1CFG_PLLB_Pos)                               /*!< 0x0000003F */
#define RCM_PLL1CFG_PLLB                                            RCM_PLL1CFG_PLLB_Msk
#define RCM_PLL1CFG_PLLB_0                                          (0x01UL << RCM_PLL1CFG_PLLB_Pos)                               /*!< 0x00000001 */
#define RCM_PLL1CFG_PLLB_1                                          (0x02UL << RCM_PLL1CFG_PLLB_Pos)                               /*!< 0x00000002 */
#define RCM_PLL1CFG_PLLB_2                                          (0x04UL << RCM_PLL1CFG_PLLB_Pos)                               /*!< 0x00000004 */
#define RCM_PLL1CFG_PLLB_3                                          (0x08UL << RCM_PLL1CFG_PLLB_Pos)                               /*!< 0x00000008 */
#define RCM_PLL1CFG_PLLB_4                                          (0x10UL << RCM_PLL1CFG_PLLB_Pos)                               /*!< 0x00000010 */
#define RCM_PLL1CFG_PLLB_5                                          (0x20UL << RCM_PLL1CFG_PLLB_Pos)                               /*!< 0x00000020 */

#define RCM_PLL1CFG_PLL1A_Pos                                       (6U)
#define RCM_PLL1CFG_PLL1A_Msk                                       (0x1FFUL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00007FC0 */
#define RCM_PLL1CFG_PLL1A                                           RCM_PLL1CFG_PLL1A_Msk
#define RCM_PLL1CFG_PLL1A_0                                         (0x001UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00000040 */
#define RCM_PLL1CFG_PLL1A_1                                         (0x002UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00000080 */
#define RCM_PLL1CFG_PLL1A_2                                         (0x004UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00000100 */
#define RCM_PLL1CFG_PLL1A_3                                         (0x008UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00000200 */
#define RCM_PLL1CFG_PLL1A_4                                         (0x010UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00000400 */
#define RCM_PLL1CFG_PLL1A_5                                         (0x020UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00000800 */
#define RCM_PLL1CFG_PLL1A_6                                         (0x040UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00001000 */
#define RCM_PLL1CFG_PLL1A_7                                         (0x080UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00002000 */
#define RCM_PLL1CFG_PLL1A_8                                         (0x100UL << RCM_PLL1CFG_PLL1A_Pos)                             /*!< 0x00004000 */

#define RCM_PLL1CFG_PLL1C_Pos                                       (16U)
#define RCM_PLL1CFG_PLL1C_Msk                                       (0x3UL << RCM_PLL1CFG_PLL1C_Pos)                               /*!< 0x00030000 */
#define RCM_PLL1CFG_PLL1C                                           RCM_PLL1CFG_PLL1C_Msk
#define RCM_PLL1CFG_PLL1C_0                                         (0x1UL << RCM_PLL1CFG_PLL1C_Pos)                               /*!< 0x00010000 */
#define RCM_PLL1CFG_PLL1C_1                                         (0x2UL << RCM_PLL1CFG_PLL1C_Pos)                               /*!< 0x00020000 */

#define RCM_PLL1CFG_PLL1CLKS_Pos                                    (22U)
#define RCM_PLL1CFG_PLL1CLKS_Msk                                    (0x1UL << RCM_PLL1CFG_PLL1CLKS_Pos)                            /*!< 0x00400000 */
#define RCM_PLL1CFG_PLL1CLKS                                        RCM_PLL1CFG_PLL1CLKS_Msk
#define RCM_PLL1CFG_PLL1CLKS_HSE_Pos                                (22U)
#define RCM_PLL1CFG_PLL1CLKS_HSE_Msk                                (0x1UL << RCM_PLL1CFG_PLL1CLKS_HSE_Pos)                        /*!< 0x00400000 */
#define RCM_PLL1CFG_PLL1CLKS_HSE                                    RCM_PLL1CFG_PLL1CLKS_HSE_Msk
#define RCM_PLL1CFG_PLL1CLKS_HSI                                    0x00000000U

#define RCM_PLL1CFG_PLLD_Pos                                        (24U)
#define RCM_PLL1CFG_PLLD_Msk                                        (0xFUL << RCM_PLL1CFG_PLLD_Pos)                                /*!< 0x0F000000 */
#define RCM_PLL1CFG_PLLD                                            RCM_PLL1CFG_PLLD_Msk
#define RCM_PLL1CFG_PLLD_0                                          (0x1UL << RCM_PLL1CFG_PLLD_Pos)                                /*!< 0x01000000 */
#define RCM_PLL1CFG_PLLD_1                                          (0x2UL << RCM_PLL1CFG_PLLD_Pos)                                /*!< 0x02000000 */
#define RCM_PLL1CFG_PLLD_2                                          (0x4UL << RCM_PLL1CFG_PLLD_Pos)                                /*!< 0x04000000 */
#define RCM_PLL1CFG_PLLD_3                                          (0x8UL << RCM_PLL1CFG_PLLD_Pos)                                /*!< 0x08000000 */


/********************  Bit definition for RCM_CFG register  ******************/
/*!< SW configuration */
#define RCM_CFG_SCLKSEL_Pos                                         (0U)
#define RCM_CFG_SCLKSEL_Msk                                         (0x3UL << RCM_CFG_SCLKSEL_Pos)                                 /*!< 0x00000003 */
#define RCM_CFG_SCLKSEL                                             RCM_CFG_SCLKSEL_Msk                                            /*!< SW[1:0] bits (System clock Switch) */
#define RCM_CFG_SCLKSEL_0                                           (0x1UL << RCM_CFG_SCLKSEL_Pos)                                 /*!< 0x00000001 */
#define RCM_CFG_SCLKSEL_1                                           (0x2UL << RCM_CFG_SCLKSEL_Pos)                                 /*!< 0x00000002 */

#define RCM_CFG_SCLKSEL_HSI                                         0x00000000U                                                    /*!< HSI selected as system clock */
#define RCM_CFG_SCLKSEL_HSE                                         0x00000001U                                                    /*!< HSE selected as system clock */
#define RCM_CFG_SCLKSEL_PLL                                         0x00000002U                                                    /*!< PLL selected as system clock */

/*!< SWS configuration */
#define RCM_CFG_SCLKSWSTS_Pos                                       (2U)
#define RCM_CFG_SCLKSWSTS_Msk                                       (0x3UL << RCM_CFG_SCLKSWSTS_Pos)                               /*!< 0x0000000C */
#define RCM_CFG_SCLKSWSTS                                           RCM_CFG_SCLKSWSTS_Msk                                          /*!< SWS[1:0] bits (System Clock Switch Status) */
#define RCM_CFG_SCLKSWSTS_0                                         (0x1UL << RCM_CFG_SCLKSWSTS_Pos)                               /*!< 0x00000004 */
#define RCM_CFG_SCLKSWSTS_1                                         (0x2UL << RCM_CFG_SCLKSWSTS_Pos)                               /*!< 0x00000008 */

#define RCM_CFG_SCLKSWSTS_HSI                                       0x00000000U                                                    /*!< HSI oscillator used as system clock        */
#define RCM_CFG_SCLKSWSTS_HSE                                       0x00000004U                                                    /*!< HSE oscillator used as system clock        */
#define RCM_CFG_SCLKSWSTS_PLL                                       0x00000008U                                                    /*!< PLL used as system clock                   */

/*!< HPRE configuration */
#define RCM_CFG_AHBPSC_Pos                                          (4U)
#define RCM_CFG_AHBPSC_Msk                                          (0xFUL << RCM_CFG_AHBPSC_Pos)                                  /*!< 0x000000F0 */
#define RCM_CFG_AHBPSC                                              RCM_CFG_AHBPSC_Msk                                             /*!< HPRE[3:0] bits (AHB prescaler) */
#define RCM_CFG_AHBPSC_0                                            (0x1UL << RCM_CFG_AHBPSC_Pos)                                  /*!< 0x00000010 */
#define RCM_CFG_AHBPSC_1                                            (0x2UL << RCM_CFG_AHBPSC_Pos)                                  /*!< 0x00000020 */
#define RCM_CFG_AHBPSC_2                                            (0x4UL << RCM_CFG_AHBPSC_Pos)                                  /*!< 0x00000040 */
#define RCM_CFG_AHBPSC_3                                            (0x8UL << RCM_CFG_AHBPSC_Pos)                                  /*!< 0x00000080 */

#define RCM_CFG_AHBPSC_DIV1                                         0x00000000U                                                    /*!< SYSCLK not divided    */
#define RCM_CFG_AHBPSC_DIV2                                         0x00000080U                                                    /*!< SYSCLK divided by 2   */
#define RCM_CFG_AHBPSC_DIV4                                         0x00000090U                                                    /*!< SYSCLK divided by 4   */
#define RCM_CFG_AHBPSC_DIV8                                         0x000000A0U                                                    /*!< SYSCLK divided by 8   */
#define RCM_CFG_AHBPSC_DIV16                                        0x000000B0U                                                    /*!< SYSCLK divided by 16  */
#define RCM_CFG_AHBPSC_DIV64                                        0x000000C0U                                                    /*!< SYSCLK divided by 64  */
#define RCM_CFG_AHBPSC_DIV128                                       0x000000D0U                                                    /*!< SYSCLK divided by 128 */
#define RCM_CFG_AHBPSC_DIV256                                       0x000000E0U                                                    /*!< SYSCLK divided by 256 */
#define RCM_CFG_AHBPSC_DIV512                                       0x000000F0U                                                    /*!< SYSCLK divided by 512 */

#define RCM_CFG_SDRAMPSC_Pos                                        (8U)
#define RCM_CFG_SDRAMPSC_Msk                                        (0x3UL << RCM_CFG_SDRAMPSC_Pos)
#define RCM_CFG_SDRAMPSC                                            RCM_CFG_SDRAMPSC_Msk
#define RCM_CFG_SDRAMPSC_0                                          (0x1UL << RCM_CFG_SDRAMPSC_Pos)
#define RCM_CFG_SDRAMPSC_1                                          (0x2UL << RCM_CFG_SDRAMPSC_Pos)

/*!< PPRE1 configuration */
#define RCM_CFG_APB1PSC_Pos                                         (10U)
#define RCM_CFG_APB1PSC_Msk                                         (0x7UL << RCM_CFG_APB1PSC_Pos)                                 /*!< 0x00001C00 */
#define RCM_CFG_APB1PSC                                             RCM_CFG_APB1PSC_Msk                                            /*!< PRE1[2:0] bits (APB1 prescaler) */
#define RCM_CFG_APB1PSC_0                                           (0x1UL << RCM_CFG_APB1PSC_Pos)                                 /*!< 0x00000400 */
#define RCM_CFG_APB1PSC_1                                           (0x2UL << RCM_CFG_APB1PSC_Pos)                                 /*!< 0x00000800 */
#define RCM_CFG_APB1PSC_2                                           (0x4UL << RCM_CFG_APB1PSC_Pos)                                 /*!< 0x00001000 */

#define RCM_CFG_APB1PSC_DIV1                                        0x00000000U                                                    /*!< HCLK not divided   */
#define RCM_CFG_APB1PSC_DIV2                                        0x00001000U                                                    /*!< HCLK divided by 2  */
#define RCM_CFG_APB1PSC_DIV4                                        0x00001400U                                                    /*!< HCLK divided by 4  */
#define RCM_CFG_APB1PSC_DIV8                                        0x00001800U                                                    /*!< HCLK divided by 8  */
#define RCM_CFG_APB1PSC_DIV16                                       0x00001C00U                                                    /*!< HCLK divided by 16 */

/*!< PPRE2 configuration */
#define RCM_CFG_APB2PSC_Pos                                         (13U)
#define RCM_CFG_APB2PSC_Msk                                         (0x7UL << RCM_CFG_APB2PSC_Pos)                                 /*!< 0x0000E000 */
#define RCM_CFG_APB2PSC                                             RCM_CFG_APB2PSC_Msk                                            /*!< PRE2[2:0] bits (APB2 prescaler) */
#define RCM_CFG_APB2PSC_0                                           (0x1UL << RCM_CFG_APB2PSC_Pos)                                 /*!< 0x00002000 */
#define RCM_CFG_APB2PSC_1                                           (0x2UL << RCM_CFG_APB2PSC_Pos)                                 /*!< 0x00004000 */
#define RCM_CFG_APB2PSC_2                                           (0x4UL << RCM_CFG_APB2PSC_Pos)                                 /*!< 0x00008000 */

#define RCM_CFG_APB2PSC_DIV1                                        0x00000000U                                                    /*!< HCLK not divided   */
#define RCM_CFG_APB2PSC_DIV2                                        0x00008000U                                                    /*!< HCLK divided by 2  */
#define RCM_CFG_APB2PSC_DIV4                                        0x0000A000U                                                    /*!< HCLK divided by 4  */
#define RCM_CFG_APB2PSC_DIV8                                        0x0000C000U                                                    /*!< HCLK divided by 8  */
#define RCM_CFG_APB2PSC_DIV16                                       0x0000E000U                                                    /*!< HCLK divided by 16 */

/*!< RTCPRE configuration */
#define RCM_CFG_RTCPSC_Pos                                          (16U)
#define RCM_CFG_RTCPSC_Msk                                          (0x1FUL << RCM_CFG_RTCPSC_Pos)                                 /*!< 0x001F0000 */
#define RCM_CFG_RTCPSC                                              RCM_CFG_RTCPSC_Msk
#define RCM_CFG_RTCPSC_0                                            (0x01UL << RCM_CFG_RTCPSC_Pos)                                 /*!< 0x00010000 */
#define RCM_CFG_RTCPSC_1                                            (0x02UL << RCM_CFG_RTCPSC_Pos)                                 /*!< 0x00020000 */
#define RCM_CFG_RTCPSC_2                                            (0x04UL << RCM_CFG_RTCPSC_Pos)                                 /*!< 0x00040000 */
#define RCM_CFG_RTCPSC_3                                            (0x08UL << RCM_CFG_RTCPSC_Pos)                                 /*!< 0x00080000 */
#define RCM_CFG_RTCPSC_4                                            (0x10UL << RCM_CFG_RTCPSC_Pos)                                 /*!< 0x00100000 */

/*!< MCO1 configuration */
#define RCM_CFG_MCO1SEL_Pos                                         (21U)
#define RCM_CFG_MCO1SEL_Msk                                         (0x3UL << RCM_CFG_MCO1SEL_Pos)                                 /*!< 0x00600000 */
#define RCM_CFG_MCO1SEL                                             RCM_CFG_MCO1SEL_Msk
#define RCM_CFG_MCO1SEL_0                                           (0x1UL << RCM_CFG_MCO1SEL_Pos)                                 /*!< 0x00200000 */
#define RCM_CFG_MCO1SEL_1                                           (0x2UL << RCM_CFG_MCO1SEL_Pos)                                 /*!< 0x00400000 */

#define RCM_CFG_I2SSEL_Pos                                          (23U)
#define RCM_CFG_I2SSEL_Msk                                          (0x1UL << RCM_CFG_I2SSEL_Pos)                                  /*!< 0x00800000 */
#define RCM_CFG_I2SSEL                                              RCM_CFG_I2SSEL_Msk

#define RCM_CFG_MCO1PSC_Pos                                         (24U)
#define RCM_CFG_MCO1PSC_Msk                                         (0x7UL << RCM_CFG_MCO1PSC_Pos)                                 /*!< 0x07000000 */
#define RCM_CFG_MCO1PSC                                             RCM_CFG_MCO1PSC_Msk
#define RCM_CFG_MCO1PSC_0                                           (0x1UL << RCM_CFG_MCO1PSC_Pos)                                 /*!< 0x01000000 */
#define RCM_CFG_MCO1PSC_1                                           (0x2UL << RCM_CFG_MCO1PSC_Pos)                                 /*!< 0x02000000 */
#define RCM_CFG_MCO1PSC_2                                           (0x4UL << RCM_CFG_MCO1PSC_Pos)                                 /*!< 0x04000000 */

#define RCM_CFG_MCO2PSC_Pos                                         (27U)
#define RCM_CFG_MCO2PSC_Msk                                         (0x7UL << RCM_CFG_MCO2PSC_Pos)                                 /*!< 0x38000000 */
#define RCM_CFG_MCO2PSC                                             RCM_CFG_MCO2PSC_Msk
#define RCM_CFG_MCO2PSC_0                                           (0x1UL << RCM_CFG_MCO2PSC_Pos)                                 /*!< 0x08000000 */
#define RCM_CFG_MCO2PSC_1                                           (0x2UL << RCM_CFG_MCO2PSC_Pos)                                 /*!< 0x10000000 */
#define RCM_CFG_MCO2PSC_2                                           (0x4UL << RCM_CFG_MCO2PSC_Pos)                                 /*!< 0x20000000 */

#define RCM_CFG_MCO2SEL_Pos                                         (30U)
#define RCM_CFG_MCO2SEL_Msk                                         (0x3UL << RCM_CFG_MCO2SEL_Pos)                                 /*!< 0xC0000000 */
#define RCM_CFG_MCO2SEL                                             RCM_CFG_MCO2SEL_Msk
#define RCM_CFG_MCO2SEL_0                                           (0x1UL << RCM_CFG_MCO2SEL_Pos)                                 /*!< 0x40000000 */
#define RCM_CFG_MCO2SEL_1                                           (0x2UL << RCM_CFG_MCO2SEL_Pos)                                 /*!< 0x80000000 */

/********************  Bit definition for RCM_INT register  *******************/
#define RCM_INT_LSIRDYFLG_Pos                                       (0U)
#define RCM_INT_LSIRDYFLG_Msk                                       (0x1UL << RCM_INT_LSIRDYFLG_Pos)                               /*!< 0x00000001 */
#define RCM_INT_LSIRDYFLG                                           RCM_INT_LSIRDYFLG_Msk
#define RCM_INT_LSERDYFLG_Pos                                       (1U)
#define RCM_INT_LSERDYFLG_Msk                                       (0x1UL << RCM_INT_LSERDYFLG_Pos)                               /*!< 0x00000002 */
#define RCM_INT_LSERDYFLG                                           RCM_INT_LSERDYFLG_Msk
#define RCM_INT_HSIRDYFLG_Pos                                       (2U)
#define RCM_INT_HSIRDYFLG_Msk                                       (0x1UL << RCM_INT_HSIRDYFLG_Pos)                               /*!< 0x00000004 */
#define RCM_INT_HSIRDYFLG                                           RCM_INT_HSIRDYFLG_Msk
#define RCM_INT_HSERDYFLG_Pos                                       (3U)
#define RCM_INT_HSERDYFLG_Msk                                       (0x1UL << RCM_INT_HSERDYFLG_Pos)                               /*!< 0x00000008 */
#define RCM_INT_HSERDYFLG                                           RCM_INT_HSERDYFLG_Msk
#define RCM_INT_PLL1RDYFLG_Pos                                      (4U)
#define RCM_INT_PLL1RDYFLG_Msk                                      (0x1UL << RCM_INT_PLL1RDYFLG_Pos)                              /*!< 0x00000010 */
#define RCM_INT_PLL1RDYFLG                                          RCM_INT_PLL1RDYFLG_Msk
#define RCM_INT_PLL2RDYFLG_Pos                                      (5U)
#define RCM_INT_PLL2RDYFLG_Msk                                      (0x1UL << RCM_INT_PLL2RDYFLG_Pos)                              /*!< 0x00000020 */
#define RCM_INT_PLL2RDYFLG                                          RCM_INT_PLL2RDYFLG_Msk

#define RCM_INT_CSSFLG_Pos                                          (7U)
#define RCM_INT_CSSFLG_Msk                                          (0x1UL << RCM_INT_CSSFLG_Pos)                                  /*!< 0x00000080 */
#define RCM_INT_CSSFLG                                              RCM_INT_CSSFLG_Msk
#define RCM_INT_LSIRDYEN_Pos                                        (8U)
#define RCM_INT_LSIRDYEN_Msk                                        (0x1UL << RCM_INT_LSIRDYEN_Pos)                                /*!< 0x00000100 */
#define RCM_INT_LSIRDYEN                                            RCM_INT_LSIRDYEN_Msk
#define RCM_INT_LSERDYEN_Pos                                        (9U)
#define RCM_INT_LSERDYEN_Msk                                        (0x1UL << RCM_INT_LSERDYEN_Pos)                                /*!< 0x00000200 */
#define RCM_INT_LSERDYEN                                            RCM_INT_LSERDYEN_Msk
#define RCM_INT_HSIRDYEN_Pos                                        (10U)
#define RCM_INT_HSIRDYEN_Msk                                        (0x1UL << RCM_INT_HSIRDYEN_Pos)                                /*!< 0x00000400 */
#define RCM_INT_HSIRDYEN                                            RCM_INT_HSIRDYEN_Msk
#define RCM_INT_HSERDYEN_Pos                                        (11U)
#define RCM_INT_HSERDYEN_Msk                                        (0x1UL << RCM_INT_HSERDYEN_Pos)                                /*!< 0x00000800 */
#define RCM_INT_HSERDYEN                                            RCM_INT_HSERDYEN_Msk
#define RCM_INT_PLL1RDYEN_Pos                                       (12U)
#define RCM_INT_PLL1RDYEN_Msk                                       (0x1UL << RCM_INT_PLL1RDYEN_Pos)                               /*!< 0x00001000 */
#define RCM_INT_PLL1RDYEN                                           RCM_INT_PLL1RDYEN_Msk
#define RCM_INT_PLL2RDYEN_Pos                                       (13U)
#define RCM_INT_PLL2RDYEN_Msk                                       (0x1UL << RCM_INT_PLL2RDYEN_Pos)                               /*!< 0x00002000 */
#define RCM_INT_PLL2RDYEN                                           RCM_INT_PLL2RDYEN_Msk

#define RCM_INT_LSIRDYCLR_Pos                                       (16U)
#define RCM_INT_LSIRDYCLR_Msk                                       (0x1UL << RCM_INT_LSIRDYCLR_Pos)                               /*!< 0x00010000 */
#define RCM_INT_LSIRDYCLR                                           RCM_INT_LSIRDYCLR_Msk
#define RCM_INT_LSERDYCLR_Pos                                       (17U)
#define RCM_INT_LSERDYCLR_Msk                                       (0x1UL << RCM_INT_LSERDYCLR_Pos)                               /*!< 0x00020000 */
#define RCM_INT_LSERDYCLR                                           RCM_INT_LSERDYCLR_Msk
#define RCM_INT_HSIRDYCLR_Pos                                       (18U)
#define RCM_INT_HSIRDYCLR_Msk                                       (0x1UL << RCM_INT_HSIRDYCLR_Pos)                               /*!< 0x00040000 */
#define RCM_INT_HSIRDYCLR                                           RCM_INT_HSIRDYCLR_Msk
#define RCM_INT_HSERDYCLR_Pos                                       (19U)
#define RCM_INT_HSERDYCLR_Msk                                       (0x1UL << RCM_INT_HSERDYCLR_Pos)                               /*!< 0x00080000 */
#define RCM_INT_HSERDYCLR                                           RCM_INT_HSERDYCLR_Msk
#define RCM_INT_PLL1RDYCLR_Pos                                      (20U)
#define RCM_INT_PLL1RDYCLR_Msk                                      (0x1UL << RCM_INT_PLL1RDYCLR_Pos)                              /*!< 0x00100000 */
#define RCM_INT_PLL1RDYCLR                                          RCM_INT_PLL1RDYCLR_Msk
#define RCM_INT_PLL2RDYCLR_Pos                                      (21U)
#define RCM_INT_PLL2RDYCLR_Msk                                      (0x1UL << RCM_INT_PLL2RDYCLR_Pos)                              /*!< 0x00200000 */
#define RCM_INT_PLL2RDYCLR                                          RCM_INT_PLL2RDYCLR_Msk

#define RCM_INT_CSSCLR_Pos                                          (23U)
#define RCM_INT_CSSCLR_Msk                                          (0x1UL << RCM_INT_CSSCLR_Pos)                                  /*!< 0x00800000 */
#define RCM_INT_CSSCLR                                              RCM_INT_CSSCLR_Msk

/********************  Bit definition for RCM_AHB1RST register  **************/
#define RCM_AHB1RST_PARST_Pos                                       (0U)
#define RCM_AHB1RST_PARST_Msk                                       (0x1UL << RCM_AHB1RST_PARST_Pos)                               /*!< 0x00000001 */
#define RCM_AHB1RST_PARST                                           RCM_AHB1RST_PARST_Msk
#define RCM_AHB1RST_PBRST_Pos                                       (1U)
#define RCM_AHB1RST_PBRST_Msk                                       (0x1UL << RCM_AHB1RST_PBRST_Pos)                               /*!< 0x00000002 */
#define RCM_AHB1RST_PBRST                                           RCM_AHB1RST_PBRST_Msk
#define RCM_AHB1RST_PCRST_Pos                                       (2U)
#define RCM_AHB1RST_PCRST_Msk                                       (0x1UL << RCM_AHB1RST_PCRST_Pos)                               /*!< 0x00000004 */
#define RCM_AHB1RST_PCRST                                           RCM_AHB1RST_PCRST_Msk
#define RCM_AHB1RST_PDRST_Pos                                       (3U)
#define RCM_AHB1RST_PDRST_Msk                                       (0x1UL << RCM_AHB1RST_PDRST_Pos)                               /*!< 0x00000008 */
#define RCM_AHB1RST_PDRST                                           RCM_AHB1RST_PDRST_Msk
#define RCM_AHB1RST_PERST_Pos                                       (4U)
#define RCM_AHB1RST_PERST_Msk                                       (0x1UL << RCM_AHB1RST_PERST_Pos)                               /*!< 0x00000010 */
#define RCM_AHB1RST_PERST                                           RCM_AHB1RST_PERST_Msk
#define RCM_AHB1RST_PFRST_Pos                                       (5U)
#define RCM_AHB1RST_PFRST_Msk                                       (0x1UL << RCM_AHB1RST_PFRST_Pos)                               /*!< 0x00000020 */
#define RCM_AHB1RST_PFRST                                           RCM_AHB1RST_PFRST_Msk
#define RCM_AHB1RST_PGRST_Pos                                       (6U)
#define RCM_AHB1RST_PGRST_Msk                                       (0x1UL << RCM_AHB1RST_PGRST_Pos)                               /*!< 0x00000040 */
#define RCM_AHB1RST_PGRST                                           RCM_AHB1RST_PGRST_Msk
#define RCM_AHB1RST_PHRST_Pos                                       (7U)
#define RCM_AHB1RST_PHRST_Msk                                       (0x1UL << RCM_AHB1RST_PHRST_Pos)                               /*!< 0x00000080 */
#define RCM_AHB1RST_PHRST                                           RCM_AHB1RST_PHRST_Msk
#define RCM_AHB1RST_PIRST_Pos                                       (8U)
#define RCM_AHB1RST_PIRST_Msk                                       (0x1UL << RCM_AHB1RST_PIRST_Pos)                               /*!< 0x00000100 */
#define RCM_AHB1RST_PIRST                                           RCM_AHB1RST_PIRST_Msk
#define RCM_AHB1RST_CRCRST_Pos                                      (12U)
#define RCM_AHB1RST_CRCRST_Msk                                      (0x1UL << RCM_AHB1RST_CRCRST_Pos)                              /*!< 0x00001000 */
#define RCM_AHB1RST_CRCRST                                          RCM_AHB1RST_CRCRST_Msk
#define RCM_AHB1RST_DMA1RST_Pos                                     (21U)
#define RCM_AHB1RST_DMA1RST_Msk                                     (0x1UL << RCM_AHB1RST_DMA1RST_Pos)                             /*!< 0x00200000 */
#define RCM_AHB1RST_DMA1RST                                         RCM_AHB1RST_DMA1RST_Msk
#define RCM_AHB1RST_DMA2RST_Pos                                     (22U)
#define RCM_AHB1RST_DMA2RST_Msk                                     (0x1UL << RCM_AHB1RST_DMA2RST_Pos)                             /*!< 0x00400000 */
#define RCM_AHB1RST_DMA2RST                                         RCM_AHB1RST_DMA2RST_Msk
#define RCM_AHB1RST_ETHRST_Pos                                      (25U)
#define RCM_AHB1RST_ETHRST_Msk                                      (0x1UL << RCM_AHB1RST_ETHRST_Pos)                              /*!< 0x02000000 */
#define RCM_AHB1RST_ETHRST                                          RCM_AHB1RST_ETHRST_Msk
#define RCM_AHB1RST_OTGHS1RST_Pos                                   (29U)
#define RCM_AHB1RST_OTGHS1RST_Msk                                   (0x1UL << RCM_AHB1RST_OTGHS1RST_Pos)                           /*!< 0x20000000 */
#define RCM_AHB1RST_OTGHS1RST                                       RCM_AHB1RST_OTGHS1RST_Msk

/********************  Bit definition for RCM_AHB2RST register  **************/
#define RCM_AHB2RST_DCIRST_Pos                                      (0U)
#define RCM_AHB2RST_DCIRST_Msk                                      (0x1UL << RCM_AHB2RST_DCIRST_Pos)                              /*!< 0x00000001 */
#define RCM_AHB2RST_DCIRST                                          RCM_AHB2RST_DCIRST_Msk
#define RCM_AHB2RST_FPURST_Pos                                      (1U)
#define RCM_AHB2RST_FPURST_Msk                                      (0x1UL << RCM_AHB2RST_FPURST_Pos)                              /*!< 0x00000002 */
#define RCM_AHB2RST_FPURST                                          RCM_AHB2RST_FPURST_Msk
#define RCM_AHB2RST_BNRST_Pos                                       (2U)
#define RCM_AHB2RST_BNRST_Msk                                       (0x1UL << RCM_AHB2RST_BNRST_Pos)                               /*!< 0x00000004 */
#define RCM_AHB2RST_BNRST                                           RCM_AHB2RST_BNRST_Msk
#define RCM_AHB2RST_SMRST_Pos                                       (3U)
#define RCM_AHB2RST_SMRST_Msk                                       (0x1UL << RCM_AHB2RST_SMRST_Pos)                               /*!< 0x00000008 */
#define RCM_AHB2RST_SMRST                                           RCM_AHB2RST_SMRST_Msk
#define RCM_AHB2RST_RNGRST_Pos                                      (6U)
#define RCM_AHB2RST_RNGRST_Msk                                      (0x1UL << RCM_AHB2RST_RNGRST_Pos)                              /*!< 0x00000040 */
#define RCM_AHB2RST_RNGRST                                          RCM_AHB2RST_RNGRST_Msk
#define RCM_AHB2RST_OTGFSRST_Pos                                    (7U)
#define RCM_AHB2RST_OTGFSRST_Msk                                    (0x1UL << RCM_AHB2RST_OTGFSRST_Pos)                            /*!< 0x00000080 */
#define RCM_AHB2RST_OTGFSRST                                        RCM_AHB2RST_OTGFSRST_Msk
/********************  Bit definition for RCM_AHB3RST register  **************/
#define RCM_AHB3RST_EMMCRST_Pos                                     (0U)
#define RCM_AHB3RST_EMMCRST_Msk                                     (0x1UL << RCM_AHB3RST_EMMCRST_Pos)                             /*!< 0x00000001 */
#define RCM_AHB3RST_EMMCRST                                         RCM_AHB3RST_EMMCRST_Msk


/********************  Bit definition for RCM_APB1RST register  **************/
#define RCM_APB1RST_TMR2RST_Pos                                     (0U)
#define RCM_APB1RST_TMR2RST_Msk                                     (0x1UL << RCM_APB1RST_TMR2RST_Pos)                             /*!< 0x00000001 */
#define RCM_APB1RST_TMR2RST                                         RCM_APB1RST_TMR2RST_Msk
#define RCM_APB1RST_TMR3RST_Pos                                     (1U)
#define RCM_APB1RST_TMR3RST_Msk                                     (0x1UL << RCM_APB1RST_TMR3RST_Pos)                             /*!< 0x00000002 */
#define RCM_APB1RST_TMR3RST                                         RCM_APB1RST_TMR3RST_Msk
#define RCM_APB1RST_TMR4RST_Pos                                     (2U)
#define RCM_APB1RST_TMR4RST_Msk                                     (0x1UL << RCM_APB1RST_TMR4RST_Pos)                             /*!< 0x00000004 */
#define RCM_APB1RST_TMR4RST                                         RCM_APB1RST_TMR4RST_Msk
#define RCM_APB1RST_TMR5RST_Pos                                     (3U)
#define RCM_APB1RST_TMR5RST_Msk                                     (0x1UL << RCM_APB1RST_TMR5RST_Pos)                             /*!< 0x00000008 */
#define RCM_APB1RST_TMR5RST                                         RCM_APB1RST_TMR5RST_Msk
#define RCM_APB1RST_TMR6RST_Pos                                     (4U)
#define RCM_APB1RST_TMR6RST_Msk                                     (0x1UL << RCM_APB1RST_TMR6RST_Pos)                             /*!< 0x00000010 */
#define RCM_APB1RST_TMR6RST                                         RCM_APB1RST_TMR6RST_Msk
#define RCM_APB1RST_TMR7RST_Pos                                     (5U)
#define RCM_APB1RST_TMR7RST_Msk                                     (0x1UL << RCM_APB1RST_TMR7RST_Pos)                             /*!< 0x00000020 */
#define RCM_APB1RST_TMR7RST                                         RCM_APB1RST_TMR7RST_Msk
#define RCM_APB1RST_TMR12RST_Pos                                    (6U)
#define RCM_APB1RST_TMR12RST_Msk                                    (0x1UL << RCM_APB1RST_TMR12RST_Pos)                            /*!< 0x00000040 */
#define RCM_APB1RST_TMR12RST                                        RCM_APB1RST_TMR12RST_Msk
#define RCM_APB1RST_TMR13RST_Pos                                    (7U)
#define RCM_APB1RST_TMR13RST_Msk                                    (0x1UL << RCM_APB1RST_TMR13RST_Pos)                            /*!< 0x00000080 */
#define RCM_APB1RST_TMR13RST                                        RCM_APB1RST_TMR13RST_Msk
#define RCM_APB1RST_TMR14RST_Pos                                    (8U)
#define RCM_APB1RST_TMR14RST_Msk                                    (0x1UL << RCM_APB1RST_TMR14RST_Pos)                            /*!< 0x00000100 */
#define RCM_APB1RST_TMR14RST                                        RCM_APB1RST_TMR14RST_Msk
#define RCM_APB1RST_WWDTRST_Pos                                     (11U)
#define RCM_APB1RST_WWDTRST_Msk                                     (0x1UL << RCM_APB1RST_WWDTRST_Pos)                             /*!< 0x00000800 */
#define RCM_APB1RST_WWDTRST                                         RCM_APB1RST_WWDTRST_Msk
#define RCM_APB1RST_SPI2RST_Pos                                     (14U)
#define RCM_APB1RST_SPI2RST_Msk                                     (0x1UL << RCM_APB1RST_SPI2RST_Pos)                             /*!< 0x00004000 */
#define RCM_APB1RST_SPI2RST                                         RCM_APB1RST_SPI2RST_Msk
#define RCM_APB1RST_SPI3RST_Pos                                     (15U)
#define RCM_APB1RST_SPI3RST_Msk                                     (0x1UL << RCM_APB1RST_SPI3RST_Pos)                             /*!< 0x00008000 */
#define RCM_APB1RST_SPI3RST                                         RCM_APB1RST_SPI3RST_Msk
#define RCM_APB1RST_USART2RST_Pos                                   (17U)
#define RCM_APB1RST_USART2RST_Msk                                   (0x1UL << RCM_APB1RST_USART2RST_Pos)                           /*!< 0x00020000 */
#define RCM_APB1RST_USART2RST                                       RCM_APB1RST_USART2RST_Msk
#define RCM_APB1RST_USART3RST_Pos                                   (18U)
#define RCM_APB1RST_USART3RST_Msk                                   (0x1UL << RCM_APB1RST_USART3RST_Pos)                           /*!< 0x00040000 */
#define RCM_APB1RST_USART3RST                                       RCM_APB1RST_USART3RST_Msk
#define RCM_APB1RST_UART4RST_Pos                                    (19U)
#define RCM_APB1RST_UART4RST_Msk                                    (0x1UL << RCM_APB1RST_UART4RST_Pos)                            /*!< 0x00080000 */
#define RCM_APB1RST_UART4RST                                        RCM_APB1RST_UART4RST_Msk
#define RCM_APB1RST_UART5RST_Pos                                    (20U)
#define RCM_APB1RST_UART5RST_Msk                                    (0x1UL << RCM_APB1RST_UART5RST_Pos)                            /*!< 0x00100000 */
#define RCM_APB1RST_UART5RST                                        RCM_APB1RST_UART5RST_Msk
#define RCM_APB1RST_I2C1RST_Pos                                     (21U)
#define RCM_APB1RST_I2C1RST_Msk                                     (0x1UL << RCM_APB1RST_I2C1RST_Pos)                             /*!< 0x00200000 */
#define RCM_APB1RST_I2C1RST                                         RCM_APB1RST_I2C1RST_Msk
#define RCM_APB1RST_I2C2RST_Pos                                     (22U)
#define RCM_APB1RST_I2C2RST_Msk                                     (0x1UL << RCM_APB1RST_I2C2RST_Pos)                             /*!< 0x00400000 */
#define RCM_APB1RST_I2C2RST                                         RCM_APB1RST_I2C2RST_Msk
#define RCM_APB1RST_I2C3RST_Pos                                     (23U)
#define RCM_APB1RST_I2C3RST_Msk                                     (0x1UL << RCM_APB1RST_I2C3RST_Pos)                             /*!< 0x00800000 */
#define RCM_APB1RST_I2C3RST                                         RCM_APB1RST_I2C3RST_Msk
#define RCM_APB1RST_CAN1RST_Pos                                     (25U)
#define RCM_APB1RST_CAN1RST_Msk                                     (0x1UL << RCM_APB1RST_CAN1RST_Pos)                             /*!< 0x02000000 */
#define RCM_APB1RST_CAN1RST                                         RCM_APB1RST_CAN1RST_Msk
#define RCM_APB1RST_CAN2RST_Pos                                     (26U)
#define RCM_APB1RST_CAN2RST_Msk                                     (0x1UL << RCM_APB1RST_CAN2RST_Pos)                             /*!< 0x04000000 */
#define RCM_APB1RST_CAN2RST                                         RCM_APB1RST_CAN2RST_Msk
#define RCM_APB1RST_PMURST_Pos                                      (28U)
#define RCM_APB1RST_PMURST_Msk                                      (0x1UL << RCM_APB1RST_PMURST_Pos)                              /*!< 0x10000000 */
#define RCM_APB1RST_PMURST                                          RCM_APB1RST_PMURST_Msk
#define RCM_APB1RST_DACRST_Pos                                      (29U)
#define RCM_APB1RST_DACRST_Msk                                      (0x1UL << RCM_APB1RST_DACRST_Pos)                              /*!< 0x20000000 */
#define RCM_APB1RST_DACRST                                          RCM_APB1RST_DACRST_Msk

/********************  Bit definition for RCM_APB2RST register  **************/
#define RCM_APB2RST_TMR1RST_Pos                                     (0U)
#define RCM_APB2RST_TMR1RST_Msk                                     (0x1UL << RCM_APB2RST_TMR1RST_Pos)                             /*!< 0x00000001 */
#define RCM_APB2RST_TMR1RST                                         RCM_APB2RST_TMR1RST_Msk
#define RCM_APB2RST_TMR8RST_Pos                                     (1U)
#define RCM_APB2RST_TMR8RST_Msk                                     (0x1UL << RCM_APB2RST_TMR8RST_Pos)                             /*!< 0x00000002 */
#define RCM_APB2RST_TMR8RST                                         RCM_APB2RST_TMR8RST_Msk
#define RCM_APB2RST_USART1RST_Pos                                   (4U)
#define RCM_APB2RST_USART1RST_Msk                                   (0x1UL << RCM_APB2RST_USART1RST_Pos)                           /*!< 0x00000010 */
#define RCM_APB2RST_USART1RST                                       RCM_APB2RST_USART1RST_Msk
#define RCM_APB2RST_USART6RST_Pos                                   (5U)
#define RCM_APB2RST_USART6RST_Msk                                   (0x1UL << RCM_APB2RST_USART6RST_Pos)                           /*!< 0x00000020 */
#define RCM_APB2RST_USART6RST                                       RCM_APB2RST_USART6RST_Msk
#define RCM_APB2RST_ADCRST_Pos                                      (8U)
#define RCM_APB2RST_ADCRST_Msk                                      (0x1UL << RCM_APB2RST_ADCRST_Pos)                              /*!< 0x00000100 */
#define RCM_APB2RST_ADCRST                                          RCM_APB2RST_ADCRST_Msk
#define RCM_APB2RST_SDIORST_Pos                                     (11U)
#define RCM_APB2RST_SDIORST_Msk                                     (0x1UL << RCM_APB2RST_SDIORST_Pos)                             /*!< 0x00000800 */
#define RCM_APB2RST_SDIORST                                         RCM_APB2RST_SDIORST_Msk
#define RCM_APB2RST_SPI1RST_Pos                                     (12U)
#define RCM_APB2RST_SPI1RST_Msk                                     (0x1UL << RCM_APB2RST_SPI1RST_Pos)                             /*!< 0x00001000 */
#define RCM_APB2RST_SPI1RST                                         RCM_APB2RST_SPI1RST_Msk
#define RCM_APB2RST_SYSCFGRST_Pos                                   (14U)
#define RCM_APB2RST_SYSCFGRST_Msk                                   (0x1UL << RCM_APB2RST_SYSCFGRST_Pos)                           /*!< 0x00004000 */
#define RCM_APB2RST_SYSCFGRST                                       RCM_APB2RST_SYSCFGRST_Msk
#define RCM_APB2RST_TMR9RST_Pos                                     (16U)
#define RCM_APB2RST_TMR9RST_Msk                                     (0x1UL << RCM_APB2RST_TMR9RST_Pos)                             /*!< 0x00010000 */
#define RCM_APB2RST_TMR9RST                                         RCM_APB2RST_TMR9RST_Msk
#define RCM_APB2RST_TMR10RST_Pos                                    (17U)
#define RCM_APB2RST_TMR10RST_Msk                                    (0x1UL << RCM_APB2RST_TMR10RST_Pos)                            /*!< 0x00020000 */
#define RCM_APB2RST_TMR10RST                                        RCM_APB2RST_TMR10RST_Msk
#define RCM_APB2RST_TMR11RST_Pos                                    (18U)
#define RCM_APB2RST_TMR11RST_Msk                                    (0x1UL << RCM_APB2RST_TMR11RST_Pos)                            /*!< 0x00040000 */
#define RCM_APB2RST_TMR11RST                                        RCM_APB2RST_TMR11RST_Msk

/* Old SPI1RST bit definition, maintained for legacy purpose */
#define RCM_APB2RST_SPI1                                            RCM_APB2RST_SPI1RST

/********************  Bit definition for RCM_AHB1CLKEN register  ***************/
#define RCM_AHB1CLKEN_PAEN_Pos                                      (0U)
#define RCM_AHB1CLKEN_PAEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PAEN_Pos)                              /*!< 0x00000001 */
#define RCM_AHB1CLKEN_PAEN                                          RCM_AHB1CLKEN_PAEN_Msk
#define RCM_AHB1CLKEN_PBEN_Pos                                      (1U)
#define RCM_AHB1CLKEN_PBEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PBEN_Pos)                              /*!< 0x00000002 */
#define RCM_AHB1CLKEN_PBEN                                          RCM_AHB1CLKEN_PBEN_Msk
#define RCM_AHB1CLKEN_PCEN_Pos                                      (2U)
#define RCM_AHB1CLKEN_PCEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PCEN_Pos)                              /*!< 0x00000004 */
#define RCM_AHB1CLKEN_PCEN                                          RCM_AHB1CLKEN_PCEN_Msk
#define RCM_AHB1CLKEN_PDEN_Pos                                      (3U)
#define RCM_AHB1CLKEN_PDEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PDEN_Pos)                              /*!< 0x00000008 */
#define RCM_AHB1CLKEN_PDEN                                          RCM_AHB1CLKEN_PDEN_Msk
#define RCM_AHB1CLKEN_PEEN_Pos                                      (4U)
#define RCM_AHB1CLKEN_PEEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PEEN_Pos)                              /*!< 0x00000010 */
#define RCM_AHB1CLKEN_PEEN                                          RCM_AHB1CLKEN_PEEN_Msk
#define RCM_AHB1CLKEN_PFEN_Pos                                      (5U)
#define RCM_AHB1CLKEN_PFEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PFEN_Pos)                              /*!< 0x00000020 */
#define RCM_AHB1CLKEN_PFEN                                          RCM_AHB1CLKEN_PFEN_Msk
#define RCM_AHB1CLKEN_PGEN_Pos                                      (6U)
#define RCM_AHB1CLKEN_PGEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PGEN_Pos)                              /*!< 0x00000040 */
#define RCM_AHB1CLKEN_PGEN                                          RCM_AHB1CLKEN_PGEN_Msk
#define RCM_AHB1CLKEN_PHEN_Pos                                      (7U)
#define RCM_AHB1CLKEN_PHEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PHEN_Pos)                              /*!< 0x00000080 */
#define RCM_AHB1CLKEN_PHEN                                          RCM_AHB1CLKEN_PHEN_Msk
#define RCM_AHB1CLKEN_PIEN_Pos                                      (8U)
#define RCM_AHB1CLKEN_PIEN_Msk                                      (0x1UL << RCM_AHB1CLKEN_PIEN_Pos)                              /*!< 0x00000100 */
#define RCM_AHB1CLKEN_PIEN                                          RCM_AHB1CLKEN_PIEN_Msk
#define RCM_AHB1CLKEN_CRCEN_Pos                                     (12U)
#define RCM_AHB1CLKEN_CRCEN_Msk                                     (0x1UL << RCM_AHB1CLKEN_CRCEN_Pos)                             /*!< 0x00001000 */
#define RCM_AHB1CLKEN_CRCEN                                         RCM_AHB1CLKEN_CRCEN_Msk
#define RCM_AHB1CLKEN_BKPSRAMEN_Pos                                 (18U)
#define RCM_AHB1CLKEN_BKPSRAMEN_Msk                                 (0x1UL << RCM_AHB1CLKEN_BKPSRAMEN_Pos)                         /*!< 0x00040000 */
#define RCM_AHB1CLKEN_BKPSRAMEN                                     RCM_AHB1CLKEN_BKPSRAMEN_Msk
#define RCM_AHB1CLKEN_DRAMEN_Pos                                    (20U)
#define RCM_AHB1CLKEN_DRAMEN_Msk                                    (0x1UL << RCM_AHB1CLKEN_DRAMEN_Pos)                            /*!< 0x00100000 */
#define RCM_AHB1CLKEN_DRAMEN                                        RCM_AHB1CLKEN_DRAMEN_Msk
#define RCM_AHB1CLKEN_DMA1EN_Pos                                    (21U)
#define RCM_AHB1CLKEN_DMA1EN_Msk                                    (0x1UL << RCM_AHB1CLKEN_DMA1EN_Pos)                            /*!< 0x00200000 */
#define RCM_AHB1CLKEN_DMA1EN                                        RCM_AHB1CLKEN_DMA1EN_Msk
#define RCM_AHB1CLKEN_DMA2EN_Pos                                    (22U)
#define RCM_AHB1CLKEN_DMA2EN_Msk                                    (0x1UL << RCM_AHB1CLKEN_DMA2EN_Pos)                            /*!< 0x00400000 */
#define RCM_AHB1CLKEN_DMA2EN                                        RCM_AHB1CLKEN_DMA2EN_Msk
#define RCM_AHB1CLKEN_ETHEN_Pos                                     (25U)
#define RCM_AHB1CLKEN_ETHEN_Msk                                     (0x1UL << RCM_AHB1CLKEN_ETHEN_Pos)                             /*!< 0x02000000 */
#define RCM_AHB1CLKEN_ETHEN                                         RCM_AHB1CLKEN_ETHEN_Msk
#define RCM_AHB1CLKEN_ETHTXEN_Pos                                   (26U)
#define RCM_AHB1CLKEN_ETHTXEN_Msk                                   (0x1UL << RCM_AHB1CLKEN_ETHTXEN_Pos)                           /*!< 0x04000000 */
#define RCM_AHB1CLKEN_ETHTXEN                                       RCM_AHB1CLKEN_ETHTXEN_Msk
#define RCM_AHB1CLKEN_ETHRXEN_Pos                                   (27U)
#define RCM_AHB1CLKEN_ETHRXEN_Msk                                   (0x1UL << RCM_AHB1CLKEN_ETHRXEN_Pos)                           /*!< 0x08000000 */
#define RCM_AHB1CLKEN_ETHRXEN                                       RCM_AHB1CLKEN_ETHRXEN_Msk
#define RCM_AHB1CLKEN_ETHPTPEN_Pos                                  (28U)
#define RCM_AHB1CLKEN_ETHPTPEN_Msk                                  (0x1UL << RCM_AHB1CLKEN_ETHPTPEN_Pos)                          /*!< 0x10000000 */
#define RCM_AHB1CLKEN_ETHPTPEN                                      RCM_AHB1CLKEN_ETHPTPEN_Msk
#define RCM_AHB1CLKEN_OTGHS1EN_Pos                                  (29U)
#define RCM_AHB1CLKEN_OTGHS1EN_Msk                                  (0x1UL << RCM_AHB1CLKEN_OTGHS1EN_Pos)                          /*!< 0x20000000 */
#define RCM_AHB1CLKEN_OTGHS1EN                                      RCM_AHB1CLKEN_OTGHS1EN_Msk
#define RCM_AHB1CLKEN_OTGHSULPIEN_Pos                               (30U)
#define RCM_AHB1CLKEN_OTGHSULPIEN_Msk                               (0x1UL << RCM_AHB1CLKEN_OTGHSULPIEN_Pos)                       /*!< 0x40000000 */
#define RCM_AHB1CLKEN_OTGHSULPIEN                                   RCM_AHB1CLKEN_OTGHSULPIEN_Msk
/********************  Bit definition for RCM_AHB2CLKEN register  ***************/
/*
 * @brief Specific device feature definitions (not present on all devices in the APM32F4 serie)
 */
#define RCM_AHB2_SUPPORT                                                                                                           /*!< AHB2 Bus is supported */

#define RCM_AHB2CLKEN_DCIEN_Pos                                     (0U)
#define RCM_AHB2CLKEN_DCIEN_Msk                                     (0x1UL << RCM_AHB2CLKEN_DCIEN_Pos)                             /*!< 0x00000001 */
#define RCM_AHB2CLKEN_DCIEN                                         RCM_AHB2CLKEN_DCIEN_Msk
#define RCM_AHB2CLKEN_FPUEN_Pos                                     (1U)
#define RCM_AHB2CLKEN_FPUEN_Msk                                     (0x1UL << RCM_AHB2CLKEN_FPUEN_Pos)                             /*!< 0x00000001 */
#define RCM_AHB2CLKEN_FPUEN                                         RCM_AHB2CLKEN_FPUEN_Msk
#define RCM_AHB2CLKEN_BNEN_Pos                                      (2U)
#define RCM_AHB2CLKEN_BNEN_Msk                                      (0x1UL << RCM_AHB2CLKEN_BNEN_Pos)                              /*!< 0x00000001 */
#define RCM_AHB2CLKEN_BNEN                                          RCM_AHB2CLKEN_BNEN_Msk
#define RCM_AHB2CLKEN_SMEN_Pos                                      (3U)
#define RCM_AHB2CLKEN_SMEN_Msk                                      (0x1UL << RCM_AHB2CLKEN_SMEN_Pos)                              /*!< 0x00000001 */
#define RCM_AHB2CLKEN_SMEN                                          RCM_AHB2CLKEN_SMEN_Msk
#define RCM_AHB2CLKEN_RNGEN_Pos                                     (6U)
#define RCM_AHB2CLKEN_RNGEN_Msk                                     (0x1UL << RCM_AHB2CLKEN_RNGEN_Pos)                             /*!< 0x00000040 */
#define RCM_AHB2CLKEN_RNGEN                                         RCM_AHB2CLKEN_RNGEN_Msk
#define RCM_AHB2CLKEN_OTGFSEN_Pos                                   (7U)
#define RCM_AHB2CLKEN_OTGFSEN_Msk                                   (0x1UL << RCM_AHB2CLKEN_OTGFSEN_Pos)                           /*!< 0x00000080 */
#define RCM_AHB2CLKEN_OTGFSEN                                       RCM_AHB2CLKEN_OTGFSEN_Msk

/********************  Bit definition for RCM_AHB3CLKEN register  ***************/
/*
 * @brief Specific device feature definitions (not present on all devices in the APM32F4 serie)
 */
#define RCM_AHB3_SUPPORT                                                                                                           /*!< AHB3 Bus is supported */

#define RCM_AHB3CLKEN_EMMCEN_Pos                                    (0U)
#define RCM_AHB3CLKEN_EMMCEN_Msk                                    (0x1UL << RCM_AHB3CLKEN_EMMCEN_Pos)                            /*!< 0x00000001 */
#define RCM_AHB3CLKEN_EMMCEN                                        RCM_AHB3CLKEN_EMMCEN_Msk

/********************  Bit definition for RCM_APB1CLKEN register  ***************/
#define RCM_APB1CLKEN_TMR2EN_Pos                                    (0U)
#define RCM_APB1CLKEN_TMR2EN_Msk                                    (0x1UL << RCM_APB1CLKEN_TMR2EN_Pos)                            /*!< 0x00000001 */
#define RCM_APB1CLKEN_TMR2EN                                        RCM_APB1CLKEN_TMR2EN_Msk
#define RCM_APB1CLKEN_TMR3EN_Pos                                    (1U)
#define RCM_APB1CLKEN_TMR3EN_Msk                                    (0x1UL << RCM_APB1CLKEN_TMR3EN_Pos)                            /*!< 0x00000002 */
#define RCM_APB1CLKEN_TMR3EN                                        RCM_APB1CLKEN_TMR3EN_Msk
#define RCM_APB1CLKEN_TMR4EN_Pos                                    (2U)
#define RCM_APB1CLKEN_TMR4EN_Msk                                    (0x1UL << RCM_APB1CLKEN_TMR4EN_Pos)                            /*!< 0x00000004 */
#define RCM_APB1CLKEN_TMR4EN                                        RCM_APB1CLKEN_TMR4EN_Msk
#define RCM_APB1CLKEN_TMR5EN_Pos                                    (3U)
#define RCM_APB1CLKEN_TMR5EN_Msk                                    (0x1UL << RCM_APB1CLKEN_TMR5EN_Pos)                            /*!< 0x00000008 */
#define RCM_APB1CLKEN_TMR5EN                                        RCM_APB1CLKEN_TMR5EN_Msk
#define RCM_APB1CLKEN_TMR6EN_Pos                                    (4U)
#define RCM_APB1CLKEN_TMR6EN_Msk                                    (0x1UL << RCM_APB1CLKEN_TMR6EN_Pos)                            /*!< 0x00000010 */
#define RCM_APB1CLKEN_TMR6EN                                        RCM_APB1CLKEN_TMR6EN_Msk
#define RCM_APB1CLKEN_TMR7EN_Pos                                    (5U)
#define RCM_APB1CLKEN_TMR7EN_Msk                                    (0x1UL << RCM_APB1CLKEN_TMR7EN_Pos)                            /*!< 0x00000020 */
#define RCM_APB1CLKEN_TMR7EN                                        RCM_APB1CLKEN_TMR7EN_Msk
#define RCM_APB1CLKEN_TMR12EN_Pos                                   (6U)
#define RCM_APB1CLKEN_TMR12EN_Msk                                   (0x1UL << RCM_APB1CLKEN_TMR12EN_Pos)                           /*!< 0x00000040 */
#define RCM_APB1CLKEN_TMR12EN                                       RCM_APB1CLKEN_TMR12EN_Msk
#define RCM_APB1CLKEN_TMR13EN_Pos                                   (7U)
#define RCM_APB1CLKEN_TMR13EN_Msk                                   (0x1UL << RCM_APB1CLKEN_TMR13EN_Pos)                           /*!< 0x00000080 */
#define RCM_APB1CLKEN_TMR13EN                                       RCM_APB1CLKEN_TMR13EN_Msk
#define RCM_APB1CLKEN_TMR14EN_Pos                                   (8U)
#define RCM_APB1CLKEN_TMR14EN_Msk                                   (0x1UL << RCM_APB1CLKEN_TMR14EN_Pos)                           /*!< 0x00000100 */
#define RCM_APB1CLKEN_TMR14EN                                       RCM_APB1CLKEN_TMR14EN_Msk
#define RCM_APB1CLKEN_WWDTEN_Pos                                    (11U)
#define RCM_APB1CLKEN_WWDTEN_Msk                                    (0x1UL << RCM_APB1CLKEN_WWDTEN_Pos)                            /*!< 0x00000800 */
#define RCM_APB1CLKEN_WWDTEN                                        RCM_APB1CLKEN_WWDTEN_Msk
#define RCM_APB1CLKEN_SPI2EN_Pos                                    (14U)
#define RCM_APB1CLKEN_SPI2EN_Msk                                    (0x1UL << RCM_APB1CLKEN_SPI2EN_Pos)                            /*!< 0x00004000 */
#define RCM_APB1CLKEN_SPI2EN                                        RCM_APB1CLKEN_SPI2EN_Msk
#define RCM_APB1CLKEN_SPI3EN_Pos                                    (15U)
#define RCM_APB1CLKEN_SPI3EN_Msk                                    (0x1UL << RCM_APB1CLKEN_SPI3EN_Pos)                            /*!< 0x00008000 */
#define RCM_APB1CLKEN_SPI3EN                                        RCM_APB1CLKEN_SPI3EN_Msk
#define RCM_APB1CLKEN_USART2EN_Pos                                  (17U)
#define RCM_APB1CLKEN_USART2EN_Msk                                  (0x1UL << RCM_APB1CLKEN_USART2EN_Pos)                          /*!< 0x00020000 */
#define RCM_APB1CLKEN_USART2EN                                      RCM_APB1CLKEN_USART2EN_Msk
#define RCM_APB1CLKEN_USART3EN_Pos                                  (18U)
#define RCM_APB1CLKEN_USART3EN_Msk                                  (0x1UL << RCM_APB1CLKEN_USART3EN_Pos)                          /*!< 0x00040000 */
#define RCM_APB1CLKEN_USART3EN                                      RCM_APB1CLKEN_USART3EN_Msk
#define RCM_APB1CLKEN_UART4EN_Pos                                   (19U)
#define RCM_APB1CLKEN_UART4EN_Msk                                   (0x1UL << RCM_APB1CLKEN_UART4EN_Pos)                           /*!< 0x00080000 */
#define RCM_APB1CLKEN_UART4EN                                       RCM_APB1CLKEN_UART4EN_Msk
#define RCM_APB1CLKEN_UART5EN_Pos                                   (20U)
#define RCM_APB1CLKEN_UART5EN_Msk                                   (0x1UL << RCM_APB1CLKEN_UART5EN_Pos)                           /*!< 0x00100000 */
#define RCM_APB1CLKEN_UART5EN                                       RCM_APB1CLKEN_UART5EN_Msk
#define RCM_APB1CLKEN_I2C1EN_Pos                                    (21U)
#define RCM_APB1CLKEN_I2C1EN_Msk                                    (0x1UL << RCM_APB1CLKEN_I2C1EN_Pos)                            /*!< 0x00200000 */
#define RCM_APB1CLKEN_I2C1EN                                        RCM_APB1CLKEN_I2C1EN_Msk
#define RCM_APB1CLKEN_I2C2EN_Pos                                    (22U)
#define RCM_APB1CLKEN_I2C2EN_Msk                                    (0x1UL << RCM_APB1CLKEN_I2C2EN_Pos)                            /*!< 0x00400000 */
#define RCM_APB1CLKEN_I2C2EN                                        RCM_APB1CLKEN_I2C2EN_Msk
#define RCM_APB1CLKEN_I2C3EN_Pos                                    (23U)
#define RCM_APB1CLKEN_I2C3EN_Msk                                    (0x1UL << RCM_APB1CLKEN_I2C3EN_Pos)                            /*!< 0x00800000 */
#define RCM_APB1CLKEN_I2C3EN                                        RCM_APB1CLKEN_I2C3EN_Msk
#define RCM_APB1CLKEN_CAN1EN_Pos                                    (25U)
#define RCM_APB1CLKEN_CAN1EN_Msk                                    (0x1UL << RCM_APB1CLKEN_CAN1EN_Pos)                            /*!< 0x02000000 */
#define RCM_APB1CLKEN_CAN1EN                                        RCM_APB1CLKEN_CAN1EN_Msk
#define RCM_APB1CLKEN_CAN2EN_Pos                                    (26U)
#define RCM_APB1CLKEN_CAN2EN_Msk                                    (0x1UL << RCM_APB1CLKEN_CAN2EN_Pos)                            /*!< 0x04000000 */
#define RCM_APB1CLKEN_CAN2EN                                        RCM_APB1CLKEN_CAN2EN_Msk
#define RCM_APB1CLKEN_PMUEN_Pos                                     (28U)
#define RCM_APB1CLKEN_PMUEN_Msk                                     (0x1UL << RCM_APB1CLKEN_PMUEN_Pos)                             /*!< 0x10000000 */
#define RCM_APB1CLKEN_PMUEN                                         RCM_APB1CLKEN_PMUEN_Msk
#define RCM_APB1CLKEN_DACEN_Pos                                     (29U)
#define RCM_APB1CLKEN_DACEN_Msk                                     (0x1UL << RCM_APB1CLKEN_DACEN_Pos)                             /*!< 0x20000000 */
#define RCM_APB1CLKEN_DACEN                                         RCM_APB1CLKEN_DACEN_Msk

/********************  Bit definition for RCM_APB2CLKEN register  ***************/
#define RCM_APB2CLKEN_TMR1EN_Pos                                    (0U)
#define RCM_APB2CLKEN_TMR1EN_Msk                                    (0x1UL << RCM_APB2CLKEN_TMR1EN_Pos)                            /*!< 0x00000001 */
#define RCM_APB2CLKEN_TMR1EN                                        RCM_APB2CLKEN_TMR1EN_Msk
#define RCM_APB2CLKEN_TMR8EN_Pos                                    (1U)
#define RCM_APB2CLKEN_TMR8EN_Msk                                    (0x1UL << RCM_APB2CLKEN_TMR8EN_Pos)                            /*!< 0x00000002 */
#define RCM_APB2CLKEN_TMR8EN                                        RCM_APB2CLKEN_TMR8EN_Msk
#define RCM_APB2CLKEN_USART1EN_Pos                                  (4U)
#define RCM_APB2CLKEN_USART1EN_Msk                                  (0x1UL << RCM_APB2CLKEN_USART1EN_Pos)                          /*!< 0x00000010 */
#define RCM_APB2CLKEN_USART1EN                                      RCM_APB2CLKEN_USART1EN_Msk
#define RCM_APB2CLKEN_USART6EN_Pos                                  (5U)
#define RCM_APB2CLKEN_USART6EN_Msk                                  (0x1UL << RCM_APB2CLKEN_USART6EN_Pos)                          /*!< 0x00000020 */
#define RCM_APB2CLKEN_USART6EN                                      RCM_APB2CLKEN_USART6EN_Msk
#define RCM_APB2CLKEN_ADC1EN_Pos                                    (8U)
#define RCM_APB2CLKEN_ADC1EN_Msk                                    (0x1UL << RCM_APB2CLKEN_ADC1EN_Pos)                            /*!< 0x00000100 */
#define RCM_APB2CLKEN_ADC1EN                                        RCM_APB2CLKEN_ADC1EN_Msk
#define RCM_APB2CLKEN_ADC2EN_Pos                                    (9U)
#define RCM_APB2CLKEN_ADC2EN_Msk                                    (0x1UL << RCM_APB2CLKEN_ADC2EN_Pos)                            /*!< 0x00000200 */
#define RCM_APB2CLKEN_ADC2EN                                        RCM_APB2CLKEN_ADC2EN_Msk
#define RCM_APB2CLKEN_ADC3EN_Pos                                    (10U)
#define RCM_APB2CLKEN_ADC3EN_Msk                                    (0x1UL << RCM_APB2CLKEN_ADC3EN_Pos)                            /*!< 0x00000400 */
#define RCM_APB2CLKEN_ADC3EN                                        RCM_APB2CLKEN_ADC3EN_Msk
#define RCM_APB2CLKEN_SDIOEN_Pos                                    (11U)
#define RCM_APB2CLKEN_SDIOEN_Msk                                    (0x1UL << RCM_APB2CLKEN_SDIOEN_Pos)                            /*!< 0x00000800 */
#define RCM_APB2CLKEN_SDIOEN                                        RCM_APB2CLKEN_SDIOEN_Msk
#define RCM_APB2CLKEN_SPI1EN_Pos                                    (12U)
#define RCM_APB2CLKEN_SPI1EN_Msk                                    (0x1UL << RCM_APB2CLKEN_SPI1EN_Pos)                            /*!< 0x00001000 */
#define RCM_APB2CLKEN_SPI1EN                                        RCM_APB2CLKEN_SPI1EN_Msk
#define RCM_APB2CLKEN_SYSCFGEN_Pos                                  (14U)
#define RCM_APB2CLKEN_SYSCFGEN_Msk                                  (0x1UL << RCM_APB2CLKEN_SYSCFGEN_Pos)                          /*!< 0x00004000 */
#define RCM_APB2CLKEN_SYSCFGEN                                      RCM_APB2CLKEN_SYSCFGEN_Msk
#define RCM_APB2CLKEN_TMR9EN_Pos                                    (16U)
#define RCM_APB2CLKEN_TMR9EN_Msk                                    (0x1UL << RCM_APB2CLKEN_TMR9EN_Pos)                            /*!< 0x00010000 */
#define RCM_APB2CLKEN_TMR9EN                                        RCM_APB2CLKEN_TMR9EN_Msk
#define RCM_APB2CLKEN_TMR10EN_Pos                                   (17U)
#define RCM_APB2CLKEN_TMR10EN_Msk                                   (0x1UL << RCM_APB2CLKEN_TMR10EN_Pos)                           /*!< 0x00020000 */
#define RCM_APB2CLKEN_TMR10EN                                       RCM_APB2CLKEN_TMR10EN_Msk
#define RCM_APB2CLKEN_TMR11EN_Pos                                   (18U)
#define RCM_APB2CLKEN_TMR11EN_Msk                                   (0x1UL << RCM_APB2CLKEN_TMR11EN_Pos)                           /*!< 0x00040000 */
#define RCM_APB2CLKEN_TMR11EN                                       RCM_APB2CLKEN_TMR11EN_Msk

/********************  Bit definition for RCM_LPAHB1CLKEN register  *************/
#define RCM_LPAHB1CLKEN_PALPEN_Pos                                  (0U)
#define RCM_LPAHB1CLKEN_PALPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PALPEN_Pos)                          /*!< 0x00000001 */
#define RCM_LPAHB1CLKEN_PALPEN                                      RCM_LPAHB1CLKEN_PALPEN_Msk
#define RCM_LPAHB1CLKEN_PBLPEN_Pos                                  (1U)
#define RCM_LPAHB1CLKEN_PBLPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PBLPEN_Pos)                          /*!< 0x00000002 */
#define RCM_LPAHB1CLKEN_PBLPEN                                      RCM_LPAHB1CLKEN_PBLPEN_Msk
#define RCM_LPAHB1CLKEN_PCLPEN_Pos                                  (2U)
#define RCM_LPAHB1CLKEN_PCLPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PCLPEN_Pos)                          /*!< 0x00000004 */
#define RCM_LPAHB1CLKEN_PCLPEN                                      RCM_LPAHB1CLKEN_PCLPEN_Msk
#define RCM_LPAHB1CLKEN_PDLPEN_Pos                                  (3U)
#define RCM_LPAHB1CLKEN_PDLPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PDLPEN_Pos)                          /*!< 0x00000008 */
#define RCM_LPAHB1CLKEN_PDLPEN                                      RCM_LPAHB1CLKEN_PDLPEN_Msk
#define RCM_LPAHB1CLKEN_PELPEN_Pos                                  (4U)
#define RCM_LPAHB1CLKEN_PELPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PELPEN_Pos)                          /*!< 0x00000010 */
#define RCM_LPAHB1CLKEN_PELPEN                                      RCM_LPAHB1CLKEN_PELPEN_Msk
#define RCM_LPAHB1CLKEN_PFLPEN_Pos                                  (5U)
#define RCM_LPAHB1CLKEN_PFLPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PFLPEN_Pos)                          /*!< 0x00000020 */
#define RCM_LPAHB1CLKEN_PFLPEN                                      RCM_LPAHB1CLKEN_PFLPEN_Msk
#define RCM_LPAHB1CLKEN_PGLPEN_Pos                                  (6U)
#define RCM_LPAHB1CLKEN_PGLPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PGLPEN_Pos)                          /*!< 0x00000040 */
#define RCM_LPAHB1CLKEN_PGLPEN                                      RCM_LPAHB1CLKEN_PGLPEN_Msk
#define RCM_LPAHB1CLKEN_PHLPEN_Pos                                  (7U)
#define RCM_LPAHB1CLKEN_PHLPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PHLPEN_Pos)                          /*!< 0x00000080 */
#define RCM_LPAHB1CLKEN_PHLPEN                                      RCM_LPAHB1CLKEN_PHLPEN_Msk
#define RCM_LPAHB1CLKEN_PILPEN_Pos                                  (8U)
#define RCM_LPAHB1CLKEN_PILPEN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_PILPEN_Pos)                          /*!< 0x00000100 */
#define RCM_LPAHB1CLKEN_PILPEN                                      RCM_LPAHB1CLKEN_PILPEN_Msk
#define RCM_LPAHB1CLKEN_CRCLPEN_Pos                                 (12U)
#define RCM_LPAHB1CLKEN_CRCLPEN_Msk                                 (0x1UL << RCM_LPAHB1CLKEN_CRCLPEN_Pos)                         /*!< 0x00001000 */
#define RCM_LPAHB1CLKEN_CRCLPEN                                     RCM_LPAHB1CLKEN_CRCLPEN_Msk
#define RCM_LPAHB1CLKEN_FMCEN_Pos                                   (15U)
#define RCM_LPAHB1CLKEN_FMCEN_Msk                                   (0x1UL << RCM_LPAHB1CLKEN_FMCEN_Pos)                           /*!< 0x00008000 */
#define RCM_LPAHB1CLKEN_FMCEN                                       RCM_LPAHB1CLKEN_FMCEN_Msk
#define RCM_LPAHB1CLKEN_SRAM1EN_Pos                                 (16U)
#define RCM_LPAHB1CLKEN_SRAM1EN_Msk                                 (0x1UL << RCM_LPAHB1CLKEN_SRAM1EN_Pos)                         /*!< 0x00010000 */
#define RCM_LPAHB1CLKEN_SRAM1EN                                     RCM_LPAHB1CLKEN_SRAM1EN_Msk
#define RCM_LPAHB1CLKEN_SRAM2EN_Pos                                 (17U)
#define RCM_LPAHB1CLKEN_SRAM2EN_Msk                                 (0x1UL << RCM_LPAHB1CLKEN_SRAM2EN_Pos)                         /*!< 0x00020000 */
#define RCM_LPAHB1CLKEN_SRAM2EN                                     RCM_LPAHB1CLKEN_SRAM2EN_Msk
#define RCM_LPAHB1CLKEN_BKPSRAMEN_Pos                               (18U)
#define RCM_LPAHB1CLKEN_BKPSRAMEN_Msk                               (0x1UL << RCM_LPAHB1CLKEN_BKPSRAMEN_Pos)                       /*!< 0x00040000 */
#define RCM_LPAHB1CLKEN_BKPSRAMEN                                   RCM_LPAHB1CLKEN_BKPSRAMEN_Msk
#define RCM_LPAHB1CLKEN_DMA1EN_Pos                                  (21U)
#define RCM_LPAHB1CLKEN_DMA1EN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_DMA1EN_Pos)                          /*!< 0x00200000 */
#define RCM_LPAHB1CLKEN_DMA1EN                                      RCM_LPAHB1CLKEN_DMA1EN_Msk
#define RCM_LPAHB1CLKEN_DMA2EN_Pos                                  (22U)
#define RCM_LPAHB1CLKEN_DMA2EN_Msk                                  (0x1UL << RCM_LPAHB1CLKEN_DMA2EN_Pos)                          /*!< 0x00400000 */
#define RCM_LPAHB1CLKEN_DMA2EN                                      RCM_LPAHB1CLKEN_DMA2EN_Msk

#define RCM_LPAHB1CLKEN_ETHEN_Pos                                   (25U)
#define RCM_LPAHB1CLKEN_ETHEN_Msk                                   (0x1UL << RCM_LPAHB1CLKEN_ETHEN_Pos)                           /*!< 0x02000000 */
#define RCM_LPAHB1CLKEN_ETHEN                                       RCM_LPAHB1CLKEN_ETHEN_Msk
#define RCM_LPAHB1CLKEN_ETHTXEN_Pos                                 (26U)
#define RCM_LPAHB1CLKEN_ETHTXEN_Msk                                 (0x1UL << RCM_LPAHB1CLKEN_ETHTXEN_Pos)                         /*!< 0x04000000 */
#define RCM_LPAHB1CLKEN_ETHTXEN                                     RCM_LPAHB1CLKEN_ETHTXEN_Msk
#define RCM_LPAHB1CLKEN_ETHRXEN_Pos                                 (27U)
#define RCM_LPAHB1CLKEN_ETHRXEN_Msk                                 (0x1UL << RCM_LPAHB1CLKEN_ETHRXEN_Pos)                         /*!< 0x08000000 */
#define RCM_LPAHB1CLKEN_ETHRXEN                                     RCM_LPAHB1CLKEN_ETHRXEN_Msk
#define RCM_LPAHB1CLKEN_ETHPTPEN_Pos                                (28U)
#define RCM_LPAHB1CLKEN_ETHPTPEN_Msk                                (0x1UL << RCM_LPAHB1CLKEN_ETHPTPEN_Pos)                        /*!< 0x10000000 */
#define RCM_LPAHB1CLKEN_ETHPTPEN                                    RCM_LPAHB1CLKEN_ETHPTPEN_Msk
#define RCM_LPAHB1CLKEN_OTGHS1EN_Pos                                (29U)
#define RCM_LPAHB1CLKEN_OTGHS1EN_Msk                                (0x1UL << RCM_LPAHB1CLKEN_OTGHS1EN_Pos)                        /*!< 0x20000000 */
#define RCM_LPAHB1CLKEN_OTGHS1EN                                    RCM_LPAHB1CLKEN_OTGHS1EN_Msk
#define RCM_LPAHB1CLKEN_OTGHSULPIEN_Pos                             (30U)
#define RCM_LPAHB1CLKEN_OTGHSULPIEN_Msk                             (0x1UL << RCM_LPAHB1CLKEN_OTGHSULPIEN_Pos)                     /*!< 0x40000000 */
#define RCM_LPAHB1CLKEN_OTGHSULPIEN                                 RCM_LPAHB1CLKEN_OTGHSULPIEN_Msk

/********************  Bit definition for RCM_LPAHB2CLKEN register  *************/
#define RCM_LPAHB2CLKEN_DCIEN_Pos                                   (0U)
#define RCM_LPAHB2CLKEN_DCIEN_Msk                                   (0x1UL << RCM_LPAHB2CLKEN_DCIEN_Pos)                           /*!< 0x00000001 */
#define RCM_LPAHB2CLKEN_DCIEN                                       RCM_LPAHB2CLKEN_DCIEN_Msk
#define RCM_LPAHB2CLKEN_RNGEN_Pos                                   (6U)
#define RCM_LPAHB2CLKEN_RNGEN_Msk                                   (0x1UL << RCM_LPAHB2CLKEN_RNGEN_Pos)                           /*!< 0x00000040 */
#define RCM_LPAHB2CLKEN_RNGEN                                       RCM_LPAHB2CLKEN_RNGEN_Msk
#define RCM_LPAHB2CLKEN_OTGFSEN_Pos                                 (7U)
#define RCM_LPAHB2CLKEN_OTGFSEN_Msk                                 (0x1UL << RCM_LPAHB2CLKEN_OTGFSEN_Pos)                         /*!< 0x00000080 */
#define RCM_LPAHB2CLKEN_OTGFSEN                                     RCM_LPAHB2CLKEN_OTGFSEN_Msk

/********************  Bit definition for RCM_LPAHB3CLKEN register  *************/
#define RCM_LPAHB3CLKEN_EMMCEN_Pos                                  (0U)
#define RCM_LPAHB3CLKEN_EMMCEN_Msk                                  (0x1UL << RCM_LPAHB3CLKEN_EMMCEN_Pos)                          /*!< 0x00000001 */
#define RCM_LPAHB3CLKEN_EMMCEN                                      RCM_LPAHB3CLKEN_EMMCEN_Msk

/********************  Bit definition for RCM_LPAPB1CLKEN register  *************/
#define RCM_LPAPB1CLKEN_TMR2EN_Pos                                  (0U)
#define RCM_LPAPB1CLKEN_TMR2EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_TMR2EN_Pos)                          /*!< 0x00000001 */
#define RCM_LPAPB1CLKEN_TMR2EN                                      RCM_LPAPB1CLKEN_TMR2EN_Msk
#define RCM_LPAPB1CLKEN_TMR3EN_Pos                                  (1U)
#define RCM_LPAPB1CLKEN_TMR3EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_TMR3EN_Pos)                          /*!< 0x00000002 */
#define RCM_LPAPB1CLKEN_TMR3EN                                      RCM_LPAPB1CLKEN_TMR3EN_Msk
#define RCM_LPAPB1CLKEN_TMR4EN_Pos                                  (2U)
#define RCM_LPAPB1CLKEN_TMR4EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_TMR4EN_Pos)                          /*!< 0x00000004 */
#define RCM_LPAPB1CLKEN_TMR4EN                                      RCM_LPAPB1CLKEN_TMR4EN_Msk
#define RCM_LPAPB1CLKEN_TMR5EN_Pos                                  (3U)
#define RCM_LPAPB1CLKEN_TMR5EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_TMR5EN_Pos)                          /*!< 0x00000008 */
#define RCM_LPAPB1CLKEN_TMR5EN                                      RCM_LPAPB1CLKEN_TMR5EN_Msk
#define RCM_LPAPB1CLKEN_TMR6EN_Pos                                  (4U)
#define RCM_LPAPB1CLKEN_TMR6EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_TMR6EN_Pos)                          /*!< 0x00000010 */
#define RCM_LPAPB1CLKEN_TMR6EN                                      RCM_LPAPB1CLKEN_TMR6EN_Msk
#define RCM_LPAPB1CLKEN_TMR7EN_Pos                                  (5U)
#define RCM_LPAPB1CLKEN_TMR7EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_TMR7EN_Pos)                          /*!< 0x00000020 */
#define RCM_LPAPB1CLKEN_TMR7EN                                      RCM_LPAPB1CLKEN_TMR7EN_Msk
#define RCM_LPAPB1CLKEN_TMR12EN_Pos                                 (6U)
#define RCM_LPAPB1CLKEN_TMR12EN_Msk                                 (0x1UL << RCM_LPAPB1CLKEN_TMR12EN_Pos)                         /*!< 0x00000040 */
#define RCM_LPAPB1CLKEN_TMR12EN                                     RCM_LPAPB1CLKEN_TMR12EN_Msk
#define RCM_LPAPB1CLKEN_TMR13EN_Pos                                 (7U)
#define RCM_LPAPB1CLKEN_TMR13EN_Msk                                 (0x1UL << RCM_LPAPB1CLKEN_TMR13EN_Pos)                         /*!< 0x00000080 */
#define RCM_LPAPB1CLKEN_TMR13EN                                     RCM_LPAPB1CLKEN_TMR13EN_Msk
#define RCM_LPAPB1CLKEN_TMR14EN_Pos                                 (8U)
#define RCM_LPAPB1CLKEN_TMR14EN_Msk                                 (0x1UL << RCM_LPAPB1CLKEN_TMR14EN_Pos)                         /*!< 0x00000100 */
#define RCM_LPAPB1CLKEN_TMR14EN                                     RCM_LPAPB1CLKEN_TMR14EN_Msk
#define RCM_LPAPB1CLKEN_WWDTEN_Pos                                  (11U)
#define RCM_LPAPB1CLKEN_WWDTEN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_WWDTEN_Pos)                          /*!< 0x00000800 */
#define RCM_LPAPB1CLKEN_WWDTEN                                      RCM_LPAPB1CLKEN_WWDTEN_Msk
#define RCM_LPAPB1CLKEN_SPI2EN_Pos                                  (14U)
#define RCM_LPAPB1CLKEN_SPI2EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_SPI2EN_Pos)                          /*!< 0x00004000 */
#define RCM_LPAPB1CLKEN_SPI2EN                                      RCM_LPAPB1CLKEN_SPI2EN_Msk
#define RCM_LPAPB1CLKEN_SPI3EN_Pos                                  (15U)
#define RCM_LPAPB1CLKEN_SPI3EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_SPI3EN_Pos)                          /*!< 0x00008000 */
#define RCM_LPAPB1CLKEN_SPI3EN                                      RCM_LPAPB1CLKEN_SPI3EN_Msk
#define RCM_LPAPB1CLKEN_USART2EN_Pos                                (17U)
#define RCM_LPAPB1CLKEN_USART2EN_Msk                                (0x1UL << RCM_LPAPB1CLKEN_USART2EN_Pos)                        /*!< 0x00020000 */
#define RCM_LPAPB1CLKEN_USART2EN                                    RCM_LPAPB1CLKEN_USART2EN_Msk
#define RCM_LPAPB1CLKEN_USART3EN_Pos                                (18U)
#define RCM_LPAPB1CLKEN_USART3EN_Msk                                (0x1UL << RCM_LPAPB1CLKEN_USART3EN_Pos)                        /*!< 0x00040000 */
#define RCM_LPAPB1CLKEN_USART3EN                                    RCM_LPAPB1CLKEN_USART3EN_Msk
#define RCM_LPAPB1CLKEN_UART4EN_Pos                                 (19U)
#define RCM_LPAPB1CLKEN_UART4EN_Msk                                 (0x1UL << RCM_LPAPB1CLKEN_UART4EN_Pos)                         /*!< 0x00080000 */
#define RCM_LPAPB1CLKEN_UART4EN                                     RCM_LPAPB1CLKEN_UART4EN_Msk
#define RCM_LPAPB1CLKEN_UART5EN_Pos                                 (20U)
#define RCM_LPAPB1CLKEN_UART5EN_Msk                                 (0x1UL << RCM_LPAPB1CLKEN_UART5EN_Pos)                         /*!< 0x00100000 */
#define RCM_LPAPB1CLKEN_UART5EN                                     RCM_LPAPB1CLKEN_UART5EN_Msk
#define RCM_LPAPB1CLKEN_I2C1EN_Pos                                  (21U)
#define RCM_LPAPB1CLKEN_I2C1EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_I2C1EN_Pos)                          /*!< 0x00200000 */
#define RCM_LPAPB1CLKEN_I2C1EN                                      RCM_LPAPB1CLKEN_I2C1EN_Msk
#define RCM_LPAPB1CLKEN_I2C2EN_Pos                                  (22U)
#define RCM_LPAPB1CLKEN_I2C2EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_I2C2EN_Pos)                          /*!< 0x00400000 */
#define RCM_LPAPB1CLKEN_I2C2EN                                      RCM_LPAPB1CLKEN_I2C2EN_Msk
#define RCM_LPAPB1CLKEN_I2C3EN_Pos                                  (23U)
#define RCM_LPAPB1CLKEN_I2C3EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_I2C3EN_Pos)                          /*!< 0x00800000 */
#define RCM_LPAPB1CLKEN_I2C3EN                                      RCM_LPAPB1CLKEN_I2C3EN_Msk
#define RCM_LPAPB1CLKEN_CAN1EN_Pos                                  (25U)
#define RCM_LPAPB1CLKEN_CAN1EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_CAN1EN_Pos)                          /*!< 0x02000000 */
#define RCM_LPAPB1CLKEN_CAN1EN                                      RCM_LPAPB1CLKEN_CAN1EN_Msk
#define RCM_LPAPB1CLKEN_CAN2EN_Pos                                  (26U)
#define RCM_LPAPB1CLKEN_CAN2EN_Msk                                  (0x1UL << RCM_LPAPB1CLKEN_CAN2EN_Pos)                          /*!< 0x04000000 */
#define RCM_LPAPB1CLKEN_CAN2EN                                      RCM_LPAPB1CLKEN_CAN2EN_Msk
#define RCM_LPAPB1CLKEN_PMUEN_Pos                                   (28U)
#define RCM_LPAPB1CLKEN_PMUEN_Msk                                   (0x1UL << RCM_LPAPB1CLKEN_PMUEN_Pos)                           /*!< 0x10000000 */
#define RCM_LPAPB1CLKEN_PMUEN                                       RCM_LPAPB1CLKEN_PMUEN_Msk
#define RCM_LPAPB1CLKEN_DACEN_Pos                                   (29U)
#define RCM_LPAPB1CLKEN_DACEN_Msk                                   (0x1UL << RCM_LPAPB1CLKEN_DACEN_Pos)                           /*!< 0x20000000 */
#define RCM_LPAPB1CLKEN_DACEN                                       RCM_LPAPB1CLKEN_DACEN_Msk

/********************  Bit definition for RCM_LPAPB2CLKEN register  *************/
#define RCM_LPAPB2CLKEN_TMR1EN_Pos                                  (0U)
#define RCM_LPAPB2CLKEN_TMR1EN_Msk                                  (0x1UL << RCM_LPAPB2CLKEN_TMR1EN_Pos)                          /*!< 0x00000001 */
#define RCM_LPAPB2CLKEN_TMR1EN                                      RCM_LPAPB2CLKEN_TMR1EN_Msk
#define RCM_LPAPB2CLKEN_TMR8EN_Pos                                  (1U)
#define RCM_LPAPB2CLKEN_TMR8EN_Msk                                  (0x1UL << RCM_LPAPB2CLKEN_TMR8EN_Pos)                          /*!< 0x00000002 */
#define RCM_LPAPB2CLKEN_TMR8EN                                      RCM_LPAPB2CLKEN_TMR8EN_Msk
#define RCM_LPAPB2CLKEN_USART1EN_Pos                                (4U)
#define RCM_LPAPB2CLKEN_USART1EN_Msk                                (0x1UL << RCM_LPAPB2CLKEN_USART1EN_Pos)                        /*!< 0x00000010 */
#define RCM_LPAPB2CLKEN_USART1EN                                    RCM_LPAPB2CLKEN_USART1EN_Msk
#define RCM_LPAPB2CLKEN_USART6EN_Pos                                (5U)
#define RCM_LPAPB2CLKEN_USART6EN_Msk                                (0x1UL << RCM_LPAPB2CLKEN_USART6EN_Pos)                        /*!< 0x00000020 */
#define RCM_LPAPB2CLKEN_USART6EN                                    RCM_LPAPB2CLKEN_USART6EN_Msk
#define RCM_LPAPB2CLKEN_ADC1EN_Pos                                  (8U)
#define RCM_LPAPB2CLKEN_ADC1EN_Msk                                  (0x1UL << RCM_LPAPB2CLKEN_ADC1EN_Pos)                          /*!< 0x00000100 */
#define RCM_LPAPB2CLKEN_ADC1EN                                      RCM_LPAPB2CLKEN_ADC1EN_Msk
#define RCM_LPAPB2CLKEN_ADC2EN_Pos                                  (9U)
#define RCM_LPAPB2CLKEN_ADC2EN_Msk                                  (0x1UL << RCM_LPAPB2CLKEN_ADC2EN_Pos)                          /*!< 0x00000200 */
#define RCM_LPAPB2CLKEN_ADC2EN                                      RCM_LPAPB2CLKEN_ADC2EN_Msk
#define RCM_LPAPB2CLKEN_ADC3EN_Pos                                  (10U)
#define RCM_LPAPB2CLKEN_ADC3EN_Msk                                  (0x1UL << RCM_LPAPB2CLKEN_ADC3EN_Pos)                          /*!< 0x00000400 */
#define RCM_LPAPB2CLKEN_ADC3EN                                      RCM_LPAPB2CLKEN_ADC3EN_Msk
#define RCM_LPAPB2CLKEN_SDIOEN_Pos                                  (11U)
#define RCM_LPAPB2CLKEN_SDIOEN_Msk                                  (0x1UL << RCM_LPAPB2CLKEN_SDIOEN_Pos)                          /*!< 0x00000800 */
#define RCM_LPAPB2CLKEN_SDIOEN                                      RCM_LPAPB2CLKEN_SDIOEN_Msk
#define RCM_LPAPB2CLKEN_SPI1EN_Pos                                  (12U)
#define RCM_LPAPB2CLKEN_SPI1EN_Msk                                  (0x1UL << RCM_LPAPB2CLKEN_SPI1EN_Pos)                          /*!< 0x00001000 */
#define RCM_LPAPB2CLKEN_SPI1EN                                      RCM_LPAPB2CLKEN_SPI1EN_Msk
#define RCM_LPAPB2CLKEN_SYSCFGEN_Pos                                (14U)
#define RCM_LPAPB2CLKEN_SYSCFGEN_Msk                                (0x1UL << RCM_LPAPB2CLKEN_SYSCFGEN_Pos)                        /*!< 0x00004000 */
#define RCM_LPAPB2CLKEN_SYSCFGEN                                    RCM_LPAPB2CLKEN_SYSCFGEN_Msk
#define RCM_LPAPB2CLKEN_TMR9EN_Pos                                  (16U)
#define RCM_LPAPB2CLKEN_TMR9EN_Msk                                  (0x1UL << RCM_LPAPB2CLKEN_TMR9EN_Pos)                          /*!< 0x00010000 */
#define RCM_LPAPB2CLKEN_TMR9EN                                      RCM_LPAPB2CLKEN_TMR9EN_Msk
#define RCM_LPAPB2CLKEN_TMR10EN_Pos                                 (17U)
#define RCM_LPAPB2CLKEN_TMR10EN_Msk                                 (0x1UL << RCM_LPAPB2CLKEN_TMR10EN_Pos)                         /*!< 0x00020000 */
#define RCM_LPAPB2CLKEN_TMR10EN                                     RCM_LPAPB2CLKEN_TMR10EN_Msk
#define RCM_LPAPB2CLKEN_TMR11EN_Pos                                 (18U)
#define RCM_LPAPB2CLKEN_TMR11EN_Msk                                 (0x1UL << RCM_LPAPB2CLKEN_TMR11EN_Pos)                         /*!< 0x00040000 */
#define RCM_LPAPB2CLKEN_TMR11EN                                     RCM_LPAPB2CLKEN_TMR11EN_Msk

/********************  Bit definition for RCM_BDCTRL register  ******************/
#define RCM_BDCTRL_LSEEN_Pos                                        (0U)
#define RCM_BDCTRL_LSEEN_Msk                                        (0x1UL << RCM_BDCTRL_LSEEN_Pos)                                /*!< 0x00000001 */
#define RCM_BDCTRL_LSEEN                                            RCM_BDCTRL_LSEEN_Msk
#define RCM_BDCTRL_LSERDYFLG_Pos                                    (1U)
#define RCM_BDCTRL_LSERDYFLG_Msk                                    (0x1UL << RCM_BDCTRL_LSERDYFLG_Pos)                            /*!< 0x00000002 */
#define RCM_BDCTRL_LSERDYFLG                                        RCM_BDCTRL_LSERDYFLG_Msk
#define RCM_BDCTRL_LSEBCFG_Pos                                      (2U)
#define RCM_BDCTRL_LSEBCFG_Msk                                      (0x1UL << RCM_BDCTRL_LSEBCFG_Pos)                              /*!< 0x00000004 */
#define RCM_BDCTRL_LSEBCFG                                          RCM_BDCTRL_LSEBCFG_Msk

#define RCM_BDCTRL_RTCSRCSEL_Pos                                    (8U)
#define RCM_BDCTRL_RTCSRCSEL_Msk                                    (0x3UL << RCM_BDCTRL_RTCSRCSEL_Pos)                            /*!< 0x00000300 */
#define RCM_BDCTRL_RTCSRCSEL                                        RCM_BDCTRL_RTCSRCSEL_Msk
#define RCM_BDCTRL_RTCSRCSEL_0                                      (0x1UL << RCM_BDCTRL_RTCSRCSEL_Pos)                            /*!< 0x00000100 */
#define RCM_BDCTRL_RTCSRCSEL_1                                      (0x2UL << RCM_BDCTRL_RTCSRCSEL_Pos)                            /*!< 0x00000200 */

#define RCM_BDCTRL_RTCCLKEN_Pos                                     (15U)
#define RCM_BDCTRL_RTCCLKEN_Msk                                     (0x1UL << RCM_BDCTRL_RTCCLKEN_Pos)                             /*!< 0x00008000 */
#define RCM_BDCTRL_RTCCLKEN                                         RCM_BDCTRL_RTCCLKEN_Msk
#define RCM_BDCTRL_BDRST_Pos                                        (16U)
#define RCM_BDCTRL_BDRST_Msk                                        (0x1UL << RCM_BDCTRL_BDRST_Pos)                                /*!< 0x00010000 */
#define RCM_BDCTRL_BDRST                                            RCM_BDCTRL_BDRST_Msk

/********************  Bit definition for RCM_CSTS register  *******************/
#define RCM_CSTS_LSIEN_Pos                                          (0U)
#define RCM_CSTS_LSIEN_Msk                                          (0x1UL << RCM_CSTS_LSIEN_Pos)                                  /*!< 0x00000001 */
#define RCM_CSTS_LSIEN                                              RCM_CSTS_LSIEN_Msk
#define RCM_CSTS_LSIRDYFLG_Pos                                      (1U)
#define RCM_CSTS_LSIRDYFLG_Msk                                      (0x1UL << RCM_CSTS_LSIRDYFLG_Pos)                              /*!< 0x00000002 */
#define RCM_CSTS_LSIRDYFLG                                          RCM_CSTS_LSIRDYFLG_Msk
#define RCM_CSTS_RSTFLGCLR_Pos                                      (24U)
#define RCM_CSTS_RSTFLGCLR_Msk                                      (0x1UL << RCM_CSTS_RSTFLGCLR_Pos)                              /*!< 0x01000000 */
#define RCM_CSTS_RSTFLGCLR                                          RCM_CSTS_RSTFLGCLR_Msk
#define RCM_CSTS_BORRSTFLG_Pos                                      (25U)
#define RCM_CSTS_BORRSTFLG_Msk                                      (0x1UL << RCM_CSTS_BORRSTFLG_Pos)                              /*!< 0x02000000 */
#define RCM_CSTS_BORRSTFLG                                          RCM_CSTS_BORRSTFLG_Msk
#define RCM_CSTS_PINRSTFLG_Pos                                      (26U)
#define RCM_CSTS_PINRSTFLG_Msk                                      (0x1UL << RCM_CSTS_PINRSTFLG_Pos)                              /*!< 0x04000000 */
#define RCM_CSTS_PINRSTFLG                                          RCM_CSTS_PINRSTFLG_Msk
#define RCM_CSTS_PODRSTFLG_Pos                                      (27U)
#define RCM_CSTS_PODRSTFLG_Msk                                      (0x1UL << RCM_CSTS_PODRSTFLG_Pos)                              /*!< 0x08000000 */
#define RCM_CSTS_PODRSTFLG                                          RCM_CSTS_PODRSTFLG_Msk
#define RCM_CSTS_SWRSTFLG_Pos                                       (28U)
#define RCM_CSTS_SWRSTFLG_Msk                                       (0x1UL << RCM_CSTS_SWRSTFLG_Pos)                               /*!< 0x10000000 */
#define RCM_CSTS_SWRSTFLG                                           RCM_CSTS_SWRSTFLG_Msk
#define RCM_CSTS_IWDTRSTFLG_Pos                                     (29U)
#define RCM_CSTS_IWDTRSTFLG_Msk                                     (0x1UL << RCM_CSTS_IWDTRSTFLG_Pos)                             /*!< 0x20000000 */
#define RCM_CSTS_IWDTRSTFLG                                         RCM_CSTS_IWDTRSTFLG_Msk
#define RCM_CSTS_WWDTRSTFLG_Pos                                     (30U)
#define RCM_CSTS_WWDTRSTFLG_Msk                                     (0x1UL << RCM_CSTS_WWDTRSTFLG_Pos)                             /*!< 0x40000000 */
#define RCM_CSTS_WWDTRSTFLG                                         RCM_CSTS_WWDTRSTFLG_Msk
#define RCM_CSTS_LPWRRSTFLG_Pos                                     (31U)
#define RCM_CSTS_LPWRRSTFLG_Msk                                     (0x1UL << RCM_CSTS_LPWRRSTFLG_Pos)                             /*!< 0x80000000 */
#define RCM_CSTS_LPWRRSTFLG                                         RCM_CSTS_LPWRRSTFLG_Msk
/* Legacy defines */
#define RCM_CSTS_PADRSTF                                            RCM_CSTS_PINRSTFLG
#define RCM_CSTS_WDGRSTF                                            RCM_CSTS_IWDTRSTFLG

/********************  Bit definition for RCM_SSCCFG register  *****************/
#define RCM_SSCCFG_MODPCFG_Pos                                      (0U)
#define RCM_SSCCFG_MODPCFG_Msk                                      (0x1FFFUL << RCM_SSCCFG_MODPCFG_Pos)                           /*!< 0x00001FFF */
#define RCM_SSCCFG_MODPCFG                                          RCM_SSCCFG_MODPCFG_Msk
#define RCM_SSCCFG_STEP_Pos                                         (13U)
#define RCM_SSCCFG_STEP_Msk                                         (0x7FFFUL << RCM_SSCCFG_STEP_Pos)                              /*!< 0x0FFFE000 */
#define RCM_SSCCFG_STEP                                             RCM_SSCCFG_STEP_Msk
#define RCM_SSCCFG_SSSEL_Pos                                        (30U)
#define RCM_SSCCFG_SSSEL_Msk                                        (0x1UL << RCM_SSCCFG_SSSEL_Pos)                                /*!< 0x40000000 */
#define RCM_SSCCFG_SSSEL                                            RCM_SSCCFG_SSSEL_Msk
#define RCM_SSCCFG_SSEN_Pos                                         (31U)
#define RCM_SSCCFG_SSEN_Msk                                         (0x1UL << RCM_SSCCFG_SSEN_Pos)                                 /*!< 0x80000000 */
#define RCM_SSCCFG_SSEN                                             RCM_SSCCFG_SSEN_Msk

/********************  Bit definition for RCM_PLL2CFG register  ************/
#define RCM_PLL2CFG_PLL2A_Pos                                       (6U)
#define RCM_PLL2CFG_PLL2A_Msk                                       (0x1FFUL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00007FC0 */
#define RCM_PLL2CFG_PLL2A                                           RCM_PLL2CFG_PLL2A_Msk
#define RCM_PLL2CFG_PLL2A_0                                         (0x001UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00000040 */
#define RCM_PLL2CFG_PLL2A_1                                         (0x002UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00000080 */
#define RCM_PLL2CFG_PLL2A_2                                         (0x004UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00000100 */
#define RCM_PLL2CFG_PLL2A_3                                         (0x008UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00000200 */
#define RCM_PLL2CFG_PLL2A_4                                         (0x010UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00000400 */
#define RCM_PLL2CFG_PLL2A_5                                         (0x020UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00000800 */
#define RCM_PLL2CFG_PLL2A_6                                         (0x040UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00001000 */
#define RCM_PLL2CFG_PLL2A_7                                         (0x080UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00002000 */
#define RCM_PLL2CFG_PLL2A_8                                         (0x100UL << RCM_PLL2CFG_PLL2A_Pos)                             /*!< 0x00004000 */

#define RCM_PLL2CFG_PLL2C_Pos                                       (28U)
#define RCM_PLL2CFG_PLL2C_Msk                                       (0x7UL << RCM_PLL2CFG_PLL2C_Pos)                               /*!< 0x70000000 */
#define RCM_PLL2CFG_PLL2C                                           RCM_PLL2CFG_PLL2C_Msk
#define RCM_PLL2CFG_PLL2C_0                                         (0x1UL << RCM_PLL2CFG_PLL2C_Pos)                               /*!< 0x10000000 */
#define RCM_PLL2CFG_PLL2C_1                                         (0x2UL << RCM_PLL2CFG_PLL2C_Pos)                               /*!< 0x20000000 */
#define RCM_PLL2CFG_PLL2C_2                                         (0x4UL << RCM_PLL2CFG_PLL2C_Pos)                               /*!< 0x40000000 */


/******************************************************************************/
/*                                                                            */
/*                                    RNG                                     */
/*                                                                            */
/******************************************************************************/
/********************  Bits definition for RNG_CTRL register  *******************/
#define RNG_CTRL_RNGEN_Pos                                          (2U)
#define RNG_CTRL_RNGEN_Msk                                          (0x1UL << RNG_CTRL_RNGEN_Pos)                                  /*!< 0x00000004 */
#define RNG_CTRL_RNGEN                                              RNG_CTRL_RNGEN_Msk
#define RNG_CTRL_INTEN_Pos                                          (3U)
#define RNG_CTRL_INTEN_Msk                                          (0x1UL << RNG_CTRL_INTEN_Pos)                                  /*!< 0x00000008 */
#define RNG_CTRL_INTEN                                              RNG_CTRL_INTEN_Msk

/********************  Bits definition for RNG_STS register  *******************/
#define RNG_STS_DATARDY_Pos                                         (0U)
#define RNG_STS_DATARDY_Msk                                         (0x1UL << RNG_STS_DATARDY_Pos)                                 /*!< 0x00000001 */
#define RNG_STS_DATARDY                                             RNG_STS_DATARDY_Msk
#define RNG_STS_CLKERCSTS_Pos                                       (1U)
#define RNG_STS_CLKERCSTS_Msk                                       (0x1UL << RNG_STS_CLKERCSTS_Pos)                               /*!< 0x00000002 */
#define RNG_STS_CLKERCSTS                                           RNG_STS_CLKERCSTS_Msk
#define RNG_STS_FSCSTS_Pos                                          (2U)
#define RNG_STS_FSCSTS_Msk                                          (0x1UL << RNG_STS_FSCSTS_Pos)                                  /*!< 0x00000004 */
#define RNG_STS_FSCSTS                                              RNG_STS_FSCSTS_Msk
#define RNG_STS_CLKERINT_Pos                                        (5U)
#define RNG_STS_CLKERINT_Msk                                        (0x1UL << RNG_STS_CLKERINT_Pos)                                /*!< 0x00000020 */
#define RNG_STS_CLKERINT                                            RNG_STS_CLKERINT_Msk
#define RNG_STS_FSINT_Pos                                           (6U)
#define RNG_STS_FSINT_Msk                                           (0x1UL << RNG_STS_FSINT_Pos)                                   /*!< 0x00000040 */
#define RNG_STS_FSINT                                               RNG_STS_FSINT_Msk

/******************************************************************************/
/*                                                                            */
/*                           Real-Time Clock (RTC)                            */
/*                                                                            */
/******************************************************************************/
/*
 * @brief Specific device feature definitions  (not present on all devices in the APM32F4 serie)
 */
#define RTC_TAMPER2_SUPPORT                                                                                                        /*!< TAMPER 2 feature support */
#define RTC_AF2_SUPPORT                                                                                                            /*!< RTC Alternate Function 2 mapping support */
/********************  Bits definition for RTC_TIME register  *******************/
#define RTC_TIME_TIMEFCFG_Pos                                       (22U)
#define RTC_TIME_TIMEFCFG_Msk                                       (0x1UL << RTC_TIME_TIMEFCFG_Pos)                               /*!< 0x00400000 */
#define RTC_TIME_TIMEFCFG                                           RTC_TIME_TIMEFCFG_Msk
#define RTC_TIME_HRT_Pos                                            (20U)
#define RTC_TIME_HRT_Msk                                            (0x3UL << RTC_TIME_HRT_Pos)                                    /*!< 0x00300000 */
#define RTC_TIME_HRT                                                RTC_TIME_HRT_Msk
#define RTC_TIME_HRT_0                                              (0x1UL << RTC_TIME_HRT_Pos)                                    /*!< 0x00100000 */
#define RTC_TIME_HRT_1                                              (0x2UL << RTC_TIME_HRT_Pos)                                    /*!< 0x00200000 */
#define RTC_TIME_HRU_Pos                                            (16U)
#define RTC_TIME_HRU_Msk                                            (0xFUL << RTC_TIME_HRU_Pos)                                    /*!< 0x000F0000 */
#define RTC_TIME_HRU                                                RTC_TIME_HRU_Msk
#define RTC_TIME_HRU_0                                              (0x1UL << RTC_TIME_HRU_Pos)                                    /*!< 0x00010000 */
#define RTC_TIME_HRU_1                                              (0x2UL << RTC_TIME_HRU_Pos)                                    /*!< 0x00020000 */
#define RTC_TIME_HRU_2                                              (0x4UL << RTC_TIME_HRU_Pos)                                    /*!< 0x00040000 */
#define RTC_TIME_HRU_3                                              (0x8UL << RTC_TIME_HRU_Pos)                                    /*!< 0x00080000 */
#define RTC_TIME_MINT_Pos                                           (12U)
#define RTC_TIME_MINT_Msk                                           (0x7UL << RTC_TIME_MINT_Pos)                                   /*!< 0x00007000 */
#define RTC_TIME_MINT                                               RTC_TIME_MINT_Msk
#define RTC_TIME_MINT_0                                             (0x1UL << RTC_TIME_MINT_Pos)                                   /*!< 0x00001000 */
#define RTC_TIME_MINT_1                                             (0x2UL << RTC_TIME_MINT_Pos)                                   /*!< 0x00002000 */
#define RTC_TIME_MINT_2                                             (0x4UL << RTC_TIME_MINT_Pos)                                   /*!< 0x00004000 */
#define RTC_TIME_MINU_Pos                                           (8U)
#define RTC_TIME_MINU_Msk                                           (0xFUL << RTC_TIME_MINU_Pos)                                   /*!< 0x00000F00 */
#define RTC_TIME_MINU                                               RTC_TIME_MINU_Msk
#define RTC_TIME_MINU_0                                             (0x1UL << RTC_TIME_MINU_Pos)                                   /*!< 0x00000100 */
#define RTC_TIME_MINU_1                                             (0x2UL << RTC_TIME_MINU_Pos)                                   /*!< 0x00000200 */
#define RTC_TIME_MINU_2                                             (0x4UL << RTC_TIME_MINU_Pos)                                   /*!< 0x00000400 */
#define RTC_TIME_MINU_3                                             (0x8UL << RTC_TIME_MINU_Pos)                                   /*!< 0x00000800 */
#define RTC_TIME_SECT_Pos                                           (4U)
#define RTC_TIME_SECT_Msk                                           (0x7UL << RTC_TIME_SECT_Pos)                                   /*!< 0x00000070 */
#define RTC_TIME_SECT                                               RTC_TIME_SECT_Msk
#define RTC_TIME_SECT_0                                             (0x1UL << RTC_TIME_SECT_Pos)                                   /*!< 0x00000010 */
#define RTC_TIME_SECT_1                                             (0x2UL << RTC_TIME_SECT_Pos)                                   /*!< 0x00000020 */
#define RTC_TIME_SECT_2                                             (0x4UL << RTC_TIME_SECT_Pos)                                   /*!< 0x00000040 */
#define RTC_TIME_SECU_Pos                                           (0U)
#define RTC_TIME_SECU_Msk                                           (0xFUL << RTC_TIME_SECU_Pos)                                   /*!< 0x0000000F */
#define RTC_TIME_SECU                                               RTC_TIME_SECU_Msk
#define RTC_TIME_SECU_0                                             (0x1UL << RTC_TIME_SECU_Pos)                                   /*!< 0x00000001 */
#define RTC_TIME_SECU_1                                             (0x2UL << RTC_TIME_SECU_Pos)                                   /*!< 0x00000002 */
#define RTC_TIME_SECU_2                                             (0x4UL << RTC_TIME_SECU_Pos)                                   /*!< 0x00000004 */
#define RTC_TIME_SECU_3                                             (0x8UL << RTC_TIME_SECU_Pos)                                   /*!< 0x00000008 */

/********************  Bits definition for RTC_DATE register  *******************/
#define RTC_DATE_YRT_Pos                                            (20U)
#define RTC_DATE_YRT_Msk                                            (0xFUL << RTC_DATE_YRT_Pos)                                    /*!< 0x00F00000 */
#define RTC_DATE_YRT                                                RTC_DATE_YRT_Msk
#define RTC_DATE_YRT_0                                              (0x1UL << RTC_DATE_YRT_Pos)                                    /*!< 0x00100000 */
#define RTC_DATE_YRT_1                                              (0x2UL << RTC_DATE_YRT_Pos)                                    /*!< 0x00200000 */
#define RTC_DATE_YRT_2                                              (0x4UL << RTC_DATE_YRT_Pos)                                    /*!< 0x00400000 */
#define RTC_DATE_YRT_3                                              (0x8UL << RTC_DATE_YRT_Pos)                                    /*!< 0x00800000 */
#define RTC_DATE_YRU_Pos                                            (16U)
#define RTC_DATE_YRU_Msk                                            (0xFUL << RTC_DATE_YRU_Pos)                                    /*!< 0x000F0000 */
#define RTC_DATE_YRU                                                RTC_DATE_YRU_Msk
#define RTC_DATE_YRU_0                                              (0x1UL << RTC_DATE_YRU_Pos)                                    /*!< 0x00010000 */
#define RTC_DATE_YRU_1                                              (0x2UL << RTC_DATE_YRU_Pos)                                    /*!< 0x00020000 */
#define RTC_DATE_YRU_2                                              (0x4UL << RTC_DATE_YRU_Pos)                                    /*!< 0x00040000 */
#define RTC_DATE_YRU_3                                              (0x8UL << RTC_DATE_YRU_Pos)                                    /*!< 0x00080000 */
#define RTC_DATE_WEEKSEL_Pos                                        (13U)
#define RTC_DATE_WEEKSEL_Msk                                        (0x7UL << RTC_DATE_WEEKSEL_Pos)                                /*!< 0x0000E000 */
#define RTC_DATE_WEEKSEL                                            RTC_DATE_WEEKSEL_Msk
#define RTC_DATE_WEEKSEL_0                                          (0x1UL << RTC_DATE_WEEKSEL_Pos)                                /*!< 0x00002000 */
#define RTC_DATE_WEEKSEL_1                                          (0x2UL << RTC_DATE_WEEKSEL_Pos)                                /*!< 0x00004000 */
#define RTC_DATE_WEEKSEL_2                                          (0x4UL << RTC_DATE_WEEKSEL_Pos)                                /*!< 0x00008000 */
#define RTC_DATE_MONT_Pos                                           (12U)
#define RTC_DATE_MONT_Msk                                           (0x1UL << RTC_DATE_MONT_Pos)                                   /*!< 0x00001000 */
#define RTC_DATE_MONT                                               RTC_DATE_MONT_Msk
#define RTC_DATE_MONU_Pos                                           (8U)
#define RTC_DATE_MONU_Msk                                           (0xFUL << RTC_DATE_MONU_Pos)                                   /*!< 0x00000F00 */
#define RTC_DATE_MONU                                               RTC_DATE_MONU_Msk
#define RTC_DATE_MONU_0                                             (0x1UL << RTC_DATE_MONU_Pos)                                   /*!< 0x00000100 */
#define RTC_DATE_MONU_1                                             (0x2UL << RTC_DATE_MONU_Pos)                                   /*!< 0x00000200 */
#define RTC_DATE_MONU_2                                             (0x4UL << RTC_DATE_MONU_Pos)                                   /*!< 0x00000400 */
#define RTC_DATE_MONU_3                                             (0x8UL << RTC_DATE_MONU_Pos)                                   /*!< 0x00000800 */
#define RTC_DATE_DAYT_Pos                                           (4U)
#define RTC_DATE_DAYT_Msk                                           (0x3UL << RTC_DATE_DAYT_Pos)                                   /*!< 0x00000030 */
#define RTC_DATE_DAYT                                               RTC_DATE_DAYT_Msk
#define RTC_DATE_DAYT_0                                             (0x1UL << RTC_DATE_DAYT_Pos)                                   /*!< 0x00000010 */
#define RTC_DATE_DAYT_1                                             (0x2UL << RTC_DATE_DAYT_Pos)                                   /*!< 0x00000020 */
#define RTC_DATE_DAYU_Pos                                           (0U)
#define RTC_DATE_DAYU_Msk                                           (0xFUL << RTC_DATE_DAYU_Pos)                                   /*!< 0x0000000F */
#define RTC_DATE_DAYU                                               RTC_DATE_DAYU_Msk
#define RTC_DATE_DAYU_0                                             (0x1UL << RTC_DATE_DAYU_Pos)                                   /*!< 0x00000001 */
#define RTC_DATE_DAYU_1                                             (0x2UL << RTC_DATE_DAYU_Pos)                                   /*!< 0x00000002 */
#define RTC_DATE_DAYU_2                                             (0x4UL << RTC_DATE_DAYU_Pos)                                   /*!< 0x00000004 */
#define RTC_DATE_DAYU_3                                             (0x8UL << RTC_DATE_DAYU_Pos)                                   /*!< 0x00000008 */

/********************  Bits definition for RTC_CTRL register  *******************/
#define RTC_CTRL_CALOEN_Pos                                         (23U)
#define RTC_CTRL_CALOEN_Msk                                         (0x1UL << RTC_CTRL_CALOEN_Pos)                                 /*!< 0x00800000 */
#define RTC_CTRL_CALOEN                                             RTC_CTRL_CALOEN_Msk
#define RTC_CTRL_OUTSEL_Pos                                         (21U)
#define RTC_CTRL_OUTSEL_Msk                                         (0x3UL << RTC_CTRL_OUTSEL_Pos)                                 /*!< 0x00600000 */
#define RTC_CTRL_OUTSEL                                             RTC_CTRL_OUTSEL_Msk
#define RTC_CTRL_OUTSEL_0                                           (0x1UL << RTC_CTRL_OUTSEL_Pos)                                 /*!< 0x00200000 */
#define RTC_CTRL_OUTSEL_1                                           (0x2UL << RTC_CTRL_OUTSEL_Pos)                                 /*!< 0x00400000 */
#define RTC_CTRL_POLCFG_Pos                                         (20U)
#define RTC_CTRL_POLCFG_Msk                                         (0x1UL << RTC_CTRL_POLCFG_Pos)                                 /*!< 0x00100000 */
#define RTC_CTRL_POLCFG                                             RTC_CTRL_POLCFG_Msk
#define RTC_CTRL_CALOSEL_Pos                                        (19U)
#define RTC_CTRL_CALOSEL_Msk                                        (0x1UL << RTC_CTRL_CALOSEL_Pos)                                /*!< 0x00080000 */
#define RTC_CTRL_CALOSEL                                            RTC_CTRL_CALOSEL_Msk
#define RTC_CTRL_BAKP_Pos                                           (18U)
#define RTC_CTRL_BAKP_Msk                                           (0x1UL << RTC_CTRL_BAKP_Pos)                                   /*!< 0x00040000 */
#define RTC_CTRL_BAKP                                               RTC_CTRL_BAKP_Msk
#define RTC_CTRL_WTCCFG_Pos                                         (17U)
#define RTC_CTRL_WTCCFG_Msk                                         (0x1UL << RTC_CTRL_WTCCFG_Pos)                                 /*!< 0x00020000 */
#define RTC_CTRL_WTCCFG                                             RTC_CTRL_WTCCFG_Msk
#define RTC_CTRL_STCCFG_Pos                                         (16U)
#define RTC_CTRL_STCCFG_Msk                                         (0x1UL << RTC_CTRL_STCCFG_Pos)                                 /*!< 0x00010000 */
#define RTC_CTRL_STCCFG                                             RTC_CTRL_STCCFG_Msk
#define RTC_CTRL_TSIEN_Pos                                          (15U)
#define RTC_CTRL_TSIEN_Msk                                          (0x1UL << RTC_CTRL_TSIEN_Pos)                                  /*!< 0x00008000 */
#define RTC_CTRL_TSIEN                                              RTC_CTRL_TSIEN_Msk
#define RTC_CTRL_WUTIEN_Pos                                         (14U)
#define RTC_CTRL_WUTIEN_Msk                                         (0x1UL << RTC_CTRL_WUTIEN_Pos)                                 /*!< 0x00004000 */
#define RTC_CTRL_WUTIEN                                             RTC_CTRL_WUTIEN_Msk
#define RTC_CTRL_ALRBIEN_Pos                                        (13U)
#define RTC_CTRL_ALRBIEN_Msk                                        (0x1UL << RTC_CTRL_ALRBIEN_Pos)                                /*!< 0x00002000 */
#define RTC_CTRL_ALRBIEN                                            RTC_CTRL_ALRBIEN_Msk
#define RTC_CTRL_ALRAIEN_Pos                                        (12U)
#define RTC_CTRL_ALRAIEN_Msk                                        (0x1UL << RTC_CTRL_ALRAIEN_Pos)                                /*!< 0x00001000 */
#define RTC_CTRL_ALRAIEN                                            RTC_CTRL_ALRAIEN_Msk
#define RTC_CTRL_TSEN_Pos                                           (11U)
#define RTC_CTRL_TSEN_Msk                                           (0x1UL << RTC_CTRL_TSEN_Pos)                                   /*!< 0x00000800 */
#define RTC_CTRL_TSEN                                               RTC_CTRL_TSEN_Msk
#define RTC_CTRL_WUTEN_Pos                                          (10U)
#define RTC_CTRL_WUTEN_Msk                                          (0x1UL << RTC_CTRL_WUTEN_Pos)                                  /*!< 0x00000400 */
#define RTC_CTRL_WUTEN                                              RTC_CTRL_WUTEN_Msk
#define RTC_CTRL_ALRBEN_Pos                                         (9U)
#define RTC_CTRL_ALRBEN_Msk                                         (0x1UL << RTC_CTRL_ALRBEN_Pos)                                 /*!< 0x00000200 */
#define RTC_CTRL_ALRBEN                                             RTC_CTRL_ALRBEN_Msk
#define RTC_CTRL_ALRAEN_Pos                                         (8U)
#define RTC_CTRL_ALRAEN_Msk                                         (0x1UL << RTC_CTRL_ALRAEN_Pos)                                 /*!< 0x00000100 */
#define RTC_CTRL_ALRAEN                                             RTC_CTRL_ALRAEN_Msk
#define RTC_CTRL_DCALEN_Pos                                         (7U)
#define RTC_CTRL_DCALEN_Msk                                         (0x1UL << RTC_CTRL_DCALEN_Pos)                                 /*!< 0x00000080 */
#define RTC_CTRL_DCALEN                                             RTC_CTRL_DCALEN_Msk
#define RTC_CTRL_TIMEFCFG_Pos                                       (6U)
#define RTC_CTRL_TIMEFCFG_Msk                                       (0x1UL << RTC_CTRL_TIMEFCFG_Pos)                               /*!< 0x00000040 */
#define RTC_CTRL_TIMEFCFG                                           RTC_CTRL_TIMEFCFG_Msk
#define RTC_CTRL_RCMCFG_Pos                                         (5U)
#define RTC_CTRL_RCMCFG_Msk                                         (0x1UL << RTC_CTRL_RCMCFG_Pos)                                 /*!< 0x00000020 */
#define RTC_CTRL_RCMCFG                                             RTC_CTRL_RCMCFG_Msk
#define RTC_CTRL_RCLKDEN_Pos                                        (4U)
#define RTC_CTRL_RCLKDEN_Msk                                        (0x1UL << RTC_CTRL_RCLKDEN_Pos)                                /*!< 0x00000010 */
#define RTC_CTRL_RCLKDEN                                            RTC_CTRL_RCLKDEN_Msk
#define RTC_CTRL_TSETECFG_Pos                                       (3U)
#define RTC_CTRL_TSETECFG_Msk                                       (0x1UL << RTC_CTRL_TSETECFG_Pos)                               /*!< 0x00000008 */
#define RTC_CTRL_TSETECFG                                           RTC_CTRL_TSETECFG_Msk
#define RTC_CTRL_WUCLKSEL_Pos                                       (0U)
#define RTC_CTRL_WUCLKSEL_Msk                                       (0x7UL << RTC_CTRL_WUCLKSEL_Pos)                               /*!< 0x00000007 */
#define RTC_CTRL_WUCLKSEL                                           RTC_CTRL_WUCLKSEL_Msk
#define RTC_CTRL_WUCLKSEL_0                                         (0x1UL << RTC_CTRL_WUCLKSEL_Pos)                               /*!< 0x00000001 */
#define RTC_CTRL_WUCLKSEL_1                                         (0x2UL << RTC_CTRL_WUCLKSEL_Pos)                               /*!< 0x00000002 */
#define RTC_CTRL_WUCLKSEL_2                                         (0x4UL << RTC_CTRL_WUCLKSEL_Pos)                               /*!< 0x00000004 */

/* Legacy defines */
#define RTC_CTRL_BCK                                                RTC_CTRL_BAKP

/********************  Bits definition for RTC_STS register  ******************/
#define RTC_STS_RCALPFLG_Pos                                        (16U)
#define RTC_STS_RCALPFLG_Msk                                        (0x1UL << RTC_STS_RCALPFLG_Pos)                                /*!< 0x00010000 */
#define RTC_STS_RCALPFLG                                            RTC_STS_RCALPFLG_Msk
#define RTC_STS_TP1FLG_Pos                                          (13U)
#define RTC_STS_TP1FLG_Msk                                          (0x1UL << RTC_STS_TP1FLG_Pos)                                  /*!< 0x00002000 */
#define RTC_STS_TP1FLG                                              RTC_STS_TP1FLG_Msk
#define RTC_STS_TP2FLG_Pos                                          (14U)
#define RTC_STS_TP2FLG_Msk                                          (0x1UL << RTC_STS_TP2FLG_Pos)                                  /*!< 0x00004000 */
#define RTC_STS_TP2FLG                                              RTC_STS_TP2FLG_Msk
#define RTC_STS_TSOVRFLG_Pos                                        (12U)
#define RTC_STS_TSOVRFLG_Msk                                        (0x1UL << RTC_STS_TSOVRFLG_Pos)                                /*!< 0x00001000 */
#define RTC_STS_TSOVRFLG                                            RTC_STS_TSOVRFLG_Msk
#define RTC_STS_TSFLG_Pos                                           (11U)
#define RTC_STS_TSFLG_Msk                                           (0x1UL << RTC_STS_TSFLG_Pos)                                   /*!< 0x00000800 */
#define RTC_STS_TSFLG                                               RTC_STS_TSFLG_Msk
#define RTC_STS_WUTFLG_Pos                                          (10U)
#define RTC_STS_WUTFLG_Msk                                          (0x1UL << RTC_STS_WUTFLG_Pos)                                  /*!< 0x00000400 */
#define RTC_STS_WUTFLG                                              RTC_STS_WUTFLG_Msk
#define RTC_STS_ALRBFLG_Pos                                         (9U)
#define RTC_STS_ALRBFLG_Msk                                         (0x1UL << RTC_STS_ALRBFLG_Pos)                                 /*!< 0x00000200 */
#define RTC_STS_ALRBFLG                                             RTC_STS_ALRBFLG_Msk
#define RTC_STS_ALRAFLG_Pos                                         (8U)
#define RTC_STS_ALRAFLG_Msk                                         (0x1UL << RTC_STS_ALRAFLG_Pos)                                 /*!< 0x00000100 */
#define RTC_STS_ALRAFLG                                             RTC_STS_ALRAFLG_Msk
#define RTC_STS_INITEN_Pos                                          (7U)
#define RTC_STS_INITEN_Msk                                          (0x1UL << RTC_STS_INITEN_Pos)                                  /*!< 0x00000080 */
#define RTC_STS_INITEN                                              RTC_STS_INITEN_Msk
#define RTC_STS_RINITFLG_Pos                                        (6U)
#define RTC_STS_RINITFLG_Msk                                        (0x1UL << RTC_STS_RINITFLG_Pos)                                /*!< 0x00000040 */
#define RTC_STS_RINITFLG                                            RTC_STS_RINITFLG_Msk
#define RTC_STS_RSFLG_Pos                                           (5U)
#define RTC_STS_RSFLG_Msk                                           (0x1UL << RTC_STS_RSFLG_Pos)                                   /*!< 0x00000020 */
#define RTC_STS_RSFLG                                               RTC_STS_RSFLG_Msk
#define RTC_STS_INITSFLG_Pos                                        (4U)
#define RTC_STS_INITSFLG_Msk                                        (0x1UL << RTC_STS_INITSFLG_Pos)                                /*!< 0x00000010 */
#define RTC_STS_INITSFLG                                            RTC_STS_INITSFLG_Msk
#define RTC_STS_SOPFLG_Pos                                          (3U)
#define RTC_STS_SOPFLG_Msk                                          (0x1UL << RTC_STS_SOPFLG_Pos)                                  /*!< 0x00000008 */
#define RTC_STS_SOPFLG                                              RTC_STS_SOPFLG_Msk
#define RTC_STS_WUTWFLG_Pos                                         (2U)
#define RTC_STS_WUTWFLG_Msk                                         (0x1UL << RTC_STS_WUTWFLG_Pos)                                 /*!< 0x00000004 */
#define RTC_STS_WUTWFLG                                             RTC_STS_WUTWFLG_Msk
#define RTC_STS_ALRBWFLG_Pos                                        (1U)
#define RTC_STS_ALRBWFLG_Msk                                        (0x1UL << RTC_STS_ALRBWFLG_Pos)                                /*!< 0x00000002 */
#define RTC_STS_ALRBWFLG                                            RTC_STS_ALRBWFLG_Msk
#define RTC_STS_ALRAWFLG_Pos                                        (0U)
#define RTC_STS_ALRAWFLG_Msk                                        (0x1UL << RTC_STS_ALRAWFLG_Pos)                                /*!< 0x00000001 */
#define RTC_STS_ALRAWFLG                                            RTC_STS_ALRAWFLG_Msk

/********************  Bits definition for RTC_PSC register  *****************/
#define RTC_PSC_APSC_Pos                                            (16U)
#define RTC_PSC_APSC_Msk                                            (0x7FUL << RTC_PSC_APSC_Pos)                                   /*!< 0x007F0000 */
#define RTC_PSC_APSC                                                RTC_PSC_APSC_Msk
#define RTC_PSC_SPSC_Pos                                            (0U)
#define RTC_PSC_SPSC_Msk                                            (0x7FFFUL << RTC_PSC_SPSC_Pos)                                 /*!< 0x00007FFF */
#define RTC_PSC_SPSC                                                RTC_PSC_SPSC_Msk

/********************  Bits definition for RTC_AUTORLD register  *****************/
#define RTC_AUTORLD_WUAUTORE_Pos                                    (0U)
#define RTC_AUTORLD_WUAUTORE_Msk                                    (0xFFFFUL << RTC_AUTORLD_WUAUTORE_Pos)                         /*!< 0x0000FFFF */
#define RTC_AUTORLD_WUAUTORE                                        RTC_AUTORLD_WUAUTORE_Msk

/********************  Bits definition for RTC_DCAL register  ***************/
#define RTC_DCAL_DCALCFG_Pos                                        (7U)
#define RTC_DCAL_DCALCFG_Msk                                        (0x1UL << RTC_DCAL_DCALCFG_Pos)                                /*!< 0x00000080 */
#define RTC_DCAL_DCALCFG                                            RTC_DCAL_DCALCFG_Msk
#define RTC_DCAL_DCAL_Pos                                           (0U)
#define RTC_DCAL_DCAL_Msk                                           (0x1FUL << RTC_DCAL_DCAL_Pos)                                  /*!< 0x0000001F */
#define RTC_DCAL_DCAL                                               RTC_DCAL_DCAL_Msk

/********************  Bits definition for RTC_ALRMA register  ***************/
#define RTC_ALRMA_DATEMEN_Pos                                       (31U)
#define RTC_ALRMA_DATEMEN_Msk                                       (0x1UL << RTC_ALRMA_DATEMEN_Pos)                               /*!< 0x80000000 */
#define RTC_ALRMA_DATEMEN                                           RTC_ALRMA_DATEMEN_Msk
#define RTC_ALRMA_WEEKSEL_Pos                                       (30U)
#define RTC_ALRMA_WEEKSEL_Msk                                       (0x1UL << RTC_ALRMA_WEEKSEL_Pos)                               /*!< 0x40000000 */
#define RTC_ALRMA_WEEKSEL                                           RTC_ALRMA_WEEKSEL_Msk
#define RTC_ALRMA_DAYT_Pos                                          (28U)
#define RTC_ALRMA_DAYT_Msk                                          (0x3UL << RTC_ALRMA_DAYT_Pos)                                  /*!< 0x30000000 */
#define RTC_ALRMA_DAYT                                              RTC_ALRMA_DAYT_Msk
#define RTC_ALRMA_DAYT_0                                            (0x1UL << RTC_ALRMA_DAYT_Pos)                                  /*!< 0x10000000 */
#define RTC_ALRMA_DAYT_1                                            (0x2UL << RTC_ALRMA_DAYT_Pos)                                  /*!< 0x20000000 */
#define RTC_ALRMA_DAYU_Pos                                          (24U)
#define RTC_ALRMA_DAYU_Msk                                          (0xFUL << RTC_ALRMA_DAYU_Pos)                                  /*!< 0x0F000000 */
#define RTC_ALRMA_DAYU                                              RTC_ALRMA_DAYU_Msk
#define RTC_ALRMA_DAYU_0                                            (0x1UL << RTC_ALRMA_DAYU_Pos)                                  /*!< 0x01000000 */
#define RTC_ALRMA_DAYU_1                                            (0x2UL << RTC_ALRMA_DAYU_Pos)                                  /*!< 0x02000000 */
#define RTC_ALRMA_DAYU_2                                            (0x4UL << RTC_ALRMA_DAYU_Pos)                                  /*!< 0x04000000 */
#define RTC_ALRMA_DAYU_3                                            (0x8UL << RTC_ALRMA_DAYU_Pos)                                  /*!< 0x08000000 */
#define RTC_ALRMA_HRMEN_Pos                                         (23U)
#define RTC_ALRMA_HRMEN_Msk                                         (0x1UL << RTC_ALRMA_HRMEN_Pos)                                 /*!< 0x00800000 */
#define RTC_ALRMA_HRMEN                                             RTC_ALRMA_HRMEN_Msk
#define RTC_ALRMA_TIMEFCFG_Pos                                      (22U)
#define RTC_ALRMA_TIMEFCFG_Msk                                      (0x1UL << RTC_ALRMA_TIMEFCFG_Pos)                              /*!< 0x00400000 */
#define RTC_ALRMA_TIMEFCFG                                          RTC_ALRMA_TIMEFCFG_Msk
#define RTC_ALRMA_HRT_Pos                                           (20U)
#define RTC_ALRMA_HRT_Msk                                           (0x3UL << RTC_ALRMA_HRT_Pos)                                   /*!< 0x00300000 */
#define RTC_ALRMA_HRT                                               RTC_ALRMA_HRT_Msk
#define RTC_ALRMA_HRT_0                                             (0x1UL << RTC_ALRMA_HRT_Pos)                                   /*!< 0x00100000 */
#define RTC_ALRMA_HRT_1                                             (0x2UL << RTC_ALRMA_HRT_Pos)                                   /*!< 0x00200000 */
#define RTC_ALRMA_HRU_Pos                                           (16U)
#define RTC_ALRMA_HRU_Msk                                           (0xFUL << RTC_ALRMA_HRU_Pos)                                   /*!< 0x000F0000 */
#define RTC_ALRMA_HRU                                               RTC_ALRMA_HRU_Msk
#define RTC_ALRMA_HRU_0                                             (0x1UL << RTC_ALRMA_HRU_Pos)                                   /*!< 0x00010000 */
#define RTC_ALRMA_HRU_1                                             (0x2UL << RTC_ALRMA_HRU_Pos)                                   /*!< 0x00020000 */
#define RTC_ALRMA_HRU_2                                             (0x4UL << RTC_ALRMA_HRU_Pos)                                   /*!< 0x00040000 */
#define RTC_ALRMA_HRU_3                                             (0x8UL << RTC_ALRMA_HRU_Pos)                                   /*!< 0x00080000 */
#define RTC_ALRMA_MINMEN_Pos                                        (15U)
#define RTC_ALRMA_MINMEN_Msk                                        (0x1UL << RTC_ALRMA_MINMEN_Pos)                                /*!< 0x00008000 */
#define RTC_ALRMA_MINMEN                                            RTC_ALRMA_MINMEN_Msk
#define RTC_ALRMA_MINT_Pos                                          (12U)
#define RTC_ALRMA_MINT_Msk                                          (0x7UL << RTC_ALRMA_MINT_Pos)                                  /*!< 0x00007000 */
#define RTC_ALRMA_MINT                                              RTC_ALRMA_MINT_Msk
#define RTC_ALRMA_MINT_0                                            (0x1UL << RTC_ALRMA_MINT_Pos)                                  /*!< 0x00001000 */
#define RTC_ALRMA_MINT_1                                            (0x2UL << RTC_ALRMA_MINT_Pos)                                  /*!< 0x00002000 */
#define RTC_ALRMA_MINT_2                                            (0x4UL << RTC_ALRMA_MINT_Pos)                                  /*!< 0x00004000 */
#define RTC_ALRMA_MINU_Pos                                          (8U)
#define RTC_ALRMA_MINU_Msk                                          (0xFUL << RTC_ALRMA_MINU_Pos)                                  /*!< 0x00000F00 */
#define RTC_ALRMA_MINU                                              RTC_ALRMA_MINU_Msk
#define RTC_ALRMA_MINU_0                                            (0x1UL << RTC_ALRMA_MINU_Pos)                                  /*!< 0x00000100 */
#define RTC_ALRMA_MINU_1                                            (0x2UL << RTC_ALRMA_MINU_Pos)                                  /*!< 0x00000200 */
#define RTC_ALRMA_MINU_2                                            (0x4UL << RTC_ALRMA_MINU_Pos)                                  /*!< 0x00000400 */
#define RTC_ALRMA_MINU_3                                            (0x8UL << RTC_ALRMA_MINU_Pos)                                  /*!< 0x00000800 */
#define RTC_ALRMA_SECMEN_Pos                                        (7U)
#define RTC_ALRMA_SECMEN_Msk                                        (0x1UL << RTC_ALRMA_SECMEN_Pos)                                /*!< 0x00000080 */
#define RTC_ALRMA_SECMEN                                            RTC_ALRMA_SECMEN_Msk
#define RTC_ALRMA_SECT_Pos                                          (4U)
#define RTC_ALRMA_SECT_Msk                                          (0x7UL << RTC_ALRMA_SECT_Pos)                                  /*!< 0x00000070 */
#define RTC_ALRMA_SECT                                              RTC_ALRMA_SECT_Msk
#define RTC_ALRMA_SECT_0                                            (0x1UL << RTC_ALRMA_SECT_Pos)                                  /*!< 0x00000010 */
#define RTC_ALRMA_SECT_1                                            (0x2UL << RTC_ALRMA_SECT_Pos)                                  /*!< 0x00000020 */
#define RTC_ALRMA_SECT_2                                            (0x4UL << RTC_ALRMA_SECT_Pos)                                  /*!< 0x00000040 */
#define RTC_ALRMA_SECU_Pos                                          (0U)
#define RTC_ALRMA_SECU_Msk                                          (0xFUL << RTC_ALRMA_SECU_Pos)                                  /*!< 0x0000000F */
#define RTC_ALRMA_SECU                                              RTC_ALRMA_SECU_Msk
#define RTC_ALRMA_SECU_0                                            (0x1UL << RTC_ALRMA_SECU_Pos)                                  /*!< 0x00000001 */
#define RTC_ALRMA_SECU_1                                            (0x2UL << RTC_ALRMA_SECU_Pos)                                  /*!< 0x00000002 */
#define RTC_ALRMA_SECU_2                                            (0x4UL << RTC_ALRMA_SECU_Pos)                                  /*!< 0x00000004 */
#define RTC_ALRMA_SECU_3                                            (0x8UL << RTC_ALRMA_SECU_Pos)                                  /*!< 0x00000008 */

/********************  Bits definition for RTC_ALRMB register  ***************/
#define RTC_ALRMB_DATEMEN_Pos                                       (31U)
#define RTC_ALRMB_DATEMEN_Msk                                       (0x1UL << RTC_ALRMB_DATEMEN_Pos)                               /*!< 0x80000000 */
#define RTC_ALRMB_DATEMEN                                           RTC_ALRMB_DATEMEN_Msk
#define RTC_ALRMB_WEEKSEL_Pos                                       (30U)
#define RTC_ALRMB_WEEKSEL_Msk                                       (0x1UL << RTC_ALRMB_WEEKSEL_Pos)                               /*!< 0x40000000 */
#define RTC_ALRMB_WEEKSEL                                           RTC_ALRMB_WEEKSEL_Msk
#define RTC_ALRMB_DAYT_Pos                                          (28U)
#define RTC_ALRMB_DAYT_Msk                                          (0x3UL << RTC_ALRMB_DAYT_Pos)                                  /*!< 0x30000000 */
#define RTC_ALRMB_DAYT                                              RTC_ALRMB_DAYT_Msk
#define RTC_ALRMB_DAYT_0                                            (0x1UL << RTC_ALRMB_DAYT_Pos)                                  /*!< 0x10000000 */
#define RTC_ALRMB_DAYT_1                                            (0x2UL << RTC_ALRMB_DAYT_Pos)                                  /*!< 0x20000000 */
#define RTC_ALRMB_DAYU_Pos                                          (24U)
#define RTC_ALRMB_DAYU_Msk                                          (0xFUL << RTC_ALRMB_DAYU_Pos)                                  /*!< 0x0F000000 */
#define RTC_ALRMB_DAYU                                              RTC_ALRMB_DAYU_Msk
#define RTC_ALRMB_DAYU_0                                            (0x1UL << RTC_ALRMB_DAYU_Pos)                                  /*!< 0x01000000 */
#define RTC_ALRMB_DAYU_1                                            (0x2UL << RTC_ALRMB_DAYU_Pos)                                  /*!< 0x02000000 */
#define RTC_ALRMB_DAYU_2                                            (0x4UL << RTC_ALRMB_DAYU_Pos)                                  /*!< 0x04000000 */
#define RTC_ALRMB_DAYU_3                                            (0x8UL << RTC_ALRMB_DAYU_Pos)                                  /*!< 0x08000000 */
#define RTC_ALRMB_HRMEN_Pos                                         (23U)
#define RTC_ALRMB_HRMEN_Msk                                         (0x1UL << RTC_ALRMB_HRMEN_Pos)                                 /*!< 0x00800000 */
#define RTC_ALRMB_HRMEN                                             RTC_ALRMB_HRMEN_Msk
#define RTC_ALRMB_TIMEFCFG_Pos                                      (22U)
#define RTC_ALRMB_TIMEFCFG_Msk                                      (0x1UL << RTC_ALRMB_TIMEFCFG_Pos)                              /*!< 0x00400000 */
#define RTC_ALRMB_TIMEFCFG                                          RTC_ALRMB_TIMEFCFG_Msk
#define RTC_ALRMB_HRT_Pos                                           (20U)
#define RTC_ALRMB_HRT_Msk                                           (0x3UL << RTC_ALRMB_HRT_Pos)                                   /*!< 0x00300000 */
#define RTC_ALRMB_HRT                                               RTC_ALRMB_HRT_Msk
#define RTC_ALRMB_HRT_0                                             (0x1UL << RTC_ALRMB_HRT_Pos)                                   /*!< 0x00100000 */
#define RTC_ALRMB_HRT_1                                             (0x2UL << RTC_ALRMB_HRT_Pos)                                   /*!< 0x00200000 */
#define RTC_ALRMB_HRU_Pos                                           (16U)
#define RTC_ALRMB_HRU_Msk                                           (0xFUL << RTC_ALRMB_HRU_Pos)                                   /*!< 0x000F0000 */
#define RTC_ALRMB_HRU                                               RTC_ALRMB_HRU_Msk
#define RTC_ALRMB_HRU_0                                             (0x1UL << RTC_ALRMB_HRU_Pos)                                   /*!< 0x00010000 */
#define RTC_ALRMB_HRU_1                                             (0x2UL << RTC_ALRMB_HRU_Pos)                                   /*!< 0x00020000 */
#define RTC_ALRMB_HRU_2                                             (0x4UL << RTC_ALRMB_HRU_Pos)                                   /*!< 0x00040000 */
#define RTC_ALRMB_HRU_3                                             (0x8UL << RTC_ALRMB_HRU_Pos)                                   /*!< 0x00080000 */
#define RTC_ALRMB_MINMEN_Pos                                        (15U)
#define RTC_ALRMB_MINMEN_Msk                                        (0x1UL << RTC_ALRMB_MINMEN_Pos)                                /*!< 0x00008000 */
#define RTC_ALRMB_MINMEN                                            RTC_ALRMB_MINMEN_Msk
#define RTC_ALRMB_MINT_Pos                                          (12U)
#define RTC_ALRMB_MINT_Msk                                          (0x7UL << RTC_ALRMB_MINT_Pos)                                  /*!< 0x00007000 */
#define RTC_ALRMB_MINT                                              RTC_ALRMB_MINT_Msk
#define RTC_ALRMB_MINT_0                                            (0x1UL << RTC_ALRMB_MINT_Pos)                                  /*!< 0x00001000 */
#define RTC_ALRMB_MINT_1                                            (0x2UL << RTC_ALRMB_MINT_Pos)                                  /*!< 0x00002000 */
#define RTC_ALRMB_MINT_2                                            (0x4UL << RTC_ALRMB_MINT_Pos)                                  /*!< 0x00004000 */
#define RTC_ALRMB_MINU_Pos                                          (8U)
#define RTC_ALRMB_MINU_Msk                                          (0xFUL << RTC_ALRMB_MINU_Pos)                                  /*!< 0x00000F00 */
#define RTC_ALRMB_MINU                                              RTC_ALRMB_MINU_Msk
#define RTC_ALRMB_MINU_0                                            (0x1UL << RTC_ALRMB_MINU_Pos)                                  /*!< 0x00000100 */
#define RTC_ALRMB_MINU_1                                            (0x2UL << RTC_ALRMB_MINU_Pos)                                  /*!< 0x00000200 */
#define RTC_ALRMB_MINU_2                                            (0x4UL << RTC_ALRMB_MINU_Pos)                                  /*!< 0x00000400 */
#define RTC_ALRMB_MINU_3                                            (0x8UL << RTC_ALRMB_MINU_Pos)                                  /*!< 0x00000800 */
#define RTC_ALRMB_SECMEN_Pos                                        (7U)
#define RTC_ALRMB_SECMEN_Msk                                        (0x1UL << RTC_ALRMB_SECMEN_Pos)                                /*!< 0x00000080 */
#define RTC_ALRMB_SECMEN                                            RTC_ALRMB_SECMEN_Msk
#define RTC_ALRMB_SECT_Pos                                          (4U)
#define RTC_ALRMB_SECT_Msk                                          (0x7UL << RTC_ALRMB_SECT_Pos)                                  /*!< 0x00000070 */
#define RTC_ALRMB_SECT                                              RTC_ALRMB_SECT_Msk
#define RTC_ALRMB_SECT_0                                            (0x1UL << RTC_ALRMB_SECT_Pos)                                  /*!< 0x00000010 */
#define RTC_ALRMB_SECT_1                                            (0x2UL << RTC_ALRMB_SECT_Pos)                                  /*!< 0x00000020 */
#define RTC_ALRMB_SECT_2                                            (0x4UL << RTC_ALRMB_SECT_Pos)                                  /*!< 0x00000040 */
#define RTC_ALRMB_SECU_Pos                                          (0U)
#define RTC_ALRMB_SECU_Msk                                          (0xFUL << RTC_ALRMB_SECU_Pos)                                  /*!< 0x0000000F */
#define RTC_ALRMB_SECU                                              RTC_ALRMB_SECU_Msk
#define RTC_ALRMB_SECU_0                                            (0x1UL << RTC_ALRMB_SECU_Pos)                                  /*!< 0x00000001 */
#define RTC_ALRMB_SECU_1                                            (0x2UL << RTC_ALRMB_SECU_Pos)                                  /*!< 0x00000002 */
#define RTC_ALRMB_SECU_2                                            (0x4UL << RTC_ALRMB_SECU_Pos)                                  /*!< 0x00000004 */
#define RTC_ALRMB_SECU_3                                            (0x8UL << RTC_ALRMB_SECU_Pos)                                  /*!< 0x00000008 */

/********************  Bits definition for RTC_WRPROT register  ******************/
#define RTC_WRPROT_KEY_Pos                                          (0U)
#define RTC_WRPROT_KEY_Msk                                          (0xFFUL << RTC_WRPROT_KEY_Pos)                                 /*!< 0x000000FF */
#define RTC_WRPROT_KEY                                              RTC_WRPROT_KEY_Msk

/********************  Bits definition for RTC_SUBSEC register  ******************/
#define RTC_SUBSEC_SUBSEC_Pos                                       (0U)
#define RTC_SUBSEC_SUBSEC_Msk                                       (0xFFFFUL << RTC_SUBSEC_SUBSEC_Pos)                            /*!< 0x0000FFFF */
#define RTC_SUBSEC_SUBSEC                                           RTC_SUBSEC_SUBSEC_Msk

/********************  Bits definition for RTC_SHIFT register  ***************/
#define RTC_SHIFT_SFSEC_Pos                                         (0U)
#define RTC_SHIFT_SFSEC_Msk                                         (0x7FFFUL << RTC_SHIFT_SFSEC_Pos)                              /*!< 0x00007FFF */
#define RTC_SHIFT_SFSEC                                             RTC_SHIFT_SFSEC_Msk
#define RTC_SHIFT_ADD1SECEN_Pos                                     (31U)
#define RTC_SHIFT_ADD1SECEN_Msk                                     (0x1UL << RTC_SHIFT_ADD1SECEN_Pos)                             /*!< 0x80000000 */
#define RTC_SHIFT_ADD1SECEN                                         RTC_SHIFT_ADD1SECEN_Msk

/********************  Bits definition for RTC_TSTIME register  *****************/
#define RTC_TSTIME_TIMEFCFG_Pos                                     (22U)
#define RTC_TSTIME_TIMEFCFG_Msk                                     (0x1UL << RTC_TSTIME_TIMEFCFG_Pos)                             /*!< 0x00400000 */
#define RTC_TSTIME_TIMEFCFG                                         RTC_TSTIME_TIMEFCFG_Msk
#define RTC_TSTIME_HRT_Pos                                          (20U)
#define RTC_TSTIME_HRT_Msk                                          (0x3UL << RTC_TSTIME_HRT_Pos)                                  /*!< 0x00300000 */
#define RTC_TSTIME_HRT                                              RTC_TSTIME_HRT_Msk
#define RTC_TSTIME_HRT_0                                            (0x1UL << RTC_TSTIME_HRT_Pos)                                  /*!< 0x00100000 */
#define RTC_TSTIME_HRT_1                                            (0x2UL << RTC_TSTIME_HRT_Pos)                                  /*!< 0x00200000 */
#define RTC_TSTIME_HRU_Pos                                          (16U)
#define RTC_TSTIME_HRU_Msk                                          (0xFUL << RTC_TSTIME_HRU_Pos)                                  /*!< 0x000F0000 */
#define RTC_TSTIME_HRU                                              RTC_TSTIME_HRU_Msk
#define RTC_TSTIME_HRU_0                                            (0x1UL << RTC_TSTIME_HRU_Pos)                                  /*!< 0x00010000 */
#define RTC_TSTIME_HRU_1                                            (0x2UL << RTC_TSTIME_HRU_Pos)                                  /*!< 0x00020000 */
#define RTC_TSTIME_HRU_2                                            (0x4UL << RTC_TSTIME_HRU_Pos)                                  /*!< 0x00040000 */
#define RTC_TSTIME_HRU_3                                            (0x8UL << RTC_TSTIME_HRU_Pos)                                  /*!< 0x00080000 */
#define RTC_TSTIME_MINT_Pos                                         (12U)
#define RTC_TSTIME_MINT_Msk                                         (0x7UL << RTC_TSTIME_MINT_Pos)                                 /*!< 0x00007000 */
#define RTC_TSTIME_MINT                                             RTC_TSTIME_MINT_Msk
#define RTC_TSTIME_MINT_0                                           (0x1UL << RTC_TSTIME_MINT_Pos)                                 /*!< 0x00001000 */
#define RTC_TSTIME_MINT_1                                           (0x2UL << RTC_TSTIME_MINT_Pos)                                 /*!< 0x00002000 */
#define RTC_TSTIME_MINT_2                                           (0x4UL << RTC_TSTIME_MINT_Pos)                                 /*!< 0x00004000 */
#define RTC_TSTIME_MINU_Pos                                         (8U)
#define RTC_TSTIME_MINU_Msk                                         (0xFUL << RTC_TSTIME_MINU_Pos)                                 /*!< 0x00000F00 */
#define RTC_TSTIME_MINU                                             RTC_TSTIME_MINU_Msk
#define RTC_TSTIME_MINU_0                                           (0x1UL << RTC_TSTIME_MINU_Pos)                                 /*!< 0x00000100 */
#define RTC_TSTIME_MINU_1                                           (0x2UL << RTC_TSTIME_MINU_Pos)                                 /*!< 0x00000200 */
#define RTC_TSTIME_MINU_2                                           (0x4UL << RTC_TSTIME_MINU_Pos)                                 /*!< 0x00000400 */
#define RTC_TSTIME_MINU_3                                           (0x8UL << RTC_TSTIME_MINU_Pos)                                 /*!< 0x00000800 */
#define RTC_TSTIME_SECT_Pos                                         (4U)
#define RTC_TSTIME_SECT_Msk                                         (0x7UL << RTC_TSTIME_SECT_Pos)                                 /*!< 0x00000070 */
#define RTC_TSTIME_SECT                                             RTC_TSTIME_SECT_Msk
#define RTC_TSTIME_SECT_0                                           (0x1UL << RTC_TSTIME_SECT_Pos)                                 /*!< 0x00000010 */
#define RTC_TSTIME_SECT_1                                           (0x2UL << RTC_TSTIME_SECT_Pos)                                 /*!< 0x00000020 */
#define RTC_TSTIME_SECT_2                                           (0x4UL << RTC_TSTIME_SECT_Pos)                                 /*!< 0x00000040 */
#define RTC_TSTIME_SECU_Pos                                         (0U)
#define RTC_TSTIME_SECU_Msk                                         (0xFUL << RTC_TSTIME_SECU_Pos)                                 /*!< 0x0000000F */
#define RTC_TSTIME_SECU                                             RTC_TSTIME_SECU_Msk
#define RTC_TSTIME_SECU_0                                           (0x1UL << RTC_TSTIME_SECU_Pos)                                 /*!< 0x00000001 */
#define RTC_TSTIME_SECU_1                                           (0x2UL << RTC_TSTIME_SECU_Pos)                                 /*!< 0x00000002 */
#define RTC_TSTIME_SECU_2                                           (0x4UL << RTC_TSTIME_SECU_Pos)                                 /*!< 0x00000004 */
#define RTC_TSTIME_SECU_3                                           (0x8UL << RTC_TSTIME_SECU_Pos)                                 /*!< 0x00000008 */

/********************  Bits definition for RTC_TSDATE register  *****************/
#define RTC_TSDATE_WEEKSEL_Pos                                      (13U)
#define RTC_TSDATE_WEEKSEL_Msk                                      (0x7UL << RTC_TSDATE_WEEKSEL_Pos)                              /*!< 0x0000E000 */
#define RTC_TSDATE_WEEKSEL                                          RTC_TSDATE_WEEKSEL_Msk
#define RTC_TSDATE_WEEKSEL_0                                        (0x1UL << RTC_TSDATE_WEEKSEL_Pos)                              /*!< 0x00002000 */
#define RTC_TSDATE_WEEKSEL_1                                        (0x2UL << RTC_TSDATE_WEEKSEL_Pos)                              /*!< 0x00004000 */
#define RTC_TSDATE_WEEKSEL_2                                        (0x4UL << RTC_TSDATE_WEEKSEL_Pos)                              /*!< 0x00008000 */
#define RTC_TSDATE_MONT_Pos                                         (12U)
#define RTC_TSDATE_MONT_Msk                                         (0x1UL << RTC_TSDATE_MONT_Pos)                                 /*!< 0x00001000 */
#define RTC_TSDATE_MONT                                             RTC_TSDATE_MONT_Msk
#define RTC_TSDATE_MONU_Pos                                         (8U)
#define RTC_TSDATE_MONU_Msk                                         (0xFUL << RTC_TSDATE_MONU_Pos)                                 /*!< 0x00000F00 */
#define RTC_TSDATE_MONU                                             RTC_TSDATE_MONU_Msk
#define RTC_TSDATE_MONU_0                                           (0x1UL << RTC_TSDATE_MONU_Pos)                                 /*!< 0x00000100 */
#define RTC_TSDATE_MONU_1                                           (0x2UL << RTC_TSDATE_MONU_Pos)                                 /*!< 0x00000200 */
#define RTC_TSDATE_MONU_2                                           (0x4UL << RTC_TSDATE_MONU_Pos)                                 /*!< 0x00000400 */
#define RTC_TSDATE_MONU_3                                           (0x8UL << RTC_TSDATE_MONU_Pos)                                 /*!< 0x00000800 */
#define RTC_TSDATE_DAYT_Pos                                         (4U)
#define RTC_TSDATE_DAYT_Msk                                         (0x3UL << RTC_TSDATE_DAYT_Pos)                                 /*!< 0x00000030 */
#define RTC_TSDATE_DAYT                                             RTC_TSDATE_DAYT_Msk
#define RTC_TSDATE_DAYT_0                                           (0x1UL << RTC_TSDATE_DAYT_Pos)                                 /*!< 0x00000010 */
#define RTC_TSDATE_DAYT_1                                           (0x2UL << RTC_TSDATE_DAYT_Pos)                                 /*!< 0x00000020 */
#define RTC_TSDATE_DAYU_Pos                                         (0U)
#define RTC_TSDATE_DAYU_Msk                                         (0xFUL << RTC_TSDATE_DAYU_Pos)                                 /*!< 0x0000000F */
#define RTC_TSDATE_DAYU                                             RTC_TSDATE_DAYU_Msk
#define RTC_TSDATE_DAYU_0                                           (0x1UL << RTC_TSDATE_DAYU_Pos)                                 /*!< 0x00000001 */
#define RTC_TSDATE_DAYU_1                                           (0x2UL << RTC_TSDATE_DAYU_Pos)                                 /*!< 0x00000002 */
#define RTC_TSDATE_DAYU_2                                           (0x4UL << RTC_TSDATE_DAYU_Pos)                                 /*!< 0x00000004 */
#define RTC_TSDATE_DAYU_3                                           (0x8UL << RTC_TSDATE_DAYU_Pos)                                 /*!< 0x00000008 */

/********************  Bits definition for RTC_TSSUBSEC register  ****************/
#define RTC_TSSUBSEC_SUBSE_Pos                                      (0U)
#define RTC_TSSUBSEC_SUBSE_Msk                                      (0xFFFFUL << RTC_TSSUBSEC_SUBSE_Pos)                           /*!< 0x0000FFFF */
#define RTC_TSSUBSEC_SUBSE                                          RTC_TSSUBSEC_SUBSE_Msk

/********************  Bits definition for RTC_CAL register  *****************/
#define RTC_CAL_ICALFEN_Pos                                         (15U)
#define RTC_CAL_ICALFEN_Msk                                         (0x1UL << RTC_CAL_ICALFEN_Pos)                                 /*!< 0x00008000 */
#define RTC_CAL_ICALFEN                                             RTC_CAL_ICALFEN_Msk
#define RTC_CAL_CAL8CFG_Pos                                         (14U)
#define RTC_CAL_CAL8CFG_Msk                                         (0x1UL << RTC_CAL_CAL8CFG_Pos)                                 /*!< 0x00004000 */
#define RTC_CAL_CAL8CFG                                             RTC_CAL_CAL8CFG_Msk
#define RTC_CAL_CAL16CFG_Pos                                        (13U)
#define RTC_CAL_CAL16CFG_Msk                                        (0x1UL << RTC_CAL_CAL16CFG_Pos)                                /*!< 0x00002000 */
#define RTC_CAL_CAL16CFG                                            RTC_CAL_CAL16CFG_Msk
#define RTC_CAL_RECALF_Pos                                          (0U)
#define RTC_CAL_RECALF_Msk                                          (0x1FFUL << RTC_CAL_RECALF_Pos)                                /*!< 0x000001FF */
#define RTC_CAL_RECALF                                              RTC_CAL_RECALF_Msk
#define RTC_CAL_RECALF_0                                            (0x001UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000001 */
#define RTC_CAL_RECALF_1                                            (0x002UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000002 */
#define RTC_CAL_RECALF_2                                            (0x004UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000004 */
#define RTC_CAL_RECALF_3                                            (0x008UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000008 */
#define RTC_CAL_RECALF_4                                            (0x010UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000010 */
#define RTC_CAL_RECALF_5                                            (0x020UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000020 */
#define RTC_CAL_RECALF_6                                            (0x040UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000040 */
#define RTC_CAL_RECALF_7                                            (0x080UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000080 */
#define RTC_CAL_RECALF_8                                            (0x100UL << RTC_CAL_RECALF_Pos)                                /*!< 0x00000100 */

/********************  Bits definition for RTC_TACFG register  ****************/
#define RTC_TACFG_ALRMOT_Pos                                        (18U)
#define RTC_TACFG_ALRMOT_Msk                                        (0x1UL << RTC_TACFG_ALRMOT_Pos)                                /*!< 0x00040000 */
#define RTC_TACFG_ALRMOT                                            RTC_TACFG_ALRMOT_Msk
#define RTC_TACFG_TSMSEL_Pos                                        (17U)
#define RTC_TACFG_TSMSEL_Msk                                        (0x1UL << RTC_TACFG_TSMSEL_Pos)                                /*!< 0x00020000 */
#define RTC_TACFG_TSMSEL                                            RTC_TACFG_TSMSEL_Msk
#define RTC_TACFG_TP1MSEL_Pos                                       (16U)
#define RTC_TACFG_TP1MSEL_Msk                                       (0x1UL << RTC_TACFG_TP1MSEL_Pos)                               /*!< 0x00010000 */
#define RTC_TACFG_TP1MSEL                                           RTC_TACFG_TP1MSEL_Msk
#define RTC_TACFG_TPPUDIS_Pos                                       (15U)
#define RTC_TACFG_TPPUDIS_Msk                                       (0x1UL << RTC_TACFG_TPPUDIS_Pos)                               /*!< 0x00008000 */
#define RTC_TACFG_TPPUDIS                                           RTC_TACFG_TPPUDIS_Msk
#define RTC_TACFG_TPPRDUSEL_Pos                                     (13U)
#define RTC_TACFG_TPPRDUSEL_Msk                                     (0x3UL << RTC_TACFG_TPPRDUSEL_Pos)                             /*!< 0x00006000 */
#define RTC_TACFG_TPPRDUSEL                                         RTC_TACFG_TPPRDUSEL_Msk
#define RTC_TACFG_TPPRDUSEL_0                                       (0x1UL << RTC_TACFG_TPPRDUSEL_Pos)                             /*!< 0x00002000 */
#define RTC_TACFG_TPPRDUSEL_1                                       (0x2UL << RTC_TACFG_TPPRDUSEL_Pos)                             /*!< 0x00004000 */
#define RTC_TACFG_TPFCSEL_Pos                                       (11U)
#define RTC_TACFG_TPFCSEL_Msk                                       (0x3UL << RTC_TACFG_TPFCSEL_Pos)                               /*!< 0x00001800 */
#define RTC_TACFG_TPFCSEL                                           RTC_TACFG_TPFCSEL_Msk
#define RTC_TACFG_TPFCSEL_0                                         (0x1UL << RTC_TACFG_TPFCSEL_Pos)                               /*!< 0x00000800 */
#define RTC_TACFG_TPFCSEL_1                                         (0x2UL << RTC_TACFG_TPFCSEL_Pos)                               /*!< 0x00001000 */
#define RTC_TACFG_TPSFSEL_Pos                                       (8U)
#define RTC_TACFG_TPSFSEL_Msk                                       (0x7UL << RTC_TACFG_TPSFSEL_Pos)                               /*!< 0x00000700 */
#define RTC_TACFG_TPSFSEL                                           RTC_TACFG_TPSFSEL_Msk
#define RTC_TACFG_TPSFSEL_0                                         (0x1UL << RTC_TACFG_TPSFSEL_Pos)                               /*!< 0x00000100 */
#define RTC_TACFG_TPSFSEL_1                                         (0x2UL << RTC_TACFG_TPSFSEL_Pos)                               /*!< 0x00000200 */
#define RTC_TACFG_TPSFSEL_2                                         (0x4UL << RTC_TACFG_TPSFSEL_Pos)                               /*!< 0x00000400 */
#define RTC_TACFG_TPTSEN_Pos                                        (7U)
#define RTC_TACFG_TPTSEN_Msk                                        (0x1UL << RTC_TACFG_TPTSEN_Pos)                                /*!< 0x00000080 */
#define RTC_TACFG_TPTSEN                                            RTC_TACFG_TPTSEN_Msk
#define RTC_TACFG_TP2ALCFG_Pos                                      (4U)
#define RTC_TACFG_TP2ALCFG_Msk                                      (0x1UL << RTC_TACFG_TP2ALCFG_Pos)                              /*!< 0x00000010 */
#define RTC_TACFG_TP2ALCFG                                          RTC_TACFG_TP2ALCFG_Msk
#define RTC_TACFG_TP2EN_Pos                                         (3U)
#define RTC_TACFG_TP2EN_Msk                                         (0x1UL << RTC_TACFG_TP2EN_Pos)                                 /*!< 0x00000008 */
#define RTC_TACFG_TP2EN                                             RTC_TACFG_TP2EN_Msk
#define RTC_TACFG_TPIEN_Pos                                         (2U)
#define RTC_TACFG_TPIEN_Msk                                         (0x1UL << RTC_TACFG_TPIEN_Pos)                                 /*!< 0x00000004 */
#define RTC_TACFG_TPIEN                                             RTC_TACFG_TPIEN_Msk
#define RTC_TACFG_TP1ALCFG_Pos                                      (1U)
#define RTC_TACFG_TP1ALCFG_Msk                                      (0x1UL << RTC_TACFG_TP1ALCFG_Pos)                              /*!< 0x00000002 */
#define RTC_TACFG_TP1ALCFG                                          RTC_TACFG_TP1ALCFG_Msk
#define RTC_TACFG_TP1EN_Pos                                         (0U)
#define RTC_TACFG_TP1EN_Msk                                         (0x1UL << RTC_TACFG_TP1EN_Pos)                                 /*!< 0x00000001 */
#define RTC_TACFG_TP1EN                                             RTC_TACFG_TP1EN_Msk

/* Legacy defines */
#define RTC_TACFG_TAMPINSEL                                         RTC_TACFG_TP1MSEL

/********************  Bits definition for RTC_ALRMASS register  *************/
#define RTC_ALRMASS_MASKSEL_Pos                                     (24U)
#define RTC_ALRMASS_MASKSEL_Msk                                     (0xFUL << RTC_ALRMASS_MASKSEL_Pos)                             /*!< 0x0F000000 */
#define RTC_ALRMASS_MASKSEL                                         RTC_ALRMASS_MASKSEL_Msk
#define RTC_ALRMASS_MASKSEL_0                                       (0x1UL << RTC_ALRMASS_MASKSEL_Pos)                             /*!< 0x01000000 */
#define RTC_ALRMASS_MASKSEL_1                                       (0x2UL << RTC_ALRMASS_MASKSEL_Pos)                             /*!< 0x02000000 */
#define RTC_ALRMASS_MASKSEL_2                                       (0x4UL << RTC_ALRMASS_MASKSEL_Pos)                             /*!< 0x04000000 */
#define RTC_ALRMASS_MASKSEL_3                                       (0x8UL << RTC_ALRMASS_MASKSEL_Pos)                             /*!< 0x08000000 */
#define RTC_ALRMASS_SUBSEC_Pos                                      (0U)
#define RTC_ALRMASS_SUBSEC_Msk                                      (0x7FFFUL << RTC_ALRMASS_SUBSEC_Pos)                           /*!< 0x00007FFF */
#define RTC_ALRMASS_SUBSEC                                          RTC_ALRMASS_SUBSEC_Msk

/********************  Bits definition for RTC_ALRMBSS register  *************/
#define RTC_ALRMBSS_MASKSEL_Pos                                     (24U)
#define RTC_ALRMBSS_MASKSEL_Msk                                     (0xFUL << RTC_ALRMBSS_MASKSEL_Pos)                             /*!< 0x0F000000 */
#define RTC_ALRMBSS_MASKSEL                                         RTC_ALRMBSS_MASKSEL_Msk
#define RTC_ALRMBSS_MASKSEL_0                                       (0x1UL << RTC_ALRMBSS_MASKSEL_Pos)                             /*!< 0x01000000 */
#define RTC_ALRMBSS_MASKSEL_1                                       (0x2UL << RTC_ALRMBSS_MASKSEL_Pos)                             /*!< 0x02000000 */
#define RTC_ALRMBSS_MASKSEL_2                                       (0x4UL << RTC_ALRMBSS_MASKSEL_Pos)                             /*!< 0x04000000 */
#define RTC_ALRMBSS_MASKSEL_3                                       (0x8UL << RTC_ALRMBSS_MASKSEL_Pos)                             /*!< 0x08000000 */
#define RTC_ALRMBSS_SUBSEC_Pos                                      (0U)
#define RTC_ALRMBSS_SUBSEC_Msk                                      (0x7FFFUL << RTC_ALRMBSS_SUBSEC_Pos)                           /*!< 0x00007FFF */
#define RTC_ALRMBSS_SUBSEC                                          RTC_ALRMBSS_SUBSEC_Msk

/********************  Bits definition for RTC_BAKP0 register  ****************/
#define RTC_BAKP0_BAKP_Pos                                          (0U)
#define RTC_BAKP0_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP0_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP0_BAKP                                              RTC_BAKP0_BAKP_Msk

/********************  Bits definition for RTC_BAKP1 register  ****************/
#define RTC_BAKP1_BAKP_Pos                                          (0U)
#define RTC_BAKP1_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP1_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP1_BAKP                                              RTC_BAKP1_BAKP_Msk

/********************  Bits definition for RTC_BAKP2 register  ****************/
#define RTC_BAKP2_BAKP_Pos                                          (0U)
#define RTC_BAKP2_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP2_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP2_BAKP                                              RTC_BAKP2_BAKP_Msk

/********************  Bits definition for RTC_BAKP3 register  ****************/
#define RTC_BAKP3_BAKP_Pos                                          (0U)
#define RTC_BAKP3_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP3_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP3_BAKP                                              RTC_BAKP3_BAKP_Msk

/********************  Bits definition for RTC_BAKP4 register  ****************/
#define RTC_BAKP4_BAKP_Pos                                          (0U)
#define RTC_BAKP4_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP4_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP4_BAKP                                              RTC_BAKP4_BAKP_Msk

/********************  Bits definition for RTC_BAKP5 register  ****************/
#define RTC_BAKP5_BAKP_Pos                                          (0U)
#define RTC_BAKP5_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP5_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP5_BAKP                                              RTC_BAKP5_BAKP_Msk

/********************  Bits definition for RTC_BAKP6 register  ****************/
#define RTC_BAKP6_BAKP_Pos                                          (0U)
#define RTC_BAKP6_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP6_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP6_BAKP                                              RTC_BAKP6_BAKP_Msk

/********************  Bits definition for RTC_BAKP7 register  ****************/
#define RTC_BAKP7_BAKP_Pos                                          (0U)
#define RTC_BAKP7_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP7_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP7_BAKP                                              RTC_BAKP7_BAKP_Msk

/********************  Bits definition for RTC_BAKP8 register  ****************/
#define RTC_BAKP8_BAKP_Pos                                          (0U)
#define RTC_BAKP8_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP8_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP8_BAKP                                              RTC_BAKP8_BAKP_Msk

/********************  Bits definition for RTC_BAKP9 register  ****************/
#define RTC_BAKP9_BAKP_Pos                                          (0U)
#define RTC_BAKP9_BAKP_Msk                                          (0xFFFFFFFFUL << RTC_BAKP9_BAKP_Pos)                           /*!< 0xFFFFFFFF */
#define RTC_BAKP9_BAKP                                              RTC_BAKP9_BAKP_Msk

/********************  Bits definition for RTC_BAKP10 register  ***************/
#define RTC_BAKP10_BAKP_Pos                                         (0U)
#define RTC_BAKP10_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP10_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP10_BAKP                                             RTC_BAKP10_BAKP_Msk

/********************  Bits definition for RTC_BAKP11 register  ***************/
#define RTC_BAKP11_BAKP_Pos                                         (0U)
#define RTC_BAKP11_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP11_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP11_BAKP                                             RTC_BAKP11_BAKP_Msk

/********************  Bits definition for RTC_BAKP12 register  ***************/
#define RTC_BAKP12_BAKP_Pos                                         (0U)
#define RTC_BAKP12_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP12_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP12_BAKP                                             RTC_BAKP12_BAKP_Msk

/********************  Bits definition for RTC_BAKP13 register  ***************/
#define RTC_BAKP13_BAKP_Pos                                         (0U)
#define RTC_BAKP13_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP13_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP13_BAKP                                             RTC_BAKP13_BAKP_Msk

/********************  Bits definition for RTC_BAKP14 register  ***************/
#define RTC_BAKP14_BAKP_Pos                                         (0U)
#define RTC_BAKP14_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP14_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP14_BAKP                                             RTC_BAKP14_BAKP_Msk

/********************  Bits definition for RTC_BAKP15 register  ***************/
#define RTC_BAKP15_BAKP_Pos                                         (0U)
#define RTC_BAKP15_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP15_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP15_BAKP                                             RTC_BAKP15_BAKP_Msk

/********************  Bits definition for RTC_BAKP16 register  ***************/
#define RTC_BAKP16_BAKP_Pos                                         (0U)
#define RTC_BAKP16_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP16_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP16_BAKP                                             RTC_BAKP16_BAKP_Msk

/********************  Bits definition for RTC_BAKP17 register  ***************/
#define RTC_BAKP17_BAKP_Pos                                         (0U)
#define RTC_BAKP17_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP17_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP17_BAKP                                             RTC_BAKP17_BAKP_Msk

/********************  Bits definition for RTC_BAKP18 register  ***************/
#define RTC_BAKP18_BAKP_Pos                                         (0U)
#define RTC_BAKP18_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP18_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP18_BAKP                                             RTC_BAKP18_BAKP_Msk

/********************  Bits definition for RTC_BAKP19 register  ***************/
#define RTC_BAKP19_BAKP_Pos                                         (0U)
#define RTC_BAKP19_BAKP_Msk                                         (0xFFFFFFFFUL << RTC_BAKP19_BAKP_Pos)                          /*!< 0xFFFFFFFF */
#define RTC_BAKP19_BAKP                                             RTC_BAKP19_BAKP_Msk

/******************** Number of backup registers ******************************/
#define RTC_BKP_NUMBER                                              0x000000014U


/******************************************************************************/
/*                                                                            */
/*                          SD host Interface                                 */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for SDIO_PWRCTRL register  ******************/
#define SDIO_PWRCTRL_PWRCTRL_Pos                                    (0U)
#define SDIO_PWRCTRL_PWRCTRL_Msk                                    (0x3UL << SDIO_PWRCTRL_PWRCTRL_Pos)                            /*!< 0x00000003 */
#define SDIO_PWRCTRL_PWRCTRL                                        SDIO_PWRCTRL_PWRCTRL_Msk                                       /*!<PWRCTRL[1:0] bits (Power supply control bits) */
#define SDIO_PWRCTRL_PWRCTRL_0                                      (0x1UL << SDIO_PWRCTRL_PWRCTRL_Pos)                            /*!< 0x01 */
#define SDIO_PWRCTRL_PWRCTRL_1                                      (0x2UL << SDIO_PWRCTRL_PWRCTRL_Pos)                            /*!< 0x02 */

/******************  Bit definition for SDIO_CLKCTRL register  ******************/
#define SDIO_CLKCTRL_CLKDIV_Pos                                     (0U)
#define SDIO_CLKCTRL_CLKDIV_Msk                                     (0xFFUL << SDIO_CLKCTRL_CLKDIV_Pos)                            /*!< 0x000000FF */
#define SDIO_CLKCTRL_CLKDIV                                         SDIO_CLKCTRL_CLKDIV_Msk                                        /*!<Clock divide factor             */
#define SDIO_CLKCTRL_CLKEN_Pos                                      (8U)
#define SDIO_CLKCTRL_CLKEN_Msk                                      (0x1UL << SDIO_CLKCTRL_CLKEN_Pos)                              /*!< 0x00000100 */
#define SDIO_CLKCTRL_CLKEN                                          SDIO_CLKCTRL_CLKEN_Msk                                         /*!<Clock enable bit                */
#define SDIO_CLKCTRL_PWRSAV_Pos                                     (9U)
#define SDIO_CLKCTRL_PWRSAV_Msk                                     (0x1UL << SDIO_CLKCTRL_PWRSAV_Pos)                             /*!< 0x00000200 */
#define SDIO_CLKCTRL_PWRSAV                                         SDIO_CLKCTRL_PWRSAV_Msk                                        /*!<Power saving configuration bit  */
#define SDIO_CLKCTRL_BYPASSEN_Pos                                   (10U)
#define SDIO_CLKCTRL_BYPASSEN_Msk                                   (0x1UL << SDIO_CLKCTRL_BYPASSEN_Pos)                           /*!< 0x00000400 */
#define SDIO_CLKCTRL_BYPASSEN                                       SDIO_CLKCTRL_BYPASSEN_Msk                                      /*!<Clock divider bypass enable bit */

#define SDIO_CLKCTRL_WBSEL_Pos                                      (11U)
#define SDIO_CLKCTRL_WBSEL_Msk                                      (0x3UL << SDIO_CLKCTRL_WBSEL_Pos)                              /*!< 0x00001800 */
#define SDIO_CLKCTRL_WBSEL                                          SDIO_CLKCTRL_WBSEL_Msk                                         /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
#define SDIO_CLKCTRL_WBSEL_0                                        (0x1UL << SDIO_CLKCTRL_WBSEL_Pos)                              /*!< 0x0800 */
#define SDIO_CLKCTRL_WBSEL_1                                        (0x2UL << SDIO_CLKCTRL_WBSEL_Pos)                              /*!< 0x1000 */

#define SDIO_CLKCTRL_DEPSEL_Pos                                     (13U)
#define SDIO_CLKCTRL_DEPSEL_Msk                                     (0x1UL << SDIO_CLKCTRL_DEPSEL_Pos)                             /*!< 0x00002000 */
#define SDIO_CLKCTRL_DEPSEL                                         SDIO_CLKCTRL_DEPSEL_Msk                                        /*!<SDIO_CK dephasing selection bit */
#define SDIO_CLKCTRL_HFCEN_EN_Pos                                   (14U)
#define SDIO_CLKCTRL_HFCEN_EN_Msk                                   (0x1UL << SDIO_CLKCTRL_HFCEN_EN_Pos)                           /*!< 0x00004000 */
#define SDIO_CLKCTRL_HFCEN_EN                                       SDIO_CLKCTRL_HFCEN_EN_Msk                                      /*!<HW Flow Control enable          */

/*******************  Bit definition for SDIO_ARG register  *******************/
#define SDIO_ARG_CMDARG_Pos                                         (0U)
#define SDIO_ARG_CMDARG_Msk                                         (0xFFFFFFFFUL << SDIO_ARG_CMDARG_Pos)                          /*!< 0xFFFFFFFF */
#define SDIO_ARG_CMDARG                                             SDIO_ARG_CMDARG_Msk                                            /*!<Command argument */

/*******************  Bit definition for SDIO_CMD register  *******************/
#define SDIO_CMD_CMDINDEX_Pos                                       (0U)
#define SDIO_CMD_CMDINDEX_Msk                                       (0x3FUL << SDIO_CMD_CMDINDEX_Pos)                              /*!< 0x0000003F */
#define SDIO_CMD_CMDINDEX                                           SDIO_CMD_CMDINDEX_Msk                                          /*!<Command Index                               */

#define SDIO_CMD_WAITRES_Pos                                        (6U)
#define SDIO_CMD_WAITRES_Msk                                        (0x3UL << SDIO_CMD_WAITRES_Pos)                                /*!< 0x000000C0 */
#define SDIO_CMD_WAITRES                                            SDIO_CMD_WAITRES_Msk                                           /*!<WAITRESP[1:0] bits (Wait for response bits) */
#define SDIO_CMD_WAITRES_0                                          (0x1UL << SDIO_CMD_WAITRES_Pos)                                /*!< 0x0040 */
#define SDIO_CMD_WAITRES_1                                          (0x2UL << SDIO_CMD_WAITRES_Pos)                                /*!< 0x0080 */

#define SDIO_CMD_WAITINT_Pos                                        (8U)
#define SDIO_CMD_WAITINT_Msk                                        (0x1UL << SDIO_CMD_WAITINT_Pos)                                /*!< 0x00000100 */
#define SDIO_CMD_WAITINT                                            SDIO_CMD_WAITINT_Msk                                           /*!<CPSM Waits for Interrupt Request                               */
#define SDIO_CMD_WENDDATA_Pos                                       (9U)
#define SDIO_CMD_WENDDATA_Msk                                       (0x1UL << SDIO_CMD_WENDDATA_Pos)                               /*!< 0x00000200 */
#define SDIO_CMD_WENDDATA                                           SDIO_CMD_WENDDATA_Msk                                          /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
#define SDIO_CMD_CPSMEN_Pos                                         (10U)
#define SDIO_CMD_CPSMEN_Msk                                         (0x1UL << SDIO_CMD_CPSMEN_Pos)                                 /*!< 0x00000400 */
#define SDIO_CMD_CPSMEN                                             SDIO_CMD_CPSMEN_Msk                                            /*!<Command path state machine (CPSM) Enable bit                   */
#define SDIO_CMD_SDIOSC_Pos                                         (11U)
#define SDIO_CMD_SDIOSC_Msk                                         (0x1UL << SDIO_CMD_SDIOSC_Pos)                                 /*!< 0x00000800 */
#define SDIO_CMD_SDIOSC                                             SDIO_CMD_SDIOSC_Msk                                            /*!<SD I/O suspend command                                         */
#define SDIO_CMD_CMDCPEN_Pos                                        (12U)
#define SDIO_CMD_CMDCPEN_Msk                                        (0x1UL << SDIO_CMD_CMDCPEN_Pos)                                /*!< 0x00001000 */
#define SDIO_CMD_CMDCPEN                                            SDIO_CMD_CMDCPEN_Msk                                           /*!<Enable CMD completion                                          */
#define SDIO_CMD_INTEN_Pos                                          (13U)
#define SDIO_CMD_INTEN_Msk                                          (0x1UL << SDIO_CMD_INTEN_Pos)                                  /*!< 0x00002000 */
#define SDIO_CMD_INTEN                                              SDIO_CMD_INTEN_Msk                                             /*!<Not Interrupt Enable                                           */
#define SDIO_CMD_ATACMD_Pos                                         (14U)
#define SDIO_CMD_ATACMD_Msk                                         (0x1UL << SDIO_CMD_ATACMD_Pos)                                 /*!< 0x00004000 */
#define SDIO_CMD_ATACMD                                             SDIO_CMD_ATACMD_Msk                                            /*!<CE-ATA command                                                 */

/*****************  Bit definition for SDIO_CMDRES register  *****************/
#define SDIO_CMDRES_CMDRES_Pos                                      (0U)
#define SDIO_CMDRES_CMDRES_Msk                                      (0x3FUL << SDIO_CMDRES_CMDRES_Pos)                             /*!< 0x0000003F */
#define SDIO_CMDRES_CMDRES                                          SDIO_CMDRES_CMDRES_Msk                                         /*!<Response command index */

/******************  Bit definition for SDIO_RES0 register  ******************/
#define SDIO_RES0_CARDSTS0_Pos                                      (0U)
#define SDIO_RES0_CARDSTS0_Msk                                      (0xFFFFFFFFUL << SDIO_RES0_CARDSTS0_Pos)                       /*!< 0xFFFFFFFF */
#define SDIO_RES0_CARDSTS0                                          SDIO_RES0_CARDSTS0_Msk                                         /*!<Card Status */

/******************  Bit definition for SDIO_RES1 register  ******************/
#define SDIO_RES1_CARDSTS1_Pos                                      (0U)
#define SDIO_RES1_CARDSTS1_Msk                                      (0xFFFFFFFFUL << SDIO_RES1_CARDSTS1_Pos)                       /*!< 0xFFFFFFFF */
#define SDIO_RES1_CARDSTS1                                          SDIO_RES1_CARDSTS1_Msk                                         /*!<Card Status */

/******************  Bit definition for SDIO_RES2 register  ******************/
#define SDIO_RES2_CARDSTS2_Pos                                      (0U)
#define SDIO_RES2_CARDSTS2_Msk                                      (0xFFFFFFFFUL << SDIO_RES2_CARDSTS2_Pos)                       /*!< 0xFFFFFFFF */
#define SDIO_RES2_CARDSTS2                                          SDIO_RES2_CARDSTS2_Msk                                         /*!<Card Status */

/******************  Bit definition for SDIO_RES3 register  ******************/
#define SDIO_RES3_CARDSTS3_Pos                                      (0U)
#define SDIO_RES3_CARDSTS3_Msk                                      (0xFFFFFFFFUL << SDIO_RES3_CARDSTS3_Pos)                       /*!< 0xFFFFFFFF */
#define SDIO_RES3_CARDSTS3                                          SDIO_RES3_CARDSTS3_Msk                                         /*!<Card Status */

/******************  Bit definition for SDIO_RES4 register  ******************/
#define SDIO_RES4_CARDSTS4_Pos                                      (0U)
#define SDIO_RES4_CARDSTS4_Msk                                      (0xFFFFFFFFUL << SDIO_RES4_CARDSTS4_Pos)                       /*!< 0xFFFFFFFF */
#define SDIO_RES4_CARDSTS4                                          SDIO_RES4_CARDSTS4_Msk                                         /*!<Card Status */

/******************  Bit definition for SDIO_DATATIME register  *****************/
#define SDIO_DATATIME_DATATIME_Pos                                  (0U)
#define SDIO_DATATIME_DATATIME_Msk                                  (0xFFFFFFFFUL << SDIO_DATATIME_DATATIME_Pos)                   /*!< 0xFFFFFFFF */
#define SDIO_DATATIME_DATATIME                                      SDIO_DATATIME_DATATIME_Msk                                     /*!<Data timeout period. */

/******************  Bit definition for SDIO_DATALEN register  *******************/
#define SDIO_DATALEN_DATALEN_Pos                                    (0U)
#define SDIO_DATALEN_DATALEN_Msk                                    (0x1FFFFFFUL << SDIO_DATALEN_DATALEN_Pos)                      /*!< 0x01FFFFFF */
#define SDIO_DATALEN_DATALEN                                        SDIO_DATALEN_DATALEN_Msk                                       /*!<Data length value    */

/******************  Bit definition for SDIO_DCTRL register  ******************/
#define SDIO_DCTRL_DTEN_Pos                                         (0U)
#define SDIO_DCTRL_DTEN_Msk                                         (0x1UL << SDIO_DCTRL_DTEN_Pos)                                 /*!< 0x00000001 */
#define SDIO_DCTRL_DTEN                                             SDIO_DCTRL_DTEN_Msk                                            /*!<Data transfer enabled bit         */
#define SDIO_DCTRL_DTDRCFG_Pos                                      (1U)
#define SDIO_DCTRL_DTDRCFG_Msk                                      (0x1UL << SDIO_DCTRL_DTDRCFG_Pos)                              /*!< 0x00000002 */
#define SDIO_DCTRL_DTDRCFG                                          SDIO_DCTRL_DTDRCFG_Msk                                         /*!<Data transfer direction selection */
#define SDIO_DCTRL_DTSEL_Pos                                        (2U)
#define SDIO_DCTRL_DTSEL_Msk                                        (0x1UL << SDIO_DCTRL_DTSEL_Pos)                                /*!< 0x00000004 */
#define SDIO_DCTRL_DTSEL                                            SDIO_DCTRL_DTSEL_Msk                                           /*!<Data transfer mode selection      */
#define SDIO_DCTRL_DMAEN_Pos                                        (3U)
#define SDIO_DCTRL_DMAEN_Msk                                        (0x1UL << SDIO_DCTRL_DMAEN_Pos)                                /*!< 0x00000008 */
#define SDIO_DCTRL_DMAEN                                            SDIO_DCTRL_DMAEN_Msk                                           /*!<DMA enabled bit                   */

#define SDIO_DCTRL_DBSIZE_Pos                                       (4U)
#define SDIO_DCTRL_DBSIZE_Msk                                       (0xFUL << SDIO_DCTRL_DBSIZE_Pos)                               /*!< 0x000000F0 */
#define SDIO_DCTRL_DBSIZE                                           SDIO_DCTRL_DBSIZE_Msk                                          /*!<DBLOCKSIZE[3:0] bits (Data block size) */
#define SDIO_DCTRL_DBSIZE_0                                         (0x1UL << SDIO_DCTRL_DBSIZE_Pos)                               /*!< 0x0010 */
#define SDIO_DCTRL_DBSIZE_1                                         (0x2UL << SDIO_DCTRL_DBSIZE_Pos)                               /*!< 0x0020 */
#define SDIO_DCTRL_DBSIZE_2                                         (0x4UL << SDIO_DCTRL_DBSIZE_Pos)                               /*!< 0x0040 */
#define SDIO_DCTRL_DBSIZE_3                                         (0x8UL << SDIO_DCTRL_DBSIZE_Pos)                               /*!< 0x0080 */

#define SDIO_DCTRL_RWSTR_Pos                                        (8U)
#define SDIO_DCTRL_RWSTR_Msk                                        (0x1UL << SDIO_DCTRL_RWSTR_Pos)                                /*!< 0x00000100 */
#define SDIO_DCTRL_RWSTR                                            SDIO_DCTRL_RWSTR_Msk                                           /*!<Read wait start         */
#define SDIO_DCTRL_RWSTOP_Pos                                       (9U)
#define SDIO_DCTRL_RWSTOP_Msk                                       (0x1UL << SDIO_DCTRL_RWSTOP_Pos)                               /*!< 0x00000200 */
#define SDIO_DCTRL_RWSTOP                                           SDIO_DCTRL_RWSTOP_Msk                                          /*!<Read wait stop          */
#define SDIO_DCTRL_RDWAIT_Pos                                       (10U)
#define SDIO_DCTRL_RDWAIT_Msk                                       (0x1UL << SDIO_DCTRL_RDWAIT_Pos)                               /*!< 0x00000400 */
#define SDIO_DCTRL_RDWAIT                                           SDIO_DCTRL_RDWAIT_Msk                                          /*!<Read wait mode          */
#define SDIO_DCTRL_SDIOF_Pos                                        (11U)
#define SDIO_DCTRL_SDIOF_Msk                                        (0x1UL << SDIO_DCTRL_SDIOF_Pos)                                /*!< 0x00000800 */
#define SDIO_DCTRL_SDIOF                                            SDIO_DCTRL_SDIOF_Msk                                           /*!<SD I/O enable functions */

/******************  Bit definition for SDIO_DCNT register  *****************/
#define SDIO_DCNT_DATACNT_Pos                                       (0U)
#define SDIO_DCNT_DATACNT_Msk                                       (0x1FFFFFFUL << SDIO_DCNT_DATACNT_Pos)                         /*!< 0x01FFFFFF */
#define SDIO_DCNT_DATACNT                                           SDIO_DCNT_DATACNT_Msk                                          /*!<Data count value */

/******************  Bit definition for SDIO_STS register  ********************/
#define SDIO_STS_COMRESP_Pos                                        (0U)
#define SDIO_STS_COMRESP_Msk                                        (0x1UL << SDIO_STS_COMRESP_Pos)                                /*!< 0x00000001 */
#define SDIO_STS_COMRESP                                            SDIO_STS_COMRESP_Msk                                           /*!<Command response received (CRC check failed)  */
#define SDIO_STS_DBDR_Pos                                           (1U)
#define SDIO_STS_DBDR_Msk                                           (0x1UL << SDIO_STS_DBDR_Pos)                                   /*!< 0x00000002 */
#define SDIO_STS_DBDR                                               SDIO_STS_DBDR_Msk                                              /*!<Data block sent/received (CRC check failed)   */
#define SDIO_STS_CMDRESTO_Pos                                       (2U)
#define SDIO_STS_CMDRESTO_Msk                                       (0x1UL << SDIO_STS_CMDRESTO_Pos)                               /*!< 0x00000004 */
#define SDIO_STS_CMDRESTO                                           SDIO_STS_CMDRESTO_Msk                                          /*!<Command response timeout                      */
#define SDIO_STS_DATATO_Pos                                         (3U)
#define SDIO_STS_DATATO_Msk                                         (0x1UL << SDIO_STS_DATATO_Pos)                                 /*!< 0x00000008 */
#define SDIO_STS_DATATO                                             SDIO_STS_DATATO_Msk                                            /*!<Data timeout                                  */
#define SDIO_STS_TXUDRER_Pos                                        (4U)
#define SDIO_STS_TXUDRER_Msk                                        (0x1UL << SDIO_STS_TXUDRER_Pos)                                /*!< 0x00000010 */
#define SDIO_STS_TXUDRER                                            SDIO_STS_TXUDRER_Msk                                           /*!<Transmit FIFO underrun error                  */
#define SDIO_STS_RXOVRER_Pos                                        (5U)
#define SDIO_STS_RXOVRER_Msk                                        (0x1UL << SDIO_STS_RXOVRER_Pos)                                /*!< 0x00000020 */
#define SDIO_STS_RXOVRER                                            SDIO_STS_RXOVRER_Msk                                           /*!<Received FIFO overrun error                   */
#define SDIO_STS_CMDRES_Pos                                         (6U)
#define SDIO_STS_CMDRES_Msk                                         (0x1UL << SDIO_STS_CMDRES_Pos)                                 /*!< 0x00000040 */
#define SDIO_STS_CMDRES                                             SDIO_STS_CMDRES_Msk                                            /*!<Command response received (CRC check passed)  */
#define SDIO_STS_CMDSENT_Pos                                        (7U)
#define SDIO_STS_CMDSENT_Msk                                        (0x1UL << SDIO_STS_CMDSENT_Pos)                                /*!< 0x00000080 */
#define SDIO_STS_CMDSENT                                            SDIO_STS_CMDSENT_Msk                                           /*!<Command sent (no response required)           */
#define SDIO_STS_DATAEND_Pos                                        (8U)
#define SDIO_STS_DATAEND_Msk                                        (0x1UL << SDIO_STS_DATAEND_Pos)                                /*!< 0x00000100 */
#define SDIO_STS_DATAEND                                            SDIO_STS_DATAEND_Msk                                           /*!<Data end (data counter, SDIDCOUNT, is zero)   */
#define SDIO_STS_SBE_Pos                                            (9U)
#define SDIO_STS_SBE_Msk                                            (0x1UL << SDIO_STS_SBE_Pos)                                    /*!< 0x00000200 */
#define SDIO_STS_SBE                                                SDIO_STS_SBE_Msk                                               /*!<Start bit not detected on all data signals in wide bus mode */
#define SDIO_STS_DBCP_Pos                                           (10U)
#define SDIO_STS_DBCP_Msk                                           (0x1UL << SDIO_STS_DBCP_Pos)                                   /*!< 0x00000400 */
#define SDIO_STS_DBCP                                               SDIO_STS_DBCP_Msk                                              /*!<Data block sent/received (CRC check passed)   */
#define SDIO_STS_CMDACT_Pos                                         (11U)
#define SDIO_STS_CMDACT_Msk                                         (0x1UL << SDIO_STS_CMDACT_Pos)                                 /*!< 0x00000800 */
#define SDIO_STS_CMDACT                                             SDIO_STS_CMDACT_Msk                                            /*!<Command transfer in progress                  */
#define SDIO_STS_TXACT_Pos                                          (12U)
#define SDIO_STS_TXACT_Msk                                          (0x1UL << SDIO_STS_TXACT_Pos)                                  /*!< 0x00001000 */
#define SDIO_STS_TXACT                                              SDIO_STS_TXACT_Msk                                             /*!<Data transmit in progress                     */
#define SDIO_STS_RXACT_Pos                                          (13U)
#define SDIO_STS_RXACT_Msk                                          (0x1UL << SDIO_STS_RXACT_Pos)                                  /*!< 0x00002000 */
#define SDIO_STS_RXACT                                              SDIO_STS_RXACT_Msk                                             /*!<Data receive in progress                      */
#define SDIO_STS_TXFHF_Pos                                          (14U)
#define SDIO_STS_TXFHF_Msk                                          (0x1UL << SDIO_STS_TXFHF_Pos)                                  /*!< 0x00004000 */
#define SDIO_STS_TXFHF                                              SDIO_STS_TXFHF_Msk                                             /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
#define SDIO_STS_RXFHF_Pos                                          (15U)
#define SDIO_STS_RXFHF_Msk                                          (0x1UL << SDIO_STS_RXFHF_Pos)                                  /*!< 0x00008000 */
#define SDIO_STS_RXFHF                                              SDIO_STS_RXFHF_Msk                                             /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
#define SDIO_STS_TXFF_Pos                                           (16U)
#define SDIO_STS_TXFF_Msk                                           (0x1UL << SDIO_STS_TXFF_Pos)                                   /*!< 0x00010000 */
#define SDIO_STS_TXFF                                               SDIO_STS_TXFF_Msk                                              /*!<Transmit FIFO full                            */
#define SDIO_STS_RXFF_Pos                                           (17U)
#define SDIO_STS_RXFF_Msk                                           (0x1UL << SDIO_STS_RXFF_Pos)                                   /*!< 0x00020000 */
#define SDIO_STS_RXFF                                               SDIO_STS_RXFF_Msk                                              /*!<Receive FIFO full                             */
#define SDIO_STS_TXFE_Pos                                           (18U)
#define SDIO_STS_TXFE_Msk                                           (0x1UL << SDIO_STS_TXFE_Pos)                                   /*!< 0x00040000 */
#define SDIO_STS_TXFE                                               SDIO_STS_TXFE_Msk                                              /*!<Transmit FIFO empty                           */
#define SDIO_STS_RXFE_Pos                                           (19U)
#define SDIO_STS_RXFE_Msk                                           (0x1UL << SDIO_STS_RXFE_Pos)                                   /*!< 0x00080000 */
#define SDIO_STS_RXFE                                               SDIO_STS_RXFE_Msk                                              /*!<Receive FIFO empty                            */
#define SDIO_STS_TXDA_Pos                                           (20U)
#define SDIO_STS_TXDA_Msk                                           (0x1UL << SDIO_STS_TXDA_Pos)                                   /*!< 0x00100000 */
#define SDIO_STS_TXDA                                               SDIO_STS_TXDA_Msk                                              /*!<Data available in transmit FIFO               */
#define SDIO_STS_RXDA_Pos                                           (21U)
#define SDIO_STS_RXDA_Msk                                           (0x1UL << SDIO_STS_RXDA_Pos)                                   /*!< 0x00200000 */
#define SDIO_STS_RXDA                                               SDIO_STS_RXDA_Msk                                              /*!<Data available in receive FIFO                */
#define SDIO_STS_SDIOINT_Pos                                        (22U)
#define SDIO_STS_SDIOINT_Msk                                        (0x1UL << SDIO_STS_SDIOINT_Pos)                                /*!< 0x00400000 */
#define SDIO_STS_SDIOINT                                            SDIO_STS_SDIOINT_Msk                                           /*!<SDIO interrupt received                       */
#define SDIO_STS_ATAEND_Pos                                         (23U)
#define SDIO_STS_ATAEND_Msk                                         (0x1UL << SDIO_STS_ATAEND_Pos)                                 /*!< 0x00800000 */
#define SDIO_STS_ATAEND                                             SDIO_STS_ATAEND_Msk                                            /*!<CE-ATA command completion signal received for CMD61 */

/*******************  Bit definition for SDIO_ICF register  *******************/
#define SDIO_ICF_CRCE_Pos                                           (0U)
#define SDIO_ICF_CRCE_Msk                                           (0x1UL << SDIO_ICF_CRCE_Pos)                                   /*!< 0x00000001 */
#define SDIO_ICF_CRCE                                               SDIO_ICF_CRCE_Msk                                              /*!<CCRCFAIL flag clear bit */
#define SDIO_ICF_DBCE_Pos                                           (1U)
#define SDIO_ICF_DBCE_Msk                                           (0x1UL << SDIO_ICF_DBCE_Pos)                                   /*!< 0x00000002 */
#define SDIO_ICF_DBCE                                               SDIO_ICF_DBCE_Msk                                              /*!<DCRCFAIL flag clear bit */
#define SDIO_ICF_CRTO_Pos                                           (2U)
#define SDIO_ICF_CRTO_Msk                                           (0x1UL << SDIO_ICF_CRTO_Pos)                                   /*!< 0x00000004 */
#define SDIO_ICF_CRTO                                               SDIO_ICF_CRTO_Msk                                              /*!<CTIMEOUT flag clear bit */
#define SDIO_ICF_DTO_Pos                                            (3U)
#define SDIO_ICF_DTO_Msk                                            (0x1UL << SDIO_ICF_DTO_Pos)                                    /*!< 0x00000008 */
#define SDIO_ICF_DTO                                                SDIO_ICF_DTO_Msk                                               /*!<DTIMEOUT flag clear bit */
#define SDIO_ICF_TXFUE_Pos                                          (4U)
#define SDIO_ICF_TXFUE_Msk                                          (0x1UL << SDIO_ICF_TXFUE_Pos)                                  /*!< 0x00000010 */
#define SDIO_ICF_TXFUE                                              SDIO_ICF_TXFUE_Msk                                             /*!<TXUNDERR flag clear bit */
#define SDIO_ICF_RXFOE_Pos                                          (5U)
#define SDIO_ICF_RXFOE_Msk                                          (0x1UL << SDIO_ICF_RXFOE_Pos)                                  /*!< 0x00000020 */
#define SDIO_ICF_RXFOE                                              SDIO_ICF_RXFOE_Msk                                             /*!<RXOVERR flag clear bit  */
#define SDIO_ICF_CMDRES_Pos                                         (6U)
#define SDIO_ICF_CMDRES_Msk                                         (0x1UL << SDIO_ICF_CMDRES_Pos)                                 /*!< 0x00000040 */
#define SDIO_ICF_CMDRES                                             SDIO_ICF_CMDRES_Msk                                            /*!<CMDREND flag clear bit  */
#define SDIO_ICF_CMDSENT_Pos                                        (7U)
#define SDIO_ICF_CMDSENT_Msk                                        (0x1UL << SDIO_ICF_CMDSENT_Pos)                                /*!< 0x00000080 */
#define SDIO_ICF_CMDSENT                                            SDIO_ICF_CMDSENT_Msk                                           /*!<CMDSENT flag clear bit  */
#define SDIO_ICF_DATAEND_Pos                                        (8U)
#define SDIO_ICF_DATAEND_Msk                                        (0x1UL << SDIO_ICF_DATAEND_Pos)                                /*!< 0x00000100 */
#define SDIO_ICF_DATAEND                                            SDIO_ICF_DATAEND_Msk                                           /*!<DATAEND flag clear bit  */
#define SDIO_ICF_SBE_Pos                                            (9U)
#define SDIO_ICF_SBE_Msk                                            (0x1UL << SDIO_ICF_SBE_Pos)                                    /*!< 0x00000200 */
#define SDIO_ICF_SBE                                                SDIO_ICF_SBE_Msk                                               /*!<STBITERR flag clear bit */
#define SDIO_ICF_DBCP_Pos                                           (10U)
#define SDIO_ICF_DBCP_Msk                                           (0x1UL << SDIO_ICF_DBCP_Pos)                                   /*!< 0x00000400 */
#define SDIO_ICF_DBCP                                               SDIO_ICF_DBCP_Msk                                              /*!<DBCKEND flag clear bit  */
#define SDIO_ICF_SDIOIT_Pos                                         (22U)
#define SDIO_ICF_SDIOIT_Msk                                         (0x1UL << SDIO_ICF_SDIOIT_Pos)                                 /*!< 0x00400000 */
#define SDIO_ICF_SDIOIT                                             SDIO_ICF_SDIOIT_Msk                                            /*!<SDIOIT flag clear bit   */
#define SDIO_ICF_ATAEND_Pos                                         (23U)
#define SDIO_ICF_ATAEND_Msk                                         (0x1UL << SDIO_ICF_ATAEND_Pos)                                 /*!< 0x00800000 */
#define SDIO_ICF_ATAEND                                             SDIO_ICF_ATAEND_Msk                                            /*!<CEATAEND flag clear bit */

/******************  Bit definition for SDIO_MASK register  *******************/
#define SDIO_MASK_CCRCFAIL_Pos                                      (0U)
#define SDIO_MASK_CCRCFAIL_Msk                                      (0x1UL << SDIO_MASK_CCRCFAIL_Pos)                              /*!< 0x00000001 */
#define SDIO_MASK_CCRCFAIL                                          SDIO_MASK_CCRCFAIL_Msk                                         /*!<Command CRC Fail Interrupt Enable          */
#define SDIO_MASK_DCRCFAIL_Pos                                      (1U)
#define SDIO_MASK_DCRCFAIL_Msk                                      (0x1UL << SDIO_MASK_DCRCFAIL_Pos)                              /*!< 0x00000002 */
#define SDIO_MASK_DCRCFAIL                                          SDIO_MASK_DCRCFAIL_Msk                                         /*!<Data CRC Fail Interrupt Enable             */
#define SDIO_MASK_CMDTO_Pos                                         (2U)
#define SDIO_MASK_CMDTO_Msk                                         (0x1UL << SDIO_MASK_CMDTO_Pos)                                 /*!< 0x00000004 */
#define SDIO_MASK_CMDTO                                             SDIO_MASK_CMDTO_Msk                                            /*!<Command TimeOut Interrupt Enable           */
#define SDIO_MASK_DATATO_Pos                                        (3U)
#define SDIO_MASK_DATATO_Msk                                        (0x1UL << SDIO_MASK_DATATO_Pos)                                /*!< 0x00000008 */
#define SDIO_MASK_DATATO                                            SDIO_MASK_DATATO_Msk                                           /*!<Data TimeOut Interrupt Enable              */
#define SDIO_MASK_TXURER_Pos                                        (4U)
#define SDIO_MASK_TXURER_Msk                                        (0x1UL << SDIO_MASK_TXURER_Pos)                                /*!< 0x00000010 */
#define SDIO_MASK_TXURER                                            SDIO_MASK_TXURER_Msk                                           /*!<Tx FIFO UnderRun Error Interrupt Enable    */
#define SDIO_MASK_RXORER_Pos                                        (5U)
#define SDIO_MASK_RXORER_Msk                                        (0x1UL << SDIO_MASK_RXORER_Pos)                                /*!< 0x00000020 */
#define SDIO_MASK_RXORER                                            SDIO_MASK_RXORER_Msk                                           /*!<Rx FIFO OverRun Error Interrupt Enable     */
#define SDIO_MASK_CMDRESRC_Pos                                      (6U)
#define SDIO_MASK_CMDRESRC_Msk                                      (0x1UL << SDIO_MASK_CMDRESRC_Pos)                              /*!< 0x00000040 */
#define SDIO_MASK_CMDRESRC                                          SDIO_MASK_CMDRESRC_Msk                                         /*!<Command Response Received Interrupt Enable */
#define SDIO_MASK_CMDSENT_Pos                                       (7U)
#define SDIO_MASK_CMDSENT_Msk                                       (0x1UL << SDIO_MASK_CMDSENT_Pos)                               /*!< 0x00000080 */
#define SDIO_MASK_CMDSENT                                           SDIO_MASK_CMDSENT_Msk                                          /*!<Command Sent Interrupt Enable              */
#define SDIO_MASK_DATAEND_Pos                                       (8U)
#define SDIO_MASK_DATAEND_Msk                                       (0x1UL << SDIO_MASK_DATAEND_Pos)                               /*!< 0x00000100 */
#define SDIO_MASK_DATAEND                                           SDIO_MASK_DATAEND_Msk                                          /*!<Data End Interrupt Enable                  */
#define SDIO_MASK_STRTER_Pos                                        (9U)
#define SDIO_MASK_STRTER_Msk                                        (0x1UL << SDIO_MASK_STRTER_Pos)                                /*!< 0x00000200 */
#define SDIO_MASK_STRTER                                            SDIO_MASK_STRTER_Msk                                           /*!<Start Bit Error Interrupt Enable           */
#define SDIO_MASK_DBEND_Pos                                         (10U)
#define SDIO_MASK_DBEND_Msk                                         (0x1UL << SDIO_MASK_DBEND_Pos)                                 /*!< 0x00000400 */
#define SDIO_MASK_DBEND                                             SDIO_MASK_DBEND_Msk                                            /*!<Data Block End Interrupt Enable            */
#define SDIO_MASK_CMDACT_Pos                                        (11U)
#define SDIO_MASK_CMDACT_Msk                                        (0x1UL << SDIO_MASK_CMDACT_Pos)                                /*!< 0x00000800 */
#define SDIO_MASK_CMDACT                                            SDIO_MASK_CMDACT_Msk                                           /*!<CCommand Acting Interrupt Enable           */
#define SDIO_MASK_TXACT_Pos                                         (12U)
#define SDIO_MASK_TXACT_Msk                                         (0x1UL << SDIO_MASK_TXACT_Pos)                                 /*!< 0x00001000 */
#define SDIO_MASK_TXACT                                             SDIO_MASK_TXACT_Msk                                            /*!<Data Transmit Acting Interrupt Enable      */
#define SDIO_MASK_RXACT_Pos                                         (13U)
#define SDIO_MASK_RXACT_Msk                                         (0x1UL << SDIO_MASK_RXACT_Pos)                                 /*!< 0x00002000 */
#define SDIO_MASK_RXACT                                             SDIO_MASK_RXACT_Msk                                            /*!<Data receive acting interrupt enabled      */
#define SDIO_MASK_TXHFERT_Pos                                       (14U)
#define SDIO_MASK_TXHFERT_Msk                                       (0x1UL << SDIO_MASK_TXHFERT_Pos)                               /*!< 0x00004000 */
#define SDIO_MASK_TXHFERT                                           SDIO_MASK_TXHFERT_Msk                                          /*!<Tx FIFO Half Empty interrupt Enable        */
#define SDIO_MASK_RXHFFUL_Pos                                       (15U)
#define SDIO_MASK_RXHFFUL_Msk                                       (0x1UL << SDIO_MASK_RXHFFUL_Pos)                               /*!< 0x00008000 */
#define SDIO_MASK_RXHFFUL                                           SDIO_MASK_RXHFFUL_Msk                                          /*!<Rx FIFO Half Full interrupt Enable         */
#define SDIO_MASK_TXFUL_Pos                                         (16U)
#define SDIO_MASK_TXFUL_Msk                                         (0x1UL << SDIO_MASK_TXFUL_Pos)                                 /*!< 0x00010000 */
#define SDIO_MASK_TXFUL                                             SDIO_MASK_TXFUL_Msk                                            /*!<Tx FIFO Full interrupt Enable              */
#define SDIO_MASK_RXFUL_Pos                                         (17U)
#define SDIO_MASK_RXFUL_Msk                                         (0x1UL << SDIO_MASK_RXFUL_Pos)                                 /*!< 0x00020000 */
#define SDIO_MASK_RXFUL                                             SDIO_MASK_RXFUL_Msk                                            /*!<Rx FIFO Full interrupt Enable              */
#define SDIO_MASK_TXEPT_Pos                                         (18U)
#define SDIO_MASK_TXEPT_Msk                                         (0x1UL << SDIO_MASK_TXEPT_Pos)                                 /*!< 0x00040000 */
#define SDIO_MASK_TXEPT                                             SDIO_MASK_TXEPT_Msk                                            /*!<Tx FIFO Empty interrupt Enable             */
#define SDIO_MASK_RXFEIE_Pos                                        (19U)
#define SDIO_MASK_RXFEIE_Msk                                        (0x1UL << SDIO_MASK_RXFEIE_Pos)                                /*!< 0x00080000 */
#define SDIO_MASK_RXFEIE                                            SDIO_MASK_RXFEIE_Msk                                           /*!<Rx FIFO Empty interrupt Enable             */
#define SDIO_MASK_TXDAVB_Pos                                        (20U)
#define SDIO_MASK_TXDAVB_Msk                                        (0x1UL << SDIO_MASK_TXDAVB_Pos)                                /*!< 0x00100000 */
#define SDIO_MASK_TXDAVB                                            SDIO_MASK_TXDAVB_Msk                                           /*!<Data available in Tx FIFO interrupt Enable */
#define SDIO_MASK_RXDAVB_Pos                                        (21U)
#define SDIO_MASK_RXDAVB_Msk                                        (0x1UL << SDIO_MASK_RXDAVB_Pos)                                /*!< 0x00200000 */
#define SDIO_MASK_RXDAVB                                            SDIO_MASK_RXDAVB_Msk                                           /*!<Data available in Rx FIFO interrupt Enable */
#define SDIO_MASK_SDIOINTREC_Pos                                    (22U)
#define SDIO_MASK_SDIOINTREC_Msk                                    (0x1UL << SDIO_MASK_SDIOINTREC_Pos)                            /*!< 0x00400000 */
#define SDIO_MASK_SDIOINTREC                                        SDIO_MASK_SDIOINTREC_Msk                                       /*!<SDIO Mode Interrupt Received interrupt Enable */
#define SDIO_MASK_ATACLPREC_Pos                                     (23U)
#define SDIO_MASK_ATACLPREC_Msk                                     (0x1UL << SDIO_MASK_ATACLPREC_Pos)                             /*!< 0x00800000 */
#define SDIO_MASK_ATACLPREC                                         SDIO_MASK_ATACLPREC_Msk                                        /*!<CE-ATA command completion signal received Interrupt Enable */

/*****************  Bit definition for SDIO_FIFOCNT register  *****************/
#define SDIO_FIFOCNT_FIFOCNT_Pos                                    (0U)
#define SDIO_FIFOCNT_FIFOCNT_Msk                                    (0xFFFFFFUL << SDIO_FIFOCNT_FIFOCNT_Pos)                       /*!< 0x00FFFFFF */
#define SDIO_FIFOCNT_FIFOCNT                                        SDIO_FIFOCNT_FIFOCNT_Msk                                       /*!<Remaining number of words to be written to or read from the FIFO */

/******************  Bit definition for SDIO_FIFODATA register  *******************/
#define SDIO_FIFODATA_DATA_Pos                                      (0U)
#define SDIO_FIFODATA_DATA_Msk                                      (0xFFFFFFFFUL << SDIO_FIFODATA_DATA_Pos)                       /*!< 0xFFFFFFFF */
#define SDIO_FIFODATA_DATA                                          SDIO_FIFODATA_DATA_Msk                                         /*!<Receive and transmit FIFO data */

/******************************************************************************/
/*                                                                            */
/*                        Serial Peripheral Interface                         */
/*                                                                            */
/******************************************************************************/
#define SPI_I2S_FULLDUPLEX_SUPPORT                                                                                                 /*!< I2S Full-Duplex support */

/*******************  Bit definition for SPI_CTRL1 register  ********************/
#define SPI_CTRL1_CPHA_Pos                                          (0U)
#define SPI_CTRL1_CPHA_Msk                                          (0x1UL << SPI_CTRL1_CPHA_Pos)                                  /*!< 0x00000001 */
#define SPI_CTRL1_CPHA                                              SPI_CTRL1_CPHA_Msk                                             /*!<Clock Phase      */
#define SPI_CTRL1_CPOL_Pos                                          (1U)
#define SPI_CTRL1_CPOL_Msk                                          (0x1UL << SPI_CTRL1_CPOL_Pos)                                  /*!< 0x00000002 */
#define SPI_CTRL1_CPOL                                              SPI_CTRL1_CPOL_Msk                                             /*!<Clock Polarity   */
#define SPI_CTRL1_MSMCFG_Pos                                        (2U)
#define SPI_CTRL1_MSMCFG_Msk                                        (0x1UL << SPI_CTRL1_MSMCFG_Pos)                                /*!< 0x00000004 */
#define SPI_CTRL1_MSMCFG                                            SPI_CTRL1_MSMCFG_Msk                                           /*!<Master Selection */

#define SPI_CTRL1_BRSEL_Pos                                         (3U)
#define SPI_CTRL1_BRSEL_Msk                                         (0x7UL << SPI_CTRL1_BRSEL_Pos)                                 /*!< 0x00000038 */
#define SPI_CTRL1_BRSEL                                             SPI_CTRL1_BRSEL_Msk                                            /*!<BR[2:0] bits (Baud Rate Control) */
#define SPI_CTRL1_BRSEL_0                                           (0x1UL << SPI_CTRL1_BRSEL_Pos)                                 /*!< 0x00000008 */
#define SPI_CTRL1_BRSEL_1                                           (0x2UL << SPI_CTRL1_BRSEL_Pos)                                 /*!< 0x00000010 */
#define SPI_CTRL1_BRSEL_2                                           (0x4UL << SPI_CTRL1_BRSEL_Pos)                                 /*!< 0x00000020 */

#define SPI_CTRL1_SPIEN_Pos                                         (6U)
#define SPI_CTRL1_SPIEN_Msk                                         (0x1UL << SPI_CTRL1_SPIEN_Pos)                                 /*!< 0x00000040 */
#define SPI_CTRL1_SPIEN                                             SPI_CTRL1_SPIEN_Msk                                            /*!<SPI Enable                          */
#define SPI_CTRL1_LSBSEL_Pos                                        (7U)
#define SPI_CTRL1_LSBSEL_Msk                                        (0x1UL << SPI_CTRL1_LSBSEL_Pos)                                /*!< 0x00000080 */
#define SPI_CTRL1_LSBSEL                                            SPI_CTRL1_LSBSEL_Msk                                           /*!<Frame Format                        */
#define SPI_CTRL1_ISSEL_Pos                                         (8U)
#define SPI_CTRL1_ISSEL_Msk                                         (0x1UL << SPI_CTRL1_ISSEL_Pos)                                 /*!< 0x00000100 */
#define SPI_CTRL1_ISSEL                                             SPI_CTRL1_ISSEL_Msk                                            /*!<Internal slave select               */
#define SPI_CTRL1_SSEN_Pos                                          (9U)
#define SPI_CTRL1_SSEN_Msk                                          (0x1UL << SPI_CTRL1_SSEN_Pos)                                  /*!< 0x00000200 */
#define SPI_CTRL1_SSEN                                              SPI_CTRL1_SSEN_Msk                                             /*!<Software slave management           */
#define SPI_CTRL1_RXOMEN_Pos                                        (10U)
#define SPI_CTRL1_RXOMEN_Msk                                        (0x1UL << SPI_CTRL1_RXOMEN_Pos)                                /*!< 0x00000400 */
#define SPI_CTRL1_RXOMEN                                            SPI_CTRL1_RXOMEN_Msk                                           /*!<Receive only                        */
#define SPI_CTRL1_DFLSEL_Pos                                        (11U)
#define SPI_CTRL1_DFLSEL_Msk                                        (0x1UL << SPI_CTRL1_DFLSEL_Pos)                                /*!< 0x00000800 */
#define SPI_CTRL1_DFLSEL                                            SPI_CTRL1_DFLSEL_Msk                                           /*!<Data Frame Format                   */
#define SPI_CTRL1_CRCNXT_Pos                                        (12U)
#define SPI_CTRL1_CRCNXT_Msk                                        (0x1UL << SPI_CTRL1_CRCNXT_Pos)                                /*!< 0x00001000 */
#define SPI_CTRL1_CRCNXT                                            SPI_CTRL1_CRCNXT_Msk                                           /*!<Transmit CRC next                   */
#define SPI_CTRL1_CRCEN_Pos                                         (13U)
#define SPI_CTRL1_CRCEN_Msk                                         (0x1UL << SPI_CTRL1_CRCEN_Pos)                                 /*!< 0x00002000 */
#define SPI_CTRL1_CRCEN                                             SPI_CTRL1_CRCEN_Msk                                            /*!<Hardware CRC calculation enable     */
#define SPI_CTRL1_BMOEN_Pos                                         (14U)
#define SPI_CTRL1_BMOEN_Msk                                         (0x1UL << SPI_CTRL1_BMOEN_Pos)                                 /*!< 0x00004000 */
#define SPI_CTRL1_BMOEN                                             SPI_CTRL1_BMOEN_Msk                                            /*!<Output enable in bidirectional mode */
#define SPI_CTRL1_BMEN_Pos                                          (15U)
#define SPI_CTRL1_BMEN_Msk                                          (0x1UL << SPI_CTRL1_BMEN_Pos)                                  /*!< 0x00008000 */
#define SPI_CTRL1_BMEN                                              SPI_CTRL1_BMEN_Msk                                             /*!<Bidirectional data mode enable      */

/*******************  Bit definition for SPI_CTRL2 register  ********************/
#define SPI_CTRL2_RXDEN_Pos                                         (0U)
#define SPI_CTRL2_RXDEN_Msk                                         (0x1UL << SPI_CTRL2_RXDEN_Pos)                                 /*!< 0x00000001 */
#define SPI_CTRL2_RXDEN                                             SPI_CTRL2_RXDEN_Msk                                            /*!<Rx Buffer DMA Enable                 */
#define SPI_CTRL2_TXDEN_Pos                                         (1U)
#define SPI_CTRL2_TXDEN_Msk                                         (0x1UL << SPI_CTRL2_TXDEN_Pos)                                 /*!< 0x00000002 */
#define SPI_CTRL2_TXDEN                                             SPI_CTRL2_TXDEN_Msk                                            /*!<Tx Buffer DMA Enable                 */
#define SPI_CTRL2_SSOEN_Pos                                         (2U)
#define SPI_CTRL2_SSOEN_Msk                                         (0x1UL << SPI_CTRL2_SSOEN_Pos)                                 /*!< 0x00000004 */
#define SPI_CTRL2_SSOEN                                             SPI_CTRL2_SSOEN_Msk                                            /*!<SS Output Enable                     */
#define SPI_CTRL2_FRFCFG_Pos                                        (4U)
#define SPI_CTRL2_FRFCFG_Msk                                        (0x1UL << SPI_CTRL2_FRFCFG_Pos)                                /*!< 0x00000010 */
#define SPI_CTRL2_FRFCFG                                            SPI_CTRL2_FRFCFG_Msk                                           /*!<Frame Format                         */
#define SPI_CTRL2_ERRIEN_Pos                                        (5U)
#define SPI_CTRL2_ERRIEN_Msk                                        (0x1UL << SPI_CTRL2_ERRIEN_Pos)                                /*!< 0x00000020 */
#define SPI_CTRL2_ERRIEN                                            SPI_CTRL2_ERRIEN_Msk                                           /*!<Error Interrupt Enable               */
#define SPI_CTRL2_RXBNEIEN_Pos                                      (6U)
#define SPI_CTRL2_RXBNEIEN_Msk                                      (0x1UL << SPI_CTRL2_RXBNEIEN_Pos)                              /*!< 0x00000040 */
#define SPI_CTRL2_RXBNEIEN                                          SPI_CTRL2_RXBNEIEN_Msk                                         /*!<RX buffer Not Empty Interrupt Enable */
#define SPI_CTRL2_TXBEIEN_Pos                                       (7U)
#define SPI_CTRL2_TXBEIEN_Msk                                       (0x1UL << SPI_CTRL2_TXBEIEN_Pos)                               /*!< 0x00000080 */
#define SPI_CTRL2_TXBEIEN                                           SPI_CTRL2_TXBEIEN_Msk                                          /*!<Tx buffer Empty Interrupt Enable     */

/********************  Bit definition for SPI_STS register  ********************/
#define SPI_STS_RXBNEFLG_Pos                                        (0U)
#define SPI_STS_RXBNEFLG_Msk                                        (0x1UL << SPI_STS_RXBNEFLG_Pos)                                /*!< 0x00000001 */
#define SPI_STS_RXBNEFLG                                            SPI_STS_RXBNEFLG_Msk                                           /*!<Receive buffer Not Empty */
#define SPI_STS_TXBEFLG_Pos                                         (1U)
#define SPI_STS_TXBEFLG_Msk                                         (0x1UL << SPI_STS_TXBEFLG_Pos)                                 /*!< 0x00000002 */
#define SPI_STS_TXBEFLG                                             SPI_STS_TXBEFLG_Msk                                            /*!<Transmit buffer Empty    */
#define SPI_STS_SCHDIR_Pos                                          (2U)
#define SPI_STS_SCHDIR_Msk                                          (0x1UL << SPI_STS_SCHDIR_Pos)                                  /*!< 0x00000004 */
#define SPI_STS_SCHDIR                                              SPI_STS_SCHDIR_Msk                                             /*!<Channel side             */
#define SPI_STS_UDRFLG_Pos                                          (3U)
#define SPI_STS_UDRFLG_Msk                                          (0x1UL << SPI_STS_UDRFLG_Pos)                                  /*!< 0x00000008 */
#define SPI_STS_UDRFLG                                              SPI_STS_UDRFLG_Msk                                             /*!<Underrun flag            */
#define SPI_STS_CRCEFLG_Pos                                         (4U)
#define SPI_STS_CRCEFLG_Msk                                         (0x1UL << SPI_STS_CRCEFLG_Pos)                                 /*!< 0x00000010 */
#define SPI_STS_CRCEFLG                                             SPI_STS_CRCEFLG_Msk                                            /*!<CRC Error flag           */
#define SPI_STS_MEFLG_Pos                                           (5U)
#define SPI_STS_MEFLG_Msk                                           (0x1UL << SPI_STS_MEFLG_Pos)                                   /*!< 0x00000020 */
#define SPI_STS_MEFLG                                               SPI_STS_MEFLG_Msk                                              /*!<Mode fault               */
#define SPI_STS_OVRFLG_Pos                                          (6U)
#define SPI_STS_OVRFLG_Msk                                          (0x1UL << SPI_STS_OVRFLG_Pos)                                  /*!< 0x00000040 */
#define SPI_STS_OVRFLG                                              SPI_STS_OVRFLG_Msk                                             /*!<Overrun flag             */
#define SPI_STS_BSYFLG_Pos                                          (7U)
#define SPI_STS_BSYFLG_Msk                                          (0x1UL << SPI_STS_BSYFLG_Pos)                                  /*!< 0x00000080 */
#define SPI_STS_BSYFLG                                              SPI_STS_BSYFLG_Msk                                             /*!<Busy flag                */
#define SPI_STS_FFERR_Pos                                           (8U)
#define SPI_STS_FFERR_Msk                                           (0x1UL << SPI_STS_FFERR_Pos)                                   /*!< 0x00000100 */
#define SPI_STS_FFERR                                               SPI_STS_FFERR_Msk                                              /*!<Frame format error flag  */

/********************  Bit definition for SPI_DATA register  ********************/
#define SPI_DATA_DATA_Pos                                           (0U)
#define SPI_DATA_DATA_Msk                                           (0xFFFFUL << SPI_DATA_DATA_Pos)                                /*!< 0x0000FFFF */
#define SPI_DATA_DATA                                               SPI_DATA_DATA_Msk                                              /*!<Data Register           */

/*******************  Bit definition for SPI_CRCPOLY register  ******************/
#define SPI_CRCPOLY_CRCPOLY_Pos                                     (0U)
#define SPI_CRCPOLY_CRCPOLY_Msk                                     (0xFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos)                          /*!< 0x0000FFFF */
#define SPI_CRCPOLY_CRCPOLY                                         SPI_CRCPOLY_CRCPOLY_Msk                                        /*!<CRC polynomial register */

/******************  Bit definition for SPI_RXCRC register  ******************/
#define SPI_RXCRC_RXCRC_Pos                                         (0U)
#define SPI_RXCRC_RXCRC_Msk                                         (0xFFFFUL << SPI_RXCRC_RXCRC_Pos)                              /*!< 0x0000FFFF */
#define SPI_RXCRC_RXCRC                                             SPI_RXCRC_RXCRC_Msk                                            /*!<Rx CRC Register         */

/******************  Bit definition for SPI_TXCRC register  ******************/
#define SPI_TXCRC_TXCRC_Pos                                         (0U)
#define SPI_TXCRC_TXCRC_Msk                                         (0xFFFFUL << SPI_TXCRC_TXCRC_Pos)                              /*!< 0x0000FFFF */
#define SPI_TXCRC_TXCRC                                             SPI_TXCRC_TXCRC_Msk                                            /*!<Tx CRC Register         */

/******************  Bit definition for SPI_I2SCFG register  *****************/
#define SPI_I2SCFG_CHLEN_Pos                                        (0U)
#define SPI_I2SCFG_CHLEN_Msk                                        (0x1UL << SPI_I2SCFG_CHLEN_Pos)                                /*!< 0x00000001 */
#define SPI_I2SCFG_CHLEN                                            SPI_I2SCFG_CHLEN_Msk                                           /*!<Channel length (number of bits per audio channel) */

#define SPI_I2SCFG_DATALEN_Pos                                      (1U)
#define SPI_I2SCFG_DATALEN_Msk                                      (0x3UL << SPI_I2SCFG_DATALEN_Pos)                              /*!< 0x00000006 */
#define SPI_I2SCFG_DATALEN                                          SPI_I2SCFG_DATALEN_Msk                                         /*!<DATLEN[1:0] bits (Data length to be transferred)  */
#define SPI_I2SCFG_DATALEN_0                                        (0x1UL << SPI_I2SCFG_DATALEN_Pos)                              /*!< 0x00000002 */
#define SPI_I2SCFG_DATALEN_1                                        (0x2UL << SPI_I2SCFG_DATALEN_Pos)                              /*!< 0x00000004 */

#define SPI_I2SCFG_CPOL_Pos                                         (3U)
#define SPI_I2SCFG_CPOL_Msk                                         (0x1UL << SPI_I2SCFG_CPOL_Pos)                                 /*!< 0x00000008 */
#define SPI_I2SCFG_CPOL                                             SPI_I2SCFG_CPOL_Msk                                            /*!<steady state clock polarity               */

#define SPI_I2SCFG_I2SSSEL_Pos                                      (4U)
#define SPI_I2SCFG_I2SSSEL_Msk                                      (0x3UL << SPI_I2SCFG_I2SSSEL_Pos)                              /*!< 0x00000030 */
#define SPI_I2SCFG_I2SSSEL                                          SPI_I2SCFG_I2SSSEL_Msk                                         /*!<I2SSTD[1:0] bits (I2S standard selection) */
#define SPI_I2SCFG_I2SSSEL_0                                        (0x1UL << SPI_I2SCFG_I2SSSEL_Pos)                              /*!< 0x00000010 */
#define SPI_I2SCFG_I2SSSEL_1                                        (0x2UL << SPI_I2SCFG_I2SSSEL_Pos)                              /*!< 0x00000020 */

#define SPI_I2SCFG_PFSSEL_Pos                                       (7U)
#define SPI_I2SCFG_PFSSEL_Msk                                       (0x1UL << SPI_I2SCFG_PFSSEL_Pos)                               /*!< 0x00000080 */
#define SPI_I2SCFG_PFSSEL                                           SPI_I2SCFG_PFSSEL_Msk                                          /*!<PCM frame synchronization                 */

#define SPI_I2SCFG_I2SMOD_Pos                                       (8U)
#define SPI_I2SCFG_I2SMOD_Msk                                       (0x3UL << SPI_I2SCFG_I2SMOD_Pos)                               /*!< 0x00000300 */
#define SPI_I2SCFG_I2SMOD                                           SPI_I2SCFG_I2SMOD_Msk                                          /*!<I2SCFG[1:0] bits (I2S configuration mode) */
#define SPI_I2SCFG_I2SMOD_0                                         (0x1UL << SPI_I2SCFG_I2SMOD_Pos)                               /*!< 0x00000100 */
#define SPI_I2SCFG_I2SMOD_1                                         (0x2UL << SPI_I2SCFG_I2SMOD_Pos)                               /*!< 0x00000200 */

#define SPI_I2SCFG_I2SEN_Pos                                        (10U)
#define SPI_I2SCFG_I2SEN_Msk                                        (0x1UL << SPI_I2SCFG_I2SEN_Pos)                                /*!< 0x00000400 */
#define SPI_I2SCFG_I2SEN                                            SPI_I2SCFG_I2SEN_Msk                                           /*!<I2S Enable         */
#define SPI_I2SCFG_MODESEL_Pos                                      (11U)
#define SPI_I2SCFG_MODESEL_Msk                                      (0x1UL << SPI_I2SCFG_MODESEL_Pos)                              /*!< 0x00000800 */
#define SPI_I2SCFG_MODESEL                                          SPI_I2SCFG_MODESEL_Msk                                         /*!<I2S mode selection */

/******************  Bit definition for SPI_I2SPSC register  *******************/
#define SPI_I2SPSC_I2SPSC_Pos                                       (0U)
#define SPI_I2SPSC_I2SPSC_Msk                                       (0xFFUL << SPI_I2SPSC_I2SPSC_Pos)                              /*!< 0x000000FF */
#define SPI_I2SPSC_I2SPSC                                           SPI_I2SPSC_I2SPSC_Msk                                          /*!<I2S Linear prescaler         */
#define SPI_I2SPSC_ODDPS_Pos                                        (8U)
#define SPI_I2SPSC_ODDPS_Msk                                        (0x1UL << SPI_I2SPSC_ODDPS_Pos)                                /*!< 0x00000100 */
#define SPI_I2SPSC_ODDPS                                            SPI_I2SPSC_ODDPS_Msk                                           /*!<Odd factor for the prescaler */
#define SPI_I2SPSC_MCOEN_Pos                                        (9U)
#define SPI_I2SPSC_MCOEN_Msk                                        (0x1UL << SPI_I2SPSC_MCOEN_Pos)                                /*!< 0x00000200 */
#define SPI_I2SPSC_MCOEN                                            SPI_I2SPSC_MCOEN_Msk                                           /*!<Master Clock Output Enable   */

/******************************************************************************/
/*                                                                            */
/*                                 SYSCFG                                     */
/*                                                                            */
/******************************************************************************/
/******************  Bit definition for SYSCFG_MMSEL register  ***************/
#define SYSCFG_MMSEL_MMSEL_Pos                                      (0U)
#define SYSCFG_MMSEL_MMSEL_Msk                                      (0x3UL << SYSCFG_MMSEL_MMSEL_Pos)                              /*!< 0x00000003 */
#define SYSCFG_MMSEL_MMSEL                                          SYSCFG_MMSEL_MMSEL_Msk                                         /*!< SYSCFG_Memory Remap Config */
#define SYSCFG_MMSEL_MMSEL_0                                        (0x1UL << SYSCFG_MMSEL_MMSEL_Pos)                              /*!< 0x00000001 */
#define SYSCFG_MMSEL_MMSEL_1                                        (0x2UL << SYSCFG_MMSEL_MMSEL_Pos)                              /*!< 0x00000002 */
/******************  Bit definition for SYSCFG_PMCFG register  ******************/
#define SYSCFG_PMCFG_ENETSEL_Pos                                    (23U)
#define SYSCFG_PMCFG_ENETSEL_Msk                                    (0x1UL << SYSCFG_PMCFG_ENETSEL_Pos)                            /*!< 0x00800000 */
#define SYSCFG_PMCFG_ENETSEL                                        SYSCFG_PMCFG_ENETSEL_Msk                                       /*!<Ethernet PHY interface selection */
/* Old MII_RMII_SEL bit definition, maintained for legacy purpose */
#define SYSCFG_PMCFG_MII_RMII                                       SYSCFG_PMCFG_ENETSEL

/*****************  Bit definition for SYSCFG_EINTCFG1 register  ***************/
#define SYSCFG_EINTCFG1_EINT0_Pos                                   (0U)
#define SYSCFG_EINTCFG1_EINT0_Msk                                   (0xFUL << SYSCFG_EINTCFG1_EINT0_Pos)                           /*!< 0x0000000F */
#define SYSCFG_EINTCFG1_EINT0                                       SYSCFG_EINTCFG1_EINT0_Msk                                      /*!<EINT 0 configuration */
#define SYSCFG_EINTCFG1_EINT1_Pos                                   (4U)
#define SYSCFG_EINTCFG1_EINT1_Msk                                   (0xFUL << SYSCFG_EINTCFG1_EINT1_Pos)                           /*!< 0x000000F0 */
#define SYSCFG_EINTCFG1_EINT1                                       SYSCFG_EINTCFG1_EINT1_Msk                                      /*!<EINT 1 configuration */
#define SYSCFG_EINTCFG1_EINT2_Pos                                   (8U)
#define SYSCFG_EINTCFG1_EINT2_Msk                                   (0xFUL << SYSCFG_EINTCFG1_EINT2_Pos)                           /*!< 0x00000F00 */
#define SYSCFG_EINTCFG1_EINT2                                       SYSCFG_EINTCFG1_EINT2_Msk                                      /*!<EINT 2 configuration */
#define SYSCFG_EINTCFG1_EINT3_Pos                                   (12U)
#define SYSCFG_EINTCFG1_EINT3_Msk                                   (0xFUL << SYSCFG_EINTCFG1_EINT3_Pos)                           /*!< 0x0000F000 */
#define SYSCFG_EINTCFG1_EINT3                                       SYSCFG_EINTCFG1_EINT3_Msk                                      /*!<EINT 3 configuration */
/**
  * @brief   EINT0 configuration  
  */
#define SYSCFG_EINTCFG1_EINT0_PA                                    0x0000U                                                        /*!<PA[0] pin */
#define SYSCFG_EINTCFG1_EINT0_PB                                    0x0001U                                                        /*!<PB[0] pin */
#define SYSCFG_EINTCFG1_EINT0_PC                                    0x0002U                                                        /*!<PC[0] pin */
#define SYSCFG_EINTCFG1_EINT0_PD                                    0x0003U                                                        /*!<PD[0] pin */
#define SYSCFG_EINTCFG1_EINT0_PE                                    0x0004U                                                        /*!<PE[0] pin */
#define SYSCFG_EINTCFG1_EINT0_PF                                    0x0005U                                                        /*!<PF[0] pin */
#define SYSCFG_EINTCFG1_EINT0_PG                                    0x0006U                                                        /*!<PG[0] pin */
#define SYSCFG_EINTCFG1_EINT0_PH                                    0x0007U                                                        /*!<PH[0] pin */
#define SYSCFG_EINTCFG1_EINT0_PI                                    0x0008U                                                        /*!<PI[0] pin */

/**
  * @brief   EINT1 configuration  
  */
#define SYSCFG_EINTCFG1_EINT1_PA                                    0x0000U                                                        /*!<PA[1] pin */
#define SYSCFG_EINTCFG1_EINT1_PB                                    0x0010U                                                        /*!<PB[1] pin */
#define SYSCFG_EINTCFG1_EINT1_PC                                    0x0020U                                                        /*!<PC[1] pin */
#define SYSCFG_EINTCFG1_EINT1_PD                                    0x0030U                                                        /*!<PD[1] pin */
#define SYSCFG_EINTCFG1_EINT1_PE                                    0x0040U                                                        /*!<PE[1] pin */
#define SYSCFG_EINTCFG1_EINT1_PF                                    0x0050U                                                        /*!<PF[1] pin */
#define SYSCFG_EINTCFG1_EINT1_PG                                    0x0060U                                                        /*!<PG[1] pin */
#define SYSCFG_EINTCFG1_EINT1_PH                                    0x0070U                                                        /*!<PH[1] pin */
#define SYSCFG_EINTCFG1_EINT1_PI                                    0x0080U                                                        /*!<PI[1] pin */

/**
  * @brief   EINT2 configuration  
  */
#define SYSCFG_EINTCFG1_EINT2_PA                                    0x0000U                                                        /*!<PA[2] pin */
#define SYSCFG_EINTCFG1_EINT2_PB                                    0x0100U                                                        /*!<PB[2] pin */
#define SYSCFG_EINTCFG1_EINT2_PC                                    0x0200U                                                        /*!<PC[2] pin */
#define SYSCFG_EINTCFG1_EINT2_PD                                    0x0300U                                                        /*!<PD[2] pin */
#define SYSCFG_EINTCFG1_EINT2_PE                                    0x0400U                                                        /*!<PE[2] pin */
#define SYSCFG_EINTCFG1_EINT2_PF                                    0x0500U                                                        /*!<PF[2] pin */
#define SYSCFG_EINTCFG1_EINT2_PG                                    0x0600U                                                        /*!<PG[2] pin */
#define SYSCFG_EINTCFG1_EINT2_PH                                    0x0700U                                                        /*!<PH[2] pin */
#define SYSCFG_EINTCFG1_EINT2_PI                                    0x0800U                                                        /*!<PI[2] pin */

/**
  * @brief   EINT3 configuration  
  */
#define SYSCFG_EINTCFG1_EINT3_PA                                    0x0000U                                                        /*!<PA[3] pin */
#define SYSCFG_EINTCFG1_EINT3_PB                                    0x1000U                                                        /*!<PB[3] pin */
#define SYSCFG_EINTCFG1_EINT3_PC                                    0x2000U                                                        /*!<PC[3] pin */
#define SYSCFG_EINTCFG1_EINT3_PD                                    0x3000U                                                        /*!<PD[3] pin */
#define SYSCFG_EINTCFG1_EINT3_PE                                    0x4000U                                                        /*!<PE[3] pin */
#define SYSCFG_EINTCFG1_EINT3_PF                                    0x5000U                                                        /*!<PF[3] pin */
#define SYSCFG_EINTCFG1_EINT3_PG                                    0x6000U                                                        /*!<PG[3] pin */
#define SYSCFG_EINTCFG1_EINT3_PH                                    0x7000U                                                        /*!<PH[3] pin */
#define SYSCFG_EINTCFG1_EINT3_PI                                    0x8000U                                                        /*!<PI[3] pin */

/*****************  Bit definition for SYSCFG_EINTCFG2 register  ***************/
#define SYSCFG_EINTCFG2_EINT4_Pos                                   (0U)
#define SYSCFG_EINTCFG2_EINT4_Msk                                   (0xFUL << SYSCFG_EINTCFG2_EINT4_Pos)                           /*!< 0x0000000F */
#define SYSCFG_EINTCFG2_EINT4                                       SYSCFG_EINTCFG2_EINT4_Msk                                      /*!<EINT 4 configuration */
#define SYSCFG_EINTCFG2_EINT5_Pos                                   (4U)
#define SYSCFG_EINTCFG2_EINT5_Msk                                   (0xFUL << SYSCFG_EINTCFG2_EINT5_Pos)                           /*!< 0x000000F0 */
#define SYSCFG_EINTCFG2_EINT5                                       SYSCFG_EINTCFG2_EINT5_Msk                                      /*!<EINT 5 configuration */
#define SYSCFG_EINTCFG2_EINT6_Pos                                   (8U)
#define SYSCFG_EINTCFG2_EINT6_Msk                                   (0xFUL << SYSCFG_EINTCFG2_EINT6_Pos)                           /*!< 0x00000F00 */
#define SYSCFG_EINTCFG2_EINT6                                       SYSCFG_EINTCFG2_EINT6_Msk                                      /*!<EINT 6 configuration */
#define SYSCFG_EINTCFG2_EINT7_Pos                                   (12U)
#define SYSCFG_EINTCFG2_EINT7_Msk                                   (0xFUL << SYSCFG_EINTCFG2_EINT7_Pos)                           /*!< 0x0000F000 */
#define SYSCFG_EINTCFG2_EINT7                                       SYSCFG_EINTCFG2_EINT7_Msk                                      /*!<EINT 7 configuration */

/**
  * @brief   EINT4 configuration  
  */
#define SYSCFG_EINTCFG2_EINT4_PA                                    0x0000U                                                        /*!<PA[4] pin */
#define SYSCFG_EINTCFG2_EINT4_PB                                    0x0001U                                                        /*!<PB[4] pin */
#define SYSCFG_EINTCFG2_EINT4_PC                                    0x0002U                                                        /*!<PC[4] pin */
#define SYSCFG_EINTCFG2_EINT4_PD                                    0x0003U                                                        /*!<PD[4] pin */
#define SYSCFG_EINTCFG2_EINT4_PE                                    0x0004U                                                        /*!<PE[4] pin */
#define SYSCFG_EINTCFG2_EINT4_PF                                    0x0005U                                                        /*!<PF[4] pin */
#define SYSCFG_EINTCFG2_EINT4_PG                                    0x0006U                                                        /*!<PG[4] pin */
#define SYSCFG_EINTCFG2_EINT4_PH                                    0x0007U                                                        /*!<PH[4] pin */
#define SYSCFG_EINTCFG2_EINT4_PI                                    0x0008U                                                        /*!<PI[4] pin */

/**
  * @brief   EINT5 configuration  
  */
#define SYSCFG_EINTCFG2_EINT5_PA                                    0x0000U                                                        /*!<PA[5] pin */
#define SYSCFG_EINTCFG2_EINT5_PB                                    0x0010U                                                        /*!<PB[5] pin */
#define SYSCFG_EINTCFG2_EINT5_PC                                    0x0020U                                                        /*!<PC[5] pin */
#define SYSCFG_EINTCFG2_EINT5_PD                                    0x0030U                                                        /*!<PD[5] pin */
#define SYSCFG_EINTCFG2_EINT5_PE                                    0x0040U                                                        /*!<PE[5] pin */
#define SYSCFG_EINTCFG2_EINT5_PF                                    0x0050U                                                        /*!<PF[5] pin */
#define SYSCFG_EINTCFG2_EINT5_PG                                    0x0060U                                                        /*!<PG[5] pin */
#define SYSCFG_EINTCFG2_EINT5_PH                                    0x0070U                                                        /*!<PH[5] pin */
#define SYSCFG_EINTCFG2_EINT5_PI                                    0x0080U                                                        /*!<PI[5] pin */

/**
  * @brief   EINT6 configuration  
  */
#define SYSCFG_EINTCFG2_EINT6_PA                                    0x0000U                                                        /*!<PA[6] pin */
#define SYSCFG_EINTCFG2_EINT6_PB                                    0x0100U                                                        /*!<PB[6] pin */
#define SYSCFG_EINTCFG2_EINT6_PC                                    0x0200U                                                        /*!<PC[6] pin */
#define SYSCFG_EINTCFG2_EINT6_PD                                    0x0300U                                                        /*!<PD[6] pin */
#define SYSCFG_EINTCFG2_EINT6_PE                                    0x0400U                                                        /*!<PE[6] pin */
#define SYSCFG_EINTCFG2_EINT6_PF                                    0x0500U                                                        /*!<PF[6] pin */
#define SYSCFG_EINTCFG2_EINT6_PG                                    0x0600U                                                        /*!<PG[6] pin */
#define SYSCFG_EINTCFG2_EINT6_PH                                    0x0700U                                                        /*!<PH[6] pin */
#define SYSCFG_EINTCFG2_EINT6_PI                                    0x0800U                                                        /*!<PI[6] pin */

/**
  * @brief   EINT7 configuration  
  */
#define SYSCFG_EINTCFG2_EINT7_PA                                    0x0000U                                                        /*!<PA[7] pin */
#define SYSCFG_EINTCFG2_EINT7_PB                                    0x1000U                                                        /*!<PB[7] pin */
#define SYSCFG_EINTCFG2_EINT7_PC                                    0x2000U                                                        /*!<PC[7] pin */
#define SYSCFG_EINTCFG2_EINT7_PD                                    0x3000U                                                        /*!<PD[7] pin */
#define SYSCFG_EINTCFG2_EINT7_PE                                    0x4000U                                                        /*!<PE[7] pin */
#define SYSCFG_EINTCFG2_EINT7_PF                                    0x5000U                                                        /*!<PF[7] pin */
#define SYSCFG_EINTCFG2_EINT7_PG                                    0x6000U                                                        /*!<PG[7] pin */
#define SYSCFG_EINTCFG2_EINT7_PH                                    0x7000U                                                        /*!<PH[7] pin */
#define SYSCFG_EINTCFG2_EINT7_PI                                    0x8000U                                                        /*!<PI[7] pin */

/*****************  Bit definition for SYSCFG_EINTCFG3 register  ***************/
#define SYSCFG_EINTCFG3_EINT8_Pos                                   (0U)
#define SYSCFG_EINTCFG3_EINT8_Msk                                   (0xFUL << SYSCFG_EINTCFG3_EINT8_Pos)                           /*!< 0x0000000F */
#define SYSCFG_EINTCFG3_EINT8                                       SYSCFG_EINTCFG3_EINT8_Msk                                      /*!<EINT 8 configuration */
#define SYSCFG_EINTCFG3_EINT9_Pos                                   (4U)
#define SYSCFG_EINTCFG3_EINT9_Msk                                   (0xFUL << SYSCFG_EINTCFG3_EINT9_Pos)                           /*!< 0x000000F0 */
#define SYSCFG_EINTCFG3_EINT9                                       SYSCFG_EINTCFG3_EINT9_Msk                                      /*!<EINT 9 configuration */
#define SYSCFG_EINTCFG3_EINT10_Pos                                  (8U)
#define SYSCFG_EINTCFG3_EINT10_Msk                                  (0xFUL << SYSCFG_EINTCFG3_EINT10_Pos)                          /*!< 0x00000F00 */
#define SYSCFG_EINTCFG3_EINT10                                      SYSCFG_EINTCFG3_EINT10_Msk                                     /*!<EINT 10 configuration */
#define SYSCFG_EINTCFG3_EINT11_Pos                                  (12U)
#define SYSCFG_EINTCFG3_EINT11_Msk                                  (0xFUL << SYSCFG_EINTCFG3_EINT11_Pos)                          /*!< 0x0000F000 */
#define SYSCFG_EINTCFG3_EINT11                                      SYSCFG_EINTCFG3_EINT11_Msk                                     /*!<EINT 11 configuration */

/**
  * @brief   EINT8 configuration  
  */
#define SYSCFG_EINTCFG3_EINT8_PA                                    0x0000U                                                        /*!<PA[8] pin */
#define SYSCFG_EINTCFG3_EINT8_PB                                    0x0001U                                                        /*!<PB[8] pin */
#define SYSCFG_EINTCFG3_EINT8_PC                                    0x0002U                                                        /*!<PC[8] pin */
#define SYSCFG_EINTCFG3_EINT8_PD                                    0x0003U                                                        /*!<PD[8] pin */
#define SYSCFG_EINTCFG3_EINT8_PE                                    0x0004U                                                        /*!<PE[8] pin */
#define SYSCFG_EINTCFG3_EINT8_PF                                    0x0005U                                                        /*!<PF[8] pin */
#define SYSCFG_EINTCFG3_EINT8_PG                                    0x0006U                                                        /*!<PG[8] pin */
#define SYSCFG_EINTCFG3_EINT8_PH                                    0x0007U                                                        /*!<PH[8] pin */
#define SYSCFG_EINTCFG3_EINT8_PI                                    0x0008U                                                        /*!<PI[8] pin */

/**
  * @brief   EINT9 configuration  
  */
#define SYSCFG_EINTCFG3_EINT9_PA                                    0x0000U                                                        /*!<PA[9] pin */
#define SYSCFG_EINTCFG3_EINT9_PB                                    0x0010U                                                        /*!<PB[9] pin */
#define SYSCFG_EINTCFG3_EINT9_PC                                    0x0020U                                                        /*!<PC[9] pin */
#define SYSCFG_EINTCFG3_EINT9_PD                                    0x0030U                                                        /*!<PD[9] pin */
#define SYSCFG_EINTCFG3_EINT9_PE                                    0x0040U                                                        /*!<PE[9] pin */
#define SYSCFG_EINTCFG3_EINT9_PF                                    0x0050U                                                        /*!<PF[9] pin */
#define SYSCFG_EINTCFG3_EINT9_PG                                    0x0060U                                                        /*!<PG[9] pin */
#define SYSCFG_EINTCFG3_EINT9_PH                                    0x0070U                                                        /*!<PH[9] pin */
#define SYSCFG_EINTCFG3_EINT9_PI                                    0x0080U                                                        /*!<PI[9] pin */

/**
  * @brief   EINT10 configuration  
  */
#define SYSCFG_EINTCFG3_EINT10_PA                                   0x0000U                                                        /*!<PA[10] pin */
#define SYSCFG_EINTCFG3_EINT10_PB                                   0x0100U                                                        /*!<PB[10] pin */
#define SYSCFG_EINTCFG3_EINT10_PC                                   0x0200U                                                        /*!<PC[10] pin */
#define SYSCFG_EINTCFG3_EINT10_PD                                   0x0300U                                                        /*!<PD[10] pin */
#define SYSCFG_EINTCFG3_EINT10_PE                                   0x0400U                                                        /*!<PE[10] pin */
#define SYSCFG_EINTCFG3_EINT10_PF                                   0x0500U                                                        /*!<PF[10] pin */
#define SYSCFG_EINTCFG3_EINT10_PG                                   0x0600U                                                        /*!<PG[10] pin */
#define SYSCFG_EINTCFG3_EINT10_PH                                   0x0700U                                                        /*!<PH[10] pin */
#define SYSCFG_EINTCFG3_EINT10_PI                                   0x0800U                                                        /*!<PI[10] pin */

/**
  * @brief   EINT11 configuration  
  */
#define SYSCFG_EINTCFG3_EINT11_PA                                   0x0000U                                                        /*!<PA[11] pin */
#define SYSCFG_EINTCFG3_EINT11_PB                                   0x1000U                                                        /*!<PB[11] pin */
#define SYSCFG_EINTCFG3_EINT11_PC                                   0x2000U                                                        /*!<PC[11] pin */
#define SYSCFG_EINTCFG3_EINT11_PD                                   0x3000U                                                        /*!<PD[11] pin */
#define SYSCFG_EINTCFG3_EINT11_PE                                   0x4000U                                                        /*!<PE[11] pin */
#define SYSCFG_EINTCFG3_EINT11_PF                                   0x5000U                                                        /*!<PF[11] pin */
#define SYSCFG_EINTCFG3_EINT11_PG                                   0x6000U                                                        /*!<PG[11] pin */
#define SYSCFG_EINTCFG3_EINT11_PH                                   0x7000U                                                        /*!<PH[11] pin */
#define SYSCFG_EINTCFG3_EINT11_PI                                   0x8000U                                                        /*!<PI[11] pin */

/*****************  Bit definition for SYSCFG_EINTCFG4 register  ***************/
#define SYSCFG_EINTCFG4_EINT12_Pos                                  (0U)
#define SYSCFG_EINTCFG4_EINT12_Msk                                  (0xFUL << SYSCFG_EINTCFG4_EINT12_Pos)                          /*!< 0x0000000F */
#define SYSCFG_EINTCFG4_EINT12                                      SYSCFG_EINTCFG4_EINT12_Msk                                     /*!<EINT 12 configuration */
#define SYSCFG_EINTCFG4_EINT13_Pos                                  (4U)
#define SYSCFG_EINTCFG4_EINT13_Msk                                  (0xFUL << SYSCFG_EINTCFG4_EINT13_Pos)                          /*!< 0x000000F0 */
#define SYSCFG_EINTCFG4_EINT13                                      SYSCFG_EINTCFG4_EINT13_Msk                                     /*!<EINT 13 configuration */
#define SYSCFG_EINTCFG4_EINT14_Pos                                  (8U)
#define SYSCFG_EINTCFG4_EINT14_Msk                                  (0xFUL << SYSCFG_EINTCFG4_EINT14_Pos)                          /*!< 0x00000F00 */
#define SYSCFG_EINTCFG4_EINT14                                      SYSCFG_EINTCFG4_EINT14_Msk                                     /*!<EINT 14 configuration */
#define SYSCFG_EINTCFG4_EINT15_Pos                                  (12U)
#define SYSCFG_EINTCFG4_EINT15_Msk                                  (0xFUL << SYSCFG_EINTCFG4_EINT15_Pos)                          /*!< 0x0000F000 */
#define SYSCFG_EINTCFG4_EINT15                                      SYSCFG_EINTCFG4_EINT15_Msk                                     /*!<EINT 15 configuration */

/**
  * @brief   EINT12 configuration  
  */
#define SYSCFG_EINTCFG4_EINT12_PA                                   0x0000U                                                        /*!<PA[12] pin */
#define SYSCFG_EINTCFG4_EINT12_PB                                   0x0001U                                                        /*!<PB[12] pin */
#define SYSCFG_EINTCFG4_EINT12_PC                                   0x0002U                                                        /*!<PC[12] pin */
#define SYSCFG_EINTCFG4_EINT12_PD                                   0x0003U                                                        /*!<PD[12] pin */
#define SYSCFG_EINTCFG4_EINT12_PE                                   0x0004U                                                        /*!<PE[12] pin */
#define SYSCFG_EINTCFG4_EINT12_PF                                   0x0005U                                                        /*!<PF[12] pin */
#define SYSCFG_EINTCFG4_EINT12_PG                                   0x0006U                                                        /*!<PG[12] pin */
#define SYSCFG_EINTCFG4_EINT12_PH                                   0x0007U                                                        /*!<PH[12] pin */

/**
  * @brief   EINT13 configuration  
  */
#define SYSCFG_EINTCFG4_EINT13_PA                                   0x0000U                                                        /*!<PA[13] pin */
#define SYSCFG_EINTCFG4_EINT13_PB                                   0x0010U                                                        /*!<PB[13] pin */
#define SYSCFG_EINTCFG4_EINT13_PC                                   0x0020U                                                        /*!<PC[13] pin */
#define SYSCFG_EINTCFG4_EINT13_PD                                   0x0030U                                                        /*!<PD[13] pin */
#define SYSCFG_EINTCFG4_EINT13_PE                                   0x0040U                                                        /*!<PE[13] pin */
#define SYSCFG_EINTCFG4_EINT13_PF                                   0x0050U                                                        /*!<PF[13] pin */
#define SYSCFG_EINTCFG4_EINT13_PG                                   0x0060U                                                        /*!<PG[13] pin */
#define SYSCFG_EINTCFG4_EINT13_PH                                   0x0070U                                                        /*!<PH[13] pin */

/**
  * @brief   EINT14 configuration  
  */
#define SYSCFG_EINTCFG4_EINT14_PA                                   0x0000U                                                        /*!<PA[14] pin */
#define SYSCFG_EINTCFG4_EINT14_PB                                   0x0100U                                                        /*!<PB[14] pin */
#define SYSCFG_EINTCFG4_EINT14_PC                                   0x0200U                                                        /*!<PC[14] pin */
#define SYSCFG_EINTCFG4_EINT14_PD                                   0x0300U                                                        /*!<PD[14] pin */
#define SYSCFG_EINTCFG4_EINT14_PE                                   0x0400U                                                        /*!<PE[14] pin */
#define SYSCFG_EINTCFG4_EINT14_PF                                   0x0500U                                                        /*!<PF[14] pin */
#define SYSCFG_EINTCFG4_EINT14_PG                                   0x0600U                                                        /*!<PG[14] pin */
#define SYSCFG_EINTCFG4_EINT14_PH                                   0x0700U                                                        /*!<PH[14] pin */

/**
  * @brief   EINT15 configuration  
  */
#define SYSCFG_EINTCFG4_EINT15_PA                                   0x0000U                                                        /*!<PA[15] pin */
#define SYSCFG_EINTCFG4_EINT15_PB                                   0x1000U                                                        /*!<PB[15] pin */
#define SYSCFG_EINTCFG4_EINT15_PC                                   0x2000U                                                        /*!<PC[15] pin */
#define SYSCFG_EINTCFG4_EINT15_PD                                   0x3000U                                                        /*!<PD[15] pin */
#define SYSCFG_EINTCFG4_EINT15_PE                                   0x4000U                                                        /*!<PE[15] pin */
#define SYSCFG_EINTCFG4_EINT15_PF                                   0x5000U                                                        /*!<PF[15] pin */
#define SYSCFG_EINTCFG4_EINT15_PG                                   0x6000U                                                        /*!<PG[15] pin */
#define SYSCFG_EINTCFG4_EINT15_PH                                   0x7000U                                                        /*!<PH[15] pin */

/******************  Bit definition for SYSCFG_CCCTRL register  ****************/
#define SYSCFG_CCCTRL_CCPD_Pos                                      (0U)
#define SYSCFG_CCCTRL_CCPD_Msk                                      (0x1UL << SYSCFG_CCCTRL_CCPD_Pos)                              /*!< 0x00000001 */
#define SYSCFG_CCCTRL_CCPD                                          SYSCFG_CCCTRL_CCPD_Msk                                         /*!<Compensation cell ready flag */
#define SYSCFG_CCCTRL_EDYFLG_Pos                                    (8U)
#define SYSCFG_CCCTRL_EDYFLG_Msk                                    (0x1UL << SYSCFG_CCCTRL_EDYFLG_Pos)                            /*!< 0x00000100 */
#define SYSCFG_CCCTRL_EDYFLG                                        SYSCFG_CCCTRL_EDYFLG_Msk                                       /*!<Compensation cell power-down */

/******************************************************************************/
/*                                                                            */
/*                                    TMR                                     */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for TMR_CTRL1 register  ********************/
#define TMR_CTRL1_CNTEN_Pos                                         (0U)
#define TMR_CTRL1_CNTEN_Msk                                         (0x1UL << TMR_CTRL1_CNTEN_Pos)                                 /*!< 0x00000001 */
#define TMR_CTRL1_CNTEN                                             TMR_CTRL1_CNTEN_Msk                                            /*!<Counter enable        */
#define TMR_CTRL1_UD_Pos                                            (1U)
#define TMR_CTRL1_UD_Msk                                            (0x1UL << TMR_CTRL1_UD_Pos)                                    /*!< 0x00000002 */
#define TMR_CTRL1_UD                                                TMR_CTRL1_UD_Msk                                               /*!<Update disable        */
#define TMR_CTRL1_URSSEL_Pos                                        (2U)
#define TMR_CTRL1_URSSEL_Msk                                        (0x1UL << TMR_CTRL1_URSSEL_Pos)                                /*!< 0x00000004 */
#define TMR_CTRL1_URSSEL                                            TMR_CTRL1_URSSEL_Msk                                           /*!<Update request source */
#define TMR_CTRL1_SPMEN_Pos                                         (3U)
#define TMR_CTRL1_SPMEN_Msk                                         (0x1UL << TMR_CTRL1_SPMEN_Pos)                                 /*!< 0x00000008 */
#define TMR_CTRL1_SPMEN                                             TMR_CTRL1_SPMEN_Msk                                            /*!<One pulse mode        */
#define TMR_CTRL1_CNTDIR_Pos                                        (4U)
#define TMR_CTRL1_CNTDIR_Msk                                        (0x1UL << TMR_CTRL1_CNTDIR_Pos)                                /*!< 0x00000010 */
#define TMR_CTRL1_CNTDIR                                            TMR_CTRL1_CNTDIR_Msk                                           /*!<Direction             */

#define TMR_CTRL1_CAMSEL_Pos                                        (5U)
#define TMR_CTRL1_CAMSEL_Msk                                        (0x3UL << TMR_CTRL1_CAMSEL_Pos)                                /*!< 0x00000060 */
#define TMR_CTRL1_CAMSEL                                            TMR_CTRL1_CAMSEL_Msk                                           /*!<CMS[1:0] bits (Center-aligned mode selection) */
#define TMR_CTRL1_CAMSEL_0                                          (0x1UL << TMR_CTRL1_CAMSEL_Pos)                                /*!< 0x0020 */
#define TMR_CTRL1_CAMSEL_1                                          (0x2UL << TMR_CTRL1_CAMSEL_Pos)                                /*!< 0x0040 */

#define TMR_CTRL1_ARPEN_Pos                                         (7U)
#define TMR_CTRL1_ARPEN_Msk                                         (0x1UL << TMR_CTRL1_ARPEN_Pos)                                 /*!< 0x00000080 */
#define TMR_CTRL1_ARPEN                                             TMR_CTRL1_ARPEN_Msk                                            /*!<Auto-reload preload enable     */

#define TMR_CTRL1_CLKDIV_Pos                                        (8U)
#define TMR_CTRL1_CLKDIV_Msk                                        (0x3UL << TMR_CTRL1_CLKDIV_Pos)                                /*!< 0x00000300 */
#define TMR_CTRL1_CLKDIV                                            TMR_CTRL1_CLKDIV_Msk                                           /*!<CKD[1:0] bits (clock division) */
#define TMR_CTRL1_CLKDIV_0                                          (0x1UL << TMR_CTRL1_CLKDIV_Pos)                                /*!< 0x0100 */
#define TMR_CTRL1_CLKDIV_1                                          (0x2UL << TMR_CTRL1_CLKDIV_Pos)                                /*!< 0x0200 */

/*******************  Bit definition for TMR_CTRL2 register  ********************/
#define TMR_CTRL2_CCPEN_Pos                                         (0U)
#define TMR_CTRL2_CCPEN_Msk                                         (0x1UL << TMR_CTRL2_CCPEN_Pos)                                 /*!< 0x00000001 */
#define TMR_CTRL2_CCPEN                                             TMR_CTRL2_CCPEN_Msk                                            /*!<Capture/Compare Preloaded Control        */
#define TMR_CTRL2_CCUSEL_Pos                                        (2U)
#define TMR_CTRL2_CCUSEL_Msk                                        (0x1UL << TMR_CTRL2_CCUSEL_Pos)                                /*!< 0x00000004 */
#define TMR_CTRL2_CCUSEL                                            TMR_CTRL2_CCUSEL_Msk                                           /*!<Capture/Compare Control Update Selection */
#define TMR_CTRL2_CCDSEL_Pos                                        (3U)
#define TMR_CTRL2_CCDSEL_Msk                                        (0x1UL << TMR_CTRL2_CCDSEL_Pos)                                /*!< 0x00000008 */
#define TMR_CTRL2_CCDSEL                                            TMR_CTRL2_CCDSEL_Msk                                           /*!<Capture/Compare DMA Selection            */

#define TMR_CTRL2_MMSEL_Pos                                         (4U)
#define TMR_CTRL2_MMSEL_Msk                                         (0x7UL << TMR_CTRL2_MMSEL_Pos)                                 /*!< 0x00000070 */
#define TMR_CTRL2_MMSEL                                             TMR_CTRL2_MMSEL_Msk                                            /*!<MMS[2:0] bits (Master Mode Selection) */
#define TMR_CTRL2_MMSEL_0                                           (0x1UL << TMR_CTRL2_MMSEL_Pos)                                 /*!< 0x0010 */
#define TMR_CTRL2_MMSEL_1                                           (0x2UL << TMR_CTRL2_MMSEL_Pos)                                 /*!< 0x0020 */
#define TMR_CTRL2_MMSEL_2                                           (0x4UL << TMR_CTRL2_MMSEL_Pos)                                 /*!< 0x0040 */

#define TMR_CTRL2_TI1SEL_Pos                                        (7U)
#define TMR_CTRL2_TI1SEL_Msk                                        (0x1UL << TMR_CTRL2_TI1SEL_Pos)                                /*!< 0x00000080 */
#define TMR_CTRL2_TI1SEL                                            TMR_CTRL2_TI1SEL_Msk                                           /*!<TI1 Selection */
#define TMR_CTRL2_OC1OIS_Pos                                        (8U)
#define TMR_CTRL2_OC1OIS_Msk                                        (0x1UL << TMR_CTRL2_OC1OIS_Pos)                                /*!< 0x00000100 */
#define TMR_CTRL2_OC1OIS                                            TMR_CTRL2_OC1OIS_Msk                                           /*!<Output Idle state 1 (OC1 output)  */
#define TMR_CTRL2_OC1NOIS_Pos                                       (9U)
#define TMR_CTRL2_OC1NOIS_Msk                                       (0x1UL << TMR_CTRL2_OC1NOIS_Pos)                               /*!< 0x00000200 */
#define TMR_CTRL2_OC1NOIS                                           TMR_CTRL2_OC1NOIS_Msk                                          /*!<Output Idle state 1 (OC1N output) */
#define TMR_CTRL2_OC2OIS_Pos                                        (10U)
#define TMR_CTRL2_OC2OIS_Msk                                        (0x1UL << TMR_CTRL2_OC2OIS_Pos)                                /*!< 0x00000400 */
#define TMR_CTRL2_OC2OIS                                            TMR_CTRL2_OC2OIS_Msk                                           /*!<Output Idle state 2 (OC2 output)  */
#define TMR_CTRL2_OC2NOIS_Pos                                       (11U)
#define TMR_CTRL2_OC2NOIS_Msk                                       (0x1UL << TMR_CTRL2_OC2NOIS_Pos)                               /*!< 0x00000800 */
#define TMR_CTRL2_OC2NOIS                                           TMR_CTRL2_OC2NOIS_Msk                                          /*!<Output Idle state 2 (OC2N output) */
#define TMR_CTRL2_OC3OIS_Pos                                        (12U)
#define TMR_CTRL2_OC3OIS_Msk                                        (0x1UL << TMR_CTRL2_OC3OIS_Pos)                                /*!< 0x00001000 */
#define TMR_CTRL2_OC3OIS                                            TMR_CTRL2_OC3OIS_Msk                                           /*!<Output Idle state 3 (OC3 output)  */
#define TMR_CTRL2_OC3NOIS_Pos                                       (13U)
#define TMR_CTRL2_OC3NOIS_Msk                                       (0x1UL << TMR_CTRL2_OC3NOIS_Pos)                               /*!< 0x00002000 */
#define TMR_CTRL2_OC3NOIS                                           TMR_CTRL2_OC3NOIS_Msk                                          /*!<Output Idle state 3 (OC3N output) */
#define TMR_CTRL2_OC4OIS_Pos                                        (14U)
#define TMR_CTRL2_OC4OIS_Msk                                        (0x1UL << TMR_CTRL2_OC4OIS_Pos)                                /*!< 0x00004000 */
#define TMR_CTRL2_OC4OIS                                            TMR_CTRL2_OC4OIS_Msk                                           /*!<Output Idle state 4 (OC4 output)  */

/*******************  Bit definition for TMR_SMCTRL register  *******************/
#define TMR_SMCTRL_SMFSEL_Pos                                       (0U)
#define TMR_SMCTRL_SMFSEL_Msk                                       (0x7UL << TMR_SMCTRL_SMFSEL_Pos)                               /*!< 0x00000007 */
#define TMR_SMCTRL_SMFSEL                                           TMR_SMCTRL_SMFSEL_Msk                                          /*!<SMS[2:0] bits (Slave mode selection)    */
#define TMR_SMCTRL_SMFSEL_0                                         (0x1UL << TMR_SMCTRL_SMFSEL_Pos)                               /*!< 0x0001 */
#define TMR_SMCTRL_SMFSEL_1                                         (0x2UL << TMR_SMCTRL_SMFSEL_Pos)                               /*!< 0x0002 */
#define TMR_SMCTRL_SMFSEL_2                                         (0x4UL << TMR_SMCTRL_SMFSEL_Pos)                               /*!< 0x0004 */

#define TMR_SMCTRL_TRGSEL_Pos                                       (4U)
#define TMR_SMCTRL_TRGSEL_Msk                                       (0x7UL << TMR_SMCTRL_TRGSEL_Pos)                               /*!< 0x00000070 */
#define TMR_SMCTRL_TRGSEL                                           TMR_SMCTRL_TRGSEL_Msk                                          /*!<TS[2:0] bits (Trigger selection)        */
#define TMR_SMCTRL_TRGSEL_0                                         (0x1UL << TMR_SMCTRL_TRGSEL_Pos)                               /*!< 0x0010 */
#define TMR_SMCTRL_TRGSEL_1                                         (0x2UL << TMR_SMCTRL_TRGSEL_Pos)                               /*!< 0x0020 */
#define TMR_SMCTRL_TRGSEL_2                                         (0x4UL << TMR_SMCTRL_TRGSEL_Pos)                               /*!< 0x0040 */

#define TMR_SMCTRL_MSMEN_Pos                                        (7U)
#define TMR_SMCTRL_MSMEN_Msk                                        (0x1UL << TMR_SMCTRL_MSMEN_Pos)                                /*!< 0x00000080 */
#define TMR_SMCTRL_MSMEN                                            TMR_SMCTRL_MSMEN_Msk                                           /*!<Master/slave mode                       */

#define TMR_SMCTRL_ETFCFG_Pos                                       (8U)
#define TMR_SMCTRL_ETFCFG_Msk                                       (0xFUL << TMR_SMCTRL_ETFCFG_Pos)                               /*!< 0x00000F00 */
#define TMR_SMCTRL_ETFCFG                                           TMR_SMCTRL_ETFCFG_Msk                                          /*!<ETF[3:0] bits (External trigger filter) */
#define TMR_SMCTRL_ETFCFG_0                                         (0x1UL << TMR_SMCTRL_ETFCFG_Pos)                               /*!< 0x0100 */
#define TMR_SMCTRL_ETFCFG_1                                         (0x2UL << TMR_SMCTRL_ETFCFG_Pos)                               /*!< 0x0200 */
#define TMR_SMCTRL_ETFCFG_2                                         (0x4UL << TMR_SMCTRL_ETFCFG_Pos)                               /*!< 0x0400 */
#define TMR_SMCTRL_ETFCFG_3                                         (0x8UL << TMR_SMCTRL_ETFCFG_Pos)                               /*!< 0x0800 */

#define TMR_SMCTRL_ETPCFG_Pos                                       (12U)
#define TMR_SMCTRL_ETPCFG_Msk                                       (0x3UL << TMR_SMCTRL_ETPCFG_Pos)                               /*!< 0x00003000 */
#define TMR_SMCTRL_ETPCFG                                           TMR_SMCTRL_ETPCFG_Msk                                          /*!<ETPS[1:0] bits (External trigger prescaler) */
#define TMR_SMCTRL_ETPCFG_0                                         (0x1UL << TMR_SMCTRL_ETPCFG_Pos)                               /*!< 0x1000 */
#define TMR_SMCTRL_ETPCFG_1                                         (0x2UL << TMR_SMCTRL_ETPCFG_Pos)                               /*!< 0x2000 */

#define TMR_SMCTRL_ECEN_Pos                                         (14U)
#define TMR_SMCTRL_ECEN_Msk                                         (0x1UL << TMR_SMCTRL_ECEN_Pos)                                 /*!< 0x00004000 */
#define TMR_SMCTRL_ECEN                                             TMR_SMCTRL_ECEN_Msk                                            /*!<External clock enable     */
#define TMR_SMCTRL_ETPOL_Pos                                        (15U)
#define TMR_SMCTRL_ETPOL_Msk                                        (0x1UL << TMR_SMCTRL_ETPOL_Pos)                                /*!< 0x00008000 */
#define TMR_SMCTRL_ETPOL                                            TMR_SMCTRL_ETPOL_Msk                                           /*!<External trigger polarity */

/*******************  Bit definition for TMR_DIEN register  *******************/
#define TMR_DIEN_UIEN_Pos                                           (0U)
#define TMR_DIEN_UIEN_Msk                                           (0x1UL << TMR_DIEN_UIEN_Pos)                                   /*!< 0x00000001 */
#define TMR_DIEN_UIEN                                               TMR_DIEN_UIEN_Msk                                              /*!<Update interrupt enable */
#define TMR_DIEN_CC1IEN_Pos                                         (1U)
#define TMR_DIEN_CC1IEN_Msk                                         (0x1UL << TMR_DIEN_CC1IEN_Pos)                                 /*!< 0x00000002 */
#define TMR_DIEN_CC1IEN                                             TMR_DIEN_CC1IEN_Msk                                            /*!<Capture/Compare 1 interrupt enable   */
#define TMR_DIEN_CC2IEN_Pos                                         (2U)
#define TMR_DIEN_CC2IEN_Msk                                         (0x1UL << TMR_DIEN_CC2IEN_Pos)                                 /*!< 0x00000004 */
#define TMR_DIEN_CC2IEN                                             TMR_DIEN_CC2IEN_Msk                                            /*!<Capture/Compare 2 interrupt enable   */
#define TMR_DIEN_CC3IEN_Pos                                         (3U)
#define TMR_DIEN_CC3IEN_Msk                                         (0x1UL << TMR_DIEN_CC3IEN_Pos)                                 /*!< 0x00000008 */
#define TMR_DIEN_CC3IEN                                             TMR_DIEN_CC3IEN_Msk                                            /*!<Capture/Compare 3 interrupt enable   */
#define TMR_DIEN_CC4IEN_Pos                                         (4U)
#define TMR_DIEN_CC4IEN_Msk                                         (0x1UL << TMR_DIEN_CC4IEN_Pos)                                 /*!< 0x00000010 */
#define TMR_DIEN_CC4IEN                                             TMR_DIEN_CC4IEN_Msk                                            /*!<Capture/Compare 4 interrupt enable   */
#define TMR_DIEN_COMIEN_Pos                                         (5U)
#define TMR_DIEN_COMIEN_Msk                                         (0x1UL << TMR_DIEN_COMIEN_Pos)                                 /*!< 0x00000020 */
#define TMR_DIEN_COMIEN                                             TMR_DIEN_COMIEN_Msk                                            /*!<COM interrupt enable                 */
#define TMR_DIEN_TRGIEN_Pos                                         (6U)
#define TMR_DIEN_TRGIEN_Msk                                         (0x1UL << TMR_DIEN_TRGIEN_Pos)                                 /*!< 0x00000040 */
#define TMR_DIEN_TRGIEN                                             TMR_DIEN_TRGIEN_Msk                                            /*!<Trigger interrupt enable             */
#define TMR_DIEN_BRKIEN_Pos                                         (7U)
#define TMR_DIEN_BRKIEN_Msk                                         (0x1UL << TMR_DIEN_BRKIEN_Pos)                                 /*!< 0x00000080 */
#define TMR_DIEN_BRKIEN                                             TMR_DIEN_BRKIEN_Msk                                            /*!<Break interrupt enable               */
#define TMR_DIEN_UDIEN_Pos                                          (8U)
#define TMR_DIEN_UDIEN_Msk                                          (0x1UL << TMR_DIEN_UDIEN_Pos)                                  /*!< 0x00000100 */
#define TMR_DIEN_UDIEN                                              TMR_DIEN_UDIEN_Msk                                             /*!<Update DMA request enable            */
#define TMR_DIEN_CC1DEN_Pos                                         (9U)
#define TMR_DIEN_CC1DEN_Msk                                         (0x1UL << TMR_DIEN_CC1DEN_Pos)                                 /*!< 0x00000200 */
#define TMR_DIEN_CC1DEN                                             TMR_DIEN_CC1DEN_Msk                                            /*!<Capture/Compare 1 DMA request enable */
#define TMR_DIEN_CC2DEN_Pos                                         (10U)
#define TMR_DIEN_CC2DEN_Msk                                         (0x1UL << TMR_DIEN_CC2DEN_Pos)                                 /*!< 0x00000400 */
#define TMR_DIEN_CC2DEN                                             TMR_DIEN_CC2DEN_Msk                                            /*!<Capture/Compare 2 DMA request enable */
#define TMR_DIEN_CC3DEN_Pos                                         (11U)
#define TMR_DIEN_CC3DEN_Msk                                         (0x1UL << TMR_DIEN_CC3DEN_Pos)                                 /*!< 0x00000800 */
#define TMR_DIEN_CC3DEN                                             TMR_DIEN_CC3DEN_Msk                                            /*!<Capture/Compare 3 DMA request enable */
#define TMR_DIEN_CC4DEN_Pos                                         (12U)
#define TMR_DIEN_CC4DEN_Msk                                         (0x1UL << TMR_DIEN_CC4DEN_Pos)                                 /*!< 0x00001000 */
#define TMR_DIEN_CC4DEN                                             TMR_DIEN_CC4DEN_Msk                                            /*!<Capture/Compare 4 DMA request enable */
#define TMR_DIEN_COMDEN_Pos                                         (13U)
#define TMR_DIEN_COMDEN_Msk                                         (0x1UL << TMR_DIEN_COMDEN_Pos)                                 /*!< 0x00002000 */
#define TMR_DIEN_COMDEN                                             TMR_DIEN_COMDEN_Msk                                            /*!<COM DMA request enable               */
#define TMR_DIEN_TRGDEN_Pos                                         (14U)
#define TMR_DIEN_TRGDEN_Msk                                         (0x1UL << TMR_DIEN_TRGDEN_Pos)                                 /*!< 0x00004000 */
#define TMR_DIEN_TRGDEN                                             TMR_DIEN_TRGDEN_Msk                                            /*!<Trigger DMA request enable           */

/********************  Bit definition for TMR_STS register  ********************/
#define TMR_STS_UIFLG_Pos                                           (0U)
#define TMR_STS_UIFLG_Msk                                           (0x1UL << TMR_STS_UIFLG_Pos)                                   /*!< 0x00000001 */
#define TMR_STS_UIFLG                                               TMR_STS_UIFLG_Msk                                              /*!<Update interrupt Flag              */
#define TMR_STS_CC1IFLG_Pos                                         (1U)
#define TMR_STS_CC1IFLG_Msk                                         (0x1UL << TMR_STS_CC1IFLG_Pos)                                 /*!< 0x00000002 */
#define TMR_STS_CC1IFLG                                             TMR_STS_CC1IFLG_Msk                                            /*!<Capture/Compare 1 interrupt Flag   */
#define TMR_STS_CC2IFLG_Pos                                         (2U)
#define TMR_STS_CC2IFLG_Msk                                         (0x1UL << TMR_STS_CC2IFLG_Pos)                                 /*!< 0x00000004 */
#define TMR_STS_CC2IFLG                                             TMR_STS_CC2IFLG_Msk                                            /*!<Capture/Compare 2 interrupt Flag   */
#define TMR_STS_CC3IFLG_Pos                                         (3U)
#define TMR_STS_CC3IFLG_Msk                                         (0x1UL << TMR_STS_CC3IFLG_Pos)                                 /*!< 0x00000008 */
#define TMR_STS_CC3IFLG                                             TMR_STS_CC3IFLG_Msk                                            /*!<Capture/Compare 3 interrupt Flag   */
#define TMR_STS_CC4IFLG_Pos                                         (4U)
#define TMR_STS_CC4IFLG_Msk                                         (0x1UL << TMR_STS_CC4IFLG_Pos)                                 /*!< 0x00000010 */
#define TMR_STS_CC4IFLG                                             TMR_STS_CC4IFLG_Msk                                            /*!<Capture/Compare 4 interrupt Flag   */
#define TMR_STS_COMIFLG_Pos                                         (5U)
#define TMR_STS_COMIFLG_Msk                                         (0x1UL << TMR_STS_COMIFLG_Pos)                                 /*!< 0x00000020 */
#define TMR_STS_COMIFLG                                             TMR_STS_COMIFLG_Msk                                            /*!<COM interrupt Flag                 */
#define TMR_STS_TRGIFLG_Pos                                         (6U)
#define TMR_STS_TRGIFLG_Msk                                         (0x1UL << TMR_STS_TRGIFLG_Pos)                                 /*!< 0x00000040 */
#define TMR_STS_TRGIFLG                                             TMR_STS_TRGIFLG_Msk                                            /*!<Trigger interrupt Flag             */
#define TMR_STS_BRKIFLG_Pos                                         (7U)
#define TMR_STS_BRKIFLG_Msk                                         (0x1UL << TMR_STS_BRKIFLG_Pos)                                 /*!< 0x00000080 */
#define TMR_STS_BRKIFLG                                             TMR_STS_BRKIFLG_Msk                                            /*!<Break interrupt Flag               */
#define TMR_STS_CC1RCFLG_Pos                                        (9U)
#define TMR_STS_CC1RCFLG_Msk                                        (0x1UL << TMR_STS_CC1RCFLG_Pos)                                /*!< 0x00000200 */
#define TMR_STS_CC1RCFLG                                            TMR_STS_CC1RCFLG_Msk                                           /*!<Capture/Compare 1 Overcapture Flag */
#define TMR_STS_CC2RCFLG_Pos                                        (10U)
#define TMR_STS_CC2RCFLG_Msk                                        (0x1UL << TMR_STS_CC2RCFLG_Pos)                                /*!< 0x00000400 */
#define TMR_STS_CC2RCFLG                                            TMR_STS_CC2RCFLG_Msk                                           /*!<Capture/Compare 2 Overcapture Flag */
#define TMR_STS_CC3RCFLG_Pos                                        (11U)
#define TMR_STS_CC3RCFLG_Msk                                        (0x1UL << TMR_STS_CC3RCFLG_Pos)                                /*!< 0x00000800 */
#define TMR_STS_CC3RCFLG                                            TMR_STS_CC3RCFLG_Msk                                           /*!<Capture/Compare 3 Overcapture Flag */
#define TMR_STS_CC4RCFLG_Pos                                        (12U)
#define TMR_STS_CC4RCFLG_Msk                                        (0x1UL << TMR_STS_CC4RCFLG_Pos)                                /*!< 0x00001000 */
#define TMR_STS_CC4RCFLG                                            TMR_STS_CC4RCFLG_Msk                                           /*!<Capture/Compare 4 Overcapture Flag */

/*******************  Bit definition for TMR_CEG register  ********************/
#define TMR_CEG_UEG_Pos                                             (0U)
#define TMR_CEG_UEG_Msk                                             (0x1UL << TMR_CEG_UEG_Pos)                                     /*!< 0x00000001 */
#define TMR_CEG_UEG                                                 TMR_CEG_UEG_Msk                                                /*!<Update Generation                         */
#define TMR_CEG_CC1EG_Pos                                           (1U)
#define TMR_CEG_CC1EG_Msk                                           (0x1UL << TMR_CEG_CC1EG_Pos)                                   /*!< 0x00000002 */
#define TMR_CEG_CC1EG                                               TMR_CEG_CC1EG_Msk                                              /*!<Capture/Compare 1 Generation              */
#define TMR_CEG_CC2EG_Pos                                           (2U)
#define TMR_CEG_CC2EG_Msk                                           (0x1UL << TMR_CEG_CC2EG_Pos)                                   /*!< 0x00000004 */
#define TMR_CEG_CC2EG                                               TMR_CEG_CC2EG_Msk                                              /*!<Capture/Compare 2 Generation              */
#define TMR_CEG_CC3EG_Pos                                           (3U)
#define TMR_CEG_CC3EG_Msk                                           (0x1UL << TMR_CEG_CC3EG_Pos)                                   /*!< 0x00000008 */
#define TMR_CEG_CC3EG                                               TMR_CEG_CC3EG_Msk                                              /*!<Capture/Compare 3 Generation              */
#define TMR_CEG_CC4EG_Pos                                           (4U)
#define TMR_CEG_CC4EG_Msk                                           (0x1UL << TMR_CEG_CC4EG_Pos)                                   /*!< 0x00000010 */
#define TMR_CEG_CC4EG                                               TMR_CEG_CC4EG_Msk                                              /*!<Capture/Compare 4 Generation              */
#define TMR_CEG_COMG_Pos                                            (5U)
#define TMR_CEG_COMG_Msk                                            (0x1UL << TMR_CEG_COMG_Pos)                                    /*!< 0x00000020 */
#define TMR_CEG_COMG                                                TMR_CEG_COMG_Msk                                               /*!<Capture/Compare Control Update Generation */
#define TMR_CEG_TEG_Pos                                             (6U)
#define TMR_CEG_TEG_Msk                                             (0x1UL << TMR_CEG_TEG_Pos)                                     /*!< 0x00000040 */
#define TMR_CEG_TEG                                                 TMR_CEG_TEG_Msk                                                /*!<Trigger Generation                        */
#define TMR_CEG_BEG_Pos                                             (7U)
#define TMR_CEG_BEG_Msk                                             (0x1UL << TMR_CEG_BEG_Pos)                                     /*!< 0x00000080 */
#define TMR_CEG_BEG                                                 TMR_CEG_BEG_Msk                                                /*!<Break Generation                          */

/******************  Bit definition for TMR_CCM1 register  *******************/
#define TMR_CCM1_CC1SEL_Pos                                         (0U)
#define TMR_CCM1_CC1SEL_Msk                                         (0x3UL << TMR_CCM1_CC1SEL_Pos)                                 /*!< 0x00000003 */
#define TMR_CCM1_CC1SEL                                             TMR_CCM1_CC1SEL_Msk                                            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
#define TMR_CCM1_CC1SEL_0                                           (0x1UL << TMR_CCM1_CC1SEL_Pos)                                 /*!< 0x0001 */
#define TMR_CCM1_CC1SEL_1                                           (0x2UL << TMR_CCM1_CC1SEL_Pos)                                 /*!< 0x0002 */

#define TMR_CCM1_OC1FEN_Pos                                         (2U)
#define TMR_CCM1_OC1FEN_Msk                                         (0x1UL << TMR_CCM1_OC1FEN_Pos)                                 /*!< 0x00000004 */
#define TMR_CCM1_OC1FEN                                             TMR_CCM1_OC1FEN_Msk                                            /*!<Output Compare 1 Fast enable                 */
#define TMR_CCM1_OC1PEN_Pos                                         (3U)
#define TMR_CCM1_OC1PEN_Msk                                         (0x1UL << TMR_CCM1_OC1PEN_Pos)                                 /*!< 0x00000008 */
#define TMR_CCM1_OC1PEN                                             TMR_CCM1_OC1PEN_Msk                                            /*!<Output Compare 1 Preload enable              */

#define TMR_CCM1_OC1MOD_Pos                                         (4U)
#define TMR_CCM1_OC1MOD_Msk                                         (0x7UL << TMR_CCM1_OC1MOD_Pos)                                 /*!< 0x00000070 */
#define TMR_CCM1_OC1MOD                                             TMR_CCM1_OC1MOD_Msk                                            /*!<OC1M[2:0] bits (Output Compare 1 Mode)       */
#define TMR_CCM1_OC1MOD_0                                           (0x1UL << TMR_CCM1_OC1MOD_Pos)                                 /*!< 0x0010 */
#define TMR_CCM1_OC1MOD_1                                           (0x2UL << TMR_CCM1_OC1MOD_Pos)                                 /*!< 0x0020 */
#define TMR_CCM1_OC1MOD_2                                           (0x4UL << TMR_CCM1_OC1MOD_Pos)                                 /*!< 0x0040 */

#define TMR_CCM1_OC1CEN_Pos                                         (7U)
#define TMR_CCM1_OC1CEN_Msk                                         (0x1UL << TMR_CCM1_OC1CEN_Pos)                                 /*!< 0x00000080 */
#define TMR_CCM1_OC1CEN                                             TMR_CCM1_OC1CEN_Msk                                            /*!<Output Compare 1Clear Enable                 */

#define TMR_CCM1_CC2SEL_Pos                                         (8U)
#define TMR_CCM1_CC2SEL_Msk                                         (0x3UL << TMR_CCM1_CC2SEL_Pos)                                 /*!< 0x00000300 */
#define TMR_CCM1_CC2SEL                                             TMR_CCM1_CC2SEL_Msk                                            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
#define TMR_CCM1_CC2SEL_0                                           (0x1UL << TMR_CCM1_CC2SEL_Pos)                                 /*!< 0x0100 */
#define TMR_CCM1_CC2SEL_1                                           (0x2UL << TMR_CCM1_CC2SEL_Pos)                                 /*!< 0x0200 */

#define TMR_CCM1_OC2FEN_Pos                                         (10U)
#define TMR_CCM1_OC2FEN_Msk                                         (0x1UL << TMR_CCM1_OC2FEN_Pos)                                 /*!< 0x00000400 */
#define TMR_CCM1_OC2FEN                                             TMR_CCM1_OC2FEN_Msk                                            /*!<Output Compare 2 Fast enable                 */
#define TMR_CCM1_OC2PEN_Pos                                         (11U)
#define TMR_CCM1_OC2PEN_Msk                                         (0x1UL << TMR_CCM1_OC2PEN_Pos)                                 /*!< 0x00000800 */
#define TMR_CCM1_OC2PEN                                             TMR_CCM1_OC2PEN_Msk                                            /*!<Output Compare 2 Preload enable              */

#define TMR_CCM1_OC2MOD_Pos                                         (12U)
#define TMR_CCM1_OC2MOD_Msk                                         (0x7UL << TMR_CCM1_OC2MOD_Pos)                                 /*!< 0x00007000 */
#define TMR_CCM1_OC2MOD                                             TMR_CCM1_OC2MOD_Msk                                            /*!<OC2M[2:0] bits (Output Compare 2 Mode)       */
#define TMR_CCM1_OC2MOD_0                                           (0x1UL << TMR_CCM1_OC2MOD_Pos)                                 /*!< 0x1000 */
#define TMR_CCM1_OC2MOD_1                                           (0x2UL << TMR_CCM1_OC2MOD_Pos)                                 /*!< 0x2000 */
#define TMR_CCM1_OC2MOD_2                                           (0x4UL << TMR_CCM1_OC2MOD_Pos)                                 /*!< 0x4000 */

#define TMR_CCM1_OC2CEN_Pos                                         (15U)
#define TMR_CCM1_OC2CEN_Msk                                         (0x1UL << TMR_CCM1_OC2CEN_Pos)                                 /*!< 0x00008000 */
#define TMR_CCM1_OC2CEN                                             TMR_CCM1_OC2CEN_Msk                                            /*!<Output Compare 2 Clear Enable */

/*----------------------------------------------------------------------------*/

#define TMR_CCM1_IC1PSC_Pos                                         (2U)
#define TMR_CCM1_IC1PSC_Msk                                         (0x3UL << TMR_CCM1_IC1PSC_Pos)                                 /*!< 0x0000000C */
#define TMR_CCM1_IC1PSC                                             TMR_CCM1_IC1PSC_Msk                                            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
#define TMR_CCM1_IC1PSC_0                                           (0x1UL << TMR_CCM1_IC1PSC_Pos)                                 /*!< 0x0004 */
#define TMR_CCM1_IC1PSC_1                                           (0x2UL << TMR_CCM1_IC1PSC_Pos)                                 /*!< 0x0008 */

#define TMR_CCM1_IC1F_Pos                                           (4U)
#define TMR_CCM1_IC1F_Msk                                           (0xFUL << TMR_CCM1_IC1F_Pos)                                   /*!< 0x000000F0 */
#define TMR_CCM1_IC1F                                               TMR_CCM1_IC1F_Msk                                              /*!<IC1F[3:0] bits (Input Capture 1 Filter)      */
#define TMR_CCM1_IC1F_0                                             (0x1UL << TMR_CCM1_IC1F_Pos)                                   /*!< 0x0010 */
#define TMR_CCM1_IC1F_1                                             (0x2UL << TMR_CCM1_IC1F_Pos)                                   /*!< 0x0020 */
#define TMR_CCM1_IC1F_2                                             (0x4UL << TMR_CCM1_IC1F_Pos)                                   /*!< 0x0040 */
#define TMR_CCM1_IC1F_3                                             (0x8UL << TMR_CCM1_IC1F_Pos)                                   /*!< 0x0080 */

#define TMR_CCM1_IC2PSC_Pos                                         (10U)
#define TMR_CCM1_IC2PSC_Msk                                         (0x3UL << TMR_CCM1_IC2PSC_Pos)                                 /*!< 0x00000C00 */
#define TMR_CCM1_IC2PSC                                             TMR_CCM1_IC2PSC_Msk                                            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler)  */
#define TMR_CCM1_IC2PSC_0                                           (0x1UL << TMR_CCM1_IC2PSC_Pos)                                 /*!< 0x0400 */
#define TMR_CCM1_IC2PSC_1                                           (0x2UL << TMR_CCM1_IC2PSC_Pos)                                 /*!< 0x0800 */

#define TMR_CCM1_IC2F_Pos                                           (12U)
#define TMR_CCM1_IC2F_Msk                                           (0xFUL << TMR_CCM1_IC2F_Pos)                                   /*!< 0x0000F000 */
#define TMR_CCM1_IC2F                                               TMR_CCM1_IC2F_Msk                                              /*!<IC2F[3:0] bits (Input Capture 2 Filter)       */
#define TMR_CCM1_IC2F_0                                             (0x1UL << TMR_CCM1_IC2F_Pos)                                   /*!< 0x1000 */
#define TMR_CCM1_IC2F_1                                             (0x2UL << TMR_CCM1_IC2F_Pos)                                   /*!< 0x2000 */
#define TMR_CCM1_IC2F_2                                             (0x4UL << TMR_CCM1_IC2F_Pos)                                   /*!< 0x4000 */
#define TMR_CCM1_IC2F_3                                             (0x8UL << TMR_CCM1_IC2F_Pos)                                   /*!< 0x8000 */

/******************  Bit definition for TMR_CCM2 register  *******************/
#define TMR_CCM2_CC3SEL_Pos                                         (0U)
#define TMR_CCM2_CC3SEL_Msk                                         (0x3UL << TMR_CCM2_CC3SEL_Pos)                                 /*!< 0x00000003 */
#define TMR_CCM2_CC3SEL                                             TMR_CCM2_CC3SEL_Msk                                            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection)  */
#define TMR_CCM2_CC3SEL_0                                           (0x1UL << TMR_CCM2_CC3SEL_Pos)                                 /*!< 0x0001 */
#define TMR_CCM2_CC3SEL_1                                           (0x2UL << TMR_CCM2_CC3SEL_Pos)                                 /*!< 0x0002 */

#define TMR_CCM2_OC3FEN_Pos                                         (2U)
#define TMR_CCM2_OC3FEN_Msk                                         (0x1UL << TMR_CCM2_OC3FEN_Pos)                                 /*!< 0x00000004 */
#define TMR_CCM2_OC3FEN                                             TMR_CCM2_OC3FEN_Msk                                            /*!<Output Compare 3 Fast enable           */
#define TMR_CCM2_OC3PEN_Pos                                         (3U)
#define TMR_CCM2_OC3PEN_Msk                                         (0x1UL << TMR_CCM2_OC3PEN_Pos)                                 /*!< 0x00000008 */
#define TMR_CCM2_OC3PEN                                             TMR_CCM2_OC3PEN_Msk                                            /*!<Output Compare 3 Preload enable        */

#define TMR_CCM2_OC3MOD_Pos                                         (4U)
#define TMR_CCM2_OC3MOD_Msk                                         (0x7UL << TMR_CCM2_OC3MOD_Pos)                                 /*!< 0x00000070 */
#define TMR_CCM2_OC3MOD                                             TMR_CCM2_OC3MOD_Msk                                            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
#define TMR_CCM2_OC3MOD_0                                           (0x1UL << TMR_CCM2_OC3MOD_Pos)                                 /*!< 0x0010 */
#define TMR_CCM2_OC3MOD_1                                           (0x2UL << TMR_CCM2_OC3MOD_Pos)                                 /*!< 0x0020 */
#define TMR_CCM2_OC3MOD_2                                           (0x4UL << TMR_CCM2_OC3MOD_Pos)                                 /*!< 0x0040 */

#define TMR_CCM2_OC3CEN_Pos                                         (7U)
#define TMR_CCM2_OC3CEN_Msk                                         (0x1UL << TMR_CCM2_OC3CEN_Pos)                                 /*!< 0x00000080 */
#define TMR_CCM2_OC3CEN                                             TMR_CCM2_OC3CEN_Msk                                            /*!<Output Compare 3 Clear Enable */

#define TMR_CCM2_CC4SEL_Pos                                         (8U)
#define TMR_CCM2_CC4SEL_Msk                                         (0x3UL << TMR_CCM2_CC4SEL_Pos)                                 /*!< 0x00000300 */
#define TMR_CCM2_CC4SEL                                             TMR_CCM2_CC4SEL_Msk                                            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
#define TMR_CCM2_CC4SEL_0                                           (0x1UL << TMR_CCM2_CC4SEL_Pos)                                 /*!< 0x0100 */
#define TMR_CCM2_CC4SEL_1                                           (0x2UL << TMR_CCM2_CC4SEL_Pos)                                 /*!< 0x0200 */

#define TMR_CCM2_OC4FEN_Pos                                         (10U)
#define TMR_CCM2_OC4FEN_Msk                                         (0x1UL << TMR_CCM2_OC4FEN_Pos)                                 /*!< 0x00000400 */
#define TMR_CCM2_OC4FEN                                             TMR_CCM2_OC4FEN_Msk                                            /*!<Output Compare 4 Fast enable    */
#define TMR_CCM2_OC4PEN_Pos                                         (11U)
#define TMR_CCM2_OC4PEN_Msk                                         (0x1UL << TMR_CCM2_OC4PEN_Pos)                                 /*!< 0x00000800 */
#define TMR_CCM2_OC4PEN                                             TMR_CCM2_OC4PEN_Msk                                            /*!<Output Compare 4 Preload enable */

#define TMR_CCM2_OC4MOD_Pos                                         (12U)
#define TMR_CCM2_OC4MOD_Msk                                         (0x7UL << TMR_CCM2_OC4MOD_Pos)                                 /*!< 0x00007000 */
#define TMR_CCM2_OC4MOD                                             TMR_CCM2_OC4MOD_Msk                                            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
#define TMR_CCM2_OC4MOD_0                                           (0x1UL << TMR_CCM2_OC4MOD_Pos)                                 /*!< 0x1000 */
#define TMR_CCM2_OC4MOD_1                                           (0x2UL << TMR_CCM2_OC4MOD_Pos)                                 /*!< 0x2000 */
#define TMR_CCM2_OC4MOD_2                                           (0x4UL << TMR_CCM2_OC4MOD_Pos)                                 /*!< 0x4000 */

#define TMR_CCM2_OC4CEN_Pos                                         (15U)
#define TMR_CCM2_OC4CEN_Msk                                         (0x1UL << TMR_CCM2_OC4CEN_Pos)                                 /*!< 0x00008000 */
#define TMR_CCM2_OC4CEN                                             TMR_CCM2_OC4CEN_Msk                                            /*!<Output Compare 4 Clear Enable */

/*----------------------------------------------------------------------------*/

#define TMR_CCM2_IC3PSC_Pos                                         (2U)
#define TMR_CCM2_IC3PSC_Msk                                         (0x3UL << TMR_CCM2_IC3PSC_Pos)                                 /*!< 0x0000000C */
#define TMR_CCM2_IC3PSC                                             TMR_CCM2_IC3PSC_Msk                                            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
#define TMR_CCM2_IC3PSC_0                                           (0x1UL << TMR_CCM2_IC3PSC_Pos)                                 /*!< 0x0004 */
#define TMR_CCM2_IC3PSC_1                                           (0x2UL << TMR_CCM2_IC3PSC_Pos)                                 /*!< 0x0008 */

#define TMR_CCM2_IC3F_Pos                                           (4U)
#define TMR_CCM2_IC3F_Msk                                           (0xFUL << TMR_CCM2_IC3F_Pos)                                   /*!< 0x000000F0 */
#define TMR_CCM2_IC3F                                               TMR_CCM2_IC3F_Msk                                              /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
#define TMR_CCM2_IC3F_0                                             (0x1UL << TMR_CCM2_IC3F_Pos)                                   /*!< 0x0010 */
#define TMR_CCM2_IC3F_1                                             (0x2UL << TMR_CCM2_IC3F_Pos)                                   /*!< 0x0020 */
#define TMR_CCM2_IC3F_2                                             (0x4UL << TMR_CCM2_IC3F_Pos)                                   /*!< 0x0040 */
#define TMR_CCM2_IC3F_3                                             (0x8UL << TMR_CCM2_IC3F_Pos)                                   /*!< 0x0080 */

#define TMR_CCM2_IC4PSC_Pos                                         (10U)
#define TMR_CCM2_IC4PSC_Msk                                         (0x3UL << TMR_CCM2_IC4PSC_Pos)                                 /*!< 0x00000C00 */
#define TMR_CCM2_IC4PSC                                             TMR_CCM2_IC4PSC_Msk                                            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
#define TMR_CCM2_IC4PSC_0                                           (0x1UL << TMR_CCM2_IC4PSC_Pos)                                 /*!< 0x0400 */
#define TMR_CCM2_IC4PSC_1                                           (0x2UL << TMR_CCM2_IC4PSC_Pos)                                 /*!< 0x0800 */

#define TMR_CCM2_IC4F_Pos                                           (12U)
#define TMR_CCM2_IC4F_Msk                                           (0xFUL << TMR_CCM2_IC4F_Pos)                                   /*!< 0x0000F000 */
#define TMR_CCM2_IC4F                                               TMR_CCM2_IC4F_Msk                                              /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
#define TMR_CCM2_IC4F_0                                             (0x1UL << TMR_CCM2_IC4F_Pos)                                   /*!< 0x1000 */
#define TMR_CCM2_IC4F_1                                             (0x2UL << TMR_CCM2_IC4F_Pos)                                   /*!< 0x2000 */
#define TMR_CCM2_IC4F_2                                             (0x4UL << TMR_CCM2_IC4F_Pos)                                   /*!< 0x4000 */
#define TMR_CCM2_IC4F_3                                             (0x8UL << TMR_CCM2_IC4F_Pos)                                   /*!< 0x8000 */

/*******************  Bit definition for TMR_CCEN register  *******************/
#define TMR_CCEN_CC1EN_Pos                                          (0U)
#define TMR_CCEN_CC1EN_Msk                                          (0x1UL << TMR_CCEN_CC1EN_Pos)                                  /*!< 0x00000001 */
#define TMR_CCEN_CC1EN                                              TMR_CCEN_CC1EN_Msk                                             /*!<Capture/Compare 1 output enable                 */
#define TMR_CCEN_CC1POL_Pos                                         (1U)
#define TMR_CCEN_CC1POL_Msk                                         (0x1UL << TMR_CCEN_CC1POL_Pos)                                 /*!< 0x00000002 */
#define TMR_CCEN_CC1POL                                             TMR_CCEN_CC1POL_Msk                                            /*!<Capture/Compare 1 output Polarity               */
#define TMR_CCEN_CC1NEN_Pos                                         (2U)
#define TMR_CCEN_CC1NEN_Msk                                         (0x1UL << TMR_CCEN_CC1NEN_Pos)                                 /*!< 0x00000004 */
#define TMR_CCEN_CC1NEN                                             TMR_CCEN_CC1NEN_Msk                                            /*!<Capture/Compare 1 Complementary output enable   */
#define TMR_CCEN_CC1NPOL_Pos                                        (3U)
#define TMR_CCEN_CC1NPOL_Msk                                        (0x1UL << TMR_CCEN_CC1NPOL_Pos)                                /*!< 0x00000008 */
#define TMR_CCEN_CC1NPOL                                            TMR_CCEN_CC1NPOL_Msk                                           /*!<Capture/Compare 1 Complementary output Polarity */
#define TMR_CCEN_CC2EN_Pos                                          (4U)
#define TMR_CCEN_CC2EN_Msk                                          (0x1UL << TMR_CCEN_CC2EN_Pos)                                  /*!< 0x00000010 */
#define TMR_CCEN_CC2EN                                              TMR_CCEN_CC2EN_Msk                                             /*!<Capture/Compare 2 output enable                 */
#define TMR_CCEN_CC2POL_Pos                                         (5U)
#define TMR_CCEN_CC2POL_Msk                                         (0x1UL << TMR_CCEN_CC2POL_Pos)                                 /*!< 0x00000020 */
#define TMR_CCEN_CC2POL                                             TMR_CCEN_CC2POL_Msk                                            /*!<Capture/Compare 2 output Polarity               */
#define TMR_CCEN_CC2NEN_Pos                                         (6U)
#define TMR_CCEN_CC2NEN_Msk                                         (0x1UL << TMR_CCEN_CC2NEN_Pos)                                 /*!< 0x00000040 */
#define TMR_CCEN_CC2NEN                                             TMR_CCEN_CC2NEN_Msk                                            /*!<Capture/Compare 2 Complementary output enable   */
#define TMR_CCEN_CC2NPOL_Pos                                        (7U)
#define TMR_CCEN_CC2NPOL_Msk                                        (0x1UL << TMR_CCEN_CC2NPOL_Pos)                                /*!< 0x00000080 */
#define TMR_CCEN_CC2NPOL                                            TMR_CCEN_CC2NPOL_Msk                                           /*!<Capture/Compare 2 Complementary output Polarity */
#define TMR_CCEN_CC3EN_Pos                                          (8U)
#define TMR_CCEN_CC3EN_Msk                                          (0x1UL << TMR_CCEN_CC3EN_Pos)                                  /*!< 0x00000100 */
#define TMR_CCEN_CC3EN                                              TMR_CCEN_CC3EN_Msk                                             /*!<Capture/Compare 3 output enable                 */
#define TMR_CCEN_CC3POL_Pos                                         (9U)
#define TMR_CCEN_CC3POL_Msk                                         (0x1UL << TMR_CCEN_CC3POL_Pos)                                 /*!< 0x00000200 */
#define TMR_CCEN_CC3POL                                             TMR_CCEN_CC3POL_Msk                                            /*!<Capture/Compare 3 output Polarity               */
#define TMR_CCEN_CC3NEN_Pos                                         (10U)
#define TMR_CCEN_CC3NEN_Msk                                         (0x1UL << TMR_CCEN_CC3NEN_Pos)                                 /*!< 0x00000400 */
#define TMR_CCEN_CC3NEN                                             TMR_CCEN_CC3NEN_Msk                                            /*!<Capture/Compare 3 Complementary output enable   */
#define TMR_CCEN_CC3NPOL_Pos                                        (11U)
#define TMR_CCEN_CC3NPOL_Msk                                        (0x1UL << TMR_CCEN_CC3NPOL_Pos)                                /*!< 0x00000800 */
#define TMR_CCEN_CC3NPOL                                            TMR_CCEN_CC3NPOL_Msk                                           /*!<Capture/Compare 3 Complementary output Polarity */
#define TMR_CCEN_CC4EN_Pos                                          (12U)
#define TMR_CCEN_CC4EN_Msk                                          (0x1UL << TMR_CCEN_CC4EN_Pos)                                  /*!< 0x00001000 */
#define TMR_CCEN_CC4EN                                              TMR_CCEN_CC4EN_Msk                                             /*!<Capture/Compare 4 output enable                 */
#define TMR_CCEN_CC4POL_Pos                                         (13U)
#define TMR_CCEN_CC4POL_Msk                                         (0x1UL << TMR_CCEN_CC4POL_Pos)                                 /*!< 0x00002000 */
#define TMR_CCEN_CC4POL                                             TMR_CCEN_CC4POL_Msk                                            /*!<Capture/Compare 4 output Polarity               */
#define TMR_CCEN_CC4NPOL_Pos                                        (15U)
#define TMR_CCEN_CC4NPOL_Msk                                        (0x1UL << TMR_CCEN_CC4NPOL_Pos)                                /*!< 0x00008000 */
#define TMR_CCEN_CC4NPOL                                            TMR_CCEN_CC4NPOL_Msk                                           /*!<Capture/Compare 4 Complementary output Polarity */

/*******************  Bit definition for TMR_CNT register  ********************/
#define TMR_CNT_CNT_Pos                                             (0U)
#define TMR_CNT_CNT_Msk                                             (0xFFFFFFFFUL << TMR_CNT_CNT_Pos)                              /*!< 0xFFFFFFFF */
#define TMR_CNT_CNT                                                 TMR_CNT_CNT_Msk                                                /*!<Counter Value            */

/*******************  Bit definition for TMR_PSC register  ********************/
#define TMR_PSC_PSC_Pos                                             (0U)
#define TMR_PSC_PSC_Msk                                             (0xFFFFUL << TMR_PSC_PSC_Pos)                                  /*!< 0x0000FFFF */
#define TMR_PSC_PSC                                                 TMR_PSC_PSC_Msk                                                /*!<Prescaler Value          */

/*******************  Bit definition for TMR_AUTORLD register  ********************/
#define TMR_AUTORLD_AUTORLD_Pos                                     (0U)
#define TMR_AUTORLD_AUTORLD_Msk                                     (0xFFFFFFFFUL << TMR_AUTORLD_AUTORLD_Pos)                      /*!< 0xFFFFFFFF */
#define TMR_AUTORLD_AUTORLD                                         TMR_AUTORLD_AUTORLD_Msk                                        /*!<actual auto-reload Value */

/*******************  Bit definition for TMR_REPCNT register  ********************/
#define TMR_REPCNT_REPCNT_Pos                                       (0U)
#define TMR_REPCNT_REPCNT_Msk                                       (0xFFUL << TMR_REPCNT_REPCNT_Pos)                              /*!< 0x000000FF */
#define TMR_REPCNT_REPCNT                                           TMR_REPCNT_REPCNT_Msk                                          /*!<Repetition Counter Value */

/*******************  Bit definition for TMR_CC1 register  *******************/
#define TMR_CC1_CC1_Pos                                             (0U)
#define TMR_CC1_CC1_Msk                                             (0xFFFFUL << TMR_CC1_CC1_Pos)                                  /*!< 0x0000FFFF */
#define TMR_CC1_CC1                                                 TMR_CC1_CC1_Msk                                                /*!<Capture/Compare 1 Value  */

/*******************  Bit definition for TMR_CC2 register  *******************/
#define TMR_CC2_CC2_Pos                                             (0U)
#define TMR_CC2_CC2_Msk                                             (0xFFFFUL << TMR_CC2_CC2_Pos)                                  /*!< 0x0000FFFF */
#define TMR_CC2_CC2                                                 TMR_CC2_CC2_Msk                                                /*!<Capture/Compare 2 Value  */

/*******************  Bit definition for TMR_CC3 register  *******************/
#define TMR_CC3_CC3_Pos                                             (0U)
#define TMR_CC3_CC3_Msk                                             (0xFFFFUL << TMR_CC3_CC3_Pos)                                  /*!< 0x0000FFFF */
#define TMR_CC3_CC3                                                 TMR_CC3_CC3_Msk                                                /*!<Capture/Compare 3 Value  */

/*******************  Bit definition for TMR_CC4 register  *******************/
#define TMR_CC4_CC4_Pos                                             (0U)
#define TMR_CC4_CC4_Msk                                             (0xFFFFUL << TMR_CC4_CC4_Pos)                                  /*!< 0x0000FFFF */
#define TMR_CC4_CC4                                                 TMR_CC4_CC4_Msk                                                /*!<Capture/Compare 4 Value  */

/*******************  Bit definition for TMR_BDT register  *******************/
#define TMR_BDT_DTS_Pos                                             (0U)
#define TMR_BDT_DTS_Msk                                             (0xFFUL << TMR_BDT_DTS_Pos)                                    /*!< 0x000000FF */
#define TMR_BDT_DTS                                                 TMR_BDT_DTS_Msk                                                /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
#define TMR_BDT_DTS_0                                               (0x01UL << TMR_BDT_DTS_Pos)                                    /*!< 0x0001 */
#define TMR_BDT_DTS_1                                               (0x02UL << TMR_BDT_DTS_Pos)                                    /*!< 0x0002 */
#define TMR_BDT_DTS_2                                               (0x04UL << TMR_BDT_DTS_Pos)                                    /*!< 0x0004 */
#define TMR_BDT_DTS_3                                               (0x08UL << TMR_BDT_DTS_Pos)                                    /*!< 0x0008 */
#define TMR_BDT_DTS_4                                               (0x10UL << TMR_BDT_DTS_Pos)                                    /*!< 0x0010 */
#define TMR_BDT_DTS_5                                               (0x20UL << TMR_BDT_DTS_Pos)                                    /*!< 0x0020 */
#define TMR_BDT_DTS_6                                               (0x40UL << TMR_BDT_DTS_Pos)                                    /*!< 0x0040 */
#define TMR_BDT_DTS_7                                               (0x80UL << TMR_BDT_DTS_Pos)                                    /*!< 0x0080 */

#define TMR_BDT_LOCKCFG_Pos                                         (8U)
#define TMR_BDT_LOCKCFG_Msk                                         (0x3UL << TMR_BDT_LOCKCFG_Pos)                                 /*!< 0x00000300 */
#define TMR_BDT_LOCKCFG                                             TMR_BDT_LOCKCFG_Msk                                            /*!<LOCK[1:0] bits (Lock Configuration) */
#define TMR_BDT_LOCKCFG_0                                           (0x1UL << TMR_BDT_LOCKCFG_Pos)                                 /*!< 0x0100 */
#define TMR_BDT_LOCKCFG_1                                           (0x2UL << TMR_BDT_LOCKCFG_Pos)                                 /*!< 0x0200 */

#define TMR_BDT_IMOS_Pos                                            (10U)
#define TMR_BDT_IMOS_Msk                                            (0x1UL << TMR_BDT_IMOS_Pos)                                    /*!< 0x00000400 */
#define TMR_BDT_IMOS                                                TMR_BDT_IMOS_Msk                                               /*!<Off-State Selection for Idle mode */
#define TMR_BDT_RMOS_Pos                                            (11U)
#define TMR_BDT_RMOS_Msk                                            (0x1UL << TMR_BDT_RMOS_Pos)                                    /*!< 0x00000800 */
#define TMR_BDT_RMOS                                                TMR_BDT_RMOS_Msk                                               /*!<Off-State Selection for Run mode  */
#define TMR_BDT_BRKEN_Pos                                           (12U)
#define TMR_BDT_BRKEN_Msk                                           (0x1UL << TMR_BDT_BRKEN_Pos)                                   /*!< 0x00001000 */
#define TMR_BDT_BRKEN                                               TMR_BDT_BRKEN_Msk                                              /*!<Break enable                      */
#define TMR_BDT_BRKPOL_Pos                                          (13U)
#define TMR_BDT_BRKPOL_Msk                                          (0x1UL << TMR_BDT_BRKPOL_Pos)                                  /*!< 0x00002000 */
#define TMR_BDT_BRKPOL                                              TMR_BDT_BRKPOL_Msk                                             /*!<Break Polarity                    */
#define TMR_BDT_AOEN_Pos                                            (14U)
#define TMR_BDT_AOEN_Msk                                            (0x1UL << TMR_BDT_AOEN_Pos)                                    /*!< 0x00004000 */
#define TMR_BDT_AOEN                                                TMR_BDT_AOEN_Msk                                               /*!<Automatic Output enable           */
#define TMR_BDT_MOEN_Pos                                            (15U)
#define TMR_BDT_MOEN_Msk                                            (0x1UL << TMR_BDT_MOEN_Pos)                                    /*!< 0x00008000 */
#define TMR_BDT_MOEN                                                TMR_BDT_MOEN_Msk                                               /*!<Main Output enable                */

/*******************  Bit definition for TMR_DCTRL register  ********************/
#define TMR_DCTRL_DBADDR_Pos                                        (0U)
#define TMR_DCTRL_DBADDR_Msk                                        (0x1FUL << TMR_DCTRL_DBADDR_Pos)                               /*!< 0x0000001F */
#define TMR_DCTRL_DBADDR                                            TMR_DCTRL_DBADDR_Msk                                           /*!<DBA[4:0] bits (DMA Base Address) */
#define TMR_DCTRL_DBADDR_0                                          (0x01UL << TMR_DCTRL_DBADDR_Pos)                               /*!< 0x0001 */
#define TMR_DCTRL_DBADDR_1                                          (0x02UL << TMR_DCTRL_DBADDR_Pos)                               /*!< 0x0002 */
#define TMR_DCTRL_DBADDR_2                                          (0x04UL << TMR_DCTRL_DBADDR_Pos)                               /*!< 0x0004 */
#define TMR_DCTRL_DBADDR_3                                          (0x08UL << TMR_DCTRL_DBADDR_Pos)                               /*!< 0x0008 */
#define TMR_DCTRL_DBADDR_4                                          (0x10UL << TMR_DCTRL_DBADDR_Pos)                               /*!< 0x0010 */

#define TMR_DCTRL_DBLEN_Pos                                         (8U)
#define TMR_DCTRL_DBLEN_Msk                                         (0x1FUL << TMR_DCTRL_DBLEN_Pos)                                /*!< 0x00001F00 */
#define TMR_DCTRL_DBLEN                                             TMR_DCTRL_DBLEN_Msk                                            /*!<DBL[4:0] bits (DMA Burst Length) */
#define TMR_DCTRL_DBLEN_0                                           (0x01UL << TMR_DCTRL_DBLEN_Pos)                                /*!< 0x0100 */
#define TMR_DCTRL_DBLEN_1                                           (0x02UL << TMR_DCTRL_DBLEN_Pos)                                /*!< 0x0200 */
#define TMR_DCTRL_DBLEN_2                                           (0x04UL << TMR_DCTRL_DBLEN_Pos)                                /*!< 0x0400 */
#define TMR_DCTRL_DBLEN_3                                           (0x08UL << TMR_DCTRL_DBLEN_Pos)                                /*!< 0x0800 */
#define TMR_DCTRL_DBLEN_4                                           (0x10UL << TMR_DCTRL_DBLEN_Pos)                                /*!< 0x1000 */

/*******************  Bit definition for TMR_DMADDR register  *******************/
#define TMR_DMADDR_DMADDR_Pos                                       (0U)
#define TMR_DMADDR_DMADDR_Msk                                       (0xFFFFUL << TMR_DMADDR_DMADDR_Pos)                            /*!< 0x0000FFFF */
#define TMR_DMADDR_DMADDR                                           TMR_DMADDR_DMADDR_Msk                                          /*!<DMA register for burst accesses                    */

/*******************  Bit definition for TMR_OR register  *********************/
#define TMR_OR_TI1_RMPSEL_Pos                                       (0U)
#define TMR_OR_TI1_RMPSEL_Msk                                       (0x3UL << TMR_OR_TI1_RMPSEL_Pos)                               /*!< 0x00000003 */
#define TMR_OR_TI1_RMPSEL                                           TMR_OR_TI1_RMPSEL_Msk                                          /*!< TI1_RMP[1:0] bits (TMR11 Input Capture 1 remap) */
#define TMR_OR_TI1_RMPSEL_0                                         (0x1UL << TMR_OR_TI1_RMPSEL_Pos)                               /*!< 0x00000001 */
#define TMR_OR_TI1_RMPSEL_1                                         (0x2UL << TMR_OR_TI1_RMPSEL_Pos)                               /*!< 0x00000002 */

#define TMR_OR_TI4_RMPSEL_Pos                                       (6U)
#define TMR_OR_TI4_RMPSEL_Msk                                       (0x3UL << TMR_OR_TI4_RMPSEL_Pos)                               /*!< 0x000000C0 */
#define TMR_OR_TI4_RMPSEL                                           TMR_OR_TI4_RMPSEL_Msk                                          /*!<TI4_RMP[1:0] bits (TMR5 Input 4 remap)             */
#define TMR_OR_TI4_RMPSEL_0                                         (0x1UL << TMR_OR_TI4_RMPSEL_Pos)                               /*!< 0x0040 */
#define TMR_OR_TI4_RMPSEL_1                                         (0x2UL << TMR_OR_TI4_RMPSEL_Pos)                               /*!< 0x0080 */
#define TMR_OR_RMPSEL_Pos                                           (10U)
#define TMR_OR_RMPSEL_Msk                                           (0x3UL << TMR_OR_RMPSEL_Pos)                                   /*!< 0x00000C00 */
#define TMR_OR_RMPSEL                                               TMR_OR_RMPSEL_Msk                                              /*!<ITR1_RMP[1:0] bits (TMR2 Internal trigger 1 remap) */
#define TMR_OR_RMPSEL_0                                             (0x1UL << TMR_OR_RMPSEL_Pos)                                   /*!< 0x0400 */
#define TMR_OR_RMPSEL_1                                             (0x2UL << TMR_OR_RMPSEL_Pos)                                   /*!< 0x0800 */


/******************************************************************************/
/*                                                                            */
/*         Universal Synchronous Asynchronous Receiver Transmitter            */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for USART_STS register  *******************/
#define USART_STS_PEFLG_Pos                                         (0U)
#define USART_STS_PEFLG_Msk                                         (0x1UL << USART_STS_PEFLG_Pos)                                 /*!< 0x00000001 */
#define USART_STS_PEFLG                                             USART_STS_PEFLG_Msk                                            /*!<Parity Error                 */
#define USART_STS_FEFLG_Pos                                         (1U)
#define USART_STS_FEFLG_Msk                                         (0x1UL << USART_STS_FEFLG_Pos)                                 /*!< 0x00000002 */
#define USART_STS_FEFLG                                             USART_STS_FEFLG_Msk                                            /*!<Framing Error                */
#define USART_STS_NEFLG_Pos                                         (2U)
#define USART_STS_NEFLG_Msk                                         (0x1UL << USART_STS_NEFLG_Pos)                                 /*!< 0x00000004 */
#define USART_STS_NEFLG                                             USART_STS_NEFLG_Msk                                            /*!<Noise Error Flag             */
#define USART_STS_OVREFLG_Pos                                       (3U)
#define USART_STS_OVREFLG_Msk                                       (0x1UL << USART_STS_OVREFLG_Pos)                               /*!< 0x00000008 */
#define USART_STS_OVREFLG                                           USART_STS_OVREFLG_Msk                                          /*!<OverRun Error                */
#define USART_STS_IDLEFLG_Pos                                       (4U)
#define USART_STS_IDLEFLG_Msk                                       (0x1UL << USART_STS_IDLEFLG_Pos)                               /*!< 0x00000010 */
#define USART_STS_IDLEFLG                                           USART_STS_IDLEFLG_Msk                                          /*!<IDLE line detected           */
#define USART_STS_RXBNEFLG_Pos                                      (5U)
#define USART_STS_RXBNEFLG_Msk                                      (0x1UL << USART_STS_RXBNEFLG_Pos)                              /*!< 0x00000020 */
#define USART_STS_RXBNEFLG                                          USART_STS_RXBNEFLG_Msk                                         /*!<Read Data Register Not Empty */
#define USART_STS_TXCFLG_Pos                                        (6U)
#define USART_STS_TXCFLG_Msk                                        (0x1UL << USART_STS_TXCFLG_Pos)                                /*!< 0x00000040 */
#define USART_STS_TXCFLG                                            USART_STS_TXCFLG_Msk                                           /*!<Transmission Complete        */
#define USART_STS_TXBEFLG_Pos                                       (7U)
#define USART_STS_TXBEFLG_Msk                                       (0x1UL << USART_STS_TXBEFLG_Pos)                               /*!< 0x00000080 */
#define USART_STS_TXBEFLG                                           USART_STS_TXBEFLG_Msk                                          /*!<Transmit Data Register Empty */
#define USART_STS_LBDFLG_Pos                                        (8U)
#define USART_STS_LBDFLG_Msk                                        (0x1UL << USART_STS_LBDFLG_Pos)                                /*!< 0x00000100 */
#define USART_STS_LBDFLG                                            USART_STS_LBDFLG_Msk                                           /*!<LIN Break Detection Flag     */
#define USART_STS_CTSFLG_Pos                                        (9U)
#define USART_STS_CTSFLG_Msk                                        (0x1UL << USART_STS_CTSFLG_Pos)                                /*!< 0x00000200 */
#define USART_STS_CTSFLG                                            USART_STS_CTSFLG_Msk                                           /*!<CTS Flag                     */

/*******************  Bit definition for USART_DATA register  *******************/
#define USART_DATA_DATA_Pos                                         (0U)
#define USART_DATA_DATA_Msk                                         (0x1FFUL << USART_DATA_DATA_Pos)                               /*!< 0x000001FF */
#define USART_DATA_DATA                                             USART_DATA_DATA_Msk                                            /*!<Data value */

/******************  Bit definition for USART_BR register  *******************/
#define USART_BR_FBR_Pos                                            (0U)
#define USART_BR_FBR_Msk                                            (0xFUL << USART_BR_FBR_Pos)                                    /*!< 0x0000000F */
#define USART_BR_FBR                                                USART_BR_FBR_Msk                                               /*!<Fraction of USARTDIV */
#define USART_BR_IBR_Pos                                            (4U)
#define USART_BR_IBR_Msk                                            (0xFFFUL << USART_BR_IBR_Pos)                                  /*!< 0x0000FFF0 */
#define USART_BR_IBR                                                USART_BR_IBR_Msk                                               /*!<Mantissa of USARTDIV */

/******************  Bit definition for USART_CTRL1 register  *******************/
#define USART_CTRL1_TXBF_Pos                                        (0U)
#define USART_CTRL1_TXBF_Msk                                        (0x1UL << USART_CTRL1_TXBF_Pos)                                /*!< 0x00000001 */
#define USART_CTRL1_TXBF                                            USART_CTRL1_TXBF_Msk                                           /*!<Send Break                             */
#define USART_CTRL1_RXMUTEEN_Pos                                    (1U)
#define USART_CTRL1_RXMUTEEN_Msk                                    (0x1UL << USART_CTRL1_RXMUTEEN_Pos)                            /*!< 0x00000002 */
#define USART_CTRL1_RXMUTEEN                                        USART_CTRL1_RXMUTEEN_Msk                                       /*!<Receiver wakeup                        */
#define USART_CTRL1_RXEN_Pos                                        (2U)
#define USART_CTRL1_RXEN_Msk                                        (0x1UL << USART_CTRL1_RXEN_Pos)                                /*!< 0x00000004 */
#define USART_CTRL1_RXEN                                            USART_CTRL1_RXEN_Msk                                           /*!<Receiver Enable                        */
#define USART_CTRL1_TXEN_Pos                                        (3U)
#define USART_CTRL1_TXEN_Msk                                        (0x1UL << USART_CTRL1_TXEN_Pos)                                /*!< 0x00000008 */
#define USART_CTRL1_TXEN                                            USART_CTRL1_TXEN_Msk                                           /*!<Transmitter Enable                     */
#define USART_CTRL1_IDLEIEN_Pos                                     (4U)
#define USART_CTRL1_IDLEIEN_Msk                                     (0x1UL << USART_CTRL1_IDLEIEN_Pos)                             /*!< 0x00000010 */
#define USART_CTRL1_IDLEIEN                                         USART_CTRL1_IDLEIEN_Msk                                        /*!<IDLE Interrupt Enable                  */
#define USART_CTRL1_RXBNEIEN_Pos                                    (5U)
#define USART_CTRL1_RXBNEIEN_Msk                                    (0x1UL << USART_CTRL1_RXBNEIEN_Pos)                            /*!< 0x00000020 */
#define USART_CTRL1_RXBNEIEN                                        USART_CTRL1_RXBNEIEN_Msk                                       /*!<RXNE Interrupt Enable                  */
#define USART_CTRL1_TXCIEN_Pos                                      (6U)
#define USART_CTRL1_TXCIEN_Msk                                      (0x1UL << USART_CTRL1_TXCIEN_Pos)                              /*!< 0x00000040 */
#define USART_CTRL1_TXCIEN                                          USART_CTRL1_TXCIEN_Msk                                         /*!<Transmission Complete Interrupt Enable */
#define USART_CTRL1_TXBEIEN_Pos                                     (7U)
#define USART_CTRL1_TXBEIEN_Msk                                     (0x1UL << USART_CTRL1_TXBEIEN_Pos)                             /*!< 0x00000080 */
#define USART_CTRL1_TXBEIEN                                         USART_CTRL1_TXBEIEN_Msk                                        /*!<TXE Interrupt Enable                   */
#define USART_CTRL1_PEIEN_Pos                                       (8U)
#define USART_CTRL1_PEIEN_Msk                                       (0x1UL << USART_CTRL1_PEIEN_Pos)                               /*!< 0x00000100 */
#define USART_CTRL1_PEIEN                                           USART_CTRL1_PEIEN_Msk                                          /*!<PE Interrupt Enable                    */
#define USART_CTRL1_PCFG_Pos                                        (9U)
#define USART_CTRL1_PCFG_Msk                                        (0x1UL << USART_CTRL1_PCFG_Pos)                                /*!< 0x00000200 */
#define USART_CTRL1_PCFG                                            USART_CTRL1_PCFG_Msk                                           /*!<Parity Selection                       */
#define USART_CTRL1_PCEN_Pos                                        (10U)
#define USART_CTRL1_PCEN_Msk                                        (0x1UL << USART_CTRL1_PCEN_Pos)                                /*!< 0x00000400 */
#define USART_CTRL1_PCEN                                            USART_CTRL1_PCEN_Msk                                           /*!<Parity Control Enable                  */
#define USART_CTRL1_WUPMCFG_Pos                                     (11U)
#define USART_CTRL1_WUPMCFG_Msk                                     (0x1UL << USART_CTRL1_WUPMCFG_Pos)                             /*!< 0x00000800 */
#define USART_CTRL1_WUPMCFG                                         USART_CTRL1_WUPMCFG_Msk                                        /*!<Wakeup method                          */
#define USART_CTRL1_DBLCFG_Pos                                      (12U)
#define USART_CTRL1_DBLCFG_Msk                                      (0x1UL << USART_CTRL1_DBLCFG_Pos)                              /*!< 0x00001000 */
#define USART_CTRL1_DBLCFG                                          USART_CTRL1_DBLCFG_Msk                                         /*!<Word length                            */
#define USART_CTRL1_UEN_Pos                                         (13U)
#define USART_CTRL1_UEN_Msk                                         (0x1UL << USART_CTRL1_UEN_Pos)                                 /*!< 0x00002000 */
#define USART_CTRL1_UEN                                             USART_CTRL1_UEN_Msk                                            /*!<USART Enable                           */
#define USART_CTRL1_OSMCFG_Pos                                      (15U)
#define USART_CTRL1_OSMCFG_Msk                                      (0x1UL << USART_CTRL1_OSMCFG_Pos)                              /*!< 0x00008000 */
#define USART_CTRL1_OSMCFG                                          USART_CTRL1_OSMCFG_Msk                                         /*!<USART Oversampling by 8 enable         */

/******************  Bit definition for USART_CTRL2 register  *******************/
#define USART_CTRL2_ADDR_Pos                                        (0U)
#define USART_CTRL2_ADDR_Msk                                        (0xFUL << USART_CTRL2_ADDR_Pos)                                /*!< 0x0000000F */
#define USART_CTRL2_ADDR                                            USART_CTRL2_ADDR_Msk                                           /*!<Address of the USART node            */
#define USART_CTRL2_LBDLCFG_Pos                                     (5U)
#define USART_CTRL2_LBDLCFG_Msk                                     (0x1UL << USART_CTRL2_LBDLCFG_Pos)                             /*!< 0x00000020 */
#define USART_CTRL2_LBDLCFG                                         USART_CTRL2_LBDLCFG_Msk                                        /*!<LIN Break Detection Length           */
#define USART_CTRL2_LBDIEN_Pos                                      (6U)
#define USART_CTRL2_LBDIEN_Msk                                      (0x1UL << USART_CTRL2_LBDIEN_Pos)                              /*!< 0x00000040 */
#define USART_CTRL2_LBDIEN                                          USART_CTRL2_LBDIEN_Msk                                         /*!<LIN Break Detection Interrupt Enable */
#define USART_CTRL2_LBCPOEN_Pos                                     (8U)
#define USART_CTRL2_LBCPOEN_Msk                                     (0x1UL << USART_CTRL2_LBCPOEN_Pos)                             /*!< 0x00000100 */
#define USART_CTRL2_LBCPOEN                                         USART_CTRL2_LBCPOEN_Msk                                        /*!<Last Bit Clock pulse                 */
#define USART_CTRL2_CPHA_Pos                                        (9U)
#define USART_CTRL2_CPHA_Msk                                        (0x1UL << USART_CTRL2_CPHA_Pos)                                /*!< 0x00000200 */
#define USART_CTRL2_CPHA                                            USART_CTRL2_CPHA_Msk                                           /*!<Clock Phase                          */
#define USART_CTRL2_CPOL_Pos                                        (10U)
#define USART_CTRL2_CPOL_Msk                                        (0x1UL << USART_CTRL2_CPOL_Pos)                                /*!< 0x00000400 */
#define USART_CTRL2_CPOL                                            USART_CTRL2_CPOL_Msk                                           /*!<Clock Polarity                       */
#define USART_CTRL2_CLKEN_Pos                                       (11U)
#define USART_CTRL2_CLKEN_Msk                                       (0x1UL << USART_CTRL2_CLKEN_Pos)                               /*!< 0x00000800 */
#define USART_CTRL2_CLKEN                                           USART_CTRL2_CLKEN_Msk                                          /*!<Clock Enable                         */

#define USART_CTRL2_STOPCFG_Pos                                     (12U)
#define USART_CTRL2_STOPCFG_Msk                                     (0x3UL << USART_CTRL2_STOPCFG_Pos)                             /*!< 0x00003000 */
#define USART_CTRL2_STOPCFG                                         USART_CTRL2_STOPCFG_Msk                                        /*!<STOP[1:0] bits (STOP bits) */
#define USART_CTRL2_STOPCFG_0                                       (0x1UL << USART_CTRL2_STOPCFG_Pos)                             /*!< 0x1000 */
#define USART_CTRL2_STOPCFG_1                                       (0x2UL << USART_CTRL2_STOPCFG_Pos)                             /*!< 0x2000 */

#define USART_CTRL2_LINMEN_Pos                                      (14U)
#define USART_CTRL2_LINMEN_Msk                                      (0x1UL << USART_CTRL2_LINMEN_Pos)                              /*!< 0x00004000 */
#define USART_CTRL2_LINMEN                                          USART_CTRL2_LINMEN_Msk                                         /*!<LIN mode enable */

/******************  Bit definition for USART_CTRL3 register  *******************/
#define USART_CTRL3_ERRIEN_Pos                                      (0U)
#define USART_CTRL3_ERRIEN_Msk                                      (0x1UL << USART_CTRL3_ERRIEN_Pos)                              /*!< 0x00000001 */
#define USART_CTRL3_ERRIEN                                          USART_CTRL3_ERRIEN_Msk                                         /*!<Error Interrupt Enable      */
#define USART_CTRL3_IREN_Pos                                        (1U)
#define USART_CTRL3_IREN_Msk                                        (0x1UL << USART_CTRL3_IREN_Pos)                                /*!< 0x00000002 */
#define USART_CTRL3_IREN                                            USART_CTRL3_IREN_Msk                                           /*!<IrDA mode Enable            */
#define USART_CTRL3_IRLPEN_Pos                                      (2U)
#define USART_CTRL3_IRLPEN_Msk                                      (0x1UL << USART_CTRL3_IRLPEN_Pos)                              /*!< 0x00000004 */
#define USART_CTRL3_IRLPEN                                          USART_CTRL3_IRLPEN_Msk                                         /*!<IrDA Low-Power              */
#define USART_CTRL3_HDEN_Pos                                        (3U)
#define USART_CTRL3_HDEN_Msk                                        (0x1UL << USART_CTRL3_HDEN_Pos)                                /*!< 0x00000008 */
#define USART_CTRL3_HDEN                                            USART_CTRL3_HDEN_Msk                                           /*!<Half-Duplex Selection       */
#define USART_CTRL3_SCNACKEN_Pos                                    (4U)
#define USART_CTRL3_SCNACKEN_Msk                                    (0x1UL << USART_CTRL3_SCNACKEN_Pos)                            /*!< 0x00000010 */
#define USART_CTRL3_SCNACKEN                                        USART_CTRL3_SCNACKEN_Msk                                       /*!<Smartcard NACK enable       */
#define USART_CTRL3_SCEN_Pos                                        (5U)
#define USART_CTRL3_SCEN_Msk                                        (0x1UL << USART_CTRL3_SCEN_Pos)                                /*!< 0x00000020 */
#define USART_CTRL3_SCEN                                            USART_CTRL3_SCEN_Msk                                           /*!<Smartcard mode enable       */
#define USART_CTRL3_DMARXEN_Pos                                     (6U)
#define USART_CTRL3_DMARXEN_Msk                                     (0x1UL << USART_CTRL3_DMARXEN_Pos)                             /*!< 0x00000040 */
#define USART_CTRL3_DMARXEN                                         USART_CTRL3_DMARXEN_Msk                                        /*!<DMA Enable Receiver         */
#define USART_CTRL3_DMATXEN_Pos                                     (7U)
#define USART_CTRL3_DMATXEN_Msk                                     (0x1UL << USART_CTRL3_DMATXEN_Pos)                             /*!< 0x00000080 */
#define USART_CTRL3_DMATXEN                                         USART_CTRL3_DMATXEN_Msk                                        /*!<DMA Enable Transmitter      */
#define USART_CTRL3_RTSEN_Pos                                       (8U)
#define USART_CTRL3_RTSEN_Msk                                       (0x1UL << USART_CTRL3_RTSEN_Pos)                               /*!< 0x00000100 */
#define USART_CTRL3_RTSEN                                           USART_CTRL3_RTSEN_Msk                                          /*!<RTS Enable                  */
#define USART_CTRL3_CTSEN_Pos                                       (9U)
#define USART_CTRL3_CTSEN_Msk                                       (0x1UL << USART_CTRL3_CTSEN_Pos)                               /*!< 0x00000200 */
#define USART_CTRL3_CTSEN                                           USART_CTRL3_CTSEN_Msk                                          /*!<CTS Enable                  */
#define USART_CTRL3_CTSIEN_Pos                                      (10U)
#define USART_CTRL3_CTSIEN_Msk                                      (0x1UL << USART_CTRL3_CTSIEN_Pos)                              /*!< 0x00000400 */
#define USART_CTRL3_CTSIEN                                          USART_CTRL3_CTSIEN_Msk                                         /*!<CTS Interrupt Enable        */
#define USART_CTRL3_SAMCFG_Pos                                      (11U)
#define USART_CTRL3_SAMCFG_Msk                                      (0x1UL << USART_CTRL3_SAMCFG_Pos)                              /*!< 0x00000800 */
#define USART_CTRL3_SAMCFG                                          USART_CTRL3_SAMCFG_Msk                                         /*!<USART One bit method enable */

/******************  Bit definition for USART_GTPSC register  ******************/
#define USART_GTPSC_PSC_Pos                                         (0U)
#define USART_GTPSC_PSC_Msk                                         (0xFFUL << USART_GTPSC_PSC_Pos)                                /*!< 0x000000FF */
#define USART_GTPSC_PSC                                             USART_GTPSC_PSC_Msk                                            /*!<PSC[7:0] bits (Prescaler value) */
#define USART_GTPSC_PSC_0                                           (0x01UL << USART_GTPSC_PSC_Pos)                                /*!< 0x0001 */
#define USART_GTPSC_PSC_1                                           (0x02UL << USART_GTPSC_PSC_Pos)                                /*!< 0x0002 */
#define USART_GTPSC_PSC_2                                           (0x04UL << USART_GTPSC_PSC_Pos)                                /*!< 0x0004 */
#define USART_GTPSC_PSC_3                                           (0x08UL << USART_GTPSC_PSC_Pos)                                /*!< 0x0008 */
#define USART_GTPSC_PSC_4                                           (0x10UL << USART_GTPSC_PSC_Pos)                                /*!< 0x0010 */
#define USART_GTPSC_PSC_5                                           (0x20UL << USART_GTPSC_PSC_Pos)                                /*!< 0x0020 */
#define USART_GTPSC_PSC_6                                           (0x40UL << USART_GTPSC_PSC_Pos)                                /*!< 0x0040 */
#define USART_GTPSC_PSC_7                                           (0x80UL << USART_GTPSC_PSC_Pos)                                /*!< 0x0080 */

#define USART_GTPSC_GRDT_Pos                                        (8U)
#define USART_GTPSC_GRDT_Msk                                        (0xFFUL << USART_GTPSC_GRDT_Pos)                               /*!< 0x0000FF00 */
#define USART_GTPSC_GRDT                                            USART_GTPSC_GRDT_Msk                                           /*!<Guard time value */

/******************************************************************************/
/*                                                                            */
/*                            Window WATCHDOG                                 */
/*                                                                            */
/******************************************************************************/
/*******************  Bit definition for WWDT_CTRL register  ********************/
#define WWDT_CTRL_CNT_Pos                                           (0U)
#define WWDT_CTRL_CNT_Msk                                           (0x7FUL << WWDT_CTRL_CNT_Pos)                                  /*!< 0x0000007F */
#define WWDT_CTRL_CNT                                               WWDT_CTRL_CNT_Msk                                              /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
#define WWDT_CTRL_CNT_0                                             (0x01UL << WWDT_CTRL_CNT_Pos)                                  /*!< 0x01 */
#define WWDT_CTRL_CNT_1                                             (0x02UL << WWDT_CTRL_CNT_Pos)                                  /*!< 0x02 */
#define WWDT_CTRL_CNT_2                                             (0x04UL << WWDT_CTRL_CNT_Pos)                                  /*!< 0x04 */
#define WWDT_CTRL_CNT_3                                             (0x08UL << WWDT_CTRL_CNT_Pos)                                  /*!< 0x08 */
#define WWDT_CTRL_CNT_4                                             (0x10UL << WWDT_CTRL_CNT_Pos)                                  /*!< 0x10 */
#define WWDT_CTRL_CNT_5                                             (0x20UL << WWDT_CTRL_CNT_Pos)                                  /*!< 0x20 */
#define WWDT_CTRL_CNT_6                                             (0x40UL << WWDT_CTRL_CNT_Pos)                                  /*!< 0x40 */
/* Legacy defines */
#define WWDT_CTRL_CNT0                                              WWDT_CTRL_CNT_0
#define WWDT_CTRL_CNT1                                              WWDT_CTRL_CNT_1
#define WWDT_CTRL_CNT2                                              WWDT_CTRL_CNT_2
#define WWDT_CTRL_CNT3                                              WWDT_CTRL_CNT_3
#define WWDT_CTRL_CNT4                                              WWDT_CTRL_CNT_4
#define WWDT_CTRL_CNT5                                              WWDT_CTRL_CNT_5
#define WWDT_CTRL_CNT6                                              WWDT_CTRL_CNT_6

#define WWDT_CTRL_WWDTEN_Pos                                        (7U)
#define WWDT_CTRL_WWDTEN_Msk                                        (0x1UL << WWDT_CTRL_WWDTEN_Pos)                                /*!< 0x00000080 */
#define WWDT_CTRL_WWDTEN                                            WWDT_CTRL_WWDTEN_Msk                                           /*!<Activation bit */

/*******************  Bit definition for WWDT_CFR register  *******************/
#define WWDT_CFR_WIN_Pos                                            (0U)
#define WWDT_CFR_WIN_Msk                                            (0x7FUL << WWDT_CFR_WIN_Pos)                                   /*!< 0x0000007F */
#define WWDT_CFR_WIN                                                WWDT_CFR_WIN_Msk                                               /*!<W[6:0] bits (7-bit window value) */
#define WWDT_CFR_WIN_0                                              (0x01UL << WWDT_CFR_WIN_Pos)                                   /*!< 0x0001 */
#define WWDT_CFR_WIN_1                                              (0x02UL << WWDT_CFR_WIN_Pos)                                   /*!< 0x0002 */
#define WWDT_CFR_WIN_2                                              (0x04UL << WWDT_CFR_WIN_Pos)                                   /*!< 0x0004 */
#define WWDT_CFR_WIN_3                                              (0x08UL << WWDT_CFR_WIN_Pos)                                   /*!< 0x0008 */
#define WWDT_CFR_WIN_4                                              (0x10UL << WWDT_CFR_WIN_Pos)                                   /*!< 0x0010 */
#define WWDT_CFR_WIN_5                                              (0x20UL << WWDT_CFR_WIN_Pos)                                   /*!< 0x0020 */
#define WWDT_CFR_WIN_6                                              (0x40UL << WWDT_CFR_WIN_Pos)                                   /*!< 0x0040 */
/* Legacy defines */
#define WWDT_CFR_WIN0                                               WWDT_CFR_WIN_0
#define WWDT_CFR_WIN1                                               WWDT_CFR_WIN_1
#define WWDT_CFR_WIN2                                               WWDT_CFR_WIN_2
#define WWDT_CFR_WIN3                                               WWDT_CFR_WIN_3
#define WWDT_CFR_WIN4                                               WWDT_CFR_WIN_4
#define WWDT_CFR_WIN5                                               WWDT_CFR_WIN_5
#define WWDT_CFR_WIN6                                               WWDT_CFR_WIN_6

#define WWDT_CFR_TBPSC_Pos                                          (7U)
#define WWDT_CFR_TBPSC_Msk                                          (0x3UL << WWDT_CFR_TBPSC_Pos)                                  /*!< 0x00000180 */
#define WWDT_CFR_TBPSC                                              WWDT_CFR_TBPSC_Msk                                             /*!<WDGTB[1:0] bits (Timer Base) */
#define WWDT_CFR_TBPSC_0                                            (0x1UL << WWDT_CFR_TBPSC_Pos)                                  /*!< 0x0080 */
#define WWDT_CFR_TBPSC_1                                            (0x2UL << WWDT_CFR_TBPSC_Pos)                                  /*!< 0x0100 */
/* Legacy defines */
#define WWDT_CFR_TBPSC0                                             WWDT_CFR_TBPSC_0
#define WWDT_CFR_TBPSC1                                             WWDT_CFR_TBPSC_1

#define WWDT_CFR_EWIEN_Pos                                          (9U)
#define WWDT_CFR_EWIEN_Msk                                          (0x1UL << WWDT_CFR_EWIEN_Pos)                                  /*!< 0x00000200 */
#define WWDT_CFR_EWIEN                                              WWDT_CFR_EWIEN_Msk                                             /*!<Early Wakeup Interrupt */

/*******************  Bit definition for WWDT_STS register  ********************/
#define WWDT_STS_EWIFLG_Pos                                         (0U)
#define WWDT_STS_EWIFLG_Msk                                         (0x1UL << WWDT_STS_EWIFLG_Pos)                                 /*!< 0x00000001 */
#define WWDT_STS_EWIFLG                                             WWDT_STS_EWIFLG_Msk                                            /*!<Early Wakeup Interrupt Flag */


/******************************************************************************/
/*                                                                            */
/*                                DBG                                         */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for DBGMCU_IDCODE register  *************/
#define DBGMCU_IDCODE_EQR_Pos                                       (0U)
#define DBGMCU_IDCODE_EQR_Msk                                       (0xFFFUL << DBGMCU_IDCODE_EQR_Pos)                             /*!< 0x00000FFF */
#define DBGMCU_IDCODE_EQR                                           DBGMCU_IDCODE_EQR_Msk
#define DBGMCU_IDCODE_WVR_Pos                                       (16U)
#define DBGMCU_IDCODE_WVR_Msk                                       (0xFFFFUL << DBGMCU_IDCODE_WVR_Pos)                            /*!< 0xFFFF0000 */
#define DBGMCU_IDCODE_WVR                                           DBGMCU_IDCODE_WVR_Msk

/********************  Bit definition for DBGMCU_CFG register  *****************/
#define DBGMCU_CFG_SLEEP_CLK_STS_Pos                                (0U)
#define DBGMCU_CFG_SLEEP_CLK_STS_Msk                                (0x1UL << DBGMCU_CFG_SLEEP_CLK_STS_Pos)                        /*!< 0x00000001 */
#define DBGMCU_CFG_SLEEP_CLK_STS                                    DBGMCU_CFG_SLEEP_CLK_STS_Msk
#define DBGMCU_CFG_STOP_CLK_STS_Pos                                 (1U)
#define DBGMCU_CFG_STOP_CLK_STS_Msk                                 (0x1UL << DBGMCU_CFG_STOP_CLK_STS_Pos)                         /*!< 0x00000002 */
#define DBGMCU_CFG_STOP_CLK_STS                                     DBGMCU_CFG_STOP_CLK_STS_Msk
#define DBGMCU_CFG_STANDBY_CLK_STS_Pos                              (2U)
#define DBGMCU_CFG_STANDBY_CLK_STS_Msk                              (0x1UL << DBGMCU_CFG_STANDBY_CLK_STS_Pos)                      /*!< 0x00000004 */
#define DBGMCU_CFG_STANDBY_CLK_STS                                  DBGMCU_CFG_STANDBY_CLK_STS_Msk
#define DBGMCU_CFG_TRACE_IOEN_Pos                                   (5U)
#define DBGMCU_CFG_TRACE_IOEN_Msk                                   (0x1UL << DBGMCU_CFG_TRACE_IOEN_Pos)                           /*!< 0x00000020 */
#define DBGMCU_CFG_TRACE_IOEN                                       DBGMCU_CFG_TRACE_IOEN_Msk

#define DBGMCU_CFG_TRACE_MODE_Pos                                   (6U)
#define DBGMCU_CFG_TRACE_MODE_Msk                                   (0x3UL << DBGMCU_CFG_TRACE_MODE_Pos)                           /*!< 0x000000C0 */
#define DBGMCU_CFG_TRACE_MODE                                       DBGMCU_CFG_TRACE_MODE_Msk
#define DBGMCU_CFG_TRACE_MODE_0                                     (0x1UL << DBGMCU_CFG_TRACE_MODE_Pos)                           /*!< 0x00000040 */
#define DBGMCU_CFG_TRACE_MODE_1                                     (0x2UL << DBGMCU_CFG_TRACE_MODE_Pos)                           /*!< 0x00000080 */

/********************  Bit definition for DBGMCU_APB1_FZ register  ************/
#define DBGMCU_APB1F_TMR2_STS_Pos                                   (0U)
#define DBGMCU_APB1F_TMR2_STS_Msk                                   (0x1UL << DBGMCU_APB1F_TMR2_STS_Pos)                           /*!< 0x00000001 */
#define DBGMCU_APB1F_TMR2_STS                                       DBGMCU_APB1F_TMR2_STS_Msk
#define DBGMCU_APB1F_TMR3_STS_Pos                                   (1U)
#define DBGMCU_APB1F_TMR3_STS_Msk                                   (0x1UL << DBGMCU_APB1F_TMR3_STS_Pos)                           /*!< 0x00000002 */
#define DBGMCU_APB1F_TMR3_STS                                       DBGMCU_APB1F_TMR3_STS_Msk
#define DBGMCU_APB1F_TMR4_STS_Pos                                   (2U)
#define DBGMCU_APB1F_TMR4_STS_Msk                                   (0x1UL << DBGMCU_APB1F_TMR4_STS_Pos)                           /*!< 0x00000004 */
#define DBGMCU_APB1F_TMR4_STS                                       DBGMCU_APB1F_TMR4_STS_Msk
#define DBGMCU_APB1F_TMR5_STS_Pos                                   (3U)
#define DBGMCU_APB1F_TMR5_STS_Msk                                   (0x1UL << DBGMCU_APB1F_TMR5_STS_Pos)                           /*!< 0x00000008 */
#define DBGMCU_APB1F_TMR5_STS                                       DBGMCU_APB1F_TMR5_STS_Msk
#define DBGMCU_APB1F_TMR6_STS_Pos                                   (4U)
#define DBGMCU_APB1F_TMR6_STS_Msk                                   (0x1UL << DBGMCU_APB1F_TMR6_STS_Pos)                           /*!< 0x00000010 */
#define DBGMCU_APB1F_TMR6_STS                                       DBGMCU_APB1F_TMR6_STS_Msk
#define DBGMCU_APB1F_TMR7_STS_Pos                                   (5U)
#define DBGMCU_APB1F_TMR7_STS_Msk                                   (0x1UL << DBGMCU_APB1F_TMR7_STS_Pos)                           /*!< 0x00000020 */
#define DBGMCU_APB1F_TMR7_STS                                       DBGMCU_APB1F_TMR7_STS_Msk
#define DBGMCU_APB1F_TMR12_STS_Pos                                  (6U)
#define DBGMCU_APB1F_TMR12_STS_Msk                                  (0x1UL << DBGMCU_APB1F_TMR12_STS_Pos)                          /*!< 0x00000040 */
#define DBGMCU_APB1F_TMR12_STS                                      DBGMCU_APB1F_TMR12_STS_Msk
#define DBGMCU_APB1F_TMR13_STS_Pos                                  (7U)
#define DBGMCU_APB1F_TMR13_STS_Msk                                  (0x1UL << DBGMCU_APB1F_TMR13_STS_Pos)                          /*!< 0x00000080 */
#define DBGMCU_APB1F_TMR13_STS                                      DBGMCU_APB1F_TMR13_STS_Msk
#define DBGMCU_APB1F_TMR14_STS_Pos                                  (8U)
#define DBGMCU_APB1F_TMR14_STS_Msk                                  (0x1UL << DBGMCU_APB1F_TMR14_STS_Pos)                          /*!< 0x00000100 */
#define DBGMCU_APB1F_TMR14_STS                                      DBGMCU_APB1F_TMR14_STS_Msk
#define DBGMCU_APB1F_RTC_STS_Pos                                    (10U)
#define DBGMCU_APB1F_RTC_STS_Msk                                    (0x1UL << DBGMCU_APB1F_RTC_STS_Pos)                            /*!< 0x00000400 */
#define DBGMCU_APB1F_RTC_STS                                        DBGMCU_APB1F_RTC_STS_Msk
#define DBGMCU_APB1F_WWDT_STS_Pos                                   (11U)
#define DBGMCU_APB1F_WWDT_STS_Msk                                   (0x1UL << DBGMCU_APB1F_WWDT_STS_Pos)                           /*!< 0x00000800 */
#define DBGMCU_APB1F_WWDT_STS                                       DBGMCU_APB1F_WWDT_STS_Msk
#define DBGMCU_APB1F_IWDT_STS_Pos                                   (12U)
#define DBGMCU_APB1F_IWDT_STS_Msk                                   (0x1UL << DBGMCU_APB1F_IWDT_STS_Pos)                           /*!< 0x00001000 */
#define DBGMCU_APB1F_IWDT_STS                                       DBGMCU_APB1F_IWDT_STS_Msk
#define DBGMCU_APB1F_I2C1_SMBUS_TIMEOUT_STS_Pos                     (21U)
#define DBGMCU_APB1F_I2C1_SMBUS_TIMEOUT_STS_Msk                     (0x1UL << DBGMCU_APB1F_I2C1_SMBUS_TIMEOUT_STS_Pos)             /*!< 0x00200000 */
#define DBGMCU_APB1F_I2C1_SMBUS_TIMEOUT_STS                         DBGMCU_APB1F_I2C1_SMBUS_TIMEOUT_STS_Msk
#define DBGMCU_APB1F_I2C2_SMBUS_TIMEOUT_STS_Pos                     (22U)
#define DBGMCU_APB1F_I2C2_SMBUS_TIMEOUT_STS_Msk                     (0x1UL << DBGMCU_APB1F_I2C2_SMBUS_TIMEOUT_STS_Pos)             /*!< 0x00400000 */
#define DBGMCU_APB1F_I2C2_SMBUS_TIMEOUT_STS                         DBGMCU_APB1F_I2C2_SMBUS_TIMEOUT_STS_Msk
#define DBGMCU_APB1F_I2C3_SMBUS_TIMEOUT_STS_Pos                     (23U)
#define DBGMCU_APB1F_I2C3_SMBUS_TIMEOUT_STS_Msk                     (0x1UL << DBGMCU_APB1F_I2C3_SMBUS_TIMEOUT_STS_Pos)             /*!< 0x00800000 */
#define DBGMCU_APB1F_I2C3_SMBUS_TIMEOUT_STS                         DBGMCU_APB1F_I2C3_SMBUS_TIMEOUT_STS_Msk
#define DBGMCU_APB1F_CAN1_STS_Pos                                   (25U)
#define DBGMCU_APB1F_CAN1_STS_Msk                                   (0x1UL << DBGMCU_APB1F_CAN1_STS_Pos)                           /*!< 0x02000000 */
#define DBGMCU_APB1F_CAN1_STS                                       DBGMCU_APB1F_CAN1_STS_Msk
#define DBGMCU_APB1F_CAN2_STS_Pos                                   (26U)
#define DBGMCU_APB1F_CAN2_STS_Msk                                   (0x1UL << DBGMCU_APB1F_CAN2_STS_Pos)                           /*!< 0x04000000 */
#define DBGMCU_APB1F_CAN2_STS                                       DBGMCU_APB1F_CAN2_STS_Msk
/* Old IWDTSTOP bit definition, maintained for legacy purpose */
#define DBGMCU_APB1F_IWDEG_STOP                                     DBGMCU_APB1F_IWDT_STS

/********************  Bit definition for DBGMCU_APB2_FZ register  ************/
#define DBGMCU_APB2F_TMR1_STS_Pos                                   (0U)
#define DBGMCU_APB2F_TMR1_STS_Msk                                   (0x1UL << DBGMCU_APB2F_TMR1_STS_Pos)                           /*!< 0x00000001 */
#define DBGMCU_APB2F_TMR1_STS                                       DBGMCU_APB2F_TMR1_STS_Msk
#define DBGMCU_APB2F_TMR8_STS_Pos                                   (1U)
#define DBGMCU_APB2F_TMR8_STS_Msk                                   (0x1UL << DBGMCU_APB2F_TMR8_STS_Pos)                           /*!< 0x00000002 */
#define DBGMCU_APB2F_TMR8_STS                                       DBGMCU_APB2F_TMR8_STS_Msk
#define DBGMCU_APB2F_TMR9_STS_Pos                                   (16U)
#define DBGMCU_APB2F_TMR9_STS_Msk                                   (0x1UL << DBGMCU_APB2F_TMR9_STS_Pos)                           /*!< 0x00010000 */
#define DBGMCU_APB2F_TMR9_STS                                       DBGMCU_APB2F_TMR9_STS_Msk
#define DBGMCU_APB2F_TMR10_STS_Pos                                  (17U)
#define DBGMCU_APB2F_TMR10_STS_Msk                                  (0x1UL << DBGMCU_APB2F_TMR10_STS_Pos)                          /*!< 0x00020000 */
#define DBGMCU_APB2F_TMR10_STS                                      DBGMCU_APB2F_TMR10_STS_Msk
#define DBGMCU_APB2F_TMR11_STS_Pos                                  (18U)
#define DBGMCU_APB2F_TMR11_STS_Msk                                  (0x1UL << DBGMCU_APB2F_TMR11_STS_Pos)                          /*!< 0x00040000 */
#define DBGMCU_APB2F_TMR11_STS                                      DBGMCU_APB2F_TMR11_STS_Msk

/******************************************************************************/
/*                                                                            */
/*                Ethernet MAC Registers bits definitions                     */
/*                                                                            */
/******************************************************************************/
/* Bit definition for Ethernet MAC Control Register register */
#define ETH_MACCFG_WDTDIS_Pos                                       (23U)
#define ETH_MACCFG_WDTDIS_Msk                                       (0x1UL << ETH_MACCFG_WDTDIS_Pos)                               /*!< 0x00800000 */
#define ETH_MACCFG_WDTDIS                                           ETH_MACCFG_WDTDIS_Msk                                          /* Watchdog disable */
#define ETH_MACCFG_JDIS_Pos                                         (22U)
#define ETH_MACCFG_JDIS_Msk                                         (0x1UL << ETH_MACCFG_JDIS_Pos)                                 /*!< 0x00400000 */
#define ETH_MACCFG_JDIS                                             ETH_MACCFG_JDIS_Msk                                            /* Jabber disable */
#define ETH_MACCFG_IFG_Pos                                          (17U)
#define ETH_MACCFG_IFG_Msk                                          (0x7UL << ETH_MACCFG_IFG_Pos)                                  /*!< 0x000E0000 */
#define ETH_MACCFG_IFG                                              ETH_MACCFG_IFG_Msk                                             /* Inter-frame gap */
#define ETH_MACCFG_IFG_96Bit                                        0x00000000U                                                    /* Minimum IFG between frames during transmission is 96Bit */
#define ETH_MACCFG_IFG_88Bit                                        0x00020000U                                                    /* Minimum IFG between frames during transmission is 88Bit */
#define ETH_MACCFG_IFG_80Bit                                        0x00040000U                                                    /* Minimum IFG between frames during transmission is 80Bit */
#define ETH_MACCFG_IFG_72Bit                                        0x00060000U                                                    /* Minimum IFG between frames during transmission is 72Bit */
#define ETH_MACCFG_IFG_64Bit                                        0x00080000U                                                    /* Minimum IFG between frames during transmission is 64Bit */
#define ETH_MACCFG_IFG_56Bit                                        0x000A0000U                                                    /* Minimum IFG between frames during transmission is 56Bit */
#define ETH_MACCFG_IFG_48Bit                                        0x000C0000U                                                    /* Minimum IFG between frames during transmission is 48Bit */
#define ETH_MACCFG_IFG_40Bit                                        0x000E0000U                                                    /* Minimum IFG between frames during transmission is 40Bit */
#define ETH_MACCFG_DISCRS_Pos                                       (16U)
#define ETH_MACCFG_DISCRS_Msk                                       (0x1UL << ETH_MACCFG_DISCRS_Pos)                               /*!< 0x00010000 */
#define ETH_MACCFG_DISCRS                                           ETH_MACCFG_DISCRS_Msk                                          /* Carrier sense disable (during transmission) */
#define ETH_MACCFG_SSEL_Pos                                         (14U)
#define ETH_MACCFG_SSEL_Msk                                         (0x1UL << ETH_MACCFG_SSEL_Pos)                                 /*!< 0x00004000 */
#define ETH_MACCFG_SSEL                                             ETH_MACCFG_SSEL_Msk                                            /* Fast ethernet speed */
#define ETH_MACCFG_DISRXO_Pos                                       (13U)
#define ETH_MACCFG_DISRXO_Msk                                       (0x1UL << ETH_MACCFG_DISRXO_Pos)                               /*!< 0x00002000 */
#define ETH_MACCFG_DISRXO                                           ETH_MACCFG_DISRXO_Msk                                          /* Receive own disable */
#define ETH_MACCFG_LBM_Pos                                          (12U)
#define ETH_MACCFG_LBM_Msk                                          (0x1UL << ETH_MACCFG_LBM_Pos)                                  /*!< 0x00001000 */
#define ETH_MACCFG_LBM                                              ETH_MACCFG_LBM_Msk                                             /* loopback mode */
#define ETH_MACCFG_DM_Pos                                           (11U)
#define ETH_MACCFG_DM_Msk                                           (0x1UL << ETH_MACCFG_DM_Pos)                                   /*!< 0x00000800 */
#define ETH_MACCFG_DM                                               ETH_MACCFG_DM_Msk                                              /* Duplex mode */
#define ETH_MACCFG_IPC_Pos                                          (10U)
#define ETH_MACCFG_IPC_Msk                                          (0x1UL << ETH_MACCFG_IPC_Pos)                                  /*!< 0x00000400 */
#define ETH_MACCFG_IPC                                              ETH_MACCFG_IPC_Msk                                             /* IP Checksum offload */
#define ETH_MACCFG_DISR_Pos                                         (9U)
#define ETH_MACCFG_DISR_Msk                                         (0x1UL << ETH_MACCFG_DISR_Pos)                                 /*!< 0x00000200 */
#define ETH_MACCFG_DISR                                             ETH_MACCFG_DISR_Msk                                            /* Retry disable */
#define ETH_MACCFG_ACS_Pos                                          (7U)
#define ETH_MACCFG_ACS_Msk                                          (0x1UL << ETH_MACCFG_ACS_Pos)                                  /*!< 0x00000080 */
#define ETH_MACCFG_ACS                                              ETH_MACCFG_ACS_Msk                                             /* Automatic Pad/CRC stripping */
#define ETH_MACCFG_BL_Pos                                           (5U)
#define ETH_MACCFG_BL_Msk                                           (0x3UL << ETH_MACCFG_BL_Pos)                                   /*!< 0x00000060 */
#define ETH_MACCFG_BL                                               ETH_MACCFG_BL_Msk                                              /* Back-off limit: random integer number (r) of slot time delays before rescheduling
                                                       a transmission attempt during retries after a collision: 0 =< r <2^k */
#define ETH_MACCFG_BL_10                                            0x00000000U                                                    /* k = min (n, 10) */
#define ETH_MACCFG_BL_8                                             0x00000020U                                                    /* k = min (n, 8) */
#define ETH_MACCFG_BL_4                                             0x00000040U                                                    /* k = min (n, 4) */
#define ETH_MACCFG_BL_1                                             0x00000060U                                                    /* k = min (n, 1) */
#define ETH_MACCFG_DC_Pos                                           (4U)
#define ETH_MACCFG_DC_Msk                                           (0x1UL << ETH_MACCFG_DC_Pos)                                   /*!< 0x00000010 */
#define ETH_MACCFG_DC                                               ETH_MACCFG_DC_Msk                                              /* Defferal check */
#define ETH_MACCFG_TXEN_Pos                                         (3U)
#define ETH_MACCFG_TXEN_Msk                                         (0x1UL << ETH_MACCFG_TXEN_Pos)                                 /*!< 0x00000008 */
#define ETH_MACCFG_TXEN                                             ETH_MACCFG_TXEN_Msk                                            /* Transmitter enable */
#define ETH_MACCFG_RXEN_Pos                                         (2U)
#define ETH_MACCFG_RXEN_Msk                                         (0x1UL << ETH_MACCFG_RXEN_Pos)                                 /*!< 0x00000004 */
#define ETH_MACCFG_RXEN                                             ETH_MACCFG_RXEN_Msk                                            /* Receiver enable */

/* Bit definition for Ethernet MAC Frame Filter Register */
#define ETH_MACFRAF_RXA_Pos                                         (31U)
#define ETH_MACFRAF_RXA_Msk                                         (0x1UL << ETH_MACFRAF_RXA_Pos)                                 /*!< 0x80000000 */
#define ETH_MACFRAF_RXA                                             ETH_MACFRAF_RXA_Msk                                            /* Receive all */
#define ETH_MACFRAF_HPF_Pos                                         (10U)
#define ETH_MACFRAF_HPF_Msk                                         (0x1UL << ETH_MACFRAF_HPF_Pos)                                 /*!< 0x00000400 */
#define ETH_MACFRAF_HPF                                             ETH_MACFRAF_HPF_Msk                                            /* Hash or perfect filter */
#define ETH_MACFRAF_SAFEN_Pos                                       (9U)
#define ETH_MACFRAF_SAFEN_Msk                                       (0x1UL << ETH_MACFRAF_SAFEN_Pos)                               /*!< 0x00000200 */
#define ETH_MACFRAF_SAFEN                                           ETH_MACFRAF_SAFEN_Msk                                          /* Source address filter enable */
#define ETH_MACFRAF_SAIF_Pos                                        (8U)
#define ETH_MACFRAF_SAIF_Msk                                        (0x1UL << ETH_MACFRAF_SAIF_Pos)                                /*!< 0x00000100 */
#define ETH_MACFRAF_SAIF                                            ETH_MACFRAF_SAIF_Msk                                           /* SA inverse filtering */
#define ETH_MACFRAF_PCTRLF_Pos                                      (6U)
#define ETH_MACFRAF_PCTRLF_Msk                                      (0x3UL << ETH_MACFRAF_PCTRLF_Pos)                              /*!< 0x000000C0 */
#define ETH_MACFRAF_PCTRLF                                          ETH_MACFRAF_PCTRLF_Msk                                         /* Pass control frames: 3 cases */
#define ETH_MACFRAF_PCTRLF_BlockAll_Pos                             (6U)
#define ETH_MACFRAF_PCTRLF_BlockAll_Msk                             (0x1UL << ETH_MACFRAF_PCTRLF_BlockAll_Pos)                     /*!< 0x00000040 */
#define ETH_MACFRAF_PCTRLF_BlockAll                                 ETH_MACFRAF_PCTRLF_BlockAll_Msk                                /* MAC filters all control frames from reaching the application */
#define ETH_MACFRAF_PCTRLF_ForwardAll_Pos                           (7U)
#define ETH_MACFRAF_PCTRLF_ForwardAll_Msk                           (0x1UL << ETH_MACFRAF_PCTRLF_ForwardAll_Pos)                   /*!< 0x00000080 */
#define ETH_MACFRAF_PCTRLF_ForwardAll                               ETH_MACFRAF_PCTRLF_ForwardAll_Msk                              /* MAC forwards all control frames to application even if they fail the Address Filter */
#define ETH_MACFRAF_PCTRLF_ForwardPassedAddrFilter_Pos              (6U)
#define ETH_MACFRAF_PCTRLF_ForwardPassedAddrFilter_Msk              (0x3UL << ETH_MACFRAF_PCTRLF_ForwardPassedAddrFilter_Pos)      /*!< 0x000000C0 */
#define ETH_MACFRAF_PCTRLF_ForwardPassedAddrFilter                  ETH_MACFRAF_PCTRLF_ForwardPassedAddrFilter_Msk                 /* MAC forwards control frames that pass the Address Filter. */
#define ETH_MACFRAF_DISBF_Pos                                       (5U)
#define ETH_MACFRAF_DISBF_Msk                                       (0x1UL << ETH_MACFRAF_DISBF_Pos)                               /*!< 0x00000020 */
#define ETH_MACFRAF_DISBF                                           ETH_MACFRAF_DISBF_Msk                                          /* Broadcast frame disable */
#define ETH_MACFRAF_PM_Pos                                          (4U)
#define ETH_MACFRAF_PM_Msk                                          (0x1UL << ETH_MACFRAF_PM_Pos)                                  /*!< 0x00000010 */
#define ETH_MACFRAF_PM                                              ETH_MACFRAF_PM_Msk                                             /* Pass all mutlicast */
#define ETH_MACFRAF_DAIF_Pos                                        (3U)
#define ETH_MACFRAF_DAIF_Msk                                        (0x1UL << ETH_MACFRAF_DAIF_Pos)                                /*!< 0x00000008 */
#define ETH_MACFRAF_DAIF                                            ETH_MACFRAF_DAIF_Msk                                           /* DA Inverse filtering */
#define ETH_MACFRAF_HMC_Pos                                         (2U)
#define ETH_MACFRAF_HMC_Msk                                         (0x1UL << ETH_MACFRAF_HMC_Pos)                                 /*!< 0x00000004 */
#define ETH_MACFRAF_HMC                                             ETH_MACFRAF_HMC_Msk                                            /* Hash multicast */
#define ETH_MACFRAF_HUC_Pos                                         (1U)
#define ETH_MACFRAF_HUC_Msk                                         (0x1UL << ETH_MACFRAF_HUC_Pos)                                 /*!< 0x00000002 */
#define ETH_MACFRAF_HUC                                             ETH_MACFRAF_HUC_Msk                                            /* Hash unicast */
#define ETH_MACFRAF_PR_Pos                                          (0U)
#define ETH_MACFRAF_PR_Msk                                          (0x1UL << ETH_MACFRAF_PR_Pos)                                  /*!< 0x00000001 */
#define ETH_MACFRAF_PR                                              ETH_MACFRAF_PR_Msk                                             /* Promiscuous mode */

/* Bit definition for Ethernet MAC Hash Table High Register */
#define ETH_MACHTH_HTH_Pos                                          (0U)
#define ETH_MACHTH_HTH_Msk                                          (0xFFFFFFFFUL << ETH_MACHTH_HTH_Pos)                           /*!< 0xFFFFFFFF */
#define ETH_MACHTH_HTH                                              ETH_MACHTH_HTH_Msk                                             /* Hash table high */

/* Bit definition for Ethernet MAC Hash Table Low Register */
#define ETH_MACHTL_HTL_Pos                                          (0U)
#define ETH_MACHTL_HTL_Msk                                          (0xFFFFFFFFUL << ETH_MACHTL_HTL_Pos)                           /*!< 0xFFFFFFFF */
#define ETH_MACHTL_HTL                                              ETH_MACHTL_HTL_Msk                                             /* Hash table low */

/* Bit definition for Ethernet MAC MII Address Register */
#define ETH_MACADDR_PA_Pos                                          (11U)
#define ETH_MACADDR_PA_Msk                                          (0x1FUL << ETH_MACADDR_PA_Pos)                                 /*!< 0x0000F800 */
#define ETH_MACADDR_PA                                              ETH_MACADDR_PA_Msk                                             /* Physical layer address */
#define ETH_MACADDR_MR_Pos                                          (6U)
#define ETH_MACADDR_MR_Msk                                          (0x1FUL << ETH_MACADDR_MR_Pos)                                 /*!< 0x000007C0 */
#define ETH_MACADDR_MR                                              ETH_MACADDR_MR_Msk                                             /* MII register in the selected PHY */
#define ETH_MACADDR_CR_Pos                                          (2U)
#define ETH_MACADDR_CR_Msk                                          (0x7UL << ETH_MACADDR_CR_Pos)                                  /*!< 0x0000001C */
#define ETH_MACADDR_CR                                              ETH_MACADDR_CR_Msk                                             /* CR clock range: 6 cases */
#define ETH_MACADDR_CR_Div42                                        0x00000000U                                                    /* HCLK:60-100 MHz; MDC clock= HCLK/42   */
#define ETH_MACADDR_CR_Div62_Pos                                    (2U)
#define ETH_MACADDR_CR_Div62_Msk                                    (0x1UL << ETH_MACADDR_CR_Div62_Pos)                            /*!< 0x00000004 */
#define ETH_MACADDR_CR_Div62                                        ETH_MACADDR_CR_Div62_Msk                                       /* HCLK:100-150 MHz; MDC clock= HCLK/62  */
#define ETH_MACADDR_CR_Div16_Pos                                    (3U)
#define ETH_MACADDR_CR_Div16_Msk                                    (0x1UL << ETH_MACADDR_CR_Div16_Pos)                            /*!< 0x00000008 */
#define ETH_MACADDR_CR_Div16                                        ETH_MACADDR_CR_Div16_Msk                                       /* HCLK:20-35 MHz; MDC clock= HCLK/16    */
#define ETH_MACADDR_CR_Div26_Pos                                    (2U)
#define ETH_MACADDR_CR_Div26_Msk                                    (0x3UL << ETH_MACADDR_CR_Div26_Pos)                            /*!< 0x0000000C */
#define ETH_MACADDR_CR_Div26                                        ETH_MACADDR_CR_Div26_Msk                                       /* HCLK:35-60 MHz; MDC clock= HCLK/26    */
#define ETH_MACADDR_CR_Div102_Pos                                   (4U)
#define ETH_MACADDR_CR_Div102_Msk                                   (0x1UL << ETH_MACADDR_CR_Div102_Pos)                           /*!< 0x00000010 */
#define ETH_MACADDR_CR_Div102                                       ETH_MACADDR_CR_Div102_Msk                                      /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
#define ETH_MACADDR_MW_Pos                                          (1U)
#define ETH_MACADDR_MW_Msk                                          (0x1UL << ETH_MACADDR_MW_Pos)                                  /*!< 0x00000002 */
#define ETH_MACADDR_MW                                              ETH_MACADDR_MW_Msk                                             /* MII write */
#define ETH_MACADDR_MB_Pos                                          (0U)
#define ETH_MACADDR_MB_Msk                                          (0x1UL << ETH_MACADDR_MB_Pos)                                  /*!< 0x00000001 */
#define ETH_MACADDR_MB                                              ETH_MACADDR_MB_Msk                                             /* MII busy  */

/* Bit definition for Ethernet MAC MII Data Register */
#define ETH_MACDATA_MD_Pos                                          (0U)
#define ETH_MACDATA_MD_Msk                                          (0xFFFFUL << ETH_MACDATA_MD_Pos)                               /*!< 0x0000FFFF */
#define ETH_MACDATA_MD                                              ETH_MACDATA_MD_Msk                                             /* MII data: read/write data from/to PHY */

/* Bit definition for Ethernet MAC Flow Control Register */
#define ETH_MACFCTRL_PT_Pos                                         (16U)
#define ETH_MACFCTRL_PT_Msk                                         (0xFFFFUL << ETH_MACFCTRL_PT_Pos)                              /*!< 0xFFFF0000 */
#define ETH_MACFCTRL_PT                                             ETH_MACFCTRL_PT_Msk                                            /* Pause time */
#define ETH_MACFCTRL_ZQPDIS_Pos                                     (7U)
#define ETH_MACFCTRL_ZQPDIS_Msk                                     (0x1UL << ETH_MACFCTRL_ZQPDIS_Pos)                             /*!< 0x00000080 */
#define ETH_MACFCTRL_ZQPDIS                                         ETH_MACFCTRL_ZQPDIS_Msk                                        /* Zero-quanta pause disable */
#define ETH_MACFCTRL_PTSEL_Pos                                      (4U)
#define ETH_MACFCTRL_PTSEL_Msk                                      (0x3UL << ETH_MACFCTRL_PTSEL_Pos)                              /*!< 0x00000030 */
#define ETH_MACFCTRL_PTSEL                                          ETH_MACFCTRL_PTSEL_Msk                                         /* Pause low threshold: 4 cases */
#define ETH_MACFCTRL_PTSEL_Minus4                                   0x00000000U                                                    /* Pause time minus 4 slot times   */
#define ETH_MACFCTRL_PTSEL_Minus28_Pos                              (4U)
#define ETH_MACFCTRL_PTSEL_Minus28_Msk                              (0x1UL << ETH_MACFCTRL_PTSEL_Minus28_Pos)                      /*!< 0x00000010 */
#define ETH_MACFCTRL_PTSEL_Minus28                                  ETH_MACFCTRL_PTSEL_Minus28_Msk                                 /* Pause time minus 28 slot times  */
#define ETH_MACFCTRL_PTSEL_Minus144_Pos                             (5U)
#define ETH_MACFCTRL_PTSEL_Minus144_Msk                             (0x1UL << ETH_MACFCTRL_PTSEL_Minus144_Pos)                     /*!< 0x00000020 */
#define ETH_MACFCTRL_PTSEL_Minus144                                 ETH_MACFCTRL_PTSEL_Minus144_Msk                                /* Pause time minus 144 slot times */
#define ETH_MACFCTRL_PTSEL_Minus256_Pos                             (4U)
#define ETH_MACFCTRL_PTSEL_Minus256_Msk                             (0x3UL << ETH_MACFCTRL_PTSEL_Minus256_Pos)                     /*!< 0x00000030 */
#define ETH_MACFCTRL_PTSEL_Minus256                                 ETH_MACFCTRL_PTSEL_Minus256_Msk                                /* Pause time minus 256 slot times */
#define ETH_MACFCTRL_UNPFDETE_Pos                                   (3U)
#define ETH_MACFCTRL_UNPFDETE_Msk                                   (0x1UL << ETH_MACFCTRL_UNPFDETE_Pos)                           /*!< 0x00000008 */
#define ETH_MACFCTRL_UNPFDETE                                       ETH_MACFCTRL_UNPFDETE_Msk                                      /* Unicast pause frame detect */
#define ETH_MACFCTRL_RXFCTRLEN_Pos                                  (2U)
#define ETH_MACFCTRL_RXFCTRLEN_Msk                                  (0x1UL << ETH_MACFCTRL_RXFCTRLEN_Pos)                          /*!< 0x00000004 */
#define ETH_MACFCTRL_RXFCTRLEN                                      ETH_MACFCTRL_RXFCTRLEN_Msk                                     /* Receive flow control enable */
#define ETH_MACFCTRL_TXFCTRLEN_Pos                                  (1U)
#define ETH_MACFCTRL_TXFCTRLEN_Msk                                  (0x1UL << ETH_MACFCTRL_TXFCTRLEN_Pos)                          /*!< 0x00000002 */
#define ETH_MACFCTRL_TXFCTRLEN                                      ETH_MACFCTRL_TXFCTRLEN_Msk                                     /* Transmit flow control enable */
#define ETH_MACFCTRL_FCTRLB_BPA_Pos                                 (0U)
#define ETH_MACFCTRL_FCTRLB_BPA_Msk                                 (0x1UL << ETH_MACFCTRL_FCTRLB_BPA_Pos)                         /*!< 0x00000001 */
#define ETH_MACFCTRL_FCTRLB_BPA                                     ETH_MACFCTRL_FCTRLB_BPA_Msk                                    /* Flow control busy/backpressure activate */

/* Bit definition for Ethernet MAC VLAN Tag Register */
#define ETH_MACVLANT_VLANTCOMP_Pos                                  (16U)
#define ETH_MACVLANT_VLANTCOMP_Msk                                  (0x1UL << ETH_MACVLANT_VLANTCOMP_Pos)                          /*!< 0x00010000 */
#define ETH_MACVLANT_VLANTCOMP                                      ETH_MACVLANT_VLANTCOMP_Msk                                     /* 12-bit VLAN tag comparison */
#define ETH_MACVLANT_VLANTID_Pos                                    (0U)
#define ETH_MACVLANT_VLANTID_Msk                                    (0xFFFFUL << ETH_MACVLANT_VLANTID_Pos)                         /*!< 0x0000FFFF */
#define ETH_MACVLANT_VLANTID                                        ETH_MACVLANT_VLANTID_Msk                                       /* VLAN tag identifier (for receive frames) */

/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */ 
#define ETH_MACREMWKUPFFL_FLXBMASK_Pos                              (0U)
#define ETH_MACREMWKUPFFL_FLXBMASK_Msk                              (0xFFFFFFFFUL << ETH_MACREMWKUPFFL_FLXBMASK_Pos)               /*!< 0xFFFFFFFF */
#define ETH_MACREMWKUPFFL_FLXBMASK                                  ETH_MACREMWKUPFFL_FLXBMASK_Msk                                 /* Wake-up frame filter register data */
/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
   Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
   Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
   Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
   Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
   Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command - 
                              RSVD - Filter1 Command - RSVD - Filter0 Command
   Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
   Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
   Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */

/* Bit definition for Ethernet MAC PMT Control and Status Register */ 
#define ETH_MACPMTCTRLSTS_WKUPFRST_Pos                              (31U)
#define ETH_MACPMTCTRLSTS_WKUPFRST_Msk                              (0x1UL << ETH_MACPMTCTRLSTS_WKUPFRST_Pos)                      /*!< 0x80000000 */
#define ETH_MACPMTCTRLSTS_WKUPFRST                                  ETH_MACPMTCTRLSTS_WKUPFRST_Msk                                 /* Wake-Up Frame Filter Register Pointer Reset */
#define ETH_MACPMTCTRLSTS_GUN_Pos                                   (9U)
#define ETH_MACPMTCTRLSTS_GUN_Msk                                   (0x1UL << ETH_MACPMTCTRLSTS_GUN_Pos)                           /*!< 0x00000200 */
#define ETH_MACPMTCTRLSTS_GUN                                       ETH_MACPMTCTRLSTS_GUN_Msk                                      /* Global Unicast                              */
#define ETH_MACPMTCTRLSTS_WKUPFRX_Pos                               (6U)
#define ETH_MACPMTCTRLSTS_WKUPFRX_Msk                               (0x1UL << ETH_MACPMTCTRLSTS_WKUPFRX_Pos)                       /*!< 0x00000040 */
#define ETH_MACPMTCTRLSTS_WKUPFRX                                   ETH_MACPMTCTRLSTS_WKUPFRX_Msk                                  /* Wake-Up Frame Received                      */
#define ETH_MACPMTCTRLSTS_MPRX_Pos                                  (5U)
#define ETH_MACPMTCTRLSTS_MPRX_Msk                                  (0x1UL << ETH_MACPMTCTRLSTS_MPRX_Pos)                          /*!< 0x00000020 */
#define ETH_MACPMTCTRLSTS_MPRX                                      ETH_MACPMTCTRLSTS_MPRX_Msk                                     /* Magic Packet Received                       */
#define ETH_MACPMTCTRLSTS_WKUPFEN_Pos                               (2U)
#define ETH_MACPMTCTRLSTS_WKUPFEN_Msk                               (0x1UL << ETH_MACPMTCTRLSTS_WKUPFEN_Pos)                       /*!< 0x00000004 */
#define ETH_MACPMTCTRLSTS_WKUPFEN                                   ETH_MACPMTCTRLSTS_WKUPFEN_Msk                                  /* Wake-Up Frame Enable                        */
#define ETH_MACPMTCTRLSTS_MPEN_Pos                                  (1U)
#define ETH_MACPMTCTRLSTS_MPEN_Msk                                  (0x1UL << ETH_MACPMTCTRLSTS_MPEN_Pos)                          /*!< 0x00000002 */
#define ETH_MACPMTCTRLSTS_MPEN                                      ETH_MACPMTCTRLSTS_MPEN_Msk                                     /* Magic Packet Enable                         */
#define ETH_MACPMTCTRLSTS_PD_Pos                                    (0U)
#define ETH_MACPMTCTRLSTS_PD_Msk                                    (0x1UL << ETH_MACPMTCTRLSTS_PD_Pos)                            /*!< 0x00000001 */
#define ETH_MACPMTCTRLSTS_PD                                        ETH_MACPMTCTRLSTS_PD_Msk                                       /* Power Down                                  */

/* Bit definition for Ethernet MAC debug Register */
#define ETH_MACDBG_TXSTSFSTS_Pos                                    (25U)
#define ETH_MACDBG_TXSTSFSTS_Msk                                    (0x1UL << ETH_MACDBG_TXSTSFSTS_Pos)                            /*!< 0x02000000 */
#define ETH_MACDBG_TXSTSFSTS                                        ETH_MACDBG_TXSTSFSTS_Msk                                       /* Tx FIFO full                                                            */
#define ETH_MACDBG_TXFSTS_Pos                                       (24U)
#define ETH_MACDBG_TXFSTS_Msk                                       (0x1UL << ETH_MACDBG_TXFSTS_Pos)                               /*!< 0x01000000 */
#define ETH_MACDBG_TXFSTS                                           ETH_MACDBG_TXFSTS_Msk                                          /* Tx FIFO not empty                                                       */
#define ETH_MACDBG_TWCSTS_Pos                                       (22U)
#define ETH_MACDBG_TWCSTS_Msk                                       (0x1UL << ETH_MACDBG_TWCSTS_Pos)                               /*!< 0x00400000 */
#define ETH_MACDBG_TWCSTS                                           ETH_MACDBG_TWCSTS_Msk                                          /* Tx FIFO write active                                                    */
#define ETH_MACDBG_TRCSTS_Pos                                       (20U)
#define ETH_MACDBG_TRCSTS_Msk                                       (0x3UL << ETH_MACDBG_TRCSTS_Pos)                               /*!< 0x00300000 */
#define ETH_MACDBG_TRCSTS                                           ETH_MACDBG_TRCSTS_Msk                                          /* Tx FIFO read status mask                                                */
#define ETH_MACDBG_TRCSTS_WRITING_Pos                               (20U)
#define ETH_MACDBG_TRCSTS_WRITING_Msk                               (0x3UL << ETH_MACDBG_TRCSTS_WRITING_Pos)                       /*!< 0x00300000 */
#define ETH_MACDBG_TRCSTS_WRITING                                   ETH_MACDBG_TRCSTS_WRITING_Msk                                  /* Writing the received TxStatus or flushing the TxFIFO                    */
#define ETH_MACDBG_TRCSTS_WAITING_Pos                               (21U)
#define ETH_MACDBG_TRCSTS_WAITING_Msk                               (0x1UL << ETH_MACDBG_TRCSTS_WAITING_Pos)                       /*!< 0x00200000 */
#define ETH_MACDBG_TRCSTS_WAITING                                   ETH_MACDBG_TRCSTS_WAITING_Msk                                  /* Waiting for TxStatus from MAC transmitter                               */
#define ETH_MACDBG_TRCSTS_READ_Pos                                  (20U)
#define ETH_MACDBG_TRCSTS_READ_Msk                                  (0x1UL << ETH_MACDBG_TRCSTS_READ_Pos)                          /*!< 0x00100000 */
#define ETH_MACDBG_TRCSTS_READ                                      ETH_MACDBG_TRCSTS_READ_Msk                                     /* Read state (transferring data to the MAC transmitter)                   */
#define ETH_MACDBG_TRCSTS_IDLE                                      0x00000000U                                                    /* Idle state                                                              */
#define ETH_MACDBG_TXPAUSED_Pos                                     (19U)
#define ETH_MACDBG_TXPAUSED_Msk                                     (0x1UL << ETH_MACDBG_TXPAUSED_Pos)                             /*!< 0x00080000 */
#define ETH_MACDBG_TXPAUSED                                         ETH_MACDBG_TXPAUSED_Msk                                        /* MAC transmitter in pause                                                */
#define ETH_MACDBG_TFCSTS_Pos                                       (17U)
#define ETH_MACDBG_TFCSTS_Msk                                       (0x3UL << ETH_MACDBG_TFCSTS_Pos)                               /*!< 0x00060000 */
#define ETH_MACDBG_TFCSTS                                           ETH_MACDBG_TFCSTS_Msk                                          /* MAC transmit frame controller status mask                               */
#define ETH_MACDBG_TFCSTS_TRANSFERRING_Pos                          (17U)
#define ETH_MACDBG_TFCSTS_TRANSFERRING_Msk                          (0x3UL << ETH_MACDBG_TFCSTS_TRANSFERRING_Pos)                  /*!< 0x00060000 */
#define ETH_MACDBG_TFCSTS_TRANSFERRING                              ETH_MACDBG_TFCSTS_TRANSFERRING_Msk                             /* Transferring input frame for transmission                               */
#define ETH_MACDBG_TFCSTS_GENERATINGPCF_Pos                         (18U)
#define ETH_MACDBG_TFCSTS_GENERATINGPCF_Msk                         (0x1UL << ETH_MACDBG_TFCSTS_GENERATINGPCF_Pos)                 /*!< 0x00040000 */
#define ETH_MACDBG_TFCSTS_GENERATINGPCF                             ETH_MACDBG_TFCSTS_GENERATINGPCF_Msk                            /* Generating and transmitting a Pause control frame (in full duplex mode) */
#define ETH_MACDBG_TFCSTS_WAITING_Pos                               (17U)
#define ETH_MACDBG_TFCSTS_WAITING_Msk                               (0x1UL << ETH_MACDBG_TFCSTS_WAITING_Pos)                       /*!< 0x00020000 */
#define ETH_MACDBG_TFCSTS_WAITING                                   ETH_MACDBG_TFCSTS_WAITING_Msk                                  /* Waiting for Status of previous frame or IFG/backoff period to be over   */
#define ETH_MACDBG_TFCSTS_IDLE                                      0x00000000U                                                    /* Idle                                                                    */
#define ETH_MACDBG_TPESTS_Pos                                       (16U)
#define ETH_MACDBG_TPESTS_Msk                                       (0x1UL << ETH_MACDBG_TPESTS_Pos)                               /*!< 0x00010000 */
#define ETH_MACDBG_TPESTS                                           ETH_MACDBG_TPESTS_Msk                                          /* MAC MII transmit engine active                                          */
#define ETH_MACDBG_RXFSTS_Pos                                       (8U)
#define ETH_MACDBG_RXFSTS_Msk                                       (0x3UL << ETH_MACDBG_RXFSTS_Pos)                               /*!< 0x00000300 */
#define ETH_MACDBG_RXFSTS                                           ETH_MACDBG_RXFSTS_Msk                                          /* Rx FIFO fill level mask                                                 */
#define ETH_MACDBG_RXFSTS_FULL_Pos                                  (8U)
#define ETH_MACDBG_RXFSTS_FULL_Msk                                  (0x3UL << ETH_MACDBG_RXFSTS_FULL_Pos)                          /*!< 0x00000300 */
#define ETH_MACDBG_RXFSTS_FULL                                      ETH_MACDBG_RXFSTS_FULL_Msk                                     /* RxFIFO full                                                             */
#define ETH_MACDBG_RXFSTS_ABOVEFCT_Pos                              (9U)
#define ETH_MACDBG_RXFSTS_ABOVEFCT_Msk                              (0x1UL << ETH_MACDBG_RXFSTS_ABOVEFCT_Pos)                      /*!< 0x00000200 */
#define ETH_MACDBG_RXFSTS_ABOVEFCT                                  ETH_MACDBG_RXFSTS_ABOVEFCT_Msk                                 /* RxFIFO fill-level above flow-control activate threshold                 */
#define ETH_MACDBG_RXFSTS_BELOWFCT_Pos                              (8U)
#define ETH_MACDBG_RXFSTS_BELOWFCT_Msk                              (0x1UL << ETH_MACDBG_RXFSTS_BELOWFCT_Pos)                      /*!< 0x00000100 */
#define ETH_MACDBG_RXFSTS_BELOWFCT                                  ETH_MACDBG_RXFSTS_BELOWFCT_Msk                                 /* RxFIFO fill-level below flow-control de-activate threshold              */
#define ETH_MACDBG_RXFSTS_EMPTY                                     0x00000000U                                                    /* RxFIFO empty                                                            */
#define ETH_MACDBG_RRCSTS_Pos                                       (5U)
#define ETH_MACDBG_RRCSTS_Msk                                       (0x3UL << ETH_MACDBG_RRCSTS_Pos)                               /*!< 0x00000060 */
#define ETH_MACDBG_RRCSTS                                           ETH_MACDBG_RRCSTS_Msk                                          /* Rx FIFO read controller status mask                                     */
#define ETH_MACDBG_RRCSTS_FLUSHING_Pos                              (5U)
#define ETH_MACDBG_RRCSTS_FLUSHING_Msk                              (0x3UL << ETH_MACDBG_RRCSTS_FLUSHING_Pos)                      /*!< 0x00000060 */
#define ETH_MACDBG_RRCSTS_FLUSHING                                  ETH_MACDBG_RRCSTS_FLUSHING_Msk                                 /* Flushing the frame data and status                                      */
#define ETH_MACDBG_RRCSTS_STATUSREADING_Pos                         (6U)
#define ETH_MACDBG_RRCSTS_STATUSREADING_Msk                         (0x1UL << ETH_MACDBG_RRCSTS_STATUSREADING_Pos)                 /*!< 0x00000040 */
#define ETH_MACDBG_RRCSTS_STATUSREADING                             ETH_MACDBG_RRCSTS_STATUSREADING_Msk                            /* Reading frame status (or time-stamp)                                    */
#define ETH_MACDBG_RRCSTS_DATAREADING_Pos                           (5U)
#define ETH_MACDBG_RRCSTS_DATAREADING_Msk                           (0x1UL << ETH_MACDBG_RRCSTS_DATAREADING_Pos)                   /*!< 0x00000020 */
#define ETH_MACDBG_RRCSTS_DATAREADING                               ETH_MACDBG_RRCSTS_DATAREADING_Msk                              /* Reading frame data                                                      */
#define ETH_MACDBG_RRCSTS_IDLE                                      0x00000000U                                                    /* IDLE state                                                              */
#define ETH_MACDBG_RWCSTS_Pos                                       (4U)
#define ETH_MACDBG_RWCSTS_Msk                                       (0x1UL << ETH_MACDBG_RWCSTS_Pos)                               /*!< 0x00000010 */
#define ETH_MACDBG_RWCSTS                                           ETH_MACDBG_RWCSTS_Msk                                          /* Rx FIFO write controller active                                         */
#define ETH_MACDBG_RFCFCSTS_Pos                                     (1U)
#define ETH_MACDBG_RFCFCSTS_Msk                                     (0x3UL << ETH_MACDBG_RFCFCSTS_Pos)                             /*!< 0x00000006 */
#define ETH_MACDBG_RFCFCSTS                                         ETH_MACDBG_RFCFCSTS_Msk                                        /* MAC small FIFO read / write controllers status  mask                    */
#define ETH_MACDBG_RFCFCSTS_1                                       (0x2UL << ETH_MACDBG_RFCFCSTS_Pos)                             /*!< 0x00000004 */
#define ETH_MACDBG_RFCFCSTS_0                                       (0x1UL << ETH_MACDBG_RFCFCSTS_Pos)                             /*!< 0x00000002 */
#define ETH_MACDBG_RPESTS_Pos                                       (0U)
#define ETH_MACDBG_RPESTS_Msk                                       (0x1UL << ETH_MACDBG_RPESTS_Pos)                               /*!< 0x00000001 */
#define ETH_MACDBG_RPESTS                                           ETH_MACDBG_RPESTS_Msk                                          /* MAC MII receive protocol engine active                                  */

/* Bit definition for Ethernet MAC Status Register */
#define ETH_MACISTS_TSTS_Pos                                        (9U)
#define ETH_MACISTS_TSTS_Msk                                        (0x1UL << ETH_MACISTS_TSTS_Pos)                                /*!< 0x00000200 */
#define ETH_MACISTS_TSTS                                            ETH_MACISTS_TSTS_Msk                                           /* Time stamp trigger status */
#define ETH_MACISTS_MMCTXIS_Pos                                     (6U)
#define ETH_MACISTS_MMCTXIS_Msk                                     (0x1UL << ETH_MACISTS_MMCTXIS_Pos)                             /*!< 0x00000040 */
#define ETH_MACISTS_MMCTXIS                                         ETH_MACISTS_MMCTXIS_Msk                                        /* MMC transmit status       */
#define ETH_MACISTS_MMCRXIS_Pos                                     (5U)
#define ETH_MACISTS_MMCRXIS_Msk                                     (0x1UL << ETH_MACISTS_MMCRXIS_Pos)                             /*!< 0x00000020 */
#define ETH_MACISTS_MMCRXIS                                         ETH_MACISTS_MMCRXIS_Msk                                        /* MMC receive status        */
#define ETH_MACISTS_MMCIS_Pos                                       (4U)
#define ETH_MACISTS_MMCIS_Msk                                       (0x1UL << ETH_MACISTS_MMCIS_Pos)                               /*!< 0x00000010 */
#define ETH_MACISTS_MMCIS                                           ETH_MACISTS_MMCIS_Msk                                          /* MMC status                */
#define ETH_MACISTS_PMTIS_Pos                                       (3U)
#define ETH_MACISTS_PMTIS_Msk                                       (0x1UL << ETH_MACISTS_PMTIS_Pos)                               /*!< 0x00000008 */
#define ETH_MACISTS_PMTIS                                           ETH_MACISTS_PMTIS_Msk                                          /* PMT status                */

/* Bit definition for Ethernet MAC Interrupt Mask Register */
#define ETH_MACIMASK_TSTIM_Pos                                      (9U)
#define ETH_MACIMASK_TSTIM_Msk                                      (0x1UL << ETH_MACIMASK_TSTIM_Pos)                              /*!< 0x00000200 */
#define ETH_MACIMASK_TSTIM                                          ETH_MACIMASK_TSTIM_Msk                                         /* Time stamp trigger interrupt mask */
#define ETH_MACIMASK_PMTIM_Pos                                      (3U)
#define ETH_MACIMASK_PMTIM_Msk                                      (0x1UL << ETH_MACIMASK_PMTIM_Pos)                              /*!< 0x00000008 */
#define ETH_MACIMASK_PMTIM                                          ETH_MACIMASK_PMTIM_Msk                                         /* PMT interrupt mask                */

/* Bit definition for Ethernet MAC Address0 High Register */
#define ETH_MACADDR0H_ADDR0H_Pos                                    (0U)
#define ETH_MACADDR0H_ADDR0H_Msk                                    (0xFFFFUL << ETH_MACADDR0H_ADDR0H_Pos)                         /*!< 0x0000FFFF */
#define ETH_MACADDR0H_ADDR0H                                        ETH_MACADDR0H_ADDR0H_Msk                                       /* MAC address0 high */

/* Bit definition for Ethernet MAC Address0 Low Register */
#define ETH_MACADDR0L_ADDR0L_Pos                                    (0U)
#define ETH_MACADDR0L_ADDR0L_Msk                                    (0xFFFFFFFFUL << ETH_MACADDR0L_ADDR0L_Pos)                     /*!< 0xFFFFFFFF */
#define ETH_MACADDR0L_ADDR0L                                        ETH_MACADDR0L_ADDR0L_Msk                                       /* MAC address0 low */

/* Bit definition for Ethernet MAC Address1 High Register */
#define ETH_MACADDR1H_ADDREN_Pos                                    (31U)
#define ETH_MACADDR1H_ADDREN_Msk                                    (0x1UL << ETH_MACADDR1H_ADDREN_Pos)                            /*!< 0x80000000 */
#define ETH_MACADDR1H_ADDREN                                        ETH_MACADDR1H_ADDREN_Msk                                       /* Address enable */
#define ETH_MACADDR1H_ADDRSEL_Pos                                   (30U)
#define ETH_MACADDR1H_ADDRSEL_Msk                                   (0x1UL << ETH_MACADDR1H_ADDRSEL_Pos)                           /*!< 0x40000000 */
#define ETH_MACADDR1H_ADDRSEL                                       ETH_MACADDR1H_ADDRSEL_Msk                                      /* Source address */
#define ETH_MACADDR1H_MASKBCTRL_Pos                                 (24U)
#define ETH_MACADDR1H_MASKBCTRL_Msk                                 (0x3FUL << ETH_MACADDR1H_MASKBCTRL_Pos)                        /*!< 0x3F000000 */
#define ETH_MACADDR1H_MASKBCTRL                                     ETH_MACADDR1H_MASKBCTRL_Msk                                    /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
#define ETH_MACADDR1H_MASKBCTRL_HBits15_8                           0x20000000U                                                    /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACADDR1H_MASKBCTRL_HBits7_0                            0x10000000U                                                    /* Mask MAC Address high reg bits [7:0]  */
#define ETH_MACADDR1H_MASKBCTRL_LBits31_24                          0x08000000U                                                    /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACADDR1H_MASKBCTRL_LBits23_16                          0x04000000U                                                    /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACADDR1H_MASKBCTRL_LBits15_8                           0x02000000U                                                    /* Mask MAC Address low reg bits [15:8]  */
#define ETH_MACADDR1H_MASKBCTRL_LBits7_0                            0x01000000U                                                    /* Mask MAC Address low reg bits [7:0]   */
#define ETH_MACADDR1H_ADDR1H_Pos                                    (0U)
#define ETH_MACADDR1H_ADDR1H_Msk                                    (0xFFFFUL << ETH_MACADDR1H_ADDR1H_Pos)                         /*!< 0x0000FFFF */
#define ETH_MACADDR1H_ADDR1H                                        ETH_MACADDR1H_ADDR1H_Msk                                       /* MAC address1 high */

/* Bit definition for Ethernet MAC Address1 Low Register */
#define ETH_MACADDR1L_ADDR1L_Pos                                    (0U)
#define ETH_MACADDR1L_ADDR1L_Msk                                    (0xFFFFFFFFUL << ETH_MACADDR1L_ADDR1L_Pos)                     /*!< 0xFFFFFFFF */
#define ETH_MACADDR1L_ADDR1L                                        ETH_MACADDR1L_ADDR1L_Msk                                       /* MAC address1 low */

/* Bit definition for Ethernet MAC Address2 High Register */
#define ETH_MACADDR2H_ADDREN_Pos                                    (31U)
#define ETH_MACADDR2H_ADDREN_Msk                                    (0x1UL << ETH_MACADDR2H_ADDREN_Pos)                            /*!< 0x80000000 */
#define ETH_MACADDR2H_ADDREN                                        ETH_MACADDR2H_ADDREN_Msk                                       /* Address enable */
#define ETH_MACADDR2H_ADDRSEL_Pos                                   (30U)
#define ETH_MACADDR2H_ADDRSEL_Msk                                   (0x1UL << ETH_MACADDR2H_ADDRSEL_Pos)                           /*!< 0x40000000 */
#define ETH_MACADDR2H_ADDRSEL                                       ETH_MACADDR2H_ADDRSEL_Msk                                      /* Source address */
#define ETH_MACADDR2H_MASKBCTRL_Pos                                 (24U)
#define ETH_MACADDR2H_MASKBCTRL_Msk                                 (0x3FUL << ETH_MACADDR2H_MASKBCTRL_Pos)                        /*!< 0x3F000000 */
#define ETH_MACADDR2H_MASKBCTRL                                     ETH_MACADDR2H_MASKBCTRL_Msk                                    /* Mask byte control */
#define ETH_MACADDR2H_MASKBCTRL_HBits15_8                           0x20000000U                                                    /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACADDR2H_MASKBCTRL_HBits7_0                            0x10000000U                                                    /* Mask MAC Address high reg bits [7:0]  */
#define ETH_MACADDR2H_MASKBCTRL_LBits31_24                          0x08000000U                                                    /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACADDR2H_MASKBCTRL_LBits23_16                          0x04000000U                                                    /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACADDR2H_MASKBCTRL_LBits15_8                           0x02000000U                                                    /* Mask MAC Address low reg bits [15:8]  */
#define ETH_MACADDR2H_MASKBCTRL_LBits7_0                            0x01000000U                                                    /* Mask MAC Address low reg bits [70]    */
#define ETH_MACADDR2H_ADDR2H_Pos                                    (0U)
#define ETH_MACADDR2H_ADDR2H_Msk                                    (0xFFFFUL << ETH_MACADDR2H_ADDR2H_Pos)                         /*!< 0x0000FFFF */
#define ETH_MACADDR2H_ADDR2H                                        ETH_MACADDR2H_ADDR2H_Msk                                       /* MAC address1 high */

/* Bit definition for Ethernet MAC Address2 Low Register */
#define ETH_MACADDR2L_ADDR2L_Pos                                    (0U)
#define ETH_MACADDR2L_ADDR2L_Msk                                    (0xFFFFFFFFUL << ETH_MACADDR2L_ADDR2L_Pos)                     /*!< 0xFFFFFFFF */
#define ETH_MACADDR2L_ADDR2L                                        ETH_MACADDR2L_ADDR2L_Msk                                       /* MAC address2 low */

/* Bit definition for Ethernet MAC Address3 High Register */
#define ETH_MACADDR3H_ADDREN_Pos                                    (31U)
#define ETH_MACADDR3H_ADDREN_Msk                                    (0x1UL << ETH_MACADDR3H_ADDREN_Pos)                            /*!< 0x80000000 */
#define ETH_MACADDR3H_ADDREN                                        ETH_MACADDR3H_ADDREN_Msk                                       /* Address enable */
#define ETH_MACADDR3H_ADDRSEL_Pos                                   (30U)
#define ETH_MACADDR3H_ADDRSEL_Msk                                   (0x1UL << ETH_MACADDR3H_ADDRSEL_Pos)                           /*!< 0x40000000 */
#define ETH_MACADDR3H_ADDRSEL                                       ETH_MACADDR3H_ADDRSEL_Msk                                      /* Source address */
#define ETH_MACADDR3H_MASKBCTRL_Pos                                 (24U)
#define ETH_MACADDR3H_MASKBCTRL_Msk                                 (0x3FUL << ETH_MACADDR3H_MASKBCTRL_Pos)                        /*!< 0x3F000000 */
#define ETH_MACADDR3H_MASKBCTRL                                     ETH_MACADDR3H_MASKBCTRL_Msk                                    /* Mask byte control */
#define ETH_MACADDR3H_MASKBCTRL_HBits15_8                           0x20000000U                                                    /* Mask MAC Address high reg bits [15:8] */
#define ETH_MACADDR3H_MASKBCTRL_HBits7_0                            0x10000000U                                                    /* Mask MAC Address high reg bits [7:0]  */
#define ETH_MACADDR3H_MASKBCTRL_LBits31_24                          0x08000000U                                                    /* Mask MAC Address low reg bits [31:24] */
#define ETH_MACADDR3H_MASKBCTRL_LBits23_16                          0x04000000U                                                    /* Mask MAC Address low reg bits [23:16] */
#define ETH_MACADDR3H_MASKBCTRL_LBits15_8                           0x02000000U                                                    /* Mask MAC Address low reg bits [15:8]  */
#define ETH_MACADDR3H_MASKBCTRL_LBits7_0                            0x01000000U                                                    /* Mask MAC Address low reg bits [70]    */
#define ETH_MACADDR3H_ADDR3H_Pos                                    (0U)
#define ETH_MACADDR3H_ADDR3H_Msk                                    (0xFFFFUL << ETH_MACADDR3H_ADDR3H_Pos)                         /*!< 0x0000FFFF */
#define ETH_MACADDR3H_ADDR3H                                        ETH_MACADDR3H_ADDR3H_Msk                                       /* MAC address3 high */

/* Bit definition for Ethernet MAC Address3 Low Register */
#define ETH_MACADDR3L_ADDR3L_Pos                                    (0U)
#define ETH_MACADDR3L_ADDR3L_Msk                                    (0xFFFFFFFFUL << ETH_MACADDR3L_ADDR3L_Pos)                     /*!< 0xFFFFFFFF */
#define ETH_MACADDR3L_ADDR3L                                        ETH_MACADDR3L_ADDR3L_Msk                                       /* MAC address3 low */

/******************************************************************************/
/*                Ethernet MMC Registers bits definition                      */
/******************************************************************************/

/* Bit definition for Ethernet MMC Control Register */
#define ETH_MMCCTRL_MCNTVALP_Pos                                    (5U)
#define ETH_MMCCTRL_MCNTVALP_Msk                                    (0x1UL << ETH_MMCCTRL_MCNTVALP_Pos)                            /*!< 0x00000020 */
#define ETH_MMCCTRL_MCNTVALP                                        ETH_MMCCTRL_MCNTVALP_Msk                                       /* MMC counter Full-Half preset */
#define ETH_MMCCTRL_MCNTP_Pos                                       (4U)
#define ETH_MMCCTRL_MCNTP_Msk                                       (0x1UL << ETH_MMCCTRL_MCNTP_Pos)                               /*!< 0x00000010 */
#define ETH_MMCCTRL_MCNTP                                           ETH_MMCCTRL_MCNTP_Msk                                          /* MMC counter preset           */
#define ETH_MMCCTRL_MCNTF_Pos                                       (3U)
#define ETH_MMCCTRL_MCNTF_Msk                                       (0x1UL << ETH_MMCCTRL_MCNTF_Pos)                               /*!< 0x00000008 */
#define ETH_MMCCTRL_MCNTF                                           ETH_MMCCTRL_MCNTF_Msk                                          /* MMC Counter Freeze           */
#define ETH_MMCCTRL_RSTOR_Pos                                       (2U)
#define ETH_MMCCTRL_RSTOR_Msk                                       (0x1UL << ETH_MMCCTRL_RSTOR_Pos)                               /*!< 0x00000004 */
#define ETH_MMCCTRL_RSTOR                                           ETH_MMCCTRL_RSTOR_Msk                                          /* Reset on Read                */
#define ETH_MMCCTRL_CNTSTOPRO_Pos                                   (1U)
#define ETH_MMCCTRL_CNTSTOPRO_Msk                                   (0x1UL << ETH_MMCCTRL_CNTSTOPRO_Pos)                           /*!< 0x00000002 */
#define ETH_MMCCTRL_CNTSTOPRO                                       ETH_MMCCTRL_CNTSTOPRO_Msk                                      /* Counter Stop Rollover        */
#define ETH_MMCCTRL_CNTRST_Pos                                      (0U)
#define ETH_MMCCTRL_CNTRST_Msk                                      (0x1UL << ETH_MMCCTRL_CNTRST_Pos)                              /*!< 0x00000001 */
#define ETH_MMCCTRL_CNTRST                                          ETH_MMCCTRL_CNTRST_Msk                                         /* Counters Reset               */

/* Bit definition for Ethernet MMC Receive Interrupt Register */
#define ETH_MMCRXINT_RXGUNF_Pos                                     (17U)
#define ETH_MMCRXINT_RXGUNF_Msk                                     (0x1UL << ETH_MMCRXINT_RXGUNF_Pos)                             /*!< 0x00020000 */
#define ETH_MMCRXINT_RXGUNF                                         ETH_MMCRXINT_RXGUNF_Msk                                        /* Set when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRXINT_RXFAE_Pos                                      (6U)
#define ETH_MMCRXINT_RXFAE_Msk                                      (0x1UL << ETH_MMCRXINT_RXFAE_Pos)                              /*!< 0x00000040 */
#define ETH_MMCRXINT_RXFAE                                          ETH_MMCRXINT_RXFAE_Msk                                         /* Set when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRXINT_RXFCE_Pos                                      (5U)
#define ETH_MMCRXINT_RXFCE_Msk                                      (0x1UL << ETH_MMCRXINT_RXFCE_Pos)                              /*!< 0x00000020 */
#define ETH_MMCRXINT_RXFCE                                          ETH_MMCRXINT_RXFCE_Msk                                         /* Set when Rx crc error counter reaches half the maximum value */

/* Bit definition for Ethernet MMC Transmit Interrupt Register */
#define ETH_MMCTXINT_TXGF_Pos                                       (21U)
#define ETH_MMCTXINT_TXGF_Msk                                       (0x1UL << ETH_MMCTXINT_TXGF_Pos)                               /*!< 0x00200000 */
#define ETH_MMCTXINT_TXGF                                           ETH_MMCTXINT_TXGF_Msk                                          /* Set when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTXINT_TXGFMCOL_Pos                                   (15U)
#define ETH_MMCTXINT_TXGFMCOL_Msk                                   (0x1UL << ETH_MMCTXINT_TXGFMCOL_Pos)                           /*!< 0x00008000 */
#define ETH_MMCTXINT_TXGFMCOL                                       ETH_MMCTXINT_TXGFMCOL_Msk                                      /* Set when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTXINT_TXGFSCOL_Pos                                   (14U)
#define ETH_MMCTXINT_TXGFSCOL_Msk                                   (0x1UL << ETH_MMCTXINT_TXGFSCOL_Pos)                           /*!< 0x00004000 */
#define ETH_MMCTXINT_TXGFSCOL                                       ETH_MMCTXINT_TXGFSCOL_Msk                                      /* Set when Tx good single col counter reaches half the maximum value */

/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
#define ETH_MMCRXINTMASK_RXGUNFM_Pos                                (17U)
#define ETH_MMCRXINTMASK_RXGUNFM_Msk                                (0x1UL << ETH_MMCRXINTMASK_RXGUNFM_Pos)                        /*!< 0x00020000 */
#define ETH_MMCRXINTMASK_RXGUNFM                                    ETH_MMCRXINTMASK_RXGUNFM_Msk                                   /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
#define ETH_MMCRXINTMASK_RXFAEM_Pos                                 (6U)
#define ETH_MMCRXINTMASK_RXFAEM_Msk                                 (0x1UL << ETH_MMCRXINTMASK_RXFAEM_Pos)                         /*!< 0x00000040 */
#define ETH_MMCRXINTMASK_RXFAEM                                     ETH_MMCRXINTMASK_RXFAEM_Msk                                    /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
#define ETH_MMCRXINTMASK_RXFCEM_Pos                                 (5U)
#define ETH_MMCRXINTMASK_RXFCEM_Msk                                 (0x1UL << ETH_MMCRXINTMASK_RXFCEM_Pos)                         /*!< 0x00000020 */
#define ETH_MMCRXINTMASK_RXFCEM                                     ETH_MMCRXINTMASK_RXFCEM_Msk                                    /* Mask the interrupt when Rx crc error counter reaches half the maximum value */

/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
#define ETH_MMCTXINTMASK_TXGFM_Pos                                  (21U)
#define ETH_MMCTXINTMASK_TXGFM_Msk                                  (0x1UL << ETH_MMCTXINTMASK_TXGFM_Pos)                          /*!< 0x00200000 */
#define ETH_MMCTXINTMASK_TXGFM                                      ETH_MMCTXINTMASK_TXGFM_Msk                                     /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
#define ETH_MMCTXINTMASK_TXGFMCOLM_Pos                              (15U)
#define ETH_MMCTXINTMASK_TXGFMCOLM_Msk                              (0x1UL << ETH_MMCTXINTMASK_TXGFMCOLM_Pos)                      /*!< 0x00008000 */
#define ETH_MMCTXINTMASK_TXGFMCOLM                                  ETH_MMCTXINTMASK_TXGFMCOLM_Msk                                 /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
#define ETH_MMCTXINTMASK_TXGFSCOLM_Pos                              (14U)
#define ETH_MMCTXINTMASK_TXGFSCOLM_Msk                              (0x1UL << ETH_MMCTXINTMASK_TXGFSCOLM_Pos)                      /*!< 0x00004000 */
#define ETH_MMCTXINTMASK_TXGFSCOLM                                  ETH_MMCTXINTMASK_TXGFSCOLM_Msk                                 /* Mask the interrupt when Tx good single col counter reaches half the maximum value */

/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
#define ETH_MMCTXGFSCCNT_TXGFSCCNT_Pos                              (0U)
#define ETH_MMCTXGFSCCNT_TXGFSCCNT_Msk                              (0xFFFFFFFFUL << ETH_MMCTXGFSCCNT_TXGFSCCNT_Pos)               /*!< 0xFFFFFFFF */
#define ETH_MMCTXGFSCCNT_TXGFSCCNT                                  ETH_MMCTXGFSCCNT_TXGFSCCNT_Msk                                 /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */

/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
#define ETH_MMCTXGFMCCNT_TXGFMCCNT_Pos                              (0U)
#define ETH_MMCTXGFMCCNT_TXGFMCCNT_Msk                              (0xFFFFFFFFUL << ETH_MMCTXGFMCCNT_TXGFMCCNT_Pos)               /*!< 0xFFFFFFFF */
#define ETH_MMCTXGFMCCNT_TXGFMCCNT                                  ETH_MMCTXGFMCCNT_TXGFMCCNT_Msk                                 /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */

/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
#define ETH_MMCTXGFCNT_TXGFCNT_Pos                                  (0U)
#define ETH_MMCTXGFCNT_TXGFCNT_Msk                                  (0xFFFFFFFFUL << ETH_MMCTXGFCNT_TXGFCNT_Pos)                   /*!< 0xFFFFFFFF */
#define ETH_MMCTXGFCNT_TXGFCNT                                      ETH_MMCTXGFCNT_TXGFCNT_Msk                                     /* Number of good frames transmitted. */

/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
#define ETH_MMCRXFCECNT_RXFCECNT_Pos                                (0U)
#define ETH_MMCRXFCECNT_RXFCECNT_Msk                                (0xFFFFFFFFUL << ETH_MMCRXFCECNT_RXFCECNT_Pos)                 /*!< 0xFFFFFFFF */
#define ETH_MMCRXFCECNT_RXFCECNT                                    ETH_MMCRXFCECNT_RXFCECNT_Msk                                   /* Number of frames received with CRC error. */

/* Bit definition for Ethernet MMC Received Frames with Alignment Error Counter Register */
#define ETH_MMCRXFAECNT_RXFAECNT_Pos                                (0U)
#define ETH_MMCRXFAECNT_RXFAECNT_Msk                                (0xFFFFFFFFUL << ETH_MMCRXFAECNT_RXFAECNT_Pos)                 /*!< 0xFFFFFFFF */
#define ETH_MMCRXFAECNT_RXFAECNT                                    ETH_MMCRXFAECNT_RXFAECNT_Msk                                   /* Number of frames received with alignment (dribble) error */

/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
#define ETH_MMCRXGUNCNT_RXFCECNT_Pos                                (0U)
#define ETH_MMCRXGUNCNT_RXFCECNT_Msk                                (0xFFFFFFFFUL << ETH_MMCRXGUNCNT_RXFCECNT_Pos)                 /*!< 0xFFFFFFFF */
#define ETH_MMCRXGUNCNT_RXFCECNT                                    ETH_MMCRXGUNCNT_RXFCECNT_Msk                                   /* Number of good unicast frames received. */

/******************************************************************************/
/*               Ethernet PTP Registers bits definition                       */
/******************************************************************************/

/* Bit definition for Ethernet PTP Time Stamp Control Register */
#define ETH_PTPTSCTRL_TSSPTPFMACEN_Pos                              (18U)
#define ETH_PTPTSCTRL_TSSPTPFMACEN_Msk                              (0x1UL << ETH_PTPTSCTRL_TSSPTPFMACEN_Pos)                      /*!< 0x00008000 */
#define ETH_PTPTSCTRL_TSSPTPFMACEN                                  ETH_PTPTSCTRL_TSSPTPFMACEN_Msk                                 /* Time stamp PTP frame filtering MAC address enable */
#define ETH_PTPTSCTRL_TSCLKNSEL_Pos                                 (16U)
#define ETH_PTPTSCTRL_TSCLKNSEL_Msk                                 (0x3UL << ETH_PTPTSCTRL_TSCLKNSEL_Pos)                         /*!< 0x00030000 */
#define ETH_PTPTSCTRL_TSCLKNSEL                                     ETH_PTPTSCTRL_TSCLKNSEL_Msk                                    /* Time stamp clock node type */
#define ETH_PTPTSCTRL_TSSMNSEL_Pos                                  (15U)
#define ETH_PTPTSCTRL_TSSMNSEL_Msk                                  (0x1UL << ETH_PTPTSCTRL_TSSMNSEL_Pos)                          /*!< 0x00008000 */
#define ETH_PTPTSCTRL_TSSMNSEL                                      ETH_PTPTSCTRL_TSSMNSEL_Msk                                     /* Time stamp snapshot for message relevant to master enable */
#define ETH_PTPTSCTRL_TSSMESEL_Pos                                  (14U)
#define ETH_PTPTSCTRL_TSSMESEL_Msk                                  (0x1UL << ETH_PTPTSCTRL_TSSMESEL_Pos)                          /*!< 0x00004000 */
#define ETH_PTPTSCTRL_TSSMESEL                                      ETH_PTPTSCTRL_TSSMESEL_Msk                                     /* Time stamp snapshot for event message enable */
#define ETH_PTPTSCTRL_TSS4EN_Pos                                    (13U)
#define ETH_PTPTSCTRL_TSS4EN_Msk                                    (0x1UL << ETH_PTPTSCTRL_TSS4EN_Pos)                            /*!< 0x00002000 */
#define ETH_PTPTSCTRL_TSS4EN                                        ETH_PTPTSCTRL_TSS4EN_Msk                                       /* Time stamp snapshot for IPv4 frames enable */
#define ETH_PTPTSCTRL_TSS6EN_Pos                                    (12U)
#define ETH_PTPTSCTRL_TSS6EN_Msk                                    (0x1UL << ETH_PTPTSCTRL_TSS6EN_Pos)                            /*!< 0x00001000 */
#define ETH_PTPTSCTRL_TSS6EN                                        ETH_PTPTSCTRL_TSS6EN_Msk                                       /* Time stamp snapshot for IPv6 frames enable */
#define ETH_PTPTSCTRL_TSSPTPEN_Pos                                  (11U)
#define ETH_PTPTSCTRL_TSSPTPEN_Msk                                  (0x1UL << ETH_PTPTSCTRL_TSSPTPEN_Pos)                          /*!< 0x00000800 */
#define ETH_PTPTSCTRL_TSSPTPEN                                      ETH_PTPTSCTRL_TSSPTPEN_Msk                                     /* Time stamp snapshot for PTP over ethernet frames enable */
#define ETH_PTPTSCTRL_LISTVSEL_Pos                                  (10U)
#define ETH_PTPTSCTRL_LISTVSEL_Msk                                  (0x1UL << ETH_PTPTSCTRL_LISTVSEL_Pos)                          /*!< 0x00000400 */
#define ETH_PTPTSCTRL_LISTVSEL                                      ETH_PTPTSCTRL_LISTVSEL_Msk                                     /* Time stamp PTP packet snooping for version2 format enable */
#define ETH_PTPTSCTRL_TSSUBRO_Pos                                   (9U)
#define ETH_PTPTSCTRL_TSSUBRO_Msk                                   (0x1UL << ETH_PTPTSCTRL_TSSUBRO_Pos)                           /*!< 0x00000200 */
#define ETH_PTPTSCTRL_TSSUBRO                                       ETH_PTPTSCTRL_TSSUBRO_Msk                                      /* Time stamp Sub-seconds rollover */
#define ETH_PTPTSCTRL_TSSNEN_Pos                                    (8U)
#define ETH_PTPTSCTRL_TSSNEN_Msk                                    (0x1UL << ETH_PTPTSCTRL_TSSNEN_Pos)                            /*!< 0x00000100 */
#define ETH_PTPTSCTRL_TSSNEN                                        ETH_PTPTSCTRL_TSSNEN_Msk                                       /* Time stamp snapshot for all received frames enable */

#define ETH_PTPTSCTRL_TSADDUD_Pos                                   (5U)
#define ETH_PTPTSCTRL_TSADDUD_Msk                                   (0x1UL << ETH_PTPTSCTRL_TSADDUD_Pos)                           /*!< 0x00000020 */
#define ETH_PTPTSCTRL_TSADDUD                                       ETH_PTPTSCTRL_TSADDUD_Msk                                      /* Addend register update */
#define ETH_PTPTSCTRL_TSTRGIEN_Pos                                  (4U)
#define ETH_PTPTSCTRL_TSTRGIEN_Msk                                  (0x1UL << ETH_PTPTSCTRL_TSTRGIEN_Pos)                          /*!< 0x00000010 */
#define ETH_PTPTSCTRL_TSTRGIEN                                      ETH_PTPTSCTRL_TSTRGIEN_Msk                                     /* Time stamp interrupt trigger enable */
#define ETH_PTPTSCTRL_TSSTUD_Pos                                    (3U)
#define ETH_PTPTSCTRL_TSSTUD_Msk                                    (0x1UL << ETH_PTPTSCTRL_TSSTUD_Pos)                            /*!< 0x00000008 */
#define ETH_PTPTSCTRL_TSSTUD                                        ETH_PTPTSCTRL_TSSTUD_Msk                                       /* Time stamp update */
#define ETH_PTPTSCTRL_TSSTINIT_Pos                                  (2U)
#define ETH_PTPTSCTRL_TSSTINIT_Msk                                  (0x1UL << ETH_PTPTSCTRL_TSSTINIT_Pos)                          /*!< 0x00000004 */
#define ETH_PTPTSCTRL_TSSTINIT                                      ETH_PTPTSCTRL_TSSTINIT_Msk                                     /* Time stamp initialize */
#define ETH_PTPTSCTRL_TSUDSEL_Pos                                   (1U)
#define ETH_PTPTSCTRL_TSUDSEL_Msk                                   (0x1UL << ETH_PTPTSCTRL_TSUDSEL_Pos)                           /*!< 0x00000002 */
#define ETH_PTPTSCTRL_TSUDSEL                                       ETH_PTPTSCTRL_TSUDSEL_Msk                                      /* Time stamp fine or coarse update */
#define ETH_PTPTSCTRL_TSEN_Pos                                      (0U)
#define ETH_PTPTSCTRL_TSEN_Msk                                      (0x1UL << ETH_PTPTSCTRL_TSEN_Pos)                              /*!< 0x00000001 */
#define ETH_PTPTSCTRL_TSEN                                          ETH_PTPTSCTRL_TSEN_Msk                                         /* Time stamp enable */

/* Bit definition for Ethernet PTP Sub-Second Increment Register */
#define ETH_PTPSUBSECI_STSUBSECI_Pos                                (0U)
#define ETH_PTPSUBSECI_STSUBSECI_Msk                                (0xFFUL << ETH_PTPSUBSECI_STSUBSECI_Pos)                       /*!< 0x000000FF */
#define ETH_PTPSUBSECI_STSUBSECI                                    ETH_PTPSUBSECI_STSUBSECI_Msk                                   /* System time Sub-second increment value */

/* Bit definition for Ethernet PTP Time Stamp High Register */
#define ETH_PTPTSH_STSEC_Pos                                        (0U)
#define ETH_PTPTSH_STSEC_Msk                                        (0xFFFFFFFFUL << ETH_PTPTSH_STSEC_Pos)                         /*!< 0xFFFFFFFF */
#define ETH_PTPTSH_STSEC                                            ETH_PTPTSH_STSEC_Msk                                           /* System Time second */

/* Bit definition for Ethernet PTP Time Stamp Low Register */
#define ETH_PTPTSL_STSEL_Pos                                        (31U)
#define ETH_PTPTSL_STSEL_Msk                                        (0x1UL << ETH_PTPTSL_STSEL_Pos)                                /*!< 0x80000000 */
#define ETH_PTPTSL_STSEL                                            ETH_PTPTSL_STSEL_Msk                                           /* System Time Positive or negative time */
#define ETH_PTPTSL_STSUBSEC_Pos                                     (0U)
#define ETH_PTPTSL_STSUBSEC_Msk                                     (0x7FFFFFFFUL << ETH_PTPTSL_STSUBSEC_Pos)                      /*!< 0x7FFFFFFF */
#define ETH_PTPTSL_STSUBSEC                                         ETH_PTPTSL_STSUBSEC_Msk                                        /* System Time sub-seconds */

/* Bit definition for Ethernet PTP Time Stamp High Update Register */
#define ETH_PTPTSHUD_TSUDSEC_Pos                                    (0U)
#define ETH_PTPTSHUD_TSUDSEC_Msk                                    (0xFFFFFFFFUL << ETH_PTPTSHUD_TSUDSEC_Pos)                     /*!< 0xFFFFFFFF */
#define ETH_PTPTSHUD_TSUDSEC                                        ETH_PTPTSHUD_TSUDSEC_Msk                                       /* Time stamp update seconds */

/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
#define ETH_PTPTSLUD_TSUDSEL_Pos                                    (31U)
#define ETH_PTPTSLUD_TSUDSEL_Msk                                    (0x1UL << ETH_PTPTSLUD_TSUDSEL_Pos)                            /*!< 0x80000000 */
#define ETH_PTPTSLUD_TSUDSEL                                        ETH_PTPTSLUD_TSUDSEL_Msk                                       /* Time stamp update Positive or negative time */
#define ETH_PTPTSLUD_TSUDSUBSEC_Pos                                 (0U)
#define ETH_PTPTSLUD_TSUDSUBSEC_Msk                                 (0x7FFFFFFFUL << ETH_PTPTSLUD_TSUDSUBSEC_Pos)                  /*!< 0x7FFFFFFF */
#define ETH_PTPTSLUD_TSUDSUBSEC                                     ETH_PTPTSLUD_TSUDSUBSEC_Msk                                    /* Time stamp update sub-seconds */

/* Bit definition for Ethernet PTP Time Stamp Addend Register */
#define ETH_PTPTSA_TSA_Pos                                          (0U)
#define ETH_PTPTSA_TSA_Msk                                          (0xFFFFFFFFUL << ETH_PTPTSA_TSA_Pos)                           /*!< 0xFFFFFFFF */
#define ETH_PTPTSA_TSA                                              ETH_PTPTSA_TSA_Msk                                             /* Time stamp addend */

/* Bit definition for Ethernet PTP Target Time High Register */
#define ETH_PTPTTSH_TTSH_Pos                                        (0U)
#define ETH_PTPTTSH_TTSH_Msk                                        (0xFFFFFFFFUL << ETH_PTPTTSH_TTSH_Pos)                         /*!< 0xFFFFFFFF */
#define ETH_PTPTTSH_TTSH                                            ETH_PTPTTSH_TTSH_Msk                                           /* Target time stamp high */

/* Bit definition for Ethernet PTP Target Time Low Register */
#define ETH_PTPTTSL_TTSL_Pos                                        (0U)
#define ETH_PTPTTSL_TTSL_Msk                                        (0xFFFFFFFFUL << ETH_PTPTTSL_TTSL_Pos)                         /*!< 0xFFFFFFFF */
#define ETH_PTPTTSL_TTSL                                            ETH_PTPTTSL_TTSL_Msk                                           /* Target time stamp low */

/* Bit definition for Ethernet PTP Time Stamp Status Register */
#define ETH_PTPTSSTS_TTSRD_Pos                                      (1U)
#define ETH_PTPTSSTS_TTSRD_Msk                                      (0x1UL << ETH_PTPTSSTS_TTSRD_Pos)                              /*!< 0x00000020 */
#define ETH_PTPTSSTS_TTSRD                                          ETH_PTPTSSTS_TTSRD_Msk                                         /* Time stamp target time reached */
#define ETH_PTPTSSTS_TSSECOVR_Pos                                   (0U)
#define ETH_PTPTSSTS_TSSECOVR_Msk                                   (0x1UL << ETH_PTPTSSTS_TSSECOVR_Pos)                           /*!< 0x00000010 */
#define ETH_PTPTSSTS_TSSECOVR                                       ETH_PTPTSSTS_TSSECOVR_Msk                                      /* Time stamp seconds overflow */

/******************************************************************************/
/*                 Ethernet DMA Registers bits definition                     */
/******************************************************************************/

/* Bit definition for Ethernet DMA Bus Mode Register */
#define ETH_DMABMOD_MB_Pos                                          (26U)
#define ETH_DMABMOD_MB_Msk                                          (0x1UL << ETH_DMABMOD_MB_Pos)                                  /*!< 0x04000000 */
#define ETH_DMABMOD_MB                                              ETH_DMABMOD_MB_Msk                                             /* Mixed Burst */
#define ETH_DMABMOD_AAL_Pos                                         (25U)
#define ETH_DMABMOD_AAL_Msk                                         (0x1UL << ETH_DMABMOD_AAL_Pos)                                 /*!< 0x02000000 */
#define ETH_DMABMOD_AAL                                             ETH_DMABMOD_AAL_Msk                                            /* Address-Aligned beats */
#define ETH_DMABMOD_PBLx4_Pos                                       (24U)
#define ETH_DMABMOD_PBLx4_Msk                                       (0x1UL << ETH_DMABMOD_PBLx4_Pos)                               /*!< 0x01000000 */
#define ETH_DMABMOD_PBLx4                                           ETH_DMABMOD_PBLx4_Msk                                          /* 4xPBL mode */
#define ETH_DMABMOD_USP_Pos                                         (23U)
#define ETH_DMABMOD_USP_Msk                                         (0x1UL << ETH_DMABMOD_USP_Pos)                                 /*!< 0x00800000 */
#define ETH_DMABMOD_USP                                             ETH_DMABMOD_USP_Msk                                            /* Use separate PBL */
#define ETH_DMABMOD_RPBL_Pos                                        (17U)
#define ETH_DMABMOD_RPBL_Msk                                        (0x3FUL << ETH_DMABMOD_RPBL_Pos)                               /*!< 0x007E0000 */
#define ETH_DMABMOD_RPBL                                            ETH_DMABMOD_RPBL_Msk                                           /* RxDMA PBL */
#define ETH_DMABMOD_RPBL_1Beat                                      0x00020000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
#define ETH_DMABMOD_RPBL_2Beat                                      0x00040000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
#define ETH_DMABMOD_RPBL_4Beat                                      0x00080000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMOD_RPBL_8Beat                                      0x00100000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMOD_RPBL_16Beat                                     0x00200000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMOD_RPBL_32Beat                                     0x00400000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMOD_RPBL_4xPBL_4Beat                                0x01020000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
#define ETH_DMABMOD_RPBL_4xPBL_8Beat                                0x01040000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
#define ETH_DMABMOD_RPBL_4xPBL_16Beat                               0x01080000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
#define ETH_DMABMOD_RPBL_4xPBL_32Beat                               0x01100000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
#define ETH_DMABMOD_RPBL_4xPBL_64Beat                               0x01200000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
#define ETH_DMABMOD_RPBL_4xPBL_128Beat                              0x01400000U                                                    /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
#define ETH_DMABMOD_FB_Pos                                          (16U)
#define ETH_DMABMOD_FB_Msk                                          (0x1UL << ETH_DMABMOD_FB_Pos)                                  /*!< 0x00010000 */
#define ETH_DMABMOD_FB                                              ETH_DMABMOD_FB_Msk                                             /* Fixed Burst */
#define ETH_DMABMOD_PR_Pos                                          (14U)
#define ETH_DMABMOD_PR_Msk                                          (0x3UL << ETH_DMABMOD_PR_Pos)                                  /*!< 0x0000C000 */
#define ETH_DMABMOD_PR                                              ETH_DMABMOD_PR_Msk                                             /* Rx Tx priority ratio */
#define ETH_DMABMOD_PR_1_1                                          0x00000000U                                                    /* Rx Tx priority ratio */
#define ETH_DMABMOD_PR_2_1                                          0x00004000U                                                    /* Rx Tx priority ratio */
#define ETH_DMABMOD_PR_3_1                                          0x00008000U                                                    /* Rx Tx priority ratio */
#define ETH_DMABMOD_PR_4_1                                          0x0000C000U                                                    /* Rx Tx priority ratio */
#define ETH_DMABMOD_PBL_Pos                                         (8U)
#define ETH_DMABMOD_PBL_Msk                                         (0x3FUL << ETH_DMABMOD_PBL_Pos)                                /*!< 0x00003F00 */
#define ETH_DMABMOD_PBL                                             ETH_DMABMOD_PBL_Msk                                            /* Programmable burst length */
#define ETH_DMABMOD_PBL_1Beat                                       0x00000100U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
#define ETH_DMABMOD_PBL_2Beat                                       0x00000200U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
#define ETH_DMABMOD_PBL_4Beat                                       0x00000400U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMOD_PBL_8Beat                                       0x00000800U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMOD_PBL_16Beat                                      0x00001000U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMOD_PBL_32Beat                                      0x00002000U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMOD_PBL_4xPBL_4Beat                                 0x01000100U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
#define ETH_DMABMOD_PBL_4xPBL_8Beat                                 0x01000200U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
#define ETH_DMABMOD_PBL_4xPBL_16Beat                                0x01000400U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
#define ETH_DMABMOD_PBL_4xPBL_32Beat                                0x01000800U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
#define ETH_DMABMOD_PBL_4xPBL_64Beat                                0x01001000U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
#define ETH_DMABMOD_PBL_4xPBL_128Beat                               0x01002000U                                                    /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
#define ETH_DMABMOD_EDFEN_Pos                                       (7U)
#define ETH_DMABMOD_EDFEN_Msk                                       (0x1UL << ETH_DMABMOD_EDFEN_Pos)                               /*!< 0x00000080 */
#define ETH_DMABMOD_EDFEN                                           ETH_DMABMOD_EDFEN_Msk                                          /* Enhanced Descriptor Enable */
#define ETH_DMABMOD_DSL_Pos                                         (2U)
#define ETH_DMABMOD_DSL_Msk                                         (0x1FUL << ETH_DMABMOD_DSL_Pos)                                /*!< 0x0000007C */
#define ETH_DMABMOD_DSL                                             ETH_DMABMOD_DSL_Msk                                            /* Descriptor Skip Length */
#define ETH_DMABMOD_DAS_Pos                                         (1U)
#define ETH_DMABMOD_DAS_Msk                                         (0x1UL << ETH_DMABMOD_DAS_Pos)                                 /*!< 0x00000002 */
#define ETH_DMABMOD_DAS                                             ETH_DMABMOD_DAS_Msk                                            /* DMA arbitration scheme */
#define ETH_DMABMOD_SWR_Pos                                         (0U)
#define ETH_DMABMOD_SWR_Msk                                         (0x1UL << ETH_DMABMOD_SWR_Pos)                                 /*!< 0x00000001 */
#define ETH_DMABMOD_SWR                                             ETH_DMABMOD_SWR_Msk                                            /* Software reset */

/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
#define ETH_DMATXPD_TXPD_Pos                                        (0U)
#define ETH_DMATXPD_TXPD_Msk                                        (0xFFFFFFFFUL << ETH_DMATXPD_TXPD_Pos)                         /*!< 0xFFFFFFFF */
#define ETH_DMATXPD_TXPD                                            ETH_DMATXPD_TXPD_Msk                                           /* Transmit poll demand */

/* Bit definition for Ethernet DMA Receive Poll Demand Register */
#define ETH_DMARXPD_RXPD_Pos                                        (0U)
#define ETH_DMARXPD_RXPD_Msk                                        (0xFFFFFFFFUL << ETH_DMARXPD_RXPD_Pos)                         /*!< 0xFFFFFFFF */
#define ETH_DMARXPD_RXPD                                            ETH_DMARXPD_RXPD_Msk                                           /* Receive poll demand  */

/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
#define ETH_DMARXDLADDR_RXSTA_Pos                                   (0U)
#define ETH_DMARXDLADDR_RXSTA_Msk                                   (0xFFFFFFFFUL << ETH_DMARXDLADDR_RXSTA_Pos)                    /*!< 0xFFFFFFFF */
#define ETH_DMARXDLADDR_RXSTA                                       ETH_DMARXDLADDR_RXSTA_Msk                                      /* Start of receive list */

/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
#define ETH_DMATXDLADDR_TXSTA_Pos                                   (0U)
#define ETH_DMATXDLADDR_TXSTA_Msk                                   (0xFFFFFFFFUL << ETH_DMATXDLADDR_TXSTA_Pos)                    /*!< 0xFFFFFFFF */
#define ETH_DMATXDLADDR_TXSTA                                       ETH_DMATXDLADDR_TXSTA_Msk                                      /* Start of transmit list */

/* Bit definition for Ethernet DMA Status Register */
#define ETH_DMASTS_TSTFLG_Pos                                       (29U)
#define ETH_DMASTS_TSTFLG_Msk                                       (0x1UL << ETH_DMASTS_TSTFLG_Pos)                               /*!< 0x20000000 */
#define ETH_DMASTS_TSTFLG                                           ETH_DMASTS_TSTFLG_Msk                                          /* Time-stamp trigger status */
#define ETH_DMASTS_PMTFLG_Pos                                       (28U)
#define ETH_DMASTS_PMTFLG_Msk                                       (0x1UL << ETH_DMASTS_PMTFLG_Pos)                               /*!< 0x10000000 */
#define ETH_DMASTS_PMTFLG                                           ETH_DMASTS_PMTFLG_Msk                                          /* PMT status */
#define ETH_DMASTS_MMCFLG_Pos                                       (27U)
#define ETH_DMASTS_MMCFLG_Msk                                       (0x1UL << ETH_DMASTS_MMCFLG_Pos)                               /*!< 0x08000000 */
#define ETH_DMASTS_MMCFLG                                           ETH_DMASTS_MMCFLG_Msk                                          /* MMC status */
#define ETH_DMASTS_ERRB_Pos                                         (23U)
#define ETH_DMASTS_ERRB_Msk                                         (0x7UL << ETH_DMASTS_ERRB_Pos)                                 /*!< 0x03800000 */
#define ETH_DMASTS_ERRB                                             ETH_DMASTS_ERRB_Msk                                            /* Error bits status */
  /* combination with EBS[2:0] for GetFlagStatus function */
#define ETH_DMASTS_ERRB_DescAccess_Pos                              (25U)
#define ETH_DMASTS_ERRB_DescAccess_Msk                              (0x1UL << ETH_DMASTS_ERRB_DescAccess_Pos)                      /*!< 0x02000000 */
#define ETH_DMASTS_ERRB_DescAccess                                  ETH_DMASTS_ERRB_DescAccess_Msk                                 /* Error bits 0-data buffer, 1-desc. access */
#define ETH_DMASTS_ERRB_ReadTransf_Pos                              (24U)
#define ETH_DMASTS_ERRB_ReadTransf_Msk                              (0x1UL << ETH_DMASTS_ERRB_ReadTransf_Pos)                      /*!< 0x01000000 */
#define ETH_DMASTS_ERRB_ReadTransf                                  ETH_DMASTS_ERRB_ReadTransf_Msk                                 /* Error bits 0-write trnsf, 1-read transfr */
#define ETH_DMASTS_ERRB_DataTransfTx_Pos                            (23U)
#define ETH_DMASTS_ERRB_DataTransfTx_Msk                            (0x1UL << ETH_DMASTS_ERRB_DataTransfTx_Pos)                    /*!< 0x00800000 */
#define ETH_DMASTS_ERRB_DataTransfTx                                ETH_DMASTS_ERRB_DataTransfTx_Msk                               /* Error bits 0-Rx DMA, 1-Tx DMA */
#define ETH_DMASTS_TXSTS_Pos                                        (20U)
#define ETH_DMASTS_TXSTS_Msk                                        (0x7UL << ETH_DMASTS_TXSTS_Pos)                                /*!< 0x00700000 */
#define ETH_DMASTS_TXSTS                                            ETH_DMASTS_TXSTS_Msk                                           /* Transmit process state */
#define ETH_DMASTS_TXSTS_Stopped                                    0x00000000U                                                    /* Stopped - Reset or Stop Tx Command issued  */
#define ETH_DMASTS_TXSTS_Fetching_Pos                               (20U)
#define ETH_DMASTS_TXSTS_Fetching_Msk                               (0x1UL << ETH_DMASTS_TXSTS_Fetching_Pos)                       /*!< 0x00100000 */
#define ETH_DMASTS_TXSTS_Fetching                                   ETH_DMASTS_TXSTS_Fetching_Msk                                  /* Running - fetching the Tx descriptor */
#define ETH_DMASTS_TXSTS_Waiting_Pos                                (21U)
#define ETH_DMASTS_TXSTS_Waiting_Msk                                (0x1UL << ETH_DMASTS_TXSTS_Waiting_Pos)                        /*!< 0x00200000 */
#define ETH_DMASTS_TXSTS_Waiting                                    ETH_DMASTS_TXSTS_Waiting_Msk                                   /* Running - waiting for status */
#define ETH_DMASTS_TXSTS_Reading_Pos                                (20U)
#define ETH_DMASTS_TXSTS_Reading_Msk                                (0x3UL << ETH_DMASTS_TXSTS_Reading_Pos)                        /*!< 0x00300000 */
#define ETH_DMASTS_TXSTS_Reading                                    ETH_DMASTS_TXSTS_Reading_Msk                                   /* Running - reading the data from host memory */
#define ETH_DMASTS_TXSTS_Suspended_Pos                              (21U)
#define ETH_DMASTS_TXSTS_Suspended_Msk                              (0x3UL << ETH_DMASTS_TXSTS_Suspended_Pos)                      /*!< 0x00600000 */
#define ETH_DMASTS_TXSTS_Suspended                                  ETH_DMASTS_TXSTS_Suspended_Msk                                 /* Suspended - Tx Descriptor unavailable */
#define ETH_DMASTS_TXSTS_Closing_Pos                                (20U)
#define ETH_DMASTS_TXSTS_Closing_Msk                                (0x7UL << ETH_DMASTS_TXSTS_Closing_Pos)                        /*!< 0x00700000 */
#define ETH_DMASTS_TXSTS_Closing                                    ETH_DMASTS_TXSTS_Closing_Msk                                   /* Running - closing Rx descriptor */
#define ETH_DMASTS_RXSTS_Pos                                        (17U)
#define ETH_DMASTS_RXSTS_Msk                                        (0x7UL << ETH_DMASTS_RXSTS_Pos)                                /*!< 0x000E0000 */
#define ETH_DMASTS_RXSTS                                            ETH_DMASTS_RXSTS_Msk                                           /* Receive process state */
#define ETH_DMASTS_RXSTS_Stopped                                    0x00000000U                                                    /* Stopped - Reset or Stop Rx Command issued */
#define ETH_DMASTS_RXSTS_Fetching_Pos                               (17U)
#define ETH_DMASTS_RXSTS_Fetching_Msk                               (0x1UL << ETH_DMASTS_RXSTS_Fetching_Pos)                       /*!< 0x00020000 */
#define ETH_DMASTS_RXSTS_Fetching                                   ETH_DMASTS_RXSTS_Fetching_Msk                                  /* Running - fetching the Rx descriptor */
#define ETH_DMASTS_RXSTS_Waiting_Pos                                (17U)
#define ETH_DMASTS_RXSTS_Waiting_Msk                                (0x3UL << ETH_DMASTS_RXSTS_Waiting_Pos)                        /*!< 0x00060000 */
#define ETH_DMASTS_RXSTS_Waiting                                    ETH_DMASTS_RXSTS_Waiting_Msk                                   /* Running - waiting for packet */
#define ETH_DMASTS_RXSTS_Suspended_Pos                              (19U)
#define ETH_DMASTS_RXSTS_Suspended_Msk                              (0x1UL << ETH_DMASTS_RXSTS_Suspended_Pos)                      /*!< 0x00080000 */
#define ETH_DMASTS_RXSTS_Suspended                                  ETH_DMASTS_RXSTS_Suspended_Msk                                 /* Suspended - Rx Descriptor unavailable */
#define ETH_DMASTS_RXSTS_Closing_Pos                                (17U)
#define ETH_DMASTS_RXSTS_Closing_Msk                                (0x5UL << ETH_DMASTS_RXSTS_Closing_Pos)                        /*!< 0x000A0000 */
#define ETH_DMASTS_RXSTS_Closing                                    ETH_DMASTS_RXSTS_Closing_Msk                                   /* Running - closing descriptor */
#define ETH_DMASTS_RXSTS_Queuing_Pos                                (17U)
#define ETH_DMASTS_RXSTS_Queuing_Msk                                (0x7UL << ETH_DMASTS_RXSTS_Queuing_Pos)                        /*!< 0x000E0000 */
#define ETH_DMASTS_RXSTS_Queuing                                    ETH_DMASTS_RXSTS_Queuing_Msk                                   /* Running - queuing the receive frame into host memory */
#define ETH_DMASTS_NINTS_Pos                                        (16U)
#define ETH_DMASTS_NINTS_Msk                                        (0x1UL << ETH_DMASTS_NINTS_Pos)                                /*!< 0x00010000 */
#define ETH_DMASTS_NINTS                                            ETH_DMASTS_NINTS_Msk                                           /* Normal interrupt summary */
#define ETH_DMASTS_AINTS_Pos                                        (15U)
#define ETH_DMASTS_AINTS_Msk                                        (0x1UL << ETH_DMASTS_AINTS_Pos)                                /*!< 0x00008000 */
#define ETH_DMASTS_AINTS                                            ETH_DMASTS_AINTS_Msk                                           /* Abnormal interrupt summary */
#define ETH_DMASTS_ERXFLG_Pos                                       (14U)
#define ETH_DMASTS_ERXFLG_Msk                                       (0x1UL << ETH_DMASTS_ERXFLG_Pos)                               /*!< 0x00004000 */
#define ETH_DMASTS_ERXFLG                                           ETH_DMASTS_ERXFLG_Msk                                          /* Early receive status */
#define ETH_DMASTS_FBERRFLG_Pos                                     (13U)
#define ETH_DMASTS_FBERRFLG_Msk                                     (0x1UL << ETH_DMASTS_FBERRFLG_Pos)                             /*!< 0x00002000 */
#define ETH_DMASTS_FBERRFLG                                         ETH_DMASTS_FBERRFLG_Msk                                        /* Fatal bus error status */
#define ETH_DMASTS_ETXFLG_Pos                                       (10U)
#define ETH_DMASTS_ETXFLG_Msk                                       (0x1UL << ETH_DMASTS_ETXFLG_Pos)                               /*!< 0x00000400 */
#define ETH_DMASTS_ETXFLG                                           ETH_DMASTS_ETXFLG_Msk                                          /* Early transmit status */
#define ETH_DMASTS_RXWTOFLG_Pos                                     (9U)
#define ETH_DMASTS_RXWTOFLG_Msk                                     (0x1UL << ETH_DMASTS_RXWTOFLG_Pos)                             /*!< 0x00000200 */
#define ETH_DMASTS_RXWTOFLG                                         ETH_DMASTS_RXWTOFLG_Msk                                        /* Receive watchdog timeout status */
#define ETH_DMASTS_RXSFLG_Pos                                       (8U)
#define ETH_DMASTS_RXSFLG_Msk                                       (0x1UL << ETH_DMASTS_RXSFLG_Pos)                               /*!< 0x00000100 */
#define ETH_DMASTS_RXSFLG                                           ETH_DMASTS_RXSFLG_Msk                                          /* Receive process stopped status */
#define ETH_DMASTS_RXBU_Pos                                         (7U)
#define ETH_DMASTS_RXBU_Msk                                         (0x1UL << ETH_DMASTS_RXBU_Pos)                                 /*!< 0x00000080 */
#define ETH_DMASTS_RXBU                                             ETH_DMASTS_RXBU_Msk                                            /* Receive buffer unavailable status */
#define ETH_DMASTS_RXFLG_Pos                                        (6U)
#define ETH_DMASTS_RXFLG_Msk                                        (0x1UL << ETH_DMASTS_RXFLG_Pos)                                /*!< 0x00000040 */
#define ETH_DMASTS_RXFLG                                            ETH_DMASTS_RXFLG_Msk                                           /* Receive status */
#define ETH_DMASTS_TXUNF_Pos                                        (5U)
#define ETH_DMASTS_TXUNF_Msk                                        (0x1UL << ETH_DMASTS_TXUNF_Pos)                                /*!< 0x00000020 */
#define ETH_DMASTS_TXUNF                                            ETH_DMASTS_TXUNF_Msk                                           /* Transmit underflow status */
#define ETH_DMASTS_RXOVF_Pos                                        (4U)
#define ETH_DMASTS_RXOVF_Msk                                        (0x1UL << ETH_DMASTS_RXOVF_Pos)                                /*!< 0x00000010 */
#define ETH_DMASTS_RXOVF                                            ETH_DMASTS_RXOVF_Msk                                           /* Receive overflow status */
#define ETH_DMASTS_TXJTO_Pos                                        (3U)
#define ETH_DMASTS_TXJTO_Msk                                        (0x1UL << ETH_DMASTS_TXJTO_Pos)                                /*!< 0x00000008 */
#define ETH_DMASTS_TXJTO                                            ETH_DMASTS_TXJTO_Msk                                           /* Transmit jabber timeout status */
#define ETH_DMASTS_TXBU_Pos                                         (2U)
#define ETH_DMASTS_TXBU_Msk                                         (0x1UL << ETH_DMASTS_TXBU_Pos)                                 /*!< 0x00000004 */
#define ETH_DMASTS_TXBU                                             ETH_DMASTS_TXBU_Msk                                            /* Transmit buffer unavailable status */
#define ETH_DMASTS_TXSFLG_Pos                                       (1U)
#define ETH_DMASTS_TXSFLG_Msk                                       (0x1UL << ETH_DMASTS_TXSFLG_Pos)                               /*!< 0x00000002 */
#define ETH_DMASTS_TXSFLG                                           ETH_DMASTS_TXSFLG_Msk                                          /* Transmit process stopped status */
#define ETH_DMASTS_TXFLG_Pos                                        (0U)
#define ETH_DMASTS_TXFLG_Msk                                        (0x1UL << ETH_DMASTS_TXFLG_Pos)                                /*!< 0x00000001 */
#define ETH_DMASTS_TXFLG                                            ETH_DMASTS_TXFLG_Msk                                           /* Transmit status */

/* Bit definition for Ethernet DMA Operation Mode Register */
#define ETH_DMAOPMOD_DISDT_Pos                                      (26U)
#define ETH_DMAOPMOD_DISDT_Msk                                      (0x1UL << ETH_DMAOPMOD_DISDT_Pos)                              /*!< 0x04000000 */
#define ETH_DMAOPMOD_DISDT                                          ETH_DMAOPMOD_DISDT_Msk                                         /* Disable Dropping of TCP/IP checksum error frames */
#define ETH_DMAOPMOD_RXSF_Pos                                       (25U)
#define ETH_DMAOPMOD_RXSF_Msk                                       (0x1UL << ETH_DMAOPMOD_RXSF_Pos)                               /*!< 0x02000000 */
#define ETH_DMAOPMOD_RXSF                                           ETH_DMAOPMOD_RXSF_Msk                                          /* Receive store and forward */
#define ETH_DMAOPMOD_DISFRXF_Pos                                    (24U)
#define ETH_DMAOPMOD_DISFRXF_Msk                                    (0x1UL << ETH_DMAOPMOD_DISFRXF_Pos)                            /*!< 0x01000000 */
#define ETH_DMAOPMOD_DISFRXF                                        ETH_DMAOPMOD_DISFRXF_Msk                                       /* Disable flushing of received frames */
#define ETH_DMAOPMOD_TXSF_Pos                                       (21U)
#define ETH_DMAOPMOD_TXSF_Msk                                       (0x1UL << ETH_DMAOPMOD_TXSF_Pos)                               /*!< 0x00200000 */
#define ETH_DMAOPMOD_TXSF                                           ETH_DMAOPMOD_TXSF_Msk                                          /* Transmit store and forward */
#define ETH_DMAOPMOD_FTXF_Pos                                       (20U)
#define ETH_DMAOPMOD_FTXF_Msk                                       (0x1UL << ETH_DMAOPMOD_FTXF_Pos)                               /*!< 0x00100000 */
#define ETH_DMAOPMOD_FTXF                                           ETH_DMAOPMOD_FTXF_Msk                                          /* Flush transmit FIFO */
#define ETH_DMAOPMOD_TXTHCTRL_Pos                                   (14U)
#define ETH_DMAOPMOD_TXTHCTRL_Msk                                   (0x7UL << ETH_DMAOPMOD_TXTHCTRL_Pos)                           /*!< 0x0001C000 */
#define ETH_DMAOPMOD_TXTHCTRL                                       ETH_DMAOPMOD_TXTHCTRL_Msk                                      /* Transmit threshold control */
#define ETH_DMAOPMOD_TXTHCTRL_64Bytes                               0x00000000U                                                    /* threshold level of the MTL Transmit FIFO is 64 Bytes */
#define ETH_DMAOPMOD_TXTHCTRL_128Bytes                              0x00004000U                                                    /* threshold level of the MTL Transmit FIFO is 128 Bytes */
#define ETH_DMAOPMOD_TXTHCTRL_192Bytes                              0x00008000U                                                    /* threshold level of the MTL Transmit FIFO is 192 Bytes */
#define ETH_DMAOPMOD_TXTHCTRL_256Bytes                              0x0000C000U                                                    /* threshold level of the MTL Transmit FIFO is 256 Bytes */
#define ETH_DMAOPMOD_TXTHCTRL_40Bytes                               0x00010000U                                                    /* threshold level of the MTL Transmit FIFO is 40 Bytes */
#define ETH_DMAOPMOD_TXTHCTRL_32Bytes                               0x00014000U                                                    /* threshold level of the MTL Transmit FIFO is 32 Bytes */
#define ETH_DMAOPMOD_TXTHCTRL_24Bytes                               0x00018000U                                                    /* threshold level of the MTL Transmit FIFO is 24 Bytes */
#define ETH_DMAOPMOD_TXTHCTRL_16Bytes                               0x0001C000U                                                    /* threshold level of the MTL Transmit FIFO is 16 Bytes */
#define ETH_DMAOPMOD_STTX_Pos                                       (13U)
#define ETH_DMAOPMOD_STTX_Msk                                       (0x1UL << ETH_DMAOPMOD_STTX_Pos)                               /*!< 0x00002000 */
#define ETH_DMAOPMOD_STTX                                           ETH_DMAOPMOD_STTX_Msk                                          /* Start/stop transmission command */
#define ETH_DMAOPMOD_FERRF_Pos                                      (7U)
#define ETH_DMAOPMOD_FERRF_Msk                                      (0x1UL << ETH_DMAOPMOD_FERRF_Pos)                              /*!< 0x00000080 */
#define ETH_DMAOPMOD_FERRF                                          ETH_DMAOPMOD_FERRF_Msk                                         /* Forward error frames */
#define ETH_DMAOPMOD_FUF_Pos                                        (6U)
#define ETH_DMAOPMOD_FUF_Msk                                        (0x1UL << ETH_DMAOPMOD_FUF_Pos)                                /*!< 0x00000040 */
#define ETH_DMAOPMOD_FUF                                            ETH_DMAOPMOD_FUF_Msk                                           /* Forward undersized good frames */
#define ETH_DMAOPMOD_RXTHCTRL_Pos                                   (3U)
#define ETH_DMAOPMOD_RXTHCTRL_Msk                                   (0x3UL << ETH_DMAOPMOD_RXTHCTRL_Pos)                           /*!< 0x00000018 */
#define ETH_DMAOPMOD_RXTHCTRL                                       ETH_DMAOPMOD_RXTHCTRL_Msk                                      /* receive threshold control */
#define ETH_DMAOPMOD_RXTHCTRL_64Bytes                               0x00000000U                                                    /* threshold level of the MTL Receive FIFO is 64 Bytes */
#define ETH_DMAOPMOD_RXTHCTRL_32Bytes                               0x00000008U                                                    /* threshold level of the MTL Receive FIFO is 32 Bytes */
#define ETH_DMAOPMOD_RXTHCTRL_96Bytes                               0x00000010U                                                    /* threshold level of the MTL Receive FIFO is 96 Bytes */
#define ETH_DMAOPMOD_RXTHCTRL_128Bytes                              0x00000018U                                                    /* threshold level of the MTL Receive FIFO is 128 Bytes */
#define ETH_DMAOPMOD_OSECF_Pos                                      (2U)
#define ETH_DMAOPMOD_OSECF_Msk                                      (0x1UL << ETH_DMAOPMOD_OSECF_Pos)                              /*!< 0x00000004 */
#define ETH_DMAOPMOD_OSECF                                          ETH_DMAOPMOD_OSECF_Msk                                         /* operate on second frame */
#define ETH_DMAOPMOD_STRX_Pos                                       (1U)
#define ETH_DMAOPMOD_STRX_Msk                                       (0x1UL << ETH_DMAOPMOD_STRX_Pos)                               /*!< 0x00000002 */
#define ETH_DMAOPMOD_STRX                                           ETH_DMAOPMOD_STRX_Msk                                          /* Start/stop receive */

/* Bit definition for Ethernet DMA Interrupt Enable Register */
#define ETH_DMAINTEN_NINTSEN_Pos                                    (16U)
#define ETH_DMAINTEN_NINTSEN_Msk                                    (0x1UL << ETH_DMAINTEN_NINTSEN_Pos)                            /*!< 0x00010000 */
#define ETH_DMAINTEN_NINTSEN                                        ETH_DMAINTEN_NINTSEN_Msk                                       /* Normal interrupt summary enable */
#define ETH_DMAINTEN_AINTSEN_Pos                                    (15U)
#define ETH_DMAINTEN_AINTSEN_Msk                                    (0x1UL << ETH_DMAINTEN_AINTSEN_Pos)                            /*!< 0x00008000 */
#define ETH_DMAINTEN_AINTSEN                                        ETH_DMAINTEN_AINTSEN_Msk                                       /* Abnormal interrupt summary enable */
#define ETH_DMAINTEN_ERXIEN_Pos                                     (14U)
#define ETH_DMAINTEN_ERXIEN_Msk                                     (0x1UL << ETH_DMAINTEN_ERXIEN_Pos)                             /*!< 0x00004000 */
#define ETH_DMAINTEN_ERXIEN                                         ETH_DMAINTEN_ERXIEN_Msk                                        /* Early receive interrupt enable */
#define ETH_DMAINTEN_FBERREN_Pos                                    (13U)
#define ETH_DMAINTEN_FBERREN_Msk                                    (0x1UL << ETH_DMAINTEN_FBERREN_Pos)                            /*!< 0x00002000 */
#define ETH_DMAINTEN_FBERREN                                        ETH_DMAINTEN_FBERREN_Msk                                       /* Fatal bus error interrupt enable */
#define ETH_DMAINTEN_ETXIEN_Pos                                     (10U)
#define ETH_DMAINTEN_ETXIEN_Msk                                     (0x1UL << ETH_DMAINTEN_ETXIEN_Pos)                             /*!< 0x00000400 */
#define ETH_DMAINTEN_ETXIEN                                         ETH_DMAINTEN_ETXIEN_Msk                                        /* Early transmit interrupt enable */
#define ETH_DMAINTEN_RXWTOEN_Pos                                    (9U)
#define ETH_DMAINTEN_RXWTOEN_Msk                                    (0x1UL << ETH_DMAINTEN_RXWTOEN_Pos)                            /*!< 0x00000200 */
#define ETH_DMAINTEN_RXWTOEN                                        ETH_DMAINTEN_RXWTOEN_Msk                                       /* Receive watchdog timeout interrupt enable */
#define ETH_DMAINTEN_RXSEN_Pos                                      (8U)
#define ETH_DMAINTEN_RXSEN_Msk                                      (0x1UL << ETH_DMAINTEN_RXSEN_Pos)                              /*!< 0x00000100 */
#define ETH_DMAINTEN_RXSEN                                          ETH_DMAINTEN_RXSEN_Msk                                         /* Receive process stopped interrupt enable */
#define ETH_DMAINTEN_RXBUEN_Pos                                     (7U)
#define ETH_DMAINTEN_RXBUEN_Msk                                     (0x1UL << ETH_DMAINTEN_RXBUEN_Pos)                             /*!< 0x00000080 */
#define ETH_DMAINTEN_RXBUEN                                         ETH_DMAINTEN_RXBUEN_Msk                                        /* Receive buffer unavailable interrupt enable */
#define ETH_DMAINTEN_RXIEN_Pos                                      (6U)
#define ETH_DMAINTEN_RXIEN_Msk                                      (0x1UL << ETH_DMAINTEN_RXIEN_Pos)                              /*!< 0x00000040 */
#define ETH_DMAINTEN_RXIEN                                          ETH_DMAINTEN_RXIEN_Msk                                         /* Receive interrupt enable */
#define ETH_DMAINTEN_TXUNFEN_Pos                                    (5U)
#define ETH_DMAINTEN_TXUNFEN_Msk                                    (0x1UL << ETH_DMAINTEN_TXUNFEN_Pos)                            /*!< 0x00000020 */
#define ETH_DMAINTEN_TXUNFEN                                        ETH_DMAINTEN_TXUNFEN_Msk                                       /* Transmit Underflow interrupt enable */
#define ETH_DMAINTEN_RXOVFEN_Pos                                    (4U)
#define ETH_DMAINTEN_RXOVFEN_Msk                                    (0x1UL << ETH_DMAINTEN_RXOVFEN_Pos)                            /*!< 0x00000010 */
#define ETH_DMAINTEN_RXOVFEN                                        ETH_DMAINTEN_RXOVFEN_Msk                                       /* Receive Overflow interrupt enable */
#define ETH_DMAINTEN_TXJTOEN_Pos                                    (3U)
#define ETH_DMAINTEN_TXJTOEN_Msk                                    (0x1UL << ETH_DMAINTEN_TXJTOEN_Pos)                            /*!< 0x00000008 */
#define ETH_DMAINTEN_TXJTOEN                                        ETH_DMAINTEN_TXJTOEN_Msk                                       /* Transmit jabber timeout interrupt enable */
#define ETH_DMAINTEN_TXBUEN_Pos                                     (2U)
#define ETH_DMAINTEN_TXBUEN_Msk                                     (0x1UL << ETH_DMAINTEN_TXBUEN_Pos)                             /*!< 0x00000004 */
#define ETH_DMAINTEN_TXBUEN                                         ETH_DMAINTEN_TXBUEN_Msk                                        /* Transmit buffer unavailable interrupt enable */
#define ETH_DMAINTEN_TXSEN_Pos                                      (1U)
#define ETH_DMAINTEN_TXSEN_Msk                                      (0x1UL << ETH_DMAINTEN_TXSEN_Pos)                              /*!< 0x00000002 */
#define ETH_DMAINTEN_TXSEN                                          ETH_DMAINTEN_TXSEN_Msk                                         /* Transmit process stopped interrupt enable */
#define ETH_DMAINTEN_TXIEN_Pos                                      (0U)
#define ETH_DMAINTEN_TXIEN_Msk                                      (0x1UL << ETH_DMAINTEN_TXIEN_Pos)                              /*!< 0x00000001 */
#define ETH_DMAINTEN_TXIEN                                          ETH_DMAINTEN_TXIEN_Msk                                         /* Transmit interrupt enable */

/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
#define ETH_DMAMFABOCNT_OVFCNTOVF_Pos                               (28U)
#define ETH_DMAMFABOCNT_OVFCNTOVF_Msk                               (0x1UL << ETH_DMAMFABOCNT_OVFCNTOVF_Pos)                       /*!< 0x10000000 */
#define ETH_DMAMFABOCNT_OVFCNTOVF                                   ETH_DMAMFABOCNT_OVFCNTOVF_Msk                                  /* Overflow bit for FIFO overflow counter */
#define ETH_DMAMFABOCNT_AMISFCNT_Pos                                (17U)
#define ETH_DMAMFABOCNT_AMISFCNT_Msk                                (0x7FFUL << ETH_DMAMFABOCNT_AMISFCNT_Pos)                      /*!< 0x0FFE0000 */
#define ETH_DMAMFABOCNT_AMISFCNT                                    ETH_DMAMFABOCNT_AMISFCNT_Msk                                   /* Number of frames missed by the application */
#define ETH_DMAMFABOCNT_MISFCNTOVF_Pos                              (16U)
#define ETH_DMAMFABOCNT_MISFCNTOVF_Msk                              (0x1UL << ETH_DMAMFABOCNT_MISFCNTOVF_Pos)                      /*!< 0x00010000 */
#define ETH_DMAMFABOCNT_MISFCNTOVF                                  ETH_DMAMFABOCNT_MISFCNTOVF_Msk                                 /* Overflow bit for missed frame counter */
#define ETH_DMAMFABOCNT_MISFCNT_Pos                                 (0U)
#define ETH_DMAMFABOCNT_MISFCNT_Msk                                 (0xFFFFUL << ETH_DMAMFABOCNT_MISFCNT_Pos)                      /*!< 0x0000FFFF */
#define ETH_DMAMFABOCNT_MISFCNT                                     ETH_DMAMFABOCNT_MISFCNT_Msk                                    /* Number of frames missed by the controller */

/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
#define ETH_DMAHTXD_HTXDADDRP_Pos                                   (0U)
#define ETH_DMAHTXD_HTXDADDRP_Msk                                   (0xFFFFFFFFUL << ETH_DMAHTXD_HTXDADDRP_Pos)                    /*!< 0xFFFFFFFF */
#define ETH_DMAHTXD_HTXDADDRP                                       ETH_DMAHTXD_HTXDADDRP_Msk                                      /* Host transmit descriptor address pointer */

/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
#define ETH_DMAHRXD_HRXDADDRP_Pos                                   (0U)
#define ETH_DMAHRXD_HRXDADDRP_Msk                                   (0xFFFFFFFFUL << ETH_DMAHRXD_HRXDADDRP_Pos)                    /*!< 0xFFFFFFFF */
#define ETH_DMAHRXD_HRXDADDRP                                       ETH_DMAHRXD_HRXDADDRP_Msk                                      /* Host receive descriptor address pointer */

/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
#define ETH_DMAHTXBADDR_HTXBADDRP_Pos                               (0U)
#define ETH_DMAHTXBADDR_HTXBADDRP_Msk                               (0xFFFFFFFFUL << ETH_DMAHTXBADDR_HTXBADDRP_Pos)                /*!< 0xFFFFFFFF */
#define ETH_DMAHTXBADDR_HTXBADDRP                                   ETH_DMAHTXBADDR_HTXBADDRP_Msk                                  /* Host transmit buffer address pointer */

/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
#define ETH_DMAHRXBADDR_HRXBADDRP_Pos                               (0U)
#define ETH_DMAHRXBADDR_HRXBADDRP_Msk                               (0xFFFFFFFFUL << ETH_DMAHRXBADDR_HRXBADDRP_Pos)                /*!< 0xFFFFFFFF */
#define ETH_DMAHRXBADDR_HRXBADDRP                                   ETH_DMAHRXBADDR_HRXBADDRP_Msk                                  /* Host receive buffer address pointer */

/******************************************************************************/
/*                                                                            */
/*                                       USB_OTG                              */
/*                                                                            */
/******************************************************************************/
/********************  Bit definition for USB_OTG_GCTRLSTS register  ***********/
#define USB_OTG_GCTRLSTS_SREQSUC_Pos                                (0U)
#define USB_OTG_GCTRLSTS_SREQSUC_Msk                                (0x1UL << USB_OTG_GCTRLSTS_SREQSUC_Pos)                        /*!< 0x00000001 */
#define USB_OTG_GCTRLSTS_SREQSUC                                    USB_OTG_GCTRLSTS_SREQSUC_Msk                                   /*!< Session request success */
#define USB_OTG_GCTRLSTS_SREQ_Pos                                   (1U)
#define USB_OTG_GCTRLSTS_SREQ_Msk                                   (0x1UL << USB_OTG_GCTRLSTS_SREQ_Pos)                           /*!< 0x00000002 */
#define USB_OTG_GCTRLSTS_SREQ                                       USB_OTG_GCTRLSTS_SREQ_Msk                                      /*!< Session request */
#define USB_OTG_GCTRLSTS_HNSUC_Pos                                  (8U)
#define USB_OTG_GCTRLSTS_HNSUC_Msk                                  (0x1UL << USB_OTG_GCTRLSTS_HNSUC_Pos)                          /*!< 0x00000100 */
#define USB_OTG_GCTRLSTS_HNSUC                                      USB_OTG_GCTRLSTS_HNSUC_Msk                                     /*!< Host set HNP enable */
#define USB_OTG_GCTRLSTS_HNPREQ_Pos                                 (9U)
#define USB_OTG_GCTRLSTS_HNPREQ_Msk                                 (0x1UL << USB_OTG_GCTRLSTS_HNPREQ_Pos)                         /*!< 0x00000200 */
#define USB_OTG_GCTRLSTS_HNPREQ                                     USB_OTG_GCTRLSTS_HNPREQ_Msk                                    /*!< HNP request */
#define USB_OTG_GCTRLSTS_HHNPEN_Pos                                 (10U)
#define USB_OTG_GCTRLSTS_HHNPEN_Msk                                 (0x1UL << USB_OTG_GCTRLSTS_HHNPEN_Pos)                         /*!< 0x00000400 */
#define USB_OTG_GCTRLSTS_HHNPEN                                     USB_OTG_GCTRLSTS_HHNPEN_Msk                                    /*!< Host set HNP enable */
#define USB_OTG_GCTRLSTS_DHNPEN_Pos                                 (11U)
#define USB_OTG_GCTRLSTS_DHNPEN_Msk                                 (0x1UL << USB_OTG_GCTRLSTS_DHNPEN_Pos)                         /*!< 0x00000800 */
#define USB_OTG_GCTRLSTS_DHNPEN                                     USB_OTG_GCTRLSTS_DHNPEN_Msk                                    /*!< Device HNP enabled */
#define USB_OTG_GCTRLSTS_CIDSTS_Pos                                 (16U)
#define USB_OTG_GCTRLSTS_CIDSTS_Msk                                 (0x1UL << USB_OTG_GCTRLSTS_CIDSTS_Pos)                         /*!< 0x00010000 */
#define USB_OTG_GCTRLSTS_CIDSTS                                     USB_OTG_GCTRLSTS_CIDSTS_Msk                                    /*!< Connector ID status */
#define USB_OTG_GCTRLSTS_LSDEBT_Pos                                 (17U)
#define USB_OTG_GCTRLSTS_LSDEBT_Msk                                 (0x1UL << USB_OTG_GCTRLSTS_LSDEBT_Pos)                         /*!< 0x00020000 */
#define USB_OTG_GCTRLSTS_LSDEBT                                     USB_OTG_GCTRLSTS_LSDEBT_Msk                                    /*!< Long/short debounce time */
#define USB_OTG_GCTRLSTS_ASVD_Pos                                   (18U)
#define USB_OTG_GCTRLSTS_ASVD_Msk                                   (0x1UL << USB_OTG_GCTRLSTS_ASVD_Pos)                           /*!< 0x00040000 */
#define USB_OTG_GCTRLSTS_ASVD                                       USB_OTG_GCTRLSTS_ASVD_Msk                                      /*!< A-session valid  */
#define USB_OTG_GCTRLSTS_BSVD_Pos                                   (19U)
#define USB_OTG_GCTRLSTS_BSVD_Msk                                   (0x1UL << USB_OTG_GCTRLSTS_BSVD_Pos)                           /*!< 0x00080000 */
#define USB_OTG_GCTRLSTS_BSVD                                       USB_OTG_GCTRLSTS_BSVD_Msk                                      /*!< B-session valid */

/********************  Bit definition for USB_OTG_HCFG register  ********************/

#define USB_OTG_HCFG_PHYCLKSEL_Pos                                  (0U)
#define USB_OTG_HCFG_PHYCLKSEL_Msk                                  (0x3UL << USB_OTG_HCFG_PHYCLKSEL_Pos)                          /*!< 0x00000003 */
#define USB_OTG_HCFG_PHYCLKSEL                                      USB_OTG_HCFG_PHYCLKSEL_Msk                                     /*!< FS/LS PHY clock select  */
#define USB_OTG_HCFG_PHYCLKSEL_0                                    (0x1UL << USB_OTG_HCFG_PHYCLKSEL_Pos)                          /*!< 0x00000001 */
#define USB_OTG_HCFG_PHYCLKSEL_1                                    (0x2UL << USB_OTG_HCFG_PHYCLKSEL_Pos)                          /*!< 0x00000002 */
#define USB_OTG_HCFG_FSSPT_Pos                                      (2U)
#define USB_OTG_HCFG_FSSPT_Msk                                      (0x1UL << USB_OTG_HCFG_FSSPT_Pos)                              /*!< 0x00000004 */
#define USB_OTG_HCFG_FSSPT                                          USB_OTG_HCFG_FSSPT_Msk                                         /*!< FS- and LS-only support */

/********************  Bit definition for USB_OTG_DCFG register  ********************/

#define USB_OTG_DCFG_DSPDSEL_Pos                                    (0U)
#define USB_OTG_DCFG_DSPDSEL_Msk                                    (0x3UL << USB_OTG_DCFG_DSPDSEL_Pos)                            /*!< 0x00000003 */
#define USB_OTG_DCFG_DSPDSEL                                        USB_OTG_DCFG_DSPDSEL_Msk                                       /*!< Device speed */
#define USB_OTG_DCFG_DSPDSEL_0                                      (0x1UL << USB_OTG_DCFG_DSPDSEL_Pos)                            /*!< 0x00000001 */
#define USB_OTG_DCFG_DSPDSEL_1                                      (0x2UL << USB_OTG_DCFG_DSPDSEL_Pos)                            /*!< 0x00000002 */
#define USB_OTG_DCFG_SENDOUT_Pos                                    (2U)
#define USB_OTG_DCFG_SENDOUT_Msk                                    (0x1UL << USB_OTG_DCFG_SENDOUT_Pos)                            /*!< 0x00000004 */
#define USB_OTG_DCFG_SENDOUT                                        USB_OTG_DCFG_SENDOUT_Msk                                       /*!< Nonzero-length status OUT handshake */

#define USB_OTG_DCFG_DADDR_Pos                                      (4U)
#define USB_OTG_DCFG_DADDR_Msk                                      (0x7FUL << USB_OTG_DCFG_DADDR_Pos)                             /*!< 0x000007F0 */
#define USB_OTG_DCFG_DADDR                                          USB_OTG_DCFG_DADDR_Msk                                         /*!< Device address */
#define USB_OTG_DCFG_DADDR_0                                        (0x01UL << USB_OTG_DCFG_DADDR_Pos)                             /*!< 0x00000010 */
#define USB_OTG_DCFG_DADDR_1                                        (0x02UL << USB_OTG_DCFG_DADDR_Pos)                             /*!< 0x00000020 */
#define USB_OTG_DCFG_DADDR_2                                        (0x04UL << USB_OTG_DCFG_DADDR_Pos)                             /*!< 0x00000040 */
#define USB_OTG_DCFG_DADDR_3                                        (0x08UL << USB_OTG_DCFG_DADDR_Pos)                             /*!< 0x00000080 */
#define USB_OTG_DCFG_DADDR_4                                        (0x10UL << USB_OTG_DCFG_DADDR_Pos)                             /*!< 0x00000100 */
#define USB_OTG_DCFG_DADDR_5                                        (0x20UL << USB_OTG_DCFG_DADDR_Pos)                             /*!< 0x00000200 */
#define USB_OTG_DCFG_DADDR_6                                        (0x40UL << USB_OTG_DCFG_DADDR_Pos)                             /*!< 0x00000400 */

#define USB_OTG_DCFG_PFITV_Pos                                      (11U)
#define USB_OTG_DCFG_PFITV_Msk                                      (0x3UL << USB_OTG_DCFG_PFITV_Pos)                              /*!< 0x00001800 */
#define USB_OTG_DCFG_PFITV                                          USB_OTG_DCFG_PFITV_Msk                                         /*!< Periodic (micro)frame interval */
#define USB_OTG_DCFG_PFITV_0                                        (0x1UL << USB_OTG_DCFG_PFITV_Pos)                              /*!< 0x00000800 */
#define USB_OTG_DCFG_PFITV_1                                        (0x2UL << USB_OTG_DCFG_PFITV_Pos)                              /*!< 0x00001000 */

#define USB_OTG_DCFG_XCVRDLY_Pos                                    (14U)
#define USB_OTG_DCFG_XCVRDLY_Msk                                    (0x1UL << USB_OTG_DCFG_XCVRDLY_Pos)                            /*!< 0x00004000 */
#define USB_OTG_DCFG_XCVRDLY                                        USB_OTG_DCFG_XCVRDLY_Msk                                       /*!< Transceiver delay */

#define USB_OTG_DCFG_ERRATMR_Pos                                    (15U)
#define USB_OTG_DCFG_ERRATMR_Msk                                    (0x1UL << USB_OTG_DCFG_ERRATMR_Pos)                            /*!< 0x00008000 */
#define USB_OTG_DCFG_ERRATMR                                        USB_OTG_DCFG_ERRATMR_Msk                                       /*!< Erratic error interrupt mask */

#define USB_OTG_DCFG_PSITV_Pos                                      (24U)
#define USB_OTG_DCFG_PSITV_Msk                                      (0x3UL << USB_OTG_DCFG_PSITV_Pos)                              /*!< 0x03000000 */
#define USB_OTG_DCFG_PSITV                                          USB_OTG_DCFG_PSITV_Msk                                         /*!< Periodic scheduling interval */
#define USB_OTG_DCFG_PSITV_0                                        (0x1UL << USB_OTG_DCFG_PSITV_Pos)                              /*!< 0x01000000 */
#define USB_OTG_DCFG_PSITV_1                                        (0x2UL << USB_OTG_DCFG_PSITV_Pos)                              /*!< 0x02000000 */

/********************  Bit definition for USB_OTG_PCGCCTL register  ********************/
#define USB_OTG_PCGCCTL_PCLKSTOP_Pos                                (0U)
#define USB_OTG_PCGCCTL_PCLKSTOP_Msk                                (0x1UL << USB_OTG_PCGCCTL_PCLKSTOP_Pos)                        /*!< 0x00000001 */
#define USB_OTG_PCGCCTL_PCLKSTOP                                    USB_OTG_PCGCCTL_PCLKSTOP_Msk                                   /*!< Stop PHY clock */
#define USB_OTG_PCGCCTL_GCLK_Pos                                    (1U)
#define USB_OTG_PCGCCTL_GCLK_Msk                                    (0x1UL << USB_OTG_PCGCCTL_GCLK_Pos)                            /*!< 0x00000002 */
#define USB_OTG_PCGCCTL_GCLK                                        USB_OTG_PCGCCTL_GCLK_Msk                                       /*!< Gate HCLK */
#define USB_OTG_PCGCR_PHYSUS_Pos                                    (4U)
#define USB_OTG_PCGCR_PHYSUS_Msk                                    (0x1UL << USB_OTG_PCGCR_PHYSUS_Pos)                            /*!< 0x00000010 */
#define USB_OTG_PCGCR_PHYSUS                                        USB_OTG_PCGCR_PHYSUS_Msk                                       /*!< PHY suspended */

/********************  Bit definition for USB_OTG_GINT register  ********************/
#define USB_OTG_GINT_SEFLG_Pos                                      (2U)
#define USB_OTG_GINT_SEFLG_Msk                                      (0x1UL << USB_OTG_GINT_SEFLG_Pos)                              /*!< 0x00000004 */
#define USB_OTG_GINT_SEFLG                                          USB_OTG_GINT_SEFLG_Msk                                         /*!< Session end detected                   */
#define USB_OTG_GINT_SREQSUCCHG_Pos                                 (8U)
#define USB_OTG_GINT_SREQSUCCHG_Msk                                 (0x1UL << USB_OTG_GINT_SREQSUCCHG_Pos)                         /*!< 0x00000100 */
#define USB_OTG_GINT_SREQSUCCHG                                     USB_OTG_GINT_SREQSUCCHG_Msk                                    /*!< Session request success status change  */
#define USB_OTG_GINT_HNSUCCHG_Pos                                   (9U)
#define USB_OTG_GINT_HNSUCCHG_Msk                                   (0x1UL << USB_OTG_GINT_HNSUCCHG_Pos)                           /*!< 0x00000200 */
#define USB_OTG_GINT_HNSUCCHG                                       USB_OTG_GINT_HNSUCCHG_Msk                                      /*!< Host negotiation success status change */
#define USB_OTG_GINT_HNFLG_Pos                                      (17U)
#define USB_OTG_GINT_HNFLG_Msk                                      (0x1UL << USB_OTG_GINT_HNFLG_Pos)                              /*!< 0x00020000 */
#define USB_OTG_GINT_HNFLG                                          USB_OTG_GINT_HNFLG_Msk                                         /*!< Host negotiation detected              */
#define USB_OTG_GINT_ADTOFLG_Pos                                    (18U)
#define USB_OTG_GINT_ADTOFLG_Msk                                    (0x1UL << USB_OTG_GINT_ADTOFLG_Pos)                            /*!< 0x00040000 */
#define USB_OTG_GINT_ADTOFLG                                        USB_OTG_GINT_ADTOFLG_Msk                                       /*!< A-device timeout change                */
#define USB_OTG_GINT_DEBDFLG_Pos                                    (19U)
#define USB_OTG_GINT_DEBDFLG_Msk                                    (0x1UL << USB_OTG_GINT_DEBDFLG_Pos)                            /*!< 0x00080000 */
#define USB_OTG_GINT_DEBDFLG                                        USB_OTG_GINT_DEBDFLG_Msk                                       /*!< Debounce done                          */

/********************  Bit definition for USB_OTG_DCTRL register  ********************/
#define USB_OTG_DCTRL_RWKUPS_Pos                                    (0U)
#define USB_OTG_DCTRL_RWKUPS_Msk                                    (0x1UL << USB_OTG_DCTRL_RWKUPS_Pos)                            /*!< 0x00000001 */
#define USB_OTG_DCTRL_RWKUPS                                        USB_OTG_DCTRL_RWKUPS_Msk                                       /*!< Remote wakeup signaling */
#define USB_OTG_DCTRL_SDCNNT_Pos                                    (1U)
#define USB_OTG_DCTRL_SDCNNT_Msk                                    (0x1UL << USB_OTG_DCTRL_SDCNNT_Pos)                            /*!< 0x00000002 */
#define USB_OTG_DCTRL_SDCNNT                                        USB_OTG_DCTRL_SDCNNT_Msk                                       /*!< Soft disconnect         */
#define USB_OTG_DCTRL_GINAKSTS_Pos                                  (2U)
#define USB_OTG_DCTRL_GINAKSTS_Msk                                  (0x1UL << USB_OTG_DCTRL_GINAKSTS_Pos)                          /*!< 0x00000004 */
#define USB_OTG_DCTRL_GINAKSTS                                      USB_OTG_DCTRL_GINAKSTS_Msk                                     /*!< Global IN NAK status    */
#define USB_OTG_DCTRL_GONAKSTS_Pos                                  (3U)
#define USB_OTG_DCTRL_GONAKSTS_Msk                                  (0x1UL << USB_OTG_DCTRL_GONAKSTS_Pos)                          /*!< 0x00000008 */
#define USB_OTG_DCTRL_GONAKSTS                                      USB_OTG_DCTRL_GONAKSTS_Msk                                     /*!< Global OUT NAK status   */

#define USB_OTG_DCTRL_TESTSEL_Pos                                   (4U)
#define USB_OTG_DCTRL_TESTSEL_Msk                                   (0x7UL << USB_OTG_DCTRL_TESTSEL_Pos)                           /*!< 0x00000070 */
#define USB_OTG_DCTRL_TESTSEL                                       USB_OTG_DCTRL_TESTSEL_Msk                                      /*!< Test control */
#define USB_OTG_DCTRL_TESTSEL_0                                     (0x1UL << USB_OTG_DCTRL_TESTSEL_Pos)                           /*!< 0x00000010 */
#define USB_OTG_DCTRL_TESTSEL_1                                     (0x2UL << USB_OTG_DCTRL_TESTSEL_Pos)                           /*!< 0x00000020 */
#define USB_OTG_DCTRL_TESTSEL_2                                     (0x4UL << USB_OTG_DCTRL_TESTSEL_Pos)                           /*!< 0x00000040 */
#define USB_OTG_DCTRL_GINAKSET_Pos                                  (7U)
#define USB_OTG_DCTRL_GINAKSET_Msk                                  (0x1UL << USB_OTG_DCTRL_GINAKSET_Pos)                          /*!< 0x00000080 */
#define USB_OTG_DCTRL_GINAKSET                                      USB_OTG_DCTRL_GINAKSET_Msk                                     /*!< Set global IN NAK         */
#define USB_OTG_DCTRL_GINAKCLR_Pos                                  (8U)
#define USB_OTG_DCTRL_GINAKCLR_Msk                                  (0x1UL << USB_OTG_DCTRL_GINAKCLR_Pos)                          /*!< 0x00000100 */
#define USB_OTG_DCTRL_GINAKCLR                                      USB_OTG_DCTRL_GINAKCLR_Msk                                     /*!< Clear global IN NAK       */
#define USB_OTG_DCTRL_GONAKSET_Pos                                  (9U)
#define USB_OTG_DCTRL_GONAKSET_Msk                                  (0x1UL << USB_OTG_DCTRL_GONAKSET_Pos)                          /*!< 0x00000200 */
#define USB_OTG_DCTRL_GONAKSET                                      USB_OTG_DCTRL_GONAKSET_Msk                                     /*!< Set global OUT NAK        */
#define USB_OTG_DCTRL_GONAKCLR_Pos                                  (10U)
#define USB_OTG_DCTRL_GONAKCLR_Msk                                  (0x1UL << USB_OTG_DCTRL_GONAKCLR_Pos)                          /*!< 0x00000400 */
#define USB_OTG_DCTRL_GONAKCLR                                      USB_OTG_DCTRL_GONAKCLR_Msk                                     /*!< Clear global OUT NAK      */
#define USB_OTG_DCTRL_POPROGCMP_Pos                                 (11U)
#define USB_OTG_DCTRL_POPROGCMP_Msk                                 (0x1UL << USB_OTG_DCTRL_POPROGCMP_Pos)                         /*!< 0x00000800 */
#define USB_OTG_DCTRL_POPROGCMP                                     USB_OTG_DCTRL_POPROGCMP_Msk                                    /*!< Power-on programming done */

/********************  Bit definition for USB_OTG_HFIVL register  ********************/
#define USB_OTG_HFIVL_FIVL_Pos                                      (0U)
#define USB_OTG_HFIVL_FIVL_Msk                                      (0xFFFFUL << USB_OTG_HFIVL_FIVL_Pos)                           /*!< 0x0000FFFF */
#define USB_OTG_HFIVL_FIVL                                          USB_OTG_HFIVL_FIVL_Msk                                         /*!< Frame interval */

/********************  Bit definition for USB_OTG_HFIFM register  ********************/
#define USB_OTG_HFIFM_FNUM_Pos                                      (0U)
#define USB_OTG_HFIFM_FNUM_Msk                                      (0xFFFFUL << USB_OTG_HFIFM_FNUM_Pos)                           /*!< 0x0000FFFF */
#define USB_OTG_HFIFM_FNUM                                          USB_OTG_HFIFM_FNUM_Msk                                         /*!< Frame number         */
#define USB_OTG_HFIFM_FRTIME_Pos                                    (16U)
#define USB_OTG_HFIFM_FRTIME_Msk                                    (0xFFFFUL << USB_OTG_HFIFM_FRTIME_Pos)                         /*!< 0xFFFF0000 */
#define USB_OTG_HFIFM_FRTIME                                        USB_OTG_HFIFM_FRTIME_Msk                                       /*!< Frame time remaining */

/********************  Bit definition for USB_OTG_DSTS register  ********************/
#define USB_OTG_DSTS_SUSSTS_Pos                                     (0U)
#define USB_OTG_DSTS_SUSSTS_Msk                                     (0x1UL << USB_OTG_DSTS_SUSSTS_Pos)                             /*!< 0x00000001 */
#define USB_OTG_DSTS_SUSSTS                                         USB_OTG_DSTS_SUSSTS_Msk                                        /*!< Suspend status   */

#define USB_OTG_DSTS_ENUMSPD_Pos                                    (1U)
#define USB_OTG_DSTS_ENUMSPD_Msk                                    (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos)                            /*!< 0x00000006 */
#define USB_OTG_DSTS_ENUMSPD                                        USB_OTG_DSTS_ENUMSPD_Msk                                       /*!< Enumerated speed */
#define USB_OTG_DSTS_ENUMSPD_0                                      (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos)                            /*!< 0x00000002 */
#define USB_OTG_DSTS_ENUMSPD_1                                      (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos)                            /*!< 0x00000004 */
#define USB_OTG_DSTS_ERTERR_Pos                                     (3U)
#define USB_OTG_DSTS_ERTERR_Msk                                     (0x1UL << USB_OTG_DSTS_ERTERR_Pos)                             /*!< 0x00000008 */
#define USB_OTG_DSTS_ERTERR                                         USB_OTG_DSTS_ERTERR_Msk                                        /*!< Erratic error     */
#define USB_OTG_DSTS_SOFNUM_Pos                                     (8U)
#define USB_OTG_DSTS_SOFNUM_Msk                                     (0x3FFFUL << USB_OTG_DSTS_SOFNUM_Pos)                          /*!< 0x003FFF00 */
#define USB_OTG_DSTS_SOFNUM                                         USB_OTG_DSTS_SOFNUM_Msk                                        /*!< Frame number of the received SOF */

/********************  Bit definition for USB_OTG_GAHBCFG register  ********************/
#define USB_OTG_GAHBCFG_GINTMASK_Pos                                (0U)
#define USB_OTG_GAHBCFG_GINTMASK_Msk                                (0x1UL << USB_OTG_GAHBCFG_GINTMASK_Pos)                        /*!< 0x00000001 */
#define USB_OTG_GAHBCFG_GINTMASK                                    USB_OTG_GAHBCFG_GINTMASK_Msk                                   /*!< Global interrupt mask */
#define USB_OTG_GAHBCFG_BLT_Pos                                     (1U)
#define USB_OTG_GAHBCFG_BLT_Msk                                     (0xFUL << USB_OTG_GAHBCFG_BLT_Pos)                             /*!< 0x0000001E */
#define USB_OTG_GAHBCFG_BLT                                         USB_OTG_GAHBCFG_BLT_Msk                                        /*!< Burst length/type */
#define USB_OTG_GAHBCFG_BLT_0                                       (0x0UL << USB_OTG_GAHBCFG_BLT_Pos)                             /*!< Single */
#define USB_OTG_GAHBCFG_BLT_1                                       (0x1UL << USB_OTG_GAHBCFG_BLT_Pos)                             /*!< INCR */
#define USB_OTG_GAHBCFG_BLT_2                                       (0x3UL << USB_OTG_GAHBCFG_BLT_Pos)                             /*!< INCR4 */
#define USB_OTG_GAHBCFG_BLT_3                                       (0x5UL << USB_OTG_GAHBCFG_BLT_Pos)                             /*!< INCR8 */
#define USB_OTG_GAHBCFG_BLT_4                                       (0x7UL << USB_OTG_GAHBCFG_BLT_Pos)                             /*!< INCR16 */
#define USB_OTG_GAHBCFG_DMAEN_Pos                                   (5U)
#define USB_OTG_GAHBCFG_DMAEN_Msk                                   (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos)                           /*!< 0x00000020 */
#define USB_OTG_GAHBCFG_DMAEN                                       USB_OTG_GAHBCFG_DMAEN_Msk                                      /*!< DMA enable */
#define USB_OTG_GAHBCFG_TXFEL_Pos                                   (7U)
#define USB_OTG_GAHBCFG_TXFEL_Msk                                   (0x1UL << USB_OTG_GAHBCFG_TXFEL_Pos)                           /*!< 0x00000080 */
#define USB_OTG_GAHBCFG_TXFEL                                       USB_OTG_GAHBCFG_TXFEL_Msk                                      /*!< TxFIFO empty level */
#define USB_OTG_GAHBCFG_PTXFEL_Pos                                  (8U)
#define USB_OTG_GAHBCFG_PTXFEL_Msk                                  (0x1UL << USB_OTG_GAHBCFG_PTXFEL_Pos)                          /*!< 0x00000100 */
#define USB_OTG_GAHBCFG_PTXFEL                                      USB_OTG_GAHBCFG_PTXFEL_Msk                                     /*!< Periodic TxFIFO empty level */

/********************  Bit definition for USB_OTG_GUSBCFG register  ********************/

#define USB_OTG_GUSBCFG_SEFLG_Pos                                   (0U)
#define USB_OTG_GUSBCFG_SEFLG_Msk                                   (0x7UL << USB_OTG_GUSBCFG_SEFLG_Pos)                           /*!< 0x00000007 */
#define USB_OTG_GUSBCFG_SEFLG                                       USB_OTG_GUSBCFG_SEFLG_Msk                                      /*!< FS timeout calibration */
#define USB_OTG_GUSBCFG_SEFLG_0                                     (0x1UL << USB_OTG_GUSBCFG_SEFLG_Pos)                           /*!< 0x00000001 */
#define USB_OTG_GUSBCFG_SEFLG_1                                     (0x2UL << USB_OTG_GUSBCFG_SEFLG_Pos)                           /*!< 0x00000002 */
#define USB_OTG_GUSBCFG_SEFLG_2                                     (0x4UL << USB_OTG_GUSBCFG_SEFLG_Pos)                           /*!< 0x00000004 */
#define USB_OTG_GUSBCFG_FSSTSEL_Pos                                 (6U)
#define USB_OTG_GUSBCFG_FSSTSEL_Msk                                 (0x1UL << USB_OTG_GUSBCFG_FSSTSEL_Pos)                         /*!< 0x00000040 */
#define USB_OTG_GUSBCFG_FSSTSEL                                     USB_OTG_GUSBCFG_FSSTSEL_Msk                                    /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
#define USB_OTG_GUSBCFG_SRPEN_Pos                                   (8U)
#define USB_OTG_GUSBCFG_SRPEN_Msk                                   (0x1UL << USB_OTG_GUSBCFG_SRPEN_Pos)                           /*!< 0x00000100 */
#define USB_OTG_GUSBCFG_SRPEN                                       USB_OTG_GUSBCFG_SRPEN_Msk                                      /*!< SRP-capable */
#define USB_OTG_GUSBCFG_HNPEN_Pos                                   (9U)
#define USB_OTG_GUSBCFG_HNPEN_Msk                                   (0x1UL << USB_OTG_GUSBCFG_HNPEN_Pos)                           /*!< 0x00000200 */
#define USB_OTG_GUSBCFG_HNPEN                                       USB_OTG_GUSBCFG_HNPEN_Msk                                      /*!< HNP-capable */
#define USB_OTG_GUSBCFG_TRTIM_Pos                                   (10U)
#define USB_OTG_GUSBCFG_TRTIM_Msk                                   (0xFUL << USB_OTG_GUSBCFG_TRTIM_Pos)                           /*!< 0x00003C00 */
#define USB_OTG_GUSBCFG_TRTIM                                       USB_OTG_GUSBCFG_TRTIM_Msk                                      /*!< USB turnaround time */
#define USB_OTG_GUSBCFG_TRTIM_0                                     (0x1UL << USB_OTG_GUSBCFG_TRTIM_Pos)                           /*!< 0x00000400 */
#define USB_OTG_GUSBCFG_TRTIM_1                                     (0x2UL << USB_OTG_GUSBCFG_TRTIM_Pos)                           /*!< 0x00000800 */
#define USB_OTG_GUSBCFG_TRTIM_2                                     (0x4UL << USB_OTG_GUSBCFG_TRTIM_Pos)                           /*!< 0x00001000 */
#define USB_OTG_GUSBCFG_TRTIM_3                                     (0x8UL << USB_OTG_GUSBCFG_TRTIM_Pos)                           /*!< 0x00002000 */
#define USB_OTG_GUSBCFG_PHYLPSEL_Pos                                (15U)
#define USB_OTG_GUSBCFG_PHYLPSEL_Msk                                (0x1UL << USB_OTG_GUSBCFG_PHYLPSEL_Pos)                        /*!< 0x00008000 */
#define USB_OTG_GUSBCFG_PHYLPSEL                                    USB_OTG_GUSBCFG_PHYLPSEL_Msk                                   /*!< PHY Low-power clock select */
#define USB_OTG_GUSBCFG_ULPISEL_Pos                                 (17U)
#define USB_OTG_GUSBCFG_ULPISEL_Msk                                 (0x1UL << USB_OTG_GUSBCFG_ULPISEL_Pos)                         /*!< 0x00020000 */
#define USB_OTG_GUSBCFG_ULPISEL                                     USB_OTG_GUSBCFG_ULPISEL_Msk                                    /*!< ULPI FS/LS select               */
#define USB_OTG_GUSBCFG_ULPIAR_Pos                                  (18U)
#define USB_OTG_GUSBCFG_ULPIAR_Msk                                  (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos)                          /*!< 0x00040000 */
#define USB_OTG_GUSBCFG_ULPIAR                                      USB_OTG_GUSBCFG_ULPIAR_Msk                                     /*!< ULPI Auto-resume                */
#define USB_OTG_GUSBCFG_ULPICLKP_Pos                                (19U)
#define USB_OTG_GUSBCFG_ULPICLKP_Msk                                (0x1UL << USB_OTG_GUSBCFG_ULPICLKP_Pos)                        /*!< 0x00080000 */
#define USB_OTG_GUSBCFG_ULPICLKP                                    USB_OTG_GUSBCFG_ULPICLKP_Msk                                   /*!< ULPI Clock SuspendM             */
#define USB_OTG_GUSBCFG_ULPIEVDSEL_Pos                              (20U)
#define USB_OTG_GUSBCFG_ULPIEVDSEL_Msk                              (0x1UL << USB_OTG_GUSBCFG_ULPIEVDSEL_Pos)                      /*!< 0x00100000 */
#define USB_OTG_GUSBCFG_ULPIEVDSEL                                  USB_OTG_GUSBCFG_ULPIEVDSEL_Msk                                 /*!< ULPI External VBUS Drive        */
#define USB_OTG_GUSBCFG_ULPIEVC_Pos                                 (21U)
#define USB_OTG_GUSBCFG_ULPIEVC_Msk                                 (0x1UL << USB_OTG_GUSBCFG_ULPIEVC_Pos)                         /*!< 0x00200000 */
#define USB_OTG_GUSBCFG_ULPIEVC                                     USB_OTG_GUSBCFG_ULPIEVC_Msk                                    /*!< ULPI external VBUS indicator    */
#define USB_OTG_GUSBCFG_DPSEL_Pos                                   (22U)
#define USB_OTG_GUSBCFG_DPSEL_Msk                                   (0x1UL << USB_OTG_GUSBCFG_DPSEL_Pos)                           /*!< 0x00400000 */
#define USB_OTG_GUSBCFG_DPSEL                                       USB_OTG_GUSBCFG_DPSEL_Msk                                      /*!< TermSel DLine pulsing selection */
#define USB_OTG_GUSBCFG_SINI_Pos                                    (23U)
#define USB_OTG_GUSBCFG_SINI_Msk                                    (0x1UL << USB_OTG_GUSBCFG_SINI_Pos)                            /*!< 0x00800000 */
#define USB_OTG_GUSBCFG_SINI                                        USB_OTG_GUSBCFG_SINI_Msk                                       /*!< Indicator complement            */
#define USB_OTG_GUSBCFG_NPTHQ_Pos                                   (24U)
#define USB_OTG_GUSBCFG_NPTHQ_Msk                                   (0x1UL << USB_OTG_GUSBCFG_NPTHQ_Pos)                           /*!< 0x01000000 */
#define USB_OTG_GUSBCFG_NPTHQ                                       USB_OTG_GUSBCFG_NPTHQ_Msk                                      /*!< Indicator pass through          */
#define USB_OTG_GUSBCFG_ULPIIPCDIS_Pos                              (25U)
#define USB_OTG_GUSBCFG_ULPIIPCDIS_Msk                              (0x1UL << USB_OTG_GUSBCFG_ULPIIPCDIS_Pos)                      /*!< 0x02000000 */
#define USB_OTG_GUSBCFG_ULPIIPCDIS                                  USB_OTG_GUSBCFG_ULPIIPCDIS_Msk                                 /*!< ULPI interface protect disable  */
#define USB_OTG_GUSBCFG_FHMODE_Pos                                  (29U)
#define USB_OTG_GUSBCFG_FHMODE_Msk                                  (0x1UL << USB_OTG_GUSBCFG_FHMODE_Pos)                          /*!< 0x20000000 */
#define USB_OTG_GUSBCFG_FHMODE                                      USB_OTG_GUSBCFG_FHMODE_Msk                                     /*!< Forced host mode                */
#define USB_OTG_GUSBCFG_FDMODE_Pos                                  (30U)
#define USB_OTG_GUSBCFG_FDMODE_Msk                                  (0x1UL << USB_OTG_GUSBCFG_FDMODE_Pos)                          /*!< 0x40000000 */
#define USB_OTG_GUSBCFG_FDMODE                                      USB_OTG_GUSBCFG_FDMODE_Msk                                     /*!< Forced peripheral mode          */
#define USB_OTG_GUSBCFG_CTXP_Pos                                    (31U)
#define USB_OTG_GUSBCFG_CTXP_Msk                                    (0x1UL << USB_OTG_GUSBCFG_CTXP_Pos)                            /*!< 0x80000000 */
#define USB_OTG_GUSBCFG_CTXP                                        USB_OTG_GUSBCFG_CTXP_Msk                                       /*!< Corrupt Tx packet               */

/********************  Bit definition for USB_OTG_GRSTCTRL register  ********************/
#define USB_OTG_GRSTCTRL_CSRST_Pos                                  (0U)
#define USB_OTG_GRSTCTRL_CSRST_Msk                                  (0x1UL << USB_OTG_GRSTCTRL_CSRST_Pos)                          /*!< 0x00000001 */
#define USB_OTG_GRSTCTRL_CSRST                                      USB_OTG_GRSTCTRL_CSRST_Msk                                     /*!< Core soft reset          */
#define USB_OTG_GRSTCTRL_HSRST_Pos                                  (1U)
#define USB_OTG_GRSTCTRL_HSRST_Msk                                  (0x1UL << USB_OTG_GRSTCTRL_HSRST_Pos)                          /*!< 0x00000002 */
#define USB_OTG_GRSTCTRL_HSRST                                      USB_OTG_GRSTCTRL_HSRST_Msk                                     /*!< HCLK soft reset          */
#define USB_OTG_GRSTCTRL_HFCNTRST_Pos                               (2U)
#define USB_OTG_GRSTCTRL_HFCNTRST_Msk                               (0x1UL << USB_OTG_GRSTCTRL_HFCNTRST_Pos)                       /*!< 0x00000004 */
#define USB_OTG_GRSTCTRL_HFCNTRST                                   USB_OTG_GRSTCTRL_HFCNTRST_Msk                                  /*!< Host frame counter reset */
#define USB_OTG_GRSTCTRL_RXFFLU_Pos                                 (4U)
#define USB_OTG_GRSTCTRL_RXFFLU_Msk                                 (0x1UL << USB_OTG_GRSTCTRL_RXFFLU_Pos)                         /*!< 0x00000010 */
#define USB_OTG_GRSTCTRL_RXFFLU                                     USB_OTG_GRSTCTRL_RXFFLU_Msk                                    /*!< RxFIFO flush             */
#define USB_OTG_GRSTCTRL_TXFFLU_Pos                                 (5U)
#define USB_OTG_GRSTCTRL_TXFFLU_Msk                                 (0x1UL << USB_OTG_GRSTCTRL_TXFFLU_Pos)                         /*!< 0x00000020 */
#define USB_OTG_GRSTCTRL_TXFFLU                                     USB_OTG_GRSTCTRL_TXFFLU_Msk                                    /*!< TxFIFO flush             */


#define USB_OTG_GRSTCTRL_TXFNUM_Pos                                 (6U)
#define USB_OTG_GRSTCTRL_TXFNUM_Msk                                 (0x1FUL << USB_OTG_GRSTCTRL_TXFNUM_Pos)                        /*!< 0x000007C0 */
#define USB_OTG_GRSTCTRL_TXFNUM                                     USB_OTG_GRSTCTRL_TXFNUM_Msk                                    /*!< TxFIFO number */
#define USB_OTG_GRSTCTRL_TXFNUM_0                                   (0x01UL << USB_OTG_GRSTCTRL_TXFNUM_Pos)                        /*!< 0x00000040 */
#define USB_OTG_GRSTCTRL_TXFNUM_1                                   (0x02UL << USB_OTG_GRSTCTRL_TXFNUM_Pos)                        /*!< 0x00000080 */
#define USB_OTG_GRSTCTRL_TXFNUM_2                                   (0x04UL << USB_OTG_GRSTCTRL_TXFNUM_Pos)                        /*!< 0x00000100 */
#define USB_OTG_GRSTCTRL_TXFNUM_3                                   (0x08UL << USB_OTG_GRSTCTRL_TXFNUM_Pos)                        /*!< 0x00000200 */
#define USB_OTG_GRSTCTRL_TXFNUM_4                                   (0x10UL << USB_OTG_GRSTCTRL_TXFNUM_Pos)                        /*!< 0x00000400 */
#define USB_OTG_GRSTCTRL_DMAREQ_Pos                                 (30U)
#define USB_OTG_GRSTCTRL_DMAREQ_Msk                                 (0x1UL << USB_OTG_GRSTCTRL_DMAREQ_Pos)                         /*!< 0x40000000 */
#define USB_OTG_GRSTCTRL_DMAREQ                                     USB_OTG_GRSTCTRL_DMAREQ_Msk                                    /*!< DMA request signal */
#define USB_OTG_GRSTCTRL_AHBMIDL_Pos                                (31U)
#define USB_OTG_GRSTCTRL_AHBMIDL_Msk                                (0x1UL << USB_OTG_GRSTCTRL_AHBMIDL_Pos)                        /*!< 0x80000000 */
#define USB_OTG_GRSTCTRL_AHBMIDL                                    USB_OTG_GRSTCTRL_AHBMIDL_Msk                                   /*!< AHB master idle */

/********************  Bit definition for USB_OTG_DINIMASK register  ********************/
#define USB_OTG_DINIMASK_TSFCMPM_Pos                                (0U)
#define USB_OTG_DINIMASK_TSFCMPM_Msk                                (0x1UL << USB_OTG_DINIMASK_TSFCMPM_Pos)                        /*!< 0x00000001 */
#define USB_OTG_DINIMASK_TSFCMPM                                    USB_OTG_DINIMASK_TSFCMPM_Msk                                   /*!< Transfer completed interrupt mask                 */
#define USB_OTG_DINIMASK_EPDISM_Pos                                 (1U)
#define USB_OTG_DINIMASK_EPDISM_Msk                                 (0x1UL << USB_OTG_DINIMASK_EPDISM_Pos)                         /*!< 0x00000002 */
#define USB_OTG_DINIMASK_EPDISM                                     USB_OTG_DINIMASK_EPDISM_Msk                                    /*!< Endpoint disabled interrupt mask                  */
#define USB_OTG_DINIMASK_TOM_Pos                                    (3U)
#define USB_OTG_DINIMASK_TOM_Msk                                    (0x1UL << USB_OTG_DINIMASK_TOM_Pos)                            /*!< 0x00000008 */
#define USB_OTG_DINIMASK_TOM                                        USB_OTG_DINIMASK_TOM_Msk                                       /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DINIMASK_ITXEMPM_Pos                                (4U)
#define USB_OTG_DINIMASK_ITXEMPM_Msk                                (0x1UL << USB_OTG_DINIMASK_ITXEMPM_Pos)                        /*!< 0x00000010 */
#define USB_OTG_DINIMASK_ITXEMPM                                    USB_OTG_DINIMASK_ITXEMPM_Msk                                   /*!< IN token received when TxFIFO empty mask          */
#define USB_OTG_DINIMASK_IEPMMM_Pos                                 (5U)
#define USB_OTG_DINIMASK_IEPMMM_Msk                                 (0x1UL << USB_OTG_DINIMASK_IEPMMM_Pos)                         /*!< 0x00000020 */
#define USB_OTG_DINIMASK_IEPMMM                                     USB_OTG_DINIMASK_IEPMMM_Msk                                    /*!< IN token received with EP mismatch mask           */
#define USB_OTG_DINIMASK_IEPNAKEM_Pos                               (6U)
#define USB_OTG_DINIMASK_IEPNAKEM_Msk                               (0x1UL << USB_OTG_DINIMASK_IEPNAKEM_Pos)                       /*!< 0x00000040 */
#define USB_OTG_DINIMASK_IEPNAKEM                                   USB_OTG_DINIMASK_IEPNAKEM_Msk                                  /*!< IN endpoint NAK effective mask                    */
#define USB_OTG_DINIMASK_FUDRM_Pos                                  (8U)
#define USB_OTG_DINIMASK_FUDRM_Msk                                  (0x1UL << USB_OTG_DINIMASK_FUDRM_Pos)                          /*!< 0x00000100 */
#define USB_OTG_DINIMASK_FUDRM                                      USB_OTG_DINIMASK_FUDRM_Msk                                     /*!< FIFO underrun mask                                */
#define USB_OTG_DINIMASK_BNAM_Pos                                   (9U)
#define USB_OTG_DINIMASK_BNAM_Msk                                   (0x1UL << USB_OTG_DINIMASK_BNAM_Pos)                           /*!< 0x00000200 */
#define USB_OTG_DINIMASK_BNAM                                       USB_OTG_DINIMASK_BNAM_Msk                                      /*!< BNA interrupt mask                                */

/********************  Bit definition for USB_OTG_HPTXSTS register  ********************/
#define USB_OTG_HPTXSTS_FSPACE_Pos                                  (0U)
#define USB_OTG_HPTXSTS_FSPACE_Msk                                  (0xFFFFUL << USB_OTG_HPTXSTS_FSPACE_Pos)                       /*!< 0x0000FFFF */
#define USB_OTG_HPTXSTS_FSPACE                                      USB_OTG_HPTXSTS_FSPACE_Msk                                     /*!< Periodic transmit data FIFO space available     */
#define USB_OTG_HPTXSTS_QSPACE_Pos                                  (16U)
#define USB_OTG_HPTXSTS_QSPACE_Msk                                  (0xFFUL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00FF0000 */
#define USB_OTG_HPTXSTS_QSPACE                                      USB_OTG_HPTXSTS_QSPACE_Msk                                     /*!< Periodic transmit request queue space available */
#define USB_OTG_HPTXSTS_QSPACE_0                                    (0x01UL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00010000 */
#define USB_OTG_HPTXSTS_QSPACE_1                                    (0x02UL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00020000 */
#define USB_OTG_HPTXSTS_QSPACE_2                                    (0x04UL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00040000 */
#define USB_OTG_HPTXSTS_QSPACE_3                                    (0x08UL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00080000 */
#define USB_OTG_HPTXSTS_QSPACE_4                                    (0x10UL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00100000 */
#define USB_OTG_HPTXSTS_QSPACE_5                                    (0x20UL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00200000 */
#define USB_OTG_HPTXSTS_QSPACE_6                                    (0x40UL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00400000 */
#define USB_OTG_HPTXSTS_QSPACE_7                                    (0x80UL << USB_OTG_HPTXSTS_QSPACE_Pos)                         /*!< 0x00800000 */

#define USB_OTG_HPTXSTS_QTOP_Pos                                    (24U)
#define USB_OTG_HPTXSTS_QTOP_Msk                                    (0xFFUL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0xFF000000 */
#define USB_OTG_HPTXSTS_QTOP                                        USB_OTG_HPTXSTS_QTOP_Msk                                       /*!< Top of the periodic transmit request queue */
#define USB_OTG_HPTXSTS_QTOP_0                                      (0x01UL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0x01000000 */
#define USB_OTG_HPTXSTS_QTOP_1                                      (0x02UL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0x02000000 */
#define USB_OTG_HPTXSTS_QTOP_2                                      (0x04UL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0x04000000 */
#define USB_OTG_HPTXSTS_QTOP_3                                      (0x08UL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0x08000000 */
#define USB_OTG_HPTXSTS_QTOP_4                                      (0x10UL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0x10000000 */
#define USB_OTG_HPTXSTS_QTOP_5                                      (0x20UL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0x20000000 */
#define USB_OTG_HPTXSTS_QTOP_6                                      (0x40UL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0x40000000 */
#define USB_OTG_HPTXSTS_QTOP_7                                      (0x80UL << USB_OTG_HPTXSTS_QTOP_Pos)                           /*!< 0x80000000 */

/********************  Bit definition for USB_OTG_HACHINT register  ********************/
#define USB_OTG_HACHINT_ACHINT_Pos                                  (0U)
#define USB_OTG_HACHINT_ACHINT_Msk                                  (0xFFFFUL << USB_OTG_HACHINT_ACHINT_Pos)                       /*!< 0x0000FFFF */
#define USB_OTG_HACHINT_ACHINT                                      USB_OTG_HACHINT_ACHINT_Msk                                     /*!< Channel interrupts */

/********************  Bit definition for USB_OTG_DOUTIMASK register  ********************/
#define USB_OTG_DOUTIMASK_TSFCMPM_Pos                               (0U)
#define USB_OTG_DOUTIMASK_TSFCMPM_Msk                               (0x1UL << USB_OTG_DOUTIMASK_TSFCMPM_Pos)                       /*!< 0x00000001 */
#define USB_OTG_DOUTIMASK_TSFCMPM                                   USB_OTG_DOUTIMASK_TSFCMPM_Msk                                  /*!< Transfer completed interrupt mask              */
#define USB_OTG_DOUTIMASK_EPDISM_Pos                                (1U)
#define USB_OTG_DOUTIMASK_EPDISM_Msk                                (0x1UL << USB_OTG_DOUTIMASK_EPDISM_Pos)                        /*!< 0x00000002 */
#define USB_OTG_DOUTIMASK_EPDISM                                    USB_OTG_DOUTIMASK_EPDISM_Msk                                   /*!< Endpoint disabled interrupt mask               */
#define USB_OTG_DOUTIMASK_AHBERRIM_Pos                              (2U)
#define USB_OTG_DOUTIMASK_AHBERRIM_Msk                              (0x1UL << USB_OTG_DOUTIMASK_AHBERRIM_Pos)                      /*!< 0x00000004 */
#define USB_OTG_DOUTIMASK_AHBERRIM                                  USB_OTG_DOUTIMASK_AHBERRIM_Msk                                 /*!< OUT transaction AHB Error interrupt mask       */
#define USB_OTG_DOUTIMASK_SETPCMPM_Pos                              (3U)
#define USB_OTG_DOUTIMASK_SETPCMPM_Msk                              (0x1UL << USB_OTG_DOUTIMASK_SETPCMPM_Pos)                      /*!< 0x00000008 */
#define USB_OTG_DOUTIMASK_SETPCMPM                                  USB_OTG_DOUTIMASK_SETPCMPM_Msk                                 /*!< SETUP phase done mask                          */
#define USB_OTG_DOUTIMASK_OTXEMPM_Pos                               (4U)
#define USB_OTG_DOUTIMASK_OTXEMPM_Msk                               (0x1UL << USB_OTG_DOUTIMASK_OTXEMPM_Pos)                       /*!< 0x00000010 */
#define USB_OTG_DOUTIMASK_OTXEMPM                                   USB_OTG_DOUTIMASK_OTXEMPM_Msk                                  /*!< OUT token received when endpoint disabled mask */
#define USB_OTG_DOUTIMASK_OTEPSPRM_Pos                              (5U)
#define USB_OTG_DOUTIMASK_OTEPSPRM_Msk                              (0x1UL << USB_OTG_DOUTIMASK_OTEPSPRM_Pos)                      /*!< 0x00000020 */
#define USB_OTG_DOUTIMASK_OTEPSPRM                                  USB_OTG_DOUTIMASK_OTEPSPRM_Msk                                 /*!< Status Phase Received mask                     */
#define USB_OTG_DOUTIMASK_BTBSETM_Pos                               (6U)
#define USB_OTG_DOUTIMASK_BTBSETM_Msk                               (0x1UL << USB_OTG_DOUTIMASK_BTBSETM_Pos)                       /*!< 0x00000040 */
#define USB_OTG_DOUTIMASK_BTBSETM                                   USB_OTG_DOUTIMASK_BTBSETM_Msk                                  /*!< Back-to-back SETUP packets received mask       */
#define USB_OTG_DOUTIMASK_OPCKTERRM_Pos                             (8U)
#define USB_OTG_DOUTIMASK_OPCKTERRM_Msk                             (0x1UL << USB_OTG_DOUTIMASK_OPCKTERRM_Pos)                     /*!< 0x00000100 */
#define USB_OTG_DOUTIMASK_OPCKTERRM                                 USB_OTG_DOUTIMASK_OPCKTERRM_Msk                                /*!< OUT packet error mask                          */
#define USB_OTG_DOUTIMASK_BNAM_Pos                                  (9U)
#define USB_OTG_DOUTIMASK_BNAM_Msk                                  (0x1UL << USB_OTG_DOUTIMASK_BNAM_Pos)                          /*!< 0x00000200 */
#define USB_OTG_DOUTIMASK_BNAM                                      USB_OTG_DOUTIMASK_BNAM_Msk                                     /*!< BNA interrupt mask                             */
#define USB_OTG_DOUTIMASK_BERRM_Pos                                 (12U)
#define USB_OTG_DOUTIMASK_BERRM_Msk                                 (0x1UL << USB_OTG_DOUTIMASK_BERRM_Pos)                         /*!< 0x00001000 */
#define USB_OTG_DOUTIMASK_BERRM                                     USB_OTG_DOUTIMASK_BERRM_Msk                                    /*!< Babble error interrupt mask                   */
#define USB_OTG_DOUTIMASK_NAKM_Pos                                  (13U)
#define USB_OTG_DOUTIMASK_NAKM_Msk                                  (0x1UL << USB_OTG_DOUTIMASK_NAKM_Pos)                          /*!< 0x00002000 */
#define USB_OTG_DOUTIMASK_NAKM                                      USB_OTG_DOUTIMASK_NAKM_Msk                                     /*!< OUT Packet NAK interrupt mask                  */
#define USB_OTG_DOUTIMASK_NYETM_Pos                                 (14U)
#define USB_OTG_DOUTIMASK_NYETM_Msk                                 (0x1UL << USB_OTG_DOUTIMASK_NYETM_Pos)                         /*!< 0x00004000 */
#define USB_OTG_DOUTIMASK_NYETM                                     USB_OTG_DOUTIMASK_NYETM_Msk                                    /*!< NYET interrupt mask                            */
/********************  Bit definition for USB_OTG_GCINT register  ********************/
#define USB_OTG_GCINT_CURMOSEL_Pos                                  (0U)
#define USB_OTG_GCINT_CURMOSEL_Msk                                  (0x1UL << USB_OTG_GCINT_CURMOSEL_Pos)                          /*!< 0x00000001 */
#define USB_OTG_GCINT_CURMOSEL                                      USB_OTG_GCINT_CURMOSEL_Msk                                     /*!< Current mode of operation                      */
#define USB_OTG_GCINT_MMIS_Pos                                      (1U)
#define USB_OTG_GCINT_MMIS_Msk                                      (0x1UL << USB_OTG_GCINT_MMIS_Pos)                              /*!< 0x00000002 */
#define USB_OTG_GCINT_MMIS                                          USB_OTG_GCINT_MMIS_Msk                                         /*!< Mode mismatch interrupt                        */
#define USB_OTG_GCINT_OTG_Pos                                       (2U)
#define USB_OTG_GCINT_OTG_Msk                                       (0x1UL << USB_OTG_GCINT_OTG_Pos)                               /*!< 0x00000004 */
#define USB_OTG_GCINT_OTG                                           USB_OTG_GCINT_OTG_Msk                                          /*!< OTG interrupt                                  */
#define USB_OTG_GCINT_SOF_Pos                                       (3U)
#define USB_OTG_GCINT_SOF_Msk                                       (0x1UL << USB_OTG_GCINT_SOF_Pos)                               /*!< 0x00000008 */
#define USB_OTG_GCINT_SOF                                           USB_OTG_GCINT_SOF_Msk                                          /*!< Start of frame                                 */
#define USB_OTG_GCINT_RXFNONE_Pos                                   (4U)
#define USB_OTG_GCINT_RXFNONE_Msk                                   (0x1UL << USB_OTG_GCINT_RXFNONE_Pos)                           /*!< 0x00000010 */
#define USB_OTG_GCINT_RXFNONE                                       USB_OTG_GCINT_RXFNONE_Msk                                      /*!< RxFIFO nonempty                                */
#define USB_OTG_GCINT_NPTXFEM_Pos                                   (5U)
#define USB_OTG_GCINT_NPTXFEM_Msk                                   (0x1UL << USB_OTG_GCINT_NPTXFEM_Pos)                           /*!< 0x00000020 */
#define USB_OTG_GCINT_NPTXFEM                                       USB_OTG_GCINT_NPTXFEM_Msk                                      /*!< Nonperiodic TxFIFO empty                       */
#define USB_OTG_GCINT_GINNPNAKE_Pos                                 (6U)
#define USB_OTG_GCINT_GINNPNAKE_Msk                                 (0x1UL << USB_OTG_GCINT_GINNPNAKE_Pos)                         /*!< 0x00000040 */
#define USB_OTG_GCINT_GINNPNAKE                                     USB_OTG_GCINT_GINNPNAKE_Msk                                    /*!< Global IN nonperiodic NAK effective            */
#define USB_OTG_GCINT_GONAKE_Pos                                    (7U)
#define USB_OTG_GCINT_GONAKE_Msk                                    (0x1UL << USB_OTG_GCINT_GONAKE_Pos)                            /*!< 0x00000080 */
#define USB_OTG_GCINT_GONAKE                                        USB_OTG_GCINT_GONAKE_Msk                                       /*!< Global OUT NAK effective                       */
#define USB_OTG_GCINT_ESUS_Pos                                      (10U)
#define USB_OTG_GCINT_ESUS_Msk                                      (0x1UL << USB_OTG_GCINT_ESUS_Pos)                              /*!< 0x00000400 */
#define USB_OTG_GCINT_ESUS                                          USB_OTG_GCINT_ESUS_Msk                                         /*!< Early suspend                                  */
#define USB_OTG_GCINT_USBSUS_Pos                                    (11U)
#define USB_OTG_GCINT_USBSUS_Msk                                    (0x1UL << USB_OTG_GCINT_USBSUS_Pos)                            /*!< 0x00000800 */
#define USB_OTG_GCINT_USBSUS                                        USB_OTG_GCINT_USBSUS_Msk                                       /*!< USB suspend                                    */
#define USB_OTG_GCINT_USBRST_Pos                                    (12U)
#define USB_OTG_GCINT_USBRST_Msk                                    (0x1UL << USB_OTG_GCINT_USBRST_Pos)                            /*!< 0x00001000 */
#define USB_OTG_GCINT_USBRST                                        USB_OTG_GCINT_USBRST_Msk                                       /*!< USB reset                                      */
#define USB_OTG_GCINT_ENUMD_Pos                                     (13U)
#define USB_OTG_GCINT_ENUMD_Msk                                     (0x1UL << USB_OTG_GCINT_ENUMD_Pos)                             /*!< 0x00002000 */
#define USB_OTG_GCINT_ENUMD                                         USB_OTG_GCINT_ENUMD_Msk                                        /*!< Enumeration done                               */
#define USB_OTG_GCINT_ISOPD_Pos                                     (14U)
#define USB_OTG_GCINT_ISOPD_Msk                                     (0x1UL << USB_OTG_GCINT_ISOPD_Pos)                             /*!< 0x00004000 */
#define USB_OTG_GCINT_ISOPD                                         USB_OTG_GCINT_ISOPD_Msk                                        /*!< Isochronous OUT packet dropped interrupt       */
#define USB_OTG_GCINT_EOPF_Pos                                      (15U)
#define USB_OTG_GCINT_EOPF_Msk                                      (0x1UL << USB_OTG_GCINT_EOPF_Pos)                              /*!< 0x00008000 */
#define USB_OTG_GCINT_EOPF                                          USB_OTG_GCINT_EOPF_Msk                                         /*!< End of periodic frame interrupt                */
#define USB_OTG_GCINT_INEP_Pos                                      (18U)
#define USB_OTG_GCINT_INEP_Msk                                      (0x1UL << USB_OTG_GCINT_INEP_Pos)                              /*!< 0x00040000 */
#define USB_OTG_GCINT_INEP                                          USB_OTG_GCINT_INEP_Msk                                         /*!< IN endpoint interrupt                          */
#define USB_OTG_GCINT_ONEP_Pos                                      (19U)
#define USB_OTG_GCINT_ONEP_Msk                                      (0x1UL << USB_OTG_GCINT_ONEP_Pos)                              /*!< 0x00080000 */
#define USB_OTG_GCINT_ONEP                                          USB_OTG_GCINT_ONEP_Msk                                         /*!< OUT endpoint interrupt                         */
#define USB_OTG_GCINT_IIINTX_Pos                                    (20U)
#define USB_OTG_GCINT_IIINTX_Msk                                    (0x1UL << USB_OTG_GCINT_IIINTX_Pos)                            /*!< 0x00100000 */
#define USB_OTG_GCINT_IIINTX                                        USB_OTG_GCINT_IIINTX_Msk                                       /*!< Incomplete isochronous IN transfer             */
#define USB_OTG_GCINT_IP_OUTTX_Pos                                  (21U)
#define USB_OTG_GCINT_IP_OUTTX_Msk                                  (0x1UL << USB_OTG_GCINT_IP_OUTTX_Pos)                          /*!< 0x00200000 */
#define USB_OTG_GCINT_IP_OUTTX                                      USB_OTG_GCINT_IP_OUTTX_Msk                                     /*!< Incomplete periodic transfer                   */
#define USB_OTG_GCINT_DFSUS_Pos                                     (22U)
#define USB_OTG_GCINT_DFSUS_Msk                                     (0x1UL << USB_OTG_GCINT_DFSUS_Pos)                             /*!< 0x00400000 */
#define USB_OTG_GCINT_DFSUS                                         USB_OTG_GCINT_DFSUS_Msk                                        /*!< Data fetch suspended                           */
#define USB_OTG_GCINT_HPORT_Pos                                     (24U)
#define USB_OTG_GCINT_HPORT_Msk                                     (0x1UL << USB_OTG_GCINT_HPORT_Pos)                             /*!< 0x01000000 */
#define USB_OTG_GCINT_HPORT                                         USB_OTG_GCINT_HPORT_Msk                                        /*!< Host port interrupt                            */
#define USB_OTG_GCINT_HCHAN_Pos                                     (25U)
#define USB_OTG_GCINT_HCHAN_Msk                                     (0x1UL << USB_OTG_GCINT_HCHAN_Pos)                             /*!< 0x02000000 */
#define USB_OTG_GCINT_HCHAN                                         USB_OTG_GCINT_HCHAN_Msk                                        /*!< Host channels interrupt                        */
#define USB_OTG_GCINT_PTXFE_Pos                                     (26U)
#define USB_OTG_GCINT_PTXFE_Msk                                     (0x1UL << USB_OTG_GCINT_PTXFE_Pos)                             /*!< 0x04000000 */
#define USB_OTG_GCINT_PTXFE                                         USB_OTG_GCINT_PTXFE_Msk                                        /*!< Periodic TxFIFO empty                          */
#define USB_OTG_GCINT_CINSTSC_Pos                                   (28U)
#define USB_OTG_GCINT_CINSTSC_Msk                                   (0x1UL << USB_OTG_GCINT_CINSTSC_Pos)                           /*!< 0x10000000 */
#define USB_OTG_GCINT_CINSTSC                                       USB_OTG_GCINT_CINSTSC_Msk                                      /*!< Connector ID status change                     */
#define USB_OTG_GCINT_DEDIS_Pos                                     (29U)
#define USB_OTG_GCINT_DEDIS_Msk                                     (0x1UL << USB_OTG_GCINT_DEDIS_Pos)                             /*!< 0x20000000 */
#define USB_OTG_GCINT_DEDIS                                         USB_OTG_GCINT_DEDIS_Msk                                        /*!< Disconnect detected interrupt                  */
#define USB_OTG_GCINT_SREQ_Pos                                      (30U)
#define USB_OTG_GCINT_SREQ_Msk                                      (0x1UL << USB_OTG_GCINT_SREQ_Pos)                              /*!< 0x40000000 */
#define USB_OTG_GCINT_SREQ                                          USB_OTG_GCINT_SREQ_Msk                                         /*!< Session request/new session detected interrupt */
#define USB_OTG_GCINT_RWAKE_Pos                                     (31U)
#define USB_OTG_GCINT_RWAKE_Msk                                     (0x1UL << USB_OTG_GCINT_RWAKE_Pos)                             /*!< 0x80000000 */
#define USB_OTG_GCINT_RWAKE                                         USB_OTG_GCINT_RWAKE_Msk                                        /*!< Resume/remote wakeup detected interrupt        */

/********************  Bit definition for USB_OTG_GINTMASK register  ********************/
#define USB_OTG_GINTMASK_MMISM_Pos                                  (1U)
#define USB_OTG_GINTMASK_MMISM_Msk                                  (0x1UL << USB_OTG_GINTMASK_MMISM_Pos)                          /*!< 0x00000002 */
#define USB_OTG_GINTMASK_MMISM                                      USB_OTG_GINTMASK_MMISM_Msk                                     /*!< Mode mismatch interrupt mask                        */
#define USB_OTG_GINTMASK_OTGM_Pos                                   (2U)
#define USB_OTG_GINTMASK_OTGM_Msk                                   (0x1UL << USB_OTG_GINTMASK_OTGM_Pos)                           /*!< 0x00000004 */
#define USB_OTG_GINTMASK_OTGM                                       USB_OTG_GINTMASK_OTGM_Msk                                      /*!< OTG interrupt mask                                  */
#define USB_OTG_GINTMASK_SOFM_Pos                                   (3U)
#define USB_OTG_GINTMASK_SOFM_Msk                                   (0x1UL << USB_OTG_GINTMASK_SOFM_Pos)                           /*!< 0x00000008 */
#define USB_OTG_GINTMASK_SOFM                                       USB_OTG_GINTMASK_SOFM_Msk                                      /*!< Start of frame mask                                 */
#define USB_OTG_GINTMASK_RXFNONEM_Pos                               (4U)
#define USB_OTG_GINTMASK_RXFNONEM_Msk                               (0x1UL << USB_OTG_GINTMASK_RXFNONEM_Pos)                       /*!< 0x00000010 */
#define USB_OTG_GINTMASK_RXFNONEM                                   USB_OTG_GINTMASK_RXFNONEM_Msk                                  /*!< Receive FIFO nonempty mask                          */
#define USB_OTG_GINTMASK_NPTXFEMM_Pos                               (5U)
#define USB_OTG_GINTMASK_NPTXFEMM_Msk                               (0x1UL << USB_OTG_GINTMASK_NPTXFEMM_Pos)                       /*!< 0x00000020 */
#define USB_OTG_GINTMASK_NPTXFEMM                                   USB_OTG_GINTMASK_NPTXFEMM_Msk                                  /*!< Nonperiodic TxFIFO empty mask                       */
#define USB_OTG_GINTMASK_GINNPNAKEM_Pos                             (6U)
#define USB_OTG_GINTMASK_GINNPNAKEM_Msk                             (0x1UL << USB_OTG_GINTMASK_GINNPNAKEM_Pos)                     /*!< 0x00000040 */
#define USB_OTG_GINTMASK_GINNPNAKEM                                 USB_OTG_GINTMASK_GINNPNAKEM_Msk                                /*!< Global nonperiodic IN NAK effective mask            */
#define USB_OTG_GINTMASK_GONAKEM_Pos                                (7U)
#define USB_OTG_GINTMASK_GONAKEM_Msk                                (0x1UL << USB_OTG_GINTMASK_GONAKEM_Pos)                        /*!< 0x00000080 */
#define USB_OTG_GINTMASK_GONAKEM                                    USB_OTG_GINTMASK_GONAKEM_Msk                                   /*!< Global OUT NAK effective mask                       */
#define USB_OTG_GINTMASK_ESUSM_Pos                                  (10U)
#define USB_OTG_GINTMASK_ESUSM_Msk                                  (0x1UL << USB_OTG_GINTMASK_ESUSM_Pos)                          /*!< 0x00000400 */
#define USB_OTG_GINTMASK_ESUSM                                      USB_OTG_GINTMASK_ESUSM_Msk                                     /*!< Early suspend mask                                  */
#define USB_OTG_GINTMASK_USBSUSM_Pos                                (11U)
#define USB_OTG_GINTMASK_USBSUSM_Msk                                (0x1UL << USB_OTG_GINTMASK_USBSUSM_Pos)                        /*!< 0x00000800 */
#define USB_OTG_GINTMASK_USBSUSM                                    USB_OTG_GINTMASK_USBSUSM_Msk                                   /*!< USB suspend mask                                    */
#define USB_OTG_GINTMASK_USBRSTM_Pos                                (12U)
#define USB_OTG_GINTMASK_USBRSTM_Msk                                (0x1UL << USB_OTG_GINTMASK_USBRSTM_Pos)                        /*!< 0x00001000 */
#define USB_OTG_GINTMASK_USBRSTM                                    USB_OTG_GINTMASK_USBRSTM_Msk                                   /*!< USB reset mask                                      */
#define USB_OTG_GINTMASK_ENUMDM_Pos                                 (13U)
#define USB_OTG_GINTMASK_ENUMDM_Msk                                 (0x1UL << USB_OTG_GINTMASK_ENUMDM_Pos)                         /*!< 0x00002000 */
#define USB_OTG_GINTMASK_ENUMDM                                     USB_OTG_GINTMASK_ENUMDM_Msk                                    /*!< Enumeration done mask                               */
#define USB_OTG_GINTMASK_ISOPDM_Pos                                 (14U)
#define USB_OTG_GINTMASK_ISOPDM_Msk                                 (0x1UL << USB_OTG_GINTMASK_ISOPDM_Pos)                         /*!< 0x00004000 */
#define USB_OTG_GINTMASK_ISOPDM                                     USB_OTG_GINTMASK_ISOPDM_Msk                                    /*!< Isochronous OUT packet dropped interrupt mask       */
#define USB_OTG_GINTMASK_EOPFM_Pos                                  (15U)
#define USB_OTG_GINTMASK_EOPFM_Msk                                  (0x1UL << USB_OTG_GINTMASK_EOPFM_Pos)                          /*!< 0x00008000 */
#define USB_OTG_GINTMASK_EOPFM                                      USB_OTG_GINTMASK_EOPFM_Msk                                     /*!< End of periodic frame interrupt mask                */
#define USB_OTG_GINTMASK_EPMISM_Pos                                 (17U)
#define USB_OTG_GINTMASK_EPMISM_Msk                                 (0x1UL << USB_OTG_GINTMASK_EPMISM_Pos)                         /*!< 0x00020000 */
#define USB_OTG_GINTMASK_EPMISM                                     USB_OTG_GINTMASK_EPMISM_Msk                                    /*!< Endpoint mismatch interrupt mask                    */
#define USB_OTG_GINTMASK_INEPM_Pos                                  (18U)
#define USB_OTG_GINTMASK_INEPM_Msk                                  (0x1UL << USB_OTG_GINTMASK_INEPM_Pos)                          /*!< 0x00040000 */
#define USB_OTG_GINTMASK_INEPM                                      USB_OTG_GINTMASK_INEPM_Msk                                     /*!< IN endpoints interrupt mask                         */
#define USB_OTG_GINTMASK_OUTEPM_Pos                                 (19U)
#define USB_OTG_GINTMASK_OUTEPM_Msk                                 (0x1UL << USB_OTG_GINTMASK_OUTEPM_Pos)                         /*!< 0x00080000 */
#define USB_OTG_GINTMASK_OUTEPM                                     USB_OTG_GINTMASK_OUTEPM_Msk                                    /*!< OUT endpoints interrupt mask                        */
#define USB_OTG_GINTMASK_IIINTXM_Pos                                (20U)
#define USB_OTG_GINTMASK_IIINTXM_Msk                                (0x1UL << USB_OTG_GINTMASK_IIINTXM_Pos)                        /*!< 0x00100000 */
#define USB_OTG_GINTMASK_IIINTXM                                    USB_OTG_GINTMASK_IIINTXM_Msk                                   /*!< Incomplete isochronous IN transfer mask             */
#define USB_OTG_GINTMASK_IP_OUTTXM_Pos                              (21U)
#define USB_OTG_GINTMASK_IP_OUTTXM_Msk                              (0x1UL << USB_OTG_GINTMASK_IP_OUTTXM_Pos)                      /*!< 0x00200000 */
#define USB_OTG_GINTMASK_IP_OUTTXM                                  USB_OTG_GINTMASK_IP_OUTTXM_Msk                                 /*!< Incomplete periodic transfer mask                   */
#define USB_OTG_GINTMASK_DFSUSM_Pos                                 (22U)
#define USB_OTG_GINTMASK_DFSUSM_Msk                                 (0x1UL << USB_OTG_GINTMASK_DFSUSM_Pos)                         /*!< 0x00400000 */
#define USB_OTG_GINTMASK_DFSUSM                                     USB_OTG_GINTMASK_DFSUSM_Msk                                    /*!< Data fetch suspended mask                           */
#define USB_OTG_GINTMASK_HPORTM_Pos                                 (24U)
#define USB_OTG_GINTMASK_HPORTM_Msk                                 (0x1UL << USB_OTG_GINTMASK_HPORTM_Pos)                         /*!< 0x01000000 */
#define USB_OTG_GINTMASK_HPORTM                                     USB_OTG_GINTMASK_HPORTM_Msk                                    /*!< Host port interrupt mask                            */
#define USB_OTG_GINTMASK_HCHM_Pos                                   (25U)
#define USB_OTG_GINTMASK_HCHM_Msk                                   (0x1UL << USB_OTG_GINTMASK_HCHM_Pos)                           /*!< 0x02000000 */
#define USB_OTG_GINTMASK_HCHM                                       USB_OTG_GINTMASK_HCHM_Msk                                      /*!< Host channels interrupt mask                        */
#define USB_OTG_GINTMASK_PTXFEM_Pos                                 (26U)
#define USB_OTG_GINTMASK_PTXFEM_Msk                                 (0x1UL << USB_OTG_GINTMASK_PTXFEM_Pos)                         /*!< 0x04000000 */
#define USB_OTG_GINTMASK_PTXFEM                                     USB_OTG_GINTMASK_PTXFEM_Msk                                    /*!< Periodic TxFIFO empty mask                          */
#define USB_OTG_GINTMASK_CIDSTSCM_Pos                               (28U)
#define USB_OTG_GINTMASK_CIDSTSCM_Msk                               (0x1UL << USB_OTG_GINTMASK_CIDSTSCM_Pos)                       /*!< 0x10000000 */
#define USB_OTG_GINTMASK_CIDSTSCM                                   USB_OTG_GINTMASK_CIDSTSCM_Msk                                  /*!< Connector ID status change mask                     */
#define USB_OTG_GINTMASK_DEDISM_Pos                                 (29U)
#define USB_OTG_GINTMASK_DEDISM_Msk                                 (0x1UL << USB_OTG_GINTMASK_DEDISM_Pos)                         /*!< 0x20000000 */
#define USB_OTG_GINTMASK_DEDISM                                     USB_OTG_GINTMASK_DEDISM_Msk                                    /*!< Disconnect detected interrupt mask                  */
#define USB_OTG_GINTMASK_SREQM_Pos                                  (30U)
#define USB_OTG_GINTMASK_SREQM_Msk                                  (0x1UL << USB_OTG_GINTMASK_SREQM_Pos)                          /*!< 0x40000000 */
#define USB_OTG_GINTMASK_SREQM                                      USB_OTG_GINTMASK_SREQM_Msk                                     /*!< Session request/new session detected interrupt mask */
#define USB_OTG_GINTMASK_RWAKEM_Pos                                 (31U)
#define USB_OTG_GINTMASK_RWAKEM_Msk                                 (0x1UL << USB_OTG_GINTMASK_RWAKEM_Pos)                         /*!< 0x80000000 */
#define USB_OTG_GINTMASK_RWAKEM                                     USB_OTG_GINTMASK_RWAKEM_Msk                                    /*!< Resume/remote wakeup detected interrupt mask        */

/********************  Bit definition for USB_OTG_DAEPINT register  ********************/
#define USB_OTG_DAEPINT_INEPINT_Pos                                 (0U)
#define USB_OTG_DAEPINT_INEPINT_Msk                                 (0xFFFFUL << USB_OTG_DAEPINT_INEPINT_Pos)                      /*!< 0x0000FFFF */
#define USB_OTG_DAEPINT_INEPINT                                     USB_OTG_DAEPINT_INEPINT_Msk                                    /*!< IN endpoint interrupt bits  */
#define USB_OTG_DAEPINT_OUTEPINT_Pos                                (16U)
#define USB_OTG_DAEPINT_OUTEPINT_Msk                                (0xFFFFUL << USB_OTG_DAEPINT_OUTEPINT_Pos)                     /*!< 0xFFFF0000 */
#define USB_OTG_DAEPINT_OUTEPINT                                    USB_OTG_DAEPINT_OUTEPINT_Msk                                   /*!< OUT endpoint interrupt bits */

/********************  Bit definition for USB_OTG_HACHIMASK register  ********************/
#define USB_OTG_HACHIMASK_ACHIMASK_Pos                              (0U)
#define USB_OTG_HACHIMASK_ACHIMASK_Msk                              (0xFFFFUL << USB_OTG_HACHIMASK_ACHIMASK_Pos)                   /*!< 0x0000FFFF */
#define USB_OTG_HACHIMASK_ACHIMASK                                  USB_OTG_HACHIMASK_ACHIMASK_Msk                                 /*!< Channel interrupt mask */

/********************  Bit definition for USB_OTG_GRXSTSP register  ********************/
#define USB_OTG_GRXSTSP_EPNUM_Pos                                   (0U)
#define USB_OTG_GRXSTSP_EPNUM_Msk                                   (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos)                           /*!< 0x0000000F */
#define USB_OTG_GRXSTSP_EPNUM                                       USB_OTG_GRXSTSP_EPNUM_Msk                                      /*!< IN EP interrupt mask bits  */
#define USB_OTG_GRXSTSP_BCNT_Pos                                    (4U)
#define USB_OTG_GRXSTSP_BCNT_Msk                                    (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos)                          /*!< 0x00007FF0 */
#define USB_OTG_GRXSTSP_BCNT                                        USB_OTG_GRXSTSP_BCNT_Msk                                       /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_DPID_Pos                                    (15U)
#define USB_OTG_GRXSTSP_DPID_Msk                                    (0x3UL << USB_OTG_GRXSTSP_DPID_Pos)                            /*!< 0x00018000 */
#define USB_OTG_GRXSTSP_DPID                                        USB_OTG_GRXSTSP_DPID_Msk                                       /*!< OUT EP interrupt mask bits */
#define USB_OTG_GRXSTSP_PSTS_Pos                                    (17U)
#define USB_OTG_GRXSTSP_PSTS_Msk                                    (0xFUL << USB_OTG_GRXSTSP_PSTS_Pos)                            /*!< 0x001E0000 */
#define USB_OTG_GRXSTSP_PSTS                                        USB_OTG_GRXSTSP_PSTS_Msk                                       /*!< OUT EP interrupt mask bits */

/********************  Bit definition for USB_OTG_DAEPIMASK register  ********************/
#define USB_OTG_DAEPIMASK_AINM_Pos                                  (0U)
#define USB_OTG_DAEPIMASK_AINM_Msk                                  (0xFFFFUL << USB_OTG_DAEPIMASK_AINM_Pos)                       /*!< 0x0000FFFF */
#define USB_OTG_DAEPIMASK_AINM                                      USB_OTG_DAEPIMASK_AINM_Msk                                     /*!< IN EP interrupt mask bits */
#define USB_OTG_DAEPIMASK_AOUTM_Pos                                 (16U)
#define USB_OTG_DAEPIMASK_AOUTM_Msk                                 (0xFFFFUL << USB_OTG_DAEPIMASK_AOUTM_Pos)                      /*!< 0xFFFF0000 */
#define USB_OTG_DAEPIMASK_AOUTM                                     USB_OTG_DAEPIMASK_AOUTM_Msk                                    /*!< OUT EP interrupt mask bits */

/********************  Bit definition for USB_OTG_GRXFIFO register  ********************/
#define USB_OTG_GRXFIFO_RXFDEP_Pos                                  (0U)
#define USB_OTG_GRXFIFO_RXFDEP_Msk                                  (0xFFFFUL << USB_OTG_GRXFIFO_RXFDEP_Pos)                       /*!< 0x0000FFFF */
#define USB_OTG_GRXFIFO_RXFDEP                                      USB_OTG_GRXFIFO_RXFDEP_Msk                                     /*!< RxFIFO depth */

/********************  Bit definition for USB_OTG_DVBUSDTIM register  ********************/
#define USB_OTG_DVBUSDTIM_VBUSDTIM_Pos                              (0U)
#define USB_OTG_DVBUSDTIM_VBUSDTIM_Msk                              (0xFFFFUL << USB_OTG_DVBUSDTIM_VBUSDTIM_Pos)                   /*!< 0x0000FFFF */
#define USB_OTG_DVBUSDTIM_VBUSDTIM                                  USB_OTG_DVBUSDTIM_VBUSDTIM_Msk                                 /*!< Device VBUS discharge time */

/********************  Bit definition for OTG register  ********************/
#define USB_OTG_NPTXSA_Pos                                          (0U)
#define USB_OTG_NPTXSA_Msk                                          (0xFFFFUL << USB_OTG_NPTXSA_Pos)                               /*!< 0x0000FFFF */
#define USB_OTG_NPTXSA                                              USB_OTG_NPTXSA_Msk                                             /*!< Nonperiodic transmit RAM start address */
#define USB_OTG_NPTXFDEP_Pos                                        (16U)
#define USB_OTG_NPTXFDEP_Msk                                        (0xFFFFUL << USB_OTG_NPTXFDEP_Pos)                             /*!< 0xFFFF0000 */
#define USB_OTG_NPTXFDEP                                            USB_OTG_NPTXFDEP_Msk                                           /*!< Nonperiodic TxFIFO depth               */
#define USB_OTG_TX0FSA_Pos                                          (0U)
#define USB_OTG_TX0FSA_Msk                                          (0xFFFFUL << USB_OTG_TX0FSA_Pos)                               /*!< 0x0000FFFF */
#define USB_OTG_TX0FSA                                              USB_OTG_TX0FSA_Msk                                             /*!< Endpoint 0 transmit RAM start address  */
#define USB_OTG_TX0FD_Pos                                           (16U)
#define USB_OTG_TX0FD_Msk                                           (0xFFFFUL << USB_OTG_TX0FD_Pos)                                /*!< 0xFFFF0000 */
#define USB_OTG_TX0FD                                               USB_OTG_TX0FD_Msk                                              /*!< Endpoint 0 TxFIFO depth                */

/********************  Bit definition forUSB_OTG_DVBUSPTIM register  ********************/
#define USB_OTG_DVBUSPTIM_VBUSPTIM_Pos                              (0U)
#define USB_OTG_DVBUSPTIM_VBUSPTIM_Msk                              (0xFFFUL << USB_OTG_DVBUSPTIM_VBUSPTIM_Pos)                    /*!< 0x00000FFF */
#define USB_OTG_DVBUSPTIM_VBUSPTIM                                  USB_OTG_DVBUSPTIM_VBUSPTIM_Msk                                 /*!< Device VBUS pulsing time */

/********************  Bit definition for USB_OTG_GNPTXFQSTS register  ********************/
#define USB_OTG_GNPTXFQSTS_NPTXFSA_Pos                              (0U)
#define USB_OTG_GNPTXFQSTS_NPTXFSA_Msk                              (0xFFFFUL << USB_OTG_GNPTXFQSTS_NPTXFSA_Pos)                   /*!< 0x0000FFFF */
#define USB_OTG_GNPTXFQSTS_NPTXFSA                                  USB_OTG_GNPTXFQSTS_NPTXFSA_Msk                                 /*!< Nonperiodic TxFIFO space available */

#define USB_OTG_GNPTXFQSTS_NPTXRSA_Pos                              (16U)
#define USB_OTG_GNPTXFQSTS_NPTXRSA_Msk                              (0xFFUL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00FF0000 */
#define USB_OTG_GNPTXFQSTS_NPTXRSA                                  USB_OTG_GNPTXFQSTS_NPTXRSA_Msk                                 /*!< Nonperiodic transmit request queue space available */
#define USB_OTG_GNPTXFQSTS_NPTXRSA_0                                (0x01UL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00010000 */
#define USB_OTG_GNPTXFQSTS_NPTXRSA_1                                (0x02UL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00020000 */
#define USB_OTG_GNPTXFQSTS_NPTXRSA_2                                (0x04UL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00040000 */
#define USB_OTG_GNPTXFQSTS_NPTXRSA_3                                (0x08UL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00080000 */
#define USB_OTG_GNPTXFQSTS_NPTXRSA_4                                (0x10UL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00100000 */
#define USB_OTG_GNPTXFQSTS_NPTXRSA_5                                (0x20UL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00200000 */
#define USB_OTG_GNPTXFQSTS_NPTXRSA_6                                (0x40UL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00400000 */
#define USB_OTG_GNPTXFQSTS_NPTXRSA_7                                (0x80UL << USB_OTG_GNPTXFQSTS_NPTXRSA_Pos)                     /*!< 0x00800000 */

#define USB_OTG_GNPTXFQSTS_NPTXRQ_Pos                               (24U)
#define USB_OTG_GNPTXFQSTS_NPTXRQ_Msk                               (0x7FUL << USB_OTG_GNPTXFQSTS_NPTXRQ_Pos)                      /*!< 0x7F000000 */
#define USB_OTG_GNPTXFQSTS_NPTXRQ                                   USB_OTG_GNPTXFQSTS_NPTXRQ_Msk                                  /*!< Top of the nonperiodic transmit request queue */
#define USB_OTG_GNPTXFQSTS_NPTXRQ_0                                 (0x01UL << USB_OTG_GNPTXFQSTS_NPTXRQ_Pos)                      /*!< 0x01000000 */
#define USB_OTG_GNPTXFQSTS_NPTXRQ_1                                 (0x02UL << USB_OTG_GNPTXFQSTS_NPTXRQ_Pos)                      /*!< 0x02000000 */
#define USB_OTG_GNPTXFQSTS_NPTXRQ_2                                 (0x04UL << USB_OTG_GNPTXFQSTS_NPTXRQ_Pos)                      /*!< 0x04000000 */
#define USB_OTG_GNPTXFQSTS_NPTXRQ_3                                 (0x08UL << USB_OTG_GNPTXFQSTS_NPTXRQ_Pos)                      /*!< 0x08000000 */
#define USB_OTG_GNPTXFQSTS_NPTXRQ_4                                 (0x10UL << USB_OTG_GNPTXFQSTS_NPTXRQ_Pos)                      /*!< 0x10000000 */
#define USB_OTG_GNPTXFQSTS_NPTXRQ_5                                 (0x20UL << USB_OTG_GNPTXFQSTS_NPTXRQ_Pos)                      /*!< 0x20000000 */
#define USB_OTG_GNPTXFQSTS_NPTXRQ_6                                 (0x40UL << USB_OTG_GNPTXFQSTS_NPTXRQ_Pos)                      /*!< 0x40000000 */

/********************  Bit definition for USB_OTG_DTHCTRL register  ********************/
#define USB_OTG_DTHCTRL_NSINTHEN_Pos                                (0U)
#define USB_OTG_DTHCTRL_NSINTHEN_Msk                                (0x1UL << USB_OTG_DTHCTRL_NSINTHEN_Pos)                        /*!< 0x00000001 */
#define USB_OTG_DTHCTRL_NSINTHEN                                    USB_OTG_DTHCTRL_NSINTHEN_Msk                                   /*!< Nonisochronous IN endpoints threshold enable */
#define USB_OTG_DTHCTRL_SINTHEN_Pos                                 (1U)
#define USB_OTG_DTHCTRL_SINTHEN_Msk                                 (0x1UL << USB_OTG_DTHCTRL_SINTHEN_Pos)                         /*!< 0x00000002 */
#define USB_OTG_DTHCTRL_SINTHEN                                     USB_OTG_DTHCTRL_SINTHEN_Msk                                    /*!< ISO IN endpoint threshold enable */

#define USB_OTG_DTHCTRL_TXTHLTH_Pos                                 (2U)
#define USB_OTG_DTHCTRL_TXTHLTH_Msk                                 (0x1FFUL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x000007FC */
#define USB_OTG_DTHCTRL_TXTHLTH                                     USB_OTG_DTHCTRL_TXTHLTH_Msk                                    /*!< Transmit threshold length */
#define USB_OTG_DTHCTRL_TXTHLTH_0                                   (0x001UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000004 */
#define USB_OTG_DTHCTRL_TXTHLTH_1                                   (0x002UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000008 */
#define USB_OTG_DTHCTRL_TXTHLTH_2                                   (0x004UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000010 */
#define USB_OTG_DTHCTRL_TXTHLTH_3                                   (0x008UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000020 */
#define USB_OTG_DTHCTRL_TXTHLTH_4                                   (0x010UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000040 */
#define USB_OTG_DTHCTRL_TXTHLTH_5                                   (0x020UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000080 */
#define USB_OTG_DTHCTRL_TXTHLTH_6                                   (0x040UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000100 */
#define USB_OTG_DTHCTRL_TXTHLTH_7                                   (0x080UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000200 */
#define USB_OTG_DTHCTRL_TXTHLTH_8                                   (0x100UL << USB_OTG_DTHCTRL_TXTHLTH_Pos)                       /*!< 0x00000400 */
#define USB_OTG_DTHCTRL_RXTHEN_Pos                                  (16U)
#define USB_OTG_DTHCTRL_RXTHEN_Msk                                  (0x1UL << USB_OTG_DTHCTRL_RXTHEN_Pos)                          /*!< 0x00010000 */
#define USB_OTG_DTHCTRL_RXTHEN                                      USB_OTG_DTHCTRL_RXTHEN_Msk                                     /*!< Receive threshold enable */

#define USB_OTG_DTHCTRL_RXTHLTH_Pos                                 (17U)
#define USB_OTG_DTHCTRL_RXTHLTH_Msk                                 (0x1FFUL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x03FE0000 */
#define USB_OTG_DTHCTRL_RXTHLTH                                     USB_OTG_DTHCTRL_RXTHLTH_Msk                                    /*!< Receive threshold length */
#define USB_OTG_DTHCTRL_RXTHLTH_0                                   (0x001UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x00020000 */
#define USB_OTG_DTHCTRL_RXTHLTH_1                                   (0x002UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x00040000 */
#define USB_OTG_DTHCTRL_RXTHLTH_2                                   (0x004UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x00080000 */
#define USB_OTG_DTHCTRL_RXTHLTH_3                                   (0x008UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x00100000 */
#define USB_OTG_DTHCTRL_RXTHLTH_4                                   (0x010UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x00200000 */
#define USB_OTG_DTHCTRL_RXTHLTH_5                                   (0x020UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x00400000 */
#define USB_OTG_DTHCTRL_RXTHLTH_6                                   (0x040UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x00800000 */
#define USB_OTG_DTHCTRL_RXTHLTH_7                                   (0x080UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x01000000 */
#define USB_OTG_DTHCTRL_RXTHLTH_8                                   (0x100UL << USB_OTG_DTHCTRL_RXTHLTH_Pos)                       /*!< 0x02000000 */
#define USB_OTG_DTHCTRL_APARKEN_Pos                                 (27U)
#define USB_OTG_DTHCTRL_APARKEN_Msk                                 (0x1UL << USB_OTG_DTHCTRL_APARKEN_Pos)                         /*!< 0x08000000 */
#define USB_OTG_DTHCTRL_APARKEN                                     USB_OTG_DTHCTRL_APARKEN_Msk                                    /*!< Arbiter parking enable */

/********************  Bit definition for USB_OTG_DIEIMASK register  ********************/
#define USB_OTG_DIEIMASK_INEM_Pos                                   (0U)
#define USB_OTG_DIEIMASK_INEM_Msk                                   (0xFFFFUL << USB_OTG_DIEIMASK_INEM_Pos)                        /*!< 0x0000FFFF */
#define USB_OTG_DIEIMASK_INEM                                       USB_OTG_DIEIMASK_INEM_Msk                                      /*!< IN EP Tx FIFO empty interrupt mask bits */

/********************  Bit definition for USB_OTG_DEPINT register  ********************/
#define USB_OTG_DEPINT_IN1INT_Pos                                   (1U)
#define USB_OTG_DEPINT_IN1INT_Msk                                   (0x1UL << USB_OTG_DEPINT_IN1INT_Pos)                           /*!< 0x00000002 */
#define USB_OTG_DEPINT_IN1INT                                       USB_OTG_DEPINT_IN1INT_Msk                                      /*!< IN endpoint 1interrupt bit   */
#define USB_OTG_DEPINT_OUT1INT_Pos                                  (17U)
#define USB_OTG_DEPINT_OUT1INT_Msk                                  (0x1UL << USB_OTG_DEPINT_OUT1INT_Pos)                          /*!< 0x00020000 */
#define USB_OTG_DEPINT_OUT1INT                                      USB_OTG_DEPINT_OUT1INT_Msk                                     /*!< OUT endpoint 1 interrupt bit */

/********************  Bit definition for USB_OTG_GGCCFG register  ********************/
#define USB_OTG_GGCCFG_PWEN_Pos                                     (16U)
#define USB_OTG_GGCCFG_PWEN_Msk                                     (0x1UL << USB_OTG_GGCCFG_PWEN_Pos)                             /*!< 0x00010000 */
#define USB_OTG_GGCCFG_PWEN                                         USB_OTG_GGCCFG_PWEN_Msk                                        /*!< Power down */
#define USB_OTG_GGCCFG_I2CBEN_Pos                                   (17U)
#define USB_OTG_GGCCFG_I2CBEN_Msk                                   (0x1UL << USB_OTG_GGCCFG_I2CBEN_Pos)                           /*!< 0x00020000 */
#define USB_OTG_GGCCFG_I2CBEN                                       USB_OTG_GGCCFG_I2CBEN_Msk                                      /*!< Enable I2C bus connection for the external I2C PHY interface*/
#define USB_OTG_GGCCFG_ADVBSEN_Pos                                  (18U)
#define USB_OTG_GGCCFG_ADVBSEN_Msk                                  (0x1UL << USB_OTG_GGCCFG_ADVBSEN_Pos)                          /*!< 0x00040000 */
#define USB_OTG_GGCCFG_ADVBSEN                                      USB_OTG_GGCCFG_ADVBSEN_Msk                                     /*!< Enable the VBUS sensing device */
#define USB_OTG_GGCCFG_BDVBSEN_Pos                                  (19U)
#define USB_OTG_GGCCFG_BDVBSEN_Msk                                  (0x1UL << USB_OTG_GGCCFG_BDVBSEN_Pos)                          /*!< 0x00080000 */
#define USB_OTG_GGCCFG_BDVBSEN                                      USB_OTG_GGCCFG_BDVBSEN_Msk                                     /*!< Enable the VBUS sensing device */
#define USB_OTG_GGCCFG_SOFPOUT_Pos                                  (20U)
#define USB_OTG_GGCCFG_SOFPOUT_Msk                                  (0x1UL << USB_OTG_GGCCFG_SOFPOUT_Pos)                          /*!< 0x00100000 */
#define USB_OTG_GGCCFG_SOFPOUT                                      USB_OTG_GGCCFG_SOFPOUT_Msk                                     /*!< SOF output enable */
#define USB_OTG_GGCCFG_VBSDIS_Pos                                   (21U)
#define USB_OTG_GGCCFG_VBSDIS_Msk                                   (0x1UL << USB_OTG_GGCCFG_VBSDIS_Pos)                           /*!< 0x00200000 */
#define USB_OTG_GGCCFG_VBSDIS                                       USB_OTG_GGCCFG_VBSDIS_Msk                                      /*!< VBUS sensing disable option*/

/********************  Bit definition forUSB_OTG_DEPIMASK register  ********************/
#define USB_OTG_DEPIMASK_IN1M_Pos                                   (1U)
#define USB_OTG_DEPIMASK_IN1M_Msk                                   (0x1UL << USB_OTG_DEPIMASK_IN1M_Pos)                           /*!< 0x00000002 */
#define USB_OTG_DEPIMASK_IN1M                                       USB_OTG_DEPIMASK_IN1M_Msk                                      /*!< IN Endpoint 1 interrupt mask bit  */
#define USB_OTG_DEPIMASK_OUT1M_Pos                                  (17U)
#define USB_OTG_DEPIMASK_OUT1M_Msk                                  (0x1UL << USB_OTG_DEPIMASK_OUT1M_Pos)                          /*!< 0x00020000 */
#define USB_OTG_DEPIMASK_OUT1M                                      USB_OTG_DEPIMASK_OUT1M_Msk                                     /*!< OUT Endpoint 1 interrupt mask bit */

/********************  Bit definition for USB_OTG_GCID register  ********************/
#define USB_OTG_GCID_PID_Pos                                        (0U)
#define USB_OTG_GCID_PID_Msk                                        (0xFFFFFFFFUL << USB_OTG_GCID_PID_Pos)                         /*!< 0xFFFFFFFF */
#define USB_OTG_GCID_PID                                            USB_OTG_GCID_PID_Msk                                           /*!< Product ID field */

/********************  Bit definition for USB_OTG_DIN1IMASK register  ********************/
#define USB_OTG_DIN1IMASK_TSFCMPM_Pos                               (0U)
#define USB_OTG_DIN1IMASK_TSFCMPM_Msk                               (0x1UL << USB_OTG_DIN1IMASK_TSFCMPM_Pos)                       /*!< 0x00000001 */
#define USB_OTG_DIN1IMASK_TSFCMPM                                   USB_OTG_DIN1IMASK_TSFCMPM_Msk                                  /*!< Transfer completed interrupt mask                 */
#define USB_OTG_DIN1IMASK_EPDISM_Pos                                (1U)
#define USB_OTG_DIN1IMASK_EPDISM_Msk                                (0x1UL << USB_OTG_DIN1IMASK_EPDISM_Pos)                        /*!< 0x00000002 */
#define USB_OTG_DIN1IMASK_EPDISM                                    USB_OTG_DIN1IMASK_EPDISM_Msk                                   /*!< Endpoint disabled interrupt mask                  */
#define USB_OTG_DIN1IMASK_TOM_Pos                                   (3U)
#define USB_OTG_DIN1IMASK_TOM_Msk                                   (0x1UL << USB_OTG_DIN1IMASK_TOM_Pos)                           /*!< 0x00000008 */
#define USB_OTG_DIN1IMASK_TOM                                       USB_OTG_DIN1IMASK_TOM_Msk                                      /*!< Timeout condition mask (nonisochronous endpoints) */
#define USB_OTG_DIN1IMASK_ITXEMPM_Pos                               (4U)
#define USB_OTG_DIN1IMASK_ITXEMPM_Msk                               (0x1UL << USB_OTG_DIN1IMASK_ITXEMPM_Pos)                       /*!< 0x00000010 */
#define USB_OTG_DIN1IMASK_ITXEMPM                                   USB_OTG_DIN1IMASK_ITXEMPM_Msk                                  /*!< IN token received when TxFIFO empty mask          */
#define USB_OTG_DIN1IMASK_IEPMMM_Pos                                (5U)
#define USB_OTG_DIN1IMASK_IEPMMM_Msk                                (0x1UL << USB_OTG_DIN1IMASK_IEPMMM_Pos)                        /*!< 0x00000020 */
#define USB_OTG_DIN1IMASK_IEPMMM                                    USB_OTG_DIN1IMASK_IEPMMM_Msk                                   /*!< IN token received with EP mismatch mask           */
#define USB_OTG_DIN1IMASK_IEPNAKEM_Pos                              (6U)
#define USB_OTG_DIN1IMASK_IEPNAKEM_Msk                              (0x1UL << USB_OTG_DIN1IMASK_IEPNAKEM_Pos)                      /*!< 0x00000040 */
#define USB_OTG_DIN1IMASK_IEPNAKEM                                  USB_OTG_DIN1IMASK_IEPNAKEM_Msk                                 /*!< IN endpoint NAK effective mask                    */
#define USB_OTG_DIN1IMASK_TXFUDRM_Pos                               (8U)
#define USB_OTG_DIN1IMASK_TXFUDRM_Msk                               (0x1UL << USB_OTG_DIN1IMASK_TXFUDRM_Pos)                       /*!< 0x00000100 */
#define USB_OTG_DIN1IMASK_TXFUDRM                                   USB_OTG_DIN1IMASK_TXFUDRM_Msk                                  /*!< FIFO underrun mask                                */
#define USB_OTG_DIN1IMASK_BNAM_Pos                                  (9U)
#define USB_OTG_DIN1IMASK_BNAM_Msk                                  (0x1UL << USB_OTG_DIN1IMASK_BNAM_Pos)                          /*!< 0x00000200 */
#define USB_OTG_DIN1IMASK_BNAM                                      USB_OTG_DIN1IMASK_BNAM_Msk                                     /*!< BNA interrupt mask                                */
#define USB_OTG_DIN1IMASK_NAKM_Pos                                  (13U)
#define USB_OTG_DIN1IMASK_NAKM_Msk                                  (0x1UL << USB_OTG_DIN1IMASK_NAKM_Pos)                          /*!< 0x00002000 */
#define USB_OTG_DIN1IMASK_NAKM                                      USB_OTG_DIN1IMASK_NAKM_Msk                                     /*!< NAK interrupt mask                                */

/********************  Bit definition for USB_OTG_HPORTCSTS register  ********************/
#define USB_OTG_HPORTCSTS_PCNNTFLG_Pos                              (0U)
#define USB_OTG_HPORTCSTS_PCNNTFLG_Msk                              (0x1UL << USB_OTG_HPORTCSTS_PCNNTFLG_Pos)                      /*!< 0x00000001 */
#define USB_OTG_HPORTCSTS_PCNNTFLG                                  USB_OTG_HPORTCSTS_PCNNTFLG_Msk                                 /*!< Port connect status        */
#define USB_OTG_HPORTCSTS_PCINTFLG_Pos                              (1U)
#define USB_OTG_HPORTCSTS_PCINTFLG_Msk                              (0x1UL << USB_OTG_HPORTCSTS_PCINTFLG_Pos)                      /*!< 0x00000002 */
#define USB_OTG_HPORTCSTS_PCINTFLG                                  USB_OTG_HPORTCSTS_PCINTFLG_Msk                                 /*!< Port connect detected      */
#define USB_OTG_HPORTCSTS_PEN_Pos                                   (2U)
#define USB_OTG_HPORTCSTS_PEN_Msk                                   (0x1UL << USB_OTG_HPORTCSTS_PEN_Pos)                           /*!< 0x00000004 */
#define USB_OTG_HPORTCSTS_PEN                                       USB_OTG_HPORTCSTS_PEN_Msk                                      /*!< Port enable                */
#define USB_OTG_HPORTCSTS_PENCHG_Pos                                (3U)
#define USB_OTG_HPORTCSTS_PENCHG_Msk                                (0x1UL << USB_OTG_HPORTCSTS_PENCHG_Pos)                        /*!< 0x00000008 */
#define USB_OTG_HPORTCSTS_PENCHG                                    USB_OTG_HPORTCSTS_PENCHG_Msk                                   /*!< Port enable/disable change */
#define USB_OTG_HPORTCSTS_POVC_Pos                                  (4U)
#define USB_OTG_HPORTCSTS_POVC_Msk                                  (0x1UL << USB_OTG_HPORTCSTS_POVC_Pos)                          /*!< 0x00000010 */
#define USB_OTG_HPORTCSTS_POVC                                      USB_OTG_HPORTCSTS_POVC_Msk                                     /*!< Port overcurrent active    */
#define USB_OTG_HPORTCSTS_POVCCHG_Pos                               (5U)
#define USB_OTG_HPORTCSTS_POVCCHG_Msk                               (0x1UL << USB_OTG_HPORTCSTS_POVCCHG_Pos)                       /*!< 0x00000020 */
#define USB_OTG_HPORTCSTS_POVCCHG                                   USB_OTG_HPORTCSTS_POVCCHG_Msk                                  /*!< Port overcurrent change    */
#define USB_OTG_HPORTCSTS_PRS_Pos                                   (6U)
#define USB_OTG_HPORTCSTS_PRS_Msk                                   (0x1UL << USB_OTG_HPORTCSTS_PRS_Pos)                           /*!< 0x00000040 */
#define USB_OTG_HPORTCSTS_PRS                                       USB_OTG_HPORTCSTS_PRS_Msk                                      /*!< Port resume                */
#define USB_OTG_HPORTCSTS_PSUS_Pos                                  (7U)
#define USB_OTG_HPORTCSTS_PSUS_Msk                                  (0x1UL << USB_OTG_HPORTCSTS_PSUS_Pos)                          /*!< 0x00000080 */
#define USB_OTG_HPORTCSTS_PSUS                                      USB_OTG_HPORTCSTS_PSUS_Msk                                     /*!< Port suspend               */
#define USB_OTG_HPORTCSTS_PRST_Pos                                  (8U)
#define USB_OTG_HPORTCSTS_PRST_Msk                                  (0x1UL << USB_OTG_HPORTCSTS_PRST_Pos)                          /*!< 0x00000100 */
#define USB_OTG_HPORTCSTS_PRST                                      USB_OTG_HPORTCSTS_PRST_Msk                                     /*!< Port reset                 */

#define USB_OTG_HPORTCSTS_PDLSTS_Pos                                (10U)
#define USB_OTG_HPORTCSTS_PDLSTS_Msk                                (0x3UL << USB_OTG_HPORTCSTS_PDLSTS_Pos)                        /*!< 0x00000C00 */
#define USB_OTG_HPORTCSTS_PDLSTS                                    USB_OTG_HPORTCSTS_PDLSTS_Msk                                   /*!< Port line status           */
#define USB_OTG_HPORTCSTS_PDLSTS_0                                  (0x1UL << USB_OTG_HPORTCSTS_PDLSTS_Pos)                        /*!< 0x00000400 */
#define USB_OTG_HPORTCSTS_PDLSTS_1                                  (0x2UL << USB_OTG_HPORTCSTS_PDLSTS_Pos)                        /*!< 0x00000800 */
#define USB_OTG_HPORTCSTS_PP_Pos                                    (12U)
#define USB_OTG_HPORTCSTS_PP_Msk                                    (0x1UL << USB_OTG_HPORTCSTS_PP_Pos)                            /*!< 0x00001000 */
#define USB_OTG_HPORTCSTS_PP                                        USB_OTG_HPORTCSTS_PP_Msk                                       /*!< Port power                 */

#define USB_OTG_HPORTCSTS_PTSEL_Pos                                 (13U)
#define USB_OTG_HPORTCSTS_PTSEL_Msk                                 (0xFUL << USB_OTG_HPORTCSTS_PTSEL_Pos)                         /*!< 0x0001E000 */
#define USB_OTG_HPORTCSTS_PTSEL                                     USB_OTG_HPORTCSTS_PTSEL_Msk                                    /*!< Port test control          */
#define USB_OTG_HPORTCSTS_PTSEL_0                                   (0x1UL << USB_OTG_HPORTCSTS_PTSEL_Pos)                         /*!< 0x00002000 */
#define USB_OTG_HPORTCSTS_PTSEL_1                                   (0x2UL << USB_OTG_HPORTCSTS_PTSEL_Pos)                         /*!< 0x00004000 */
#define USB_OTG_HPORTCSTS_PTSEL_2                                   (0x4UL << USB_OTG_HPORTCSTS_PTSEL_Pos)                         /*!< 0x00008000 */
#define USB_OTG_HPORTCSTS_PTSEL_3                                   (0x8UL << USB_OTG_HPORTCSTS_PTSEL_Pos)                         /*!< 0x00010000 */

#define USB_OTG_HPORTCSTS_PSPDSEL_Pos                               (17U)
#define USB_OTG_HPORTCSTS_PSPDSEL_Msk                               (0x3UL << USB_OTG_HPORTCSTS_PSPDSEL_Pos)                       /*!< 0x00060000 */
#define USB_OTG_HPORTCSTS_PSPDSEL                                   USB_OTG_HPORTCSTS_PSPDSEL_Msk                                  /*!< Port speed                 */
#define USB_OTG_HPORTCSTS_PSPDSEL_0                                 (0x1UL << USB_OTG_HPORTCSTS_PSPDSEL_Pos)                       /*!< 0x00020000 */
#define USB_OTG_HPORTCSTS_PSPDSEL_1                                 (0x2UL << USB_OTG_HPORTCSTS_PSPDSEL_Pos)                       /*!< 0x00040000 */

/********************  Bit definition for USB_OTG_DOUT1MASK register  ********************/
#define USB_OTG_DOUT1MASK_TSFCMPM_Pos                               (0U)
#define USB_OTG_DOUT1MASK_TSFCMPM_Msk                               (0x1UL << USB_OTG_DOUT1MASK_TSFCMPM_Pos)                       /*!< 0x00000001 */
#define USB_OTG_DOUT1MASK_TSFCMPM                                   USB_OTG_DOUT1MASK_TSFCMPM_Msk                                  /*!< Transfer completed interrupt mask         */
#define USB_OTG_DOUT1MASK_EPDISM_Pos                                (1U)
#define USB_OTG_DOUT1MASK_EPDISM_Msk                                (0x1UL << USB_OTG_DOUT1MASK_EPDISM_Pos)                        /*!< 0x00000002 */
#define USB_OTG_DOUT1MASK_EPDISM                                    USB_OTG_DOUT1MASK_EPDISM_Msk                                   /*!< Endpoint disabled interrupt mask          */
#define USB_OTG_DOUT1MASK_TOM_Pos                                   (3U)
#define USB_OTG_DOUT1MASK_TOM_Msk                                   (0x1UL << USB_OTG_DOUT1MASK_TOM_Pos)                           /*!< 0x00000008 */
#define USB_OTG_DOUT1MASK_TOM                                       USB_OTG_DOUT1MASK_TOM_Msk                                      /*!< Timeout condition mask                    */
#define USB_OTG_DOUT1MASK_ITXEMPM_Pos                               (4U)
#define USB_OTG_DOUT1MASK_ITXEMPM_Msk                               (0x1UL << USB_OTG_DOUT1MASK_ITXEMPM_Pos)                       /*!< 0x00000010 */
#define USB_OTG_DOUT1MASK_ITXEMPM                                   USB_OTG_DOUT1MASK_ITXEMPM_Msk                                  /*!< IN token received when TxFIFO empty mask  */
#define USB_OTG_DOUT1MASK_IEPMMM_Pos                                (5U)
#define USB_OTG_DOUT1MASK_IEPMMM_Msk                                (0x1UL << USB_OTG_DOUT1MASK_IEPMMM_Pos)                        /*!< 0x00000020 */
#define USB_OTG_DOUT1MASK_IEPMMM                                    USB_OTG_DOUT1MASK_IEPMMM_Msk                                   /*!< IN token received with EP mismatch mask   */
#define USB_OTG_DOUT1MASK_IEPNAKEM_Pos                              (6U)
#define USB_OTG_DOUT1MASK_IEPNAKEM_Msk                              (0x1UL << USB_OTG_DOUT1MASK_IEPNAKEM_Pos)                      /*!< 0x00000040 */
#define USB_OTG_DOUT1MASK_IEPNAKEM                                  USB_OTG_DOUT1MASK_IEPNAKEM_Msk                                 /*!< IN endpoint NAK effective mask            */
#define USB_OTG_DOUT1MASK_FUDRM_Pos                                 (8U)
#define USB_OTG_DOUT1MASK_FUDRM_Msk                                 (0x1UL << USB_OTG_DOUT1MASK_FUDRM_Pos)                         /*!< 0x00000100 */
#define USB_OTG_DOUT1MASK_FUDRM                                     USB_OTG_DOUT1MASK_FUDRM_Msk                                    /*!< OUT packet error mask                     */
#define USB_OTG_DOUT1MASK_BNAM_Pos                                  (9U)
#define USB_OTG_DOUT1MASK_BNAM_Msk                                  (0x1UL << USB_OTG_DOUT1MASK_BNAM_Pos)                          /*!< 0x00000200 */
#define USB_OTG_DOUT1MASK_BNAM                                      USB_OTG_DOUT1MASK_BNAM_Msk                                     /*!< BNA interrupt mask                        */
#define USB_OTG_DOUT1MASK_BERRM_Pos                                 (12U)
#define USB_OTG_DOUT1MASK_BERRM_Msk                                 (0x1UL << USB_OTG_DOUT1MASK_BERRM_Pos)                         /*!< 0x00001000 */
#define USB_OTG_DOUT1MASK_BERRM                                     USB_OTG_DOUT1MASK_BERRM_Msk                                    /*!< Bubble error interrupt mask               */
#define USB_OTG_DOUT1MASK_NAKM_Pos                                  (13U)
#define USB_OTG_DOUT1MASK_NAKM_Msk                                  (0x1UL << USB_OTG_DOUT1MASK_NAKM_Pos)                          /*!< 0x00002000 */
#define USB_OTG_DOUT1MASK_NAKM                                      USB_OTG_DOUT1MASK_NAKM_Msk                                     /*!< NAK interrupt mask                        */
#define USB_OTG_DOUT1MASK_NYETM_Pos                                 (14U)
#define USB_OTG_DOUT1MASK_NYETM_Msk                                 (0x1UL << USB_OTG_DOUT1MASK_NYETM_Pos)                         /*!< 0x00004000 */
#define USB_OTG_DOUT1MASK_NYETM                                     USB_OTG_DOUT1MASK_NYETM_Msk                                    /*!< NYET interrupt mask                       */

/********************  Bit definition for USB_OTG_GHPTXFSIZE register  ********************/
#define USB_OTG_GHPTXFSIZE_HPDTXFSA_Pos                             (0U)
#define USB_OTG_GHPTXFSIZE_HPDTXFSA_Msk                             (0xFFFFUL << USB_OTG_GHPTXFSIZE_HPDTXFSA_Pos)                  /*!< 0x0000FFFF */
#define USB_OTG_GHPTXFSIZE_HPDTXFSA                                 USB_OTG_GHPTXFSIZE_HPDTXFSA_Msk                                /*!< Host periodic TxFIFO start address            */
#define USB_OTG_GHPTXFSIZE_HPDTXFDEP_Pos                            (16U)
#define USB_OTG_GHPTXFSIZE_HPDTXFDEP_Msk                            (0xFFFFUL << USB_OTG_GHPTXFSIZE_HPDTXFDEP_Pos)                 /*!< 0xFFFF0000 */
#define USB_OTG_GHPTXFSIZE_HPDTXFDEP                                USB_OTG_GHPTXFSIZE_HPDTXFDEP_Msk                               /*!< Host periodic TxFIFO depth                    */

/********************  Bit definition for USB_OTG_DIEPCTRL register  ********************/
#define USB_OTG_DIEPCTRL_MAXPS_Pos                                  (0U)
#define USB_OTG_DIEPCTRL_MAXPS_Msk                                  (0x7FFUL << USB_OTG_DIEPCTRL_MAXPS_Pos)                        /*!< 0x000007FF */
#define USB_OTG_DIEPCTRL_MAXPS                                      USB_OTG_DIEPCTRL_MAXPS_Msk                                     /*!< Maximum packet size              */
#define USB_OTG_DIEPCTRL_USBAEP_Pos                                 (15U)
#define USB_OTG_DIEPCTRL_USBAEP_Msk                                 (0x1UL << USB_OTG_DIEPCTRL_USBAEP_Pos)                         /*!< 0x00008000 */
#define USB_OTG_DIEPCTRL_USBAEP                                     USB_OTG_DIEPCTRL_USBAEP_Msk                                    /*!< USB active endpoint              */
#define USB_OTG_DIEPCTRL_EOF_PID_Pos                                (16U)
#define USB_OTG_DIEPCTRL_EOF_PID_Msk                                (0x1UL << USB_OTG_DIEPCTRL_EOF_PID_Pos)                        /*!< 0x00010000 */
#define USB_OTG_DIEPCTRL_EOF_PID                                    USB_OTG_DIEPCTRL_EOF_PID_Msk                                   /*!< Even/odd frame                   */
#define USB_OTG_DIEPCTRL_NAKSTS_Pos                                 (17U)
#define USB_OTG_DIEPCTRL_NAKSTS_Msk                                 (0x1UL << USB_OTG_DIEPCTRL_NAKSTS_Pos)                         /*!< 0x00020000 */
#define USB_OTG_DIEPCTRL_NAKSTS                                     USB_OTG_DIEPCTRL_NAKSTS_Msk                                    /*!< NAK status                       */

#define USB_OTG_DIEPCTRL_EPTYPE_Pos                                 (18U)
#define USB_OTG_DIEPCTRL_EPTYPE_Msk                                 (0x3UL << USB_OTG_DIEPCTRL_EPTYPE_Pos)                         /*!< 0x000C0000 */
#define USB_OTG_DIEPCTRL_EPTYPE                                     USB_OTG_DIEPCTRL_EPTYPE_Msk                                    /*!< Endpoint type                    */
#define USB_OTG_DIEPCTRL_EPTYPE_0                                   (0x1UL << USB_OTG_DIEPCTRL_EPTYPE_Pos)                         /*!< 0x00040000 */
#define USB_OTG_DIEPCTRL_EPTYPE_1                                   (0x2UL << USB_OTG_DIEPCTRL_EPTYPE_Pos)                         /*!< 0x00080000 */
#define USB_OTG_DIEPCTRL_STALLH_Pos                                 (21U)
#define USB_OTG_DIEPCTRL_STALLH_Msk                                 (0x1UL << USB_OTG_DIEPCTRL_STALLH_Pos)                         /*!< 0x00200000 */
#define USB_OTG_DIEPCTRL_STALLH                                     USB_OTG_DIEPCTRL_STALLH_Msk                                    /*!< STALL handshake                  */

#define USB_OTG_DIEPCTRL_TXFNUM_Pos                                 (22U)
#define USB_OTG_DIEPCTRL_TXFNUM_Msk                                 (0xFUL << USB_OTG_DIEPCTRL_TXFNUM_Pos)                         /*!< 0x03C00000 */
#define USB_OTG_DIEPCTRL_TXFNUM                                     USB_OTG_DIEPCTRL_TXFNUM_Msk                                    /*!< TxFIFO number                    */
#define USB_OTG_DIEPCTRL_TXFNUM_0                                   (0x1UL << USB_OTG_DIEPCTRL_TXFNUM_Pos)                         /*!< 0x00400000 */
#define USB_OTG_DIEPCTRL_TXFNUM_1                                   (0x2UL << USB_OTG_DIEPCTRL_TXFNUM_Pos)                         /*!< 0x00800000 */
#define USB_OTG_DIEPCTRL_TXFNUM_2                                   (0x4UL << USB_OTG_DIEPCTRL_TXFNUM_Pos)                         /*!< 0x01000000 */
#define USB_OTG_DIEPCTRL_TXFNUM_3                                   (0x8UL << USB_OTG_DIEPCTRL_TXFNUM_Pos)                         /*!< 0x02000000 */
#define USB_OTG_DIEPCTRL_NAKCLR_Pos                                 (26U)
#define USB_OTG_DIEPCTRL_NAKCLR_Msk                                 (0x1UL << USB_OTG_DIEPCTRL_NAKCLR_Pos)                         /*!< 0x04000000 */
#define USB_OTG_DIEPCTRL_NAKCLR                                     USB_OTG_DIEPCTRL_NAKCLR_Msk                                    /*!< Clear NAK                        */
#define USB_OTG_DIEPCTRL_NAKSET_Pos                                 (27U)
#define USB_OTG_DIEPCTRL_NAKSET_Msk                                 (0x1UL << USB_OTG_DIEPCTRL_NAKSET_Pos)                         /*!< 0x08000000 */
#define USB_OTG_DIEPCTRL_NAKSET                                     USB_OTG_DIEPCTRL_NAKSET_Msk                                    /*!< Set NAK */
#define USB_OTG_DIEPCTRL_DPIDSET_Pos                                (28U)
#define USB_OTG_DIEPCTRL_DPIDSET_Msk                                (0x1UL << USB_OTG_DIEPCTRL_DPIDSET_Pos)                        /*!< 0x10000000 */
#define USB_OTG_DIEPCTRL_DPIDSET                                    USB_OTG_DIEPCTRL_DPIDSET_Msk                                   /*!< Set DATA0 PID                    */
#define USB_OTG_DIEPCTRL_OFSET_Pos                                  (29U)
#define USB_OTG_DIEPCTRL_OFSET_Msk                                  (0x1UL << USB_OTG_DIEPCTRL_OFSET_Pos)                          /*!< 0x20000000 */
#define USB_OTG_DIEPCTRL_OFSET                                      USB_OTG_DIEPCTRL_OFSET_Msk                                     /*!< Set odd frame                    */
#define USB_OTG_DIEPCTRL_EPDIS_Pos                                  (30U)
#define USB_OTG_DIEPCTRL_EPDIS_Msk                                  (0x1UL << USB_OTG_DIEPCTRL_EPDIS_Pos)                          /*!< 0x40000000 */
#define USB_OTG_DIEPCTRL_EPDIS                                      USB_OTG_DIEPCTRL_EPDIS_Msk                                     /*!< Endpoint disable                 */
#define USB_OTG_DIEPCTRL_EPEN_Pos                                   (31U)
#define USB_OTG_DIEPCTRL_EPEN_Msk                                   (0x1UL << USB_OTG_DIEPCTRL_EPEN_Pos)                           /*!< 0x80000000 */
#define USB_OTG_DIEPCTRL_EPEN                                       USB_OTG_DIEPCTRL_EPEN_Msk                                      /*!< Endpoint enable                  */

/********************  Bit definition for USB_OTG_HCH register  ********************/
#define USB_OTG_HCH_MAXPSIZE_Pos                                    (0U)
#define USB_OTG_HCH_MAXPSIZE_Msk                                    (0x7FFUL << USB_OTG_HCH_MAXPSIZE_Pos)                          /*!< 0x000007FF */
#define USB_OTG_HCH_MAXPSIZE                                        USB_OTG_HCH_MAXPSIZE_Msk                                       /*!< Maximum packet size */

#define USB_OTG_HCH_EDPNUM_Pos                                      (11U)
#define USB_OTG_HCH_EDPNUM_Msk                                      (0xFUL << USB_OTG_HCH_EDPNUM_Pos)                              /*!< 0x00007800 */
#define USB_OTG_HCH_EDPNUM                                          USB_OTG_HCH_EDPNUM_Msk                                         /*!< Endpoint number */
#define USB_OTG_HCH_EDPNUM_0                                        (0x1UL << USB_OTG_HCH_EDPNUM_Pos)                              /*!< 0x00000800 */
#define USB_OTG_HCH_EDPNUM_1                                        (0x2UL << USB_OTG_HCH_EDPNUM_Pos)                              /*!< 0x00001000 */
#define USB_OTG_HCH_EDPNUM_2                                        (0x4UL << USB_OTG_HCH_EDPNUM_Pos)                              /*!< 0x00002000 */
#define USB_OTG_HCH_EDPNUM_3                                        (0x8UL << USB_OTG_HCH_EDPNUM_Pos)                              /*!< 0x00004000 */
#define USB_OTG_HCH_EDPDRT_Pos                                      (15U)
#define USB_OTG_HCH_EDPDRT_Msk                                      (0x1UL << USB_OTG_HCH_EDPDRT_Pos)                              /*!< 0x00008000 */
#define USB_OTG_HCH_EDPDRT                                          USB_OTG_HCH_EDPDRT_Msk                                         /*!< Endpoint direction */
#define USB_OTG_HCH_LSDV_Pos                                        (17U)
#define USB_OTG_HCH_LSDV_Msk                                        (0x1UL << USB_OTG_HCH_LSDV_Pos)                                /*!< 0x00020000 */
#define USB_OTG_HCH_LSDV                                            USB_OTG_HCH_LSDV_Msk                                           /*!< Low-speed device */

#define USB_OTG_HCH_EDPTYP_Pos                                      (18U)
#define USB_OTG_HCH_EDPTYP_Msk                                      (0x3UL << USB_OTG_HCH_EDPTYP_Pos)                              /*!< 0x000C0000 */
#define USB_OTG_HCH_EDPTYP                                          USB_OTG_HCH_EDPTYP_Msk                                         /*!< Endpoint type */
#define USB_OTG_HCH_EDPTYP_0                                        (0x1UL << USB_OTG_HCH_EDPTYP_Pos)                              /*!< 0x00040000 */
#define USB_OTG_HCH_EDPTYP_1                                        (0x2UL << USB_OTG_HCH_EDPTYP_Pos)                              /*!< 0x00080000 */

#define USB_OTG_HCH_CNTSEL_Pos                                      (20U)
#define USB_OTG_HCH_CNTSEL_Msk                                      (0x3UL << USB_OTG_HCH_CNTSEL_Pos)                              /*!< 0x00300000 */
#define USB_OTG_HCH_CNTSEL                                          USB_OTG_HCH_CNTSEL_Msk                                         /*!< Multi Count (MC) / Error Count (EC) */
#define USB_OTG_HCH_CNTSEL_0                                        (0x1UL << USB_OTG_HCH_CNTSEL_Pos)                              /*!< 0x00100000 */
#define USB_OTG_HCH_CNTSEL_1                                        (0x2UL << USB_OTG_HCH_CNTSEL_Pos)                              /*!< 0x00200000 */

#define USB_OTG_HCH_DVADDR_Pos                                      (22U)
#define USB_OTG_HCH_DVADDR_Msk                                      (0x7FUL << USB_OTG_HCH_DVADDR_Pos)                             /*!< 0x1FC00000 */
#define USB_OTG_HCH_DVADDR                                          USB_OTG_HCH_DVADDR_Msk                                         /*!< Device address */
#define USB_OTG_HCH_DVADDR_0                                        (0x01UL << USB_OTG_HCH_DVADDR_Pos)                             /*!< 0x00400000 */
#define USB_OTG_HCH_DVADDR_1                                        (0x02UL << USB_OTG_HCH_DVADDR_Pos)                             /*!< 0x00800000 */
#define USB_OTG_HCH_DVADDR_2                                        (0x04UL << USB_OTG_HCH_DVADDR_Pos)                             /*!< 0x01000000 */
#define USB_OTG_HCH_DVADDR_3                                        (0x08UL << USB_OTG_HCH_DVADDR_Pos)                             /*!< 0x02000000 */
#define USB_OTG_HCH_DVADDR_4                                        (0x10UL << USB_OTG_HCH_DVADDR_Pos)                             /*!< 0x04000000 */
#define USB_OTG_HCH_DVADDR_5                                        (0x20UL << USB_OTG_HCH_DVADDR_Pos)                             /*!< 0x08000000 */
#define USB_OTG_HCH_DVADDR_6                                        (0x40UL << USB_OTG_HCH_DVADDR_Pos)                             /*!< 0x10000000 */
#define USB_OTG_HCH_ODDF_Pos                                        (29U)
#define USB_OTG_HCH_ODDF_Msk                                        (0x1UL << USB_OTG_HCH_ODDF_Pos)                                /*!< 0x20000000 */
#define USB_OTG_HCH_ODDF                                            USB_OTG_HCH_ODDF_Msk                                           /*!< Odd frame */
#define USB_OTG_HCH_CHINT_Pos                                       (30U)
#define USB_OTG_HCH_CHINT_Msk                                       (0x1UL << USB_OTG_HCH_CHINT_Pos)                               /*!< 0x40000000 */
#define USB_OTG_HCH_CHINT                                           USB_OTG_HCH_CHINT_Msk                                          /*!< Channel disable */
#define USB_OTG_HCH_CHEN_Pos                                        (31U)
#define USB_OTG_HCH_CHEN_Msk                                        (0x1UL << USB_OTG_HCH_CHEN_Pos)                                /*!< 0x80000000 */
#define USB_OTG_HCH_CHEN                                            USB_OTG_HCH_CHEN_Msk                                           /*!< Channel enable */

/********************  Bit definition for USB_OTG_HCHSCTRL register  ********************/

#define USB_OTG_HCHSCTRL_PADDR_Pos                                  (0U)
#define USB_OTG_HCHSCTRL_PADDR_Msk                                  (0x7FUL << USB_OTG_HCHSCTRL_PADDR_Pos)                         /*!< 0x0000007F */
#define USB_OTG_HCHSCTRL_PADDR                                      USB_OTG_HCHSCTRL_PADDR_Msk                                     /*!< Port address */
#define USB_OTG_HCHSCTRL_PADDR_0                                    (0x01UL << USB_OTG_HCHSCTRL_PADDR_Pos)                         /*!< 0x00000001 */
#define USB_OTG_HCHSCTRL_PADDR_1                                    (0x02UL << USB_OTG_HCHSCTRL_PADDR_Pos)                         /*!< 0x00000002 */
#define USB_OTG_HCHSCTRL_PADDR_2                                    (0x04UL << USB_OTG_HCHSCTRL_PADDR_Pos)                         /*!< 0x00000004 */
#define USB_OTG_HCHSCTRL_PADDR_3                                    (0x08UL << USB_OTG_HCHSCTRL_PADDR_Pos)                         /*!< 0x00000008 */
#define USB_OTG_HCHSCTRL_PADDR_4                                    (0x10UL << USB_OTG_HCHSCTRL_PADDR_Pos)                         /*!< 0x00000010 */
#define USB_OTG_HCHSCTRL_PADDR_5                                    (0x20UL << USB_OTG_HCHSCTRL_PADDR_Pos)                         /*!< 0x00000020 */
#define USB_OTG_HCHSCTRL_PADDR_6                                    (0x40UL << USB_OTG_HCHSCTRL_PADDR_Pos)                         /*!< 0x00000040 */

#define USB_OTG_HCHSCTRL_HADDR_Pos                                  (7U)
#define USB_OTG_HCHSCTRL_HADDR_Msk                                  (0x7FUL << USB_OTG_HCHSCTRL_HADDR_Pos)                         /*!< 0x00003F80 */
#define USB_OTG_HCHSCTRL_HADDR                                      USB_OTG_HCHSCTRL_HADDR_Msk                                     /*!< Hub address */
#define USB_OTG_HCHSCTRL_HADDR_0                                    (0x01UL << USB_OTG_HCHSCTRL_HADDR_Pos)                         /*!< 0x00000080 */
#define USB_OTG_HCHSCTRL_HADDR_1                                    (0x02UL << USB_OTG_HCHSCTRL_HADDR_Pos)                         /*!< 0x00000100 */
#define USB_OTG_HCHSCTRL_HADDR_2                                    (0x04UL << USB_OTG_HCHSCTRL_HADDR_Pos)                         /*!< 0x00000200 */
#define USB_OTG_HCHSCTRL_HADDR_3                                    (0x08UL << USB_OTG_HCHSCTRL_HADDR_Pos)                         /*!< 0x00000400 */
#define USB_OTG_HCHSCTRL_HADDR_4                                    (0x10UL << USB_OTG_HCHSCTRL_HADDR_Pos)                         /*!< 0x00000800 */
#define USB_OTG_HCHSCTRL_HADDR_5                                    (0x20UL << USB_OTG_HCHSCTRL_HADDR_Pos)                         /*!< 0x00001000 */
#define USB_OTG_HCHSCTRL_HADDR_6                                    (0x40UL << USB_OTG_HCHSCTRL_HADDR_Pos)                         /*!< 0x00002000 */

#define USB_OTG_HCHSCTRL_TPOST_Pos                                  (14U)
#define USB_OTG_HCHSCTRL_TPOST_Msk                                  (0x3UL << USB_OTG_HCHSCTRL_TPOST_Pos)                          /*!< 0x0000C000 */
#define USB_OTG_HCHSCTRL_TPOST                                      USB_OTG_HCHSCTRL_TPOST_Msk                                     /*!< XACTPOS */
#define USB_OTG_HCHSCTRL_TPOST_0                                    (0x1UL << USB_OTG_HCHSCTRL_TPOST_Pos)                          /*!< 0x00004000 */
#define USB_OTG_HCHSCTRL_TPOST_1                                    (0x2UL << USB_OTG_HCHSCTRL_TPOST_Pos)                          /*!< 0x00008000 */
#define USB_OTG_HCHSCTRL_DO_CMP_SPL_Pos                             (16U)
#define USB_OTG_HCHSCTRL_DO_CMP_SPL_Msk                             (0x1UL << USB_OTG_HCHSCTRL_DO_CMP_SPL_Pos)                     /*!< 0x00010000 */
#define USB_OTG_HCHSCTRL_DO_CMP_SPL                                 USB_OTG_HCHSCTRL_DO_CMP_SPL_Msk                                /*!< Do complete split */
#define USB_OTG_HCHSCTRL_SPLEN_Pos                                  (31U)
#define USB_OTG_HCHSCTRL_SPLEN_Msk                                  (0x1UL << USB_OTG_HCHSCTRL_SPLEN_Pos)                          /*!< 0x80000000 */
#define USB_OTG_HCHSCTRL_SPLEN                                      USB_OTG_HCHSCTRL_SPLEN_Msk                                     /*!< Split enable */

/********************  Bit definition for USB_OTG_HCHINT register  ********************/
#define USB_OTG_HCHINT_TSFCMPN_Pos                                  (0U)
#define USB_OTG_HCHINT_TSFCMPN_Msk                                  (0x1UL << USB_OTG_HCHINT_TSFCMPN_Pos)                          /*!< 0x00000001 */
#define USB_OTG_HCHINT_TSFCMPN                                      USB_OTG_HCHINT_TSFCMPN_Msk                                     /*!< Transfer completed */
#define USB_OTG_HCHINT_TSFCMPAN_Pos                                 (1U)
#define USB_OTG_HCHINT_TSFCMPAN_Msk                                 (0x1UL << USB_OTG_HCHINT_TSFCMPAN_Pos)                         /*!< 0x00000002 */
#define USB_OTG_HCHINT_TSFCMPAN                                     USB_OTG_HCHINT_TSFCMPAN_Msk                                    /*!< Channel halted */
#define USB_OTG_HCHINT_AHBERR_Pos                                   (2U)
#define USB_OTG_HCHINT_AHBERR_Msk                                   (0x1UL << USB_OTG_HCHINT_AHBERR_Pos)                           /*!< 0x00000004 */
#define USB_OTG_HCHINT_AHBERR                                       USB_OTG_HCHINT_AHBERR_Msk                                      /*!< AHB error */
#define USB_OTG_HCHINT_RXSTALL_Pos                                  (3U)
#define USB_OTG_HCHINT_RXSTALL_Msk                                  (0x1UL << USB_OTG_HCHINT_RXSTALL_Pos)                          /*!< 0x00000008 */
#define USB_OTG_HCHINT_RXSTALL                                      USB_OTG_HCHINT_RXSTALL_Msk                                     /*!< STALL response received interrupt */
#define USB_OTG_HCHINT_RXNAK_Pos                                    (4U)
#define USB_OTG_HCHINT_RXNAK_Msk                                    (0x1UL << USB_OTG_HCHINT_RXNAK_Pos)                            /*!< 0x00000010 */
#define USB_OTG_HCHINT_RXNAK                                        USB_OTG_HCHINT_RXNAK_Msk                                       /*!< NAK response received interrupt */
#define USB_OTG_HCHINT_RXTXACK_Pos                                  (5U)
#define USB_OTG_HCHINT_RXTXACK_Msk                                  (0x1UL << USB_OTG_HCHINT_RXTXACK_Pos)                          /*!< 0x00000020 */
#define USB_OTG_HCHINT_RXTXACK                                      USB_OTG_HCHINT_RXTXACK_Msk                                     /*!< ACK response received/transmitted interrupt */
#define USB_OTG_HCHINT_RXNYET_Pos                                   (6U)
#define USB_OTG_HCHINT_RXNYET_Msk                                   (0x1UL << USB_OTG_HCHINT_RXNYET_Pos)                           /*!< 0x00000040 */
#define USB_OTG_HCHINT_RXNYET                                       USB_OTG_HCHINT_RXNYET_Msk                                      /*!< Response received interrupt */
#define USB_OTG_HCHINT_TERR_Pos                                     (7U)
#define USB_OTG_HCHINT_TERR_Msk                                     (0x1UL << USB_OTG_HCHINT_TERR_Pos)                             /*!< 0x00000080 */
#define USB_OTG_HCHINT_TERR                                         USB_OTG_HCHINT_TERR_Msk                                        /*!< Transaction error */
#define USB_OTG_HCHINT_BABBLE_Pos                                   (8U)
#define USB_OTG_HCHINT_BABBLE_Msk                                   (0x1UL << USB_OTG_HCHINT_BABBLE_Pos)                           /*!< 0x00000100 */
#define USB_OTG_HCHINT_BABBLE                                       USB_OTG_HCHINT_BABBLE_Msk                                      /*!< Babble error */
#define USB_OTG_HCHINT_FOVR_Pos                                     (9U)
#define USB_OTG_HCHINT_FOVR_Msk                                     (0x1UL << USB_OTG_HCHINT_FOVR_Pos)                             /*!< 0x00000200 */
#define USB_OTG_HCHINT_FOVR                                         USB_OTG_HCHINT_FOVR_Msk                                        /*!< Frame overrun */
#define USB_OTG_HCHINT_DTOG_Pos                                     (10U)
#define USB_OTG_HCHINT_DTOG_Msk                                     (0x1UL << USB_OTG_HCHINT_DTOG_Pos)                             /*!< 0x00000400 */
#define USB_OTG_HCHINT_DTOG                                         USB_OTG_HCHINT_DTOG_Msk                                        /*!< Data toggle error */

/********************  Bit definition for USB_OTG_DIEPINT register  ********************/
#define USB_OTG_DIEPINT_TSFCMP_Pos                                  (0U)
#define USB_OTG_DIEPINT_TSFCMP_Msk                                  (0x1UL << USB_OTG_DIEPINT_TSFCMP_Pos)                          /*!< 0x00000001 */
#define USB_OTG_DIEPINT_TSFCMP                                      USB_OTG_DIEPINT_TSFCMP_Msk                                     /*!< Transfer completed interrupt */
#define USB_OTG_DIEPINT_EPDIS_Pos                                   (1U)
#define USB_OTG_DIEPINT_EPDIS_Msk                                   (0x1UL << USB_OTG_DIEPINT_EPDIS_Pos)                           /*!< 0x00000002 */
#define USB_OTG_DIEPINT_EPDIS                                       USB_OTG_DIEPINT_EPDIS_Msk                                      /*!< Endpoint disabled interrupt */
#define USB_OTG_DIEPINT_AHBERR_Pos                                  (2U)
#define USB_OTG_DIEPINT_AHBERR_Msk                                  (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos)                          /*!< 0x00000004 */
#define USB_OTG_DIEPINT_AHBERR                                      USB_OTG_DIEPINT_AHBERR_Msk                                     /*!< AHB Error (AHBErr) during an IN transaction */
#define USB_OTG_DIEPINT_TO_Pos                                      (3U)
#define USB_OTG_DIEPINT_TO_Msk                                      (0x1UL << USB_OTG_DIEPINT_TO_Pos)                              /*!< 0x00000008 */
#define USB_OTG_DIEPINT_TO                                          USB_OTG_DIEPINT_TO_Msk                                         /*!< Timeout condition */
#define USB_OTG_DIEPINT_ITXEMP_Pos                                  (4U)
#define USB_OTG_DIEPINT_ITXEMP_Msk                                  (0x1UL << USB_OTG_DIEPINT_ITXEMP_Pos)                          /*!< 0x00000010 */
#define USB_OTG_DIEPINT_ITXEMP                                      USB_OTG_DIEPINT_ITXEMP_Msk                                     /*!< IN token received when TxFIFO is empty */
#define USB_OTG_DIEPINT_IEPMM_Pos                                   (5U)
#define USB_OTG_DIEPINT_IEPMM_Msk                                   (0x1UL << USB_OTG_DIEPINT_IEPMM_Pos)                           /*!< 0x00000004 */
#define USB_OTG_DIEPINT_IEPMM                                       USB_OTG_DIEPINT_IEPMM_Msk                                      /*!< IN token received with EP mismatch */
#define USB_OTG_DIEPINT_IEPNAKE_Pos                                 (6U)
#define USB_OTG_DIEPINT_IEPNAKE_Msk                                 (0x1UL << USB_OTG_DIEPINT_IEPNAKE_Pos)                         /*!< 0x00000040 */
#define USB_OTG_DIEPINT_IEPNAKE                                     USB_OTG_DIEPINT_IEPNAKE_Msk                                    /*!< IN endpoint NAK effective */
#define USB_OTG_DIEPINT_TXFE_Pos                                    (7U)
#define USB_OTG_DIEPINT_TXFE_Msk                                    (0x1UL << USB_OTG_DIEPINT_TXFE_Pos)                            /*!< 0x00000080 */
#define USB_OTG_DIEPINT_TXFE                                        USB_OTG_DIEPINT_TXFE_Msk                                       /*!< Transmit FIFO empty */
#define USB_OTG_DIEPINT_TXFUDR_Pos                                  (8U)
#define USB_OTG_DIEPINT_TXFUDR_Msk                                  (0x1UL << USB_OTG_DIEPINT_TXFUDR_Pos)                          /*!< 0x00000100 */
#define USB_OTG_DIEPINT_TXFUDR                                      USB_OTG_DIEPINT_TXFUDR_Msk                                     /*!< Transmit Fifo Underrun */
#define USB_OTG_DIEPINT_BUFFNA_Pos                                  (9U)
#define USB_OTG_DIEPINT_BUFFNA_Msk                                  (0x1UL << USB_OTG_DIEPINT_BUFFNA_Pos)                          /*!< 0x00000200 */
#define USB_OTG_DIEPINT_BUFFNA                                      USB_OTG_DIEPINT_BUFFNA_Msk                                     /*!< Buffer not available interrupt */
#define USB_OTG_DIEPINT_PDROFLG_Pos                                 (11U)
#define USB_OTG_DIEPINT_PDROFLG_Msk                                 (0x1UL << USB_OTG_DIEPINT_PDROFLG_Pos)                         /*!< 0x00000800 */
#define USB_OTG_DIEPINT_PDROFLG                                     USB_OTG_DIEPINT_PDROFLG_Msk                                    /*!< Packet dropped status */
#define USB_OTG_DIEPINT_BERR_Pos                                    (12U)
#define USB_OTG_DIEPINT_BERR_Msk                                    (0x1UL << USB_OTG_DIEPINT_BERR_Pos)                            /*!< 0x00001000 */
#define USB_OTG_DIEPINT_BERR                                        USB_OTG_DIEPINT_BERR_Msk                                       /*!< Babble error interrupt */
#define USB_OTG_DIEPINT_NAK_Pos                                     (13U)
#define USB_OTG_DIEPINT_NAK_Msk                                     (0x1UL << USB_OTG_DIEPINT_NAK_Pos)                             /*!< 0x00002000 */
#define USB_OTG_DIEPINT_NAK                                         USB_OTG_DIEPINT_NAK_Msk                                        /*!< NAK interrupt */

/********************  Bit definition forUSB_OTG_HCHIMASK register  ********************/
#define USB_OTG_HCHIMASK_TSFCMPNM_Pos                               (0U)
#define USB_OTG_HCHIMASK_TSFCMPNM_Msk                               (0x1UL << USB_OTG_HCHIMASK_TSFCMPNM_Pos)                       /*!< 0x00000001 */
#define USB_OTG_HCHIMASK_TSFCMPNM                                   USB_OTG_HCHIMASK_TSFCMPNM_Msk                                  /*!< Transfer completed mask */
#define USB_OTG_HCHIMASK_TSFCMPANM_Pos                              (1U)
#define USB_OTG_HCHIMASK_TSFCMPANM_Msk                              (0x1UL << USB_OTG_HCHIMASK_TSFCMPANM_Pos)                      /*!< 0x00000002 */
#define USB_OTG_HCHIMASK_TSFCMPANM                                  USB_OTG_HCHIMASK_TSFCMPANM_Msk                                 /*!< Channel halted mask */
#define USB_OTG_HCHIMASK_AHBERRM_Pos                                (2U)
#define USB_OTG_HCHIMASK_AHBERRM_Msk                                (0x1UL << USB_OTG_HCHIMASK_AHBERRM_Pos)                        /*!< 0x00000004 */
#define USB_OTG_HCHIMASK_AHBERRM                                    USB_OTG_HCHIMASK_AHBERRM_Msk                                   /*!< AHB error */
#define USB_OTG_HCHIMASK_RXSTALLM_Pos                               (3U)
#define USB_OTG_HCHIMASK_RXSTALLM_Msk                               (0x1UL << USB_OTG_HCHIMASK_RXSTALLM_Pos)                       /*!< 0x00000008 */
#define USB_OTG_HCHIMASK_RXSTALLM                                   USB_OTG_HCHIMASK_RXSTALLM_Msk                                  /*!< STALL response received interrupt mask */
#define USB_OTG_HCHIMASK_RXNAKM_Pos                                 (4U)
#define USB_OTG_HCHIMASK_RXNAKM_Msk                                 (0x1UL << USB_OTG_HCHIMASK_RXNAKM_Pos)                         /*!< 0x00000010 */
#define USB_OTG_HCHIMASK_RXNAKM                                     USB_OTG_HCHIMASK_RXNAKM_Msk                                    /*!< NAK response received interrupt mask */
#define USB_OTG_HCHIMASK_RXTXACKM_Pos                               (5U)
#define USB_OTG_HCHIMASK_RXTXACKM_Msk                               (0x1UL << USB_OTG_HCHIMASK_RXTXACKM_Pos)                       /*!< 0x00000020 */
#define USB_OTG_HCHIMASK_RXTXACKM                                   USB_OTG_HCHIMASK_RXTXACKM_Msk                                  /*!< ACK response received/transmitted interrupt mask */
#define USB_OTG_HCHIMASK_RXNYETM_Pos                                (6U)
#define USB_OTG_HCHIMASK_RXNYETM_Msk                                (0x1UL << USB_OTG_HCHIMASK_RXNYETM_Pos)                        /*!< 0x00000040 */
#define USB_OTG_HCHIMASK_RXNYETM                                    USB_OTG_HCHIMASK_RXNYETM_Msk                                   /*!< response received interrupt mask */
#define USB_OTG_HCHIMASK_TERRM_Pos                                  (7U)
#define USB_OTG_HCHIMASK_TERRM_Msk                                  (0x1UL << USB_OTG_HCHIMASK_TERRM_Pos)                          /*!< 0x00000080 */
#define USB_OTG_HCHIMASK_TERRM                                      USB_OTG_HCHIMASK_TERRM_Msk                                     /*!< Transaction error mask */
#define USB_OTG_HCHIMASK_BABBLEM_Pos                                (8U)
#define USB_OTG_HCHIMASK_BABBLEM_Msk                                (0x1UL << USB_OTG_HCHIMASK_BABBLEM_Pos)                        /*!< 0x00000100 */
#define USB_OTG_HCHIMASK_BABBLEM                                    USB_OTG_HCHIMASK_BABBLEM_Msk                                   /*!< Babble error mask */
#define USB_OTG_HCHIMASK_FOVRM_Pos                                  (9U)
#define USB_OTG_HCHIMASK_FOVRM_Msk                                  (0x1UL << USB_OTG_HCHIMASK_FOVRM_Pos)                          /*!< 0x00000200 */
#define USB_OTG_HCHIMASK_FOVRM                                      USB_OTG_HCHIMASK_FOVRM_Msk                                     /*!< Frame overrun mask */
#define USB_OTG_HCHIMASK_DTOGM_Pos                                  (10U)
#define USB_OTG_HCHIMASK_DTOGM_Msk                                  (0x1UL << USB_OTG_HCHIMASK_DTOGM_Pos)                          /*!< 0x00000400 */
#define USB_OTG_HCHIMASK_DTOGM                                      USB_OTG_HCHIMASK_DTOGM_Msk                                     /*!< Data toggle error mask */

/********************  Bit definition for USB_OTG_DIEPTRS register  ********************/

#define USB_OTG_DIEPTRS_EPTRS_Pos                                   (0U)
#define USB_OTG_DIEPTRS_EPTRS_Msk                                   (0x7FFFFUL << USB_OTG_DIEPTRS_EPTRS_Pos)                       /*!< 0x0007FFFF */
#define USB_OTG_DIEPTRS_EPTRS                                       USB_OTG_DIEPTRS_EPTRS_Msk                                      /*!< Transfer size */
#define USB_OTG_DIEPTRS_EPPCNT_Pos                                  (19U)
#define USB_OTG_DIEPTRS_EPPCNT_Msk                                  (0x3FFUL << USB_OTG_DIEPTRS_EPPCNT_Pos)                        /*!< 0x1FF80000 */
#define USB_OTG_DIEPTRS_EPPCNT                                      USB_OTG_DIEPTRS_EPPCNT_Msk                                     /*!< Packet count */
#define USB_OTG_DIEPTRS_TXDSEL_Pos                                  (29U)
#define USB_OTG_DIEPTRS_TXDSEL_Msk                                  (0x3UL << USB_OTG_DIEPTRS_TXDSEL_Pos)                          /*!< 0x60000000 */
#define USB_OTG_DIEPTRS_TXDSEL                                      USB_OTG_DIEPTRS_TXDSEL_Msk                                     /*!< Packet count */
/********************  Bit definition for USB_OTG_HCHTSIZE register  ********************/
#define USB_OTG_HCHTSIZE_TSFSIZE_Pos                                (0U)
#define USB_OTG_HCHTSIZE_TSFSIZE_Msk                                (0x7FFFFUL << USB_OTG_HCHTSIZE_TSFSIZE_Pos)                    /*!< 0x0007FFFF */
#define USB_OTG_HCHTSIZE_TSFSIZE                                    USB_OTG_HCHTSIZE_TSFSIZE_Msk                                   /*!< Transfer size */
#define USB_OTG_HCHTSIZE_PCKTCNT_Pos                                (19U)
#define USB_OTG_HCHTSIZE_PCKTCNT_Msk                                (0x3FFUL << USB_OTG_HCHTSIZE_PCKTCNT_Pos)                      /*!< 0x1FF80000 */
#define USB_OTG_HCHTSIZE_PCKTCNT                                    USB_OTG_HCHTSIZE_PCKTCNT_Msk                                   /*!< Packet count */
#define USB_OTG_HCHTSIZE_DO_PING_Pos                                (31U)
#define USB_OTG_HCHTSIZE_DO_PING_Msk                                (0x1UL << USB_OTG_HCHTSIZE_DO_PING_Pos)                        /*!< 0x80000000 */
#define USB_OTG_HCHTSIZE_DO_PING                                    USB_OTG_HCHTSIZE_DO_PING_Msk                                   /*!< Do PING */
#define USB_OTG_HCHTSIZE_DATAPID_Pos                                (29U)
#define USB_OTG_HCHTSIZE_DATAPID_Msk                                (0x3UL << USB_OTG_HCHTSIZE_DATAPID_Pos)                        /*!< 0x60000000 */
#define USB_OTG_HCHTSIZE_DATAPID                                    USB_OTG_HCHTSIZE_DATAPID_Msk                                   /*!< Data PID */
#define USB_OTG_HCHTSIZE_DATAPID_0                                  (0x1UL << USB_OTG_HCHTSIZE_DATAPID_Pos)                        /*!< 0x20000000 */
#define USB_OTG_HCHTSIZE_DATAPID_1                                  (0x2UL << USB_OTG_HCHTSIZE_DATAPID_Pos)                        /*!< 0x40000000 */

/********************  Bit definition for USB_OTG_DIEPDMA register  ********************/
#define USB_OTG_DIEPDMA_DMAADDR_Pos                                 (0U)
#define USB_OTG_DIEPDMA_DMAADDR_Msk                                 (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos)                  /*!< 0xFFFFFFFF */
#define USB_OTG_DIEPDMA_DMAADDR                                     USB_OTG_DIEPDMA_DMAADDR_Msk                                    /*!< DMA address */

/********************  Bit definition for USB_OTG_HCHDMA register  ********************/
#define USB_OTG_HCHDMA_ADDR_Pos                                     (0U)
#define USB_OTG_HCHDMA_ADDR_Msk                                     (0xFFFFFFFFUL << USB_OTG_HCHDMA_ADDR_Pos)                      /*!< 0xFFFFFFFF */
#define USB_OTG_HCHDMA_ADDR                                         USB_OTG_HCHDMA_ADDR_Msk                                        /*!< DMA address */

/********************  Bit definition for USB_OTG_DITXFSTS register  ********************/
#define USB_OTG_DITXFSTS_INEPTXFSA_Pos                              (0U)
#define USB_OTG_DITXFSTS_INEPTXFSA_Msk                              (0xFFFFUL << USB_OTG_DITXFSTS_INEPTXFSA_Pos)                   /*!< 0x0000FFFF */
#define USB_OTG_DITXFSTS_INEPTXFSA                                  USB_OTG_DITXFSTS_INEPTXFSA_Msk                                 /*!< IN endpoint TxFIFO space available */

/********************  Bit definition for USB_OTG_DTXFIFO register  ********************/
#define USB_OTG_DTXFIFO_INEPTXFRSA_Pos                              (0U)
#define USB_OTG_DTXFIFO_INEPTXFRSA_Msk                              (0xFFFFUL << USB_OTG_DTXFIFO_INEPTXFRSA_Pos)                   /*!< 0x0000FFFF */
#define USB_OTG_DTXFIFO_INEPTXFRSA                                  USB_OTG_DTXFIFO_INEPTXFRSA_Msk                                 /*!< IN endpoint FIFOx transmit RAM start address */
#define USB_OTG_DTXFIFO_INEPTXFDEP_Pos                              (16U)
#define USB_OTG_DTXFIFO_INEPTXFDEP_Msk                              (0xFFFFUL << USB_OTG_DTXFIFO_INEPTXFDEP_Pos)                   /*!< 0xFFFF0000 */
#define USB_OTG_DTXFIFO_INEPTXFDEP                                  USB_OTG_DTXFIFO_INEPTXFDEP_Msk                                 /*!< IN endpoint TxFIFO depth */

/********************  Bit definition for USB_OTG_DOEPCTRL register  ********************/

#define USB_OTG_DOEPCTRL_MAXPS_Pos                                  (0U)
#define USB_OTG_DOEPCTRL_MAXPS_Msk                                  (0x7FFUL << USB_OTG_DOEPCTRL_MAXPS_Pos)                        /*!< 0x000007FF */
#define USB_OTG_DOEPCTRL_MAXPS                                      USB_OTG_DOEPCTRL_MAXPS_Msk                                     /*!< Maximum packet size */          /*!<Bit 1 */
#define USB_OTG_DOEPCTRL_USBAEP_Pos                                 (15U)
#define USB_OTG_DOEPCTRL_USBAEP_Msk                                 (0x1UL << USB_OTG_DOEPCTRL_USBAEP_Pos)                         /*!< 0x00008000 */
#define USB_OTG_DOEPCTRL_USBAEP                                     USB_OTG_DOEPCTRL_USBAEP_Msk                                    /*!< USB active endpoint */
#define USB_OTG_DOEPCTRL_NAKSTS_Pos                                 (17U)
#define USB_OTG_DOEPCTRL_NAKSTS_Msk                                 (0x1UL << USB_OTG_DOEPCTRL_NAKSTS_Pos)                         /*!< 0x00020000 */
#define USB_OTG_DOEPCTRL_NAKSTS                                     USB_OTG_DOEPCTRL_NAKSTS_Msk                                    /*!< NAK status */
#define USB_OTG_DOEPCTRL_DPIDSET_Pos                                (28U)
#define USB_OTG_DOEPCTRL_DPIDSET_Msk                                (0x1UL << USB_OTG_DOEPCTRL_DPIDSET_Pos)                        /*!< 0x10000000 */
#define USB_OTG_DOEPCTRL_DPIDSET                                    USB_OTG_DOEPCTRL_DPIDSET_Msk                                   /*!< Set DATA0 PID */
#define USB_OTG_DOEPCTRL_OFSET_Pos                                  (29U)
#define USB_OTG_DOEPCTRL_OFSET_Msk                                  (0x1UL << USB_OTG_DOEPCTRL_OFSET_Pos)                          /*!< 0x20000000 */
#define USB_OTG_DOEPCTRL_OFSET                                      USB_OTG_DOEPCTRL_OFSET_Msk                                     /*!< Set odd frame */
#define USB_OTG_DOEPCTRL_EPTYPE_Pos                                 (18U)
#define USB_OTG_DOEPCTRL_EPTYPE_Msk                                 (0x3UL << USB_OTG_DOEPCTRL_EPTYPE_Pos)                         /*!< 0x000C0000 */
#define USB_OTG_DOEPCTRL_EPTYPE                                     USB_OTG_DOEPCTRL_EPTYPE_Msk                                    /*!< Endpoint type */
#define USB_OTG_DOEPCTRL_EPTYPE_0                                   (0x1UL << USB_OTG_DOEPCTRL_EPTYPE_Pos)                         /*!< 0x00040000 */
#define USB_OTG_DOEPCTRL_EPTYPE_1                                   (0x2UL << USB_OTG_DOEPCTRL_EPTYPE_Pos)                         /*!< 0x00080000 */
#define USB_OTG_DOEPCTRL_SNMEN_Pos                                  (20U)
#define USB_OTG_DOEPCTRL_SNMEN_Msk                                  (0x1UL << USB_OTG_DOEPCTRL_SNMEN_Pos)                          /*!< 0x00100000 */
#define USB_OTG_DOEPCTRL_SNMEN                                      USB_OTG_DOEPCTRL_SNMEN_Msk                                     /*!< Snoop mode */
#define USB_OTG_DOEPCTRL_STALLH_Pos                                 (21U)
#define USB_OTG_DOEPCTRL_STALLH_Msk                                 (0x1UL << USB_OTG_DOEPCTRL_STALLH_Pos)                         /*!< 0x00200000 */
#define USB_OTG_DOEPCTRL_STALLH                                     USB_OTG_DOEPCTRL_STALLH_Msk                                    /*!< STALL handshake */
#define USB_OTG_DOEPCTRL_NAKCLR_Pos                                 (26U)
#define USB_OTG_DOEPCTRL_NAKCLR_Msk                                 (0x1UL << USB_OTG_DOEPCTRL_NAKCLR_Pos)                         /*!< 0x04000000 */
#define USB_OTG_DOEPCTRL_NAKCLR                                     USB_OTG_DOEPCTRL_NAKCLR_Msk                                    /*!< Clear NAK */
#define USB_OTG_DOEPCTRL_NAKSET_Pos                                 (27U)
#define USB_OTG_DOEPCTRL_NAKSET_Msk                                 (0x1UL << USB_OTG_DOEPCTRL_NAKSET_Pos)                         /*!< 0x08000000 */
#define USB_OTG_DOEPCTRL_NAKSET                                     USB_OTG_DOEPCTRL_NAKSET_Msk                                    /*!< Set NAK */
#define USB_OTG_DOEPCTRL_EPDIS_Pos                                  (30U)
#define USB_OTG_DOEPCTRL_EPDIS_Msk                                  (0x1UL << USB_OTG_DOEPCTRL_EPDIS_Pos)                          /*!< 0x40000000 */
#define USB_OTG_DOEPCTRL_EPDIS                                      USB_OTG_DOEPCTRL_EPDIS_Msk                                     /*!< Endpoint disable */
#define USB_OTG_DOEPCTRL_EPEN_Pos                                   (31U)
#define USB_OTG_DOEPCTRL_EPEN_Msk                                   (0x1UL << USB_OTG_DOEPCTRL_EPEN_Pos)                           /*!< 0x80000000 */
#define USB_OTG_DOEPCTRL_EPEN                                       USB_OTG_DOEPCTRL_EPEN_Msk                                      /*!< Endpoint enable */

/********************  Bit definition for USB_OTG_DOEPINT register  ********************/
#define USB_OTG_DOEPINT_TSFCMP_Pos                                  (0U)
#define USB_OTG_DOEPINT_TSFCMP_Msk                                  (0x1UL << USB_OTG_DOEPINT_TSFCMP_Pos)                          /*!< 0x00000001 */
#define USB_OTG_DOEPINT_TSFCMP                                      USB_OTG_DOEPINT_TSFCMP_Msk                                     /*!< Transfer completed interrupt */
#define USB_OTG_DOEPINT_EPDIS_Pos                                   (1U)
#define USB_OTG_DOEPINT_EPDIS_Msk                                   (0x1UL << USB_OTG_DOEPINT_EPDIS_Pos)                           /*!< 0x00000002 */
#define USB_OTG_DOEPINT_EPDIS                                       USB_OTG_DOEPINT_EPDIS_Msk                                      /*!< Endpoint disabled interrupt */
#define USB_OTG_DOEPINT_AHBERR_Pos                                  (2U)
#define USB_OTG_DOEPINT_AHBERR_Msk                                  (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos)                          /*!< 0x00000004 */
#define USB_OTG_DOEPINT_AHBERR                                      USB_OTG_DOEPINT_AHBERR_Msk                                     /*!< AHB Error (AHBErr) during an OUT transaction */
#define USB_OTG_DOEPINT_SETPCMP_Pos                                 (3U)
#define USB_OTG_DOEPINT_SETPCMP_Msk                                 (0x1UL << USB_OTG_DOEPINT_SETPCMP_Pos)                         /*!< 0x00000008 */
#define USB_OTG_DOEPINT_SETPCMP                                     USB_OTG_DOEPINT_SETPCMP_Msk                                    /*!< SETUP phase done */
#define USB_OTG_DOEPINT_RXOTDIS_Pos                                 (4U)
#define USB_OTG_DOEPINT_RXOTDIS_Msk                                 (0x1UL << USB_OTG_DOEPINT_RXOTDIS_Pos)                         /*!< 0x00000010 */
#define USB_OTG_DOEPINT_RXOTDIS                                     USB_OTG_DOEPINT_RXOTDIS_Msk                                    /*!< OUT token received when endpoint disabled */
#define USB_OTG_DOEPINT_OTEPSPR_Pos                                 (5U)
#define USB_OTG_DOEPINT_OTEPSPR_Msk                                 (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos)                         /*!< 0x00000020 */
#define USB_OTG_DOEPINT_OTEPSPR                                     USB_OTG_DOEPINT_OTEPSPR_Msk                                    /*!< Status Phase Received For Control Write */
#define USB_OTG_DOEPINT_RXBSP_Pos                                   (6U)
#define USB_OTG_DOEPINT_RXBSP_Msk                                   (0x1UL << USB_OTG_DOEPINT_RXBSP_Pos)                           /*!< 0x00000040 */
#define USB_OTG_DOEPINT_RXBSP                                       USB_OTG_DOEPINT_RXBSP_Msk                                      /*!< Back-to-back SETUP packets received */
#define USB_OTG_DOEPINT_OUTPKTERR_Pos                               (8U)
#define USB_OTG_DOEPINT_OUTPKTERR_Msk                               (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos)                       /*!< 0x00000100 */
#define USB_OTG_DOEPINT_OUTPKTERR                                   USB_OTG_DOEPINT_OUTPKTERR_Msk                                  /*!< OUT packet error */
#define USB_OTG_DOEPINT_NAK_Pos                                     (13U)
#define USB_OTG_DOEPINT_NAK_Msk                                     (0x1UL << USB_OTG_DOEPINT_NAK_Pos)                             /*!< 0x00002000 */
#define USB_OTG_DOEPINT_NAK                                         USB_OTG_DOEPINT_NAK_Msk                                        /*!< NAK Packet is transmitted by the device */
#define USB_OTG_DOEPINT_NYET_Pos                                    (14U)
#define USB_OTG_DOEPINT_NYET_Msk                                    (0x1UL << USB_OTG_DOEPINT_NYET_Pos)                            /*!< 0x00004000 */
#define USB_OTG_DOEPINT_NYET                                        USB_OTG_DOEPINT_NYET_Msk                                       /*!< NYET interrupt */
#define USB_OTG_DOEPINT_STPKTRX_Pos                                 (15U)
#define USB_OTG_DOEPINT_STPKTRX_Msk                                 (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos)                         /*!< 0x00008000 */
#define USB_OTG_DOEPINT_STPKTRX                                     USB_OTG_DOEPINT_STPKTRX_Msk                                    /*!< Setup Packet Received */
/********************  Bit definition for USB_OTG_DOEPTRS register  ********************/

#define USB_OTG_DOEPTRS_EPTRS_Pos                                   (0U)
#define USB_OTG_DOEPTRS_EPTRS_Msk                                   (0x7FFFFUL << USB_OTG_DOEPTRS_EPTRS_Pos)                       /*!< 0x0007FFFF */
#define USB_OTG_DOEPTRS_EPTRS                                       USB_OTG_DOEPTRS_EPTRS_Msk                                      /*!< Transfer size */
#define USB_OTG_DOEPTRS_EPPCNT_Pos                                  (19U)
#define USB_OTG_DOEPTRS_EPPCNT_Msk                                  (0x3FFUL << USB_OTG_DOEPTRS_EPPCNT_Pos)                        /*!< 0x1FF80000 */
#define USB_OTG_DOEPTRS_EPPCNT                                      USB_OTG_DOEPTRS_EPPCNT_Msk                                     /*!< Packet count */

#define USB_OTG_DOEPTRS_SPCNT_Pos                                   (29U)
#define USB_OTG_DOEPTRS_SPCNT_Msk                                   (0x3UL << USB_OTG_DOEPTRS_SPCNT_Pos)                           /*!< 0x60000000 */
#define USB_OTG_DOEPTRS_SPCNT                                       USB_OTG_DOEPTRS_SPCNT_Msk                                      /*!< SETUP packet count */
#define USB_OTG_DOEPTRS_SPCNT_0                                     (0x1UL << USB_OTG_DOEPTRS_SPCNT_Pos)                           /*!< 0x20000000 */
#define USB_OTG_DOEPTRS_SPCNT_1                                     (0x2UL << USB_OTG_DOEPTRS_SPCNT_Pos)                           /*!< 0x40000000 */

/********************  Bit definition for USB_OTG_DOEPDMA register  ********************/
#define USB_OTG_DOEPDMA_DMAADDR_Pos                                 (0U)
#define USB_OTG_DOEPDMA_DMAADDR_Msk                                 (0xFFFFFFFFUL << USB_OTG_DOEPDMA_DMAADDR_Pos)                  /*!< 0xFFFFFFFF */
#define USB_OTG_DOEPDMA_DMAADDR                                     USB_OTG_DOEPDMA_DMAADDR_Msk                                    /*!< DMA address */


/********************  Bit definition for PCGCCTL register  ********************/
#define USB_OTG_PCGCCTL_STOPCLK_Pos                                 (0U)
#define USB_OTG_PCGCCTL_STOPCLK_Msk                                 (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos)                         /*!< 0x00000001 */
#define USB_OTG_PCGCCTL_STOPCLK                                     USB_OTG_PCGCCTL_STOPCLK_Msk                                    /*!< SETUP packet count */
#define USB_OTG_PCGCCTL_GATECLK_Pos                                 (1U)
#define USB_OTG_PCGCCTL_GATECLK_Msk                                 (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos)                         /*!< 0x00000002 */
#define USB_OTG_PCGCCTL_GATECLK                                     USB_OTG_PCGCCTL_GATECLK_Msk                                    /*!<Bit 0 */
#define USB_OTG_PCGCCTL_PHYSUSP_Pos                                 (4U)
#define USB_OTG_PCGCCTL_PHYSUSP_Msk                                 (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos)                         /*!< 0x00000010 */
#define USB_OTG_PCGCCTL_PHYSUSP                                     USB_OTG_PCGCCTL_PHYSUSP_Msk                                    /*!<Bit 1 */

/* Legacy define */
/********************  Bit definition for OTG register  ********************/
#define USB_OTG_CHNUM_Pos                                           (0U)
#define USB_OTG_CHNUM_Msk                                           (0xFUL << USB_OTG_CHNUM_Pos)                                   /*!< 0x0000000F */
#define USB_OTG_CHNUM                                               USB_OTG_CHNUM_Msk                                              /*!< Channel number */
#define USB_OTG_CHNUM_0                                             (0x1UL << USB_OTG_CHNUM_Pos)                                   /*!< 0x00000001 */
#define USB_OTG_CHNUM_1                                             (0x2UL << USB_OTG_CHNUM_Pos)                                   /*!< 0x00000002 */
#define USB_OTG_CHNUM_2                                             (0x4UL << USB_OTG_CHNUM_Pos)                                   /*!< 0x00000004 */
#define USB_OTG_CHNUM_3                                             (0x8UL << USB_OTG_CHNUM_Pos)                                   /*!< 0x00000008 */
#define USB_OTG_BCNT_Pos                                            (4U)
#define USB_OTG_BCNT_Msk                                            (0x7FFUL << USB_OTG_BCNT_Pos)                                  /*!< 0x00007FF0 */
#define USB_OTG_BCNT                                                USB_OTG_BCNT_Msk                                               /*!< Byte count */

#define USB_OTG_DPID_Pos                                            (15U)
#define USB_OTG_DPID_Msk                                            (0x3UL << USB_OTG_DPID_Pos)                                    /*!< 0x00018000 */
#define USB_OTG_DPID                                                USB_OTG_DPID_Msk                                               /*!< Data PID */
#define USB_OTG_DPID_0                                              (0x1UL << USB_OTG_DPID_Pos)                                    /*!< 0x00008000 */
#define USB_OTG_DPID_1                                              (0x2UL << USB_OTG_DPID_Pos)                                    /*!< 0x00010000 */

#define USB_OTG_PKTSTS_Pos                                          (17U)
#define USB_OTG_PKTSTS_Msk                                          (0xFUL << USB_OTG_PKTSTS_Pos)                                  /*!< 0x001E0000 */
#define USB_OTG_PKTSTS                                              USB_OTG_PKTSTS_Msk                                             /*!< Packet status */
#define USB_OTG_PKTSTS_0                                            (0x1UL << USB_OTG_PKTSTS_Pos)                                  /*!< 0x00020000 */
#define USB_OTG_PKTSTS_1                                            (0x2UL << USB_OTG_PKTSTS_Pos)                                  /*!< 0x00040000 */
#define USB_OTG_PKTSTS_2                                            (0x4UL << USB_OTG_PKTSTS_Pos)                                  /*!< 0x00080000 */
#define USB_OTG_PKTSTS_3                                            (0x8UL << USB_OTG_PKTSTS_Pos)                                  /*!< 0x00100000 */

#define USB_OTG_EPNUM_Pos                                           (0U)
#define USB_OTG_EPNUM_Msk                                           (0xFUL << USB_OTG_EPNUM_Pos)                                   /*!< 0x0000000F */
#define USB_OTG_EPNUM                                               USB_OTG_EPNUM_Msk                                              /*!< Endpoint number */
#define USB_OTG_EPNUM_0                                             (0x1UL << USB_OTG_EPNUM_Pos)                                   /*!< 0x00000001 */
#define USB_OTG_EPNUM_1                                             (0x2UL << USB_OTG_EPNUM_Pos)                                   /*!< 0x00000002 */
#define USB_OTG_EPNUM_2                                             (0x4UL << USB_OTG_EPNUM_Pos)                                   /*!< 0x00000004 */
#define USB_OTG_EPNUM_3                                             (0x8UL << USB_OTG_EPNUM_Pos)                                   /*!< 0x00000008 */

#define USB_OTG_FRMNUM_Pos                                          (21U)
#define USB_OTG_FRMNUM_Msk                                          (0xFUL << USB_OTG_FRMNUM_Pos)                                  /*!< 0x01E00000 */
#define USB_OTG_FRMNUM                                              USB_OTG_FRMNUM_Msk                                             /*!< Frame number */
#define USB_OTG_FRMNUM_0                                            (0x1UL << USB_OTG_FRMNUM_Pos)                                  /*!< 0x00200000 */
#define USB_OTG_FRMNUM_1                                            (0x2UL << USB_OTG_FRMNUM_Pos)                                  /*!< 0x00400000 */
#define USB_OTG_FRMNUM_2                                            (0x4UL << USB_OTG_FRMNUM_Pos)                                  /*!< 0x00800000 */
#define USB_OTG_FRMNUM_3                                            (0x8UL << USB_OTG_FRMNUM_Pos)                                  /*!< 0x01000000 */

/********************  Bit definition for OTG HS2 register  ********************/
#define USB_OTG_HS2_USB_SWITCH_usb_switch_Pos                       (0U)
#define USB_OTG_HS2_USB_SWITCH_usb_switch_Msk                       (0x1UL << USB_OTG_HS2_USB_SWITCH_usb_switch_Pos)               /*!< 0x00000001 */
#define USB_OTG_HS2_USB_SWITCH                                      USB_OTG_HS2_USB_SWITCH_usb_switch_Msk                          /*!< USB Switch */

#define USB_OTG_HS2_POWERON_CORE_poweron_core_Pos                   (0U)
#define USB_OTG_HS2_POWERON_CORE_poweron_core_Msk                   (0x1UL << USB_OTG_HS2_POWERON_CORE_poweron_core_Pos)           /*!< 0x00000001 */
#define USB_OTG_HS2_POWERON_CORE                                    USB_OTG_HS2_POWERON_CORE_poweron_core_Msk                      /*!< Power On Core */

#define USB_OTG_HS2_USB_PLL_EN_usb_pll_en_Pos                       (0U)
#define USB_OTG_HS2_USB_PLL_EN_usb_pll_en_Msk                       (0x1UL << USB_OTG_HS2_USB_PLL_EN_usb_pll_en_Pos)               /*!< 0x00000001 */
#define USB_OTG_HS2_USB_PLL_EN                                      USB_OTG_HS2_USB_PLL_EN_usb_pll_en_Msk                          /*!< USB PLL Enable */

#define USB_OTG_HS2_SHORT_5V_ENABLE_short_5v_enable_Pos             (0U)
#define USB_OTG_HS2_SHORT_5V_ENABLE_short_5v_enable_Msk             (0x1UL << USB_OTG_HS2_SHORT_5V_ENABLE_short_5v_enable_Pos)     /*!< 0x00000001 */
#define USB_OTG_HS2_SHORT_5V_ENABLE                                 USB_OTG_HS2_SHORT_5V_ENABLE_short_5v_enable_Msk                /*!< Short 5V Enable */

#define USB_OTG_HS2_OTG_SUSPENDM_otg_suspendm_Pos                   (0U)
#define USB_OTG_HS2_OTG_SUSPENDM_otg_suspendm_Msk                   (0x1UL << USB_OTG_HS2_OTG_SUSPENDM_otg_suspendm_Pos)           /*!< 0x00000001 */
#define USB_OTG_HS2_OTG_SUSPENDM                                    USB_OTG_HS2_OTG_SUSPENDM_otg_suspendm_Msk                      /*!< OTG VBUS Suspend */

#define USB_OTG_HS2_TXBITSTUFFENABLE_txbitstuffenable_Pos           (0U)
#define USB_OTG_HS2_TXBITSTUFFENABLE_txbitstuffenable_Msk           (0x1UL << USB_OTG_HS2_TXBITSTUFFENABLE_txbitstuffenable_Pos)   /*!< 0x00000001 */
#define USB_OTG_HS2_TXBITSTUFFENABLE                                USB_OTG_HS2_TXBITSTUFFENABLE_txbitstuffenable_Msk              /*!< TX Bit Stuff Enable */

#define USB_OTG_HS2_PLLICP_SEL_I2C_pllicp_sel_i2c_Pos               (0U)
#define USB_OTG_HS2_PLLICP_SEL_I2C_pllicp_sel_i2c_Msk               (0x1UL << USB_OTG_HS2_PLLICP_SEL_I2C_pllicp_sel_i2c_Pos)       /*!< 0x00000001 */
#define USB_OTG_HS2_PLLICP_SEL_I2C                                  USB_OTG_HS2_PLLICP_SEL_I2C_pllicp_sel_i2c_Msk                  /*!< PLL Charge Current Setting */

#define USB_OTG_HS2_HSZR_CNTL_I2C_hszr_cntl_i2c_Pos                 (0U)
#define USB_OTG_HS2_HSZR_CNTL_I2C_hszr_cntl_i2c_Msk                 (0x7UL << USB_OTG_HS2_HSZR_CNTL_I2C_hszr_cntl_i2c_Pos)         /*!< 0x00000007 */
#define USB_OTG_HS2_HSZR_CNTL_I2C                                   USB_OTG_HS2_HSZR_CNTL_I2C_hszr_cntl_i2c_Msk                    /*!< The DP/DM to the Ground Impedance Setting */

#define USB_OTG_HS2_SQVTH_CNTL_I2C_sqvth_cntl_i2c_Pos               (0U)
#define USB_OTG_HS2_SQVTH_CNTL_I2C_sqvth_cntl_i2c_Msk               (0x3UL << USB_OTG_HS2_SQVTH_CNTL_I2C_sqvth_cntl_i2c_Pos)       /*!< 0x00000003 */
#define USB_OTG_HS2_SQVTH_CNTL_I2C                                  USB_OTG_HS2_SQVTH_CNTL_I2C_sqvth_cntl_i2c_Msk                  /*!< The SQ Reference Voltage Setting */

#define USB_OTG_HS2_SW_RREF_I2C_sw_rref_i2c_Pos                     (0U)
#define USB_OTG_HS2_SW_RREF_I2C_sw_rref_i2c_Msk                     (0x7UL << USB_OTG_HS2_SW_RREF_I2C_sw_rref_i2c_Pos)             /*!< 0x00000007 */
#define USB_OTG_HS2_SW_RREF_I2C                                     USB_OTG_HS2_SW_RREF_I2C_sw_rref_i2c_Msk                        /*!< The DP/DM Output Swing Setting When HS Mode */

#define USB_OTG_HS2_SW_BUF_I2C_sw_buf_i2c_Pos                       (0U)
#define USB_OTG_HS2_SW_BUF_I2C_sw_buf_i2c_Msk                       (0x1UL << USB_OTG_HS2_SW_BUF_I2C_sw_buf_i2c_Pos)               /*!< 0x00000001 */
#define USB_OTG_HS2_SW_BUF_I2C                                      USB_OTG_HS2_SW_BUF_I2C_sw_buf_i2c_Msk                          /*!< The TX Driver Setting */

#define USB_OTG_HS2_TX2RX_T_CFG_tx2rx_t_cfg_i2c_Pos                 (0U)
#define USB_OTG_HS2_TX2RX_T_CFG_tx2rx_t_cfg_i2c_Msk                 (0x3UL << USB_OTG_HS2_TX2RX_T_CFG_tx2rx_t_cfg_i2c_Pos)         /*!< 0x00000003 */
#define USB_OTG_HS2_TX2RX_T_CFG                                     USB_OTG_HS2_TX2RX_T_CFG_tx2rx_t_cfg_i2c_Msk                    /*!< Debug Control Signal */

#define USB_OTG_HS2_TEST_ANA_FAST_I2C_test_ana_fast_i2c_Pos         (0U)
#define USB_OTG_HS2_TEST_ANA_FAST_I2C_test_ana_fast_i2c_Msk         (0x7UL << USB_OTG_HS2_TEST_ANA_FAST_I2C_test_ana_fast_i2c_Pos) /*!< 0x00000007 */
#define USB_OTG_HS2_TEST_ANA_FAST_I2C                               USB_OTG_HS2_TEST_ANA_FAST_I2C_test_ana_fast_i2c_Msk            /*!< Debug Control Signal */

#define USB_OTG_HS2_CLK_MODE_I2C_clk_mode_i2c_Pos                   (0U)
#define USB_OTG_HS2_CLK_MODE_I2C_clk_mode_i2c_Msk                   (0x7UL << USB_OTG_HS2_CLK_MODE_I2C_clk_mode_i2c_Pos)           /*!< 0x00000007 */
#define USB_OTG_HS2_CLK_MODE_I2C                                    USB_OTG_HS2_CLK_MODE_I2C_clk_mode_i2c_Msk                      /*!< Debug Control Signal */

#define USB_OTG_HS2_USB_DBNCE_FLTR_BYPASS_usb_dbnce_fltr_bypass_Pos (0U)
#define USB_OTG_HS2_USB_DBNCE_FLTR_BYPASS_usb_dbnce_fltr_bypass_Msk (0x1UL << USB_OTG_HS2_CLK_MODE_I2C_clk_mode_i2c_Pos)           /*!< 0x00000001 */
#define USB_OTG_HS2_USB_DBNCE_FLTR_BYPASS                           USB_OTG_HS2_CLK_MODE_I2C_clk_mode_i2c_Msk                      /*!< Bypass debounce filters for avalid, bvalid, vbusvalid, sessend, iddig signals when enabled */

#define USB_OTG_HS2_USB_SS_SCALEDOWN_MODE_clk_mode_i2c_Pos          (0U)
#define USB_OTG_HS2_USB_SS_SCALEDOWN_MODE_clk_mode_i2c_Msk          (0x7UL << USB_OTG_HS2_CLK_MODE_I2C_clk_mode_i2c_Pos)           /*!< 0x00000007 */
#define USB_OTG_HS2_USB_SS_SCALEDOWN_MODE                           USB_OTG_HS2_CLK_MODE_I2C_clk_mode_i2c_Msk                      /*!< Debug Control Signal */

/**
  * @}
  */ 

/**
  * @}
  */

/** @addtogroup Exported_macros
  * @{
  */

/******************************* ADC Instances ********************************/
#define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
                                       ((INSTANCE) == ADC2) || \
                                       ((INSTANCE) == ADC3))

#define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)

#define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC123_COMMON)

/******************************* CAN Instances ********************************/
#define IS_CAN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == CAN1) || \
                                       ((INSTANCE) == CAN2))
/******************************* CRC Instances ********************************/
#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)

/******************************* DAC Instances ********************************/
#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)

/******************************* DCI Instances *******************************/
#define IS_DCI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DCI)

/******************************** DMA Instances *******************************/
#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
                                              ((INSTANCE) == DMA1_Stream1) || \
                                              ((INSTANCE) == DMA1_Stream2) || \
                                              ((INSTANCE) == DMA1_Stream3) || \
                                              ((INSTANCE) == DMA1_Stream4) || \
                                              ((INSTANCE) == DMA1_Stream5) || \
                                              ((INSTANCE) == DMA1_Stream6) || \
                                              ((INSTANCE) == DMA1_Stream7) || \
                                              ((INSTANCE) == DMA2_Stream0) || \
                                              ((INSTANCE) == DMA2_Stream1) || \
                                              ((INSTANCE) == DMA2_Stream2) || \
                                              ((INSTANCE) == DMA2_Stream3) || \
                                              ((INSTANCE) == DMA2_Stream4) || \
                                              ((INSTANCE) == DMA2_Stream5) || \
                                              ((INSTANCE) == DMA2_Stream6) || \
                                              ((INSTANCE) == DMA2_Stream7))

/******************************* GPIO Instances *******************************/
#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
                                        ((INSTANCE) == GPIOB) || \
                                        ((INSTANCE) == GPIOC) || \
                                        ((INSTANCE) == GPIOD) || \
                                        ((INSTANCE) == GPIOE) || \
                                        ((INSTANCE) == GPIOF) || \
                                        ((INSTANCE) == GPIOG) || \
                                        ((INSTANCE) == GPIOH) || \
                                        ((INSTANCE) == GPIOI))

/******************************** I2C Instances *******************************/
#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
                                       ((INSTANCE) == I2C2) || \
                                       ((INSTANCE) == I2C3))

/******************************* SMBUS Instances ******************************/
#define IS_SMBUS_ALL_INSTANCE         IS_I2C_ALL_INSTANCE

/******************************** I2S Instances *******************************/

#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \
                                       ((INSTANCE) == SPI3))

/*************************** I2S Extended Instances ***************************/
#define IS_I2S_EXT_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2S2ext)|| \
                                           ((INSTANCE) == I2S3ext))
/* Legacy Defines */
#define IS_I2S_ALL_INSTANCE_EXT    IS_I2S_EXT_ALL_INSTANCE

/******************************* RNG Instances ********************************/
#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)

/****************************** RTC Instances *********************************/
#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)


/******************************** SPI Instances *******************************/
#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
                                       ((INSTANCE) == SPI2) || \
                                       ((INSTANCE) == SPI3))


/****************** TMR Instances : All supported instances *******************/
#define IS_TMR_INSTANCE(INSTANCE) (((INSTANCE) == TMR1)  || \
                                    ((INSTANCE) == TMR2) || \
                                    ((INSTANCE) == TMR3) || \
                                    ((INSTANCE) == TMR4) || \
                                    ((INSTANCE) == TMR5) || \
                                    ((INSTANCE) == TMR6) || \
                                    ((INSTANCE) == TMR7) || \
                                    ((INSTANCE) == TMR8) || \
                                    ((INSTANCE) == TMR9) || \
                                    ((INSTANCE) == TMR10)|| \
                                    ((INSTANCE) == TMR11)|| \
                                    ((INSTANCE) == TMR12)|| \
                                    ((INSTANCE) == TMR13)|| \
                                    ((INSTANCE) == TMR14))

/************* TMR Instances : at least 1 capture/compare channel *************/
#define IS_TMR_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TMR1)  || \
                                         ((INSTANCE) == TMR2)  || \
                                         ((INSTANCE) == TMR3)  || \
                                         ((INSTANCE) == TMR4)  || \
                                         ((INSTANCE) == TMR5)  || \
                                         ((INSTANCE) == TMR8)  || \
                                         ((INSTANCE) == TMR9)  || \
                                         ((INSTANCE) == TMR10) || \
                                         ((INSTANCE) == TMR11) || \
                                         ((INSTANCE) == TMR12) || \
                                         ((INSTANCE) == TMR13) || \
                                         ((INSTANCE) == TMR14))

/************ TMR Instances : at least 2 capture/compare channels *************/
#define IS_TMR_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \
                                       ((INSTANCE) == TMR2) || \
                                       ((INSTANCE) == TMR3) || \
                                       ((INSTANCE) == TMR4) || \
                                       ((INSTANCE) == TMR5) || \
                                       ((INSTANCE) == TMR8) || \
                                       ((INSTANCE) == TMR9) || \
                                       ((INSTANCE) == TMR12)) 

/************ TMR Instances : at least 3 capture/compare channels *************/
#define IS_TMR_CC3_INSTANCE(INSTANCE)   (((INSTANCE) == TMR1) || \
                                         ((INSTANCE) == TMR2) || \
                                         ((INSTANCE) == TMR3) || \
                                         ((INSTANCE) == TMR4) || \
                                         ((INSTANCE) == TMR5) || \
                                         ((INSTANCE) == TMR8))

/************ TMR Instances : at least 4 capture/compare channels *************/
#define IS_TMR_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \
                                       ((INSTANCE) == TMR2) || \
                                       ((INSTANCE) == TMR3) || \
                                       ((INSTANCE) == TMR4) || \
                                       ((INSTANCE) == TMR5) || \
                                       ((INSTANCE) == TMR8))

/******************** TMR Instances : Advanced-control timers *****************/
#define IS_TMR_ADVANCED_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \
                                           ((INSTANCE) == TMR8))

/******************* TMR Instances : Timer input XOR function *****************/
#define IS_TMR_XOR_INSTANCE(INSTANCE)   (((INSTANCE) == TMR1) || \
                                         ((INSTANCE) == TMR2) || \
                                         ((INSTANCE) == TMR3) || \
                                         ((INSTANCE) == TMR4) || \
                                         ((INSTANCE) == TMR5) || \
                                         ((INSTANCE) == TMR8))

/****************** TMR Instances : DMA requests generation (UDE) *************/
#define IS_TMR_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \
                                       ((INSTANCE) == TMR2) || \
                                       ((INSTANCE) == TMR3) || \
                                       ((INSTANCE) == TMR4) || \
                                       ((INSTANCE) == TMR5) || \
                                       ((INSTANCE) == TMR6) || \
                                       ((INSTANCE) == TMR7) || \
                                       ((INSTANCE) == TMR8))

/************ TMR Instances : DMA requests generation (CCxDE) *****************/
#define IS_TMR_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \
                                          ((INSTANCE) == TMR2) || \
                                          ((INSTANCE) == TMR3) || \
                                          ((INSTANCE) == TMR4) || \
                                          ((INSTANCE) == TMR5) || \
                                          ((INSTANCE) == TMR8))

/************ TMR Instances : DMA requests generation (COMDE) *****************/
#define IS_TMR_CCDMA_INSTANCE(INSTANCE)  (((INSTANCE) == TMR1) || \
                                          ((INSTANCE) == TMR2) || \
                                          ((INSTANCE) == TMR3) || \
                                          ((INSTANCE) == TMR4) || \
                                          ((INSTANCE) == TMR5) || \
                                          ((INSTANCE) == TMR8))

/******************** TMR Instances : DMA burst feature ***********************/
#define IS_TMR_DMABURST_INSTANCE(INSTANCE)  (((INSTANCE) == TMR1) || \
                                             ((INSTANCE) == TMR2) || \
                                             ((INSTANCE) == TMR3) || \
                                             ((INSTANCE) == TMR4) || \
                                             ((INSTANCE) == TMR5) || \
                                             ((INSTANCE) == TMR8))

/****** TMR Instances : master mode available (TMRx_CR2.MMS available )********/
#define IS_TMR_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TMR1)  || \
                                          ((INSTANCE) == TMR2)  || \
                                          ((INSTANCE) == TMR3)  || \
                                          ((INSTANCE) == TMR4)  || \
                                          ((INSTANCE) == TMR5)  || \
                                          ((INSTANCE) == TMR6)  || \
                                          ((INSTANCE) == TMR7)  || \
                                          ((INSTANCE) == TMR8))

/*********** TMR Instances : Slave mode available (TMRx_SMCR available )*******/
#define IS_TMR_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \
                                         ((INSTANCE) == TMR2) || \
                                         ((INSTANCE) == TMR3) || \
                                         ((INSTANCE) == TMR4) || \
                                         ((INSTANCE) == TMR5) || \
                                         ((INSTANCE) == TMR8) || \
                                         ((INSTANCE) == TMR9) || \
                                         ((INSTANCE) == TMR12))
/********************** TMR Instances : 32 bit Counter ************************/
#define IS_TMR_32B_COUNTER_INSTANCE(INSTANCE)(((INSTANCE) == TMR2) || \
                                              ((INSTANCE) == TMR5))

/***************** TMR Instances : external trigger input available ************/
#define IS_TMR_ETR_INSTANCE(INSTANCE)  (((INSTANCE) == TMR1) || \
                                        ((INSTANCE) == TMR2) || \
                                        ((INSTANCE) == TMR3) || \
                                        ((INSTANCE) == TMR4) || \
                                        ((INSTANCE) == TMR5) || \
                                        ((INSTANCE) == TMR8))

/****************** TMR Instances : remapping capability **********************/
#define IS_TMR_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TMR2)  || \
                                         ((INSTANCE) == TMR5)  || \
                                         ((INSTANCE) == TMR11))

/******************* TMR Instances : output(s) available **********************/
#define IS_TMR_CCX_INSTANCE(INSTANCE, CHANNEL) \
    ((((INSTANCE) == TMR1) &&                  \
     (((CHANNEL) == TMR_CHANNEL_1) ||          \
      ((CHANNEL) == TMR_CHANNEL_2) ||          \
      ((CHANNEL) == TMR_CHANNEL_3) ||          \
      ((CHANNEL) == TMR_CHANNEL_4)))           \
    ||                                         \
    (((INSTANCE) == TMR2) &&                   \
     (((CHANNEL) == TMR_CHANNEL_1) ||          \
      ((CHANNEL) == TMR_CHANNEL_2) ||          \
      ((CHANNEL) == TMR_CHANNEL_3) ||          \
      ((CHANNEL) == TMR_CHANNEL_4)))           \
    ||                                         \
    (((INSTANCE) == TMR3) &&                   \
     (((CHANNEL) == TMR_CHANNEL_1) ||          \
      ((CHANNEL) == TMR_CHANNEL_2) ||          \
      ((CHANNEL) == TMR_CHANNEL_3) ||          \
      ((CHANNEL) == TMR_CHANNEL_4)))           \
    ||                                         \
    (((INSTANCE) == TMR4) &&                   \
     (((CHANNEL) == TMR_CHANNEL_1) ||          \
      ((CHANNEL) == TMR_CHANNEL_2) ||          \
      ((CHANNEL) == TMR_CHANNEL_3) ||          \
      ((CHANNEL) == TMR_CHANNEL_4)))           \
    ||                                         \
    (((INSTANCE) == TMR5) &&                   \
     (((CHANNEL) == TMR_CHANNEL_1) ||          \
      ((CHANNEL) == TMR_CHANNEL_2) ||          \
      ((CHANNEL) == TMR_CHANNEL_3) ||          \
      ((CHANNEL) == TMR_CHANNEL_4)))           \
    ||                                         \
    (((INSTANCE) == TMR8) &&                   \
     (((CHANNEL) == TMR_CHANNEL_1) ||          \
      ((CHANNEL) == TMR_CHANNEL_2) ||          \
      ((CHANNEL) == TMR_CHANNEL_3) ||          \
      ((CHANNEL) == TMR_CHANNEL_4)))           \
    ||                                         \
    (((INSTANCE) == TMR9) &&                   \
     (((CHANNEL) == TMR_CHANNEL_1) ||          \
      ((CHANNEL) == TMR_CHANNEL_2)))           \
    ||                                         \
    (((INSTANCE) == TMR10) &&                  \
     (((CHANNEL) == TMR_CHANNEL_1)))           \
    ||                                         \
    (((INSTANCE) == TMR11) &&                  \
     (((CHANNEL) == TMR_CHANNEL_1)))           \
    ||                                         \
    (((INSTANCE) == TMR12) &&                  \
     (((CHANNEL) == TMR_CHANNEL_1) ||          \
      ((CHANNEL) == TMR_CHANNEL_2)))           \
    ||                                         \
    (((INSTANCE) == TMR13) &&                  \
     (((CHANNEL) == TMR_CHANNEL_1)))           \
    ||                                         \
    (((INSTANCE) == TMR14) &&                  \
     (((CHANNEL) == TMR_CHANNEL_1))))

/************ TMR Instances : complementary output(s) available ***************/
#define IS_TMR_CCXN_INSTANCE(INSTANCE, CHANNEL) \
   ((((INSTANCE) == TMR1) &&                    \
     (((CHANNEL) == TMR_CHANNEL_1) ||           \
      ((CHANNEL) == TMR_CHANNEL_2) ||           \
      ((CHANNEL) == TMR_CHANNEL_3)))            \
    ||                                          \
    (((INSTANCE) == TMR8) &&                    \
     (((CHANNEL) == TMR_CHANNEL_1) ||           \
      ((CHANNEL) == TMR_CHANNEL_2) ||           \
      ((CHANNEL) == TMR_CHANNEL_3))))

/****************** TMR Instances : supporting counting mode selection ********/
#define IS_TMR_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)  (((INSTANCE) == TMR1) || \
                                                        ((INSTANCE) == TMR2) || \
                                                        ((INSTANCE) == TMR3) || \
                                                        ((INSTANCE) == TMR4) || \
                                                        ((INSTANCE) == TMR5) || \
                                                        ((INSTANCE) == TMR8))

/****************** TMR Instances : supporting clock division *****************/
#define IS_TMR_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TMR1)  || \
                                                  ((INSTANCE) == TMR2) || \
                                                  ((INSTANCE) == TMR3) || \
                                                  ((INSTANCE) == TMR4) || \
                                                  ((INSTANCE) == TMR5) || \
                                                  ((INSTANCE) == TMR8) || \
                                                  ((INSTANCE) == TMR9) || \
                                                  ((INSTANCE) == TMR10)|| \
                                                  ((INSTANCE) == TMR11)|| \
                                                  ((INSTANCE) == TMR12)|| \
                                                  ((INSTANCE) == TMR13)|| \
                                                  ((INSTANCE) == TMR14))

/****************** TMR Instances : supporting commutation event generation ***/
#define IS_TMR_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TMR1)|| \
                                                     ((INSTANCE) == TMR8))


/****************** TMR Instances : supporting OCxREF clear *******************/
#define IS_TMR_OCXREF_CLEAR_INSTANCE(INSTANCE)        (((INSTANCE) == TMR1) || \
                                                       ((INSTANCE) == TMR2) || \
                                                       ((INSTANCE) == TMR3) || \
                                                       ((INSTANCE) == TMR4) || \
                                                       ((INSTANCE) == TMR5) || \
                                                       ((INSTANCE) == TMR8))

/****** TMR Instances : supporting external clock mode 1 for ETRF input *******/
#define IS_TMR_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \
                                                        ((INSTANCE) == TMR2) || \
                                                        ((INSTANCE) == TMR3) || \
                                                        ((INSTANCE) == TMR4) || \
                                                        ((INSTANCE) == TMR5) || \
                                                        ((INSTANCE) == TMR8) || \
                                                        ((INSTANCE) == TMR9) || \
                                                        ((INSTANCE) == TMR12))

/****** TMR Instances : supporting external clock mode 2 for ETRF input *******/
#define IS_TMR_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TMR1) || \
                                                        ((INSTANCE) == TMR2) || \
                                                        ((INSTANCE) == TMR3) || \
                                                        ((INSTANCE) == TMR4) || \
                                                        ((INSTANCE) == TMR5) || \
                                                        ((INSTANCE) == TMR8))

/****** TMR Instances : supporting external clock mode 1 for TIX inputs ******/
#define IS_TMR_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)      (((INSTANCE) == TMR1) || \
                                                        ((INSTANCE) == TMR2) || \
                                                        ((INSTANCE) == TMR3) || \
                                                        ((INSTANCE) == TMR4) || \
                                                        ((INSTANCE) == TMR5) || \
                                                        ((INSTANCE) == TMR8) || \
                                                        ((INSTANCE) == TMR9) || \
                                                        ((INSTANCE) == TMR12))

/********** TMR Instances : supporting internal trigger inputs(ITRX) *********/
#define IS_TMR_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)     (((INSTANCE) == TMR1) || \
                                                        ((INSTANCE) == TMR2) || \
                                                        ((INSTANCE) == TMR3) || \
                                                        ((INSTANCE) == TMR4) || \
                                                        ((INSTANCE) == TMR5) || \
                                                        ((INSTANCE) == TMR8) || \
                                                        ((INSTANCE) == TMR9) || \
                                                        ((INSTANCE) == TMR12))

/****************** TMR Instances : supporting repetition counter *************/
#define IS_TMR_REPETITION_COUNTER_INSTANCE(INSTANCE)  (((INSTANCE) == TMR1) || \
                                                       ((INSTANCE) == TMR8))

/****************** TMR Instances : supporting encoder interface **************/
#define IS_TMR_ENCODER_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TMR1) || \
                                                      ((INSTANCE) == TMR2) || \
                                                      ((INSTANCE) == TMR3) || \
                                                      ((INSTANCE) == TMR4) || \
                                                      ((INSTANCE) == TMR5) || \
                                                      ((INSTANCE) == TMR8) || \
                                                      ((INSTANCE) == TMR9) || \
                                                      ((INSTANCE) == TMR12))
/****************** TMR Instances : supporting Hall sensor interface **********/
#define IS_TMR_HALL_SENSOR_INTERFACE_INSTANCE(INSTANCE)  (((INSTANCE) == TMR1) || \
                                                          ((INSTANCE) == TMR2) || \
                                                          ((INSTANCE) == TMR3) || \
                                                          ((INSTANCE) == TMR4) || \
                                                          ((INSTANCE) == TMR5) || \
                                                          ((INSTANCE) == TMR8))
/****************** TMR Instances : supporting the break function *************/
#define IS_TMR_BREAK_INSTANCE(INSTANCE)  (((INSTANCE) == TMR1) || \
                                          ((INSTANCE) == TMR8))

/******************** USART Instances : Synchronous mode **********************/
#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                     ((INSTANCE) == USART2) || \
                                     ((INSTANCE) == USART3) || \
                                     ((INSTANCE) == USART6))

/******************** UART Instances : Half-Duplex mode **********************/
#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                               ((INSTANCE) == USART2) || \
                                               ((INSTANCE) == USART3) || \
                                               ((INSTANCE) == UART4)  || \
                                               ((INSTANCE) == UART5)  || \
                                               ((INSTANCE) == USART6))

/* Legacy defines */
#define IS_UART_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE

/****************** UART Instances : Hardware Flow control ********************/
#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                           ((INSTANCE) == USART2) || \
                                           ((INSTANCE) == USART3) || \
                                           ((INSTANCE) == USART6))
/******************** UART Instances : LIN mode **********************/
#define IS_UART_LIN_INSTANCE          IS_UART_HALFDUPLEX_INSTANCE

/********************* UART Instances : Smart card mode ***********************/
#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                         ((INSTANCE) == USART2) || \
                                         ((INSTANCE) == USART3) || \
                                         ((INSTANCE) == USART6))

/*********************** UART Instances : IRDA mode ***************************/
#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
                                    ((INSTANCE) == USART2) || \
                                    ((INSTANCE) == USART3) || \
                                    ((INSTANCE) == UART4)  || \
                                    ((INSTANCE) == UART5)  || \
                                    ((INSTANCE) == USART6))


/*********************** PCD Instances ****************************************/
#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
                                       ((INSTANCE) == USB_OTG_HS))

/*********************** HCD Instances ****************************************/
#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
                                       ((INSTANCE) == USB_OTG_HS))

/****************************** SDIO Instances ********************************/
#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)

/****************************** IWDT Instances ********************************/
#define IS_IWDT_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDT)

/****************************** WWDT Instances ********************************/
#define IS_WWDT_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDT)

/****************************** USB Exported Constants ************************/
#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8U
#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4U    /* Including EP0 */
#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4U    /* Including EP0 */
#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280U /* in Bytes */

/*
 * @brief Specific devices reset values definitions
 */
#define RCM_PLL1CFG_RST_VALUE              0x24003010U
#define RCM_PLL2CFG_RST_VALUE           0x20003000U

#define RCM_MAX_FREQUENCY           168000000U         /*!< Max frequency of family in Hz*/
#define RCM_MAX_FREQUENCY_SCALE1    RCM_MAX_FREQUENCY  /*!< Maximum frequency for system clock at power scale1, in Hz */
#define RCM_MAX_FREQUENCY_SCALE2    144000000U         /*!< Maximum frequency for system clock at power scale2, in Hz */
#define RCM_PLLVCO_OUTPUT_MIN       100000000U       /*!< Frequency min for PLLVCO output, in Hz */
#define RCM_PLLVCO_INPUT_MIN           950000U       /*!< Frequency min for PLLVCO input, in Hz  */
#define RCM_PLLVCO_INPUT_MAX          2100000U       /*!< Frequency max for PLLVCO input, in Hz  */
#define RCM_PLLVCO_OUTPUT_MAX       432000000U       /*!< Frequency max for PLLVCO output, in Hz */

#define RCM_PLL1A_MIN_VALUE                 50U
#define RCM_PLL1A_MAX_VALUE                432U

#define FLASH_SCALE1_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 1  */
#define FLASH_SCALE1_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 1  */
#define FLASH_SCALE1_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 1  */
#define FLASH_SCALE1_LATENCY4_FREQ   120000000U     /*!< HCLK frequency to set FLASH latency 4 in power scale 1  */
#define FLASH_SCALE1_LATENCY5_FREQ   150000000U     /*!< HCLK frequency to set FLASH latency 5 in power scale 1  */

#define FLASH_SCALE2_LATENCY1_FREQ   30000000U      /*!< HCLK frequency to set FLASH latency 1 in power scale 2  */
#define FLASH_SCALE2_LATENCY2_FREQ   60000000U      /*!< HCLK frequency to set FLASH latency 2 in power scale 2  */
#define FLASH_SCALE2_LATENCY3_FREQ   90000000U      /*!< HCLK frequency to set FLASH latency 3 in power scale 2  */
#define FLASH_SCALE2_LATENCY4_FREQ   12000000U      /*!< HCLK frequency to set FLASH latency 4 in power scale 2  */

#define USB_OTG_HS_HOST_MAX_CHANNEL_NBR                12U
#define USB_OTG_HS_MAX_IN_ENDPOINTS                    6U    /* Including EP0 */
#define USB_OTG_HS_MAX_OUT_ENDPOINTS                   6U    /* Including EP0 */
#define USB_OTG_HS_TOTAL_FIFO_SIZE                     4096U /* in Bytes */
/******************************************************************************/
/*  For a painless codes migration between the APM32F4xx device product       */
/*  lines, the aliases defined below are put in place to overcome the         */
/*  differences in the interrupt handlers and IRQn definitions.               */
/*  No need to update developed interrupt code when moving across             */
/*  product lines within the same APM32F4 Family                              */
/******************************************************************************/
/* Aliases for __IRQn */
#define SMC_IRQn              EMMC_IRQn

/* Aliases for __IRQHandler */
#define SMC_IRQHandler        EMMC_IRQHandler

/**
  * @}
  */

/**
  * @}
  */

/**
  * @}
  */

#ifdef __cplusplus
}
#endif /* __cplusplus */

#endif /* __APM32F407xx_H */
