Release Notes for STM32F4xx Standard Peripherals Library Drivers

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# Release Notes for STM32F4xx Standard Peripherals Drivers Copyright 2015 STMicroelectronics
## Contents STM32F4xx Standard Peripherals Library Drivers update History License ## STM32F4xx Standard Peripherals Library Drivers update History ### V1.6.1 / 21-October-2015 Main Changes stm32f4xx_rcc.c/h update Update PLLN, PLLI2SN and PLLSAIN min value to reach 50 instead of 192. stm32f4xx_dsi.c/h update Update TCCR register assigned value in HAL_DSI_ConfigHostTimeouts() function Update WPCR register assigned value in HAL_DSI_Init(), HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetLowPowerRXFilter() / HAL_DSI_SetSDD(), HAL_DSI_SetLanePinsConfiguration(), HAL_DSI_SetPHYTimings(), HAL_DSI_ForceTXStopMode(), HAL_DSI_ForceRXLowPower(), HAL_DSI_ForceDataLanesInRX(), HAL_DSI_SetPullDown() and HAL_DSI_SetContentionDetectionOff() functions Update DSI_HS_PM_ENABLE define value Implement workaround for the hardware limitation: “The time to activate the clock between HS transmissions is not calculated correctly” Rename DSI_ConfigLowPowerCommand() by DSI_ConfigCommand(): this API can be used in normal and low power modes stm32f4xx_fmc.c/h update Remove the Clock Division and Data Latency configuration for NOR/SRAM extended mode Add the clear sequence before writing on the BWTR register for NOR/SRAM extended mode stm32f4xx_fsmc.c/h update Remove the Clock Division and Data Latency configuration for NOR/SRAM extended mode ### V1.6.0 / 10-July-2015 Main Changes Add support of STM32F410xx, STM32F469xx and STM32F479xx devices Add new driver for LPTIM, DSI peripherals Update the system drivers (RCC, PWR, FLASH, GPIO and SYSCFG) to support the new STM32F410xx, STM32F469xx and STM32F479xx features ### V1.5.1 / 22-May-2015 Main Changes Update QSPI, FMPI2C, CEC and SPDIFRX drivers to compile only when the STM32F446xx device is selected stm32f4xx_fmpi2c.c: Correct the name of the header file to be included, use lowercase instead of uppercase ### V1.5.0 / 06-March-2015 Main Changes Add support of STM32F446xx devices Add new driver for QSPI, FMPI2C, CEC and SPDIFRX peripherals Update the system drivers (RCC, PWR, FLASH, GPIO and SYSCFG) to support the new STM32F446xx features ### V1.4.0 / 04-August-2014 Main Changes Add support of STM32F411xExx devices stm32f4xx_rcc.c/.h: Update RCC_PLLI2SConfig() function to configure the new I2S parameter: PLLI2SM Add new defines for LSE mode: RCC_LSE_LOWPOWER_MODE and RCC_LSE_HIGHDRIVE_MODE Add new function to configure LSE mode: RCC_LSEModeConfig() stm32f4xx_flash.c/.h: Update IS_FLASH_ADDRESS() macro stm32f4xx_gpio.c/.h: Add new defines for the new alternate functions stm32f4xx_flash_ramfunc.c/.h: Add new driver for ram functions stm32f4xx_pwr.c/.h: Fix PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF): this flag need to be cleared at application level before to call this function. Add new function to ENABLE/DISABLE the main regulator low voltage: PWR_MainRegulatorLowVoltageCmd() Add new function to ENABLE/DISABLE the low regulator low voltage: PWR_LowRegulatorLowVoltageCmd() Limitation Fix: stm32f4xx_spi.c/h Update I2S_Init() to support HSI oscillator as PLL source. stm32f4xx_gpio.c/h Update assert macro IS_GPIO_AF() macro to work as expected stm32f4xx_fmc.c/h and stm32f4xx_fsmc.c/h Update the FSMC_NORSRAMStructInit() function to point the FSMC_DefaultTimingStruct and FSMC_DefaultTimingStruct parameters on a default const structure. ### V1.3.0 / 08-November-2013 Main Changes Add support of STM32F401xExx devices stm32f4xx_gpio.c/h Update GPIOSpeed_TypeDef structure’s fields name to be in line with GPIO out speed definition in the product Reference Manual Add a legacy defines to keep compatibility with previous version stm32f4xx_flash.c/h File’s header comments: update description of the maximum AHB frequency vs. voltage scaling configuration ### V1.2.1 / 19-September-2013 Main Changes stm32f4xx_pwr.c/.h Add new function to configure the Under-Drive STOP Mode : PWR_EnterUnderDriveSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry) only used in case of STM32F427/437/429/439xx devices. ### V1.2.0 / 11-September-2013 Main Changes Add support of STM32F429/439xx and STM32F401xCxx devices Update definition of STM32F427/437xx devices : extension of the features to include system clock up to 180MHz, dual bank Flash, reduced STOP Mode current, SAI, PCROP, SDRAM and DMA2D Add drivers for new peripherals of STM32F4xx STM32F427/437xx and STM32F429/439xx devices: stm32f4xx_dma2d.h/.c stm32f4xx_fmc.h/.c stm32f4xx_ltdc.h/.c stm32f4xx_sai.h/.c stm32f4xx_adc.c/.h Update the Temperature sensor channel for STM32F427/STM32F437x/STM32F429x/STM32F439x devices from Channel 16 to Channel 18 Add a note in ADC_VBATCmd() header function to inform that the Voltage measured is VBAT/2 in case of STM3240xxx/41xxx and VBAT/4 in case of STM32F42xxx/43xxx. In ADC_GetSoftwareStartConvStatus() function, replace "ADC_CR2_JSWSTART" by "ADC_CR2_SWSTART" stm32f4xx_flash.c/.h Update the header file description, add the table of number of wait states according to system frequency selected for all STM32F4xx family devices Update FLASH_EraseAllSectors() function to support the erase for all sectors within Bank1 and Bank2 in case of STM32F42/43xxx devices Add new FLASH Latency values: FLASH_Latency_8, FLASH_Latency_9, FLASH_Latency_10, FLASH_Latency_11, FLASH_Latency_12, FLASH_Latency_13, FLASH_Latency_14, FLASH_Latency_15. Add new flag error in FLASH_Status structure: " FLASH_ERROR_RD" Add new functions: FLASH_EraseAllBank1Sectors(): mass erase in bank 1 (Half mass erase) FLASH_EraseAllBank2Sectors(): mass erase in Bank 2 (Half mass erase) FLASH_OB_BootConfig(): configure Dual bank boot mode FLASH_OB_PCROPSelectionConfig(): select PCROP feature FLASH_OB_WRP1Config(): configure write protection from Sector 12 to sector 23 FLASH_OB_PCROPConfig(): configure PC read/write protection from Sector 0 to sector 11 FLASH_OB_PCROP1Config(): configure PC read/write protection from Sector12 to sector23 FLASH_OB_GetWRP1(): Read the write protected sectors from 12 to 23 FLASH_OB_GetPCROP(): Read the PC read/write protected sectors from 0 to 11 FLASH_OB_GetPCROP1(): Read the PC read/write protected sectors from 12 to 23 stm32f4xx_gpio.c/.h Update GPIO_DeInit() function : Add GPIOJ, GPIOK clock reset/enable Add a new alternate function for I2C2 and I2C3 : #define GPIO_AF9_I2C2 ((uint8_t)0x09) /* I2C2 Alternate Function mapping */ #define GPIO_AF9_I2C3 ((uint8_t)0x09) /* I2C3 Alternate Function mapping */ Update all functions header comments. stm32f4xx_rcc.c/.h Add new definitions for new peripherals: SAI1, LTDC, FMC Add a new parameter in RCC_PLLI2SConfig() function : PLLI2SQ to specifies the division factor for SAI1 clock Add new functions: RCC_PLLSAIConfig(), RCC_PLLSAICmd(): PLL SAI Clock configuration Add new function RCC_SAICLKConfig(): SAI clock division factors configuration RCC_LCDCLKConfig(): LCD clock division factors configuration stm32l1xx_syscfg.c/.h Add new SYSCFG port sources configurations : EXTI_PortSourceGPIOJ, EXTI_PortSourceGPIOK Add new function SYSCFG_MemorySwappingBank(): swap between bank 1 and Bank 2 stm32f4xx_pwr.c/.h Add more details and update comments in functions and groups description Add the following functions to configure the Over-drive and Under-drive Modes : PWR_OverDriveCmd() PWR_OverDriveSWCmd() PWR_UnderDriveCmd() ### V1.1.0 / 11-January-2013 Main Changes Official release for STM32F427x/437x devices. stm32f4xx_cryp.c/.h Update CRYP_Init() function : add the support for new algorithms (GCM/CCM). Add new function : CRYP_PhaseConfig() used for new AES-GCM and AES-CCM algorithms. CRYP_InitTypeDef structure : update all structure fields from uint16_t to uint32_t and update all driver functions parameters and the correspondant define to be declared with uint32_t type. Replace the "CRYP_ContextSave->CR_bits9to2" by "CRYP_ContextSave->CurrentConfig". stm32f4xx_flash.c/.h Update FLASH sectors numbers "FLASH_Sector_x" with x = 0..23. Update FLASH_EraseAllSectors() function to support mass erase for STM32F427x/437x devices. stm32f4xx_gpio.c/.h Add Alternate functions for new peripherals: SPI4, SPI5, SPI6, UART7, UART8. Update all functions header comment. stm32f4xx_hash.c/.h Update HASH_GetDigest() function : add the HASH_DIGEST structure. Add new function HASH_AutoStartDigest(). Update HASH_MsgDigest structure: to support SHA-224 and SHA-256 modes. Update HASH_Context structure. Update some define using bit definitions already declared in stm32f4xx.h. stm32f4xx_i2c.c/.h Add new functions: I2C_AnalogFilterCmd(): enable/disable the analog I2C filters. I2C_DigitalFilterConfig(): configure the digital I2C filters. stm32f4xx_pwr.c/.h Add new argument "PWR_Regulator_Voltage_Scale3" to PWR_MainRegulatorModeConfig() function to be in line with Reference Manual description. stm32f4xx_rcc.c/.h Add new definitions for new peripherals: SPI4, SPI5, SPI6, SAI1, UART7, UART8. Add a new parameter in RCC_PLLI2SConfig() function : PLLI2SQ to specifies the division factor for SAI1 clock. Add RCC_TIMCLKPresConfig() function : TIMER Prescaler selection. stm32l1xx_spi.c/.h Update to support SPI4, SPI5, SPI6. Update all functions header comment. stm32l1xx_usart.c/.h Update to support UART7 and UART8. Update all functions header comment. ### V1.0.2 / 05-March-2012 Main Changes All source files: license disclaimer text update and add link to the License file on ST Internet. stm32f4xx_dcmi.c DCMI_GetFlagStatus() function: fix test condition on RISR register, use if (dcmireg == 0x00) instead of if (dcmireg == 0x01) stm32f4xx_pwr.c PWR_PVDLevelConfig() function: remove value of the voltage threshold corresponding to each PVD detection level, user should refer to the electrical characteristics of the STM32 device datasheet to have the correct value ### V1.0.1 / 28-December-2011 Main Changes All source files: update disclaimer to add reference to the new license agreement stm32f4xx_rtc.c: In “RTC_FLAGS_MASK” define: add RTC_FLAG_RECALPF and RTC_FLAG_SHPF RTC_DeInit() function: add reset of the following registers: SHIFTR, CALR, ALRMASSR and ALRMBSSR RTC_SetTime() and RTC_SetDate() functions: add test condition on BYPSHAD flag before to test RSF flag (when Bypass mode is enabled, the RSF bit is never set). ### V1.0.0 / 30-September-2011 Main Changes First official release for STM32F40x/41x devices stm32f4xx_rtc.c: remove useless code from RTC_GetDate() function stm32f4xx_rcc.c, stm32f4xx_spi.c, stm32f4xx_wwdg.c and stm32f4xx_syscfg.c: driver's comments update ### V1.0.0RC2 / 26-September-2011 Main Changes Official version (V1.0.0) Release Candidate1 for STM32F40x/STM32F41x devices stm32f4xx_usart.h/.c Update procedure to check on overrun error interrupt pending bit, defines for the following flag are added: USART_IT_ORE_RX: this flag is set if overrun error interrupt occurs and RXNEIE bit is set USART_IT_ORE_ER: this flag is set if overrun error interrupt occurs and EIE bit is set stm32f4xx_tim.c TIM_UpdateRequestConfig(): correct function header's comment TIM_ICInit(): add assert macros to test if the passed TIM parameter has channel 2, 3 or 4 stm32f4xx_pwr.h/.c Rename PWR_FLAG_REGRDY constant to PWR_CSR_REGRDY Rename PWR_FLAG_VOSRDY constant to PWR_CSR_VOSRDY Rename PWR_HighPerformanceModeCmd(FunctionalState NewState) function to PWR_MainRegulatorModeConfig(uint32_t PWR_Regulator_Voltage) stm32f4xx_rcc.h/.c RCC_AHB1PeriphClockCmd(): add new constant RCC_AHB1Periph_CCMDATARAMEN as value for RCC_AHB1Periph parameter stm32f4xx_spi.h IS_I2S_EXT_PERIPH(): add check on I2S3ext peripheral ### V1.0.0RC1 / 25-August-2011 Main Changes Official version (V1.0.0) Release Candidate1 for STM32F4xx devices ## License Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this package except in compliance with the License. You may obtain a copy of the License at: http://www.st.com/software_license_agreement_liberty_v2 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. For complete documentation on STM32 Microcontrollers visit www.st.com/STM32