<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<!-- Awlsim project file generated by awlsim-0.55 -->
<awlsim_project date_create="2012-08-13 00:00:00.000000"
                date_modify="2017-07-29 20:28:50.172151"
                format_version="1">
	<!-- CPU core configuration -->
	<cpu>
		<!-- CPU core feature specification -->
		<specs nr_accus="2"
		       nr_counters="256"
		       nr_flags="2048"
		       nr_inputs="128"
		       nr_localbytes="1024"
		       nr_outputs="128"
		       nr_timers="256" />

		<!-- CPU core configuration -->
		<config clock_memory_byte="-1"
		        ext_insns_enable="1"
		        mnemonics="2"
		        ob_startinfo_enable="0" />
	</cpu>

	<!-- AWL/STL language configuration -->
	<language_awl>
		<!-- AWL/STL source code -->
		<source name="Main"
		        type="0"><![CDATA[
ORGANIZATION_BLOCK OB 1
BEGIN
	CALL "FC_TEST_assign"
	CALL "FC_TEST_and_and_or"
	CALL "FC_TEST_branch"
	CALL "FC_TEST_not_1"
	CALL "FC_TEST_not_2"
	
	CALL SFC 46 // STOP CPU
END_ORGANIZATION_BLOCK

]]></source>

		<!-- AWL/STL source code -->
		<source name="TEST assign"
		        type="0"><![CDATA[
FUNCTION "FC_TEST_assign" : VOID
BEGIN
	// Test: "FC_assign"
	// Equations:
	// OUT0 = IN0 * IN1
	// OUT1 = IN0 * IN1
	// OUT2 = IN0 * IN1
	
	CALL "FC_assign" (
		IN0 := FALSE,
		IN1 := FALSE,
		OUT0 := M 0.0,
		OUT1 := M 0.1,
		OUT2 := M 0.2,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	
	
	CALL "FC_assign" (
		IN0 := TRUE,
		IN1 := FALSE,
		OUT0 := M 0.0,
		OUT1 := M 0.1,
		OUT2 := M 0.2,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	
	
	CALL "FC_assign" (
		IN0 := FALSE,
		IN1 := TRUE,
		OUT0 := M 0.0,
		OUT1 := M 0.1,
		OUT2 := M 0.2,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	
	
	CALL "FC_assign" (
		IN0 := TRUE,
		IN1 := TRUE,
		OUT0 := M 0.0,
		OUT1 := M 0.1,
		OUT2 := M 0.2,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, TRUE
	
	
	BE
END_FUNCTION

]]></source>

		<!-- AWL/STL source code -->
		<source name="TEST and_and_or"
		        type="0"><![CDATA[
FUNCTION "FC_TEST_and_and_or" : VOID
BEGIN
	// Test: "FC_and_and_or"
	// Equations:
	// RET_VAL = (INP0 * INP1) + (INP2 * INP3)
	
	CALL	"FC_and_and_or" (
		INP0	:= FALSE,
		INP1	:= FALSE,
		INP2	:= FALSE,
		INP3	:= FALSE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= TRUE,
		INP1	:= FALSE,
		INP2	:= FALSE,
		INP3	:= FALSE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= FALSE,
		INP1	:= TRUE,
		INP2	:= FALSE,
		INP3	:= FALSE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= TRUE,
		INP1	:= TRUE,
		INP2	:= FALSE,
		INP3	:= FALSE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	TRUE
	
	CALL	"FC_and_and_or" (
		INP0	:= FALSE,
		INP1	:= FALSE,
		INP2	:= TRUE,
		INP3	:= FALSE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= TRUE,
		INP1	:= FALSE,
		INP2	:= TRUE,
		INP3	:= FALSE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= FALSE,
		INP1	:= TRUE,
		INP2	:= TRUE,
		INP3	:= FALSE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= TRUE,
		INP1	:= TRUE,
		INP2	:= TRUE,
		INP3	:= FALSE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	TRUE
	
	CALL	"FC_and_and_or" (
		INP0	:= FALSE,
		INP1	:= FALSE,
		INP2	:= FALSE,
		INP3	:= TRUE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= TRUE,
		INP1	:= FALSE,
		INP2	:= FALSE,
		INP3	:= TRUE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= FALSE,
		INP1	:= TRUE,
		INP2	:= FALSE,
		INP3	:= TRUE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	FALSE
	
	CALL	"FC_and_and_or" (
		INP0	:= TRUE,
		INP1	:= TRUE,
		INP2	:= FALSE,
		INP3	:= TRUE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	TRUE
	
	CALL	"FC_and_and_or" (
		INP0	:= FALSE,
		INP1	:= FALSE,
		INP2	:= TRUE,
		INP3	:= TRUE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	TRUE
	
	CALL	"FC_and_and_or" (
		INP0	:= TRUE,
		INP1	:= FALSE,
		INP2	:= TRUE,
		INP3	:= TRUE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	TRUE
	
	CALL	"FC_and_and_or" (
		INP0	:= FALSE,
		INP1	:= TRUE,
		INP2	:= TRUE,
		INP3	:= TRUE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	TRUE
	
	CALL	"FC_and_and_or" (
		INP0	:= TRUE,
		INP1	:= TRUE,
		INP2	:= TRUE,
		INP3	:= TRUE,
		RET_VAL	:= M 0.0,
	)
	__ASSERT==	M 0.0,	TRUE
	
	BE
END_FUNCTION

]]></source>

		<!-- AWL/STL source code -->
		<source name="TEST branch"
		        type="0"><![CDATA[
FUNCTION "FC_TEST_branch" : VOID
BEGIN
	// Test: "FC_branch"
	// Equations:
	// OUT10 = (IN00 :+: IN01) * IN10
	// OUT20 = (IN00 :+: IN01) * IN20
	// OUT40 = IN30 * IN40
	// OUT50 = IN30 * IN50
	// OUT60 = IN60 :+: IN61
	// OUT61 = IN60 :+: IN61
	// OUT70 = (IN60 :+: IN61) :+: IN70
	// OUT80 = IN80 :+: IN81
	// OUT81 = IN80 :+: IN81
	// OUT90 = (IN80 :+: IN81) :+: IN90
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := TRUE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := TRUE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := TRUE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := TRUE,
		
		IN30 := TRUE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := TRUE,
		
		IN30 := FALSE,
		IN40 := TRUE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := TRUE,
		
		IN30 := TRUE,
		IN40 := TRUE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, TRUE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := TRUE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := TRUE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := TRUE,
		
		IN30 := TRUE,
		IN40 := FALSE,
		IN50 := TRUE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, TRUE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := TRUE,
		
		IN30 := FALSE,
		IN40 := TRUE,
		IN50 := TRUE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := TRUE,
		IN01 := FALSE,
		IN10 := TRUE,
		IN20 := TRUE,
		
		IN30 := TRUE,
		IN40 := TRUE,
		IN50 := TRUE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, TRUE
	__ASSERT==	M 0.1, TRUE
	__ASSERT==	M 0.2, TRUE
	__ASSERT==	M 0.3, TRUE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := TRUE,
		IN61 := FALSE,
		IN70 := FALSE,
		
		IN80 := TRUE,
		IN81 := FALSE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, TRUE
	__ASSERT==	M 0.5, TRUE
	__ASSERT==	M 0.6, TRUE
	__ASSERT==	M 0.7, TRUE
	__ASSERT==	M 1.0, TRUE
	__ASSERT==	M 1.1, TRUE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := TRUE,
		IN70 := FALSE,
		
		IN80 := FALSE,
		IN81 := TRUE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, TRUE
	__ASSERT==	M 0.5, TRUE
	__ASSERT==	M 0.6, TRUE
	__ASSERT==	M 0.7, TRUE
	__ASSERT==	M 1.0, TRUE
	__ASSERT==	M 1.1, TRUE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := TRUE,
		IN61 := TRUE,
		IN70 := FALSE,
		
		IN80 := TRUE,
		IN81 := TRUE,
		IN90 := FALSE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := FALSE,
		IN70 := TRUE,
		
		IN80 := FALSE,
		IN81 := FALSE,
		IN90 := TRUE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, TRUE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, TRUE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := TRUE,
		IN61 := FALSE,
		IN70 := TRUE,
		
		IN80 := TRUE,
		IN81 := FALSE,
		IN90 := TRUE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, TRUE
	__ASSERT==	M 0.5, TRUE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, TRUE
	__ASSERT==	M 1.0, TRUE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := FALSE,
		IN61 := TRUE,
		IN70 := TRUE,
		
		IN80 := FALSE,
		IN81 := TRUE,
		IN90 := TRUE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, TRUE
	__ASSERT==	M 0.5, TRUE
	__ASSERT==	M 0.6, FALSE
	__ASSERT==	M 0.7, TRUE
	__ASSERT==	M 1.0, TRUE
	__ASSERT==	M 1.1, FALSE
	
	
	CALL "FC_branch" (
		IN00 := FALSE,
		IN01 := FALSE,
		IN10 := FALSE,
		IN20 := FALSE,
		
		IN30 := FALSE,
		IN40 := FALSE,
		IN50 := FALSE,
		
		IN60 := TRUE,
		IN61 := TRUE,
		IN70 := TRUE,
		
		IN80 := TRUE,
		IN81 := TRUE,
		IN90 := TRUE,
		
		OUT10 := M 0.0,
		OUT20 := M 0.1,
		OUT40 := M 0.2,
		OUT50 := M 0.3,
		OUT60 := M 0.4,
		OUT61 := M 0.5,
		OUT70 := M 0.6,
		OUT80 := M 0.7,
		OUT81 := M 1.0,
		OUT90 := M 1.1,
	)
	__ASSERT==	M 0.0, FALSE
	__ASSERT==	M 0.1, FALSE
	__ASSERT==	M 0.2, FALSE
	__ASSERT==	M 0.3, FALSE
	__ASSERT==	M 0.4, FALSE
	__ASSERT==	M 0.5, FALSE
	__ASSERT==	M 0.6, TRUE
	__ASSERT==	M 0.7, FALSE
	__ASSERT==	M 1.0, FALSE
	__ASSERT==	M 1.1, TRUE
	
	
	BE
END_FUNCTION

]]></source>

		<!-- AWL/STL source code -->
		<source name="TEST not 1"
		        type="0"><![CDATA[
FUNCTION "FC_TEST_not_1" : VOID
BEGIN
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= FALSE,  // BOOL
		IN01		:= FALSE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN20		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= TRUE,  // BOOL
		IN01		:= FALSE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN20		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= FALSE,  // BOOL
		IN01		:= TRUE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN20		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	TRUE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= TRUE,  // BOOL
		IN01		:= TRUE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN20		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= FALSE,  // BOOL
		IN01		:= FALSE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN20		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= TRUE,  // BOOL
		IN01		:= FALSE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN20		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= FALSE,  // BOOL
		IN01		:= TRUE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN20		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= TRUE,  // BOOL
		IN01		:= TRUE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN20		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= FALSE,  // BOOL
		IN01		:= FALSE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN20		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	FALSE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= TRUE,  // BOOL
		IN01		:= FALSE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN20		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	FALSE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= FALSE,  // BOOL
		IN01		:= TRUE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN20		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	TRUE
	__ASSERT==	M 0.1,	TRUE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= TRUE,  // BOOL
		IN01		:= TRUE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN20		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	FALSE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= FALSE,  // BOOL
		IN01		:= FALSE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN20		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	FALSE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= TRUE,  // BOOL
		IN01		:= FALSE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN20		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	FALSE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= FALSE,  // BOOL
		IN01		:= TRUE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN20		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	FALSE
	
	
	L	0
	T	MD 0
	CALL "FC_not_1" (
		// VAR_INPUT
		IN00		:= TRUE,  // BOOL
		IN01		:= TRUE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN20		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT10		:= M 0.0,  // BOOL
		OUT20		:= M 0.1,  // BOOL
	)
	__ASSERT==	M 0.0,	FALSE
	__ASSERT==	M 0.1,	FALSE
	
	
	BE
END_FUNCTION
]]></source>

		<!-- AWL/STL source code -->
		<source name="TEST not 2"
		        type="0"><![CDATA[
FUNCTION "FC_TEST_not_2" : VOID
BEGIN
	L	0
	T	MD 0
	T	MD 10
	CALL "FC_not_2" (
		// VAR_INPUT
		IN01		:= 4242,  // INT
		IN02		:= FALSE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN11		:= 2424,  // INT
		IN12		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT00		:= MW 0,  // INT
		OUT01		:= M 2.0,  // BOOL
		OUT10		:= MW 10,  // INT
		OUT11		:= M 12.0,  // BOOL
	)
	__ASSERT==	MW 0,	4242
	__ASSERT==	M 2.0,	FALSE
	__ASSERT==	MW 10,	0
	__ASSERT==	M 12.0,	TRUE
	
	
	L	0
	T	MD 0
	T	MD 10
	CALL "FC_not_2" (
		// VAR_INPUT
		IN01		:= 4242,  // INT
		IN02		:= TRUE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN11		:= 2424,  // INT
		IN12		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT00		:= MW 0,  // INT
		OUT01		:= M 2.0,  // BOOL
		OUT10		:= MW 10,  // INT
		OUT11		:= M 12.0,  // BOOL
	)
	__ASSERT==	MW 0,	4242
	__ASSERT==	M 2.0,	TRUE
	__ASSERT==	MW 10,	0
	__ASSERT==	M 12.0,	TRUE
	
	
	L	0
	T	MD 0
	T	MD 10
	CALL "FC_not_2" (
		// VAR_INPUT
		IN01		:= 4242,  // INT
		IN02		:= FALSE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN11		:= 2424,  // INT
		IN12		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT00		:= MW 0,  // INT
		OUT01		:= M 2.0,  // BOOL
		OUT10		:= MW 10,  // INT
		OUT11		:= M 12.0,  // BOOL
	)
	__ASSERT==	MW 0,	4242
	__ASSERT==	M 2.0,	FALSE
	__ASSERT==	MW 10,	2424
	__ASSERT==	M 12.0,	FALSE
	
	
	L	0
	T	MD 0
	T	MD 10
	CALL "FC_not_2" (
		// VAR_INPUT
		IN01		:= 4242,  // INT
		IN02		:= TRUE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN11		:= 2424,  // INT
		IN12		:= FALSE,  // BOOL
		// VAR_OUTPUT
		OUT00		:= MW 0,  // INT
		OUT01		:= M 2.0,  // BOOL
		OUT10		:= MW 10,  // INT
		OUT11		:= M 12.0,  // BOOL
	)
	__ASSERT==	MW 0,	4242
	__ASSERT==	M 2.0,	TRUE
	__ASSERT==	MW 10,	2424
	__ASSERT==	M 12.0,	FALSE
	
	
	L	0
	T	MD 0
	T	MD 10
	CALL "FC_not_2" (
		// VAR_INPUT
		IN01		:= 4242,  // INT
		IN02		:= FALSE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN11		:= 2424,  // INT
		IN12		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT00		:= MW 0,  // INT
		OUT01		:= M 2.0,  // BOOL
		OUT10		:= MW 10,  // INT
		OUT11		:= M 12.0,  // BOOL
	)
	__ASSERT==	MW 0,	4242
	__ASSERT==	M 2.0,	FALSE
	__ASSERT==	MW 10,	0
	__ASSERT==	M 12.0,	FALSE
	
	
	L	0
	T	MD 0
	T	MD 10
	CALL "FC_not_2" (
		// VAR_INPUT
		IN01		:= 4242,  // INT
		IN02		:= TRUE,  // BOOL
		IN10		:= FALSE,  // BOOL
		IN11		:= 2424,  // INT
		IN12		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT00		:= MW 0,  // INT
		OUT01		:= M 2.0,  // BOOL
		OUT10		:= MW 10,  // INT
		OUT11		:= M 12.0,  // BOOL
	)
	__ASSERT==	MW 0,	4242
	__ASSERT==	M 2.0,	TRUE
	__ASSERT==	MW 10,	0
	__ASSERT==	M 12.0,	FALSE
	
	
	L	0
	T	MD 0
	T	MD 10
	CALL "FC_not_2" (
		// VAR_INPUT
		IN01		:= 4242,  // INT
		IN02		:= FALSE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN11		:= 2424,  // INT
		IN12		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT00		:= MW 0,  // INT
		OUT01		:= M 2.0,  // BOOL
		OUT10		:= MW 10,  // INT
		OUT11		:= M 12.0,  // BOOL
	)
	__ASSERT==	MW 0,	4242
	__ASSERT==	M 2.0,	FALSE
	__ASSERT==	MW 10,	2424
	__ASSERT==	M 12.0,	TRUE
	
	
	L	0
	T	MD 0
	T	MD 10
	CALL "FC_not_2" (
		// VAR_INPUT
		IN01		:= 4242,  // INT
		IN02		:= TRUE,  // BOOL
		IN10		:= TRUE,  // BOOL
		IN11		:= 2424,  // INT
		IN12		:= TRUE,  // BOOL
		// VAR_OUTPUT
		OUT00		:= MW 0,  // INT
		OUT01		:= M 2.0,  // BOOL
		OUT10		:= MW 10,  // INT
		OUT11		:= M 12.0,  // BOOL
	)
	__ASSERT==	MW 0,	4242
	__ASSERT==	M 2.0,	TRUE
	__ASSERT==	MW 10,	2424
	__ASSERT==	M 12.0,	TRUE
	
	
	BE
END_FUNCTION
]]></source>
	</language_awl>

	<!-- FUP/FBD language configuration -->
	<language_fup>
		<!-- FUP/FBD source code -->
		<source name="assign"
		        type="1"><![CDATA[
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<FUP version="0">
	<blockdecl name='"FC_assign"' type="FC" />
	<interface allow_initvalue="0"
	           allow_inouts="1"
	           allow_inputs="1"
	           allow_outputs="1"
	           allow_retval="1"
	           allow_stats="0"
	           allow_temps="1">
		<inputs>
			<field name="IN0" type="BOOL" />
			<field name="IN1" type="BOOL" />
		</inputs>
		<outputs>
			<field name="OUT0" type="BOOL" />
			<field name="OUT1" type="BOOL" />
			<field name="OUT2" type="BOOL" />
		</outputs>
		<retval>
			<field name="RET_VAL" type="void" />
		</retval>
	</interface>
	<grids>
		<grid height="18" width="12">
			<wires>
				<wire id="0" />
				<wire id="1" />
				<wire id="2" />
			</wires>
			<elements>
				<element subtype="and" type="boolean" x="2" y="2">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="1" />
						<connection dir_in="1" dir_out="0" pos="1" wire="2" />
						<connection dir_in="0" dir_out="1" pos="0" wire="0" />
					</connections>
				</element>
				<element content="#OUT0" subtype="assign" type="operand" x="3" y="3">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="0" />
					</connections>
				</element>
				<element content="#OUT1" subtype="assign" type="operand" x="3" y="4">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="0" />
					</connections>
				</element>
				<element content="#OUT2" subtype="assign" type="operand" x="3" y="5">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="0" />
					</connections>
				</element>
				<element content="#IN0" subtype="load" type="operand" x="1" y="2">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="1" />
					</connections>
				</element>
				<element content="#IN1" subtype="load" type="operand" x="1" y="3">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="2" />
					</connections>
				</element>
			</elements>
		</grid>
	</grids>
</FUP>

]]></source>

		<!-- FUP/FBD source code -->
		<source name="and_and_or"
		        type="1"><![CDATA[
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<FUP version="0">
	<blockdecl name='"FC_and_and_or"' type="FC" />
	<interface allow_initvalue="0"
	           allow_inouts="1"
	           allow_inputs="1"
	           allow_outputs="1"
	           allow_retval="1"
	           allow_stats="0"
	           allow_temps="1">
		<inputs>
			<field name="INP0" type="bool" />
			<field name="INP1" type="bool" />
			<field name="INP2" type="bool" />
			<field name="INP3" type="bool" />
		</inputs>
		<retval>
			<field name="RET_VAL" type="bool" />
		</retval>
	</interface>
	<grids>
		<grid height="32" width="12">
			<wires>
				<wire id="0" />
				<wire id="1" />
				<wire id="2" />
				<wire id="3" />
				<wire id="4" />
				<wire id="5" />
				<wire id="6" />
			</wires>
			<elements>
				<element subtype="and" type="boolean" x="2" y="2">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="0" />
						<connection dir_in="1" dir_out="0" pos="1" wire="1" />
						<connection dir_in="0" dir_out="1" pos="0" wire="5" />
					</connections>
				</element>
				<element content="#INP0" subtype="load" type="operand" x="1" y="2">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="0" />
					</connections>
				</element>
				<element content="#INP1" subtype="load" type="operand" x="1" y="3">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="1" />
					</connections>
				</element>
				<element content="#RET_VAL" subtype="assign" type="operand" x="4" y="5">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="4" />
					</connections>
				</element>
				<element subtype="or" type="boolean" x="3" y="4">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="5" />
						<connection dir_in="1" dir_out="0" pos="1" wire="6" />
						<connection dir_in="0" dir_out="1" pos="0" wire="4" />
					</connections>
				</element>
				<element subtype="and" type="boolean" x="2" y="5">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="2" />
						<connection dir_in="1" dir_out="0" pos="1" wire="3" />
						<connection dir_in="0" dir_out="1" pos="0" wire="6" />
					</connections>
				</element>
				<element content="#INP2" subtype="load" type="operand" x="1" y="5">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="2" />
					</connections>
				</element>
				<element content="#INP3" subtype="load" type="operand" x="1" y="6">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="3" />
					</connections>
				</element>
			</elements>
		</grid>
	</grids>
</FUP>

]]></source>

		<!-- FUP/FBD source code -->
		<source name="branch"
		        type="1"><![CDATA[
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<FUP version="0">
	<blockdecl name='"FC_branch"' type="FC" />
	<interface allow_initvalue="0"
	           allow_inouts="1"
	           allow_inputs="1"
	           allow_outputs="1"
	           allow_retval="1"
	           allow_stats="0"
	           allow_temps="1">
		<inputs>
			<field name="IN00" type="BOOL" />
			<field name="IN01" type="BOOL" />
			<field name="IN10" type="BOOL" />
			<field name="IN20" type="BOOL" />
			<field name="IN30" type="BOOL" />
			<field name="IN40" type="BOOL" />
			<field name="IN50" type="BOOL" />
			<field name="IN60" type="BOOL" />
			<field name="IN61" type="BOOL" />
			<field name="IN70" type="BOOL" />
			<field name="IN80" type="BOOL" />
			<field name="IN81" type="BOOL" />
			<field name="IN90" type="BOOL" />
		</inputs>
		<outputs>
			<field name="OUT10" type="BOOL" />
			<field name="OUT20" type="BOOL" />
			<field name="OUT40" type="BOOL" />
			<field name="OUT50" type="BOOL" />
			<field name="OUT60" type="BOOL" />
			<field name="OUT61" type="BOOL" />
			<field name="OUT70" type="BOOL" />
			<field name="OUT80" type="BOOL" />
			<field name="OUT81" type="BOOL" />
			<field name="OUT90" type="BOOL" />
		</outputs>
		<temps>
			<field name="temp_A" type="BOOL" />
			<field name="temp_B" type="INT" />
		</temps>
		<retval>
			<field name="RET_VAL" type="void" />
		</retval>
	</interface>
	<grids>
		<grid height="33" width="12">
			<wires>
				<wire id="0" />
				<wire id="1" />
				<wire id="2" />
				<wire id="3" />
				<wire id="4" />
				<wire id="5" />
				<wire id="6" />
				<wire id="7" />
				<wire id="8" />
				<wire id="9" />
				<wire id="10" />
				<wire id="11" />
				<wire id="12" />
				<wire id="13" />
				<wire id="14" />
				<wire id="15" />
				<wire id="16" />
				<wire id="17" />
				<wire id="18" />
				<wire id="19" />
				<wire id="20" />
				<wire id="21" />
			</wires>
			<elements>
				<element subtype="xor" type="boolean" x="2" y="1">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="1" />
						<connection dir_in="1" dir_out="0" pos="1" wire="2" />
						<connection dir_in="0" dir_out="1" pos="0" wire="0" />
					</connections>
				</element>
				<element subtype="and" type="boolean" x="4" y="2">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="0" />
						<connection dir_in="1" dir_out="0" pos="1" wire="3" />
						<connection dir_in="0" dir_out="1" pos="0" wire="5" />
					</connections>
				</element>
				<element subtype="and" type="boolean" x="4" y="5">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="0" />
						<connection dir_in="1" dir_out="0" pos="1" wire="4" />
						<connection dir_in="0" dir_out="1" pos="0" wire="6" />
					</connections>
				</element>
				<element content="#IN00" subtype="load" type="operand" x="1" y="1">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="1" />
					</connections>
				</element>
				<element content="#IN01" subtype="load" type="operand" x="1" y="2">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="2" />
					</connections>
				</element>
				<element content="#IN10" subtype="load" type="operand" x="3" y="3">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="3" />
					</connections>
				</element>
				<element content="#IN20" subtype="load" type="operand" x="3" y="6">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="4" />
					</connections>
				</element>
				<element content="#OUT10" subtype="assign" type="operand" x="5" y="3">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="5" />
					</connections>
				</element>
				<element content="#OUT20" subtype="assign" type="operand" x="5" y="6">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="6" />
					</connections>
				</element>
				<element subtype="and" type="boolean" x="4" y="9">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="7" />
						<connection dir_in="1" dir_out="0" pos="1" wire="8" />
						<connection dir_in="0" dir_out="1" pos="0" wire="10" />
					</connections>
				</element>
				<element content="#IN30" subtype="load" type="operand" x="1" y="9">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="7" />
					</connections>
				</element>
				<element subtype="and" type="boolean" x="4" y="12">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="7" />
						<connection dir_in="1" dir_out="0" pos="1" wire="9" />
						<connection dir_in="0" dir_out="1" pos="0" wire="11" />
					</connections>
				</element>
				<element content="#IN40" subtype="load" type="operand" x="3" y="10">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="8" />
					</connections>
				</element>
				<element content="#IN50" subtype="load" type="operand" x="3" y="13">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="9" />
					</connections>
				</element>
				<element content="#OUT40" subtype="assign" type="operand" x="5" y="10">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="10" />
					</connections>
				</element>
				<element content="#OUT50" subtype="assign" type="operand" x="5" y="13">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="11" />
					</connections>
				</element>
				<element content="#OUT60" subtype="assign" type="operand" x="3" y="17">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="12" />
					</connections>
				</element>
				<element content="#IN60" subtype="load" type="operand" x="1" y="16">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="13" />
					</connections>
				</element>
				<element content="#IN61" subtype="load" type="operand" x="1" y="17">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="14" />
					</connections>
				</element>
				<element content="#IN70" subtype="load" type="operand" x="3" y="21">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="15" />
					</connections>
				</element>
				<element content="#OUT70" subtype="assign" type="operand" x="5" y="21">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="16" />
					</connections>
				</element>
				<element content="#IN80" subtype="load" type="operand" x="1" y="23">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="17" />
					</connections>
				</element>
				<element content="#IN81" subtype="load" type="operand" x="1" y="24">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="18" />
					</connections>
				</element>
				<element content="#OUT80" subtype="assign" type="operand" x="3" y="27">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="21" />
					</connections>
				</element>
				<element content="#IN90" subtype="load" type="operand" x="3" y="25">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="19" />
					</connections>
				</element>
				<element content="#OUT90" subtype="assign" type="operand" x="5" y="25">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="20" />
					</connections>
				</element>
				<element content="#OUT61" subtype="assign" type="operand" x="3" y="18">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="12" />
					</connections>
				</element>
				<element content="#OUT81" subtype="assign" type="operand" x="3" y="28">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="21" />
					</connections>
				</element>
				<element subtype="xor" type="boolean" x="2" y="16">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="13" />
						<connection dir_in="1" dir_out="0" pos="1" wire="14" />
						<connection dir_in="0" dir_out="1" pos="0" wire="12" />
					</connections>
				</element>
				<element subtype="xor" type="boolean" x="4" y="20">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="12" />
						<connection dir_in="1" dir_out="0" pos="1" wire="15" />
						<connection dir_in="0" dir_out="1" pos="0" wire="16" />
					</connections>
				</element>
				<element subtype="xor" type="boolean" x="2" y="23">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="17" />
						<connection dir_in="1" dir_out="0" pos="1" wire="18" />
						<connection dir_in="0" dir_out="1" pos="0" wire="21" />
					</connections>
				</element>
				<element subtype="xor" type="boolean" x="4" y="24">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="21" />
						<connection dir_in="1" dir_out="0" pos="1" wire="19" />
						<connection dir_in="0" dir_out="1" pos="0" wire="20" />
					</connections>
				</element>
			</elements>
		</grid>
	</grids>
</FUP>

]]></source>

		<!-- FUP/FBD source code -->
		<source name="not 1"
		        type="1"><![CDATA[
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<FUP version="0">
	<blockdecl name='"FC_not_1"' type="FC" />
	<interface allow_initvalue="0"
	           allow_inouts="1"
	           allow_inputs="1"
	           allow_outputs="1"
	           allow_retval="1"
	           allow_stats="0"
	           allow_temps="1">
		<inputs>
			<field name="IN00" type="BOOL" />
			<field name="IN01" type="BOOL" />
			<field name="IN10" type="BOOL" />
			<field name="IN20" type="BOOL" />
		</inputs>
		<outputs>
			<field name="OUT10" type="BOOL" />
			<field name="OUT20" type="BOOL" />
		</outputs>
		<retval>
			<field name="RET_VAL" type="VOID" />
		</retval>
	</interface>
	<grids>
		<grid height="18" width="12">
			<wires>
				<wire id="0" />
				<wire id="1" />
				<wire id="2" />
				<wire id="3" />
				<wire id="4" />
				<wire id="5" />
				<wire id="6" />
			</wires>
			<elements>
				<element subtype="and" type="boolean" x="2" y="2">
					<connections>
						<connection dir_in="1" dir_out="0" inverted="1" pos="0" wire="1" />
						<connection dir_in="1" dir_out="0" pos="1" wire="5" />
						<connection dir_in="0" dir_out="1" inverted="1" pos="0" wire="0" />
					</connections>
				</element>
				<element subtype="or" type="boolean" x="4" y="2">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="4" />
						<connection dir_in="1" dir_out="0" pos="1" wire="0" />
						<connection dir_in="0" dir_out="1" inverted="1" pos="0" wire="2" />
					</connections>
				</element>
				<element subtype="and" type="boolean" x="5" y="5">
					<connections>
						<connection dir_in="1" dir_out="0" inverted="1" pos="0" wire="2" />
						<connection dir_in="1" dir_out="0" pos="1" wire="6" />
						<connection dir_in="0" dir_out="1" inverted="1" pos="0" wire="3" />
					</connections>
				</element>
				<element content="#IN00" subtype="load" type="operand" x="1" y="2">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="1" />
					</connections>
				</element>
				<element content="#OUT10" subtype="assign" type="operand" x="5" y="3">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="2" />
					</connections>
				</element>
				<element content="#OUT20" subtype="assign" type="operand" x="6" y="6">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="3" />
					</connections>
				</element>
				<element content="#IN10" subtype="load" type="operand" x="3" y="2">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="4" />
					</connections>
				</element>
				<element content="#IN01" subtype="load" type="operand" x="1" y="3">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="5" />
					</connections>
				</element>
				<element content="#IN20" subtype="load" type="operand" x="4" y="6">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="6" />
					</connections>
				</element>
			</elements>
		</grid>
	</grids>
</FUP>

]]></source>

		<!-- FUP/FBD source code -->
		<source name="not 2"
		        type="1"><![CDATA[
<?xml version="1.0" encoding="UTF-8" standalone="yes"?>
<FUP version="0">
	<blockdecl name='"FC_not_2"' type="FC" />
	<interface allow_initvalue="0"
	           allow_inouts="1"
	           allow_inputs="1"
	           allow_outputs="1"
	           allow_retval="1"
	           allow_stats="0"
	           allow_temps="1">
		<inputs>
			<field name="IN01" type="INT" />
			<field name="IN02" type="BOOL" />
			<field name="IN10" type="BOOL" />
			<field name="IN11" type="INT" />
			<field name="IN12" type="BOOL" />
		</inputs>
		<outputs>
			<field name="OUT00" type="INT" />
			<field name="OUT01" type="BOOL" />
			<field name="OUT10" type="INT" />
			<field name="OUT11" type="BOOL" />
		</outputs>
		<retval>
			<field name="RET_VAL" type="VOID" />
		</retval>
	</interface>
	<grids>
		<grid height="18" width="12">
			<wires>
				<wire id="0" />
				<wire id="1" />
				<wire id="2" />
				<wire id="3" />
				<wire id="4" />
				<wire id="5" />
				<wire id="6" />
				<wire id="7" />
				<wire id="8" />
				<wire id="9" />
				<wire id="10" />
			</wires>
			<elements>
				<element type="move" x="2" y="1">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" text="EN" wire="-1" />
						<connection dir_in="1" dir_out="0" pos="1" text="IN" wire="3" />
						<connection dir_in="0" dir_out="1" pos="0" text="OUT0" wire="5" />
						<connection dir_in="0" dir_out="1" pos="1" text="ENO" wire="0" />
					</connections>
				</element>
				<element subtype="xor" type="boolean" x="3" y="3">
					<connections>
						<connection dir_in="1" dir_out="0" inverted="1" pos="0" wire="0" />
						<connection dir_in="1" dir_out="0" pos="1" wire="6" />
						<connection dir_in="0" dir_out="1" pos="0" wire="7" />
					</connections>
				</element>
				<element type="move" x="2" y="6">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" text="EN" wire="2" />
						<connection dir_in="1" dir_out="0" pos="1" text="IN" wire="4" />
						<connection dir_in="0" dir_out="1" pos="0" text="OUT0" wire="9" />
						<connection dir_in="0" dir_out="1" pos="1" text="ENO" wire="1" />
					</connections>
				</element>
				<element subtype="xor" type="boolean" x="3" y="8">
					<connections>
						<connection dir_in="1" dir_out="0" inverted="1" pos="0" wire="1" />
						<connection dir_in="1" dir_out="0" pos="1" wire="8" />
						<connection dir_in="0" dir_out="1" pos="0" wire="10" />
					</connections>
				</element>
				<element content="#IN10" subtype="load" type="operand" x="1" y="7">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="2" />
					</connections>
				</element>
				<element content="#IN01" subtype="load" type="operand" x="1" y="3">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="3" />
					</connections>
				</element>
				<element content="#IN11" subtype="load" type="operand" x="1" y="8">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="4" />
					</connections>
				</element>
				<element content="#OUT00" subtype="assign" type="operand" x="3" y="2">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="5" />
					</connections>
				</element>
				<element content="#IN02" subtype="load" type="operand" x="2" y="4">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="6" />
					</connections>
				</element>
				<element content="#OUT01" subtype="assign" type="operand" x="4" y="4">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="7" />
					</connections>
				</element>
				<element content="#IN12" subtype="load" type="operand" x="2" y="9">
					<connections>
						<connection dir_in="0" dir_out="1" pos="0" wire="8" />
					</connections>
				</element>
				<element content="#OUT10" subtype="assign" type="operand" x="3" y="7">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="9" />
					</connections>
				</element>
				<element content="#OUT11" subtype="assign" type="operand" x="4" y="9">
					<connections>
						<connection dir_in="1" dir_out="0" pos="0" wire="10" />
					</connections>
				</element>
			</elements>
		</grid>
	</grids>
</FUP>

]]></source>
	</language_fup>

	<!-- Symbol table configuration -->
	<symbols>
		<!-- symbol table source code -->
		<source name="symbol table"
		        type="3"><![CDATA[
126,FC_assign               FC 20       FC 20
126,FC_TEST_assign          FC 21       FC 21
126,FC_and_and_or           FC 30       FC 30
126,FC_TEST_and_and_or      FC 31       FC 31
126,FC_branch               FC 40       FC 40
126,FC_TEST_branch          FC 41       FC 41
126,FC_not_1                FC 50       FC 50
126,FC_TEST_not_1           FC 51       FC 51
126,FC_not_2                FC 60       FC 60
126,FC_TEST_not_2           FC 61       FC 61

]]></source>
	</symbols>

	<!-- Core server link configuration -->
	<core_link>
		<!-- Locally spawned core server -->
		<spawn_local enable="1"
		             interpreters="$DEFAULT"
		             port_range_begin="4183"
		             port_range_end="8278" />

		<!-- Remote server connection -->
		<connect host="192.168.179.31"
		         port="4151"
		         timeout_ms="3000" />

		<!-- Transport tunnel -->
		<tunnel local_port="-1"
		        type="0">
			<ssh executable="ssh"
			     port="22"
			     user="pi" />
		</tunnel>
	</core_link>

	<!-- Hardware modules configuration -->
	<hardware>
		<!-- Loaded hardware module -->
		<module name="dummy">
			<params>
				<param name="inputAddressBase"
				       value="0" />
				<param name="outputAddressBase"
				       value="0" />
				<param name="removeOnReset"
				       value="True" />
			</params>
		</module>
	</hardware>

	<!-- Graphical user interface configuration -->
	<gui>
		<editor autoindent="1"
		        font="Courier,11,-1,5,50,0,0,0,0,0"
		        paste_autoindent="1"
		        validation="1" />
	</gui>
</awlsim_project>
