###
### This file was automatically generated
###

from archinfo.arch import register_arch, Endness, Register

from .common import ArchPcode


class ArchPcode_SuperH4_LE_32_default(ArchPcode):
    name = 'SuperH4:LE:32:default'
    pcode_arch = 'SuperH4:LE:32:default'
    description = 'SuperH-4(a) (SH4) little endian'
    bits = 32
    ip_offset = 0x80c
    sp_offset = 0x3c
    bp_offset = sp_offset
    instruction_endness = Endness.LE
    register_list = [
        Register('r0', 4, 0x0),
        Register('r1', 4, 0x4),
        Register('r2', 4, 0x8),
        Register('r3', 4, 0xc),
        Register('r4', 4, 0x10),
        Register('r5', 4, 0x14),
        Register('r6', 4, 0x18),
        Register('r7', 4, 0x1c),
        Register('r8', 4, 0x20),
        Register('r9', 4, 0x24),
        Register('r10', 4, 0x28),
        Register('r11', 4, 0x2c),
        Register('r12', 4, 0x30),
        Register('r13', 4, 0x34),
        Register('r14', 4, 0x38),
        Register('r15', 4, 0x3c),
        Register('r0_bank', 4, 0x40),
        Register('r1_bank', 4, 0x44),
        Register('r2_bank', 4, 0x48),
        Register('r3_bank', 4, 0x4c),
        Register('r4_bank', 4, 0x50),
        Register('r5_bank', 4, 0x54),
        Register('r6_bank', 4, 0x58),
        Register('r7_bank', 4, 0x5c),
        Register('fv0', 16, 0x200),
        Register('dr0', 8, 0x200),
        Register('fr1', 4, 0x200),
        Register('fr0', 4, 0x204),
        Register('dr2', 8, 0x208),
        Register('fr3', 4, 0x208),
        Register('fr2', 4, 0x20c),
        Register('fv4', 16, 0x210),
        Register('dr4', 8, 0x210),
        Register('fr5', 4, 0x210),
        Register('fr4', 4, 0x214),
        Register('dr6', 8, 0x218),
        Register('fr7', 4, 0x218),
        Register('fr6', 4, 0x21c),
        Register('fv8', 16, 0x220),
        Register('dr8', 8, 0x220),
        Register('fr9', 4, 0x220),
        Register('fr8', 4, 0x224),
        Register('dr10', 8, 0x228),
        Register('fr11', 4, 0x228),
        Register('fr10', 4, 0x22c),
        Register('fv12', 16, 0x230),
        Register('dr12', 8, 0x230),
        Register('fr13', 4, 0x230),
        Register('fr12', 4, 0x234),
        Register('dr14', 8, 0x238),
        Register('fr15', 4, 0x238),
        Register('fr14', 4, 0x23c),
        Register('xd0', 8, 0x240),
        Register('xf0', 4, 0x240),
        Register('xf1', 4, 0x244),
        Register('xd2', 8, 0x248),
        Register('xf2', 4, 0x248),
        Register('xf3', 4, 0x24c),
        Register('xd4', 8, 0x250),
        Register('xf4', 4, 0x250),
        Register('xf5', 4, 0x254),
        Register('xd6', 8, 0x258),
        Register('xf6', 4, 0x258),
        Register('xf7', 4, 0x25c),
        Register('xd8', 8, 0x260),
        Register('xf8', 4, 0x260),
        Register('xf9', 4, 0x264),
        Register('xd10', 8, 0x268),
        Register('xf10', 4, 0x268),
        Register('xf11', 4, 0x26c),
        Register('xd12', 8, 0x270),
        Register('xf12', 4, 0x270),
        Register('xf13', 4, 0x274),
        Register('xd14', 8, 0x278),
        Register('xf14', 4, 0x278),
        Register('xf15', 4, 0x27c),
        Register('gbr', 4, 0x400),
        Register('sr', 4, 0x404),
        Register('ssr', 4, 0x408),
        Register('spc', 4, 0x40c),
        Register('vbr', 4, 0x410),
        Register('sgr', 4, 0x414),
        Register('dbr', 4, 0x418),
        Register('md', 1, 0x600),
        Register('rb', 1, 0x601),
        Register('bl', 1, 0x602),
        Register('fd', 1, 0x603),
        Register('m', 1, 0x604),
        Register('q', 1, 0x605),
        Register('imask', 1, 0x606),
        Register('s', 1, 0x607),
        Register('t', 1, 0x608),
        Register('mach', 4, 0x800),
        Register('macl', 4, 0x804),
        Register('pr', 4, 0x808),
        Register('pc', 4, 0x80c, alias_names=('ip',)),
        Register('fpscr', 4, 0x810),
        Register('fpul', 4, 0x814),
        Register('fpscr_rm', 1, 0xa00),
        Register('fpscr_flag', 1, 0xa01),
        Register('fpscr_enable', 1, 0xa02),
        Register('fpscr_cause', 1, 0xa03),
        Register('fpscr_dn', 1, 0xa04),
        Register('fpscr_pr', 1, 0xa05),
        Register('fpscr_sz', 1, 0xa06),
        Register('fpscr_fr', 1, 0xa07)
    ]

register_arch(['superh4:le:32:default'], 32, Endness.LE, ArchPcode_SuperH4_LE_32_default)
